2 * OHCI HCD (Host Controller Driver) for USB.
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
7 * This file is licenced under the GPL.
11 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
12 * __leXX (normally) or __beXX (given OHCI_BIG_ENDIAN), depending on the
13 * host controller implementation.
15 typedef __u32 __bitwise __hc32
;
16 typedef __u16 __bitwise __hc16
;
19 * OHCI Endpoint Descriptor (ED) ... holds TD queue
20 * See OHCI spec, section 4.2
22 * This is a "Queue Head" for those transfers, which is why
23 * both EHCI and UHCI call similar structures a "QH".
26 #define TD_DATALEN_MAX 4096
29 #define ED_MASK ((u32)~(ED_ALIGN-1)) /* strip hw status in low addr bits */
32 /* first fields are hardware-specified */
33 __hc32 hwINFO
; /* endpoint config bitmap */
34 /* info bits defined by hcd */
35 #define ED_DEQUEUE (1 << 27)
36 /* info bits defined by the hardware */
37 #define ED_MPS_SHIFT 16
38 #define ED_MPS_MASK ((1 << 11)-1)
39 #define ED_MPS_GET(x) (((x) >> ED_MPS_SHIFT) & ED_MPS_MASK)
40 #define ED_ISO (1 << 15) /* isochronous endpoint */
41 #define ED_SKIP (1 << 14)
42 #define ED_SPEED_FULL (1 << 13) /* fullspeed device */
43 #define ED_INT (1 << 11) /* interrupt endpoint */
44 #define ED_EN_SHIFT 7 /* endpoint shift */
45 #define ED_EN_MASK ((1 << 4)-1) /* endpoint mask */
46 #define ED_EN_GET(x) (((x) >> ED_EN_SHIFT) & ED_EN_MASK)
47 #define ED_FA_MASK ((1 << 7)-1) /* function address mask */
48 #define ED_FA_GET(x) ((x) & ED_FA_MASK)
49 __hc32 hwTailP
; /* tail of TD list */
50 __hc32 hwHeadP
; /* head of TD list (hc r/w) */
51 #define ED_C (0x02) /* toggle carry */
52 #define ED_H (0x01) /* halted */
53 __hc32 hwNextED
; /* next ED in list */
55 /* rest are purely for the driver's use */
56 dma_addr_t dma
; /* addr of ED */
57 struct td
*dummy
; /* next TD to activate */
59 struct list_head urb_list
; /* list of our URBs */
61 struct list_head ed_list
; /* list of all EDs*/
62 struct list_head rm_list
; /* for remove list */
64 /* host's view of schedule */
65 struct ed
*ed_next
; /* on schedule list */
66 struct ed
*ed_prev
; /* for non-interrupt EDs */
67 struct ed
*ed_rm_next
; /* on rm list */
68 struct ed
*ed_soft_list
; /* on software int list */
69 struct list_head td_list
; /* "shadow list" of our TDs */
71 /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
72 * usually: OPER --> UNLINK --> (IDLE | OPER) --> ...
74 u8 state
; /* ED_{IDLE,UNLINK,OPER} */
75 #define ED_IDLE 0x00 /* NOT linked to HC */
76 #define ED_UNLINK 0x01 /* being unlinked from hc */
77 #define ED_OPER 0x02 /* IS linked to hc */
79 u8 type
; /* PIPE_{BULK,...} */
81 /* periodic scheduling params (for intr and iso) */
85 u16 last_iso
; /* iso only */
87 /* HC may see EDs on rm_list until next frame (frame_no == tick) */
89 } __attribute__ ((aligned(ED_ALIGN
)));
92 * OHCI Transfer Descriptor (TD) ... one per transfer segment
93 * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt)
98 #define TD_MASK ((u32)~(TD_ALIGN-1)) /* strip hw status in low addr bits */
101 /* first fields are hardware-specified */
102 __hc32 hwINFO
; /* transfer info bitmask */
105 #define TD_OWN (1 << 31) /* owner of the descriptor */
106 #define TD_CC_SHIFT 27 /* condition code */
107 #define TD_CC_MASK 0xf
108 #define TD_CC (TD_CC_MASK << TD_CC_SHIFT)
109 #define TD_CC_GET(x) (((x) >> TD_CC_SHIFT) & TD_CC_MASK)
111 #define TD_EC_SHIFT 25 /* error count */
112 #define TD_EC_MASK 0x3
113 #define TD_EC (TD_EC_MASK << TD_EC_SHIFT)
114 #define TD_EC_GET(x) ((x >> TD_EC_SHIFT) & TD_EC_MASK)
115 #define TD_T_SHIFT 23 /* data toggle state */
116 #define TD_T_MASK 0x3
117 #define TD_T (TD_T_MASK << TD_T_SHIFT)
118 #define TD_T_DATA0 (0x2 << TD_T_SHIFT) /* DATA0 */
119 #define TD_T_DATA1 (0x3 << TD_T_SHIFT) /* DATA1 */
120 #define TD_T_CARRY (0x0 << TD_T_SHIFT) /* uses ED_C */
121 #define TD_T_GET(x) (((x) >> TD_T_SHIFT) & TD_T_MASK)
122 #define TD_DP_SHIFT 21 /* direction/pid */
123 #define TD_DP_MASK 0x3
124 #define TD_DP (TD_DP_MASK << TD_DP_SHIFT)
125 #define TD_DP_SETUP (0x0 << TD_DP_SHIFT) /* SETUP pid */
126 #define TD_DP_OUT (0x1 << TD_DP_SHIFT) /* OUT pid */
127 #define TD_DP_IN (0x2 << TD_DP_SHIFT) /* IN pid */
128 #define TD_ISI_SHIFT 8 /* Interrupt Service Interval */
129 #define TD_ISI_MASK 0x3f
130 #define TD_ISI_GET(x) (((x) >> TD_ISI_SHIFT) & TD_ISI_MASK)
131 #define TD_FN_MASK 0x3f /* frame number */
132 #define TD_FN_GET(x) ((x) & TD_FN_MASK)
134 __hc32 hwDBP
; /* Data Buffer Pointer (or 0) */
135 __hc32 hwCBL
; /* Controller/Buffer Length */
138 #define TD_BL_MASK 0xffff /* buffer length */
139 #define TD_BL_GET(x) ((x) & TD_BL_MASK)
140 #define TD_IE (1 << 16) /* interrupt enable */
141 __hc32 hwNextTD
; /* Next TD Pointer */
143 /* rest are purely for the driver's use */
146 struct td
*td_hash
; /* dma-->td hashtable */
147 struct td
*next_dl_td
;
150 dma_addr_t td_dma
; /* addr of this TD */
151 dma_addr_t data_dma
; /* addr of data it points to */
153 struct list_head td_list
; /* "shadow list", TDs on same ED */
156 #define TD_FLAG_DONE (1 << 17) /* retired to done list */
157 #define TD_FLAG_ISO (1 << 16) /* copy of ED_ISO */
158 } __attribute__ ((aligned(TD_ALIGN
))); /* c/b/i need 16; only iso needs 32 */
161 * Hardware transfer status codes -- CC from td->hwINFO
163 #define TD_CC_NOERROR 0x00
164 #define TD_CC_CRC 0x01
165 #define TD_CC_BITSTUFFING 0x02
166 #define TD_CC_DATATOGGLEM 0x03
167 #define TD_CC_STALL 0x04
168 #define TD_CC_DEVNOTRESP 0x05
169 #define TD_CC_PIDCHECKFAIL 0x06
170 #define TD_CC_UNEXPECTEDPID 0x07
171 #define TD_CC_DATAOVERRUN 0x08
172 #define TD_CC_DATAUNDERRUN 0x09
173 /* 0x0A, 0x0B reserved for hardware */
174 #define TD_CC_BUFFEROVERRUN 0x0C
175 #define TD_CC_BUFFERUNDERRUN 0x0D
176 /* 0x0E, 0x0F reserved for HCD */
177 #define TD_CC_HCD0 0x0E
178 #define TD_CC_NOTACCESSED 0x0F
181 * preshifted status codes
183 #define TD_SCC_NOTACCESSED (TD_CC_NOTACCESSED << TD_CC_SHIFT)
186 /* map OHCI TD status codes (CC) to errno values */
187 static const int cc_to_error
[16] = {
189 /* CRC Error */ -EILSEQ
,
190 /* Bit Stuff */ -EPROTO
,
191 /* Data Togg */ -EILSEQ
,
193 /* DevNotResp */ -ETIME
,
194 /* PIDCheck */ -EPROTO
,
195 /* UnExpPID */ -EPROTO
,
196 /* DataOver */ -EOVERFLOW
,
197 /* DataUnder */ -EREMOTEIO
,
200 /* BufferOver */ -ECOMM
,
201 /* BuffUnder */ -ENOSR
,
202 /* (for HCD) */ -EALREADY
,
203 /* (for HCD) */ -EALREADY
209 * This is the structure of the OHCI controller's memory mapped I/O region.
210 * You must use readl() and writel() (in <asm/io.h>) to access these fields!!
211 * Layout is in section 7 (and appendix B) of the spec.
214 __hc32 gencontrol
; /* General Control */
215 __hc32 int_status
; /* Interrupt Status */
216 __hc32 int_enable
; /* Interrupt Enable */
218 __hc32 host_control
; /* Host General Control */
220 __hc32 fminterval
; /* Frame Interval */
221 __hc32 fmnumber
; /* Frame Number */
242 __hc32 lsthresh
; /* Low Speed Threshold */
243 __hc32 rhdesc
; /* Root Hub Descriptor */
244 #define MAX_ROOT_PORTS 2
245 __hc32 portstatus
[MAX_ROOT_PORTS
]; /* Port Status */
246 __hc32 hosthead
; /* Host Descriptor Head */
247 } __attribute__ ((aligned(32)));
250 * General Control register bits
252 #define ADMHC_CTRL_UHFE (1 << 0) /* USB Host Function Enable */
253 #define ADMHC_CTRL_SIR (1 << 1) /* Software Interrupt request */
254 #define ADMHC_CTRL_DMAA (1 << 2) /* DMA Arbitration Control */
255 #define ADMHC_CTRL_SR (1 << 3) /* Software Reset */
258 * Host General Control register bits
260 #define ADMHC_HC_BUSS 0x3 /* USB bus state */
261 #define ADMHC_BUSS_RESET 0x0
262 #define ADMHC_BUSS_RESUME 0x1
263 #define ADMHC_BUSS_OPER 0x2
264 #define ADMHC_BUSS_SUSPEND 0x3
265 #define ADMHC_HC_DMAE (1 << 2) /* DMA enable */
268 * Interrupt Status/Enable register bits
270 #define ADMHC_INTR_SOFI (1 << 4) /* start of frame */
271 #define ADMHC_INTR_RESI (1 << 5) /* resume detected */
272 #define ADMHC_INTR_BABI (1 << 8) /* babble detected */
273 #define ADMHC_INTR_INSM (1 << 9) /* root hub status change */
274 #define ADMHC_INTR_SO (1 << 10) /* scheduling overrun */
275 #define ADMHC_INTR_FNO (1 << 11) /* frame number overflow */
276 #define ADMHC_INTR_TDC (1 << 20) /* transfer descriptor completed */
277 #define ADMHC_INTR_SWI (1 << 29) /* software interrupt */
278 #define ADMHC_INTR_FATI (1 << 30) /* fatal error */
279 #define ADMHC_INTR_INTA (1 << 31) /* interrupt active */
281 #define ADMHC_INTR_MIE (1 << 31) /* master interrupt enable */
284 * SOF Frame Interval register bits
286 #define ADMHC_SFI_FI_MASK ((1 << 14)-1) /* Frame Interval value */
287 #define ADMHC_SFI_FSLDP_SHIFT 16
288 #define ADMHC_SFI_FSLDP_MASK ((1 << 15)-1)
289 #define ADMHC_SFI_FIT (1 << 31) /* Frame Interval Toggle */
292 * SOF Frame Number register bits
294 #define ADMHC_SFN_FN_MASK ((1 << 16)-1) /* Frame Number Mask */
295 #define ADMHC_SFN_FR_SHIFT 16 /* Frame Remaining Shift */
296 #define ADMHC_SFN_FR_MASK ((1 << 14)-1) /* Frame Remaining Mask */
297 #define ADMHC_SFN_FRT (1 << 31) /* Frame Remaining Toggle */
300 * Root Hub Descriptor register bits
302 #define ADMHC_RH_NUMP 0xff /* number of ports */
303 #define ADMHC_RH_PSM (1 << 8) /* power switching mode */
304 #define ADMHC_RH_NPS (1 << 9) /* no power switching */
305 #define ADMHC_RH_OCPM (1 << 10) /* over current protection mode */
306 #define ADMHC_RH_NOCP (1 << 11) /* no over current protection */
307 #define ADMHC_RH_PPCM (0xff << 16) /* port power control */
309 #define ADMHC_RH_LPS (1 << 24) /* local power switch */
310 #define ADMHC_RH_OCI (1 << 25) /* over current indicator */
312 /* status change bits */
313 #define ADMHC_RH_LPSC (1 << 26) /* local power switch change */
314 #define ADMHC_RH_OCIC (1 << 27) /* over current indicator change */
316 #define ADMHC_RH_DRWE (1 << 28) /* device remote wakeup enable */
317 #define ADMHC_RH_CRWE (1 << 29) /* clear remote wakeup enable */
319 #define ADMHC_RH_CGP (1 << 24) /* clear global power */
320 #define ADMHC_RH_SGP (1 << 26) /* set global power */
323 * Port Status register bits
325 #define ADMHC_PS_CCS (1 << 0) /* current connect status */
326 #define ADMHC_PS_PES (1 << 1) /* port enable status */
327 #define ADMHC_PS_PSS (1 << 2) /* port suspend status */
328 #define ADMHC_PS_POCI (1 << 3) /* port over current indicator */
329 #define ADMHC_PS_PRS (1 << 4) /* port reset status */
330 #define ADMHC_PS_PPS (1 << 8) /* port power status */
331 #define ADMHC_PS_LSDA (1 << 9) /* low speed device attached */
333 /* status change bits */
334 #define ADMHC_PS_CSC (1 << 16) /* connect status change */
335 #define ADMHC_PS_PESC (1 << 17) /* port enable status change */
336 #define ADMHC_PS_PSSC (1 << 18) /* port suspend status change */
337 #define ADMHC_PS_OCIC (1 << 19) /* over current indicator change */
338 #define ADMHC_PS_PRSC (1 << 20) /* port reset status change */
340 /* port feature bits */
341 #define ADMHC_PS_CPE (1 << 0) /* clear port enable */
342 #define ADMHC_PS_SPE (1 << 1) /* set port enable */
343 #define ADMHC_PS_SPS (1 << 2) /* set port suspend */
344 #define ADMHC_PS_CPS (1 << 3) /* clear suspend status */
345 #define ADMHC_PS_SPR (1 << 4) /* set port reset */
346 #define ADMHC_PS_SPP (1 << 8) /* set port power */
347 #define ADMHC_PS_CPP (1 << 9) /* clear port power */
350 * the POTPGT value is not defined in the ADMHC, so define a dummy value
352 #define ADMHC_POTPGT 2 /* in ms */
354 /* hcd-private per-urb state */
357 struct list_head pending
; /* URBs on the same ED */
359 u32 td_cnt
; /* # tds in this request */
360 u32 td_idx
; /* index of the current td */
361 struct td
*td
[0]; /* all TDs in this request */
364 #define TD_HASH_SIZE 64 /* power'o'two */
365 /* sizeof (struct td) ~= 64 == 2^6 ... */
366 #define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE)
369 * This is the full ADMHCD controller description
371 * Note how the "proper" USB information is just
372 * a subset of what the full implementation needs. (Linus)
379 * I/O memory used to communicate with the HC (dma-consistent)
381 struct admhcd_regs __iomem
*regs
;
384 * hcd adds to schedule for a live hc any time, but removals finish
385 * only at the start of the next frame.
389 struct ed
*ed_tails
[4];
391 struct ed
*ed_rm_list
; /* to be removed */
392 struct ed
*ed_halt_list
; /* halted due to an error */
393 struct ed
*ed_soft_list
; /* for software interrupt processing */
395 struct ed
*periodic
[NUM_INTS
]; /* shadow int_table */
397 #if 0 /* TODO: remove? */
399 * OTG controllers and transceivers need software interaction;
400 * other external transceivers should be software-transparent
402 struct otg_transceiver
*transceiver
;
406 * memory management for queue data structures
408 struct dma_pool
*td_cache
;
409 struct dma_pool
*ed_cache
;
410 struct td
*td_hash
[TD_HASH_SIZE
];
411 struct list_head pending
;
418 u32 host_control
; /* copy of the host_control reg */
419 unsigned long next_statechange
; /* suspend/resume */
420 u32 fminterval
; /* saved register */
421 unsigned autostop
:1; /* rh auto stopping/stopped */
423 unsigned long flags
; /* for HC bugs */
424 #define OHCI_QUIRK_AMD756 0x01 /* erratum #4 */
425 #define OHCI_QUIRK_SUPERIO 0x02 /* natsemi */
426 #define OHCI_QUIRK_INITRESET 0x04 /* SiS, OPTi, ... */
427 #define OHCI_QUIRK_BE_DESC 0x08 /* BE descriptors */
428 #define OHCI_QUIRK_BE_MMIO 0x10 /* BE registers */
429 #define OHCI_QUIRK_ZFMICRO 0x20 /* Compaq ZFMicro chipset*/
430 // there are also chip quirks/bugs in init logic
433 /* convert between an hcd pointer and the corresponding ahcd_hcd */
434 static inline struct admhcd
*hcd_to_admhcd(struct usb_hcd
*hcd
)
436 return (struct admhcd
*)(hcd
->hcd_priv
);
438 static inline struct usb_hcd
*admhcd_to_hcd(const struct admhcd
*ahcd
)
440 return container_of((void *)ahcd
, struct usb_hcd
, hcd_priv
);
443 /*-------------------------------------------------------------------------*/
446 #define STUB_DEBUG_FILES
449 #define admhc_dbg(ahcd, fmt, args...) \
450 dev_dbg(admhcd_to_hcd(ahcd)->self.controller , fmt , ## args )
451 #define admhc_err(ahcd, fmt, args...) \
452 dev_err(admhcd_to_hcd(ahcd)->self.controller , fmt , ## args )
453 #define ahcd_info(ahcd, fmt, args...) \
454 dev_info(admhcd_to_hcd(ahcd)->self.controller , fmt , ## args )
455 #define admhc_warn(ahcd, fmt, args...) \
456 dev_warn(admhcd_to_hcd(ahcd)->self.controller , fmt , ## args )
458 #ifdef ADMHC_VERBOSE_DEBUG
459 # define admhc_vdbg admhc_dbg
461 # define admhc_vdbg(ahcd, fmt, args...) do { } while (0)
464 /*-------------------------------------------------------------------------*/
467 * While most USB host controllers implement their registers and
468 * in-memory communication descriptors in little-endian format,
469 * a minority (notably the IBM STB04XXX and the Motorola MPC5200
470 * processors) implement them in big endian format.
472 * In addition some more exotic implementations like the Toshiba
473 * Spider (aka SCC) cell southbridge are "mixed" endian, that is,
474 * they have a different endianness for registers vs. in-memory
477 * This attempts to support either format at compile time without a
478 * runtime penalty, or both formats with the additional overhead
479 * of checking a flag bit.
481 * That leads to some tricky Kconfig rules howevber. There are
482 * different defaults based on some arch/ppc platforms, though
483 * the basic rules are:
485 * Controller type Kconfig options needed
486 * --------------- ----------------------
487 * little endian CONFIG_USB_ADMHC_LITTLE_ENDIAN
489 * fully big endian CONFIG_USB_ADMHC_BIG_ENDIAN_DESC _and_
490 * CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
492 * mixed endian CONFIG_USB_ADMHC_LITTLE_ENDIAN _and_
493 * CONFIG_USB_OHCI_BIG_ENDIAN_{MMIO,DESC}
495 * (If you have a mixed endian controller, you -must- also define
496 * CONFIG_USB_ADMHC_LITTLE_ENDIAN or things will not work when building
497 * both your mixed endian and a fully big endian controller support in
498 * the same kernel image).
501 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_DESC
502 #ifdef CONFIG_USB_ADMHC_LITTLE_ENDIAN
503 #define big_endian_desc(ahcd) (ahcd->flags & OHCI_QUIRK_BE_DESC)
505 #define big_endian_desc(ahcd) 1 /* only big endian */
508 #define big_endian_desc(ahcd) 0 /* only little endian */
511 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
512 #ifdef CONFIG_USB_ADMHC_LITTLE_ENDIAN
513 #define big_endian_mmio(ahcd) (ahcd->flags & OHCI_QUIRK_BE_MMIO)
515 #define big_endian_mmio(ahcd) 1 /* only big endian */
518 #define big_endian_mmio(ahcd) 0 /* only little endian */
522 * Big-endian read/write functions are arch-specific.
523 * Other arches can be added if/when they're needed.
525 * REVISIT: arch/powerpc now has readl/writel_be, so the
526 * definition below can die once the STB04xxx support is
527 * finally ported over.
529 #if defined(CONFIG_PPC) && !defined(CONFIG_PPC_MERGE)
530 #define readl_be(addr) in_be32((__force unsigned *)addr)
531 #define writel_be(val, addr) out_be32((__force unsigned *)addr, val)
534 static inline unsigned int admhc_readl(const struct admhcd
*ahcd
,
535 __hc32 __iomem
*regs
)
537 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
538 return big_endian_mmio(ahcd
) ?
546 static inline void admhc_writel(const struct admhcd
*ahcd
,
547 const unsigned int val
, __hc32 __iomem
*regs
)
549 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
550 big_endian_mmio(ahcd
) ?
551 writel_be(val
, regs
) :
558 static inline void admhc_writel_flush(const struct admhcd
*ahcd
)
560 #if 0 /* TODO: needed? */
561 (void) admhc_readl(ahcd
, &ahcd
->regs
->control
);
566 /*-------------------------------------------------------------------------*/
569 static inline __hc16
cpu_to_hc16(const struct admhcd
*ahcd
, const u16 x
)
571 return big_endian_desc(ahcd
) ?
572 (__force __hc16
)cpu_to_be16(x
) :
573 (__force __hc16
)cpu_to_le16(x
);
576 static inline __hc16
cpu_to_hc16p(const struct admhcd
*ahcd
, const u16
*x
)
578 return big_endian_desc(ahcd
) ?
583 static inline __hc32
cpu_to_hc32(const struct admhcd
*ahcd
, const u32 x
)
585 return big_endian_desc(ahcd
) ?
586 (__force __hc32
)cpu_to_be32(x
) :
587 (__force __hc32
)cpu_to_le32(x
);
590 static inline __hc32
cpu_to_hc32p(const struct admhcd
*ahcd
, const u32
*x
)
592 return big_endian_desc(ahcd
) ?
598 static inline u16
hc16_to_cpu(const struct admhcd
*ahcd
, const __hc16 x
)
600 return big_endian_desc(ahcd
) ?
601 be16_to_cpu((__force __be16
)x
) :
602 le16_to_cpu((__force __le16
)x
);
605 static inline u16
hc16_to_cpup(const struct admhcd
*ahcd
, const __hc16
*x
)
607 return big_endian_desc(ahcd
) ?
608 be16_to_cpup((__force __be16
*)x
) :
609 le16_to_cpup((__force __le16
*)x
);
612 static inline u32
hc32_to_cpu(const struct admhcd
*ahcd
, const __hc32 x
)
614 return big_endian_desc(ahcd
) ?
615 be32_to_cpu((__force __be32
)x
) :
616 le32_to_cpu((__force __le32
)x
);
619 static inline u32
hc32_to_cpup(const struct admhcd
*ahcd
, const __hc32
*x
)
621 return big_endian_desc(ahcd
) ?
622 be32_to_cpup((__force __be32
*)x
) :
623 le32_to_cpup((__force __le32
*)x
);
626 /*-------------------------------------------------------------------------*/
628 static inline u16
admhc_frame_no(const struct admhcd
*ahcd
)
632 t
= admhc_readl(ahcd
, &ahcd
->regs
->fmnumber
) & ADMHC_SFN_FN_MASK
;
636 /*-------------------------------------------------------------------------*/
638 static inline void admhc_disable(struct admhcd
*ahcd
)
640 admhcd_to_hcd(ahcd
)->state
= HC_STATE_HALT
;
643 #define FI 0x2edf /* 12000 bits per frame (-1) */
644 #define FSLDP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
645 #define FIT ADMHC_SFI_FIT
646 #define LSTHRESH 0x628 /* lowspeed bit threshold */
648 static inline void periodic_reinit(struct admhcd
*ahcd
)
650 u32 fi
= ahcd
->fminterval
& ADMHC_SFI_FI_MASK
;
651 u32 fit
= admhc_readl(ahcd
, &ahcd
->regs
->fminterval
) & FIT
;
653 /* TODO: adjust FSLargestDataPacket value too? */
654 admhc_writel(ahcd
, (fit
^ FIT
) | ahcd
->fminterval
,
655 &ahcd
->regs
->fminterval
);
658 static inline u32
admhc_get_rhdesc(struct admhcd
*ahcd
)
660 return admhc_readl(ahcd
, &ahcd
->regs
->rhdesc
);
663 static inline u32
admhc_get_portstatus(struct admhcd
*ahcd
, int port
)
665 return admhc_readl(ahcd
, &ahcd
->regs
->portstatus
[port
]);
668 static inline void roothub_write_status(struct admhcd
*ahcd
, u32 value
)
670 /* FIXME: read-only bits must be masked out */
671 admhc_writel(ahcd
, value
, &ahcd
->regs
->rhdesc
);
674 static inline void admhc_intr_disable(struct admhcd
*ahcd
, u32 ints
)
678 t
= admhc_readl(ahcd
, &ahcd
->regs
->int_enable
);
680 admhc_writel(ahcd
, t
, &ahcd
->regs
->int_enable
);
681 /* TODO: flush writes ?*/
684 static inline void admhc_intr_enable(struct admhcd
*ahcd
, u32 ints
)
688 t
= admhc_readl(ahcd
, &ahcd
->regs
->int_enable
);
690 admhc_writel(ahcd
, t
, &ahcd
->regs
->int_enable
);
691 /* TODO: flush writes ?*/
694 static inline void admhc_intr_ack(struct admhcd
*ahcd
, u32 ints
)
696 admhc_writel(ahcd
, ints
, &ahcd
->regs
->int_status
);
699 static inline void admhc_dma_enable(struct admhcd
*ahcd
)
701 ahcd
->host_control
= admhc_readl(ahcd
, &ahcd
->regs
->host_control
);
702 if (ahcd
->host_control
& ADMHC_HC_DMAE
)
705 ahcd
->host_control
|= ADMHC_HC_DMAE
;
706 admhc_writel(ahcd
, ahcd
->host_control
, &ahcd
->regs
->host_control
);
709 static inline void admhc_dma_disable(struct admhcd
*ahcd
)
711 ahcd
->host_control
= admhc_readl(ahcd
, &ahcd
->regs
->host_control
);
712 ahcd
->host_control
&= ~ADMHC_HC_DMAE
;
713 admhc_writel(ahcd
, ahcd
->host_control
, &ahcd
->regs
->host_control
);
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