target/linux/brcm47xx/patches-2.6.30/130-remove_scache.patch

   1 --- a/arch/mips/Kconfig
   2 +++ b/arch/mips/Kconfig
   3 @@ -195,7 +195,6 @@ config MIPS_MALTA
   4         select I8259
   5         select MIPS_BOARDS_GEN
   6         select MIPS_BONITO64
   7 -       select MIPS_CPU_SCACHE
   8         select PCI_GT64XXX_PCI0
   9         select MIPS_MSC
  10         select SWAP_IO_SPACE
  11 @@ -1473,13 +1472,6 @@ config IP22_CPU_SCACHE
  12         bool
  13         select BOARD_SCACHE
  14
  15 -#
  16 -# Support for a MIPS32 / MIPS64 style S-caches
  17 -#
  18 -config MIPS_CPU_SCACHE
  19 -       bool
  20 -       select BOARD_SCACHE
  21 -
  22  config R5000_CPU_SCACHE
  23         bool
  24         select BOARD_SCACHE
  25 --- a/arch/mips/kernel/cpu-probe.c
  26 +++ b/arch/mips/kernel/cpu-probe.c
  27 @@ -753,6 +753,8 @@ static inline void cpu_probe_mips(struct
  28         case PRID_IMP_25KF:
  29                 c->cputype = CPU_25KF;
  30                 __cpu_name[cpu] = "MIPS 25Kc";
  31 +               /* Probe for L2 cache */
  32 +               c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
  33                 break;
  34         case PRID_IMP_34K:
  35                 c->cputype = CPU_34K;
  36 --- a/arch/mips/mm/Makefile
  37 +++ b/arch/mips/mm/Makefile
  38 @@ -32,6 +32,5 @@ obj-$(CONFIG_CPU_CAVIUM_OCTEON)       += c-oct
  39  obj-$(CONFIG_IP22_CPU_SCACHE)  += sc-ip22.o
  40  obj-$(CONFIG_R5000_CPU_SCACHE)  += sc-r5k.o
  41  obj-$(CONFIG_RM7000_CPU_SCACHE)        += sc-rm7k.o
  42 -obj-$(CONFIG_MIPS_CPU_SCACHE)  += sc-mips.o
  43
  44  EXTRA_CFLAGS += -Werror
  45 --- a/arch/mips/mm/c-r4k.c
  46 +++ b/arch/mips/mm/c-r4k.c
  47 @@ -1135,7 +1135,6 @@ static void __init loongson2_sc_init(voi
  48
  49  extern int r5k_sc_init(void);
  50  extern int rm7k_sc_init(void);
  51 -extern int mips_sc_init(void);
  52
  53  static void __cpuinit setup_scache(void)
  54  {
  55 @@ -1189,29 +1188,17 @@ static void __cpuinit setup_scache(void)
  56  #endif
  57
  58         default:
  59 -               if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
  60 -                   c->isa_level == MIPS_CPU_ISA_M32R2 ||
  61 -                   c->isa_level == MIPS_CPU_ISA_M64R1 ||
  62 -                   c->isa_level == MIPS_CPU_ISA_M64R2) {
  63 -#ifdef CONFIG_MIPS_CPU_SCACHE
  64 -                       if (mips_sc_init ()) {
  65 -                               scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
  66 -                               printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
  67 -                                      scache_size >> 10,
  68 -                                      way_string[c->scache.ways], c->scache.linesz);
  69 -                       }
  70 -#else
  71 -                       if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
  72 -                               panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
  73 -#endif
  74 -                       return;
  75 -               }
  76                 sc_present = 0;
  77         }
  78
  79         if (!sc_present)
  80                 return;
  81
  82 +       if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
  83 +            c->isa_level == MIPS_CPU_ISA_M64R1) &&
  84 +           !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
  85 +               panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
  86 +
  87         /* compute a couple of other cache variables */
  88         c->scache.waysize = scache_size / c->scache.ways;
  89