2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4720/JZ4740 SoC RTC driver
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/spinlock.h>
20 #include <linux/rtc.h>
22 #define JZ_REG_RTC_CTRL 0x00
23 #define JZ_REG_RTC_SEC 0x04
24 #define JZ_REG_RTC_SEC_ALARM 0x08
25 #define JZ_REG_RTC_REGULATOR 0x0C
26 #define JZ_REG_RTC_SCRATCHPAD 0x34
28 #define JZ_RTC_CTRL_WRDY BIT(7)
29 #define JZ_RTC_CTRL_1HZ BIT(6)
30 #define JZ_RTC_CTRL_1HZ_IRQ BIT(5)
31 #define JZ_RTC_CTRL_AF BIT(4)
32 #define JZ_RTC_CTRL_AF_IRQ BIT(3)
33 #define JZ_RTC_CTRL_AE BIT(2)
34 #define JZ_RTC_CTRL_ENABLE BIT(0)
40 struct rtc_device
*rtc
;
47 static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc
*rtc
, size_t reg
)
49 return readl(rtc
->base
+ reg
);
52 static inline void jz4740_rtc_wait_write_ready(struct jz4740_rtc
*rtc
)
56 ctrl
= jz4740_rtc_reg_read(rtc
, JZ_REG_RTC_CTRL
);
57 } while (!(ctrl
& JZ_RTC_CTRL_WRDY
));
61 static inline void jz4740_rtc_reg_write(struct jz4740_rtc
*rtc
, size_t reg
,
64 jz4740_rtc_wait_write_ready(rtc
);
65 writel(val
, rtc
->base
+ reg
);
68 static void jz4740_rtc_ctrl_set_bits(struct jz4740_rtc
*rtc
, uint32_t mask
,
74 spin_lock_irqsave(&rtc
->lock
, flags
);
76 ctrl
= jz4740_rtc_reg_read(rtc
, JZ_REG_RTC_CTRL
);
78 /* Don't clear interrupt flags by accident */
79 ctrl
|= JZ_RTC_CTRL_1HZ
| JZ_RTC_CTRL_AF
;
84 jz4740_rtc_reg_write(rtc
, JZ_REG_RTC_CTRL
, ctrl
);
86 spin_unlock_irqrestore(&rtc
->lock
, flags
);
89 static inline struct jz4740_rtc
*dev_to_rtc(struct device
*dev
)
91 return dev_get_drvdata(dev
);
94 static int jz4740_rtc_read_time(struct device
*dev
, struct rtc_time
*time
)
96 struct jz4740_rtc
*rtc
= dev_to_rtc(dev
);
99 secs
= jz4740_rtc_reg_read(rtc
, JZ_REG_RTC_SEC
);
100 secs2
= jz4740_rtc_reg_read(rtc
, JZ_REG_RTC_SEC
);
102 while (secs
!= secs2
) {
104 secs2
= jz4740_rtc_reg_read(rtc
, JZ_REG_RTC_SEC
);
107 rtc_time_to_tm(secs
, time
);
109 return rtc_valid_tm(time
);
112 static int jz4740_rtc_set_mmss(struct device
*dev
, unsigned long secs
)
114 struct jz4740_rtc
*rtc
= dev_to_rtc(dev
);
116 if ((uint32_t)secs
!= secs
)
119 jz4740_rtc_reg_write(rtc
, JZ_REG_RTC_SEC
, secs
);
124 static int jz4740_rtc_read_alarm(struct device
*dev
, struct rtc_wkalrm
*alrm
)
126 struct jz4740_rtc
*rtc
= dev_to_rtc(dev
);
127 uint32_t secs
, secs2
;
130 secs
= jz4740_rtc_reg_read(rtc
, JZ_REG_RTC_SEC_ALARM
);
131 secs2
= jz4740_rtc_reg_read(rtc
, JZ_REG_RTC_SEC_ALARM
);
133 while (secs
!= secs2
){
135 secs2
= jz4740_rtc_reg_read(rtc
, JZ_REG_RTC_SEC_ALARM
);
138 ctrl
= jz4740_rtc_reg_read(rtc
, JZ_REG_RTC_CTRL
);
140 alrm
->enabled
= !!(ctrl
& JZ_RTC_CTRL_AE
);
141 alrm
->pending
= !!(ctrl
& JZ_RTC_CTRL_AF
);
143 rtc_time_to_tm(secs
, &alrm
->time
);
145 return rtc_valid_tm(&alrm
->time
);
148 static int jz4740_rtc_set_alarm(struct device
*dev
, struct rtc_wkalrm
*alrm
)
150 struct jz4740_rtc
*rtc
= dev_to_rtc(dev
);
153 rtc_tm_to_time(&alrm
->time
, &secs
);
155 if ((uint32_t)secs
!= secs
)
158 jz4740_rtc_reg_write(rtc
, JZ_REG_RTC_SEC_ALARM
, (uint32_t)secs
);
159 jz4740_rtc_ctrl_set_bits(rtc
, JZ_RTC_CTRL_AE
,
160 alrm
->enabled
? JZ_RTC_CTRL_AE
: 0);
165 static int jz4740_rtc_update_irq_enable(struct device
*dev
, unsigned int enabled
)
167 struct jz4740_rtc
*rtc
= dev_to_rtc(dev
);
168 jz4740_rtc_ctrl_set_bits(rtc
, JZ_RTC_CTRL_1HZ_IRQ
,
169 enabled
? JZ_RTC_CTRL_1HZ_IRQ
: 0);
174 static int jz4740_rtc_alarm_irq_enable(struct device
*dev
, unsigned int enabled
)
176 struct jz4740_rtc
*rtc
= dev_to_rtc(dev
);
177 jz4740_rtc_ctrl_set_bits(rtc
, JZ_RTC_CTRL_AF_IRQ
,
178 enabled
? JZ_RTC_CTRL_AF_IRQ
: 0);
182 static struct rtc_class_ops jz4740_rtc_ops
= {
183 .read_time
= jz4740_rtc_read_time
,
184 .set_mmss
= jz4740_rtc_set_mmss
,
185 .read_alarm
= jz4740_rtc_read_alarm
,
186 .set_alarm
= jz4740_rtc_set_alarm
,
187 .update_irq_enable
= jz4740_rtc_update_irq_enable
,
188 .alarm_irq_enable
= jz4740_rtc_alarm_irq_enable
,
191 static irqreturn_t
jz4740_rtc_irq(int irq
, void *data
)
193 struct jz4740_rtc
*rtc
= data
;
195 unsigned long events
= 0;
196 ctrl
= jz4740_rtc_reg_read(rtc
, JZ_REG_RTC_CTRL
);
198 if (ctrl
& JZ_RTC_CTRL_1HZ
)
199 events
|= (RTC_UF
| RTC_IRQF
);
201 if (ctrl
& JZ_RTC_CTRL_AF
)
202 events
|= (RTC_AF
| RTC_IRQF
);
204 rtc_update_irq(rtc
->rtc
, 1, events
);
206 jz4740_rtc_ctrl_set_bits(rtc
, JZ_RTC_CTRL_1HZ
| JZ_RTC_CTRL_AF
, 0);
211 static int __devinit
jz4740_rtc_probe(struct platform_device
*pdev
)
214 struct jz4740_rtc
*rtc
;
217 rtc
= kmalloc(sizeof(*rtc
), GFP_KERNEL
);
219 rtc
->irq
= platform_get_irq(pdev
, 0);
223 dev_err(&pdev
->dev
, "Failed to get platform irq\n");
227 rtc
->mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
230 dev_err(&pdev
->dev
, "Failed to get platform mmio memory\n");
234 rtc
->mem
= request_mem_region(rtc
->mem
->start
, resource_size(rtc
->mem
),
239 dev_err(&pdev
->dev
, "Failed to request mmio memory region\n");
243 rtc
->base
= ioremap_nocache(rtc
->mem
->start
, resource_size(rtc
->mem
));
247 dev_err(&pdev
->dev
, "Failed to ioremap mmio memory\n");
248 goto err_release_mem_region
;
251 platform_set_drvdata(pdev
, rtc
);
253 rtc
->rtc
= rtc_device_register(pdev
->name
, &pdev
->dev
, &jz4740_rtc_ops
,
256 if (IS_ERR(rtc
->rtc
)) {
257 ret
= PTR_ERR(rtc
->rtc
);
258 dev_err(&pdev
->dev
, "Failed to register rtc device: %d\n", ret
);
262 ret
= request_irq(rtc
->irq
, jz4740_rtc_irq
, 0,
266 dev_err(&pdev
->dev
, "Failed to request rtc irq: %d\n", ret
);
267 goto err_unregister_rtc
;
270 scratchpad
= jz4740_rtc_reg_read(rtc
, JZ_REG_RTC_SCRATCHPAD
);
271 if (scratchpad
!= 0x12345678) {
272 jz4740_rtc_reg_write(rtc
, JZ_REG_RTC_SCRATCHPAD
, 0x12345678);
273 jz4740_rtc_reg_write(rtc
, JZ_REG_RTC_SEC
, 0);
279 rtc_device_unregister(rtc
->rtc
);
281 platform_set_drvdata(pdev
, NULL
);
283 err_release_mem_region
:
284 release_mem_region(rtc
->mem
->start
, resource_size(rtc
->mem
));
291 static int __devexit
jz4740_rtc_remove(struct platform_device
*pdev
)
293 struct jz4740_rtc
*rtc
= platform_get_drvdata(pdev
);
295 rtc_device_unregister(rtc
->rtc
);
298 release_mem_region(rtc
->mem
->start
, resource_size(rtc
->mem
));
302 platform_set_drvdata(pdev
, NULL
);
307 struct platform_driver jz4740_rtc_driver
= {
308 .probe
= jz4740_rtc_probe
,
309 .remove
= __devexit_p(jz4740_rtc_remove
),
311 .name
= "jz4740-rtc",
312 .owner
= THIS_MODULE
,
316 static int __init
jz4740_rtc_init(void)
318 return platform_driver_register(&jz4740_rtc_driver
);
320 module_init(jz4740_rtc_init
);
322 static void __exit
jz4740_rtc_exit(void)
324 platform_driver_unregister(&jz4740_rtc_driver
);
326 module_exit(jz4740_rtc_exit
);
328 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
329 MODULE_LICENSE("GPL");
330 MODULE_DESCRIPTION("RTC driver for the JZ4720/JZ4740 SoC\n");
331 MODULE_ALIAS("platform:jz4740-rtc");
332 MODULE_ALIAS("platform:jz4720-rtc");