package/mac80211/patches/404-ath9k-uninline-ath9k_io-read-write-32-routines.patch

   1 From dd51972ba5d11df434faf9171fe02c0cc48d35c1 Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Wed, 29 Apr 2009 08:52:16 +0200
   4 Subject: [PATCH] ath9k: uninline ath9k_io{read,write}32 routines
   5
   6 The spin_lock handling uses lots of instructions on some archs.
   7 With this patch the size of the ath9k module will be significantly
   8 smaller.
   9
  10 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  11 ---
  12 Example results on different platforms:
  13
  14 xscale:     468344 -> 293022 (62.6%)
  15 mips32:     549847 -> 389421 (70.8%)
  16 mips32r2:   510520 -> 394020 (77.2%)
  17 ppc40x:     365153 -> 296928 (81.3%)
  18
  19  drivers/net/wireless/ath9k/ath9k.h |   33 +------------------------------
  20  drivers/net/wireless/ath9k/hw.c    |   32 +++++++++++++++++++++++++++++++
  21  2 files changed, 34 insertions(+), 31 deletions(-)
  22
  23 --- a/drivers/net/wireless/ath9k/ath9k.h
  24 +++ b/drivers/net/wireless/ath9k/ath9k.h
  25 @@ -721,36 +721,7 @@ void ath9k_wiphy_pause_all_forced(struct
  26  bool ath9k_wiphy_scanning(struct ath_softc *sc);
  27  void ath9k_wiphy_work(struct work_struct *work);
  28
  29 -/*
  30 - * Read and write, they both share the same lock. We do this to serialize
  31 - * reads and writes on Atheros 802.11n PCI devices only. This is required
  32 - * as the FIFO on these devices can only accept sanely 2 requests. After
  33 - * that the device goes bananas. Serializing the reads/writes prevents this
  34 - * from happening.
  35 - */
  36 -
  37 -static inline void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
  38 -{
  39 -       if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
  40 -               unsigned long flags;
  41 -               spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
  42 -               iowrite32(val, ah->ah_sc->mem + reg_offset);
  43 -               spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
  44 -       } else
  45 -               iowrite32(val, ah->ah_sc->mem + reg_offset);
  46 -}
  47 -
  48 -static inline unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
  49 -{
  50 -       u32 val;
  51 -       if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
  52 -               unsigned long flags;
  53 -               spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
  54 -               val = ioread32(ah->ah_sc->mem + reg_offset);
  55 -               spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
  56 -       } else
  57 -               val = ioread32(ah->ah_sc->mem + reg_offset);
  58 -       return val;
  59 -}
  60 +void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val);
  61 +unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset);
  62
  63  #endif /* ATH9K_H */
  64 --- a/drivers/net/wireless/ath9k/hw.c
  65 +++ b/drivers/net/wireless/ath9k/hw.c
  66 @@ -84,6 +84,38 @@ static u32 ath9k_hw_mac_to_clks(struct a
  67                 return ath9k_hw_mac_clks(ah, usecs);
  68  }
  69
  70 +/*
  71 + * Read and write, they both share the same lock. We do this to serialize
  72 + * reads and writes on Atheros 802.11n PCI devices only. This is required
  73 + * as the FIFO on these devices can only accept sanely 2 requests. After
  74 + * that the device goes bananas. Serializing the reads/writes prevents this
  75 + * from happening.
  76 + */
  77 +
  78 +void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
  79 +{
  80 +       if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
  81 +               unsigned long flags;
  82 +               spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
  83 +               iowrite32(val, ah->ah_sc->mem + reg_offset);
  84 +               spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
  85 +       } else
  86 +               iowrite32(val, ah->ah_sc->mem + reg_offset);
  87 +}
  88 +
  89 +unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
  90 +{
  91 +       u32 val;
  92 +       if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
  93 +               unsigned long flags;
  94 +               spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
  95 +               val = ioread32(ah->ah_sc->mem + reg_offset);
  96 +               spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
  97 +       } else
  98 +               val = ioread32(ah->ah_sc->mem + reg_offset);
  99 +       return val;
 100 +}
 101 +
 102  bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 103  {
 104         int i;