openwrt/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch

   1 diff -urN linux.old/arch/mips/kernel/genex.S linux.dev/arch/mips/kernel/genex.S
   2 --- linux.old/arch/mips/kernel/genex.S  2005-12-04 06:10:42.000000000 +0100
   3 +++ linux.dev/arch/mips/kernel/genex.S  2005-12-18 05:30:48.564937750 +0100
   4 @@ -72,6 +72,10 @@
   5         .set    push
   6         .set    mips3
   7         .set    noat
   8 +#ifdef CONFIG_BCM4710
   9 +       nop
  10 +       nop
  11 +#endif
  12         mfc0    k1, CP0_CAUSE
  13         li      k0, 31<<2
  14         andi    k1, k1, 0x7c
  15 diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
  16 --- linux.old/arch/mips/mm/c-r4k.c      2005-12-04 06:10:42.000000000 +0100
  17 +++ linux.dev/arch/mips/mm/c-r4k.c      2005-12-18 06:08:19.112437750 +0100
  18 @@ -14,6 +14,12 @@
  19  #include <linux/mm.h>
  20  #include <linux/bitops.h>
  21
  22 +#ifdef CONFIG_BCM4710
  23 +#include "../bcm947xx/include/typedefs.h"
  24 +#include "../bcm947xx/include/sbconfig.h"
  25 +#include <asm/paccess.h>
  26 +#endif
  27 +
  28  #include <asm/bcache.h>
  29  #include <asm/bootinfo.h>
  30  #include <asm/cache.h>
  31 @@ -29,6 +35,9 @@
  32  #include <asm/war.h>
  33  #include <asm/cacheflush.h> /* for run_uncached() */
  34
  35 +/* For enabling BCM4710 cache workarounds */
  36 +int bcm4710 = 0;
  37 +
  38  /*
  39   * Must die.
  40   */
  41 @@ -73,7 +82,9 @@
  42  {
  43         unsigned long  dc_lsize = cpu_dcache_line_size();
  44
  45 -       if (dc_lsize == 16)
  46 +       if (bcm4710)
  47 +               r4k_blast_dcache_page = blast_dcache_page;
  48 +       else if (dc_lsize == 16)
  49                 r4k_blast_dcache_page = blast_dcache16_page;
  50         else if (dc_lsize == 32)
  51                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
  52 @@ -85,7 +96,9 @@
  53  {
  54         unsigned long dc_lsize = cpu_dcache_line_size();
  55
  56 -       if (dc_lsize == 16)
  57 +       if (bcm4710)
  58 +               r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
  59 +       else if (dc_lsize == 16)
  60                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
  61         else if (dc_lsize == 32)
  62                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
  63 @@ -97,7 +110,9 @@
  64  {
  65         unsigned long dc_lsize = cpu_dcache_line_size();
  66
  67 -       if (dc_lsize == 16)
  68 +       if (bcm4710)
  69 +               r4k_blast_dcache = blast_dcache;
  70 +       else if (dc_lsize == 16)
  71                 r4k_blast_dcache = blast_dcache16;
  72         else if (dc_lsize == 32)
  73                 r4k_blast_dcache = blast_dcache32;
  74 @@ -486,6 +501,9 @@
  75                         addr = start & ~(dc_lsize - 1);
  76                         aend = (end - 1) & ~(dc_lsize - 1);
  77
  78 +                       BCM4710_PROTECTED_FILL_TLB(addr);
  79 +                       BCM4710_PROTECTED_FILL_TLB(aend);
  80 +
  81                         while (1) {
  82                                 /* Hit_Writeback_Inv_D */
  83                                 protected_writeback_dcache_line(addr);
  84 @@ -657,6 +675,10 @@
  85                 R4600_HIT_CACHEOP_WAR_IMPL;
  86                 a = addr & ~(dc_lsize - 1);
  87                 end = (addr + size - 1) & ~(dc_lsize - 1);
  88 +
  89 +               BCM4710_FILL_TLB(a);
  90 +               BCM4710_FILL_TLB(end);
  91 +
  92                 while (1) {
  93                         flush_dcache_line(a);   /* Hit_Writeback_Inv_D */
  94                         if (a == end)
  95 @@ -702,6 +724,10 @@
  96                 R4600_HIT_CACHEOP_WAR_IMPL;
  97                 a = addr & ~(dc_lsize - 1);
  98                 end = (addr + size - 1) & ~(dc_lsize - 1);
  99 +
 100 +               BCM4710_FILL_TLB(a);
 101 +               BCM4710_FILL_TLB(end);
 102 +
 103                 while (1) {
 104                         flush_dcache_line(a);   /* Hit_Writeback_Inv_D */
 105                         if (a == end)
 106 @@ -727,6 +753,8 @@
 107         unsigned long addr = (unsigned long) arg;
 108
 109         R4600_HIT_CACHEOP_WAR_IMPL;
 110 +       BCM4710_PROTECTED_FILL_TLB(addr);
 111 +       BCM4710_PROTECTED_FILL_TLB(addr + 4);
 112         protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
 113         if (!cpu_icache_snoops_remote_store)
 114                 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
 115 @@ -1202,6 +1230,16 @@
 116  static inline void coherency_setup(void)
 117  {
 118         change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
 119 +#if defined(CONFIG_BCM4310) || defined(CONFIG_BCM4704) || defined(CONFIG_BCM5365)
 120 +       if (BCM330X(current_cpu_data.processor_id)) {
 121 +               __u32 cm = read_c0_diag();
 122 +               /* Enable icache */
 123 +               cm |= (1 << 31);
 124 +               /* Enable dcache */
 125 +               cm |= (1 << 30);
 126 +               write_c0_diag(cm);
 127 +       }
 128 +#endif
 129
 130         /*
 131          * c0_status.cu=0 specifies that updates by the sc instruction use
 132 @@ -1231,6 +1269,15 @@
 133
 134         /* Default cache error handler for R4000 and R5000 family */
 135         set_uncached_handler (0x100, &except_vec2_generic, 0x80);
 136 +
 137 +       /* Check if special workarounds are required */
 138 +#ifdef CONFIG_BCM4710
 139 +       if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
 140 +               printk("Enabling BCM4710A0 cache workarounds.\n");
 141 +               bcm4710 = 1;
 142 +       } else
 143 +#endif
 144 +               bcm4710 = 0;
 145
 146         probe_pcache();
 147         setup_scache();
 148 diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
 149 --- linux.old/arch/mips/mm/tlbex.c      2005-12-15 12:57:27.945158000 +0100
 150 +++ linux.dev/arch/mips/mm/tlbex.c      2005-12-18 06:06:17.916863500 +0100
 151 @@ -28,6 +28,10 @@
 152
 153  /* #define DEBUG_TLB */
 154
 155 +#ifdef CONFIG_BCM4710
 156 +extern int bcm4710;
 157 +#endif
 158 +
 159  static __init int __attribute__((unused)) r45k_bvahwbug(void)
 160  {
 161         /* XXX: We should probe for the presence of this bug, but we don't. */
 162 @@ -1152,6 +1156,12 @@
 163         memset(relocs, 0, sizeof(relocs));
 164         memset(final_handler, 0, sizeof(final_handler));
 165
 166 +#ifdef CONFIG_BCM4710
 167 +       if (bcm4710) {
 168 +               i_nop(&p);
 169 +       }
 170 +#endif
 171 +
 172         /*
 173          * create the plain linear handler
 174          */
 175 diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
 176 --- linux.old/include/asm-mips/r4kcache.h       2005-12-17 22:39:19.281320000 +0100
 177 +++ linux.dev/include/asm-mips/r4kcache.h       2005-12-18 05:22:06.020280750 +0100
 178 @@ -15,6 +15,18 @@
 179  #include <asm/asm.h>
 180  #include <asm/cacheops.h>
 181
 182 +#ifdef CONFIG_BCM4710
 183 +#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
 184 +
 185 +#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
 186 +#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
 187 +#else
 188 +#define BCM4710_DUMMY_RREG()
 189 +
 190 +#define BCM4710_FILL_TLB(addr)
 191 +#define BCM4710_PROTECTED_FILL_TLB(addr)
 192 +#endif
 193 +
 194  /*
 195   * This macro return a properly sign-extended address suitable as base address
 196   * for indexed cache operations.  Two issues here:
 197 @@ -45,6 +57,7 @@
 198
 199  static inline void flush_dcache_line_indexed(unsigned long addr)
 200  {
 201 +       BCM4710_DUMMY_RREG();
 202         cache_op(Index_Writeback_Inv_D, addr);
 203  }
 204
 205 @@ -60,11 +73,13 @@
 206
 207  static inline void flush_dcache_line(unsigned long addr)
 208  {
 209 +       BCM4710_DUMMY_RREG();
 210         cache_op(Hit_Writeback_Inv_D, addr);
 211  }
 212
 213  static inline void invalidate_dcache_line(unsigned long addr)
 214  {
 215 +       BCM4710_DUMMY_RREG();
 216         cache_op(Hit_Invalidate_D, addr);
 217  }
 218
 219 @@ -104,6 +119,7 @@
 220   */
 221  static inline void protected_writeback_dcache_line(unsigned long addr)
 222  {
 223 +       BCM4710_DUMMY_RREG();
 224         __asm__ __volatile__(
 225                 "       .set    push                    \n"
 226                 "       .set    noreorder               \n"
 227 @@ -166,6 +182,49 @@
 228                 : "r" (base),                                           \
 229                   "i" (op));
 230
 231 +static inline void blast_dcache(void)
 232 +{
 233 +       unsigned long start = KSEG0;
 234 +       unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
 235 +       unsigned long end = (start + dcache_size);
 236 +
 237 +       do {
 238 +               BCM4710_DUMMY_RREG();
 239 +               cache_op(Index_Writeback_Inv_D, start);
 240 +               start += current_cpu_data.dcache.linesz;
 241 +       } while(start < end);
 242 +}
 243 +
 244 +static inline void blast_dcache_page(unsigned long page)
 245 +{
 246 +       unsigned long start = page;
 247 +       unsigned long end = start + PAGE_SIZE;
 248 +
 249 +       BCM4710_FILL_TLB(start);
 250 +       do {
 251 +               BCM4710_DUMMY_RREG();
 252 +               cache_op(Hit_Writeback_Inv_D, start);
 253 +               start += current_cpu_data.dcache.linesz;
 254 +       } while(start < end);
 255 +}
 256 +
 257 +static inline void blast_dcache_page_indexed(unsigned long page)
 258 +{
 259 +       unsigned long start = page;
 260 +       unsigned long end = start + PAGE_SIZE;
 261 +       unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
 262 +       unsigned long ws_end = current_cpu_data.dcache.ways <<
 263 +                              current_cpu_data.dcache.waybit;
 264 +       unsigned long ws, addr;
 265 +       for (ws = 0; ws < ws_end; ws += ws_inc) {
 266 +               start = page + ws;
 267 +               for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
 268 +                       BCM4710_DUMMY_RREG();
 269 +                       cache_op(Index_Writeback_Inv_D, addr);
 270 +               }
 271 +       }
 272 +}
 273 +
 274  static inline void blast_dcache16(void)
 275  {
 276         unsigned long start = INDEX_BASE;
 277 @@ -213,7 +272,8 @@
 278         unsigned long ws_end = current_cpu_data.icache.ways <<
 279                                current_cpu_data.icache.waybit;
 280         unsigned long ws, addr;
 281 -
 282 +
 283 +       BCM4710_FILL_TLB(start);
 284         for (ws = 0; ws < ws_end; ws += ws_inc)
 285                 for (addr = start; addr < end; addr += 0x200)
 286                         cache16_unroll32(addr|ws,Index_Invalidate_I);
 287 @@ -357,6 +417,7 @@
 288                                current_cpu_data.icache.waybit;
 289         unsigned long ws, addr;
 290
 291 +       BCM4710_FILL_TLB(start);
 292         for (ws = 0; ws < ws_end; ws += ws_inc)
 293                 for (addr = start; addr < end; addr += 0x400)
 294                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 295 @@ -471,6 +532,7 @@
 296         unsigned long start = page;
 297         unsigned long end = start + PAGE_SIZE;
 298
 299 +       BCM4710_FILL_TLB(start);
 300         do {
 301                 cache64_unroll32(start,Hit_Invalidate_I);
 302                 start += 0x800;
 303 diff -urN linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h
 304 --- linux.old/include/asm-mips/stackframe.h     2005-12-04 06:10:42.000000000 +0100
 305 +++ linux.dev/include/asm-mips/stackframe.h     2005-12-18 05:33:02.405302250 +0100
 306 @@ -285,6 +285,10 @@
 307                 .macro  RESTORE_SP_AND_RET
 308                 LONG_L  sp, PT_R29(sp)
 309                 .set    mips3
 310 +#ifdef CONFIG_BCM4710
 311 +               nop
 312 +               nop
 313 +#endif
 314                 eret
 315                 .set    mips0
 316                 .endm