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[ixp4xx]: update the gpiolib patch
[openwrt.git] / target / linux / omap24xx / patches-2.6.36 / 200-omap-platform.patch
1 ---
2 arch/arm/include/asm/setup.h | 12
3 arch/arm/plat-omap/Kconfig | 32 +
4 arch/arm/plat-omap/Makefile | 5
5 arch/arm/plat-omap/bootreason.c | 79 ++
6 arch/arm/plat-omap/common.c | 70 ++
7 arch/arm/plat-omap/component-version.c | 64 ++
8 arch/arm/plat-omap/gpio-switch.c | 554 ++++++++++++++++++
9 arch/arm/plat-omap/include/mach/blizzard.h | 12
10 arch/arm/plat-omap/include/mach/board-ams-delta.h | 76 ++
11 arch/arm/plat-omap/include/mach/board-sx1.h | 52 +
12 arch/arm/plat-omap/include/mach/board-voiceblue.h | 19
13 arch/arm/plat-omap/include/mach/board.h | 169 +++++
14 arch/arm/plat-omap/include/mach/cbus.h | 31 +
15 arch/arm/plat-omap/include/mach/clkdev.h | 13
16 arch/arm/plat-omap/include/mach/clkdev_omap.h | 41 +
17 arch/arm/plat-omap/include/mach/clock.h | 168 +++++
18 arch/arm/plat-omap/include/mach/clockdomain.h | 111 +++
19 arch/arm/plat-omap/include/mach/common.h | 83 ++
20 arch/arm/plat-omap/include/mach/control.h | 325 ++++++++++
21 arch/arm/plat-omap/include/mach/cpu.h | 516 +++++++++++++++++
22 arch/arm/plat-omap/include/mach/display.h | 575 +++++++++++++++++++
23 arch/arm/plat-omap/include/mach/dma.h | 640 +++++++++++++++++++++
24 arch/arm/plat-omap/include/mach/dmtimer.h | 84 ++
25 arch/arm/plat-omap/include/mach/dsp_common.h | 40 +
26 arch/arm/plat-omap/include/mach/fpga.h | 197 ++++++
27 arch/arm/plat-omap/include/mach/gpio-switch.h | 54 +
28 arch/arm/plat-omap/include/mach/gpio.h | 129 ++++
29 arch/arm/plat-omap/include/mach/gpmc-smc91x.h | 42 +
30 arch/arm/plat-omap/include/mach/gpmc.h | 115 +++
31 arch/arm/plat-omap/include/mach/hardware.h | 290 +++++++++
32 arch/arm/plat-omap/include/mach/hwa742.h | 8
33 arch/arm/plat-omap/include/mach/i2c.h | 39 +
34 arch/arm/plat-omap/include/mach/io.h | 287 +++++++++
35 arch/arm/plat-omap/include/mach/iommu.h | 168 +++++
36 arch/arm/plat-omap/include/mach/iommu2.h | 96 +++
37 arch/arm/plat-omap/include/mach/iovmm.h | 94 +++
38 arch/arm/plat-omap/include/mach/irda.h | 33 +
39 arch/arm/plat-omap/include/mach/irqs.h | 506 ++++++++++++++++
40 arch/arm/plat-omap/include/mach/keypad.h | 45 +
41 arch/arm/plat-omap/include/mach/lcd_mipid.h | 29
42 arch/arm/plat-omap/include/mach/led.h | 24
43 arch/arm/plat-omap/include/mach/mailbox.h | 111 +++
44 arch/arm/plat-omap/include/mach/mcbsp.h | 462 +++++++++++++++
45 arch/arm/plat-omap/include/mach/mcspi.h | 15
46 arch/arm/plat-omap/include/mach/memory.h | 103 +++
47 arch/arm/plat-omap/include/mach/menelaus.h | 49 +
48 arch/arm/plat-omap/include/mach/mmc.h | 157 +++++
49 arch/arm/plat-omap/include/mach/mux.h | 662 ++++++++++++++++++++++
50 arch/arm/plat-omap/include/mach/nand.h | 24
51 arch/arm/plat-omap/include/mach/omap-alsa.h | 123 ++++
52 arch/arm/plat-omap/include/mach/omap-pm.h | 301 ++++++++++
53 arch/arm/plat-omap/include/mach/omap1510.h | 50 +
54 arch/arm/plat-omap/include/mach/omap16xx.h | 202 ++++++
55 arch/arm/plat-omap/include/mach/omap24xx.h | 89 ++
56 arch/arm/plat-omap/include/mach/omap34xx.h | 86 ++
57 arch/arm/plat-omap/include/mach/omap44xx.h | 48 +
58 arch/arm/plat-omap/include/mach/omap730.h | 102 +++
59 arch/arm/plat-omap/include/mach/omap7xx.h | 104 +++
60 arch/arm/plat-omap/include/mach/omap850.h | 102 +++
61 arch/arm/plat-omap/include/mach/omap_device.h | 143 ++++
62 arch/arm/plat-omap/include/mach/omap_hwmod.h | 467 +++++++++++++++
63 arch/arm/plat-omap/include/mach/onenand.h | 43 +
64 arch/arm/plat-omap/include/mach/param.h | 8
65 arch/arm/plat-omap/include/mach/powerdomain.h | 187 ++++++
66 arch/arm/plat-omap/include/mach/prcm.h | 39 +
67 arch/arm/plat-omap/include/mach/sdrc.h | 158 +++++
68 arch/arm/plat-omap/include/mach/serial.h | 65 ++
69 arch/arm/plat-omap/include/mach/smp.h | 53 +
70 arch/arm/plat-omap/include/mach/sram.h | 78 ++
71 arch/arm/plat-omap/include/mach/system.h | 51 +
72 arch/arm/plat-omap/include/mach/tc.h | 106 +++
73 arch/arm/plat-omap/include/mach/timer-gp.h | 17
74 arch/arm/plat-omap/include/mach/timex.h | 41 +
75 arch/arm/plat-omap/include/mach/uncompress.h | 88 ++
76 arch/arm/plat-omap/include/mach/usb.h | 162 +++++
77 arch/arm/plat-omap/include/mach/vram.h | 62 ++
78 arch/arm/plat-omap/include/mach/vrfb.h | 50 +
79 arch/arm/plat-omap/include/plat/board.h | 8
80 arch/arm/plat-omap/include/plat/cbus.h | 31 +
81 79 files changed, 10573 insertions(+), 1 deletion(-)
82
83 --- /dev/null
84 +++ linux-2.6.36-rc4/arch/arm/plat-omap/bootreason.c
85 @@ -0,0 +1,79 @@
86 +/*
87 + * linux/arch/arm/plat-omap/bootreason.c
88 + *
89 + * OMAP Bootreason passing
90 + *
91 + * Copyright (c) 2004 Nokia
92 + *
93 + * Written by David Weinehall <david.weinehall@nokia.com>
94 + *
95 + * This program is free software; you can redistribute it and/or modify it
96 + * under the terms of the GNU General Public License as published by the
97 + * Free Software Foundation; either version 2 of the License, or (at your
98 + * option) any later version.
99 + *
100 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
101 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
102 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
103 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
104 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
105 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
106 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
107 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
108 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
109 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
110 + *
111 + * You should have received a copy of the GNU General Public License along
112 + * with this program; if not, write to the Free Software Foundation, Inc.,
113 + * 675 Mass Ave, Cambridge, MA 02139, USA.
114 + */
115 +#include <linux/proc_fs.h>
116 +#include <linux/errno.h>
117 +#include <plat/board.h>
118 +
119 +static char boot_reason[16];
120 +
121 +static int omap_bootreason_read_proc(char *page, char **start, off_t off,
122 + int count, int *eof, void *data)
123 +{
124 + int len = 0;
125 +
126 + len += sprintf(page + len, "%s\n", boot_reason);
127 +
128 + *start = page + off;
129 +
130 + if (len > off)
131 + len -= off;
132 + else
133 + len = 0;
134 +
135 + return len < count ? len : count;
136 +}
137 +
138 +static int __init bootreason_init(void)
139 +{
140 + const struct omap_boot_reason_config *cfg;
141 + int reason_valid = 0;
142 +
143 + cfg = omap_get_config(OMAP_TAG_BOOT_REASON, struct omap_boot_reason_config);
144 + if (cfg != NULL) {
145 + strncpy(boot_reason, cfg->reason_str, sizeof(cfg->reason_str));
146 + boot_reason[sizeof(cfg->reason_str)] = 0;
147 + reason_valid = 1;
148 + } else {
149 + /* Read the boot reason from the OMAP registers */
150 + }
151 +
152 + if (!reason_valid)
153 + return -ENOENT;
154 +
155 + printk(KERN_INFO "Bootup reason: %s\n", boot_reason);
156 +
157 + if (!create_proc_read_entry("bootreason", S_IRUGO, NULL,
158 + omap_bootreason_read_proc, NULL))
159 + return -ENOMEM;
160 +
161 + return 0;
162 +}
163 +
164 +late_initcall(bootreason_init);
165 --- linux-2.6.36-rc4.orig/arch/arm/plat-omap/common.c
166 +++ linux-2.6.36-rc4/arch/arm/plat-omap/common.c
167 @@ -49,11 +49,81 @@
168 struct omap_board_config_kernel *omap_board_config;
169 int omap_board_config_size;
170
171 +unsigned char omap_bootloader_tag[1024];
172 +int omap_bootloader_tag_len;
173 +
174 +/* used by omap-smp.c and board-4430sdp.c */
175 +void __iomem *gic_cpu_base_addr;
176 +
177 +#ifdef CONFIG_OMAP_BOOT_TAG
178 +
179 +static int __init parse_tag_omap(const struct tag *tag)
180 +{
181 + u32 size = tag->hdr.size - (sizeof(tag->hdr) >> 2);
182 +
183 + size <<= 2;
184 + if (size > sizeof(omap_bootloader_tag))
185 + return -1;
186 +
187 + memcpy(omap_bootloader_tag, tag->u.omap.data, size);
188 + omap_bootloader_tag_len = size;
189 +
190 + return 0;
191 +}
192 +
193 +__tagtable(ATAG_BOARD, parse_tag_omap);
194 +
195 +#endif
196 +
197 static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
198 {
199 struct omap_board_config_kernel *kinfo = NULL;
200 int i;
201
202 +#ifdef CONFIG_OMAP_BOOT_TAG
203 + struct omap_board_config_entry *info = NULL;
204 +
205 + if (omap_bootloader_tag_len > 4)
206 + info = (struct omap_board_config_entry *) omap_bootloader_tag;
207 + while (info != NULL) {
208 + u8 *next;
209 +
210 + if (info->tag == tag) {
211 + if (skip == 0)
212 + break;
213 + skip--;
214 + }
215 +
216 + if ((info->len & 0x03) != 0) {
217 + /* We bail out to avoid an alignment fault */
218 + printk(KERN_ERR "OMAP peripheral config: Length (%d) not word-aligned (tag %04x)\n",
219 + info->len, info->tag);
220 + return NULL;
221 + }
222 + next = (u8 *) info + sizeof(*info) + info->len;
223 + if (next >= omap_bootloader_tag + omap_bootloader_tag_len)
224 + info = NULL;
225 + else
226 + info = (struct omap_board_config_entry *) next;
227 + }
228 + if (info != NULL) {
229 + /* Check the length as a lame attempt to check for
230 + * binary inconsistency. */
231 + if (len != NO_LENGTH_CHECK) {
232 + /* Word-align len */
233 + if (len & 0x03)
234 + len = (len + 3) & ~0x03;
235 + if (info->len != len) {
236 + printk(KERN_ERR "OMAP peripheral config: Length mismatch with tag %x (want %d, got %d)\n",
237 + tag, len, info->len);
238 + return NULL;
239 + }
240 + }
241 + if (len_out != NULL)
242 + *len_out = info->len;
243 + return info->data;
244 + }
245 +#endif
246 /* Try to find the config from the board-specific structures
247 * in the kernel. */
248 for (i = 0; i < omap_board_config_size; i++) {
249 --- /dev/null
250 +++ linux-2.6.36-rc4/arch/arm/plat-omap/component-version.c
251 @@ -0,0 +1,64 @@
252 +/*
253 + * linux/arch/arm/plat-omap/component-version.c
254 + *
255 + * Copyright (C) 2005 Nokia Corporation
256 + * Written by Juha Yrjölä <juha.yrjola@nokia.com>
257 + *
258 + * This program is free software; you can redistribute it and/or modify
259 + * it under the terms of the GNU General Public License version 2 as
260 + * published by the Free Software Foundation.
261 + */
262 +
263 +#include <linux/init.h>
264 +#include <linux/module.h>
265 +#include <linux/err.h>
266 +#include <linux/proc_fs.h>
267 +#include <plat/board.h>
268 +
269 +static int component_version_read_proc(char *page, char **start, off_t off,
270 + int count, int *eof, void *data)
271 +{
272 + int len, i;
273 + const struct omap_version_config *ver;
274 + char *p;
275 +
276 + i = 0;
277 + p = page;
278 + while ((ver = omap_get_nr_config(OMAP_TAG_VERSION_STR,
279 + struct omap_version_config, i)) != NULL) {
280 + p += sprintf(p, "%-12s%s\n", ver->component, ver->version);
281 + i++;
282 + }
283 +
284 + len = (p - page) - off;
285 + if (len < 0)
286 + len = 0;
287 +
288 + *eof = (len <= count) ? 1 : 0;
289 + *start = page + off;
290 +
291 + return len;
292 +}
293 +
294 +static int __init component_version_init(void)
295 +{
296 + if (omap_get_config(OMAP_TAG_VERSION_STR, struct omap_version_config) == NULL)
297 + return -ENODEV;
298 + if (!create_proc_read_entry("component_version", S_IRUGO, NULL,
299 + component_version_read_proc, NULL))
300 + return -ENOMEM;
301 +
302 + return 0;
303 +}
304 +
305 +static void __exit component_version_exit(void)
306 +{
307 + remove_proc_entry("component_version", NULL);
308 +}
309 +
310 +late_initcall(component_version_init);
311 +module_exit(component_version_exit);
312 +
313 +MODULE_AUTHOR("Juha Yrjölä <juha.yrjola@nokia.com>");
314 +MODULE_DESCRIPTION("Component version driver");
315 +MODULE_LICENSE("GPL");
316 --- /dev/null
317 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/blizzard.h
318 @@ -0,0 +1,12 @@
319 +#ifndef _BLIZZARD_H
320 +#define _BLIZZARD_H
321 +
322 +struct blizzard_platform_data {
323 + void (*power_up)(struct device *dev);
324 + void (*power_down)(struct device *dev);
325 + unsigned long (*get_clock_rate)(struct device *dev);
326 +
327 + unsigned te_connected : 1;
328 +};
329 +
330 +#endif
331 --- /dev/null
332 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/board-ams-delta.h
333 @@ -0,0 +1,76 @@
334 +/*
335 + * arch/arm/plat-omap/include/mach/board-ams-delta.h
336 + *
337 + * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
338 + *
339 + * This program is free software; you can redistribute it and/or modify it
340 + * under the terms of the GNU General Public License as published by the
341 + * Free Software Foundation; either version 2 of the License, or (at your
342 + * option) any later version.
343 + *
344 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
345 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
346 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
347 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
348 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
349 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
350 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
351 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
352 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
353 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
354 + *
355 + * You should have received a copy of the GNU General Public License along
356 + * with this program; if not, write to the Free Software Foundation, Inc.,
357 + * 675 Mass Ave, Cambridge, MA 02139, USA.
358 + */
359 +#ifndef __ASM_ARCH_OMAP_AMS_DELTA_H
360 +#define __ASM_ARCH_OMAP_AMS_DELTA_H
361 +
362 +#if defined (CONFIG_MACH_AMS_DELTA)
363 +
364 +#define AMS_DELTA_LATCH1_PHYS 0x01000000
365 +#define AMS_DELTA_LATCH1_VIRT 0xEA000000
366 +#define AMS_DELTA_MODEM_PHYS 0x04000000
367 +#define AMS_DELTA_MODEM_VIRT 0xEB000000
368 +#define AMS_DELTA_LATCH2_PHYS 0x08000000
369 +#define AMS_DELTA_LATCH2_VIRT 0xEC000000
370 +
371 +#define AMS_DELTA_LATCH1_LED_CAMERA 0x01
372 +#define AMS_DELTA_LATCH1_LED_ADVERT 0x02
373 +#define AMS_DELTA_LATCH1_LED_EMAIL 0x04
374 +#define AMS_DELTA_LATCH1_LED_HANDSFREE 0x08
375 +#define AMS_DELTA_LATCH1_LED_VOICEMAIL 0x10
376 +#define AMS_DELTA_LATCH1_LED_VOICE 0x20
377 +
378 +#define AMS_DELTA_LATCH2_LCD_VBLEN 0x0001
379 +#define AMS_DELTA_LATCH2_LCD_NDISP 0x0002
380 +#define AMS_DELTA_LATCH2_NAND_NCE 0x0004
381 +#define AMS_DELTA_LATCH2_NAND_NRE 0x0008
382 +#define AMS_DELTA_LATCH2_NAND_NWP 0x0010
383 +#define AMS_DELTA_LATCH2_NAND_NWE 0x0020
384 +#define AMS_DELTA_LATCH2_NAND_ALE 0x0040
385 +#define AMS_DELTA_LATCH2_NAND_CLE 0x0080
386 +#define AMD_DELTA_LATCH2_KEYBRD_PWR 0x0100
387 +#define AMD_DELTA_LATCH2_KEYBRD_DATA 0x0200
388 +#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400
389 +#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800
390 +#define AMS_DELTA_LATCH2_MODEM_NRESET 0x1000
391 +#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000
392 +
393 +#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0
394 +#define AMS_DELTA_GPIO_PIN_KEYBRD_CLK 1
395 +#define AMS_DELTA_GPIO_PIN_MODEM_IRQ 2
396 +#define AMS_DELTA_GPIO_PIN_HOOK_SWITCH 4
397 +#define AMS_DELTA_GPIO_PIN_SCARD_NOFF 6
398 +#define AMS_DELTA_GPIO_PIN_SCARD_IO 7
399 +#define AMS_DELTA_GPIO_PIN_CONFIG 11
400 +#define AMS_DELTA_GPIO_PIN_NAND_RB 12
401 +
402 +#ifndef __ASSEMBLY__
403 +void ams_delta_latch1_write(u8 mask, u8 value);
404 +void ams_delta_latch2_write(u16 mask, u16 value);
405 +#endif
406 +
407 +#endif /* CONFIG_MACH_AMS_DELTA */
408 +
409 +#endif /* __ASM_ARCH_OMAP_AMS_DELTA_H */
410 --- /dev/null
411 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/board.h
412 @@ -0,0 +1,169 @@
413 +/*
414 + * arch/arm/plat-omap/include/mach/board.h
415 + *
416 + * Information structures for board-specific data
417 + *
418 + * Copyright (C) 2004 Nokia Corporation
419 + * Written by Juha Yrjölä <juha.yrjola@nokia.com>
420 + */
421 +
422 +#ifndef _OMAP_BOARD_H
423 +#define _OMAP_BOARD_H
424 +
425 +#include <linux/types.h>
426 +
427 +#include <plat/gpio-switch.h>
428 +
429 +/*
430 + * OMAP35x EVM revision
431 + * Run time detection of EVM revision is done by reading Ethernet
432 + * PHY ID -
433 + * GEN_1 = 0x01150000
434 + * GEN_2 = 0x92200000
435 + */
436 +enum {
437 + OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */
438 + OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */
439 +};
440 +
441 +/* Different peripheral ids */
442 +#define OMAP_TAG_CLOCK 0x4f01
443 +#define OMAP_TAG_LCD 0x4f05
444 +#define OMAP_TAG_GPIO_SWITCH 0x4f06
445 +#define OMAP_TAG_FBMEM 0x4f08
446 +#define OMAP_TAG_STI_CONSOLE 0x4f09
447 +#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
448 +
449 +#define OMAP_TAG_BOOT_REASON 0x4f80
450 +#define OMAP_TAG_FLASH_PART 0x4f81
451 +#define OMAP_TAG_VERSION_STR 0x4f82
452 +
453 +struct omap_clock_config {
454 + /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
455 + u8 system_clock_type;
456 +};
457 +
458 +struct omap_serial_console_config {
459 + u8 console_uart;
460 + u32 console_speed;
461 +};
462 +
463 +struct omap_sti_console_config {
464 + unsigned enable:1;
465 + u8 channel;
466 +};
467 +
468 +struct omap_camera_sensor_config {
469 + u16 reset_gpio;
470 + int (*power_on)(void * data);
471 + int (*power_off)(void * data);
472 +};
473 +
474 +struct omap_usb_config {
475 + /* Configure drivers according to the connectors on your board:
476 + * - "A" connector (rectagular)
477 + * ... for host/OHCI use, set "register_host".
478 + * - "B" connector (squarish) or "Mini-B"
479 + * ... for device/gadget use, set "register_dev".
480 + * - "Mini-AB" connector (very similar to Mini-B)
481 + * ... for OTG use as device OR host, initialize "otg"
482 + */
483 + unsigned register_host:1;
484 + unsigned register_dev:1;
485 + u8 otg; /* port number, 1-based: usb1 == 2 */
486 +
487 + u8 hmc_mode;
488 +
489 + /* implicitly true if otg: host supports remote wakeup? */
490 + u8 rwc;
491 +
492 + /* signaling pins used to talk to transceiver on usbN:
493 + * 0 == usbN unused
494 + * 2 == usb0-only, using internal transceiver
495 + * 3 == 3 wire bidirectional
496 + * 4 == 4 wire bidirectional
497 + * 6 == 6 wire unidirectional (or TLL)
498 + */
499 + u8 pins[3];
500 +};
501 +
502 +struct omap_lcd_config {
503 + char panel_name[16];
504 + char ctrl_name[16];
505 + s16 nreset_gpio;
506 + u8 data_lines;
507 +};
508 +
509 +struct device;
510 +struct fb_info;
511 +struct omap_backlight_config {
512 + int default_intensity;
513 + int (*set_power)(struct device *dev, int state);
514 + int (*check_fb)(struct fb_info *fb);
515 +};
516 +
517 +struct omap_fbmem_config {
518 + u32 start;
519 + u32 size;
520 +};
521 +
522 +struct omap_pwm_led_platform_data {
523 + const char *name;
524 + int intensity_timer;
525 + int blink_timer;
526 + void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
527 +};
528 +
529 +struct omap_uart_config {
530 + /* Bit field of UARTs present; bit 0 --> UART1 */
531 + unsigned int enabled_uarts;
532 +};
533 +
534 +
535 +struct omap_flash_part_config {
536 + char part_table[0];
537 +};
538 +
539 +struct omap_boot_reason_config {
540 + char reason_str[12];
541 +};
542 +
543 +struct omap_version_config {
544 + char component[12];
545 + char version[12];
546 +};
547 +
548 +struct omap_board_config_entry {
549 + u16 tag;
550 + u16 len;
551 + u8 data[0];
552 +};
553 +
554 +struct omap_board_config_kernel {
555 + u16 tag;
556 + const void *data;
557 +};
558 +
559 +extern const void *__omap_get_config(u16 tag, size_t len, int nr);
560 +
561 +#define omap_get_config(tag, type) \
562 + ((const type *) __omap_get_config((tag), sizeof(type), 0))
563 +#define omap_get_nr_config(tag, type, nr) \
564 + ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
565 +
566 +extern const void *omap_get_var_config(u16 tag, size_t *len);
567 +
568 +extern struct omap_board_config_kernel *omap_board_config;
569 +extern int omap_board_config_size;
570 +
571 +
572 +/* for TI reference platforms sharing the same debug card */
573 +extern int debug_card_init(u32 addr, unsigned gpio);
574 +
575 +/* OMAP3EVM revision */
576 +#if defined(CONFIG_MACH_OMAP3EVM)
577 +u8 get_omap3_evm_rev(void);
578 +#else
579 +#define get_omap3_evm_rev() (-EINVAL)
580 +#endif
581 +#endif
582 --- /dev/null
583 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/board-sx1.h
584 @@ -0,0 +1,52 @@
585 +/*
586 + * Siemens SX1 board definitions
587 + *
588 + * Copyright: Vovan888 at gmail com
589 + *
590 + * This package is free software; you can redistribute it and/or modify
591 + * it under the terms of the GNU General Public License version 2 as
592 + * published by the Free Software Foundation.
593 + *
594 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
595 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
596 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
597 + */
598 +
599 +#ifndef __ASM_ARCH_SX1_I2C_CHIPS_H
600 +#define __ASM_ARCH_SX1_I2C_CHIPS_H
601 +
602 +#define SOFIA_MAX_LIGHT_VAL 0x2B
603 +
604 +#define SOFIA_I2C_ADDR 0x32
605 +/* Sofia reg 3 bits masks */
606 +#define SOFIA_POWER1_REG 0x03
607 +
608 +#define SOFIA_USB_POWER 0x01
609 +#define SOFIA_MMC_POWER 0x04
610 +#define SOFIA_BLUETOOTH_POWER 0x08
611 +#define SOFIA_MMILIGHT_POWER 0x20
612 +
613 +#define SOFIA_POWER2_REG 0x04
614 +#define SOFIA_BACKLIGHT_REG 0x06
615 +#define SOFIA_KEYLIGHT_REG 0x07
616 +#define SOFIA_DIMMING_REG 0x09
617 +
618 +
619 +/* Function Prototypes for SX1 devices control on I2C bus */
620 +
621 +int sx1_setbacklight(u8 backlight);
622 +int sx1_getbacklight(u8 *backlight);
623 +int sx1_setkeylight(u8 keylight);
624 +int sx1_getkeylight(u8 *keylight);
625 +
626 +int sx1_setmmipower(u8 onoff);
627 +int sx1_setusbpower(u8 onoff);
628 +int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value);
629 +int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value);
630 +
631 +/* MMC prototypes */
632 +
633 +extern void sx1_mmc_init(void);
634 +extern void sx1_mmc_slot_cover_handler(void *arg, int state);
635 +
636 +#endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */
637 --- /dev/null
638 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/board-voiceblue.h
639 @@ -0,0 +1,19 @@
640 +/*
641 + * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
642 + *
643 + * Hardware definitions for OMAP5910 based VoiceBlue board.
644 + *
645 + * This program is free software; you can redistribute it and/or modify
646 + * it under the terms of the GNU General Public License version 2 as
647 + * published by the Free Software Foundation.
648 + */
649 +
650 +#ifndef __ASM_ARCH_VOICEBLUE_H
651 +#define __ASM_ARCH_VOICEBLUE_H
652 +
653 +extern void voiceblue_wdt_enable(void);
654 +extern void voiceblue_wdt_disable(void);
655 +extern void voiceblue_wdt_ping(void);
656 +
657 +#endif /* __ASM_ARCH_VOICEBLUE_H */
658 +
659 --- /dev/null
660 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/cbus.h
661 @@ -0,0 +1,31 @@
662 +/*
663 + * cbus.h - CBUS platform_data definition
664 + *
665 + * Copyright (C) 2004 - 2009 Nokia Corporation
666 + *
667 + * Written by Felipe Balbi <felipe.balbi@nokia.com>
668 + *
669 + * This file is subject to the terms and conditions of the GNU General
670 + * Public License. See the file "COPYING" in the main directory of this
671 + * archive for more details.
672 + *
673 + * This program is distributed in the hope that it will be useful,
674 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
675 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
676 + * GNU General Public License for more details.
677 + *
678 + * You should have received a copy of the GNU General Public License
679 + * along with this program; if not, write to the Free Software
680 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
681 + */
682 +
683 +#ifndef __PLAT_CBUS_H
684 +#define __PLAT_CBUS_H
685 +
686 +struct cbus_host_platform_data {
687 + int dat_gpio;
688 + int clk_gpio;
689 + int sel_gpio;
690 +};
691 +
692 +#endif /* __PLAT_CBUS_H */
693 --- /dev/null
694 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/clkdev.h
695 @@ -0,0 +1,13 @@
696 +#ifndef __MACH_CLKDEV_H
697 +#define __MACH_CLKDEV_H
698 +
699 +static inline int __clk_get(struct clk *clk)
700 +{
701 + return 1;
702 +}
703 +
704 +static inline void __clk_put(struct clk *clk)
705 +{
706 +}
707 +
708 +#endif
709 --- /dev/null
710 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/clkdev_omap.h
711 @@ -0,0 +1,41 @@
712 +/*
713 + * clkdev <-> OMAP integration
714 + *
715 + * Russell King <linux@arm.linux.org.uk>
716 + *
717 + */
718 +
719 +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
720 +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
721 +
722 +#include <asm/clkdev.h>
723 +
724 +struct omap_clk {
725 + u16 cpu;
726 + struct clk_lookup lk;
727 +};
728 +
729 +#define CLK(dev, con, ck, cp) \
730 + { \
731 + .cpu = cp, \
732 + .lk = { \
733 + .dev_id = dev, \
734 + .con_id = con, \
735 + .clk = ck, \
736 + }, \
737 + }
738 +
739 +
740 +#define CK_310 (1 << 0)
741 +#define CK_7XX (1 << 1)
742 +#define CK_1510 (1 << 2)
743 +#define CK_16XX (1 << 3)
744 +#define CK_243X (1 << 4)
745 +#define CK_242X (1 << 5)
746 +#define CK_343X (1 << 6)
747 +#define CK_3430ES1 (1 << 7)
748 +#define CK_3430ES2 (1 << 8)
749 +#define CK_443X (1 << 9)
750 +
751 +#endif
752 +
753 --- /dev/null
754 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/clockdomain.h
755 @@ -0,0 +1,111 @@
756 +/*
757 + * arch/arm/plat-omap/include/mach/clockdomain.h
758 + *
759 + * OMAP2/3 clockdomain framework functions
760 + *
761 + * Copyright (C) 2008 Texas Instruments, Inc.
762 + * Copyright (C) 2008 Nokia Corporation
763 + *
764 + * Written by Paul Walmsley
765 + *
766 + * This program is free software; you can redistribute it and/or modify
767 + * it under the terms of the GNU General Public License version 2 as
768 + * published by the Free Software Foundation.
769 + */
770 +
771 +#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
772 +#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
773 +
774 +#include <plat/powerdomain.h>
775 +#include <plat/clock.h>
776 +#include <plat/cpu.h>
777 +
778 +/* Clockdomain capability flags */
779 +#define CLKDM_CAN_FORCE_SLEEP (1 << 0)
780 +#define CLKDM_CAN_FORCE_WAKEUP (1 << 1)
781 +#define CLKDM_CAN_ENABLE_AUTO (1 << 2)
782 +#define CLKDM_CAN_DISABLE_AUTO (1 << 3)
783 +
784 +#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
785 +#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
786 +#define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
787 +
788 +/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
789 +#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
790 +#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
791 +
792 +/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
793 +#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0
794 +#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1
795 +#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2
796 +#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3
797 +
798 +/*
799 + * struct clkdm_pwrdm_autodep - a powerdomain that should have wkdeps
800 + * and sleepdeps added when a powerdomain should stay active in hwsup mode;
801 + * and conversely, removed when the powerdomain should be allowed to go
802 + * inactive in hwsup mode.
803 + */
804 +struct clkdm_pwrdm_autodep {
805 +
806 + union {
807 + /* Name of the powerdomain to add a wkdep/sleepdep on */
808 + const char *name;
809 +
810 + /* Powerdomain pointer (looked up at clkdm_init() time) */
811 + struct powerdomain *ptr;
812 + } pwrdm;
813 +
814 + /* OMAP chip types that this clockdomain dep is valid on */
815 + const struct omap_chip_id omap_chip;
816 +
817 +};
818 +
819 +struct clockdomain {
820 +
821 + /* Clockdomain name */
822 + const char *name;
823 +
824 + union {
825 + /* Powerdomain enclosing this clockdomain */
826 + const char *name;
827 +
828 + /* Powerdomain pointer assigned at clkdm_register() */
829 + struct powerdomain *ptr;
830 + } pwrdm;
831 +
832 + /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */
833 + const u16 clktrctrl_mask;
834 +
835 + /* Clockdomain capability flags */
836 + const u8 flags;
837 +
838 + /* OMAP chip types that this clockdomain is valid on */
839 + const struct omap_chip_id omap_chip;
840 +
841 + /* Usecount tracking */
842 + atomic_t usecount;
843 +
844 + struct list_head node;
845 +
846 +};
847 +
848 +void clkdm_init(struct clockdomain **clkdms, struct clkdm_pwrdm_autodep *autodeps);
849 +int clkdm_register(struct clockdomain *clkdm);
850 +int clkdm_unregister(struct clockdomain *clkdm);
851 +struct clockdomain *clkdm_lookup(const char *name);
852 +
853 +int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
854 + void *user);
855 +struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
856 +
857 +void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
858 +void omap2_clkdm_deny_idle(struct clockdomain *clkdm);
859 +
860 +int omap2_clkdm_wakeup(struct clockdomain *clkdm);
861 +int omap2_clkdm_sleep(struct clockdomain *clkdm);
862 +
863 +int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
864 +int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
865 +
866 +#endif
867 --- /dev/null
868 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/clock.h
869 @@ -0,0 +1,168 @@
870 +/*
871 + * arch/arm/plat-omap/include/mach/clock.h
872 + *
873 + * Copyright (C) 2004 - 2005 Nokia corporation
874 + * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
875 + * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
876 + *
877 + * This program is free software; you can redistribute it and/or modify
878 + * it under the terms of the GNU General Public License version 2 as
879 + * published by the Free Software Foundation.
880 + */
881 +
882 +#ifndef __ARCH_ARM_OMAP_CLOCK_H
883 +#define __ARCH_ARM_OMAP_CLOCK_H
884 +
885 +#include <linux/list.h>
886 +
887 +struct module;
888 +struct clk;
889 +struct clockdomain;
890 +
891 +struct clkops {
892 + int (*enable)(struct clk *);
893 + void (*disable)(struct clk *);
894 + void (*find_idlest)(struct clk *, void __iomem **, u8 *);
895 + void (*find_companion)(struct clk *, void __iomem **, u8 *);
896 +};
897 +
898 +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
899 + defined(CONFIG_ARCH_OMAP4)
900 +
901 +struct clksel_rate {
902 + u32 val;
903 + u8 div;
904 + u8 flags;
905 +};
906 +
907 +struct clksel {
908 + struct clk *parent;
909 + const struct clksel_rate *rates;
910 +};
911 +
912 +struct dpll_data {
913 + void __iomem *mult_div1_reg;
914 + u32 mult_mask;
915 + u32 div1_mask;
916 + struct clk *clk_bypass;
917 + struct clk *clk_ref;
918 + void __iomem *control_reg;
919 + u32 enable_mask;
920 + unsigned int rate_tolerance;
921 + unsigned long last_rounded_rate;
922 + u16 last_rounded_m;
923 + u8 last_rounded_n;
924 + u8 min_divider;
925 + u8 max_divider;
926 + u32 max_tolerance;
927 + u16 max_multiplier;
928 +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
929 + u8 modes;
930 + void __iomem *autoidle_reg;
931 + void __iomem *idlest_reg;
932 + u32 autoidle_mask;
933 + u32 freqsel_mask;
934 + u32 idlest_mask;
935 + u8 auto_recal_bit;
936 + u8 recal_en_bit;
937 + u8 recal_st_bit;
938 +# endif
939 +};
940 +
941 +#endif
942 +
943 +struct clk {
944 + struct list_head node;
945 + const struct clkops *ops;
946 + const char *name;
947 + int id;
948 + struct clk *parent;
949 + struct list_head children;
950 + struct list_head sibling; /* node for children */
951 + unsigned long rate;
952 + __u32 flags;
953 + void __iomem *enable_reg;
954 + unsigned long (*recalc)(struct clk *);
955 + int (*set_rate)(struct clk *, unsigned long);
956 + long (*round_rate)(struct clk *, unsigned long);
957 + void (*init)(struct clk *);
958 + __u8 enable_bit;
959 + __s8 usecount;
960 +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
961 + defined(CONFIG_ARCH_OMAP4)
962 + u8 fixed_div;
963 + void __iomem *clksel_reg;
964 + u32 clksel_mask;
965 + const struct clksel *clksel;
966 + struct dpll_data *dpll_data;
967 + const char *clkdm_name;
968 + struct clockdomain *clkdm;
969 +#else
970 + __u8 rate_offset;
971 + __u8 src_offset;
972 +#endif
973 +#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
974 + struct dentry *dent; /* For visible tree hierarchy */
975 +#endif
976 +};
977 +
978 +struct cpufreq_frequency_table;
979 +
980 +struct clk_functions {
981 + int (*clk_enable)(struct clk *clk);
982 + void (*clk_disable)(struct clk *clk);
983 + long (*clk_round_rate)(struct clk *clk, unsigned long rate);
984 + int (*clk_set_rate)(struct clk *clk, unsigned long rate);
985 + int (*clk_set_parent)(struct clk *clk, struct clk *parent);
986 + void (*clk_allow_idle)(struct clk *clk);
987 + void (*clk_deny_idle)(struct clk *clk);
988 + void (*clk_disable_unused)(struct clk *clk);
989 +#ifdef CONFIG_CPU_FREQ
990 + void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
991 +#endif
992 +};
993 +
994 +extern unsigned int mpurate;
995 +
996 +extern int clk_init(struct clk_functions *custom_clocks);
997 +extern void clk_preinit(struct clk *clk);
998 +extern int clk_register(struct clk *clk);
999 +extern void clk_reparent(struct clk *child, struct clk *parent);
1000 +extern void clk_unregister(struct clk *clk);
1001 +extern void propagate_rate(struct clk *clk);
1002 +extern void recalculate_root_clocks(void);
1003 +extern unsigned long followparent_recalc(struct clk *clk);
1004 +extern void clk_enable_init_clocks(void);
1005 +#ifdef CONFIG_CPU_FREQ
1006 +extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
1007 +#endif
1008 +
1009 +extern const struct clkops clkops_null;
1010 +
1011 +/* Clock flags */
1012 +/* bit 0 is free */
1013 +#define RATE_FIXED (1 << 1) /* Fixed clock rate */
1014 +/* bits 2-4 are free */
1015 +#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */
1016 +#define CLOCK_IDLE_CONTROL (1 << 7)
1017 +#define CLOCK_NO_IDLE_PARENT (1 << 8)
1018 +#define DELAYED_APP (1 << 9) /* Delay application of clock */
1019 +#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
1020 +#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
1021 +#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
1022 +#define CLOCK_IN_OMAP4430 (1 << 13)
1023 +#define ALWAYS_ENABLED (1 << 14)
1024 +/* bits 13-31 are currently free */
1025 +
1026 +/* Clksel_rate flags */
1027 +#define DEFAULT_RATE (1 << 0)
1028 +#define RATE_IN_242X (1 << 1)
1029 +#define RATE_IN_243X (1 << 2)
1030 +#define RATE_IN_343X (1 << 3) /* rates common to all 343X */
1031 +#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
1032 +#define RATE_IN_4430 (1 << 5)
1033 +
1034 +#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
1035 +
1036 +
1037 +#endif
1038 --- /dev/null
1039 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/common.h
1040 @@ -0,0 +1,83 @@
1041 +/*
1042 + * arch/arm/plat-omap/include/mach/common.h
1043 + *
1044 + * Header for code common to all OMAP machines.
1045 + *
1046 + * This program is free software; you can redistribute it and/or modify it
1047 + * under the terms of the GNU General Public License as published by the
1048 + * Free Software Foundation; either version 2 of the License, or (at your
1049 + * option) any later version.
1050 + *
1051 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1052 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1053 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1054 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1055 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1056 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1057 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1058 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1059 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1060 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1061 + *
1062 + * You should have received a copy of the GNU General Public License along
1063 + * with this program; if not, write to the Free Software Foundation, Inc.,
1064 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1065 + */
1066 +
1067 +#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
1068 +#define __ARCH_ARM_MACH_OMAP_COMMON_H
1069 +
1070 +#include <plat/i2c.h>
1071 +
1072 +struct sys_timer;
1073 +
1074 +/* used by omap-smp.c and board-4430sdp.c */
1075 +extern void __iomem *gic_cpu_base_addr;
1076 +
1077 +extern void omap_map_common_io(void);
1078 +extern struct sys_timer omap_timer;
1079 +
1080 +/* IO bases for various OMAP processors */
1081 +struct omap_globals {
1082 + u32 class; /* OMAP class to detect */
1083 + void __iomem *tap; /* Control module ID code */
1084 + void __iomem *sdrc; /* SDRAM Controller */
1085 + void __iomem *sms; /* SDRAM Memory Scheduler */
1086 + void __iomem *ctrl; /* System Control Module */
1087 + void __iomem *prm; /* Power and Reset Management */
1088 + void __iomem *cm; /* Clock Management */
1089 + void __iomem *cm2;
1090 +};
1091 +
1092 +void omap2_set_globals_242x(void);
1093 +void omap2_set_globals_243x(void);
1094 +void omap2_set_globals_343x(void);
1095 +void omap2_set_globals_443x(void);
1096 +
1097 +/* These get called from omap2_set_globals_xxxx(), do not call these */
1098 +void omap2_set_globals_tap(struct omap_globals *);
1099 +void omap2_set_globals_sdrc(struct omap_globals *);
1100 +void omap2_set_globals_control(struct omap_globals *);
1101 +void omap2_set_globals_prcm(struct omap_globals *);
1102 +
1103 +/**
1104 + * omap_test_timeout - busy-loop, testing a condition
1105 + * @cond: condition to test until it evaluates to true
1106 + * @timeout: maximum number of microseconds in the timeout
1107 + * @index: loop index (integer)
1108 + *
1109 + * Loop waiting for @cond to become true or until at least @timeout
1110 + * microseconds have passed. To use, define some integer @index in the
1111 + * calling code. After running, if @index == @timeout, then the loop has
1112 + * timed out.
1113 + */
1114 +#define omap_test_timeout(cond, timeout, index) \
1115 +({ \
1116 + for (index = 0; index < timeout; index++) { \
1117 + if (cond) \
1118 + break; \
1119 + udelay(1); \
1120 + } \
1121 +})
1122 +
1123 +#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
1124 --- /dev/null
1125 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/control.h
1126 @@ -0,0 +1,325 @@
1127 +/*
1128 + * arch/arm/plat-omap/include/mach/control.h
1129 + *
1130 + * OMAP2/3/4 System Control Module definitions
1131 + *
1132 + * Copyright (C) 2007-2009 Texas Instruments, Inc.
1133 + * Copyright (C) 2007-2008 Nokia Corporation
1134 + *
1135 + * Written by Paul Walmsley
1136 + *
1137 + * This program is free software; you can redistribute it and/or modify
1138 + * it under the terms of the GNU General Public License as published by
1139 + * the Free Software Foundation.
1140 + */
1141 +
1142 +#ifndef __ASM_ARCH_CONTROL_H
1143 +#define __ASM_ARCH_CONTROL_H
1144 +
1145 +#include <mach/io.h>
1146 +
1147 +#ifndef __ASSEMBLY__
1148 +#define OMAP242X_CTRL_REGADDR(reg) \
1149 + OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
1150 +#define OMAP243X_CTRL_REGADDR(reg) \
1151 + OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
1152 +#define OMAP343X_CTRL_REGADDR(reg) \
1153 + OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
1154 +#else
1155 +#define OMAP242X_CTRL_REGADDR(reg) \
1156 + OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
1157 +#define OMAP243X_CTRL_REGADDR(reg) \
1158 + OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
1159 +#define OMAP343X_CTRL_REGADDR(reg) \
1160 + OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
1161 +#endif /* __ASSEMBLY__ */
1162 +
1163 +/*
1164 + * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
1165 + * OMAP24XX and OMAP34XX.
1166 + */
1167 +
1168 +/* Control submodule offsets */
1169 +
1170 +#define OMAP2_CONTROL_INTERFACE 0x000
1171 +#define OMAP2_CONTROL_PADCONFS 0x030
1172 +#define OMAP2_CONTROL_GENERAL 0x270
1173 +#define OMAP343X_CONTROL_MEM_WKUP 0x600
1174 +#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
1175 +#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
1176 +
1177 +/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
1178 +
1179 +#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
1180 +
1181 +/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
1182 +#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004)
1183 +#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020)
1184 +#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024)
1185 +#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028)
1186 +#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c)
1187 +#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030)
1188 +#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034)
1189 +#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040)
1190 +#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090)
1191 +#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094)
1192 +#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
1193 +#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
1194 +
1195 +/* 242x-only CONTROL_GENERAL register offsets */
1196 +#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
1197 +#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
1198 +
1199 +/* 243x-only CONTROL_GENERAL register offsets */
1200 +/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
1201 +#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
1202 +#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
1203 +#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
1204 +#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
1205 +#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
1206 +#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230)
1207 +
1208 +/* 24xx-only CONTROL_GENERAL register offsets */
1209 +#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
1210 +#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
1211 +#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
1212 +#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
1213 +#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
1214 +#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
1215 +#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
1216 +#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
1217 +#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
1218 +#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
1219 +#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
1220 +#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
1221 +#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
1222 +#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
1223 +#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
1224 +#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
1225 +#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
1226 +#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
1227 +#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
1228 +#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
1229 +#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
1230 +#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
1231 +#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
1232 +#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
1233 +#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
1234 +#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
1235 +#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
1236 +#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
1237 +#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
1238 +#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
1239 +#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
1240 +
1241 +#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
1242 +
1243 +/* 34xx-only CONTROL_GENERAL register offsets */
1244 +#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
1245 +#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
1246 +#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c)
1247 +#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068)
1248 +#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c)
1249 +#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070)
1250 +#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074)
1251 +#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078)
1252 +#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
1253 +#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
1254 +#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0)
1255 +#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8)
1256 +#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac)
1257 +#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0)
1258 +#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4)
1259 +#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8)
1260 +#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc)
1261 +#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0)
1262 +#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4)
1263 +#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8)
1264 +#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc)
1265 +#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0)
1266 +#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4)
1267 +#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8)
1268 +#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec)
1269 +#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0)
1270 +#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
1271 +#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
1272 +#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
1273 +#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
1274 +#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
1275 +#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \
1276 + + ((i) >> 1) * 4 + (!(i) & 1) * 2)
1277 +#define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4)
1278 +#define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8)
1279 +#define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0)
1280 +#define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4)
1281 +#define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8)
1282 +#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
1283 +#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0)
1284 +#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4)
1285 +#define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8)
1286 +#define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0)
1287 +#define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4)
1288 +
1289 +
1290 +/* 34xx PADCONF register offsets */
1291 +#define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
1292 + (i)*2)
1293 +#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0)
1294 +#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1)
1295 +#define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2)
1296 +#define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3)
1297 +#define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4)
1298 +#define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5)
1299 +#define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6)
1300 +#define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7)
1301 +#define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8)
1302 +#define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9)
1303 +#define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10)
1304 +#define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11)
1305 +#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12)
1306 +#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13)
1307 +#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14)
1308 +#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15)
1309 +#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16)
1310 +#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17)
1311 +
1312 +/* 34xx GENERAL_WKUP regist offsets */
1313 +#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
1314 + 0x008 + (i))
1315 +#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
1316 +#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
1317 +#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
1318 +#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
1319 +#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
1320 +
1321 +/* 34xx D2D idle-related pins, handled by PM core */
1322 +#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
1323 +#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
1324 +
1325 +/*
1326 + * REVISIT: This list of registers is not comprehensive - there are more
1327 + * that should be added.
1328 + */
1329 +
1330 +/*
1331 + * Control module register bit defines - these should eventually go into
1332 + * their own regbits file. Some of these will be complicated, depending
1333 + * on the device type (general-purpose, emulator, test, secure, bad, other)
1334 + * and the security mode (secure, non-secure, don't care)
1335 + */
1336 +/* CONTROL_DEVCONF0 bits */
1337 +#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */
1338 +#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
1339 +#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
1340 +#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
1341 +
1342 +/* CONTROL_DEVCONF1 bits */
1343 +#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31)
1344 +#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */
1345 +#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
1346 +#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
1347 +#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */
1348 +
1349 +/* CONTROL_STATUS bits */
1350 +#define OMAP2_DEVICETYPE_MASK (0x7 << 8)
1351 +#define OMAP2_SYSBOOT_5_MASK (1 << 5)
1352 +#define OMAP2_SYSBOOT_4_MASK (1 << 4)
1353 +#define OMAP2_SYSBOOT_3_MASK (1 << 3)
1354 +#define OMAP2_SYSBOOT_2_MASK (1 << 2)
1355 +#define OMAP2_SYSBOOT_1_MASK (1 << 1)
1356 +#define OMAP2_SYSBOOT_0_MASK (1 << 0)
1357 +
1358 +/* CONTROL_PBIAS_LITE bits */
1359 +#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15)
1360 +#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11)
1361 +#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10)
1362 +#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9)
1363 +#define OMAP343X_PBIASLITEVMODE1 (1 << 8)
1364 +#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7)
1365 +#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3)
1366 +#define OMAP2_PBIASSPEEDCTRL0 (1 << 2)
1367 +#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
1368 +#define OMAP2_PBIASLITEVMODE0 (1 << 0)
1369 +
1370 +/* CONTROL_PROG_IO1 bits */
1371 +#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
1372 +
1373 +/* CONTROL_IVA2_BOOTMOD bits */
1374 +#define OMAP3_IVA2_BOOTMOD_SHIFT 0
1375 +#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
1376 +#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0)
1377 +
1378 +/* CONTROL_PADCONF_X bits */
1379 +#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
1380 +#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
1381 +
1382 +#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
1383 +#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
1384 +#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
1385 +
1386 +/*
1387 + * CONTROL OMAP STATUS register to identify OMAP3 features
1388 + */
1389 +#define OMAP3_CONTROL_OMAP_STATUS 0x044c
1390 +
1391 +#define OMAP3_SGX_SHIFT 13
1392 +#define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT)
1393 +#define FEAT_SGX_FULL 0
1394 +#define FEAT_SGX_HALF 1
1395 +#define FEAT_SGX_NONE 2
1396 +
1397 +#define OMAP3_IVA_SHIFT 12
1398 +#define OMAP3_IVA_MASK (1 << OMAP3_SGX_SHIFT)
1399 +#define FEAT_IVA 0
1400 +#define FEAT_IVA_NONE 1
1401 +
1402 +#define OMAP3_L2CACHE_SHIFT 10
1403 +#define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT)
1404 +#define FEAT_L2CACHE_NONE 0
1405 +#define FEAT_L2CACHE_64KB 1
1406 +#define FEAT_L2CACHE_128KB 2
1407 +#define FEAT_L2CACHE_256KB 3
1408 +
1409 +#define OMAP3_ISP_SHIFT 5
1410 +#define OMAP3_ISP_MASK (1<< OMAP3_ISP_SHIFT)
1411 +#define FEAT_ISP 0
1412 +#define FEAT_ISP_NONE 1
1413 +
1414 +#define OMAP3_NEON_SHIFT 4
1415 +#define OMAP3_NEON_MASK (1<< OMAP3_NEON_SHIFT)
1416 +#define FEAT_NEON 0
1417 +#define FEAT_NEON_NONE 1
1418 +
1419 +
1420 +#ifndef __ASSEMBLY__
1421 +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
1422 + defined(CONFIG_ARCH_OMAP4)
1423 +extern void __iomem *omap_ctrl_base_get(void);
1424 +extern u8 omap_ctrl_readb(u16 offset);
1425 +extern u16 omap_ctrl_readw(u16 offset);
1426 +extern u32 omap_ctrl_readl(u16 offset);
1427 +extern void omap_ctrl_writeb(u8 val, u16 offset);
1428 +extern void omap_ctrl_writew(u16 val, u16 offset);
1429 +extern void omap_ctrl_writel(u32 val, u16 offset);
1430 +
1431 +extern void omap3_save_scratchpad_contents(void);
1432 +extern void omap3_clear_scratchpad_contents(void);
1433 +extern u32 *get_restore_pointer(void);
1434 +extern u32 *get_es3_restore_pointer(void);
1435 +extern u32 omap3_arm_context[128];
1436 +extern void omap3_control_save_context(void);
1437 +extern void omap3_control_restore_context(void);
1438 +
1439 +#else
1440 +#define omap_ctrl_base_get() 0
1441 +#define omap_ctrl_readb(x) 0
1442 +#define omap_ctrl_readw(x) 0
1443 +#define omap_ctrl_readl(x) 0
1444 +#define omap_ctrl_writeb(x, y) WARN_ON(1)
1445 +#define omap_ctrl_writew(x, y) WARN_ON(1)
1446 +#define omap_ctrl_writel(x, y) WARN_ON(1)
1447 +#endif
1448 +#endif /* __ASSEMBLY__ */
1449 +
1450 +#endif /* __ASM_ARCH_CONTROL_H */
1451 +
1452 --- /dev/null
1453 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/cpu.h
1454 @@ -0,0 +1,516 @@
1455 +/*
1456 + * arch/arm/plat-omap/include/mach/cpu.h
1457 + *
1458 + * OMAP cpu type detection
1459 + *
1460 + * Copyright (C) 2004, 2008 Nokia Corporation
1461 + *
1462 + * Copyright (C) 2009 Texas Instruments.
1463 + *
1464 + * Written by Tony Lindgren <tony.lindgren@nokia.com>
1465 + *
1466 + * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
1467 + *
1468 + * This program is free software; you can redistribute it and/or modify
1469 + * it under the terms of the GNU General Public License as published by
1470 + * the Free Software Foundation; either version 2 of the License, or
1471 + * (at your option) any later version.
1472 + *
1473 + * This program is distributed in the hope that it will be useful,
1474 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1475 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1476 + * GNU General Public License for more details.
1477 + *
1478 + * You should have received a copy of the GNU General Public License
1479 + * along with this program; if not, write to the Free Software
1480 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1481 + *
1482 + */
1483 +
1484 +#ifndef __ASM_ARCH_OMAP_CPU_H
1485 +#define __ASM_ARCH_OMAP_CPU_H
1486 +
1487 +#include <linux/bitops.h>
1488 +
1489 +/*
1490 + * Omap device type i.e. EMU/HS/TST/GP/BAD
1491 + */
1492 +#define OMAP2_DEVICE_TYPE_TEST 0
1493 +#define OMAP2_DEVICE_TYPE_EMU 1
1494 +#define OMAP2_DEVICE_TYPE_SEC 2
1495 +#define OMAP2_DEVICE_TYPE_GP 3
1496 +#define OMAP2_DEVICE_TYPE_BAD 4
1497 +
1498 +int omap_type(void);
1499 +
1500 +struct omap_chip_id {
1501 + u8 oc;
1502 + u8 type;
1503 +};
1504 +
1505 +#define OMAP_CHIP_INIT(x) { .oc = x }
1506 +
1507 +/*
1508 + * omap_rev bits:
1509 + * CPU id bits (0730, 1510, 1710, 2422...) [31:16]
1510 + * CPU revision (See _REV_ defined in cpu.h) [15:08]
1511 + * CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00]
1512 + */
1513 +unsigned int omap_rev(void);
1514 +
1515 +/*
1516 + * Define CPU revision bits
1517 + *
1518 + * Verbose meaning of the revision bits may be different for a silicon
1519 + * family. This difference can be handled separately.
1520 + */
1521 +#define OMAP_REVBITS_00 0x00
1522 +#define OMAP_REVBITS_10 0x10
1523 +#define OMAP_REVBITS_20 0x20
1524 +#define OMAP_REVBITS_30 0x30
1525 +#define OMAP_REVBITS_40 0x40
1526 +
1527 +/*
1528 + * Get the CPU revision for OMAP devices
1529 + */
1530 +#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
1531 +
1532 +/*
1533 + * Test if multicore OMAP support is needed
1534 + */
1535 +#undef MULTI_OMAP1
1536 +#undef MULTI_OMAP2
1537 +#undef OMAP_NAME
1538 +
1539 +#ifdef CONFIG_ARCH_OMAP730
1540 +# ifdef OMAP_NAME
1541 +# undef MULTI_OMAP1
1542 +# define MULTI_OMAP1
1543 +# else
1544 +# define OMAP_NAME omap730
1545 +# endif
1546 +#endif
1547 +#ifdef CONFIG_ARCH_OMAP850
1548 +# ifdef OMAP_NAME
1549 +# undef MULTI_OMAP1
1550 +# define MULTI_OMAP1
1551 +# else
1552 +# define OMAP_NAME omap850
1553 +# endif
1554 +#endif
1555 +#ifdef CONFIG_ARCH_OMAP15XX
1556 +# ifdef OMAP_NAME
1557 +# undef MULTI_OMAP1
1558 +# define MULTI_OMAP1
1559 +# else
1560 +# define OMAP_NAME omap1510
1561 +# endif
1562 +#endif
1563 +#ifdef CONFIG_ARCH_OMAP16XX
1564 +# ifdef OMAP_NAME
1565 +# undef MULTI_OMAP1
1566 +# define MULTI_OMAP1
1567 +# else
1568 +# define OMAP_NAME omap16xx
1569 +# endif
1570 +#endif
1571 +#if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX))
1572 +# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
1573 +# error "OMAP1 and OMAP2 can't be selected at the same time"
1574 +# endif
1575 +#endif
1576 +#ifdef CONFIG_ARCH_OMAP2420
1577 +# ifdef OMAP_NAME
1578 +# undef MULTI_OMAP2
1579 +# define MULTI_OMAP2
1580 +# else
1581 +# define OMAP_NAME omap2420
1582 +# endif
1583 +#endif
1584 +#ifdef CONFIG_ARCH_OMAP2430
1585 +# ifdef OMAP_NAME
1586 +# undef MULTI_OMAP2
1587 +# define MULTI_OMAP2
1588 +# else
1589 +# define OMAP_NAME omap2430
1590 +# endif
1591 +#endif
1592 +#ifdef CONFIG_ARCH_OMAP3430
1593 +# ifdef OMAP_NAME
1594 +# undef MULTI_OMAP2
1595 +# define MULTI_OMAP2
1596 +# else
1597 +# define OMAP_NAME omap3430
1598 +# endif
1599 +#endif
1600 +
1601 +/*
1602 + * Macros to group OMAP into cpu classes.
1603 + * These can be used in most places.
1604 + * cpu_is_omap7xx(): True for OMAP730, OMAP850
1605 + * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310
1606 + * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710
1607 + * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
1608 + * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
1609 + * cpu_is_omap243x(): True for OMAP2430
1610 + * cpu_is_omap343x(): True for OMAP3430
1611 + */
1612 +#define GET_OMAP_CLASS (omap_rev() & 0xff)
1613 +
1614 +#define IS_OMAP_CLASS(class, id) \
1615 +static inline int is_omap ##class (void) \
1616 +{ \
1617 + return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
1618 +}
1619 +
1620 +#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
1621 +
1622 +#define IS_OMAP_SUBCLASS(subclass, id) \
1623 +static inline int is_omap ##subclass (void) \
1624 +{ \
1625 + return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
1626 +}
1627 +
1628 +IS_OMAP_CLASS(7xx, 0x07)
1629 +IS_OMAP_CLASS(15xx, 0x15)
1630 +IS_OMAP_CLASS(16xx, 0x16)
1631 +IS_OMAP_CLASS(24xx, 0x24)
1632 +IS_OMAP_CLASS(34xx, 0x34)
1633 +IS_OMAP_CLASS(44xx, 0x44)
1634 +
1635 +IS_OMAP_SUBCLASS(242x, 0x242)
1636 +IS_OMAP_SUBCLASS(243x, 0x243)
1637 +IS_OMAP_SUBCLASS(343x, 0x343)
1638 +IS_OMAP_SUBCLASS(363x, 0x363)
1639 +IS_OMAP_SUBCLASS(443x, 0x443)
1640 +
1641 +#define cpu_is_omap7xx() 0
1642 +#define cpu_is_omap15xx() 0
1643 +#define cpu_is_omap16xx() 0
1644 +#define cpu_is_omap24xx() 0
1645 +#define cpu_is_omap242x() 0
1646 +#define cpu_is_omap243x() 0
1647 +#define cpu_is_omap34xx() 0
1648 +#define cpu_is_omap343x() 0
1649 +#define cpu_is_omap44xx() 0
1650 +#define cpu_is_omap443x() 0
1651 +
1652 +#if defined(MULTI_OMAP1)
1653 +# if defined(CONFIG_ARCH_OMAP730)
1654 +# undef cpu_is_omap7xx
1655 +# define cpu_is_omap7xx() is_omap7xx()
1656 +# endif
1657 +# if defined(CONFIG_ARCH_OMAP850)
1658 +# undef cpu_is_omap7xx
1659 +# define cpu_is_omap7xx() is_omap7xx()
1660 +# endif
1661 +# if defined(CONFIG_ARCH_OMAP15XX)
1662 +# undef cpu_is_omap15xx
1663 +# define cpu_is_omap15xx() is_omap15xx()
1664 +# endif
1665 +# if defined(CONFIG_ARCH_OMAP16XX)
1666 +# undef cpu_is_omap16xx
1667 +# define cpu_is_omap16xx() is_omap16xx()
1668 +# endif
1669 +#else
1670 +# if defined(CONFIG_ARCH_OMAP730)
1671 +# undef cpu_is_omap7xx
1672 +# define cpu_is_omap7xx() 1
1673 +# endif
1674 +# if defined(CONFIG_ARCH_OMAP850)
1675 +# undef cpu_is_omap7xx
1676 +# define cpu_is_omap7xx() 1
1677 +# endif
1678 +# if defined(CONFIG_ARCH_OMAP15XX)
1679 +# undef cpu_is_omap15xx
1680 +# define cpu_is_omap15xx() 1
1681 +# endif
1682 +# if defined(CONFIG_ARCH_OMAP16XX)
1683 +# undef cpu_is_omap16xx
1684 +# define cpu_is_omap16xx() 1
1685 +# endif
1686 +#endif
1687 +
1688 +#if defined(MULTI_OMAP2)
1689 +# if defined(CONFIG_ARCH_OMAP24XX)
1690 +# undef cpu_is_omap24xx
1691 +# undef cpu_is_omap242x
1692 +# undef cpu_is_omap243x
1693 +# define cpu_is_omap24xx() is_omap24xx()
1694 +# define cpu_is_omap242x() is_omap242x()
1695 +# define cpu_is_omap243x() is_omap243x()
1696 +# endif
1697 +# if defined(CONFIG_ARCH_OMAP34XX)
1698 +# undef cpu_is_omap34xx
1699 +# undef cpu_is_omap343x
1700 +# define cpu_is_omap34xx() is_omap34xx()
1701 +# define cpu_is_omap343x() is_omap343x()
1702 +# endif
1703 +#else
1704 +# if defined(CONFIG_ARCH_OMAP24XX)
1705 +# undef cpu_is_omap24xx
1706 +# define cpu_is_omap24xx() 1
1707 +# endif
1708 +# if defined(CONFIG_ARCH_OMAP2420)
1709 +# undef cpu_is_omap242x
1710 +# define cpu_is_omap242x() 1
1711 +# endif
1712 +# if defined(CONFIG_ARCH_OMAP2430)
1713 +# undef cpu_is_omap243x
1714 +# define cpu_is_omap243x() 1
1715 +# endif
1716 +# if defined(CONFIG_ARCH_OMAP34XX)
1717 +# undef cpu_is_omap34xx
1718 +# define cpu_is_omap34xx() 1
1719 +# endif
1720 +# if defined(CONFIG_ARCH_OMAP3430)
1721 +# undef cpu_is_omap343x
1722 +# define cpu_is_omap343x() 1
1723 +# endif
1724 +#endif
1725 +
1726 +/*
1727 + * Macros to detect individual cpu types.
1728 + * These are only rarely needed.
1729 + * cpu_is_omap330(): True for OMAP330
1730 + * cpu_is_omap730(): True for OMAP730
1731 + * cpu_is_omap850(): True for OMAP850
1732 + * cpu_is_omap1510(): True for OMAP1510
1733 + * cpu_is_omap1610(): True for OMAP1610
1734 + * cpu_is_omap1611(): True for OMAP1611
1735 + * cpu_is_omap5912(): True for OMAP5912
1736 + * cpu_is_omap1621(): True for OMAP1621
1737 + * cpu_is_omap1710(): True for OMAP1710
1738 + * cpu_is_omap2420(): True for OMAP2420
1739 + * cpu_is_omap2422(): True for OMAP2422
1740 + * cpu_is_omap2423(): True for OMAP2423
1741 + * cpu_is_omap2430(): True for OMAP2430
1742 + * cpu_is_omap3430(): True for OMAP3430
1743 + * cpu_is_omap3505(): True for OMAP3505
1744 + * cpu_is_omap3517(): True for OMAP3517
1745 + */
1746 +#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
1747 +
1748 +#define IS_OMAP_TYPE(type, id) \
1749 +static inline int is_omap ##type (void) \
1750 +{ \
1751 + return (GET_OMAP_TYPE == (id)) ? 1 : 0; \
1752 +}
1753 +
1754 +IS_OMAP_TYPE(310, 0x0310)
1755 +IS_OMAP_TYPE(730, 0x0730)
1756 +IS_OMAP_TYPE(850, 0x0850)
1757 +IS_OMAP_TYPE(1510, 0x1510)
1758 +IS_OMAP_TYPE(1610, 0x1610)
1759 +IS_OMAP_TYPE(1611, 0x1611)
1760 +IS_OMAP_TYPE(5912, 0x1611)
1761 +IS_OMAP_TYPE(1621, 0x1621)
1762 +IS_OMAP_TYPE(1710, 0x1710)
1763 +IS_OMAP_TYPE(2420, 0x2420)
1764 +IS_OMAP_TYPE(2422, 0x2422)
1765 +IS_OMAP_TYPE(2423, 0x2423)
1766 +IS_OMAP_TYPE(2430, 0x2430)
1767 +IS_OMAP_TYPE(3430, 0x3430)
1768 +IS_OMAP_TYPE(3505, 0x3505)
1769 +IS_OMAP_TYPE(3517, 0x3517)
1770 +
1771 +#define cpu_is_omap310() 0
1772 +#define cpu_is_omap730() 0
1773 +#define cpu_is_omap850() 0
1774 +#define cpu_is_omap1510() 0
1775 +#define cpu_is_omap1610() 0
1776 +#define cpu_is_omap5912() 0
1777 +#define cpu_is_omap1611() 0
1778 +#define cpu_is_omap1621() 0
1779 +#define cpu_is_omap1710() 0
1780 +#define cpu_is_omap2420() 0
1781 +#define cpu_is_omap2422() 0
1782 +#define cpu_is_omap2423() 0
1783 +#define cpu_is_omap2430() 0
1784 +#define cpu_is_omap3503() 0
1785 +#define cpu_is_omap3515() 0
1786 +#define cpu_is_omap3525() 0
1787 +#define cpu_is_omap3530() 0
1788 +#define cpu_is_omap3505() 0
1789 +#define cpu_is_omap3517() 0
1790 +#define cpu_is_omap3430() 0
1791 +#define cpu_is_omap3630() 0
1792 +
1793 +/*
1794 + * Whether we have MULTI_OMAP1 or not, we still need to distinguish
1795 + * between 730 vs 850, 330 vs. 1510 and 1611B/5912 vs. 1710.
1796 + */
1797 +
1798 +#if defined(CONFIG_ARCH_OMAP730)
1799 +# undef cpu_is_omap730
1800 +# define cpu_is_omap730() is_omap730()
1801 +#endif
1802 +
1803 +#if defined(CONFIG_ARCH_OMAP850)
1804 +# undef cpu_is_omap850
1805 +# define cpu_is_omap850() is_omap850()
1806 +#endif
1807 +
1808 +#if defined(CONFIG_ARCH_OMAP15XX)
1809 +# undef cpu_is_omap310
1810 +# undef cpu_is_omap1510
1811 +# define cpu_is_omap310() is_omap310()
1812 +# define cpu_is_omap1510() is_omap1510()
1813 +#endif
1814 +
1815 +#if defined(CONFIG_ARCH_OMAP16XX)
1816 +# undef cpu_is_omap1610
1817 +# undef cpu_is_omap1611
1818 +# undef cpu_is_omap5912
1819 +# undef cpu_is_omap1621
1820 +# undef cpu_is_omap1710
1821 +# define cpu_is_omap1610() is_omap1610()
1822 +# define cpu_is_omap1611() is_omap1611()
1823 +# define cpu_is_omap5912() is_omap5912()
1824 +# define cpu_is_omap1621() is_omap1621()
1825 +# define cpu_is_omap1710() is_omap1710()
1826 +#endif
1827 +
1828 +#if defined(CONFIG_ARCH_OMAP24XX)
1829 +# undef cpu_is_omap2420
1830 +# undef cpu_is_omap2422
1831 +# undef cpu_is_omap2423
1832 +# undef cpu_is_omap2430
1833 +# define cpu_is_omap2420() is_omap2420()
1834 +# define cpu_is_omap2422() is_omap2422()
1835 +# define cpu_is_omap2423() is_omap2423()
1836 +# define cpu_is_omap2430() is_omap2430()
1837 +#endif
1838 +
1839 +#if defined(CONFIG_ARCH_OMAP34XX)
1840 +# undef cpu_is_omap3430
1841 +# undef cpu_is_omap3503
1842 +# undef cpu_is_omap3515
1843 +# undef cpu_is_omap3525
1844 +# undef cpu_is_omap3530
1845 +# undef cpu_is_omap3505
1846 +# undef cpu_is_omap3517
1847 +# define cpu_is_omap3430() is_omap3430()
1848 +# define cpu_is_omap3503() (cpu_is_omap3430() && \
1849 + (!omap3_has_iva()) && \
1850 + (!omap3_has_sgx()))
1851 +# define cpu_is_omap3515() (cpu_is_omap3430() && \
1852 + (!omap3_has_iva()) && \
1853 + (omap3_has_sgx()))
1854 +# define cpu_is_omap3525() (cpu_is_omap3430() && \
1855 + (!omap3_has_sgx()) && \
1856 + (omap3_has_iva()))
1857 +# define cpu_is_omap3530() (cpu_is_omap3430())
1858 +# define cpu_is_omap3505() is_omap3505()
1859 +# define cpu_is_omap3517() is_omap3517()
1860 +# undef cpu_is_omap3630
1861 +# define cpu_is_omap3630() is_omap363x()
1862 +#endif
1863 +
1864 +# if defined(CONFIG_ARCH_OMAP4)
1865 +# undef cpu_is_omap44xx
1866 +# undef cpu_is_omap443x
1867 +# define cpu_is_omap44xx() is_omap44xx()
1868 +# define cpu_is_omap443x() is_omap443x()
1869 +# endif
1870 +
1871 +/* Macros to detect if we have OMAP1 or OMAP2 */
1872 +#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \
1873 + cpu_is_omap16xx())
1874 +#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
1875 + cpu_is_omap44xx())
1876 +
1877 +/* Various silicon revisions for omap2 */
1878 +#define OMAP242X_CLASS 0x24200024
1879 +#define OMAP2420_REV_ES1_0 0x24200024
1880 +#define OMAP2420_REV_ES2_0 0x24201024
1881 +
1882 +#define OMAP243X_CLASS 0x24300024
1883 +#define OMAP2430_REV_ES1_0 0x24300024
1884 +
1885 +#define OMAP343X_CLASS 0x34300034
1886 +#define OMAP3430_REV_ES1_0 0x34300034
1887 +#define OMAP3430_REV_ES2_0 0x34301034
1888 +#define OMAP3430_REV_ES2_1 0x34302034
1889 +#define OMAP3430_REV_ES3_0 0x34303034
1890 +#define OMAP3430_REV_ES3_1 0x34304034
1891 +
1892 +#define OMAP3630_REV_ES1_0 0x36300034
1893 +
1894 +#define OMAP35XX_CLASS 0x35000034
1895 +#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
1896 +#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8))
1897 +#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
1898 +#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
1899 +#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
1900 +#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
1901 +
1902 +#define OMAP443X_CLASS 0x44300044
1903 +#define OMAP4430_REV_ES1_0 0x44300044
1904 +
1905 +/*
1906 + * omap_chip bits
1907 + *
1908 + * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
1909 + * valid on all chips of that type. CHIP_IS_OMAP3430ES{1,2} indicates
1910 + * something that is only valid on that particular ES revision.
1911 + *
1912 + * These bits may be ORed together to indicate structures that are
1913 + * available on multiple chip types.
1914 + *
1915 + * To test whether a particular structure matches the current OMAP chip type,
1916 + * use omap_chip_is().
1917 + *
1918 + */
1919 +#define CHIP_IS_OMAP2420 (1 << 0)
1920 +#define CHIP_IS_OMAP2430 (1 << 1)
1921 +#define CHIP_IS_OMAP3430 (1 << 2)
1922 +#define CHIP_IS_OMAP3430ES1 (1 << 3)
1923 +#define CHIP_IS_OMAP3430ES2 (1 << 4)
1924 +#define CHIP_IS_OMAP3430ES3_0 (1 << 5)
1925 +#define CHIP_IS_OMAP3430ES3_1 (1 << 6)
1926 +#define CHIP_IS_OMAP3630ES1 (1 << 7)
1927 +
1928 +#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
1929 +
1930 +/*
1931 + * "GE" here represents "greater than or equal to" in terms of ES
1932 + * levels. So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
1933 + * chips at ES2 and beyond, but not, for example, any OMAP lines after
1934 + * OMAP3.
1935 + */
1936 +#define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \
1937 + CHIP_IS_OMAP3430ES3_0 | \
1938 + CHIP_IS_OMAP3430ES3_1 | \
1939 + CHIP_IS_OMAP3630ES1)
1940 +#define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \
1941 + CHIP_IS_OMAP3630ES1)
1942 +
1943 +
1944 +int omap_chip_is(struct omap_chip_id oci);
1945 +void omap2_check_revision(void);
1946 +
1947 +/*
1948 + * Runtime detection of OMAP3 features
1949 + */
1950 +extern u32 omap3_features;
1951 +
1952 +#define OMAP3_HAS_L2CACHE BIT(0)
1953 +#define OMAP3_HAS_IVA BIT(1)
1954 +#define OMAP3_HAS_SGX BIT(2)
1955 +#define OMAP3_HAS_NEON BIT(3)
1956 +#define OMAP3_HAS_ISP BIT(4)
1957 +
1958 +#define OMAP3_HAS_FEATURE(feat,flag) \
1959 +static inline unsigned int omap3_has_ ##feat(void) \
1960 +{ \
1961 + return (omap3_features & OMAP3_HAS_ ##flag); \
1962 +} \
1963 +
1964 +OMAP3_HAS_FEATURE(l2cache, L2CACHE)
1965 +OMAP3_HAS_FEATURE(sgx, SGX)
1966 +OMAP3_HAS_FEATURE(iva, IVA)
1967 +OMAP3_HAS_FEATURE(neon, NEON)
1968 +OMAP3_HAS_FEATURE(isp, ISP)
1969 +
1970 +#endif
1971 --- /dev/null
1972 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/display.h
1973 @@ -0,0 +1,575 @@
1974 +/*
1975 + * linux/include/asm-arm/arch-omap/display.h
1976 + *
1977 + * Copyright (C) 2008 Nokia Corporation
1978 + * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
1979 + *
1980 + * This program is free software; you can redistribute it and/or modify it
1981 + * under the terms of the GNU General Public License version 2 as published by
1982 + * the Free Software Foundation.
1983 + *
1984 + * This program is distributed in the hope that it will be useful, but WITHOUT
1985 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1986 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1987 + * more details.
1988 + *
1989 + * You should have received a copy of the GNU General Public License along with
1990 + * this program. If not, see <http://www.gnu.org/licenses/>.
1991 + */
1992 +
1993 +#ifndef __ASM_ARCH_OMAP_DISPLAY_H
1994 +#define __ASM_ARCH_OMAP_DISPLAY_H
1995 +
1996 +#include <linux/list.h>
1997 +#include <linux/kobject.h>
1998 +#include <linux/device.h>
1999 +#include <asm/atomic.h>
2000 +
2001 +#define DISPC_IRQ_FRAMEDONE (1 << 0)
2002 +#define DISPC_IRQ_VSYNC (1 << 1)
2003 +#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
2004 +#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
2005 +#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
2006 +#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
2007 +#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
2008 +#define DISPC_IRQ_GFX_END_WIN (1 << 7)
2009 +#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
2010 +#define DISPC_IRQ_OCP_ERR (1 << 9)
2011 +#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
2012 +#define DISPC_IRQ_VID1_END_WIN (1 << 11)
2013 +#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
2014 +#define DISPC_IRQ_VID2_END_WIN (1 << 13)
2015 +#define DISPC_IRQ_SYNC_LOST (1 << 14)
2016 +#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
2017 +#define DISPC_IRQ_WAKEUP (1 << 16)
2018 +
2019 +struct omap_dss_device;
2020 +struct omap_overlay_manager;
2021 +
2022 +enum omap_display_type {
2023 + OMAP_DISPLAY_TYPE_NONE = 0,
2024 + OMAP_DISPLAY_TYPE_DPI = 1 << 0,
2025 + OMAP_DISPLAY_TYPE_DBI = 1 << 1,
2026 + OMAP_DISPLAY_TYPE_SDI = 1 << 2,
2027 + OMAP_DISPLAY_TYPE_DSI = 1 << 3,
2028 + OMAP_DISPLAY_TYPE_VENC = 1 << 4,
2029 +};
2030 +
2031 +enum omap_plane {
2032 + OMAP_DSS_GFX = 0,
2033 + OMAP_DSS_VIDEO1 = 1,
2034 + OMAP_DSS_VIDEO2 = 2
2035 +};
2036 +
2037 +enum omap_channel {
2038 + OMAP_DSS_CHANNEL_LCD = 0,
2039 + OMAP_DSS_CHANNEL_DIGIT = 1,
2040 +};
2041 +
2042 +enum omap_color_mode {
2043 + OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
2044 + OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
2045 + OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
2046 + OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
2047 + OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
2048 + OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
2049 + OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
2050 + OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
2051 + OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
2052 + OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
2053 + OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
2054 + OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
2055 + OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
2056 + OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
2057 +
2058 + OMAP_DSS_COLOR_GFX_OMAP2 =
2059 + OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
2060 + OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
2061 + OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
2062 + OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
2063 +
2064 + OMAP_DSS_COLOR_VID_OMAP2 =
2065 + OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
2066 + OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
2067 + OMAP_DSS_COLOR_UYVY,
2068 +
2069 + OMAP_DSS_COLOR_GFX_OMAP3 =
2070 + OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
2071 + OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
2072 + OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
2073 + OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
2074 + OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
2075 + OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
2076 +
2077 + OMAP_DSS_COLOR_VID1_OMAP3 =
2078 + OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
2079 + OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
2080 + OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
2081 +
2082 + OMAP_DSS_COLOR_VID2_OMAP3 =
2083 + OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
2084 + OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
2085 + OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
2086 + OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
2087 + OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
2088 +};
2089 +
2090 +enum omap_lcd_display_type {
2091 + OMAP_DSS_LCD_DISPLAY_STN,
2092 + OMAP_DSS_LCD_DISPLAY_TFT,
2093 +};
2094 +
2095 +enum omap_dss_load_mode {
2096 + OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
2097 + OMAP_DSS_LOAD_CLUT_ONLY = 1,
2098 + OMAP_DSS_LOAD_FRAME_ONLY = 2,
2099 + OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
2100 +};
2101 +
2102 +enum omap_dss_trans_key_type {
2103 + OMAP_DSS_COLOR_KEY_GFX_DST = 0,
2104 + OMAP_DSS_COLOR_KEY_VID_SRC = 1,
2105 +};
2106 +
2107 +enum omap_rfbi_te_mode {
2108 + OMAP_DSS_RFBI_TE_MODE_1 = 1,
2109 + OMAP_DSS_RFBI_TE_MODE_2 = 2,
2110 +};
2111 +
2112 +enum omap_panel_config {
2113 + OMAP_DSS_LCD_IVS = 1<<0,
2114 + OMAP_DSS_LCD_IHS = 1<<1,
2115 + OMAP_DSS_LCD_IPC = 1<<2,
2116 + OMAP_DSS_LCD_IEO = 1<<3,
2117 + OMAP_DSS_LCD_RF = 1<<4,
2118 + OMAP_DSS_LCD_ONOFF = 1<<5,
2119 +
2120 + OMAP_DSS_LCD_TFT = 1<<20,
2121 +};
2122 +
2123 +enum omap_dss_venc_type {
2124 + OMAP_DSS_VENC_TYPE_COMPOSITE,
2125 + OMAP_DSS_VENC_TYPE_SVIDEO,
2126 +};
2127 +
2128 +enum omap_display_caps {
2129 + OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
2130 + OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
2131 +};
2132 +
2133 +enum omap_dss_update_mode {
2134 + OMAP_DSS_UPDATE_DISABLED = 0,
2135 + OMAP_DSS_UPDATE_AUTO,
2136 + OMAP_DSS_UPDATE_MANUAL,
2137 +};
2138 +
2139 +enum omap_dss_display_state {
2140 + OMAP_DSS_DISPLAY_DISABLED = 0,
2141 + OMAP_DSS_DISPLAY_ACTIVE,
2142 + OMAP_DSS_DISPLAY_SUSPENDED,
2143 +};
2144 +
2145 +/* XXX perhaps this should be removed */
2146 +enum omap_dss_overlay_managers {
2147 + OMAP_DSS_OVL_MGR_LCD,
2148 + OMAP_DSS_OVL_MGR_TV,
2149 +};
2150 +
2151 +enum omap_dss_rotation_type {
2152 + OMAP_DSS_ROT_DMA = 0,
2153 + OMAP_DSS_ROT_VRFB = 1,
2154 +};
2155 +
2156 +/* clockwise rotation angle */
2157 +enum omap_dss_rotation_angle {
2158 + OMAP_DSS_ROT_0 = 0,
2159 + OMAP_DSS_ROT_90 = 1,
2160 + OMAP_DSS_ROT_180 = 2,
2161 + OMAP_DSS_ROT_270 = 3,
2162 +};
2163 +
2164 +enum omap_overlay_caps {
2165 + OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
2166 + OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
2167 +};
2168 +
2169 +enum omap_overlay_manager_caps {
2170 + OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
2171 +};
2172 +
2173 +/* RFBI */
2174 +
2175 +struct rfbi_timings {
2176 + int cs_on_time;
2177 + int cs_off_time;
2178 + int we_on_time;
2179 + int we_off_time;
2180 + int re_on_time;
2181 + int re_off_time;
2182 + int we_cycle_time;
2183 + int re_cycle_time;
2184 + int cs_pulse_width;
2185 + int access_time;
2186 +
2187 + int clk_div;
2188 +
2189 + u32 tim[5]; /* set by rfbi_convert_timings() */
2190 +
2191 + int converted;
2192 +};
2193 +
2194 +void omap_rfbi_write_command(const void *buf, u32 len);
2195 +void omap_rfbi_read_data(void *buf, u32 len);
2196 +void omap_rfbi_write_data(const void *buf, u32 len);
2197 +void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
2198 + u16 x, u16 y,
2199 + u16 w, u16 h);
2200 +int omap_rfbi_enable_te(bool enable, unsigned line);
2201 +int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
2202 + unsigned hs_pulse_time, unsigned vs_pulse_time,
2203 + int hs_pol_inv, int vs_pol_inv, int extif_div);
2204 +
2205 +/* DSI */
2206 +void dsi_bus_lock(void);
2207 +void dsi_bus_unlock(void);
2208 +int dsi_vc_dcs_write(int channel, u8 *data, int len);
2209 +int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
2210 +int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
2211 +int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
2212 +int dsi_vc_send_null(int channel);
2213 +int dsi_vc_send_bta_sync(int channel);
2214 +
2215 +/* Board specific data */
2216 +struct omap_dss_board_info {
2217 + int (*get_last_off_on_transaction_id)(struct device *dev);
2218 + int num_devices;
2219 + struct omap_dss_device **devices;
2220 + struct omap_dss_device *default_device;
2221 +};
2222 +
2223 +struct omap_video_timings {
2224 + /* Unit: pixels */
2225 + u16 x_res;
2226 + /* Unit: pixels */
2227 + u16 y_res;
2228 + /* Unit: KHz */
2229 + u32 pixel_clock;
2230 + /* Unit: pixel clocks */
2231 + u16 hsw; /* Horizontal synchronization pulse width */
2232 + /* Unit: pixel clocks */
2233 + u16 hfp; /* Horizontal front porch */
2234 + /* Unit: pixel clocks */
2235 + u16 hbp; /* Horizontal back porch */
2236 + /* Unit: line clocks */
2237 + u16 vsw; /* Vertical synchronization pulse width */
2238 + /* Unit: line clocks */
2239 + u16 vfp; /* Vertical front porch */
2240 + /* Unit: line clocks */
2241 + u16 vbp; /* Vertical back porch */
2242 +};
2243 +
2244 +#ifdef CONFIG_OMAP2_DSS_VENC
2245 +/* Hardcoded timings for tv modes. Venc only uses these to
2246 + * identify the mode, and does not actually use the configs
2247 + * itself. However, the configs should be something that
2248 + * a normal monitor can also show */
2249 +const extern struct omap_video_timings omap_dss_pal_timings;
2250 +const extern struct omap_video_timings omap_dss_ntsc_timings;
2251 +#endif
2252 +
2253 +struct omap_overlay_info {
2254 + bool enabled;
2255 +
2256 + u32 paddr;
2257 + void __iomem *vaddr;
2258 + u16 screen_width;
2259 + u16 width;
2260 + u16 height;
2261 + enum omap_color_mode color_mode;
2262 + u8 rotation;
2263 + enum omap_dss_rotation_type rotation_type;
2264 + bool mirror;
2265 +
2266 + u16 pos_x;
2267 + u16 pos_y;
2268 + u16 out_width; /* if 0, out_width == width */
2269 + u16 out_height; /* if 0, out_height == height */
2270 + u8 global_alpha;
2271 +};
2272 +
2273 +struct omap_overlay {
2274 + struct kobject kobj;
2275 + struct list_head list;
2276 +
2277 + /* static fields */
2278 + const char *name;
2279 + int id;
2280 + enum omap_color_mode supported_modes;
2281 + enum omap_overlay_caps caps;
2282 +
2283 + /* dynamic fields */
2284 + struct omap_overlay_manager *manager;
2285 + struct omap_overlay_info info;
2286 +
2287 + /* if true, info has been changed, but not applied() yet */
2288 + bool info_dirty;
2289 +
2290 + int (*set_manager)(struct omap_overlay *ovl,
2291 + struct omap_overlay_manager *mgr);
2292 + int (*unset_manager)(struct omap_overlay *ovl);
2293 +
2294 + int (*set_overlay_info)(struct omap_overlay *ovl,
2295 + struct omap_overlay_info *info);
2296 + void (*get_overlay_info)(struct omap_overlay *ovl,
2297 + struct omap_overlay_info *info);
2298 +
2299 + int (*wait_for_go)(struct omap_overlay *ovl);
2300 +};
2301 +
2302 +struct omap_overlay_manager_info {
2303 + u32 default_color;
2304 +
2305 + enum omap_dss_trans_key_type trans_key_type;
2306 + u32 trans_key;
2307 + bool trans_enabled;
2308 +
2309 + bool alpha_enabled;
2310 +};
2311 +
2312 +struct omap_overlay_manager {
2313 + struct kobject kobj;
2314 + struct list_head list;
2315 +
2316 + /* static fields */
2317 + const char *name;
2318 + int id;
2319 + enum omap_overlay_manager_caps caps;
2320 + int num_overlays;
2321 + struct omap_overlay **overlays;
2322 + enum omap_display_type supported_displays;
2323 +
2324 + /* dynamic fields */
2325 + struct omap_dss_device *device;
2326 + struct omap_overlay_manager_info info;
2327 +
2328 + bool device_changed;
2329 + /* if true, info has been changed but not applied() yet */
2330 + bool info_dirty;
2331 +
2332 + int (*set_device)(struct omap_overlay_manager *mgr,
2333 + struct omap_dss_device *dssdev);
2334 + int (*unset_device)(struct omap_overlay_manager *mgr);
2335 +
2336 + int (*set_manager_info)(struct omap_overlay_manager *mgr,
2337 + struct omap_overlay_manager_info *info);
2338 + void (*get_manager_info)(struct omap_overlay_manager *mgr,
2339 + struct omap_overlay_manager_info *info);
2340 +
2341 + int (*apply)(struct omap_overlay_manager *mgr);
2342 + int (*wait_for_go)(struct omap_overlay_manager *mgr);
2343 +};
2344 +
2345 +struct omap_dss_device {
2346 + struct device dev;
2347 +
2348 + enum omap_display_type type;
2349 +
2350 + union {
2351 + struct {
2352 + u8 data_lines;
2353 + } dpi;
2354 +
2355 + struct {
2356 + u8 channel;
2357 + u8 data_lines;
2358 + } rfbi;
2359 +
2360 + struct {
2361 + u8 datapairs;
2362 + } sdi;
2363 +
2364 + struct {
2365 + u8 clk_lane;
2366 + u8 clk_pol;
2367 + u8 data1_lane;
2368 + u8 data1_pol;
2369 + u8 data2_lane;
2370 + u8 data2_pol;
2371 +
2372 + struct {
2373 + u16 regn;
2374 + u16 regm;
2375 + u16 regm3;
2376 + u16 regm4;
2377 +
2378 + u16 lp_clk_div;
2379 +
2380 + u16 lck_div;
2381 + u16 pck_div;
2382 + } div;
2383 +
2384 + bool ext_te;
2385 + u8 ext_te_gpio;
2386 + } dsi;
2387 +
2388 + struct {
2389 + enum omap_dss_venc_type type;
2390 + bool invert_polarity;
2391 + } venc;
2392 + } phy;
2393 +
2394 + struct {
2395 + struct omap_video_timings timings;
2396 +
2397 + int acbi; /* ac-bias pin transitions per interrupt */
2398 + /* Unit: line clocks */
2399 + int acb; /* ac-bias pin frequency */
2400 +
2401 + enum omap_panel_config config;
2402 +
2403 + u8 recommended_bpp;
2404 +
2405 + struct omap_dss_device *ctrl;
2406 + } panel;
2407 +
2408 + struct {
2409 + u8 pixel_size;
2410 + struct rfbi_timings rfbi_timings;
2411 + struct omap_dss_device *panel;
2412 + } ctrl;
2413 +
2414 + int reset_gpio;
2415 +
2416 + int max_backlight_level;
2417 +
2418 + const char *name;
2419 +
2420 + /* used to match device to driver */
2421 + const char *driver_name;
2422 +
2423 + void *data;
2424 +
2425 + struct omap_dss_driver *driver;
2426 +
2427 + /* helper variable for driver suspend/resume */
2428 + bool activate_after_resume;
2429 +
2430 + enum omap_display_caps caps;
2431 +
2432 + struct omap_overlay_manager *manager;
2433 +
2434 + enum omap_dss_display_state state;
2435 +
2436 + int (*enable)(struct omap_dss_device *dssdev);
2437 + void (*disable)(struct omap_dss_device *dssdev);
2438 +
2439 + int (*suspend)(struct omap_dss_device *dssdev);
2440 + int (*resume)(struct omap_dss_device *dssdev);
2441 +
2442 + void (*get_resolution)(struct omap_dss_device *dssdev,
2443 + u16 *xres, u16 *yres);
2444 + int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
2445 +
2446 + int (*check_timings)(struct omap_dss_device *dssdev,
2447 + struct omap_video_timings *timings);
2448 + void (*set_timings)(struct omap_dss_device *dssdev,
2449 + struct omap_video_timings *timings);
2450 + void (*get_timings)(struct omap_dss_device *dssdev,
2451 + struct omap_video_timings *timings);
2452 + int (*update)(struct omap_dss_device *dssdev,
2453 + u16 x, u16 y, u16 w, u16 h);
2454 + int (*sync)(struct omap_dss_device *dssdev);
2455 + int (*wait_vsync)(struct omap_dss_device *dssdev);
2456 +
2457 + int (*set_update_mode)(struct omap_dss_device *dssdev,
2458 + enum omap_dss_update_mode);
2459 + enum omap_dss_update_mode (*get_update_mode)
2460 + (struct omap_dss_device *dssdev);
2461 +
2462 + int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
2463 + int (*get_te)(struct omap_dss_device *dssdev);
2464 +
2465 + u8 (*get_rotate)(struct omap_dss_device *dssdev);
2466 + int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
2467 +
2468 + bool (*get_mirror)(struct omap_dss_device *dssdev);
2469 + int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
2470 +
2471 + int (*run_test)(struct omap_dss_device *dssdev, int test);
2472 + int (*memory_read)(struct omap_dss_device *dssdev,
2473 + void *buf, size_t size,
2474 + u16 x, u16 y, u16 w, u16 h);
2475 +
2476 + int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
2477 + u32 (*get_wss)(struct omap_dss_device *dssdev);
2478 +
2479 + /* platform specific */
2480 + int (*platform_enable)(struct omap_dss_device *dssdev);
2481 + void (*platform_disable)(struct omap_dss_device *dssdev);
2482 + int (*set_backlight)(struct omap_dss_device *dssdev, int level);
2483 + int (*get_backlight)(struct omap_dss_device *dssdev);
2484 +};
2485 +
2486 +struct omap_dss_driver {
2487 + struct device_driver driver;
2488 +
2489 + int (*probe)(struct omap_dss_device *);
2490 + void (*remove)(struct omap_dss_device *);
2491 +
2492 + int (*enable)(struct omap_dss_device *display);
2493 + void (*disable)(struct omap_dss_device *display);
2494 + int (*suspend)(struct omap_dss_device *display);
2495 + int (*resume)(struct omap_dss_device *display);
2496 + int (*run_test)(struct omap_dss_device *display, int test);
2497 +
2498 + void (*setup_update)(struct omap_dss_device *dssdev,
2499 + u16 x, u16 y, u16 w, u16 h);
2500 +
2501 + int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
2502 + int (*wait_for_te)(struct omap_dss_device *dssdev);
2503 +
2504 + u8 (*get_rotate)(struct omap_dss_device *dssdev);
2505 + int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
2506 +
2507 + bool (*get_mirror)(struct omap_dss_device *dssdev);
2508 + int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
2509 +
2510 + int (*memory_read)(struct omap_dss_device *dssdev,
2511 + void *buf, size_t size,
2512 + u16 x, u16 y, u16 w, u16 h);
2513 +};
2514 +
2515 +int omap_dss_register_driver(struct omap_dss_driver *);
2516 +void omap_dss_unregister_driver(struct omap_dss_driver *);
2517 +
2518 +int omap_dss_register_device(struct omap_dss_device *);
2519 +void omap_dss_unregister_device(struct omap_dss_device *);
2520 +
2521 +void omap_dss_get_device(struct omap_dss_device *dssdev);
2522 +void omap_dss_put_device(struct omap_dss_device *dssdev);
2523 +#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
2524 +struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
2525 +struct omap_dss_device *omap_dss_find_device(void *data,
2526 + int (*match)(struct omap_dss_device *dssdev, void *data));
2527 +
2528 +int omap_dss_start_device(struct omap_dss_device *dssdev);
2529 +void omap_dss_stop_device(struct omap_dss_device *dssdev);
2530 +
2531 +int omap_dss_get_num_overlay_managers(void);
2532 +struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
2533 +
2534 +int omap_dss_get_num_overlays(void);
2535 +struct omap_overlay *omap_dss_get_overlay(int num);
2536 +
2537 +typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
2538 +int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
2539 +int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
2540 +
2541 +int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
2542 +int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2543 + unsigned long timeout);
2544 +
2545 +#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
2546 +#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
2547 +
2548 +#endif
2549 --- /dev/null
2550 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/dma.h
2551 @@ -0,0 +1,640 @@
2552 +/*
2553 + * arch/arm/plat-omap/include/mach/dma.h
2554 + *
2555 + * Copyright (C) 2003 Nokia Corporation
2556 + * Author: Juha Yrjölä <juha.yrjola@nokia.com>
2557 + *
2558 + * This program is free software; you can redistribute it and/or modify
2559 + * it under the terms of the GNU General Public License as published by
2560 + * the Free Software Foundation; either version 2 of the License, or
2561 + * (at your option) any later version.
2562 + *
2563 + * This program is distributed in the hope that it will be useful,
2564 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2565 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2566 + * GNU General Public License for more details.
2567 + *
2568 + * You should have received a copy of the GNU General Public License
2569 + * along with this program; if not, write to the Free Software
2570 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2571 + */
2572 +#ifndef __ASM_ARCH_DMA_H
2573 +#define __ASM_ARCH_DMA_H
2574 +
2575 +/* Hardware registers for omap1 */
2576 +#define OMAP1_DMA_BASE (0xfffed800)
2577 +
2578 +#define OMAP1_DMA_GCR 0x400
2579 +#define OMAP1_DMA_GSCR 0x404
2580 +#define OMAP1_DMA_GRST 0x408
2581 +#define OMAP1_DMA_HW_ID 0x442
2582 +#define OMAP1_DMA_PCH2_ID 0x444
2583 +#define OMAP1_DMA_PCH0_ID 0x446
2584 +#define OMAP1_DMA_PCH1_ID 0x448
2585 +#define OMAP1_DMA_PCHG_ID 0x44a
2586 +#define OMAP1_DMA_PCHD_ID 0x44c
2587 +#define OMAP1_DMA_CAPS_0_U 0x44e
2588 +#define OMAP1_DMA_CAPS_0_L 0x450
2589 +#define OMAP1_DMA_CAPS_1_U 0x452
2590 +#define OMAP1_DMA_CAPS_1_L 0x454
2591 +#define OMAP1_DMA_CAPS_2 0x456
2592 +#define OMAP1_DMA_CAPS_3 0x458
2593 +#define OMAP1_DMA_CAPS_4 0x45a
2594 +#define OMAP1_DMA_PCH2_SR 0x460
2595 +#define OMAP1_DMA_PCH0_SR 0x480
2596 +#define OMAP1_DMA_PCH1_SR 0x482
2597 +#define OMAP1_DMA_PCHD_SR 0x4c0
2598 +
2599 +/* Hardware registers for omap2 and omap3 */
2600 +#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
2601 +#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
2602 +#define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000)
2603 +
2604 +#define OMAP_DMA4_REVISION 0x00
2605 +#define OMAP_DMA4_GCR 0x78
2606 +#define OMAP_DMA4_IRQSTATUS_L0 0x08
2607 +#define OMAP_DMA4_IRQSTATUS_L1 0x0c
2608 +#define OMAP_DMA4_IRQSTATUS_L2 0x10
2609 +#define OMAP_DMA4_IRQSTATUS_L3 0x14
2610 +#define OMAP_DMA4_IRQENABLE_L0 0x18
2611 +#define OMAP_DMA4_IRQENABLE_L1 0x1c
2612 +#define OMAP_DMA4_IRQENABLE_L2 0x20
2613 +#define OMAP_DMA4_IRQENABLE_L3 0x24
2614 +#define OMAP_DMA4_SYSSTATUS 0x28
2615 +#define OMAP_DMA4_OCP_SYSCONFIG 0x2c
2616 +#define OMAP_DMA4_CAPS_0 0x64
2617 +#define OMAP_DMA4_CAPS_2 0x6c
2618 +#define OMAP_DMA4_CAPS_3 0x70
2619 +#define OMAP_DMA4_CAPS_4 0x74
2620 +
2621 +#define OMAP1_LOGICAL_DMA_CH_COUNT 17
2622 +#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
2623 +
2624 +/* Common channel specific registers for omap1 */
2625 +#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00)
2626 +#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00)
2627 +#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02)
2628 +#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04)
2629 +#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06)
2630 +#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10)
2631 +#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12)
2632 +#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14)
2633 +#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16)
2634 +#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */
2635 +#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18)
2636 +#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a)
2637 +#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c)
2638 +#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e)
2639 +#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28)
2640 +
2641 +/* Common channel specific registers for omap2 */
2642 +#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80)
2643 +#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80)
2644 +#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84)
2645 +#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88)
2646 +#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c)
2647 +#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90)
2648 +#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94)
2649 +#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98)
2650 +#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4)
2651 +#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8)
2652 +#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac)
2653 +#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0)
2654 +#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4)
2655 +#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8)
2656 +
2657 +/* Channel specific registers only on omap1 */
2658 +#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08)
2659 +#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a)
2660 +#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c)
2661 +#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e)
2662 +#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20)
2663 +#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22)
2664 +#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24)
2665 +#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */
2666 +#define OMAP1_DMA_CCEN(n) 0
2667 +#define OMAP1_DMA_CCFN(n) 0
2668 +
2669 +/* Channel specific registers only on omap2 */
2670 +#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c)
2671 +#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0)
2672 +#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc)
2673 +#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
2674 +#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
2675 +
2676 +/* Additional registers available on OMAP4 */
2677 +#define OMAP_DMA4_CDP(n) (0x60 * (n) + 0xd0)
2678 +#define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4)
2679 +#define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8)
2680 +
2681 +/* Dummy defines to keep multi-omap compiles happy */
2682 +#define OMAP1_DMA_REVISION 0
2683 +#define OMAP1_DMA_IRQSTATUS_L0 0
2684 +#define OMAP1_DMA_IRQENABLE_L0 0
2685 +#define OMAP1_DMA_OCP_SYSCONFIG 0
2686 +#define OMAP_DMA4_HW_ID 0
2687 +#define OMAP_DMA4_CAPS_0_L 0
2688 +#define OMAP_DMA4_CAPS_0_U 0
2689 +#define OMAP_DMA4_CAPS_1_L 0
2690 +#define OMAP_DMA4_CAPS_1_U 0
2691 +#define OMAP_DMA4_GSCR 0
2692 +#define OMAP_DMA4_CPC(n) 0
2693 +
2694 +#define OMAP_DMA4_LCH_CTRL(n) 0
2695 +#define OMAP_DMA4_COLOR_L(n) 0
2696 +#define OMAP_DMA4_COLOR_U(n) 0
2697 +#define OMAP_DMA4_CCR2(n) 0
2698 +#define OMAP1_DMA_CSSA(n) 0
2699 +#define OMAP1_DMA_CDSA(n) 0
2700 +#define OMAP_DMA4_CSSA_L(n) 0
2701 +#define OMAP_DMA4_CSSA_U(n) 0
2702 +#define OMAP_DMA4_CDSA_L(n) 0
2703 +#define OMAP_DMA4_CDSA_U(n) 0
2704 +#define OMAP1_DMA_COLOR(n) 0
2705 +
2706 +/*----------------------------------------------------------------------------*/
2707 +
2708 +/* DMA channels for omap1 */
2709 +#define OMAP_DMA_NO_DEVICE 0
2710 +#define OMAP_DMA_MCSI1_TX 1
2711 +#define OMAP_DMA_MCSI1_RX 2
2712 +#define OMAP_DMA_I2C_RX 3
2713 +#define OMAP_DMA_I2C_TX 4
2714 +#define OMAP_DMA_EXT_NDMA_REQ 5
2715 +#define OMAP_DMA_EXT_NDMA_REQ2 6
2716 +#define OMAP_DMA_UWIRE_TX 7
2717 +#define OMAP_DMA_MCBSP1_TX 8
2718 +#define OMAP_DMA_MCBSP1_RX 9
2719 +#define OMAP_DMA_MCBSP3_TX 10
2720 +#define OMAP_DMA_MCBSP3_RX 11
2721 +#define OMAP_DMA_UART1_TX 12
2722 +#define OMAP_DMA_UART1_RX 13
2723 +#define OMAP_DMA_UART2_TX 14
2724 +#define OMAP_DMA_UART2_RX 15
2725 +#define OMAP_DMA_MCBSP2_TX 16
2726 +#define OMAP_DMA_MCBSP2_RX 17
2727 +#define OMAP_DMA_UART3_TX 18
2728 +#define OMAP_DMA_UART3_RX 19
2729 +#define OMAP_DMA_CAMERA_IF_RX 20
2730 +#define OMAP_DMA_MMC_TX 21
2731 +#define OMAP_DMA_MMC_RX 22
2732 +#define OMAP_DMA_NAND 23
2733 +#define OMAP_DMA_IRQ_LCD_LINE 24
2734 +#define OMAP_DMA_MEMORY_STICK 25
2735 +#define OMAP_DMA_USB_W2FC_RX0 26
2736 +#define OMAP_DMA_USB_W2FC_RX1 27
2737 +#define OMAP_DMA_USB_W2FC_RX2 28
2738 +#define OMAP_DMA_USB_W2FC_TX0 29
2739 +#define OMAP_DMA_USB_W2FC_TX1 30
2740 +#define OMAP_DMA_USB_W2FC_TX2 31
2741 +
2742 +/* These are only for 1610 */
2743 +#define OMAP_DMA_CRYPTO_DES_IN 32
2744 +#define OMAP_DMA_SPI_TX 33
2745 +#define OMAP_DMA_SPI_RX 34
2746 +#define OMAP_DMA_CRYPTO_HASH 35
2747 +#define OMAP_DMA_CCP_ATTN 36
2748 +#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
2749 +#define OMAP_DMA_CMT_APE_TX_CHAN_0 38
2750 +#define OMAP_DMA_CMT_APE_RV_CHAN_0 39
2751 +#define OMAP_DMA_CMT_APE_TX_CHAN_1 40
2752 +#define OMAP_DMA_CMT_APE_RV_CHAN_1 41
2753 +#define OMAP_DMA_CMT_APE_TX_CHAN_2 42
2754 +#define OMAP_DMA_CMT_APE_RV_CHAN_2 43
2755 +#define OMAP_DMA_CMT_APE_TX_CHAN_3 44
2756 +#define OMAP_DMA_CMT_APE_RV_CHAN_3 45
2757 +#define OMAP_DMA_CMT_APE_TX_CHAN_4 46
2758 +#define OMAP_DMA_CMT_APE_RV_CHAN_4 47
2759 +#define OMAP_DMA_CMT_APE_TX_CHAN_5 48
2760 +#define OMAP_DMA_CMT_APE_RV_CHAN_5 49
2761 +#define OMAP_DMA_CMT_APE_TX_CHAN_6 50
2762 +#define OMAP_DMA_CMT_APE_RV_CHAN_6 51
2763 +#define OMAP_DMA_CMT_APE_TX_CHAN_7 52
2764 +#define OMAP_DMA_CMT_APE_RV_CHAN_7 53
2765 +#define OMAP_DMA_MMC2_TX 54
2766 +#define OMAP_DMA_MMC2_RX 55
2767 +#define OMAP_DMA_CRYPTO_DES_OUT 56
2768 +
2769 +/* DMA channels for 24xx */
2770 +#define OMAP24XX_DMA_NO_DEVICE 0
2771 +#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
2772 +#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */
2773 +#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */
2774 +#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
2775 +#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
2776 +#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
2777 +#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */
2778 +#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */
2779 +#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
2780 +#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
2781 +#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
2782 +#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
2783 +#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
2784 +#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
2785 +#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */
2786 +#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
2787 +#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
2788 +#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
2789 +#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */
2790 +#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */
2791 +#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
2792 +#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
2793 +#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
2794 +#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
2795 +#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
2796 +#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
2797 +#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
2798 +#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
2799 +#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */
2800 +#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
2801 +#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
2802 +#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */
2803 +#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */
2804 +#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */
2805 +#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */
2806 +#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */
2807 +#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */
2808 +#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
2809 +#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
2810 +#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */
2811 +#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */
2812 +#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */
2813 +#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */
2814 +#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
2815 +#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
2816 +#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
2817 +#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
2818 +#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */
2819 +#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */
2820 +#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */
2821 +#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */
2822 +#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
2823 +#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
2824 +#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
2825 +#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
2826 +#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
2827 +#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
2828 +#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
2829 +#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
2830 +#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
2831 +#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
2832 +#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
2833 +#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
2834 +#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */
2835 +#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */
2836 +#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */
2837 +#define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */
2838 +#define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */
2839 +#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */
2840 +#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */
2841 +#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */
2842 +#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */
2843 +#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */
2844 +#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */
2845 +#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */
2846 +#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */
2847 +#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */
2848 +#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */
2849 +#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */
2850 +#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */
2851 +#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
2852 +#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */
2853 +#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */
2854 +#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */
2855 +#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */
2856 +#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */
2857 +#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */
2858 +#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */
2859 +#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
2860 +#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
2861 +#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */
2862 +#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */
2863 +#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */
2864 +#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */
2865 +#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */
2866 +#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */
2867 +#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
2868 +#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
2869 +
2870 +/* DMA request lines for 44xx */
2871 +#define OMAP44XX_DMA_DSS_DISPC_REQ 6 /* S_DMA_5 */
2872 +#define OMAP44XX_DMA_SYS_REQ2 7 /* S_DMA_6 */
2873 +#define OMAP44XX_DMA_ISS_REQ1 9 /* S_DMA_8 */
2874 +#define OMAP44XX_DMA_ISS_REQ2 10 /* S_DMA_9 */
2875 +#define OMAP44XX_DMA_ISS_REQ3 12 /* S_DMA_11 */
2876 +#define OMAP44XX_DMA_ISS_REQ4 13 /* S_DMA_12 */
2877 +#define OMAP44XX_DMA_DSS_RFBI_REQ 14 /* S_DMA_13 */
2878 +#define OMAP44XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
2879 +#define OMAP44XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
2880 +#define OMAP44XX_DMA_MCBSP2_TX 17 /* S_DMA_16 */
2881 +#define OMAP44XX_DMA_MCBSP2_RX 18 /* S_DMA_17 */
2882 +#define OMAP44XX_DMA_MCBSP3_TX 19 /* S_DMA_18 */
2883 +#define OMAP44XX_DMA_MCBSP3_RX 20 /* S_DMA_19 */
2884 +#define OMAP44XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
2885 +#define OMAP44XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
2886 +#define OMAP44XX_DMA_I2C3_TX 25 /* S_DMA_24 */
2887 +#define OMAP44XX_DMA_I2C3_RX 26 /* S_DMA_25 */
2888 +#define OMAP44XX_DMA_I2C1_TX 27 /* S_DMA_26 */
2889 +#define OMAP44XX_DMA_I2C1_RX 28 /* S_DMA_27 */
2890 +#define OMAP44XX_DMA_I2C2_TX 29 /* S_DMA_28 */
2891 +#define OMAP44XX_DMA_I2C2_RX 30 /* S_DMA_29 */
2892 +#define OMAP44XX_DMA_MCBSP4_TX 31 /* S_DMA_30 */
2893 +#define OMAP44XX_DMA_MCBSP4_RX 32 /* S_DMA_31 */
2894 +#define OMAP44XX_DMA_MCBSP1_TX 33 /* S_DMA_32 */
2895 +#define OMAP44XX_DMA_MCBSP1_RX 34 /* S_DMA_33 */
2896 +#define OMAP44XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
2897 +#define OMAP44XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
2898 +#define OMAP44XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
2899 +#define OMAP44XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
2900 +#define OMAP44XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
2901 +#define OMAP44XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
2902 +#define OMAP44XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
2903 +#define OMAP44XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
2904 +#define OMAP44XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
2905 +#define OMAP44XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
2906 +#define OMAP44XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
2907 +#define OMAP44XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
2908 +#define OMAP44XX_DMA_MMC2_TX 47 /* S_DMA_46 */
2909 +#define OMAP44XX_DMA_MMC2_RX 48 /* S_DMA_47 */
2910 +#define OMAP44XX_DMA_UART1_TX 49 /* S_DMA_48 */
2911 +#define OMAP44XX_DMA_UART1_RX 50 /* S_DMA_49 */
2912 +#define OMAP44XX_DMA_UART2_TX 51 /* S_DMA_50 */
2913 +#define OMAP44XX_DMA_UART2_RX 52 /* S_DMA_51 */
2914 +#define OMAP44XX_DMA_UART3_TX 53 /* S_DMA_52 */
2915 +#define OMAP44XX_DMA_UART3_RX 54 /* S_DMA_53 */
2916 +#define OMAP44XX_DMA_UART4_TX 55 /* S_DMA_54 */
2917 +#define OMAP44XX_DMA_UART4_RX 56 /* S_DMA_55 */
2918 +#define OMAP44XX_DMA_MMC4_TX 57 /* S_DMA_56 */
2919 +#define OMAP44XX_DMA_MMC4_RX 58 /* S_DMA_57 */
2920 +#define OMAP44XX_DMA_MMC5_TX 59 /* S_DMA_58 */
2921 +#define OMAP44XX_DMA_MMC5_RX 60 /* S_DMA_59 */
2922 +#define OMAP44XX_DMA_MMC1_TX 61 /* S_DMA_60 */
2923 +#define OMAP44XX_DMA_MMC1_RX 62 /* S_DMA_61 */
2924 +#define OMAP44XX_DMA_SYS_REQ3 64 /* S_DMA_63 */
2925 +#define OMAP44XX_DMA_MCPDM_UP 65 /* S_DMA_64 */
2926 +#define OMAP44XX_DMA_MCPDM_DL 66 /* S_DMA_65 */
2927 +#define OMAP44XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
2928 +#define OMAP44XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
2929 +#define OMAP44XX_DMA_DSS_DSI1_REQ0 72 /* S_DMA_71 */
2930 +#define OMAP44XX_DMA_DSS_DSI1_REQ1 73 /* S_DMA_72 */
2931 +#define OMAP44XX_DMA_DSS_DSI1_REQ2 74 /* S_DMA_73 */
2932 +#define OMAP44XX_DMA_DSS_DSI1_REQ3 75 /* S_DMA_74 */
2933 +#define OMAP44XX_DMA_DSS_HDMI_REQ 76 /* S_DMA_75 */
2934 +#define OMAP44XX_DMA_MMC3_TX 77 /* S_DMA_76 */
2935 +#define OMAP44XX_DMA_MMC3_RX 78 /* S_DMA_77 */
2936 +#define OMAP44XX_DMA_USIM_TX 79 /* S_DMA_78 */
2937 +#define OMAP44XX_DMA_USIM_RX 80 /* S_DMA_79 */
2938 +#define OMAP44XX_DMA_DSS_DSI2_REQ0 81 /* S_DMA_80 */
2939 +#define OMAP44XX_DMA_DSS_DSI2_REQ1 82 /* S_DMA_81 */
2940 +#define OMAP44XX_DMA_DSS_DSI2_REQ2 83 /* S_DMA_82 */
2941 +#define OMAP44XX_DMA_DSS_DSI2_REQ3 84 /* S_DMA_83 */
2942 +#define OMAP44XX_DMA_ABE_REQ0 101 /* S_DMA_100 */
2943 +#define OMAP44XX_DMA_ABE_REQ1 102 /* S_DMA_101 */
2944 +#define OMAP44XX_DMA_ABE_REQ2 103 /* S_DMA_102 */
2945 +#define OMAP44XX_DMA_ABE_REQ3 104 /* S_DMA_103 */
2946 +#define OMAP44XX_DMA_ABE_REQ4 105 /* S_DMA_104 */
2947 +#define OMAP44XX_DMA_ABE_REQ5 106 /* S_DMA_105 */
2948 +#define OMAP44XX_DMA_ABE_REQ6 107 /* S_DMA_106 */
2949 +#define OMAP44XX_DMA_ABE_REQ7 108 /* S_DMA_107 */
2950 +#define OMAP44XX_DMA_I2C4_TX 124 /* S_DMA_123 */
2951 +#define OMAP44XX_DMA_I2C4_RX 125 /* S_DMA_124 */
2952 +
2953 +/*----------------------------------------------------------------------------*/
2954 +
2955 +#define OMAP1_DMA_TOUT_IRQ (1 << 0)
2956 +#define OMAP_DMA_DROP_IRQ (1 << 1)
2957 +#define OMAP_DMA_HALF_IRQ (1 << 2)
2958 +#define OMAP_DMA_FRAME_IRQ (1 << 3)
2959 +#define OMAP_DMA_LAST_IRQ (1 << 4)
2960 +#define OMAP_DMA_BLOCK_IRQ (1 << 5)
2961 +#define OMAP1_DMA_SYNC_IRQ (1 << 6)
2962 +#define OMAP2_DMA_PKT_IRQ (1 << 7)
2963 +#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
2964 +#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
2965 +#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
2966 +#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
2967 +
2968 +#define OMAP_DMA_CCR_EN (1 << 7)
2969 +
2970 +#define OMAP_DMA_DATA_TYPE_S8 0x00
2971 +#define OMAP_DMA_DATA_TYPE_S16 0x01
2972 +#define OMAP_DMA_DATA_TYPE_S32 0x02
2973 +
2974 +#define OMAP_DMA_SYNC_ELEMENT 0x00
2975 +#define OMAP_DMA_SYNC_FRAME 0x01
2976 +#define OMAP_DMA_SYNC_BLOCK 0x02
2977 +#define OMAP_DMA_SYNC_PACKET 0x03
2978 +
2979 +#define OMAP_DMA_SRC_SYNC 0x01
2980 +#define OMAP_DMA_DST_SYNC 0x00
2981 +
2982 +#define OMAP_DMA_PORT_EMIFF 0x00
2983 +#define OMAP_DMA_PORT_EMIFS 0x01
2984 +#define OMAP_DMA_PORT_OCP_T1 0x02
2985 +#define OMAP_DMA_PORT_TIPB 0x03
2986 +#define OMAP_DMA_PORT_OCP_T2 0x04
2987 +#define OMAP_DMA_PORT_MPUI 0x05
2988 +
2989 +#define OMAP_DMA_AMODE_CONSTANT 0x00
2990 +#define OMAP_DMA_AMODE_POST_INC 0x01
2991 +#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
2992 +#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
2993 +
2994 +#define DMA_DEFAULT_FIFO_DEPTH 0x10
2995 +#define DMA_DEFAULT_ARB_RATE 0x01
2996 +/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
2997 +#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
2998 +#define DMA_THREAD_RESERVE_ONET (0x01 << 12)
2999 +#define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
3000 +#define DMA_THREAD_RESERVE_THREET (0x03 << 12)
3001 +#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
3002 +#define DMA_THREAD_FIFO_75 (0x01 << 14)
3003 +#define DMA_THREAD_FIFO_25 (0x02 << 14)
3004 +#define DMA_THREAD_FIFO_50 (0x03 << 14)
3005 +
3006 +/* DMA4_OCP_SYSCONFIG bits */
3007 +#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12)
3008 +#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
3009 +#define DMA_SYSCONFIG_EMUFREE (1 << 5)
3010 +#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3)
3011 +#define DMA_SYSCONFIG_SOFTRESET (1 << 2)
3012 +#define DMA_SYSCONFIG_AUTOIDLE (1 << 0)
3013 +
3014 +#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12)
3015 +#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3)
3016 +
3017 +#define DMA_IDLEMODE_SMARTIDLE 0x2
3018 +#define DMA_IDLEMODE_NO_IDLE 0x1
3019 +#define DMA_IDLEMODE_FORCE_IDLE 0x0
3020 +
3021 +/* Chaining modes*/
3022 +#ifndef CONFIG_ARCH_OMAP1
3023 +#define OMAP_DMA_STATIC_CHAIN 0x1
3024 +#define OMAP_DMA_DYNAMIC_CHAIN 0x2
3025 +#define OMAP_DMA_CHAIN_ACTIVE 0x1
3026 +#define OMAP_DMA_CHAIN_INACTIVE 0x0
3027 +#endif
3028 +
3029 +#define DMA_CH_PRIO_HIGH 0x1
3030 +#define DMA_CH_PRIO_LOW 0x0 /* Def */
3031 +
3032 +enum omap_dma_burst_mode {
3033 + OMAP_DMA_DATA_BURST_DIS = 0,
3034 + OMAP_DMA_DATA_BURST_4,
3035 + OMAP_DMA_DATA_BURST_8,
3036 + OMAP_DMA_DATA_BURST_16,
3037 +};
3038 +
3039 +enum end_type {
3040 + OMAP_DMA_LITTLE_ENDIAN = 0,
3041 + OMAP_DMA_BIG_ENDIAN
3042 +};
3043 +
3044 +enum omap_dma_color_mode {
3045 + OMAP_DMA_COLOR_DIS = 0,
3046 + OMAP_DMA_CONSTANT_FILL,
3047 + OMAP_DMA_TRANSPARENT_COPY
3048 +};
3049 +
3050 +enum omap_dma_write_mode {
3051 + OMAP_DMA_WRITE_NON_POSTED = 0,
3052 + OMAP_DMA_WRITE_POSTED,
3053 + OMAP_DMA_WRITE_LAST_NON_POSTED
3054 +};
3055 +
3056 +enum omap_dma_channel_mode {
3057 + OMAP_DMA_LCH_2D = 0,
3058 + OMAP_DMA_LCH_G,
3059 + OMAP_DMA_LCH_P,
3060 + OMAP_DMA_LCH_PD
3061 +};
3062 +
3063 +struct omap_dma_channel_params {
3064 + int data_type; /* data type 8,16,32 */
3065 + int elem_count; /* number of elements in a frame */
3066 + int frame_count; /* number of frames in a element */
3067 +
3068 + int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
3069 + int src_amode; /* constant, post increment, indexed,
3070 + double indexed */
3071 + unsigned long src_start; /* source address : physical */
3072 + int src_ei; /* source element index */
3073 + int src_fi; /* source frame index */
3074 +
3075 + int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
3076 + int dst_amode; /* constant, post increment, indexed,
3077 + double indexed */
3078 + unsigned long dst_start; /* source address : physical */
3079 + int dst_ei; /* source element index */
3080 + int dst_fi; /* source frame index */
3081 +
3082 + int trigger; /* trigger attached if the channel is
3083 + synchronized */
3084 + int sync_mode; /* sycn on element, frame , block or packet */
3085 + int src_or_dst_synch; /* source synch(1) or destination synch(0) */
3086 +
3087 + int ie; /* interrupt enabled */
3088 +
3089 + unsigned char read_prio;/* read priority */
3090 + unsigned char write_prio;/* write priority */
3091 +
3092 +#ifndef CONFIG_ARCH_OMAP1
3093 + enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
3094 +#endif
3095 +};
3096 +
3097 +
3098 +extern void omap_set_dma_priority(int lch, int dst_port, int priority);
3099 +extern int omap_request_dma(int dev_id, const char *dev_name,
3100 + void (*callback)(int lch, u16 ch_status, void *data),
3101 + void *data, int *dma_ch);
3102 +extern void omap_enable_dma_irq(int ch, u16 irq_bits);
3103 +extern void omap_disable_dma_irq(int ch, u16 irq_bits);
3104 +extern void omap_free_dma(int ch);
3105 +extern void omap_start_dma(int lch);
3106 +extern void omap_stop_dma(int lch);
3107 +extern void omap_set_dma_transfer_params(int lch, int data_type,
3108 + int elem_count, int frame_count,
3109 + int sync_mode,
3110 + int dma_trigger, int src_or_dst_synch);
3111 +extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
3112 + u32 color);
3113 +extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
3114 +extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
3115 +
3116 +extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
3117 + unsigned long src_start,
3118 + int src_ei, int src_fi);
3119 +extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
3120 +extern void omap_set_dma_src_data_pack(int lch, int enable);
3121 +extern void omap_set_dma_src_burst_mode(int lch,
3122 + enum omap_dma_burst_mode burst_mode);
3123 +
3124 +extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
3125 + unsigned long dest_start,
3126 + int dst_ei, int dst_fi);
3127 +extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
3128 +extern void omap_set_dma_dest_data_pack(int lch, int enable);
3129 +extern void omap_set_dma_dest_burst_mode(int lch,
3130 + enum omap_dma_burst_mode burst_mode);
3131 +
3132 +extern void omap_set_dma_params(int lch,
3133 + struct omap_dma_channel_params *params);
3134 +
3135 +extern void omap_dma_link_lch(int lch_head, int lch_queue);
3136 +extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
3137 +
3138 +extern int omap_set_dma_callback(int lch,
3139 + void (*callback)(int lch, u16 ch_status, void *data),
3140 + void *data);
3141 +extern dma_addr_t omap_get_dma_src_pos(int lch);
3142 +extern dma_addr_t omap_get_dma_dst_pos(int lch);
3143 +extern void omap_clear_dma(int lch);
3144 +extern int omap_get_dma_active_status(int lch);
3145 +extern int omap_dma_running(void);
3146 +extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
3147 + int tparams);
3148 +extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
3149 + unsigned char write_prio);
3150 +extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
3151 +extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
3152 +extern int omap_get_dma_index(int lch, int *ei, int *fi);
3153 +
3154 +void omap_dma_global_context_save(void);
3155 +void omap_dma_global_context_restore(void);
3156 +
3157 +extern void omap_dma_disable_irq(int lch);
3158 +
3159 +/* Chaining APIs */
3160 +#ifndef CONFIG_ARCH_OMAP1
3161 +extern int omap_request_dma_chain(int dev_id, const char *dev_name,
3162 + void (*callback) (int lch, u16 ch_status,
3163 + void *data),
3164 + int *chain_id, int no_of_chans,
3165 + int chain_mode,
3166 + struct omap_dma_channel_params params);
3167 +extern int omap_free_dma_chain(int chain_id);
3168 +extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
3169 + int dest_start, int elem_count,
3170 + int frame_count, void *callbk_data);
3171 +extern int omap_start_dma_chain_transfers(int chain_id);
3172 +extern int omap_stop_dma_chain_transfers(int chain_id);
3173 +extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
3174 +extern int omap_get_dma_chain_dst_pos(int chain_id);
3175 +extern int omap_get_dma_chain_src_pos(int chain_id);
3176 +
3177 +extern int omap_modify_dma_chain_params(int chain_id,
3178 + struct omap_dma_channel_params params);
3179 +extern int omap_dma_chain_status(int chain_id);
3180 +#endif
3181 +
3182 +#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
3183 +#include <mach/lcd_dma.h>
3184 +#else
3185 +static inline int omap_lcd_dma_running(void)
3186 +{
3187 + return 0;
3188 +}
3189 +#endif
3190 +
3191 +#endif /* __ASM_ARCH_DMA_H */
3192 --- /dev/null
3193 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/dmtimer.h
3194 @@ -0,0 +1,84 @@
3195 +/*
3196 + * arch/arm/plat-omap/include/mach/dmtimer.h
3197 + *
3198 + * OMAP Dual-Mode Timers
3199 + *
3200 + * Copyright (C) 2005 Nokia Corporation
3201 + * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
3202 + * PWM and clock framwork support by Timo Teras.
3203 + *
3204 + * This program is free software; you can redistribute it and/or modify it
3205 + * under the terms of the GNU General Public License as published by the
3206 + * Free Software Foundation; either version 2 of the License, or (at your
3207 + * option) any later version.
3208 + *
3209 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3210 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3211 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3212 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3213 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3214 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3215 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3216 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3217 + *
3218 + * You should have received a copy of the GNU General Public License along
3219 + * with this program; if not, write to the Free Software Foundation, Inc.,
3220 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3221 + */
3222 +
3223 +#ifndef __ASM_ARCH_DMTIMER_H
3224 +#define __ASM_ARCH_DMTIMER_H
3225 +
3226 +/* clock sources */
3227 +#define OMAP_TIMER_SRC_SYS_CLK 0x00
3228 +#define OMAP_TIMER_SRC_32_KHZ 0x01
3229 +#define OMAP_TIMER_SRC_EXT_CLK 0x02
3230 +
3231 +/* timer interrupt enable bits */
3232 +#define OMAP_TIMER_INT_CAPTURE (1 << 2)
3233 +#define OMAP_TIMER_INT_OVERFLOW (1 << 1)
3234 +#define OMAP_TIMER_INT_MATCH (1 << 0)
3235 +
3236 +/* trigger types */
3237 +#define OMAP_TIMER_TRIGGER_NONE 0x00
3238 +#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
3239 +#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
3240 +
3241 +struct omap_dm_timer;
3242 +struct clk;
3243 +
3244 +int omap_dm_timer_init(void);
3245 +
3246 +struct omap_dm_timer *omap_dm_timer_request(void);
3247 +struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
3248 +void omap_dm_timer_free(struct omap_dm_timer *timer);
3249 +void omap_dm_timer_enable(struct omap_dm_timer *timer);
3250 +void omap_dm_timer_disable(struct omap_dm_timer *timer);
3251 +
3252 +int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
3253 +
3254 +u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
3255 +struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
3256 +
3257 +void omap_dm_timer_trigger(struct omap_dm_timer *timer);
3258 +void omap_dm_timer_start(struct omap_dm_timer *timer);
3259 +void omap_dm_timer_stop(struct omap_dm_timer *timer);
3260 +
3261 +int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
3262 +void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
3263 +void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
3264 +void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
3265 +void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
3266 +void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
3267 +
3268 +void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
3269 +
3270 +unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
3271 +void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
3272 +unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
3273 +void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
3274 +
3275 +int omap_dm_timers_active(void);
3276 +
3277 +
3278 +#endif /* __ASM_ARCH_DMTIMER_H */
3279 --- /dev/null
3280 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/dsp_common.h
3281 @@ -0,0 +1,40 @@
3282 +/*
3283 + * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
3284 + *
3285 + * Copyright (C) 2004-2006 Nokia Corporation. All rights reserved.
3286 + *
3287 + * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
3288 + *
3289 + * This program is free software; you can redistribute it and/or
3290 + * modify it under the terms of the GNU General Public License
3291 + * version 2 as published by the Free Software Foundation.
3292 + *
3293 + * This program is distributed in the hope that it will be useful, but
3294 + * WITHOUT ANY WARRANTY; without even the implied warranty of
3295 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
3296 + * General Public License for more details.
3297 + *
3298 + * You should have received a copy of the GNU General Public License
3299 + * along with this program; if not, write to the Free Software
3300 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
3301 + * 02110-1301 USA
3302 + *
3303 + */
3304 +
3305 +#ifndef ASM_ARCH_DSP_COMMON_H
3306 +#define ASM_ARCH_DSP_COMMON_H
3307 +
3308 +#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_OMAP_MMU_FWK)
3309 +extern void omap_dsp_request_mpui(void);
3310 +extern void omap_dsp_release_mpui(void);
3311 +extern int omap_dsp_request_mem(void);
3312 +extern int omap_dsp_release_mem(void);
3313 +#else
3314 +static inline int omap_dsp_request_mem(void)
3315 +{
3316 + return 0;
3317 +}
3318 +#define omap_dsp_release_mem() do {} while (0)
3319 +#endif
3320 +
3321 +#endif /* ASM_ARCH_DSP_COMMON_H */
3322 --- /dev/null
3323 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/fpga.h
3324 @@ -0,0 +1,197 @@
3325 +/*
3326 + * arch/arm/plat-omap/include/mach/fpga.h
3327 + *
3328 + * Interrupt handler for OMAP-1510 FPGA
3329 + *
3330 + * Copyright (C) 2001 RidgeRun, Inc.
3331 + * Author: Greg Lonnon <glonnon@ridgerun.com>
3332 + *
3333 + * Copyright (C) 2002 MontaVista Software, Inc.
3334 + *
3335 + * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
3336 + * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
3337 + *
3338 + * This program is free software; you can redistribute it and/or modify
3339 + * it under the terms of the GNU General Public License version 2 as
3340 + * published by the Free Software Foundation.
3341 + */
3342 +
3343 +#ifndef __ASM_ARCH_OMAP_FPGA_H
3344 +#define __ASM_ARCH_OMAP_FPGA_H
3345 +
3346 +#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
3347 +extern void omap1510_fpga_init_irq(void);
3348 +#else
3349 +#define omap1510_fpga_init_irq() (0)
3350 +#endif
3351 +
3352 +#define fpga_read(reg) __raw_readb(reg)
3353 +#define fpga_write(val, reg) __raw_writeb(val, reg)
3354 +
3355 +/*
3356 + * ---------------------------------------------------------------------------
3357 + * H2/P2 Debug board FPGA
3358 + * ---------------------------------------------------------------------------
3359 + */
3360 +/* maps in the FPGA registers and the ETHR registers */
3361 +#define H2P2_DBG_FPGA_BASE IOMEM(0xE8000000) /* VA */
3362 +#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
3363 +#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
3364 +
3365 +#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
3366 +#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
3367 +#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
3368 +#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
3369 +#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
3370 +#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
3371 +#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
3372 +#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
3373 +
3374 +/* NOTE: most boards don't have a static mapping for the FPGA ... */
3375 +struct h2p2_dbg_fpga {
3376 + /* offset 0x00 */
3377 + u16 smc91x[8];
3378 + /* offset 0x10 */
3379 + u16 fpga_rev;
3380 + u16 board_rev;
3381 + u16 gpio_outputs;
3382 + u16 leds;
3383 + /* offset 0x18 */
3384 + u16 misc_inputs;
3385 + u16 lan_status;
3386 + u16 lan_reset;
3387 + u16 reserved0;
3388 + /* offset 0x20 */
3389 + u16 ps2_data;
3390 + u16 ps2_ctrl;
3391 + /* plus also 4 rs232 ports ... */
3392 +};
3393 +
3394 +/* LEDs definition on debug board (16 LEDs, all physically green) */
3395 +#define H2P2_DBG_FPGA_LED_GREEN (1 << 15)
3396 +#define H2P2_DBG_FPGA_LED_AMBER (1 << 14)
3397 +#define H2P2_DBG_FPGA_LED_RED (1 << 13)
3398 +#define H2P2_DBG_FPGA_LED_BLUE (1 << 12)
3399 +/* cpu0 load-meter LEDs */
3400 +#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ...
3401 +#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
3402 +#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
3403 +
3404 +#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)
3405 +#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1)
3406 +
3407 +/*
3408 + * ---------------------------------------------------------------------------
3409 + * OMAP-1510 FPGA
3410 + * ---------------------------------------------------------------------------
3411 + */
3412 +#define OMAP1510_FPGA_BASE IOMEM(0xE8000000) /* VA */
3413 +#define OMAP1510_FPGA_SIZE SZ_4K
3414 +#define OMAP1510_FPGA_START 0x08000000 /* PA */
3415 +
3416 +/* Revision */
3417 +#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
3418 +#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1)
3419 +
3420 +#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2)
3421 +#define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3)
3422 +#define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4)
3423 +#define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5)
3424 +
3425 +/* Interrupt status */
3426 +#define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6)
3427 +#define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7)
3428 +
3429 +/* Interrupt mask */
3430 +#define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8)
3431 +#define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9)
3432 +
3433 +/* Reset registers */
3434 +#define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa)
3435 +#define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb)
3436 +
3437 +#define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc)
3438 +#define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe)
3439 +#define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf)
3440 +#define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14)
3441 +#define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15)
3442 +#define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16)
3443 +#define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18)
3444 +#define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100)
3445 +#define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101)
3446 +#define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102)
3447 +
3448 +#define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204)
3449 +
3450 +#define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205)
3451 +#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206)
3452 +#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207)
3453 +#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208)
3454 +#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209)
3455 +#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a)
3456 +#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b)
3457 +#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c)
3458 +#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d)
3459 +#define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e)
3460 +#define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210)
3461 +
3462 +#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300)
3463 +
3464 +/*
3465 + * Power up Giga UART driver, turn on HID clock.
3466 + * Turn off BT power, since we're not using it and it
3467 + * draws power.
3468 + */
3469 +#define OMAP1510_FPGA_RESET_VALUE 0x42
3470 +
3471 +#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7)
3472 +#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6)
3473 +#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5)
3474 +#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4)
3475 +#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3)
3476 +#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2)
3477 +#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
3478 +#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
3479 +
3480 +/*
3481 + * Innovator/OMAP1510 FPGA HID register bit definitions
3482 + */
3483 +#define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */
3484 +#define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */
3485 +#define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */
3486 +#define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */
3487 +#define OMAP1510_FPGA_HID_MISO (1<<4) /* input */
3488 +#define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */
3489 +#define OMAP1510_FPGA_HID_rsrvd (1<<6)
3490 +#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
3491 +
3492 +/* The FPGA IRQ is cascaded through GPIO_13 */
3493 +#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
3494 +
3495 +/* IRQ Numbers for interrupts muxed through the FPGA */
3496 +#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0)
3497 +#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1)
3498 +#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2)
3499 +#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3)
3500 +#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4)
3501 +#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5)
3502 +#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6)
3503 +#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7)
3504 +#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8)
3505 +#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9)
3506 +#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10)
3507 +#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11)
3508 +#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12)
3509 +#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13)
3510 +#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14)
3511 +#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15)
3512 +#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16)
3513 +#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17)
3514 +#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18)
3515 +#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19)
3516 +#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20)
3517 +#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21)
3518 +#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22)
3519 +#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23)
3520 +
3521 +#endif
3522 --- /dev/null
3523 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/gpio.h
3524 @@ -0,0 +1,129 @@
3525 +/*
3526 + * arch/arm/plat-omap/include/mach/gpio.h
3527 + *
3528 + * OMAP GPIO handling defines and functions
3529 + *
3530 + * Copyright (C) 2003-2005 Nokia Corporation
3531 + *
3532 + * Written by Juha Yrjölä <juha.yrjola@nokia.com>
3533 + *
3534 + * This program is free software; you can redistribute it and/or modify
3535 + * it under the terms of the GNU General Public License as published by
3536 + * the Free Software Foundation; either version 2 of the License, or
3537 + * (at your option) any later version.
3538 + *
3539 + * This program is distributed in the hope that it will be useful,
3540 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3541 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3542 + * GNU General Public License for more details.
3543 + *
3544 + * You should have received a copy of the GNU General Public License
3545 + * along with this program; if not, write to the Free Software
3546 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3547 + *
3548 + */
3549 +
3550 +#ifndef __ASM_ARCH_OMAP_GPIO_H
3551 +#define __ASM_ARCH_OMAP_GPIO_H
3552 +
3553 +#include <linux/io.h>
3554 +#include <mach/irqs.h>
3555 +
3556 +#define OMAP1_MPUIO_BASE 0xfffb5000
3557 +
3558 +#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850))
3559 +
3560 +#define OMAP_MPUIO_INPUT_LATCH 0x00
3561 +#define OMAP_MPUIO_OUTPUT 0x02
3562 +#define OMAP_MPUIO_IO_CNTL 0x04
3563 +#define OMAP_MPUIO_KBR_LATCH 0x08
3564 +#define OMAP_MPUIO_KBC 0x0a
3565 +#define OMAP_MPUIO_GPIO_EVENT_MODE 0x0c
3566 +#define OMAP_MPUIO_GPIO_INT_EDGE 0x0e
3567 +#define OMAP_MPUIO_KBD_INT 0x10
3568 +#define OMAP_MPUIO_GPIO_INT 0x12
3569 +#define OMAP_MPUIO_KBD_MASKIT 0x14
3570 +#define OMAP_MPUIO_GPIO_MASKIT 0x16
3571 +#define OMAP_MPUIO_GPIO_DEBOUNCING 0x18
3572 +#define OMAP_MPUIO_LATCH 0x1a
3573 +#else
3574 +#define OMAP_MPUIO_INPUT_LATCH 0x00
3575 +#define OMAP_MPUIO_OUTPUT 0x04
3576 +#define OMAP_MPUIO_IO_CNTL 0x08
3577 +#define OMAP_MPUIO_KBR_LATCH 0x10
3578 +#define OMAP_MPUIO_KBC 0x14
3579 +#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
3580 +#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
3581 +#define OMAP_MPUIO_KBD_INT 0x20
3582 +#define OMAP_MPUIO_GPIO_INT 0x24
3583 +#define OMAP_MPUIO_KBD_MASKIT 0x28
3584 +#define OMAP_MPUIO_GPIO_MASKIT 0x2c
3585 +#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
3586 +#define OMAP_MPUIO_LATCH 0x34
3587 +#endif
3588 +
3589 +#define OMAP34XX_NR_GPIOS 6
3590 +
3591 +#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
3592 +#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
3593 +
3594 +#define OMAP_GPIO_IRQ(nr) (OMAP_GPIO_IS_MPUIO(nr) ? \
3595 + IH_MPUIO_BASE + ((nr) & 0x0f) : \
3596 + IH_GPIO_BASE + (nr))
3597 +
3598 +extern int omap_gpio_init(void); /* Call from board init only */
3599 +extern void omap2_gpio_prepare_for_retention(void);
3600 +extern void omap2_gpio_resume_after_retention(void);
3601 +extern void omap_set_gpio_debounce(int gpio, int enable);
3602 +extern void omap_set_gpio_debounce_time(int gpio, int enable);
3603 +extern void omap_gpio_save_context(void);
3604 +extern void omap_gpio_restore_context(void);
3605 +/*-------------------------------------------------------------------------*/
3606 +
3607 +/* Wrappers for "new style" GPIO calls, using the new infrastructure
3608 + * which lets us plug in FPGA, I2C, and other implementations.
3609 + * *
3610 + * The original OMAP-specfic calls should eventually be removed.
3611 + */
3612 +
3613 +#include <linux/errno.h>
3614 +#include <asm-generic/gpio.h>
3615 +
3616 +static inline int gpio_get_value(unsigned gpio)
3617 +{
3618 + return __gpio_get_value(gpio);
3619 +}
3620 +
3621 +static inline void gpio_set_value(unsigned gpio, int value)
3622 +{
3623 + __gpio_set_value(gpio, value);
3624 +}
3625 +
3626 +static inline int gpio_cansleep(unsigned gpio)
3627 +{
3628 + return __gpio_cansleep(gpio);
3629 +}
3630 +
3631 +static inline int gpio_to_irq(unsigned gpio)
3632 +{
3633 + return __gpio_to_irq(gpio);
3634 +}
3635 +
3636 +static inline int irq_to_gpio(unsigned irq)
3637 +{
3638 + int tmp;
3639 +
3640 + /* omap1 SOC mpuio */
3641 + if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16)))
3642 + return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES;
3643 +
3644 + /* SOC gpio */
3645 + tmp = irq - IH_GPIO_BASE;
3646 + if (tmp < OMAP_MAX_GPIO_LINES)
3647 + return tmp;
3648 +
3649 + /* we don't supply reverse mappings for non-SOC gpios */
3650 + return -EIO;
3651 +}
3652 +
3653 +#endif
3654 --- /dev/null
3655 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/gpio-switch.h
3656 @@ -0,0 +1,54 @@
3657 +/*
3658 + * GPIO switch definitions
3659 + *
3660 + * Copyright (C) 2006 Nokia Corporation
3661 + *
3662 + * This program is free software; you can redistribute it and/or modify
3663 + * it under the terms of the GNU General Public License version 2 as
3664 + * published by the Free Software Foundation.
3665 + */
3666 +
3667 +#ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H
3668 +#define __ASM_ARCH_OMAP_GPIO_SWITCH_H
3669 +
3670 +#include <linux/types.h>
3671 +
3672 +/* Cover:
3673 + * high -> closed
3674 + * low -> open
3675 + * Connection:
3676 + * high -> connected
3677 + * low -> disconnected
3678 + * Activity:
3679 + * high -> active
3680 + * low -> inactive
3681 + *
3682 + */
3683 +#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000
3684 +#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001
3685 +#define OMAP_GPIO_SWITCH_TYPE_ACTIVITY 0x0002
3686 +#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
3687 +#define OMAP_GPIO_SWITCH_FLAG_OUTPUT 0x0002
3688 +
3689 +struct omap_gpio_switch {
3690 + const char *name;
3691 + s16 gpio;
3692 + unsigned flags:4;
3693 + unsigned type:4;
3694 +
3695 + /* Time in ms to debounce when transitioning from
3696 + * inactive state to active state. */
3697 + u16 debounce_rising;
3698 + /* Same for transition from active to inactive state. */
3699 + u16 debounce_falling;
3700 +
3701 + /* notify board-specific code about state changes */
3702 + void (* notify)(void *data, int state);
3703 + void *notify_data;
3704 +};
3705 +
3706 +/* Call at init time only */
3707 +extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
3708 + int count);
3709 +
3710 +#endif
3711 --- /dev/null
3712 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/gpmc.h
3713 @@ -0,0 +1,115 @@
3714 +/*
3715 + * General-Purpose Memory Controller for OMAP2
3716 + *
3717 + * Copyright (C) 2005-2006 Nokia Corporation
3718 + *
3719 + * This program is free software; you can redistribute it and/or modify
3720 + * it under the terms of the GNU General Public License version 2 as
3721 + * published by the Free Software Foundation.
3722 + */
3723 +
3724 +#ifndef __OMAP2_GPMC_H
3725 +#define __OMAP2_GPMC_H
3726 +
3727 +/* Maximum Number of Chip Selects */
3728 +#define GPMC_CS_NUM 8
3729 +
3730 +#define GPMC_CS_CONFIG1 0x00
3731 +#define GPMC_CS_CONFIG2 0x04
3732 +#define GPMC_CS_CONFIG3 0x08
3733 +#define GPMC_CS_CONFIG4 0x0c
3734 +#define GPMC_CS_CONFIG5 0x10
3735 +#define GPMC_CS_CONFIG6 0x14
3736 +#define GPMC_CS_CONFIG7 0x18
3737 +#define GPMC_CS_NAND_COMMAND 0x1c
3738 +#define GPMC_CS_NAND_ADDRESS 0x20
3739 +#define GPMC_CS_NAND_DATA 0x24
3740 +
3741 +#define GPMC_CONFIG 0x50
3742 +#define GPMC_STATUS 0x54
3743 +
3744 +#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
3745 +#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
3746 +#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
3747 +#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
3748 +#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
3749 +#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
3750 +#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
3751 +#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
3752 +#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
3753 +#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
3754 +#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
3755 +#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
3756 +#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
3757 +#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
3758 +#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
3759 +#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
3760 +#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
3761 +#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(2)
3762 +#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
3763 +#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
3764 +#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
3765 +#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
3766 +#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
3767 +#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
3768 +#define GPMC_CONFIG7_CSVALID (1 << 6)
3769 +
3770 +/*
3771 + * Note that all values in this struct are in nanoseconds, while
3772 + * the register values are in gpmc_fck cycles.
3773 + */
3774 +struct gpmc_timings {
3775 + /* Minimum clock period for synchronous mode */
3776 + u16 sync_clk;
3777 +
3778 + /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
3779 + u16 cs_on; /* Assertion time */
3780 + u16 cs_rd_off; /* Read deassertion time */
3781 + u16 cs_wr_off; /* Write deassertion time */
3782 +
3783 + /* ADV signal timings corresponding to GPMC_CONFIG3 */
3784 + u16 adv_on; /* Assertion time */
3785 + u16 adv_rd_off; /* Read deassertion time */
3786 + u16 adv_wr_off; /* Write deassertion time */
3787 +
3788 + /* WE signals timings corresponding to GPMC_CONFIG4 */
3789 + u16 we_on; /* WE assertion time */
3790 + u16 we_off; /* WE deassertion time */
3791 +
3792 + /* OE signals timings corresponding to GPMC_CONFIG4 */
3793 + u16 oe_on; /* OE assertion time */
3794 + u16 oe_off; /* OE deassertion time */
3795 +
3796 + /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
3797 + u16 page_burst_access; /* Multiple access word delay */
3798 + u16 access; /* Start-cycle to first data valid delay */
3799 + u16 rd_cycle; /* Total read cycle time */
3800 + u16 wr_cycle; /* Total write cycle time */
3801 +
3802 + /* The following are only on OMAP3430 */
3803 + u16 wr_access; /* WRACCESSTIME */
3804 + u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
3805 +};
3806 +
3807 +extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
3808 +extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
3809 +extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
3810 +extern unsigned long gpmc_get_fclk_period(void);
3811 +
3812 +extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
3813 +extern u32 gpmc_cs_read_reg(int cs, int idx);
3814 +extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
3815 +extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
3816 +extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
3817 +extern void gpmc_cs_free(int cs);
3818 +extern int gpmc_cs_set_reserved(int cs, int reserved);
3819 +extern int gpmc_cs_reserved(int cs);
3820 +extern int gpmc_prefetch_enable(int cs, int dma_mode,
3821 + unsigned int u32_count, int is_write);
3822 +extern void gpmc_prefetch_reset(void);
3823 +extern int gpmc_prefetch_status(void);
3824 +extern void omap3_gpmc_save_context(void);
3825 +extern void omap3_gpmc_restore_context(void);
3826 +extern void __init gpmc_init(void);
3827 +
3828 +#endif
3829 --- /dev/null
3830 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/gpmc-smc91x.h
3831 @@ -0,0 +1,42 @@
3832 +/*
3833 + * arch/arm/plat-omap/include/mach/gpmc-smc91x.h
3834 + *
3835 + * Copyright (C) 2009 Nokia Corporation
3836 + *
3837 + * This program is free software; you can redistribute it and/or modify
3838 + * it under the terms of the GNU General Public License version 2 as
3839 + * published by the Free Software Foundation.
3840 + */
3841 +
3842 +#ifndef __ASM_ARCH_OMAP_GPMC_SMC91X_H__
3843 +
3844 +#define GPMC_TIMINGS_SMC91C96 (1 << 4)
3845 +#define GPMC_MUX_ADD_DATA (1 << 5) /* GPMC_CONFIG1_MUXADDDATA */
3846 +#define GPMC_READ_MON (1 << 6) /* GPMC_CONFIG1_WAIT_READ_MON */
3847 +#define GPMC_WRITE_MON (1 << 7) /* GPMC_CONFIG1_WAIT_WRITE_MON */
3848 +
3849 +struct omap_smc91x_platform_data {
3850 + int cs;
3851 + int gpio_irq;
3852 + int gpio_pwrdwn;
3853 + int gpio_reset;
3854 + int wait_pin; /* Optional GPMC_CONFIG1_WAITPINSELECT */
3855 + u32 flags;
3856 + int (*retime)(void);
3857 +};
3858 +
3859 +#if defined(CONFIG_SMC91X) || \
3860 + defined(CONFIG_SMC91X_MODULE)
3861 +
3862 +extern void gpmc_smc91x_init(struct omap_smc91x_platform_data *d);
3863 +
3864 +#else
3865 +
3866 +#define board_smc91x_data NULL
3867 +
3868 +static inline void gpmc_smc91x_init(struct omap_smc91x_platform_data *d)
3869 +{
3870 +}
3871 +
3872 +#endif
3873 +#endif
3874 --- /dev/null
3875 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/hardware.h
3876 @@ -0,0 +1,290 @@
3877 +/*
3878 + * arch/arm/plat-omap/include/mach/hardware.h
3879 + *
3880 + * Hardware definitions for TI OMAP processors and boards
3881 + *
3882 + * NOTE: Please put device driver specific defines into a separate header
3883 + * file for each driver.
3884 + *
3885 + * Copyright (C) 2001 RidgeRun, Inc.
3886 + * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
3887 + *
3888 + * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
3889 + * and Dirk Behme <dirk.behme@de.bosch.com>
3890 + *
3891 + * This program is free software; you can redistribute it and/or modify it
3892 + * under the terms of the GNU General Public License as published by the
3893 + * Free Software Foundation; either version 2 of the License, or (at your
3894 + * option) any later version.
3895 + *
3896 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3897 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3898 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3899 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3900 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3901 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3902 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3903 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3904 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3905 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3906 + *
3907 + * You should have received a copy of the GNU General Public License along
3908 + * with this program; if not, write to the Free Software Foundation, Inc.,
3909 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3910 + */
3911 +
3912 +#ifndef __ASM_ARCH_OMAP_HARDWARE_H
3913 +#define __ASM_ARCH_OMAP_HARDWARE_H
3914 +
3915 +#include <asm/sizes.h>
3916 +#ifndef __ASSEMBLER__
3917 +#include <asm/types.h>
3918 +#include <plat/cpu.h>
3919 +#endif
3920 +#include <plat/serial.h>
3921 +
3922 +/*
3923 + * ---------------------------------------------------------------------------
3924 + * Common definitions for all OMAP processors
3925 + * NOTE: Put all processor or board specific parts to the special header
3926 + * files.
3927 + * ---------------------------------------------------------------------------
3928 + */
3929 +
3930 +/*
3931 + * ----------------------------------------------------------------------------
3932 + * Timers
3933 + * ----------------------------------------------------------------------------
3934 + */
3935 +#define OMAP_MPU_TIMER1_BASE (0xfffec500)
3936 +#define OMAP_MPU_TIMER2_BASE (0xfffec600)
3937 +#define OMAP_MPU_TIMER3_BASE (0xfffec700)
3938 +#define MPU_TIMER_FREE (1 << 6)
3939 +#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
3940 +#define MPU_TIMER_AR (1 << 1)
3941 +#define MPU_TIMER_ST (1 << 0)
3942 +
3943 +/*
3944 + * ----------------------------------------------------------------------------
3945 + * Clocks
3946 + * ----------------------------------------------------------------------------
3947 + */
3948 +#define CLKGEN_REG_BASE (0xfffece00)
3949 +#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
3950 +#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
3951 +#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
3952 +#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
3953 +#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
3954 +#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
3955 +#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
3956 +#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
3957 +
3958 +#define CK_RATEF 1
3959 +#define CK_IDLEF 2
3960 +#define CK_ENABLEF 4
3961 +#define CK_SELECTF 8
3962 +#define SETARM_IDLE_SHIFT
3963 +
3964 +/* DPLL control registers */
3965 +#define DPLL_CTL (0xfffecf00)
3966 +
3967 +/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
3968 +#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
3969 +#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
3970 +#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
3971 +#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
3972 +#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
3973 +
3974 +/*
3975 + * ---------------------------------------------------------------------------
3976 + * UPLD
3977 + * ---------------------------------------------------------------------------
3978 + */
3979 +#define ULPD_REG_BASE (0xfffe0800)
3980 +#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
3981 +#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
3982 +#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
3983 +# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
3984 +# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
3985 +#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
3986 +# define SOFT_UDC_REQ (1 << 4)
3987 +# define SOFT_USB_CLK_REQ (1 << 3)
3988 +# define SOFT_DPLL_REQ (1 << 0)
3989 +#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
3990 +#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
3991 +#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
3992 +#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
3993 +#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
3994 +# define DIS_MMC2_DPLL_REQ (1 << 11)
3995 +# define DIS_MMC1_DPLL_REQ (1 << 10)
3996 +# define DIS_UART3_DPLL_REQ (1 << 9)
3997 +# define DIS_UART2_DPLL_REQ (1 << 8)
3998 +# define DIS_UART1_DPLL_REQ (1 << 7)
3999 +# define DIS_USB_HOST_DPLL_REQ (1 << 6)
4000 +#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
4001 +#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
4002 +
4003 +/*
4004 + * ---------------------------------------------------------------------------
4005 + * Watchdog timer
4006 + * ---------------------------------------------------------------------------
4007 + */
4008 +
4009 +/* Watchdog timer within the OMAP3.2 gigacell */
4010 +#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
4011 +#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
4012 +#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
4013 +#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
4014 +#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
4015 +
4016 +/*
4017 + * ---------------------------------------------------------------------------
4018 + * Interrupts
4019 + * ---------------------------------------------------------------------------
4020 + */
4021 +#ifdef CONFIG_ARCH_OMAP1
4022 +
4023 +/*
4024 + * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
4025 + * or something similar.. -- PFM.
4026 + */
4027 +
4028 +#define OMAP_IH1_BASE 0xfffecb00
4029 +#define OMAP_IH2_BASE 0xfffe0000
4030 +
4031 +#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
4032 +#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
4033 +#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
4034 +#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
4035 +#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
4036 +#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
4037 +#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
4038 +
4039 +#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
4040 +#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
4041 +#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
4042 +#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
4043 +#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
4044 +#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
4045 +#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
4046 +
4047 +#define IRQ_ITR_REG_OFFSET 0x00
4048 +#define IRQ_MIR_REG_OFFSET 0x04
4049 +#define IRQ_SIR_IRQ_REG_OFFSET 0x10
4050 +#define IRQ_SIR_FIQ_REG_OFFSET 0x14
4051 +#define IRQ_CONTROL_REG_OFFSET 0x18
4052 +#define IRQ_ISR_REG_OFFSET 0x9c
4053 +#define IRQ_ILR0_REG_OFFSET 0x1c
4054 +#define IRQ_GMR_REG_OFFSET 0xa0
4055 +
4056 +#endif
4057 +
4058 +/*
4059 + * ----------------------------------------------------------------------------
4060 + * System control registers
4061 + * ----------------------------------------------------------------------------
4062 + */
4063 +#define MOD_CONF_CTRL_0 0xfffe1080
4064 +#define MOD_CONF_CTRL_1 0xfffe1110
4065 +
4066 +/*
4067 + * ----------------------------------------------------------------------------
4068 + * Pin multiplexing registers
4069 + * ----------------------------------------------------------------------------
4070 + */
4071 +#define FUNC_MUX_CTRL_0 0xfffe1000
4072 +#define FUNC_MUX_CTRL_1 0xfffe1004
4073 +#define FUNC_MUX_CTRL_2 0xfffe1008
4074 +#define COMP_MODE_CTRL_0 0xfffe100c
4075 +#define FUNC_MUX_CTRL_3 0xfffe1010
4076 +#define FUNC_MUX_CTRL_4 0xfffe1014
4077 +#define FUNC_MUX_CTRL_5 0xfffe1018
4078 +#define FUNC_MUX_CTRL_6 0xfffe101C
4079 +#define FUNC_MUX_CTRL_7 0xfffe1020
4080 +#define FUNC_MUX_CTRL_8 0xfffe1024
4081 +#define FUNC_MUX_CTRL_9 0xfffe1028
4082 +#define FUNC_MUX_CTRL_A 0xfffe102C
4083 +#define FUNC_MUX_CTRL_B 0xfffe1030
4084 +#define FUNC_MUX_CTRL_C 0xfffe1034
4085 +#define FUNC_MUX_CTRL_D 0xfffe1038
4086 +#define PULL_DWN_CTRL_0 0xfffe1040
4087 +#define PULL_DWN_CTRL_1 0xfffe1044
4088 +#define PULL_DWN_CTRL_2 0xfffe1048
4089 +#define PULL_DWN_CTRL_3 0xfffe104c
4090 +#define PULL_DWN_CTRL_4 0xfffe10ac
4091 +
4092 +/* OMAP-1610 specific multiplexing registers */
4093 +#define FUNC_MUX_CTRL_E 0xfffe1090
4094 +#define FUNC_MUX_CTRL_F 0xfffe1094
4095 +#define FUNC_MUX_CTRL_10 0xfffe1098
4096 +#define FUNC_MUX_CTRL_11 0xfffe109c
4097 +#define FUNC_MUX_CTRL_12 0xfffe10a0
4098 +#define PU_PD_SEL_0 0xfffe10b4
4099 +#define PU_PD_SEL_1 0xfffe10b8
4100 +#define PU_PD_SEL_2 0xfffe10bc
4101 +#define PU_PD_SEL_3 0xfffe10c0
4102 +#define PU_PD_SEL_4 0xfffe10c4
4103 +
4104 +/* Timer32K for 1610 and 1710*/
4105 +#define OMAP_TIMER32K_BASE 0xFFFBC400
4106 +
4107 +/*
4108 + * ---------------------------------------------------------------------------
4109 + * TIPB bus interface
4110 + * ---------------------------------------------------------------------------
4111 + */
4112 +#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
4113 +#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
4114 +#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
4115 +#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
4116 +
4117 +/*
4118 + * ----------------------------------------------------------------------------
4119 + * MPUI interface
4120 + * ----------------------------------------------------------------------------
4121 + */
4122 +#define MPUI_BASE (0xfffec900)
4123 +#define MPUI_CTRL (MPUI_BASE + 0x0)
4124 +#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
4125 +#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
4126 +#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
4127 +#define MPUI_STATUS_REG (MPUI_BASE + 0x10)
4128 +#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
4129 +#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
4130 +#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
4131 +
4132 +/*
4133 + * ----------------------------------------------------------------------------
4134 + * LED Pulse Generator
4135 + * ----------------------------------------------------------------------------
4136 + */
4137 +#define OMAP_LPG1_BASE 0xfffbd000
4138 +#define OMAP_LPG2_BASE 0xfffbd800
4139 +#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
4140 +#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
4141 +#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
4142 +#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
4143 +
4144 +/*
4145 + * ----------------------------------------------------------------------------
4146 + * Pulse-Width Light
4147 + * ----------------------------------------------------------------------------
4148 + */
4149 +#define OMAP_PWL_BASE 0xfffb5800
4150 +#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
4151 +#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
4152 +
4153 +/*
4154 + * ---------------------------------------------------------------------------
4155 + * Processor specific defines
4156 + * ---------------------------------------------------------------------------
4157 + */
4158 +
4159 +#include <plat/omap7xx.h>
4160 +#include <plat/omap1510.h>
4161 +#include <plat/omap16xx.h>
4162 +#include <plat/omap24xx.h>
4163 +#include <plat/omap34xx.h>
4164 +#include <plat/omap44xx.h>
4165 +
4166 +#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
4167 --- /dev/null
4168 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/hwa742.h
4169 @@ -0,0 +1,8 @@
4170 +#ifndef _HWA742_H
4171 +#define _HWA742_H
4172 +
4173 +struct hwa742_platform_data {
4174 + unsigned te_connected:1;
4175 +};
4176 +
4177 +#endif
4178 --- /dev/null
4179 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/i2c.h
4180 @@ -0,0 +1,39 @@
4181 +/*
4182 + * Helper module for board specific I2C bus registration
4183 + *
4184 + * Copyright (C) 2009 Nokia Corporation.
4185 + *
4186 + * This program is free software; you can redistribute it and/or
4187 + * modify it under the terms of the GNU General Public License
4188 + * version 2 as published by the Free Software Foundation.
4189 + *
4190 + * This program is distributed in the hope that it will be useful, but
4191 + * WITHOUT ANY WARRANTY; without even the implied warranty of
4192 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
4193 + * General Public License for more details.
4194 + *
4195 + * You should have received a copy of the GNU General Public License
4196 + * along with this program; if not, write to the Free Software
4197 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
4198 + * 02110-1301 USA
4199 + *
4200 + */
4201 +
4202 +#include <linux/i2c.h>
4203 +
4204 +#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
4205 +extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
4206 + struct i2c_board_info const *info,
4207 + unsigned len);
4208 +#else
4209 +static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
4210 + struct i2c_board_info const *info,
4211 + unsigned len)
4212 +{
4213 + return 0;
4214 +}
4215 +#endif
4216 +
4217 +int omap_plat_register_i2c_bus(int bus_id, u32 clkrate,
4218 + struct i2c_board_info const *info,
4219 + unsigned len);
4220 --- /dev/null
4221 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/io.h
4222 @@ -0,0 +1,287 @@
4223 +/*
4224 + * arch/arm/plat-omap/include/mach/io.h
4225 + *
4226 + * IO definitions for TI OMAP processors and boards
4227 + *
4228 + * Copied from arch/arm/mach-sa1100/include/mach/io.h
4229 + * Copyright (C) 1997-1999 Russell King
4230 + *
4231 + * Copyright (C) 2009 Texas Instruments
4232 + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
4233 + *
4234 + * This program is free software; you can redistribute it and/or modify it
4235 + * under the terms of the GNU General Public License as published by the
4236 + * Free Software Foundation; either version 2 of the License, or (at your
4237 + * option) any later version.
4238 + *
4239 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4240 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4241 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4242 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4243 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4244 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4245 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4246 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4247 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4248 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4249 + *
4250 + * You should have received a copy of the GNU General Public License along
4251 + * with this program; if not, write to the Free Software Foundation, Inc.,
4252 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4253 + *
4254 + * Modifications:
4255 + * 06-12-1997 RMK Created.
4256 + * 07-04-1999 RMK Major cleanup
4257 + */
4258 +
4259 +#ifndef __ASM_ARM_ARCH_IO_H
4260 +#define __ASM_ARM_ARCH_IO_H
4261 +
4262 +#include <mach/hardware.h>
4263 +
4264 +#define IO_SPACE_LIMIT 0xffffffff
4265 +
4266 +/*
4267 + * We don't actually have real ISA nor PCI buses, but there is so many
4268 + * drivers out there that might just work if we fake them...
4269 + */
4270 +#define __io(a) __typesafe_io(a)
4271 +#define __mem_pci(a) (a)
4272 +
4273 +/*
4274 + * ----------------------------------------------------------------------------
4275 + * I/O mapping
4276 + * ----------------------------------------------------------------------------
4277 + */
4278 +
4279 +#ifdef __ASSEMBLER__
4280 +#define IOMEM(x) (x)
4281 +#else
4282 +#define IOMEM(x) ((void __force __iomem *)(x))
4283 +#endif
4284 +
4285 +#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
4286 +#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
4287 +
4288 +#define OMAP2_L3_IO_OFFSET 0x90000000
4289 +#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
4290 +
4291 +
4292 +#define OMAP2_L4_IO_OFFSET 0xb2000000
4293 +#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
4294 +
4295 +#define OMAP4_L3_IO_OFFSET 0xb4000000
4296 +#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
4297 +
4298 +#define OMAP4_L3_PER_IO_OFFSET 0xb1100000
4299 +#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
4300 +
4301 +#define OMAP4_GPMC_IO_OFFSET 0xa9000000
4302 +#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
4303 +
4304 +#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
4305 +#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
4306 +
4307 +/*
4308 + * ----------------------------------------------------------------------------
4309 + * Omap1 specific IO mapping
4310 + * ----------------------------------------------------------------------------
4311 + */
4312 +
4313 +#define OMAP1_IO_PHYS 0xFFFB0000
4314 +#define OMAP1_IO_SIZE 0x40000
4315 +#define OMAP1_IO_VIRT (OMAP1_IO_PHYS - OMAP1_IO_OFFSET)
4316 +
4317 +/*
4318 + * ----------------------------------------------------------------------------
4319 + * Omap2 specific IO mapping
4320 + * ----------------------------------------------------------------------------
4321 + */
4322 +
4323 +/* We map both L3 and L4 on OMAP2 */
4324 +#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
4325 +#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
4326 +#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
4327 +#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
4328 +#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
4329 +#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
4330 +
4331 +#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
4332 +#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
4333 +#define L4_WK_243X_SIZE SZ_1M
4334 +#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE
4335 +#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
4336 + /* 0x6e000000 --> 0xfe000000 */
4337 +#define OMAP243X_GPMC_SIZE SZ_1M
4338 +#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
4339 + /* 0x6D000000 --> 0xfd000000 */
4340 +#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
4341 +#define OMAP243X_SDRC_SIZE SZ_1M
4342 +#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
4343 + /* 0x6c000000 --> 0xfc000000 */
4344 +#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
4345 +#define OMAP243X_SMS_SIZE SZ_1M
4346 +
4347 +/* DSP */
4348 +#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
4349 +#define DSP_MEM_24XX_VIRT 0xe0000000
4350 +#define DSP_MEM_24XX_SIZE 0x28000
4351 +#define DSP_IPI_24XX_PHYS OMAP2420_DSP_IPI_BASE /* 0x59000000 */
4352 +#define DSP_IPI_24XX_VIRT 0xe1000000
4353 +#define DSP_IPI_24XX_SIZE SZ_4K
4354 +#define DSP_MMU_24XX_PHYS OMAP2420_DSP_MMU_BASE /* 0x5a000000 */
4355 +#define DSP_MMU_24XX_VIRT 0xe2000000
4356 +#define DSP_MMU_24XX_SIZE SZ_4K
4357 +
4358 +/*
4359 + * ----------------------------------------------------------------------------
4360 + * Omap3 specific IO mapping
4361 + * ----------------------------------------------------------------------------
4362 + */
4363 +
4364 +/* We map both L3 and L4 on OMAP3 */
4365 +#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */
4366 +#define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
4367 +#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
4368 +
4369 +#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */
4370 +#define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
4371 +#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
4372 +
4373 +/*
4374 + * Need to look at the Size 4M for L4.
4375 + * VPOM3430 was not working for Int controller
4376 + */
4377 +
4378 +#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 --> 0xfa300000 */
4379 +#define L4_WK_34XX_VIRT (L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET)
4380 +#define L4_WK_34XX_SIZE SZ_1M
4381 +
4382 +#define L4_PER_34XX_PHYS L4_PER_34XX_BASE
4383 + /* 0x49000000 --> 0xfb000000 */
4384 +#define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
4385 +#define L4_PER_34XX_SIZE SZ_1M
4386 +
4387 +#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE
4388 + /* 0x54000000 --> 0xfe800000 */
4389 +#define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
4390 +#define L4_EMU_34XX_SIZE SZ_8M
4391 +
4392 +#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE
4393 + /* 0x6e000000 --> 0xfe000000 */
4394 +#define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
4395 +#define OMAP34XX_GPMC_SIZE SZ_1M
4396 +
4397 +#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE
4398 + /* 0x6c000000 --> 0xfc000000 */
4399 +#define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
4400 +#define OMAP343X_SMS_SIZE SZ_1M
4401 +
4402 +#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE
4403 + /* 0x6D000000 --> 0xfd000000 */
4404 +#define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
4405 +#define OMAP343X_SDRC_SIZE SZ_1M
4406 +
4407 +/* DSP */
4408 +#define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */
4409 +#define DSP_MEM_34XX_VIRT 0xe0000000
4410 +#define DSP_MEM_34XX_SIZE 0x28000
4411 +#define DSP_IPI_34XX_PHYS OMAP34XX_DSP_IPI_BASE /* 0x59000000 */
4412 +#define DSP_IPI_34XX_VIRT 0xe1000000
4413 +#define DSP_IPI_34XX_SIZE SZ_4K
4414 +#define DSP_MMU_34XX_PHYS OMAP34XX_DSP_MMU_BASE /* 0x5a000000 */
4415 +#define DSP_MMU_34XX_VIRT 0xe2000000
4416 +#define DSP_MMU_34XX_SIZE SZ_4K
4417 +
4418 +/*
4419 + * ----------------------------------------------------------------------------
4420 + * Omap4 specific IO mapping
4421 + * ----------------------------------------------------------------------------
4422 + */
4423 +
4424 +/* We map both L3 and L4 on OMAP4 */
4425 +#define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */
4426 +#define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
4427 +#define L3_44XX_SIZE SZ_1M
4428 +
4429 +#define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */
4430 +#define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4431 +#define L4_44XX_SIZE SZ_4M
4432 +
4433 +
4434 +#define L4_WK_44XX_PHYS L4_WK_44XX_BASE /* 0x4a300000 --> 0xfc300000 */
4435 +#define L4_WK_44XX_VIRT (L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4436 +#define L4_WK_44XX_SIZE SZ_1M
4437 +
4438 +#define L4_PER_44XX_PHYS L4_PER_44XX_BASE
4439 + /* 0x48000000 --> 0xfa000000 */
4440 +#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4441 +#define L4_PER_44XX_SIZE SZ_4M
4442 +
4443 +#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE
4444 + /* 0x49000000 --> 0xfb000000 */
4445 +#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4446 +#define L4_ABE_44XX_SIZE SZ_1M
4447 +
4448 +#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
4449 + /* 0x54000000 --> 0xfe800000 */
4450 +#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
4451 +#define L4_EMU_44XX_SIZE SZ_8M
4452 +
4453 +#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE
4454 + /* 0x50000000 --> 0xf9000000 */
4455 +#define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
4456 +#define OMAP44XX_GPMC_SIZE SZ_1M
4457 +
4458 +
4459 +#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE
4460 + /* 0x4c000000 --> 0xfd100000 */
4461 +#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
4462 +#define OMAP44XX_EMIF1_SIZE SZ_1M
4463 +
4464 +#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
4465 + /* 0x4d000000 --> 0xfd200000 */
4466 +#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
4467 +#define OMAP44XX_EMIF2_SIZE SZ_1M
4468 +
4469 +#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
4470 + /* 0x4e000000 --> 0xfd300000 */
4471 +#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
4472 +#define OMAP44XX_DMM_SIZE SZ_1M
4473 +/*
4474 + * ----------------------------------------------------------------------------
4475 + * Omap specific register access
4476 + * ----------------------------------------------------------------------------
4477 + */
4478 +
4479 +#ifndef __ASSEMBLER__
4480 +
4481 +/*
4482 + * NOTE: Please use ioremap + __raw_read/write where possible instead of these
4483 + */
4484 +
4485 +extern u8 omap_readb(u32 pa);
4486 +extern u16 omap_readw(u32 pa);
4487 +extern u32 omap_readl(u32 pa);
4488 +extern void omap_writeb(u8 v, u32 pa);
4489 +extern void omap_writew(u16 v, u32 pa);
4490 +extern void omap_writel(u32 v, u32 pa);
4491 +
4492 +struct omap_sdrc_params;
4493 +
4494 +extern void omap1_map_common_io(void);
4495 +extern void omap1_init_common_hw(void);
4496 +
4497 +extern void omap2_map_common_io(void);
4498 +extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
4499 + struct omap_sdrc_params *sdrc_cs1);
4500 +
4501 +#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
4502 +#define __arch_iounmap(v) omap_iounmap(v)
4503 +
4504 +void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
4505 +void omap_iounmap(volatile void __iomem *addr);
4506 +
4507 +#endif
4508 +
4509 +#endif
4510 --- /dev/null
4511 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/iommu2.h
4512 @@ -0,0 +1,96 @@
4513 +/*
4514 + * omap iommu: omap2 architecture specific definitions
4515 + *
4516 + * Copyright (C) 2008-2009 Nokia Corporation
4517 + *
4518 + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
4519 + *
4520 + * This program is free software; you can redistribute it and/or modify
4521 + * it under the terms of the GNU General Public License version 2 as
4522 + * published by the Free Software Foundation.
4523 + */
4524 +
4525 +#ifndef __MACH_IOMMU2_H
4526 +#define __MACH_IOMMU2_H
4527 +
4528 +#include <linux/io.h>
4529 +
4530 +/*
4531 + * MMU Register offsets
4532 + */
4533 +#define MMU_REVISION 0x00
4534 +#define MMU_SYSCONFIG 0x10
4535 +#define MMU_SYSSTATUS 0x14
4536 +#define MMU_IRQSTATUS 0x18
4537 +#define MMU_IRQENABLE 0x1c
4538 +#define MMU_WALKING_ST 0x40
4539 +#define MMU_CNTL 0x44
4540 +#define MMU_FAULT_AD 0x48
4541 +#define MMU_TTB 0x4c
4542 +#define MMU_LOCK 0x50
4543 +#define MMU_LD_TLB 0x54
4544 +#define MMU_CAM 0x58
4545 +#define MMU_RAM 0x5c
4546 +#define MMU_GFLUSH 0x60
4547 +#define MMU_FLUSH_ENTRY 0x64
4548 +#define MMU_READ_CAM 0x68
4549 +#define MMU_READ_RAM 0x6c
4550 +#define MMU_EMU_FAULT_AD 0x70
4551 +
4552 +#define MMU_REG_SIZE 256
4553 +
4554 +/*
4555 + * MMU Register bit definitions
4556 + */
4557 +#define MMU_LOCK_BASE_SHIFT 10
4558 +#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
4559 +#define MMU_LOCK_BASE(x) \
4560 + ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
4561 +
4562 +#define MMU_LOCK_VICT_SHIFT 4
4563 +#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
4564 +#define MMU_LOCK_VICT(x) \
4565 + ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
4566 +
4567 +#define MMU_CAM_VATAG_SHIFT 12
4568 +#define MMU_CAM_VATAG_MASK \
4569 + ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
4570 +#define MMU_CAM_P (1 << 3)
4571 +#define MMU_CAM_V (1 << 2)
4572 +#define MMU_CAM_PGSZ_MASK 3
4573 +#define MMU_CAM_PGSZ_1M (0 << 0)
4574 +#define MMU_CAM_PGSZ_64K (1 << 0)
4575 +#define MMU_CAM_PGSZ_4K (2 << 0)
4576 +#define MMU_CAM_PGSZ_16M (3 << 0)
4577 +
4578 +#define MMU_RAM_PADDR_SHIFT 12
4579 +#define MMU_RAM_PADDR_MASK \
4580 + ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
4581 +#define MMU_RAM_ENDIAN_SHIFT 9
4582 +#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
4583 +#define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT)
4584 +#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
4585 +#define MMU_RAM_ELSZ_SHIFT 7
4586 +#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
4587 +#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
4588 +#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
4589 +#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
4590 +#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
4591 +#define MMU_RAM_MIXED_SHIFT 6
4592 +#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
4593 +#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
4594 +
4595 +/*
4596 + * register accessors
4597 + */
4598 +static inline u32 iommu_read_reg(struct iommu *obj, size_t offs)
4599 +{
4600 + return __raw_readl(obj->regbase + offs);
4601 +}
4602 +
4603 +static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs)
4604 +{
4605 + __raw_writel(val, obj->regbase + offs);
4606 +}
4607 +
4608 +#endif /* __MACH_IOMMU2_H */
4609 --- /dev/null
4610 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/iommu.h
4611 @@ -0,0 +1,168 @@
4612 +/*
4613 + * omap iommu: main structures
4614 + *
4615 + * Copyright (C) 2008-2009 Nokia Corporation
4616 + *
4617 + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
4618 + *
4619 + * This program is free software; you can redistribute it and/or modify
4620 + * it under the terms of the GNU General Public License version 2 as
4621 + * published by the Free Software Foundation.
4622 + */
4623 +
4624 +#ifndef __MACH_IOMMU_H
4625 +#define __MACH_IOMMU_H
4626 +
4627 +struct iotlb_entry {
4628 + u32 da;
4629 + u32 pa;
4630 + u32 pgsz, prsvd, valid;
4631 + union {
4632 + u16 ap;
4633 + struct {
4634 + u32 endian, elsz, mixed;
4635 + };
4636 + };
4637 +};
4638 +
4639 +struct iommu {
4640 + const char *name;
4641 + struct module *owner;
4642 + struct clk *clk;
4643 + void __iomem *regbase;
4644 + struct device *dev;
4645 +
4646 + unsigned int refcount;
4647 + struct mutex iommu_lock; /* global for this whole object */
4648 +
4649 + /*
4650 + * We don't change iopgd for a situation like pgd for a task,
4651 + * but share it globally for each iommu.
4652 + */
4653 + u32 *iopgd;
4654 + spinlock_t page_table_lock; /* protect iopgd */
4655 +
4656 + int nr_tlb_entries;
4657 +
4658 + struct list_head mmap;
4659 + struct mutex mmap_lock; /* protect mmap */
4660 +
4661 + int (*isr)(struct iommu *obj);
4662 +
4663 + void *ctx; /* iommu context: registres saved area */
4664 +};
4665 +
4666 +struct cr_regs {
4667 + union {
4668 + struct {
4669 + u16 cam_l;
4670 + u16 cam_h;
4671 + };
4672 + u32 cam;
4673 + };
4674 + union {
4675 + struct {
4676 + u16 ram_l;
4677 + u16 ram_h;
4678 + };
4679 + u32 ram;
4680 + };
4681 +};
4682 +
4683 +struct iotlb_lock {
4684 + short base;
4685 + short vict;
4686 +};
4687 +
4688 +/* architecture specific functions */
4689 +struct iommu_functions {
4690 + unsigned long version;
4691 +
4692 + int (*enable)(struct iommu *obj);
4693 + void (*disable)(struct iommu *obj);
4694 + u32 (*fault_isr)(struct iommu *obj, u32 *ra);
4695 +
4696 + void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
4697 + void (*tlb_load_cr)(struct iommu *obj, struct cr_regs *cr);
4698 +
4699 + struct cr_regs *(*alloc_cr)(struct iommu *obj, struct iotlb_entry *e);
4700 + int (*cr_valid)(struct cr_regs *cr);
4701 + u32 (*cr_to_virt)(struct cr_regs *cr);
4702 + void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
4703 + ssize_t (*dump_cr)(struct iommu *obj, struct cr_regs *cr, char *buf);
4704 +
4705 + u32 (*get_pte_attr)(struct iotlb_entry *e);
4706 +
4707 + void (*save_ctx)(struct iommu *obj);
4708 + void (*restore_ctx)(struct iommu *obj);
4709 + ssize_t (*dump_ctx)(struct iommu *obj, char *buf, ssize_t len);
4710 +};
4711 +
4712 +struct iommu_platform_data {
4713 + const char *name;
4714 + const char *clk_name;
4715 + const int nr_tlb_entries;
4716 +};
4717 +
4718 +#if defined(CONFIG_ARCH_OMAP1)
4719 +#error "iommu for this processor not implemented yet"
4720 +#else
4721 +#include <plat/iommu2.h>
4722 +#endif
4723 +
4724 +/*
4725 + * utilities for super page(16MB, 1MB, 64KB and 4KB)
4726 + */
4727 +
4728 +#define iopgsz_max(bytes) \
4729 + (((bytes) >= SZ_16M) ? SZ_16M : \
4730 + ((bytes) >= SZ_1M) ? SZ_1M : \
4731 + ((bytes) >= SZ_64K) ? SZ_64K : \
4732 + ((bytes) >= SZ_4K) ? SZ_4K : 0)
4733 +
4734 +#define bytes_to_iopgsz(bytes) \
4735 + (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
4736 + ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
4737 + ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
4738 + ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
4739 +
4740 +#define iopgsz_to_bytes(iopgsz) \
4741 + (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
4742 + ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
4743 + ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
4744 + ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
4745 +
4746 +#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
4747 +
4748 +/*
4749 + * global functions
4750 + */
4751 +extern u32 iommu_arch_version(void);
4752 +
4753 +extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
4754 +extern u32 iotlb_cr_to_virt(struct cr_regs *cr);
4755 +
4756 +extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e);
4757 +extern void flush_iotlb_page(struct iommu *obj, u32 da);
4758 +extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
4759 +extern void flush_iotlb_all(struct iommu *obj);
4760 +
4761 +extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
4762 +extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
4763 +
4764 +extern struct iommu *iommu_get(const char *name);
4765 +extern void iommu_put(struct iommu *obj);
4766 +
4767 +extern void iommu_save_ctx(struct iommu *obj);
4768 +extern void iommu_restore_ctx(struct iommu *obj);
4769 +
4770 +extern int install_iommu_arch(const struct iommu_functions *ops);
4771 +extern void uninstall_iommu_arch(const struct iommu_functions *ops);
4772 +
4773 +extern int foreach_iommu_device(void *data,
4774 + int (*fn)(struct device *, void *));
4775 +
4776 +extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len);
4777 +extern size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t len);
4778 +
4779 +#endif /* __MACH_IOMMU_H */
4780 --- /dev/null
4781 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/iovmm.h
4782 @@ -0,0 +1,94 @@
4783 +/*
4784 + * omap iommu: simple virtual address space management
4785 + *
4786 + * Copyright (C) 2008-2009 Nokia Corporation
4787 + *
4788 + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
4789 + *
4790 + * This program is free software; you can redistribute it and/or modify
4791 + * it under the terms of the GNU General Public License version 2 as
4792 + * published by the Free Software Foundation.
4793 + */
4794 +
4795 +#ifndef __IOMMU_MMAP_H
4796 +#define __IOMMU_MMAP_H
4797 +
4798 +struct iovm_struct {
4799 + struct iommu *iommu; /* iommu object which this belongs to */
4800 + u32 da_start; /* area definition */
4801 + u32 da_end;
4802 + u32 flags; /* IOVMF_: see below */
4803 + struct list_head list; /* linked in ascending order */
4804 + const struct sg_table *sgt; /* keep 'page' <-> 'da' mapping */
4805 + void *va; /* mpu side mapped address */
4806 +};
4807 +
4808 +/*
4809 + * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma)
4810 + *
4811 + * lower 16 bit is used for h/w and upper 16 bit is for s/w.
4812 + */
4813 +#define IOVMF_SW_SHIFT 16
4814 +#define IOVMF_HW_SIZE (1 << IOVMF_SW_SHIFT)
4815 +#define IOVMF_HW_MASK (IOVMF_HW_SIZE - 1)
4816 +#define IOVMF_SW_MASK (~IOVMF_HW_MASK)UL
4817 +
4818 +/*
4819 + * iovma: h/w flags derived from cam and ram attribute
4820 + */
4821 +#define IOVMF_CAM_MASK (~((1 << 10) - 1))
4822 +#define IOVMF_RAM_MASK (~IOVMF_CAM_MASK)
4823 +
4824 +#define IOVMF_PGSZ_MASK (3 << 0)
4825 +#define IOVMF_PGSZ_1M MMU_CAM_PGSZ_1M
4826 +#define IOVMF_PGSZ_64K MMU_CAM_PGSZ_64K
4827 +#define IOVMF_PGSZ_4K MMU_CAM_PGSZ_4K
4828 +#define IOVMF_PGSZ_16M MMU_CAM_PGSZ_16M
4829 +
4830 +#define IOVMF_ENDIAN_MASK (1 << 9)
4831 +#define IOVMF_ENDIAN_BIG MMU_RAM_ENDIAN_BIG
4832 +#define IOVMF_ENDIAN_LITTLE MMU_RAM_ENDIAN_LITTLE
4833 +
4834 +#define IOVMF_ELSZ_MASK (3 << 7)
4835 +#define IOVMF_ELSZ_8 MMU_RAM_ELSZ_8
4836 +#define IOVMF_ELSZ_16 MMU_RAM_ELSZ_16
4837 +#define IOVMF_ELSZ_32 MMU_RAM_ELSZ_32
4838 +#define IOVMF_ELSZ_NONE MMU_RAM_ELSZ_NONE
4839 +
4840 +#define IOVMF_MIXED_MASK (1 << 6)
4841 +#define IOVMF_MIXED MMU_RAM_MIXED
4842 +
4843 +/*
4844 + * iovma: s/w flags, used for mapping and umapping internally.
4845 + */
4846 +#define IOVMF_MMIO (1 << IOVMF_SW_SHIFT)
4847 +#define IOVMF_ALLOC (2 << IOVMF_SW_SHIFT)
4848 +#define IOVMF_ALLOC_MASK (3 << IOVMF_SW_SHIFT)
4849 +
4850 +/* "superpages" is supported just with physically linear pages */
4851 +#define IOVMF_DISCONT (1 << (2 + IOVMF_SW_SHIFT))
4852 +#define IOVMF_LINEAR (2 << (2 + IOVMF_SW_SHIFT))
4853 +#define IOVMF_LINEAR_MASK (3 << (2 + IOVMF_SW_SHIFT))
4854 +
4855 +#define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT))
4856 +#define IOVMF_DA_ANON (2 << (4 + IOVMF_SW_SHIFT))
4857 +#define IOVMF_DA_MASK (3 << (4 + IOVMF_SW_SHIFT))
4858 +
4859 +
4860 +extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da);
4861 +extern u32 iommu_vmap(struct iommu *obj, u32 da,
4862 + const struct sg_table *sgt, u32 flags);
4863 +extern struct sg_table *iommu_vunmap(struct iommu *obj, u32 da);
4864 +extern u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes,
4865 + u32 flags);
4866 +extern void iommu_vfree(struct iommu *obj, const u32 da);
4867 +extern u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes,
4868 + u32 flags);
4869 +extern void iommu_kunmap(struct iommu *obj, u32 da);
4870 +extern u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes,
4871 + u32 flags);
4872 +extern void iommu_kfree(struct iommu *obj, u32 da);
4873 +
4874 +extern void *da_to_va(struct iommu *obj, u32 da);
4875 +
4876 +#endif /* __IOMMU_MMAP_H */
4877 --- /dev/null
4878 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/irda.h
4879 @@ -0,0 +1,33 @@
4880 +/*
4881 + * arch/arm/plat-omap/include/mach/irda.h
4882 + *
4883 + * Copyright (C) 2005-2006 Komal Shah <komal_shah802003@yahoo.com>
4884 + *
4885 + * This program is free software; you can redistribute it and/or modify
4886 + * it under the terms of the GNU General Public License version 2 as
4887 + * published by the Free Software Foundation.
4888 + */
4889 +#ifndef ASMARM_ARCH_IRDA_H
4890 +#define ASMARM_ARCH_IRDA_H
4891 +
4892 +/* board specific transceiver capabilities */
4893 +
4894 +#define IR_SEL 1 /* Selects IrDA */
4895 +#define IR_SIRMODE 2
4896 +#define IR_FIRMODE 4
4897 +#define IR_MIRMODE 8
4898 +
4899 +struct omap_irda_config {
4900 + int transceiver_cap;
4901 + int (*transceiver_mode)(struct device *dev, int mode);
4902 + int (*select_irda)(struct device *dev, int state);
4903 + int rx_channel;
4904 + int tx_channel;
4905 + unsigned long dest_start;
4906 + unsigned long src_start;
4907 + int tx_trigger;
4908 + int rx_trigger;
4909 + int mode;
4910 +};
4911 +
4912 +#endif
4913 --- /dev/null
4914 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/irqs.h
4915 @@ -0,0 +1,506 @@
4916 +/*
4917 + * arch/arm/plat-omap/include/mach/irqs.h
4918 + *
4919 + * Copyright (C) Greg Lonnon 2001
4920 + * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
4921 + *
4922 + * Copyright (C) 2009 Texas Instruments
4923 + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
4924 + *
4925 + * This program is free software; you can redistribute it and/or modify
4926 + * it under the terms of the GNU General Public License as published by
4927 + * the Free Software Foundation; either version 2 of the License, or
4928 + * (at your option) any later version.
4929 + *
4930 + * This program is distributed in the hope that it will be useful,
4931 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4932 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4933 + * GNU General Public License for more details.
4934 + *
4935 + * You should have received a copy of the GNU General Public License
4936 + * along with this program; if not, write to the Free Software
4937 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4938 + *
4939 + * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
4940 + * are different.
4941 + */
4942 +
4943 +#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
4944 +#define __ASM_ARCH_OMAP15XX_IRQS_H
4945 +
4946 +/*
4947 + * IRQ numbers for interrupt handler 1
4948 + *
4949 + * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
4950 + *
4951 + */
4952 +#define INT_CAMERA 1
4953 +#define INT_FIQ 3
4954 +#define INT_RTDX 6
4955 +#define INT_DSP_MMU_ABORT 7
4956 +#define INT_HOST 8
4957 +#define INT_ABORT 9
4958 +#define INT_BRIDGE_PRIV 13
4959 +#define INT_GPIO_BANK1 14
4960 +#define INT_UART3 15
4961 +#define INT_TIMER3 16
4962 +#define INT_DMA_CH0_6 19
4963 +#define INT_DMA_CH1_7 20
4964 +#define INT_DMA_CH2_8 21
4965 +#define INT_DMA_CH3 22
4966 +#define INT_DMA_CH4 23
4967 +#define INT_DMA_CH5 24
4968 +#define INT_DMA_LCD 25
4969 +#define INT_TIMER1 26
4970 +#define INT_WD_TIMER 27
4971 +#define INT_BRIDGE_PUB 28
4972 +#define INT_TIMER2 30
4973 +#define INT_LCD_CTRL 31
4974 +
4975 +/*
4976 + * OMAP-1510 specific IRQ numbers for interrupt handler 1
4977 + */
4978 +#define INT_1510_IH2_IRQ 0
4979 +#define INT_1510_RES2 2
4980 +#define INT_1510_SPI_TX 4
4981 +#define INT_1510_SPI_RX 5
4982 +#define INT_1510_DSP_MAILBOX1 10
4983 +#define INT_1510_DSP_MAILBOX2 11
4984 +#define INT_1510_RES12 12
4985 +#define INT_1510_LB_MMU 17
4986 +#define INT_1510_RES18 18
4987 +#define INT_1510_LOCAL_BUS 29
4988 +
4989 +/*
4990 + * OMAP-1610 specific IRQ numbers for interrupt handler 1
4991 + */
4992 +#define INT_1610_IH2_IRQ 0
4993 +#define INT_1610_IH2_FIQ 2
4994 +#define INT_1610_McBSP2_TX 4
4995 +#define INT_1610_McBSP2_RX 5
4996 +#define INT_1610_DSP_MAILBOX1 10
4997 +#define INT_1610_DSP_MAILBOX2 11
4998 +#define INT_1610_LCD_LINE 12
4999 +#define INT_1610_GPTIMER1 17
5000 +#define INT_1610_GPTIMER2 18
5001 +#define INT_1610_SSR_FIFO_0 29
5002 +
5003 +/*
5004 + * OMAP-7xx specific IRQ numbers for interrupt handler 1
5005 + */
5006 +#define INT_7XX_IH2_FIQ 0
5007 +#define INT_7XX_IH2_IRQ 1
5008 +#define INT_7XX_USB_NON_ISO 2
5009 +#define INT_7XX_USB_ISO 3
5010 +#define INT_7XX_ICR 4
5011 +#define INT_7XX_EAC 5
5012 +#define INT_7XX_GPIO_BANK1 6
5013 +#define INT_7XX_GPIO_BANK2 7
5014 +#define INT_7XX_GPIO_BANK3 8
5015 +#define INT_7XX_McBSP2TX 10
5016 +#define INT_7XX_McBSP2RX 11
5017 +#define INT_7XX_McBSP2RX_OVF 12
5018 +#define INT_7XX_LCD_LINE 14
5019 +#define INT_7XX_GSM_PROTECT 15
5020 +#define INT_7XX_TIMER3 16
5021 +#define INT_7XX_GPIO_BANK5 17
5022 +#define INT_7XX_GPIO_BANK6 18
5023 +#define INT_7XX_SPGIO_WR 29
5024 +
5025 +/*
5026 + * IRQ numbers for interrupt handler 2
5027 + *
5028 + * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
5029 + */
5030 +#define IH2_BASE 32
5031 +
5032 +#define INT_KEYBOARD (1 + IH2_BASE)
5033 +#define INT_uWireTX (2 + IH2_BASE)
5034 +#define INT_uWireRX (3 + IH2_BASE)
5035 +#define INT_I2C (4 + IH2_BASE)
5036 +#define INT_MPUIO (5 + IH2_BASE)
5037 +#define INT_USB_HHC_1 (6 + IH2_BASE)
5038 +#define INT_McBSP3TX (10 + IH2_BASE)
5039 +#define INT_McBSP3RX (11 + IH2_BASE)
5040 +#define INT_McBSP1TX (12 + IH2_BASE)
5041 +#define INT_McBSP1RX (13 + IH2_BASE)
5042 +#define INT_UART1 (14 + IH2_BASE)
5043 +#define INT_UART2 (15 + IH2_BASE)
5044 +#define INT_BT_MCSI1TX (16 + IH2_BASE)
5045 +#define INT_BT_MCSI1RX (17 + IH2_BASE)
5046 +#define INT_SOSSI_MATCH (19 + IH2_BASE)
5047 +#define INT_USB_W2FC (20 + IH2_BASE)
5048 +#define INT_1WIRE (21 + IH2_BASE)
5049 +#define INT_OS_TIMER (22 + IH2_BASE)
5050 +#define INT_MMC (23 + IH2_BASE)
5051 +#define INT_GAUGE_32K (24 + IH2_BASE)
5052 +#define INT_RTC_TIMER (25 + IH2_BASE)
5053 +#define INT_RTC_ALARM (26 + IH2_BASE)
5054 +#define INT_MEM_STICK (27 + IH2_BASE)
5055 +
5056 +/*
5057 + * OMAP-1510 specific IRQ numbers for interrupt handler 2
5058 + */
5059 +#define INT_1510_DSP_MMU (28 + IH2_BASE)
5060 +#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
5061 +
5062 +/*
5063 + * OMAP-1610 specific IRQ numbers for interrupt handler 2
5064 + */
5065 +#define INT_1610_FAC (0 + IH2_BASE)
5066 +#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
5067 +#define INT_1610_USB_OTG (8 + IH2_BASE)
5068 +#define INT_1610_SoSSI (9 + IH2_BASE)
5069 +#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
5070 +#define INT_1610_DSP_MMU (28 + IH2_BASE)
5071 +#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
5072 +#define INT_1610_STI (32 + IH2_BASE)
5073 +#define INT_1610_STI_WAKEUP (33 + IH2_BASE)
5074 +#define INT_1610_GPTIMER3 (34 + IH2_BASE)
5075 +#define INT_1610_GPTIMER4 (35 + IH2_BASE)
5076 +#define INT_1610_GPTIMER5 (36 + IH2_BASE)
5077 +#define INT_1610_GPTIMER6 (37 + IH2_BASE)
5078 +#define INT_1610_GPTIMER7 (38 + IH2_BASE)
5079 +#define INT_1610_GPTIMER8 (39 + IH2_BASE)
5080 +#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
5081 +#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
5082 +#define INT_1610_MMC2 (42 + IH2_BASE)
5083 +#define INT_1610_CF (43 + IH2_BASE)
5084 +#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
5085 +#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
5086 +#define INT_1610_SPI (49 + IH2_BASE)
5087 +#define INT_1610_DMA_CH6 (53 + IH2_BASE)
5088 +#define INT_1610_DMA_CH7 (54 + IH2_BASE)
5089 +#define INT_1610_DMA_CH8 (55 + IH2_BASE)
5090 +#define INT_1610_DMA_CH9 (56 + IH2_BASE)
5091 +#define INT_1610_DMA_CH10 (57 + IH2_BASE)
5092 +#define INT_1610_DMA_CH11 (58 + IH2_BASE)
5093 +#define INT_1610_DMA_CH12 (59 + IH2_BASE)
5094 +#define INT_1610_DMA_CH13 (60 + IH2_BASE)
5095 +#define INT_1610_DMA_CH14 (61 + IH2_BASE)
5096 +#define INT_1610_DMA_CH15 (62 + IH2_BASE)
5097 +#define INT_1610_NAND (63 + IH2_BASE)
5098 +#define INT_1610_SHA1MD5 (91 + IH2_BASE)
5099 +
5100 +/*
5101 + * OMAP-7xx specific IRQ numbers for interrupt handler 2
5102 + */
5103 +#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
5104 +#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
5105 +#define INT_7XX_CFCD (2 + IH2_BASE)
5106 +#define INT_7XX_CFIREQ (3 + IH2_BASE)
5107 +#define INT_7XX_I2C (4 + IH2_BASE)
5108 +#define INT_7XX_PCC (5 + IH2_BASE)
5109 +#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
5110 +#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
5111 +#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
5112 +#define INT_7XX_VLYNQ (9 + IH2_BASE)
5113 +#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
5114 +#define INT_7XX_McBSP1TX (11 + IH2_BASE)
5115 +#define INT_7XX_McBSP1RX (12 + IH2_BASE)
5116 +#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
5117 +#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
5118 +#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
5119 +#define INT_7XX_MCSI (16 + IH2_BASE)
5120 +#define INT_7XX_uWireTX (17 + IH2_BASE)
5121 +#define INT_7XX_uWireRX (18 + IH2_BASE)
5122 +#define INT_7XX_SMC_CD (19 + IH2_BASE)
5123 +#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
5124 +#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
5125 +#define INT_7XX_TIMER32K (22 + IH2_BASE)
5126 +#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
5127 +#define INT_7XX_UPLD (24 + IH2_BASE)
5128 +#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
5129 +#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
5130 +#define INT_7XX_USB_GENI (29 + IH2_BASE)
5131 +#define INT_7XX_USB_OTG (30 + IH2_BASE)
5132 +#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
5133 +#define INT_7XX_RNG (32 + IH2_BASE)
5134 +#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
5135 +#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
5136 +#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
5137 +#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
5138 +#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
5139 +#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
5140 +#define INT_7XX_MPUIO (39 + IH2_BASE)
5141 +#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
5142 +#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
5143 +#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
5144 +#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
5145 +#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
5146 +#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
5147 +#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
5148 +#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
5149 +#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
5150 +#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
5151 +#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
5152 +#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
5153 +#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
5154 +#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
5155 +#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
5156 +#define INT_7XX_NAND (63 + IH2_BASE)
5157 +
5158 +#define INT_24XX_SYS_NIRQ 7
5159 +#define INT_24XX_SDMA_IRQ0 12
5160 +#define INT_24XX_SDMA_IRQ1 13
5161 +#define INT_24XX_SDMA_IRQ2 14
5162 +#define INT_24XX_SDMA_IRQ3 15
5163 +#define INT_24XX_CAM_IRQ 24
5164 +#define INT_24XX_DSS_IRQ 25
5165 +#define INT_24XX_MAIL_U0_MPU 26
5166 +#define INT_24XX_DSP_UMA 27
5167 +#define INT_24XX_DSP_MMU 28
5168 +#define INT_24XX_GPIO_BANK1 29
5169 +#define INT_24XX_GPIO_BANK2 30
5170 +#define INT_24XX_GPIO_BANK3 31
5171 +#define INT_24XX_GPIO_BANK4 32
5172 +#define INT_24XX_GPIO_BANK5 33
5173 +#define INT_24XX_MAIL_U3_MPU 34
5174 +#define INT_24XX_GPTIMER1 37
5175 +#define INT_24XX_GPTIMER2 38
5176 +#define INT_24XX_GPTIMER3 39
5177 +#define INT_24XX_GPTIMER4 40
5178 +#define INT_24XX_GPTIMER5 41
5179 +#define INT_24XX_GPTIMER6 42
5180 +#define INT_24XX_GPTIMER7 43
5181 +#define INT_24XX_GPTIMER8 44
5182 +#define INT_24XX_GPTIMER9 45
5183 +#define INT_24XX_GPTIMER10 46
5184 +#define INT_24XX_GPTIMER11 47
5185 +#define INT_24XX_GPTIMER12 48
5186 +#define INT_24XX_SHA1MD5 51
5187 +#define INT_24XX_MCBSP4_IRQ_TX 54
5188 +#define INT_24XX_MCBSP4_IRQ_RX 55
5189 +#define INT_24XX_I2C1_IRQ 56
5190 +#define INT_24XX_I2C2_IRQ 57
5191 +#define INT_24XX_HDQ_IRQ 58
5192 +#define INT_24XX_MCBSP1_IRQ_TX 59
5193 +#define INT_24XX_MCBSP1_IRQ_RX 60
5194 +#define INT_24XX_MCBSP2_IRQ_TX 62
5195 +#define INT_24XX_MCBSP2_IRQ_RX 63
5196 +#define INT_24XX_SPI1_IRQ 65
5197 +#define INT_24XX_SPI2_IRQ 66
5198 +#define INT_24XX_UART1_IRQ 72
5199 +#define INT_24XX_UART2_IRQ 73
5200 +#define INT_24XX_UART3_IRQ 74
5201 +#define INT_24XX_USB_IRQ_GEN 75
5202 +#define INT_24XX_USB_IRQ_NISO 76
5203 +#define INT_24XX_USB_IRQ_ISO 77
5204 +#define INT_24XX_USB_IRQ_HGEN 78
5205 +#define INT_24XX_USB_IRQ_HSOF 79
5206 +#define INT_24XX_USB_IRQ_OTG 80
5207 +#define INT_24XX_MCBSP5_IRQ_TX 81
5208 +#define INT_24XX_MCBSP5_IRQ_RX 82
5209 +#define INT_24XX_MMC_IRQ 83
5210 +#define INT_24XX_MMC2_IRQ 86
5211 +#define INT_24XX_MCBSP3_IRQ_TX 89
5212 +#define INT_24XX_MCBSP3_IRQ_RX 90
5213 +#define INT_24XX_SPI3_IRQ 91
5214 +
5215 +#define INT_243X_MCBSP2_IRQ 16
5216 +#define INT_243X_MCBSP3_IRQ 17
5217 +#define INT_243X_MCBSP4_IRQ 18
5218 +#define INT_243X_MCBSP5_IRQ 19
5219 +#define INT_243X_MCBSP1_IRQ 64
5220 +#define INT_243X_HS_USB_MC 92
5221 +#define INT_243X_HS_USB_DMA 93
5222 +#define INT_243X_CARKIT_IRQ 94
5223 +
5224 +#define INT_34XX_BENCH_MPU_EMUL 3
5225 +#define INT_34XX_ST_MCBSP2_IRQ 4
5226 +#define INT_34XX_ST_MCBSP3_IRQ 5
5227 +#define INT_34XX_SSM_ABORT_IRQ 6
5228 +#define INT_34XX_SYS_NIRQ 7
5229 +#define INT_34XX_D2D_FW_IRQ 8
5230 +#define INT_34XX_PRCM_MPU_IRQ 11
5231 +#define INT_34XX_MCBSP1_IRQ 16
5232 +#define INT_34XX_MCBSP2_IRQ 17
5233 +#define INT_34XX_MCBSP3_IRQ 22
5234 +#define INT_34XX_MCBSP4_IRQ 23
5235 +#define INT_34XX_CAM_IRQ 24
5236 +#define INT_34XX_MCBSP5_IRQ 27
5237 +#define INT_34XX_GPIO_BANK1 29
5238 +#define INT_34XX_GPIO_BANK2 30
5239 +#define INT_34XX_GPIO_BANK3 31
5240 +#define INT_34XX_GPIO_BANK4 32
5241 +#define INT_34XX_GPIO_BANK5 33
5242 +#define INT_34XX_GPIO_BANK6 34
5243 +#define INT_34XX_USIM_IRQ 35
5244 +#define INT_34XX_WDT3_IRQ 36
5245 +#define INT_34XX_SPI4_IRQ 48
5246 +#define INT_34XX_SHA1MD52_IRQ 49
5247 +#define INT_34XX_FPKA_READY_IRQ 50
5248 +#define INT_34XX_SHA1MD51_IRQ 51
5249 +#define INT_34XX_RNG_IRQ 52
5250 +#define INT_34XX_I2C3_IRQ 61
5251 +#define INT_34XX_FPKA_ERROR_IRQ 64
5252 +#define INT_34XX_PBIAS_IRQ 75
5253 +#define INT_34XX_OHCI_IRQ 76
5254 +#define INT_34XX_EHCI_IRQ 77
5255 +#define INT_34XX_TLL_IRQ 78
5256 +#define INT_34XX_PARTHASH_IRQ 79
5257 +#define INT_34XX_MMC3_IRQ 94
5258 +#define INT_34XX_GPT12_IRQ 95
5259 +
5260 +#define INT_34XX_BENCH_MPU_EMUL 3
5261 +
5262 +
5263 +#define IRQ_GIC_START 32
5264 +#define INT_44XX_LOCALTIMER_IRQ 29
5265 +#define INT_44XX_LOCALWDT_IRQ 30
5266 +
5267 +#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START)
5268 +#define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START)
5269 +#define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START)
5270 +#define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START)
5271 +#define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START)
5272 +#define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START)
5273 +#define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START)
5274 +#define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START)
5275 +#define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START)
5276 +#define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START)
5277 +#define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START)
5278 +#define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START)
5279 +#define INT_44XX_DSP_MMU (28 + IRQ_GIC_START)
5280 +#define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START)
5281 +#define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START)
5282 +#define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START)
5283 +#define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START)
5284 +#define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START)
5285 +#define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START)
5286 +#define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START)
5287 +#define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START)
5288 +#define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START)
5289 +#define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START)
5290 +#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START)
5291 +#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START)
5292 +#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START)
5293 +#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START)
5294 +#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START)
5295 +#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START)
5296 +#define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START)
5297 +#define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START)
5298 +#define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START)
5299 +#define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START)
5300 +#define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START)
5301 +#define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START)
5302 +#define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START)
5303 +#define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START)
5304 +#define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START)
5305 +#define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START)
5306 +#define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START)
5307 +#define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START)
5308 +#define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START)
5309 +#define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START)
5310 +#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START)
5311 +#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START)
5312 +#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START)
5313 +#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START)
5314 +#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START)
5315 +#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START)
5316 +#define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START)
5317 +#define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START)
5318 +
5319 +#define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START)
5320 +#define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START)
5321 +#define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START)
5322 +#define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START)
5323 +#define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START)
5324 +#define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START)
5325 +#define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START)
5326 +
5327 +#define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START)
5328 +#define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START)
5329 +#define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START)
5330 +#define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START)
5331 +#define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START)
5332 +#define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START)
5333 +#define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START)
5334 +#define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START)
5335 +#define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START)
5336 +#define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START)
5337 +#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START)
5338 +#define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START)
5339 +#define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START)
5340 +#define INT_44XX_MMC5_IRQ (59 + IRQ_GIC_START)
5341 +#define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START)
5342 +#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START)
5343 +#define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START)
5344 +#define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START)
5345 +#define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START)
5346 +#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START)
5347 +#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START)
5348 +#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START)
5349 +#define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START)
5350 +
5351 +
5352 +/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
5353 + * 16 MPUIO lines */
5354 +#define OMAP_MAX_GPIO_LINES 192
5355 +#define IH_GPIO_BASE (128 + IH2_BASE)
5356 +#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
5357 +#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
5358 +
5359 +/* External FPGA handles interrupts on Innovator boards */
5360 +#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
5361 +#ifdef CONFIG_MACH_OMAP_INNOVATOR
5362 +#define OMAP_FPGA_NR_IRQS 24
5363 +#else
5364 +#define OMAP_FPGA_NR_IRQS 0
5365 +#endif
5366 +#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
5367 +
5368 +/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
5369 +#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
5370 +#ifdef CONFIG_TWL4030_CORE
5371 +#define TWL4030_BASE_NR_IRQS 8
5372 +#define TWL4030_PWR_NR_IRQS 8
5373 +#else
5374 +#define TWL4030_BASE_NR_IRQS 0
5375 +#define TWL4030_PWR_NR_IRQS 0
5376 +#endif
5377 +#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
5378 +#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
5379 +#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
5380 +
5381 +/* External TWL4030 gpio interrupts are optional */
5382 +#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
5383 +#ifdef CONFIG_GPIO_TWL4030
5384 +#define TWL4030_GPIO_NR_IRQS 18
5385 +#else
5386 +#define TWL4030_GPIO_NR_IRQS 0
5387 +#endif
5388 +#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
5389 +
5390 +#define TWL6030_IRQ_BASE (OMAP_FPGA_IRQ_END)
5391 +#ifdef CONFIG_TWL4030_CORE
5392 +#define TWL6030_BASE_NR_IRQS 20
5393 +#else
5394 +#define TWL6030_BASE_NR_IRQS 0
5395 +#endif
5396 +#define TWL6030_IRQ_END (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
5397 +
5398 +/* Total number of interrupts depends on the enabled blocks above */
5399 +#if (TWL4030_GPIO_IRQ_END > TWL6030_IRQ_END)
5400 +#define TWL_IRQ_END TWL4030_GPIO_IRQ_END
5401 +#else
5402 +#define TWL_IRQ_END TWL6030_IRQ_END
5403 +#endif
5404 +
5405 +#define NR_IRQS TWL_IRQ_END
5406 +
5407 +#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
5408 +
5409 +#define INTCPS_NR_MIR_REGS 3
5410 +#define INTCPS_NR_IRQS 96
5411 +
5412 +#ifndef __ASSEMBLY__
5413 +extern void omap_init_irq(void);
5414 +extern int omap_irq_pending(void);
5415 +void omap_intc_save_context(void);
5416 +void omap_intc_restore_context(void);
5417 +#endif
5418 +
5419 +#include <mach/hardware.h>
5420 +
5421 +#endif
5422 --- /dev/null
5423 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/keypad.h
5424 @@ -0,0 +1,45 @@
5425 +/*
5426 + * arch/arm/plat-omap/include/mach/keypad.h
5427 + *
5428 + * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
5429 + *
5430 + * This program is free software; you can redistribute it and/or modify
5431 + * it under the terms of the GNU General Public License version 2 as
5432 + * published by the Free Software Foundation.
5433 + */
5434 +#ifndef ASMARM_ARCH_KEYPAD_H
5435 +#define ASMARM_ARCH_KEYPAD_H
5436 +
5437 +#warning: Please update the board to use matrix_keypad.h instead
5438 +
5439 +struct omap_kp_platform_data {
5440 + int rows;
5441 + int cols;
5442 + int *keymap;
5443 + unsigned int keymapsize;
5444 + unsigned int rep:1;
5445 + unsigned long delay;
5446 + unsigned int dbounce:1;
5447 + /* specific to OMAP242x*/
5448 + unsigned int *row_gpios;
5449 + unsigned int *col_gpios;
5450 +};
5451 +
5452 +/* Group (0..3) -- when multiple keys are pressed, only the
5453 + * keys pressed in the same group are considered as pressed. This is
5454 + * in order to workaround certain crappy HW designs that produce ghost
5455 + * keypresses. */
5456 +#define GROUP_0 (0 << 16)
5457 +#define GROUP_1 (1 << 16)
5458 +#define GROUP_2 (2 << 16)
5459 +#define GROUP_3 (3 << 16)
5460 +#define GROUP_MASK GROUP_3
5461 +
5462 +#define KEY_PERSISTENT 0x00800000
5463 +#define KEYNUM_MASK 0x00EFFFFF
5464 +#define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val))
5465 +#define PERSISTENT_KEY(col, row) (((col) << 28) | ((row) << 24) | \
5466 + KEY_PERSISTENT)
5467 +
5468 +#endif
5469 +
5470 --- /dev/null
5471 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/lcd_mipid.h
5472 @@ -0,0 +1,29 @@
5473 +#ifndef __LCD_MIPID_H
5474 +#define __LCD_MIPID_H
5475 +
5476 +enum mipid_test_num {
5477 + MIPID_TEST_RGB_LINES,
5478 +};
5479 +
5480 +enum mipid_test_result {
5481 + MIPID_TEST_SUCCESS,
5482 + MIPID_TEST_INVALID,
5483 + MIPID_TEST_FAILED,
5484 +};
5485 +
5486 +#ifdef __KERNEL__
5487 +
5488 +struct mipid_platform_data {
5489 + int nreset_gpio;
5490 + int data_lines;
5491 +
5492 + void (*shutdown)(struct mipid_platform_data *pdata);
5493 + void (*set_bklight_level)(struct mipid_platform_data *pdata,
5494 + int level);
5495 + int (*get_bklight_level)(struct mipid_platform_data *pdata);
5496 + int (*get_bklight_max)(struct mipid_platform_data *pdata);
5497 +};
5498 +
5499 +#endif
5500 +
5501 +#endif
5502 --- /dev/null
5503 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/led.h
5504 @@ -0,0 +1,24 @@
5505 +/*
5506 + * arch/arm/plat-omap/include/mach/led.h
5507 + *
5508 + * Copyright (C) 2006 Samsung Electronics
5509 + * Kyungmin Park <kyungmin.park@samsung.com>
5510 + *
5511 + * This program is free software; you can redistribute it and/or modify
5512 + * it under the terms of the GNU General Public License version 2 as
5513 + * published by the Free Software Foundation.
5514 + */
5515 +#ifndef ASMARM_ARCH_LED_H
5516 +#define ASMARM_ARCH_LED_H
5517 +
5518 +struct omap_led_config {
5519 + struct led_classdev cdev;
5520 + s16 gpio;
5521 +};
5522 +
5523 +struct omap_led_platform_data {
5524 + s16 nr_leds;
5525 + struct omap_led_config *leds;
5526 +};
5527 +
5528 +#endif
5529 --- /dev/null
5530 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/mailbox.h
5531 @@ -0,0 +1,111 @@
5532 +/* mailbox.h */
5533 +
5534 +#ifndef MAILBOX_H
5535 +#define MAILBOX_H
5536 +
5537 +#include <linux/wait.h>
5538 +#include <linux/workqueue.h>
5539 +#include <linux/blkdev.h>
5540 +#include <linux/interrupt.h>
5541 +
5542 +typedef u32 mbox_msg_t;
5543 +struct omap_mbox;
5544 +
5545 +typedef int __bitwise omap_mbox_irq_t;
5546 +#define IRQ_TX ((__force omap_mbox_irq_t) 1)
5547 +#define IRQ_RX ((__force omap_mbox_irq_t) 2)
5548 +
5549 +typedef int __bitwise omap_mbox_type_t;
5550 +#define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1)
5551 +#define OMAP_MBOX_TYPE2 ((__force omap_mbox_type_t) 2)
5552 +
5553 +struct omap_mbox_ops {
5554 + omap_mbox_type_t type;
5555 + int (*startup)(struct omap_mbox *mbox);
5556 + void (*shutdown)(struct omap_mbox *mbox);
5557 + /* fifo */
5558 + mbox_msg_t (*fifo_read)(struct omap_mbox *mbox);
5559 + void (*fifo_write)(struct omap_mbox *mbox, mbox_msg_t msg);
5560 + int (*fifo_empty)(struct omap_mbox *mbox);
5561 + int (*fifo_full)(struct omap_mbox *mbox);
5562 + /* irq */
5563 + void (*enable_irq)(struct omap_mbox *mbox,
5564 + omap_mbox_irq_t irq);
5565 + void (*disable_irq)(struct omap_mbox *mbox,
5566 + omap_mbox_irq_t irq);
5567 + void (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
5568 + int (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
5569 + /* ctx */
5570 + void (*save_ctx)(struct omap_mbox *mbox);
5571 + void (*restore_ctx)(struct omap_mbox *mbox);
5572 +};
5573 +
5574 +struct omap_mbox_queue {
5575 + spinlock_t lock;
5576 + struct request_queue *queue;
5577 + struct work_struct work;
5578 + struct tasklet_struct tasklet;
5579 + int (*callback)(void *);
5580 + struct omap_mbox *mbox;
5581 +};
5582 +
5583 +struct omap_mbox {
5584 + char *name;
5585 + unsigned int irq;
5586 +
5587 + struct omap_mbox_queue *txq, *rxq;
5588 +
5589 + struct omap_mbox_ops *ops;
5590 +
5591 + mbox_msg_t seq_snd, seq_rcv;
5592 +
5593 + struct device *dev;
5594 +
5595 + struct omap_mbox *next;
5596 + void *priv;
5597 +
5598 + void (*err_notify)(void);
5599 +};
5600 +
5601 +int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
5602 +void omap_mbox_init_seq(struct omap_mbox *);
5603 +
5604 +struct omap_mbox *omap_mbox_get(const char *);
5605 +void omap_mbox_put(struct omap_mbox *);
5606 +
5607 +int omap_mbox_register(struct device *parent, struct omap_mbox *);
5608 +int omap_mbox_unregister(struct omap_mbox *);
5609 +
5610 +static inline void omap_mbox_save_ctx(struct omap_mbox *mbox)
5611 +{
5612 + if (!mbox->ops->save_ctx) {
5613 + dev_err(mbox->dev, "%s:\tno save\n", __func__);
5614 + return;
5615 + }
5616 +
5617 + mbox->ops->save_ctx(mbox);
5618 +}
5619 +
5620 +static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox)
5621 +{
5622 + if (!mbox->ops->restore_ctx) {
5623 + dev_err(mbox->dev, "%s:\tno restore\n", __func__);
5624 + return;
5625 + }
5626 +
5627 + mbox->ops->restore_ctx(mbox);
5628 +}
5629 +
5630 +static inline void omap_mbox_enable_irq(struct omap_mbox *mbox,
5631 + omap_mbox_irq_t irq)
5632 +{
5633 + mbox->ops->enable_irq(mbox, irq);
5634 +}
5635 +
5636 +static inline void omap_mbox_disable_irq(struct omap_mbox *mbox,
5637 + omap_mbox_irq_t irq)
5638 +{
5639 + mbox->ops->disable_irq(mbox, irq);
5640 +}
5641 +
5642 +#endif /* MAILBOX_H */
5643 --- /dev/null
5644 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/mcbsp.h
5645 @@ -0,0 +1,462 @@
5646 +/*
5647 + * arch/arm/plat-omap/include/mach/mcbsp.h
5648 + *
5649 + * Defines for Multi-Channel Buffered Serial Port
5650 + *
5651 + * Copyright (C) 2002 RidgeRun, Inc.
5652 + * Author: Steve Johnson
5653 + *
5654 + * This program is free software; you can redistribute it and/or modify
5655 + * it under the terms of the GNU General Public License as published by
5656 + * the Free Software Foundation; either version 2 of the License, or
5657 + * (at your option) any later version.
5658 + *
5659 + * This program is distributed in the hope that it will be useful,
5660 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5661 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5662 + * GNU General Public License for more details.
5663 + *
5664 + * You should have received a copy of the GNU General Public License
5665 + * along with this program; if not, write to the Free Software
5666 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5667 + *
5668 + */
5669 +#ifndef __ASM_ARCH_OMAP_MCBSP_H
5670 +#define __ASM_ARCH_OMAP_MCBSP_H
5671 +
5672 +#include <linux/completion.h>
5673 +#include <linux/spinlock.h>
5674 +
5675 +#include <mach/hardware.h>
5676 +#include <plat/clock.h>
5677 +
5678 +#define OMAP7XX_MCBSP1_BASE 0xfffb1000
5679 +#define OMAP7XX_MCBSP2_BASE 0xfffb1800
5680 +
5681 +#define OMAP1510_MCBSP1_BASE 0xe1011800
5682 +#define OMAP1510_MCBSP2_BASE 0xfffb1000
5683 +#define OMAP1510_MCBSP3_BASE 0xe1017000
5684 +
5685 +#define OMAP1610_MCBSP1_BASE 0xe1011800
5686 +#define OMAP1610_MCBSP2_BASE 0xfffb1000
5687 +#define OMAP1610_MCBSP3_BASE 0xe1017000
5688 +
5689 +#define OMAP24XX_MCBSP1_BASE 0x48074000
5690 +#define OMAP24XX_MCBSP2_BASE 0x48076000
5691 +#define OMAP2430_MCBSP3_BASE 0x4808c000
5692 +#define OMAP2430_MCBSP4_BASE 0x4808e000
5693 +#define OMAP2430_MCBSP5_BASE 0x48096000
5694 +
5695 +#define OMAP34XX_MCBSP1_BASE 0x48074000
5696 +#define OMAP34XX_MCBSP2_BASE 0x49022000
5697 +#define OMAP34XX_MCBSP3_BASE 0x49024000
5698 +#define OMAP34XX_MCBSP4_BASE 0x49026000
5699 +#define OMAP34XX_MCBSP5_BASE 0x48096000
5700 +
5701 +#define OMAP44XX_MCBSP1_BASE 0x49022000
5702 +#define OMAP44XX_MCBSP2_BASE 0x49024000
5703 +#define OMAP44XX_MCBSP3_BASE 0x49026000
5704 +#define OMAP44XX_MCBSP4_BASE 0x48074000
5705 +
5706 +#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
5707 +
5708 +#define OMAP_MCBSP_REG_DRR2 0x00
5709 +#define OMAP_MCBSP_REG_DRR1 0x02
5710 +#define OMAP_MCBSP_REG_DXR2 0x04
5711 +#define OMAP_MCBSP_REG_DXR1 0x06
5712 +#define OMAP_MCBSP_REG_SPCR2 0x08
5713 +#define OMAP_MCBSP_REG_SPCR1 0x0a
5714 +#define OMAP_MCBSP_REG_RCR2 0x0c
5715 +#define OMAP_MCBSP_REG_RCR1 0x0e
5716 +#define OMAP_MCBSP_REG_XCR2 0x10
5717 +#define OMAP_MCBSP_REG_XCR1 0x12
5718 +#define OMAP_MCBSP_REG_SRGR2 0x14
5719 +#define OMAP_MCBSP_REG_SRGR1 0x16
5720 +#define OMAP_MCBSP_REG_MCR2 0x18
5721 +#define OMAP_MCBSP_REG_MCR1 0x1a
5722 +#define OMAP_MCBSP_REG_RCERA 0x1c
5723 +#define OMAP_MCBSP_REG_RCERB 0x1e
5724 +#define OMAP_MCBSP_REG_XCERA 0x20
5725 +#define OMAP_MCBSP_REG_XCERB 0x22
5726 +#define OMAP_MCBSP_REG_PCR0 0x24
5727 +#define OMAP_MCBSP_REG_RCERC 0x26
5728 +#define OMAP_MCBSP_REG_RCERD 0x28
5729 +#define OMAP_MCBSP_REG_XCERC 0x2A
5730 +#define OMAP_MCBSP_REG_XCERD 0x2C
5731 +#define OMAP_MCBSP_REG_RCERE 0x2E
5732 +#define OMAP_MCBSP_REG_RCERF 0x30
5733 +#define OMAP_MCBSP_REG_XCERE 0x32
5734 +#define OMAP_MCBSP_REG_XCERF 0x34
5735 +#define OMAP_MCBSP_REG_RCERG 0x36
5736 +#define OMAP_MCBSP_REG_RCERH 0x38
5737 +#define OMAP_MCBSP_REG_XCERG 0x3A
5738 +#define OMAP_MCBSP_REG_XCERH 0x3C
5739 +
5740 +/* Dummy defines, these are not available on omap1 */
5741 +#define OMAP_MCBSP_REG_XCCR 0x00
5742 +#define OMAP_MCBSP_REG_RCCR 0x00
5743 +
5744 +#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
5745 +#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
5746 +
5747 +#define AUDIO_MCBSP OMAP_MCBSP1
5748 +#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
5749 +#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
5750 +
5751 +#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
5752 + defined(CONFIG_ARCH_OMAP4)
5753 +
5754 +#define OMAP_MCBSP_REG_DRR2 0x00
5755 +#define OMAP_MCBSP_REG_DRR1 0x04
5756 +#define OMAP_MCBSP_REG_DXR2 0x08
5757 +#define OMAP_MCBSP_REG_DXR1 0x0C
5758 +#define OMAP_MCBSP_REG_DRR 0x00
5759 +#define OMAP_MCBSP_REG_DXR 0x08
5760 +#define OMAP_MCBSP_REG_SPCR2 0x10
5761 +#define OMAP_MCBSP_REG_SPCR1 0x14
5762 +#define OMAP_MCBSP_REG_RCR2 0x18
5763 +#define OMAP_MCBSP_REG_RCR1 0x1C
5764 +#define OMAP_MCBSP_REG_XCR2 0x20
5765 +#define OMAP_MCBSP_REG_XCR1 0x24
5766 +#define OMAP_MCBSP_REG_SRGR2 0x28
5767 +#define OMAP_MCBSP_REG_SRGR1 0x2C
5768 +#define OMAP_MCBSP_REG_MCR2 0x30
5769 +#define OMAP_MCBSP_REG_MCR1 0x34
5770 +#define OMAP_MCBSP_REG_RCERA 0x38
5771 +#define OMAP_MCBSP_REG_RCERB 0x3C
5772 +#define OMAP_MCBSP_REG_XCERA 0x40
5773 +#define OMAP_MCBSP_REG_XCERB 0x44
5774 +#define OMAP_MCBSP_REG_PCR0 0x48
5775 +#define OMAP_MCBSP_REG_RCERC 0x4C
5776 +#define OMAP_MCBSP_REG_RCERD 0x50
5777 +#define OMAP_MCBSP_REG_XCERC 0x54
5778 +#define OMAP_MCBSP_REG_XCERD 0x58
5779 +#define OMAP_MCBSP_REG_RCERE 0x5C
5780 +#define OMAP_MCBSP_REG_RCERF 0x60
5781 +#define OMAP_MCBSP_REG_XCERE 0x64
5782 +#define OMAP_MCBSP_REG_XCERF 0x68
5783 +#define OMAP_MCBSP_REG_RCERG 0x6C
5784 +#define OMAP_MCBSP_REG_RCERH 0x70
5785 +#define OMAP_MCBSP_REG_XCERG 0x74
5786 +#define OMAP_MCBSP_REG_XCERH 0x78
5787 +#define OMAP_MCBSP_REG_SYSCON 0x8C
5788 +#define OMAP_MCBSP_REG_THRSH2 0x90
5789 +#define OMAP_MCBSP_REG_THRSH1 0x94
5790 +#define OMAP_MCBSP_REG_IRQST 0xA0
5791 +#define OMAP_MCBSP_REG_IRQEN 0xA4
5792 +#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
5793 +#define OMAP_MCBSP_REG_XCCR 0xAC
5794 +#define OMAP_MCBSP_REG_RCCR 0xB0
5795 +
5796 +#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
5797 +#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
5798 +
5799 +#define AUDIO_MCBSP OMAP_MCBSP2
5800 +#define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX
5801 +#define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX
5802 +
5803 +#endif
5804 +
5805 +/************************** McBSP SPCR1 bit definitions ***********************/
5806 +#define RRST 0x0001
5807 +#define RRDY 0x0002
5808 +#define RFULL 0x0004
5809 +#define RSYNC_ERR 0x0008
5810 +#define RINTM(value) ((value)<<4) /* bits 4:5 */
5811 +#define ABIS 0x0040
5812 +#define DXENA 0x0080
5813 +#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
5814 +#define RJUST(value) ((value)<<13) /* bits 13:14 */
5815 +#define ALB 0x8000
5816 +#define DLB 0x8000
5817 +
5818 +/************************** McBSP SPCR2 bit definitions ***********************/
5819 +#define XRST 0x0001
5820 +#define XRDY 0x0002
5821 +#define XEMPTY 0x0004
5822 +#define XSYNC_ERR 0x0008
5823 +#define XINTM(value) ((value)<<4) /* bits 4:5 */
5824 +#define GRST 0x0040
5825 +#define FRST 0x0080
5826 +#define SOFT 0x0100
5827 +#define FREE 0x0200
5828 +
5829 +/************************** McBSP PCR bit definitions *************************/
5830 +#define CLKRP 0x0001
5831 +#define CLKXP 0x0002
5832 +#define FSRP 0x0004
5833 +#define FSXP 0x0008
5834 +#define DR_STAT 0x0010
5835 +#define DX_STAT 0x0020
5836 +#define CLKS_STAT 0x0040
5837 +#define SCLKME 0x0080
5838 +#define CLKRM 0x0100
5839 +#define CLKXM 0x0200
5840 +#define FSRM 0x0400
5841 +#define FSXM 0x0800
5842 +#define RIOEN 0x1000
5843 +#define XIOEN 0x2000
5844 +#define IDLE_EN 0x4000
5845 +
5846 +/************************** McBSP RCR1 bit definitions ************************/
5847 +#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
5848 +#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
5849 +
5850 +/************************** McBSP XCR1 bit definitions ************************/
5851 +#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
5852 +#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
5853 +
5854 +/*************************** McBSP RCR2 bit definitions ***********************/
5855 +#define RDATDLY(value) (value) /* Bits 0:1 */
5856 +#define RFIG 0x0004
5857 +#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
5858 +#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
5859 +#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
5860 +#define RPHASE 0x8000
5861 +
5862 +/*************************** McBSP XCR2 bit definitions ***********************/
5863 +#define XDATDLY(value) (value) /* Bits 0:1 */
5864 +#define XFIG 0x0004
5865 +#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
5866 +#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
5867 +#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
5868 +#define XPHASE 0x8000
5869 +
5870 +/************************* McBSP SRGR1 bit definitions ************************/
5871 +#define CLKGDV(value) (value) /* Bits 0:7 */
5872 +#define FWID(value) ((value)<<8) /* Bits 8:15 */
5873 +
5874 +/************************* McBSP SRGR2 bit definitions ************************/
5875 +#define FPER(value) (value) /* Bits 0:11 */
5876 +#define FSGM 0x1000
5877 +#define CLKSM 0x2000
5878 +#define CLKSP 0x4000
5879 +#define GSYNC 0x8000
5880 +
5881 +/************************* McBSP MCR1 bit definitions *************************/
5882 +#define RMCM 0x0001
5883 +#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
5884 +#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
5885 +#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
5886 +
5887 +/************************* McBSP MCR2 bit definitions *************************/
5888 +#define XMCM(value) (value) /* Bits 0:1 */
5889 +#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
5890 +#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
5891 +#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
5892 +
5893 +/*********************** McBSP XCCR bit definitions *************************/
5894 +#define EXTCLKGATE 0x8000
5895 +#define PPCONNECT 0x4000
5896 +#define DXENDLY(value) ((value)<<12) /* Bits 12:13 */
5897 +#define XFULL_CYCLE 0x0800
5898 +#define DILB 0x0020
5899 +#define XDMAEN 0x0008
5900 +#define XDISABLE 0x0001
5901 +
5902 +/********************** McBSP RCCR bit definitions *************************/
5903 +#define RFULL_CYCLE 0x0800
5904 +#define RDMAEN 0x0008
5905 +#define RDISABLE 0x0001
5906 +
5907 +/********************** McBSP SYSCONFIG bit definitions ********************/
5908 +#define CLOCKACTIVITY(value) ((value)<<8)
5909 +#define SIDLEMODE(value) ((value)<<3)
5910 +#define ENAWAKEUP 0x0004
5911 +#define SOFTRST 0x0002
5912 +
5913 +/********************** McBSP DMA operating modes **************************/
5914 +#define MCBSP_DMA_MODE_ELEMENT 0
5915 +#define MCBSP_DMA_MODE_THRESHOLD 1
5916 +#define MCBSP_DMA_MODE_FRAME 2
5917 +
5918 +/********************** McBSP WAKEUPEN bit definitions *********************/
5919 +#define XEMPTYEOFEN 0x4000
5920 +#define XRDYEN 0x0400
5921 +#define XEOFEN 0x0200
5922 +#define XFSXEN 0x0100
5923 +#define XSYNCERREN 0x0080
5924 +#define RRDYEN 0x0008
5925 +#define REOFEN 0x0004
5926 +#define RFSREN 0x0002
5927 +#define RSYNCERREN 0x0001
5928 +
5929 +/* we don't do multichannel for now */
5930 +struct omap_mcbsp_reg_cfg {
5931 + u16 spcr2;
5932 + u16 spcr1;
5933 + u16 rcr2;
5934 + u16 rcr1;
5935 + u16 xcr2;
5936 + u16 xcr1;
5937 + u16 srgr2;
5938 + u16 srgr1;
5939 + u16 mcr2;
5940 + u16 mcr1;
5941 + u16 pcr0;
5942 + u16 rcerc;
5943 + u16 rcerd;
5944 + u16 xcerc;
5945 + u16 xcerd;
5946 + u16 rcere;
5947 + u16 rcerf;
5948 + u16 xcere;
5949 + u16 xcerf;
5950 + u16 rcerg;
5951 + u16 rcerh;
5952 + u16 xcerg;
5953 + u16 xcerh;
5954 + u16 xccr;
5955 + u16 rccr;
5956 +};
5957 +
5958 +typedef enum {
5959 + OMAP_MCBSP1 = 0,
5960 + OMAP_MCBSP2,
5961 + OMAP_MCBSP3,
5962 + OMAP_MCBSP4,
5963 + OMAP_MCBSP5
5964 +} omap_mcbsp_id;
5965 +
5966 +typedef int __bitwise omap_mcbsp_io_type_t;
5967 +#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
5968 +#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
5969 +
5970 +typedef enum {
5971 + OMAP_MCBSP_WORD_8 = 0,
5972 + OMAP_MCBSP_WORD_12,
5973 + OMAP_MCBSP_WORD_16,
5974 + OMAP_MCBSP_WORD_20,
5975 + OMAP_MCBSP_WORD_24,
5976 + OMAP_MCBSP_WORD_32,
5977 +} omap_mcbsp_word_length;
5978 +
5979 +typedef enum {
5980 + OMAP_MCBSP_CLK_RISING = 0,
5981 + OMAP_MCBSP_CLK_FALLING,
5982 +} omap_mcbsp_clk_polarity;
5983 +
5984 +typedef enum {
5985 + OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
5986 + OMAP_MCBSP_FS_ACTIVE_LOW,
5987 +} omap_mcbsp_fs_polarity;
5988 +
5989 +typedef enum {
5990 + OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
5991 + OMAP_MCBSP_CLK_STP_MODE_DELAY,
5992 +} omap_mcbsp_clk_stp_mode;
5993 +
5994 +
5995 +/******* SPI specific mode **********/
5996 +typedef enum {
5997 + OMAP_MCBSP_SPI_MASTER = 0,
5998 + OMAP_MCBSP_SPI_SLAVE,
5999 +} omap_mcbsp_spi_mode;
6000 +
6001 +struct omap_mcbsp_spi_cfg {
6002 + omap_mcbsp_spi_mode spi_mode;
6003 + omap_mcbsp_clk_polarity rx_clock_polarity;
6004 + omap_mcbsp_clk_polarity tx_clock_polarity;
6005 + omap_mcbsp_fs_polarity fsx_polarity;
6006 + u8 clk_div;
6007 + omap_mcbsp_clk_stp_mode clk_stp_mode;
6008 + omap_mcbsp_word_length word_length;
6009 +};
6010 +
6011 +/* Platform specific configuration */
6012 +struct omap_mcbsp_ops {
6013 + void (*request)(unsigned int);
6014 + void (*free)(unsigned int);
6015 +};
6016 +
6017 +struct omap_mcbsp_platform_data {
6018 + unsigned long phys_base;
6019 + u8 dma_rx_sync, dma_tx_sync;
6020 + u16 rx_irq, tx_irq;
6021 + struct omap_mcbsp_ops *ops;
6022 +#ifdef CONFIG_ARCH_OMAP34XX
6023 + u16 buffer_size;
6024 +#endif
6025 +};
6026 +
6027 +struct omap_mcbsp {
6028 + struct device *dev;
6029 + unsigned long phys_base;
6030 + void __iomem *io_base;
6031 + u8 id;
6032 + u8 free;
6033 + omap_mcbsp_word_length rx_word_length;
6034 + omap_mcbsp_word_length tx_word_length;
6035 +
6036 + omap_mcbsp_io_type_t io_type; /* IRQ or poll */
6037 + /* IRQ based TX/RX */
6038 + int rx_irq;
6039 + int tx_irq;
6040 +
6041 + /* DMA stuff */
6042 + u8 dma_rx_sync;
6043 + short dma_rx_lch;
6044 + u8 dma_tx_sync;
6045 + short dma_tx_lch;
6046 +
6047 + /* Completion queues */
6048 + struct completion tx_irq_completion;
6049 + struct completion rx_irq_completion;
6050 + struct completion tx_dma_completion;
6051 + struct completion rx_dma_completion;
6052 +
6053 + /* Protect the field .free, while checking if the mcbsp is in use */
6054 + spinlock_t lock;
6055 + struct omap_mcbsp_platform_data *pdata;
6056 + struct clk *iclk;
6057 + struct clk *fclk;
6058 +#ifdef CONFIG_ARCH_OMAP34XX
6059 + int dma_op_mode;
6060 + u16 max_tx_thres;
6061 + u16 max_rx_thres;
6062 +#endif
6063 +};
6064 +extern struct omap_mcbsp **mcbsp_ptr;
6065 +extern int omap_mcbsp_count;
6066 +
6067 +int omap_mcbsp_init(void);
6068 +void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
6069 + int size);
6070 +void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
6071 +#ifdef CONFIG_ARCH_OMAP34XX
6072 +void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
6073 +void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
6074 +u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
6075 +u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
6076 +int omap_mcbsp_get_dma_op_mode(unsigned int id);
6077 +#else
6078 +static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
6079 +{ }
6080 +static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
6081 +{ }
6082 +static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
6083 +static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
6084 +static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
6085 +#endif
6086 +int omap_mcbsp_request(unsigned int id);
6087 +void omap_mcbsp_free(unsigned int id);
6088 +void omap_mcbsp_start(unsigned int id, int tx, int rx);
6089 +void omap_mcbsp_stop(unsigned int id, int tx, int rx);
6090 +void omap_mcbsp_xmit_word(unsigned int id, u32 word);
6091 +u32 omap_mcbsp_recv_word(unsigned int id);
6092 +
6093 +int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
6094 +int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
6095 +int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
6096 +int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
6097 +
6098 +
6099 +/* SPI specific API */
6100 +void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
6101 +
6102 +/* Polled read/write functions */
6103 +int omap_mcbsp_pollread(unsigned int id, u16 * buf);
6104 +int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
6105 +int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
6106 +
6107 +#endif
6108 --- /dev/null
6109 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/mcspi.h
6110 @@ -0,0 +1,15 @@
6111 +#ifndef _OMAP2_MCSPI_H
6112 +#define _OMAP2_MCSPI_H
6113 +
6114 +struct omap2_mcspi_platform_config {
6115 + unsigned short num_cs;
6116 +};
6117 +
6118 +struct omap2_mcspi_device_config {
6119 + unsigned turbo_mode:1;
6120 +
6121 + /* Do we want one channel enabled at the same time? */
6122 + unsigned single_channel:1;
6123 +};
6124 +
6125 +#endif
6126 --- /dev/null
6127 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/memory.h
6128 @@ -0,0 +1,103 @@
6129 +/*
6130 + * arch/arm/plat-omap/include/mach/memory.h
6131 + *
6132 + * Memory map for OMAP-1510 and 1610
6133 + *
6134 + * Copyright (C) 2000 RidgeRun, Inc.
6135 + * Author: Greg Lonnon <glonnon@ridgerun.com>
6136 + *
6137 + * This file was derived from arch/arm/mach-intergrator/include/mach/memory.h
6138 + * Copyright (C) 1999 ARM Limited
6139 + *
6140 + * This program is free software; you can redistribute it and/or modify it
6141 + * under the terms of the GNU General Public License as published by the
6142 + * Free Software Foundation; either version 2 of the License, or (at your
6143 + * option) any later version.
6144 + *
6145 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6146 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6147 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6148 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6149 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6150 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6151 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6152 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6153 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6154 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6155 + *
6156 + * You should have received a copy of the GNU General Public License along
6157 + * with this program; if not, write to the Free Software Foundation, Inc.,
6158 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6159 + */
6160 +
6161 +#ifndef __ASM_ARCH_MEMORY_H
6162 +#define __ASM_ARCH_MEMORY_H
6163 +
6164 +/*
6165 + * Physical DRAM offset.
6166 + */
6167 +#if defined(CONFIG_ARCH_OMAP1)
6168 +#define PHYS_OFFSET UL(0x10000000)
6169 +#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
6170 + defined(CONFIG_ARCH_OMAP4)
6171 +#define PHYS_OFFSET UL(0x80000000)
6172 +#endif
6173 +
6174 +/*
6175 + * Bus address is physical address, except for OMAP-1510 Local Bus.
6176 + * OMAP-1510 bus address is translated into a Local Bus address if the
6177 + * OMAP bus type is lbus. We do the address translation based on the
6178 + * device overriding the defaults used in the dma-mapping API.
6179 + * Note that the is_lbus_device() test is not very efficient on 1510
6180 + * because of the strncmp().
6181 + */
6182 +#ifdef CONFIG_ARCH_OMAP15XX
6183 +
6184 +/*
6185 + * OMAP-1510 Local Bus address offset
6186 + */
6187 +#define OMAP1510_LB_OFFSET UL(0x30000000)
6188 +
6189 +#define virt_to_lbus(x) ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
6190 +#define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
6191 +#define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0))
6192 +
6193 +#define __arch_page_to_dma(dev, page) \
6194 + ({ dma_addr_t __dma = page_to_phys(page); \
6195 + if (is_lbus_device(dev)) \
6196 + __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \
6197 + __dma; })
6198 +
6199 +#define __arch_dma_to_page(dev, addr) \
6200 + ({ dma_addr_t __dma = addr; \
6201 + if (is_lbus_device(dev)) \
6202 + __dma += PHYS_OFFSET - OMAP1510_LB_OFFSET; \
6203 + phys_to_page(__dma); \
6204 + })
6205 +
6206 +#define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \
6207 + lbus_to_virt(addr) : \
6208 + __phys_to_virt(addr)); })
6209 +
6210 +#define __arch_virt_to_dma(dev, addr) ({ unsigned long __addr = (unsigned long)(addr); \
6211 + (dma_addr_t) (is_lbus_device(dev) ? \
6212 + virt_to_lbus(__addr) : \
6213 + __virt_to_phys(__addr)); })
6214 +
6215 +#endif /* CONFIG_ARCH_OMAP15XX */
6216 +
6217 +/* Override the ARM default */
6218 +#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
6219 +
6220 +#if (CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE == 0)
6221 +#undef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
6222 +#define CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE 2
6223 +#endif
6224 +
6225 +#define CONSISTENT_DMA_SIZE \
6226 + (((CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE + 1) & ~1) * 1024 * 1024)
6227 +
6228 +#endif
6229 +
6230 +#endif
6231 +
6232 --- /dev/null
6233 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/menelaus.h
6234 @@ -0,0 +1,49 @@
6235 +/*
6236 + * arch/arm/plat-omap/include/mach/menelaus.h
6237 + *
6238 + * Functions to access Menelaus power management chip
6239 + */
6240 +
6241 +#ifndef __ASM_ARCH_MENELAUS_H
6242 +#define __ASM_ARCH_MENELAUS_H
6243 +
6244 +struct device;
6245 +
6246 +struct menelaus_platform_data {
6247 + int (* late_init)(struct device *dev);
6248 +};
6249 +
6250 +extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
6251 + void *data);
6252 +extern void menelaus_unregister_mmc_callback(void);
6253 +extern int menelaus_set_mmc_opendrain(int slot, int enable);
6254 +extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on);
6255 +
6256 +extern int menelaus_set_vmem(unsigned int mV);
6257 +extern int menelaus_set_vio(unsigned int mV);
6258 +extern int menelaus_set_vmmc(unsigned int mV);
6259 +extern int menelaus_set_vaux(unsigned int mV);
6260 +extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
6261 +extern int menelaus_set_slot_sel(int enable);
6262 +extern int menelaus_get_slot_pin_states(void);
6263 +extern int menelaus_set_vcore_sw(unsigned int mV);
6264 +extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
6265 +
6266 +#define EN_VPLL_SLEEP (1 << 7)
6267 +#define EN_VMMC_SLEEP (1 << 6)
6268 +#define EN_VAUX_SLEEP (1 << 5)
6269 +#define EN_VIO_SLEEP (1 << 4)
6270 +#define EN_VMEM_SLEEP (1 << 3)
6271 +#define EN_DC3_SLEEP (1 << 2)
6272 +#define EN_DC2_SLEEP (1 << 1)
6273 +#define EN_VC_SLEEP (1 << 0)
6274 +
6275 +extern int menelaus_set_regulator_sleep(int enable, u32 val);
6276 +
6277 +#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS)
6278 +#define omap_has_menelaus() 1
6279 +#else
6280 +#define omap_has_menelaus() 0
6281 +#endif
6282 +
6283 +#endif
6284 --- /dev/null
6285 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/mmc.h
6286 @@ -0,0 +1,157 @@
6287 +/*
6288 + * MMC definitions for OMAP2
6289 + *
6290 + * Copyright (C) 2006 Nokia Corporation
6291 + *
6292 + * This program is free software; you can redistribute it and/or modify
6293 + * it under the terms of the GNU General Public License version 2 as
6294 + * published by the Free Software Foundation.
6295 + */
6296 +
6297 +#ifndef __OMAP2_MMC_H
6298 +#define __OMAP2_MMC_H
6299 +
6300 +#include <linux/types.h>
6301 +#include <linux/device.h>
6302 +#include <linux/mmc/host.h>
6303 +
6304 +#include <plat/board.h>
6305 +
6306 +#define OMAP15XX_NR_MMC 1
6307 +#define OMAP16XX_NR_MMC 2
6308 +#define OMAP1_MMC_SIZE 0x080
6309 +#define OMAP1_MMC1_BASE 0xfffb7800
6310 +#define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */
6311 +
6312 +#define OMAP24XX_NR_MMC 2
6313 +#define OMAP34XX_NR_MMC 3
6314 +#define OMAP44XX_NR_MMC 5
6315 +#define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE
6316 +#define OMAP3_HSMMC_SIZE 0x200
6317 +#define OMAP4_HSMMC_SIZE 0x1000
6318 +#define OMAP2_MMC1_BASE 0x4809c000
6319 +#define OMAP2_MMC2_BASE 0x480b4000
6320 +#define OMAP3_MMC3_BASE 0x480ad000
6321 +#define OMAP4_MMC4_BASE 0x480d1000
6322 +#define OMAP4_MMC5_BASE 0x480d5000
6323 +#define OMAP4_MMC_REG_OFFSET 0x100
6324 +#define HSMMC5 (1 << 4)
6325 +#define HSMMC4 (1 << 3)
6326 +#define HSMMC3 (1 << 2)
6327 +#define HSMMC2 (1 << 1)
6328 +#define HSMMC1 (1 << 0)
6329 +
6330 +#define OMAP_MMC_MAX_SLOTS 2
6331 +
6332 +struct omap_mmc_platform_data {
6333 + /* back-link to device */
6334 + struct device *dev;
6335 +
6336 + /* number of slots per controller */
6337 + unsigned nr_slots:2;
6338 +
6339 + /* set if your board has components or wiring that limits the
6340 + * maximum frequency on the MMC bus */
6341 + unsigned int max_freq;
6342 +
6343 + /* switch the bus to a new slot */
6344 + int (* switch_slot)(struct device *dev, int slot);
6345 + /* initialize board-specific MMC functionality, can be NULL if
6346 + * not supported */
6347 + int (* init)(struct device *dev);
6348 + void (* cleanup)(struct device *dev);
6349 + void (* shutdown)(struct device *dev);
6350 +
6351 + /* To handle board related suspend/resume functionality for MMC */
6352 + int (*suspend)(struct device *dev, int slot);
6353 + int (*resume)(struct device *dev, int slot);
6354 +
6355 + /* Return context loss count due to PM states changing */
6356 + int (*get_context_loss_count)(struct device *dev);
6357 +
6358 + u64 dma_mask;
6359 +
6360 + struct omap_mmc_slot_data {
6361 +
6362 + /* 4 wire signaling is optional, and is used for SD/SDIO/HSMMC;
6363 + * 8 wire signaling is also optional, and is used with HSMMC
6364 + */
6365 + u8 wires;
6366 +
6367 + /*
6368 + * nomux means "standard" muxing is wrong on this board, and
6369 + * that board-specific code handled it before common init logic.
6370 + */
6371 + unsigned nomux:1;
6372 +
6373 + /* switch pin can be for card detect (default) or card cover */
6374 + unsigned cover:1;
6375 +
6376 + /* use the internal clock */
6377 + unsigned internal_clock:1;
6378 +
6379 + /* nonremovable e.g. eMMC */
6380 + unsigned nonremovable:1;
6381 +
6382 + /* Try to sleep or power off when possible */
6383 + unsigned power_saving:1;
6384 +
6385 + int switch_pin; /* gpio (card detect) */
6386 + int gpio_wp; /* gpio (write protect) */
6387 +
6388 + int (* set_bus_mode)(struct device *dev, int slot, int bus_mode);
6389 + int (* set_power)(struct device *dev, int slot, int power_on, int vdd);
6390 + int (* get_ro)(struct device *dev, int slot);
6391 + int (*set_sleep)(struct device *dev, int slot, int sleep,
6392 + int vdd, int cardsleep);
6393 +
6394 + /* return MMC cover switch state, can be NULL if not supported.
6395 + *
6396 + * possible return values:
6397 + * 0 - closed
6398 + * 1 - open
6399 + */
6400 + int (* get_cover_state)(struct device *dev, int slot);
6401 +
6402 + const char *name;
6403 + u32 ocr_mask;
6404 +
6405 + /* Card detection IRQs */
6406 + int card_detect_irq;
6407 + int (* card_detect)(int irq);
6408 +
6409 + unsigned int ban_openended:1;
6410 +
6411 + } slots[OMAP_MMC_MAX_SLOTS];
6412 +};
6413 +
6414 +/* called from board-specific card detection service routine */
6415 +extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed);
6416 +
6417 +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
6418 + defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
6419 +void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
6420 + int nr_controllers);
6421 +void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
6422 + int nr_controllers);
6423 +int omap_mmc_add(const char *name, int id, unsigned long base,
6424 + unsigned long size, unsigned int irq,
6425 + struct omap_mmc_platform_data *data);
6426 +#else
6427 +static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
6428 + int nr_controllers)
6429 +{
6430 +}
6431 +static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
6432 + int nr_controllers)
6433 +{
6434 +}
6435 +static inline int omap_mmc_add(const char *name, int id, unsigned long base,
6436 + unsigned long size, unsigned int irq,
6437 + struct omap_mmc_platform_data *data)
6438 +{
6439 + return 0;
6440 +}
6441 +
6442 +#endif
6443 +#endif
6444 --- /dev/null
6445 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/mux.h
6446 @@ -0,0 +1,662 @@
6447 +/*
6448 + * arch/arm/plat-omap/include/mach/mux.h
6449 + *
6450 + * Table of the Omap register configurations for the FUNC_MUX and
6451 + * PULL_DWN combinations.
6452 + *
6453 + * Copyright (C) 2004 - 2008 Texas Instruments Inc.
6454 + * Copyright (C) 2003 - 2008 Nokia Corporation
6455 + *
6456 + * Written by Tony Lindgren
6457 + *
6458 + * This program is free software; you can redistribute it and/or modify
6459 + * it under the terms of the GNU General Public License as published by
6460 + * the Free Software Foundation; either version 2 of the License, or
6461 + * (at your option) any later version.
6462 + *
6463 + * This program is distributed in the hope that it will be useful,
6464 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6465 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6466 + * GNU General Public License for more details.
6467 + *
6468 + * You should have received a copy of the GNU General Public License
6469 + * along with this program; if not, write to the Free Software
6470 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6471 + *
6472 + * NOTE: Please use the following naming style for new pin entries.
6473 + * For example, W8_1610_MMC2_DAT0, where:
6474 + * - W8 = ball
6475 + * - 1610 = 1510 or 1610, none if common for both 1510 and 1610
6476 + * - MMC2_DAT0 = function
6477 + */
6478 +
6479 +#ifndef __ASM_ARCH_MUX_H
6480 +#define __ASM_ARCH_MUX_H
6481 +
6482 +#define PU_PD_SEL_NA 0 /* No pu_pd reg available */
6483 +#define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
6484 +
6485 +#ifdef CONFIG_OMAP_MUX_DEBUG
6486 +#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
6487 + .mux_reg = FUNC_MUX_CTRL_##reg, \
6488 + .mask_offset = mode_offset, \
6489 + .mask = mode,
6490 +
6491 +#define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
6492 + .pull_reg = PULL_DWN_CTRL_##reg, \
6493 + .pull_bit = bit, \
6494 + .pull_val = status,
6495 +
6496 +#define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
6497 + .pu_pd_reg = PU_PD_SEL_##reg, \
6498 + .pu_pd_val = status,
6499 +
6500 +#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
6501 + .mux_reg = OMAP7XX_IO_CONF_##reg, \
6502 + .mask_offset = mode_offset, \
6503 + .mask = mode,
6504 +
6505 +#define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \
6506 + .pull_reg = OMAP7XX_IO_CONF_##reg, \
6507 + .pull_bit = bit, \
6508 + .pull_val = status,
6509 +
6510 +#else
6511 +
6512 +#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
6513 + .mask_offset = mode_offset, \
6514 + .mask = mode,
6515 +
6516 +#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
6517 + .pull_bit = bit, \
6518 + .pull_val = status,
6519 +
6520 +#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
6521 + .pu_pd_val = status,
6522 +
6523 +#define MUX_REG_7XX(reg, mode_offset, mode) \
6524 + .mux_reg = OMAP7XX_IO_CONF_##reg, \
6525 + .mask_offset = mode_offset, \
6526 + .mask = mode,
6527 +
6528 +#define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \
6529 + .pull_bit = bit, \
6530 + .pull_val = status,
6531 +
6532 +#endif /* CONFIG_OMAP_MUX_DEBUG */
6533 +
6534 +#define MUX_CFG(desc, mux_reg, mode_offset, mode, \
6535 + pull_reg, pull_bit, pull_status, \
6536 + pu_pd_reg, pu_pd_status, debug_status) \
6537 +{ \
6538 + .name = desc, \
6539 + .debug = debug_status, \
6540 + MUX_REG(mux_reg, mode_offset, mode) \
6541 + PULL_REG(pull_reg, pull_bit, pull_status) \
6542 + PU_PD_REG(pu_pd_reg, pu_pd_status) \
6543 +},
6544 +
6545 +
6546 +/*
6547 + * OMAP730/850 has a slightly different config for the pin mux.
6548 + * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
6549 + * not the FUNC_MUX_CTRL_x regs from hardware.h
6550 + * - for pull-up/down, only has one enable bit which is is in the same register
6551 + * as mux config
6552 + */
6553 +#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \
6554 + pull_bit, pull_status, debug_status)\
6555 +{ \
6556 + .name = desc, \
6557 + .debug = debug_status, \
6558 + MUX_REG_7XX(mux_reg, mode_offset, mode) \
6559 + PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
6560 + PU_PD_REG(NA, 0) \
6561 +},
6562 +
6563 +#define MUX_CFG_24XX(desc, reg_offset, mode, \
6564 + pull_en, pull_mode, dbg) \
6565 +{ \
6566 + .name = desc, \
6567 + .debug = dbg, \
6568 + .mux_reg = reg_offset, \
6569 + .mask = mode, \
6570 + .pull_val = pull_en, \
6571 + .pu_pd_val = pull_mode, \
6572 +},
6573 +
6574 +/* 24xx/34xx mux bit defines */
6575 +#define OMAP2_PULL_ENA (1 << 3)
6576 +#define OMAP2_PULL_UP (1 << 4)
6577 +#define OMAP2_ALTELECTRICALSEL (1 << 5)
6578 +
6579 +struct pin_config {
6580 + char *name;
6581 + const unsigned int mux_reg;
6582 + unsigned char debug;
6583 +
6584 +#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
6585 + const unsigned char mask_offset;
6586 + const unsigned char mask;
6587 +
6588 + const char *pull_name;
6589 + const unsigned int pull_reg;
6590 + const unsigned char pull_val;
6591 + const unsigned char pull_bit;
6592 +
6593 + const char *pu_pd_name;
6594 + const unsigned int pu_pd_reg;
6595 + const unsigned char pu_pd_val;
6596 +#endif
6597 +
6598 +#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
6599 + const char *mux_reg_name;
6600 +#endif
6601 +
6602 +};
6603 +
6604 +enum omap7xx_index {
6605 + /* OMAP 730 keyboard */
6606 + E2_7XX_KBR0,
6607 + J7_7XX_KBR1,
6608 + E1_7XX_KBR2,
6609 + F3_7XX_KBR3,
6610 + D2_7XX_KBR4,
6611 + C2_7XX_KBC0,
6612 + D3_7XX_KBC1,
6613 + E4_7XX_KBC2,
6614 + F4_7XX_KBC3,
6615 + E3_7XX_KBC4,
6616 +
6617 + /* USB */
6618 + AA17_7XX_USB_DM,
6619 + W16_7XX_USB_PU_EN,
6620 + W17_7XX_USB_VBUSI,
6621 + W18_7XX_USB_DMCK_OUT,
6622 + W19_7XX_USB_DCRST,
6623 +
6624 + /* MMC */
6625 + MMC_7XX_CMD,
6626 + MMC_7XX_CLK,
6627 + MMC_7XX_DAT0,
6628 +
6629 + /* I2C */
6630 + I2C_7XX_SCL,
6631 + I2C_7XX_SDA,
6632 +};
6633 +
6634 +enum omap1xxx_index {
6635 + /* UART1 (BT_UART_GATING)*/
6636 + UART1_TX = 0,
6637 + UART1_RTS,
6638 +
6639 + /* UART2 (COM_UART_GATING)*/
6640 + UART2_TX,
6641 + UART2_RX,
6642 + UART2_CTS,
6643 + UART2_RTS,
6644 +
6645 + /* UART3 (GIGA_UART_GATING) */
6646 + UART3_TX,
6647 + UART3_RX,
6648 + UART3_CTS,
6649 + UART3_RTS,
6650 + UART3_CLKREQ,
6651 + UART3_BCLK, /* 12MHz clock out */
6652 + Y15_1610_UART3_RTS,
6653 +
6654 + /* PWT & PWL */
6655 + PWT,
6656 + PWL,
6657 +
6658 + /* USB master generic */
6659 + R18_USB_VBUS,
6660 + R18_1510_USB_GPIO0,
6661 + W4_USB_PUEN,
6662 + W4_USB_CLKO,
6663 + W4_USB_HIGHZ,
6664 + W4_GPIO58,
6665 +
6666 + /* USB1 master */
6667 + USB1_SUSP,
6668 + USB1_SEO,
6669 + W13_1610_USB1_SE0,
6670 + USB1_TXEN,
6671 + USB1_TXD,
6672 + USB1_VP,
6673 + USB1_VM,
6674 + USB1_RCV,
6675 + USB1_SPEED,
6676 + R13_1610_USB1_SPEED,
6677 + R13_1710_USB1_SE0,
6678 +
6679 + /* USB2 master */
6680 + USB2_SUSP,
6681 + USB2_VP,
6682 + USB2_TXEN,
6683 + USB2_VM,
6684 + USB2_RCV,
6685 + USB2_SEO,
6686 + USB2_TXD,
6687 +
6688 + /* OMAP-1510 GPIO */
6689 + R18_1510_GPIO0,
6690 + R19_1510_GPIO1,
6691 + M14_1510_GPIO2,
6692 +
6693 + /* OMAP1610 GPIO */
6694 + P18_1610_GPIO3,
6695 + Y15_1610_GPIO17,
6696 +
6697 + /* OMAP-1710 GPIO */
6698 + R18_1710_GPIO0,
6699 + V2_1710_GPIO10,
6700 + N21_1710_GPIO14,
6701 + W15_1710_GPIO40,
6702 +
6703 + /* MPUIO */
6704 + MPUIO2,
6705 + N15_1610_MPUIO2,
6706 + MPUIO4,
6707 + MPUIO5,
6708 + T20_1610_MPUIO5,
6709 + W11_1610_MPUIO6,
6710 + V10_1610_MPUIO7,
6711 + W11_1610_MPUIO9,
6712 + V10_1610_MPUIO10,
6713 + W10_1610_MPUIO11,
6714 + E20_1610_MPUIO13,
6715 + U20_1610_MPUIO14,
6716 + E19_1610_MPUIO15,
6717 +
6718 + /* MCBSP2 */
6719 + MCBSP2_CLKR,
6720 + MCBSP2_CLKX,
6721 + MCBSP2_DR,
6722 + MCBSP2_DX,
6723 + MCBSP2_FSR,
6724 + MCBSP2_FSX,
6725 +
6726 + /* MCBSP3 */
6727 + MCBSP3_CLKX,
6728 +
6729 + /* Misc ballouts */
6730 + BALLOUT_V8_ARMIO3,
6731 + N20_HDQ,
6732 +
6733 + /* OMAP-1610 MMC2 */
6734 + W8_1610_MMC2_DAT0,
6735 + V8_1610_MMC2_DAT1,
6736 + W15_1610_MMC2_DAT2,
6737 + R10_1610_MMC2_DAT3,
6738 + Y10_1610_MMC2_CLK,
6739 + Y8_1610_MMC2_CMD,
6740 + V9_1610_MMC2_CMDDIR,
6741 + V5_1610_MMC2_DATDIR0,
6742 + W19_1610_MMC2_DATDIR1,
6743 + R18_1610_MMC2_CLKIN,
6744 +
6745 + /* OMAP-1610 External Trace Interface */
6746 + M19_1610_ETM_PSTAT0,
6747 + L15_1610_ETM_PSTAT1,
6748 + L18_1610_ETM_PSTAT2,
6749 + L19_1610_ETM_D0,
6750 + J19_1610_ETM_D6,
6751 + J18_1610_ETM_D7,
6752 +
6753 + /* OMAP16XX GPIO */
6754 + P20_1610_GPIO4,
6755 + V9_1610_GPIO7,
6756 + W8_1610_GPIO9,
6757 + N20_1610_GPIO11,
6758 + N19_1610_GPIO13,
6759 + P10_1610_GPIO22,
6760 + V5_1610_GPIO24,
6761 + AA20_1610_GPIO_41,
6762 + W19_1610_GPIO48,
6763 + M7_1610_GPIO62,
6764 + V14_16XX_GPIO37,
6765 + R9_16XX_GPIO18,
6766 + L14_16XX_GPIO49,
6767 +
6768 + /* OMAP-1610 uWire */
6769 + V19_1610_UWIRE_SCLK,
6770 + U18_1610_UWIRE_SDI,
6771 + W21_1610_UWIRE_SDO,
6772 + N14_1610_UWIRE_CS0,
6773 + P15_1610_UWIRE_CS3,
6774 + N15_1610_UWIRE_CS1,
6775 +
6776 + /* OMAP-1610 SPI */
6777 + U19_1610_SPIF_SCK,
6778 + U18_1610_SPIF_DIN,
6779 + P20_1610_SPIF_DIN,
6780 + W21_1610_SPIF_DOUT,
6781 + R18_1610_SPIF_DOUT,
6782 + N14_1610_SPIF_CS0,
6783 + N15_1610_SPIF_CS1,
6784 + T19_1610_SPIF_CS2,
6785 + P15_1610_SPIF_CS3,
6786 +
6787 + /* OMAP-1610 Flash */
6788 + L3_1610_FLASH_CS2B_OE,
6789 + M8_1610_FLASH_CS2B_WE,
6790 +
6791 + /* First MMC */
6792 + MMC_CMD,
6793 + MMC_DAT1,
6794 + MMC_DAT2,
6795 + MMC_DAT0,
6796 + MMC_CLK,
6797 + MMC_DAT3,
6798 +
6799 + /* OMAP-1710 MMC CMDDIR and DATDIR0 */
6800 + M15_1710_MMC_CLKI,
6801 + P19_1710_MMC_CMDDIR,
6802 + P20_1710_MMC_DATDIR0,
6803 +
6804 + /* OMAP-1610 USB0 alternate pin configuration */
6805 + W9_USB0_TXEN,
6806 + AA9_USB0_VP,
6807 + Y5_USB0_RCV,
6808 + R9_USB0_VM,
6809 + V6_USB0_TXD,
6810 + W5_USB0_SE0,
6811 + V9_USB0_SPEED,
6812 + V9_USB0_SUSP,
6813 +
6814 + /* USB2 */
6815 + W9_USB2_TXEN,
6816 + AA9_USB2_VP,
6817 + Y5_USB2_RCV,
6818 + R9_USB2_VM,
6819 + V6_USB2_TXD,
6820 + W5_USB2_SE0,
6821 +
6822 + /* 16XX UART */
6823 + R13_1610_UART1_TX,
6824 + V14_16XX_UART1_RX,
6825 + R14_1610_UART1_CTS,
6826 + AA15_1610_UART1_RTS,
6827 + R9_16XX_UART2_RX,
6828 + L14_16XX_UART3_RX,
6829 +
6830 + /* I2C OMAP-1610 */
6831 + I2C_SCL,
6832 + I2C_SDA,
6833 +
6834 + /* Keypad */
6835 + F18_1610_KBC0,
6836 + D20_1610_KBC1,
6837 + D19_1610_KBC2,
6838 + E18_1610_KBC3,
6839 + C21_1610_KBC4,
6840 + G18_1610_KBR0,
6841 + F19_1610_KBR1,
6842 + H14_1610_KBR2,
6843 + E20_1610_KBR3,
6844 + E19_1610_KBR4,
6845 + N19_1610_KBR5,
6846 +
6847 + /* Power management */
6848 + T20_1610_LOW_PWR,
6849 +
6850 + /* MCLK Settings */
6851 + V5_1710_MCLK_ON,
6852 + V5_1710_MCLK_OFF,
6853 + R10_1610_MCLK_ON,
6854 + R10_1610_MCLK_OFF,
6855 +
6856 + /* CompactFlash controller */
6857 + P11_1610_CF_CD2,
6858 + R11_1610_CF_IOIS16,
6859 + V10_1610_CF_IREQ,
6860 + W10_1610_CF_RESET,
6861 + W11_1610_CF_CD1,
6862 +
6863 + /* parallel camera */
6864 + J15_1610_CAM_LCLK,
6865 + J18_1610_CAM_D7,
6866 + J19_1610_CAM_D6,
6867 + J14_1610_CAM_D5,
6868 + K18_1610_CAM_D4,
6869 + K19_1610_CAM_D3,
6870 + K15_1610_CAM_D2,
6871 + K14_1610_CAM_D1,
6872 + L19_1610_CAM_D0,
6873 + L18_1610_CAM_VS,
6874 + L15_1610_CAM_HS,
6875 + M19_1610_CAM_RSTZ,
6876 + Y15_1610_CAM_OUTCLK,
6877 +
6878 + /* serial camera */
6879 + H19_1610_CAM_EXCLK,
6880 + Y12_1610_CCP_CLKP,
6881 + W13_1610_CCP_CLKM,
6882 + W14_1610_CCP_DATAP,
6883 + Y14_1610_CCP_DATAM,
6884 +
6885 +};
6886 +
6887 +enum omap24xx_index {
6888 + /* 24xx I2C */
6889 + M19_24XX_I2C1_SCL,
6890 + L15_24XX_I2C1_SDA,
6891 + J15_24XX_I2C2_SCL,
6892 + H19_24XX_I2C2_SDA,
6893 +
6894 + /* 24xx Menelaus interrupt */
6895 + W19_24XX_SYS_NIRQ,
6896 +
6897 + /* 24xx clock */
6898 + W14_24XX_SYS_CLKOUT,
6899 +
6900 + /* 24xx GPMC chipselects, wait pin monitoring */
6901 + E2_GPMC_NCS2,
6902 + L2_GPMC_NCS7,
6903 + L3_GPMC_WAIT0,
6904 + N7_GPMC_WAIT1,
6905 + M1_GPMC_WAIT2,
6906 + P1_GPMC_WAIT3,
6907 +
6908 + /* 242X McBSP */
6909 + Y15_24XX_MCBSP2_CLKX,
6910 + R14_24XX_MCBSP2_FSX,
6911 + W15_24XX_MCBSP2_DR,
6912 + V15_24XX_MCBSP2_DX,
6913 +
6914 + /* 24xx GPIO */
6915 + M21_242X_GPIO11,
6916 + P21_242X_GPIO12,
6917 + AA10_242X_GPIO13,
6918 + AA6_242X_GPIO14,
6919 + AA4_242X_GPIO15,
6920 + Y11_242X_GPIO16,
6921 + AA12_242X_GPIO17,
6922 + AA8_242X_GPIO58,
6923 + Y20_24XX_GPIO60,
6924 + W4__24XX_GPIO74,
6925 + N15_24XX_GPIO85,
6926 + M15_24XX_GPIO92,
6927 + P20_24XX_GPIO93,
6928 + P18_24XX_GPIO95,
6929 + M18_24XX_GPIO96,
6930 + L14_24XX_GPIO97,
6931 + J15_24XX_GPIO99,
6932 + V14_24XX_GPIO117,
6933 + P14_24XX_GPIO125,
6934 +
6935 + /* 242x DBG GPIO */
6936 + V4_242X_GPIO49,
6937 + W2_242X_GPIO50,
6938 + U4_242X_GPIO51,
6939 + V3_242X_GPIO52,
6940 + V2_242X_GPIO53,
6941 + V6_242X_GPIO53,
6942 + T4_242X_GPIO54,
6943 + Y4_242X_GPIO54,
6944 + T3_242X_GPIO55,
6945 + U2_242X_GPIO56,
6946 +
6947 + /* 24xx external DMA requests */
6948 + AA10_242X_DMAREQ0,
6949 + AA6_242X_DMAREQ1,
6950 + E4_242X_DMAREQ2,
6951 + G4_242X_DMAREQ3,
6952 + D3_242X_DMAREQ4,
6953 + E3_242X_DMAREQ5,
6954 +
6955 + /* UART3 */
6956 + K15_24XX_UART3_TX,
6957 + K14_24XX_UART3_RX,
6958 +
6959 + /* MMC/SDIO */
6960 + G19_24XX_MMC_CLKO,
6961 + H18_24XX_MMC_CMD,
6962 + F20_24XX_MMC_DAT0,
6963 + H14_24XX_MMC_DAT1,
6964 + E19_24XX_MMC_DAT2,
6965 + D19_24XX_MMC_DAT3,
6966 + F19_24XX_MMC_DAT_DIR0,
6967 + E20_24XX_MMC_DAT_DIR1,
6968 + F18_24XX_MMC_DAT_DIR2,
6969 + E18_24XX_MMC_DAT_DIR3,
6970 + G18_24XX_MMC_CMD_DIR,
6971 + H15_24XX_MMC_CLKI,
6972 +
6973 + /* Full speed USB */
6974 + J20_24XX_USB0_PUEN,
6975 + J19_24XX_USB0_VP,
6976 + K20_24XX_USB0_VM,
6977 + J18_24XX_USB0_RCV,
6978 + K19_24XX_USB0_TXEN,
6979 + J14_24XX_USB0_SE0,
6980 + K18_24XX_USB0_DAT,
6981 +
6982 + N14_24XX_USB1_SE0,
6983 + W12_24XX_USB1_SE0,
6984 + P15_24XX_USB1_DAT,
6985 + R13_24XX_USB1_DAT,
6986 + W20_24XX_USB1_TXEN,
6987 + P13_24XX_USB1_TXEN,
6988 + V19_24XX_USB1_RCV,
6989 + V12_24XX_USB1_RCV,
6990 +
6991 + AA10_24XX_USB2_SE0,
6992 + Y11_24XX_USB2_DAT,
6993 + AA12_24XX_USB2_TXEN,
6994 + AA6_24XX_USB2_RCV,
6995 + AA4_24XX_USB2_TLLSE0,
6996 +
6997 + /* Keypad GPIO*/
6998 + T19_24XX_KBR0,
6999 + R19_24XX_KBR1,
7000 + V18_24XX_KBR2,
7001 + M21_24XX_KBR3,
7002 + E5__24XX_KBR4,
7003 + M18_24XX_KBR5,
7004 + R20_24XX_KBC0,
7005 + M14_24XX_KBC1,
7006 + H19_24XX_KBC2,
7007 + V17_24XX_KBC3,
7008 + P21_24XX_KBC4,
7009 + L14_24XX_KBC5,
7010 + N19_24XX_KBC6,
7011 +
7012 + /* 24xx Menelaus Keypad GPIO */
7013 + B3__24XX_KBR5,
7014 + AA4_24XX_KBC2,
7015 + B13_24XX_KBC6,
7016 +
7017 + /* 2430 USB */
7018 + AD9_2430_USB0_PUEN,
7019 + Y11_2430_USB0_VP,
7020 + AD7_2430_USB0_VM,
7021 + AE7_2430_USB0_RCV,
7022 + AD4_2430_USB0_TXEN,
7023 + AF9_2430_USB0_SE0,
7024 + AE6_2430_USB0_DAT,
7025 + AD24_2430_USB1_SE0,
7026 + AB24_2430_USB1_RCV,
7027 + Y25_2430_USB1_TXEN,
7028 + AA26_2430_USB1_DAT,
7029 +
7030 + /* 2430 HS-USB */
7031 + AD9_2430_USB0HS_DATA3,
7032 + Y11_2430_USB0HS_DATA4,
7033 + AD7_2430_USB0HS_DATA5,
7034 + AE7_2430_USB0HS_DATA6,
7035 + AD4_2430_USB0HS_DATA2,
7036 + AF9_2430_USB0HS_DATA0,
7037 + AE6_2430_USB0HS_DATA1,
7038 + AE8_2430_USB0HS_CLK,
7039 + AD8_2430_USB0HS_DIR,
7040 + AE5_2430_USB0HS_STP,
7041 + AE9_2430_USB0HS_NXT,
7042 + AC7_2430_USB0HS_DATA7,
7043 +
7044 + /* 2430 McBSP */
7045 + AD6_2430_MCBSP_CLKS,
7046 +
7047 + AB2_2430_MCBSP1_CLKR,
7048 + AD5_2430_MCBSP1_FSR,
7049 + AA1_2430_MCBSP1_DX,
7050 + AF3_2430_MCBSP1_DR,
7051 + AB3_2430_MCBSP1_FSX,
7052 + Y9_2430_MCBSP1_CLKX,
7053 +
7054 + AC10_2430_MCBSP2_FSX,
7055 + AD16_2430_MCBSP2_CLX,
7056 + AE13_2430_MCBSP2_DX,
7057 + AD13_2430_MCBSP2_DR,
7058 + AC10_2430_MCBSP2_FSX_OFF,
7059 + AD16_2430_MCBSP2_CLX_OFF,
7060 + AE13_2430_MCBSP2_DX_OFF,
7061 + AD13_2430_MCBSP2_DR_OFF,
7062 +
7063 + AC9_2430_MCBSP3_CLKX,
7064 + AE4_2430_MCBSP3_FSX,
7065 + AE2_2430_MCBSP3_DR,
7066 + AF4_2430_MCBSP3_DX,
7067 +
7068 + N3_2430_MCBSP4_CLKX,
7069 + AD23_2430_MCBSP4_DR,
7070 + AB25_2430_MCBSP4_DX,
7071 + AC25_2430_MCBSP4_FSX,
7072 +
7073 + AE16_2430_MCBSP5_CLKX,
7074 + AF12_2430_MCBSP5_FSX,
7075 + K7_2430_MCBSP5_DX,
7076 + M1_2430_MCBSP5_DR,
7077 +
7078 + /* 2430 McSPI*/
7079 + Y18_2430_MCSPI1_CLK,
7080 + AD15_2430_MCSPI1_SIMO,
7081 + AE17_2430_MCSPI1_SOMI,
7082 + U1_2430_MCSPI1_CS0,
7083 +
7084 + /* Touchscreen GPIO */
7085 + AF19_2430_GPIO_85,
7086 +
7087 +};
7088 +
7089 +struct omap_mux_cfg {
7090 + struct pin_config *pins;
7091 + unsigned long size;
7092 + int (*cfg_reg)(const struct pin_config *cfg);
7093 +};
7094 +
7095 +#ifdef CONFIG_OMAP_MUX
7096 +/* setup pin muxing in Linux */
7097 +extern int omap1_mux_init(void);
7098 +extern int omap_mux_register(struct omap_mux_cfg *);
7099 +extern int omap_cfg_reg(unsigned long reg_cfg);
7100 +#else
7101 +/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
7102 +static inline int omap1_mux_init(void) { return 0; }
7103 +static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
7104 +#endif
7105 +
7106 +extern int omap2_mux_init(void);
7107 +
7108 +#endif
7109 --- /dev/null
7110 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/nand.h
7111 @@ -0,0 +1,24 @@
7112 +/*
7113 + * arch/arm/plat-omap/include/mach/nand.h
7114 + *
7115 + * Copyright (C) 2006 Micron Technology Inc.
7116 + *
7117 + * This program is free software; you can redistribute it and/or modify
7118 + * it under the terms of the GNU General Public License version 2 as
7119 + * published by the Free Software Foundation.
7120 + */
7121 +
7122 +#include <linux/mtd/partitions.h>
7123 +
7124 +struct omap_nand_platform_data {
7125 + unsigned int options;
7126 + int cs;
7127 + int gpio_irq;
7128 + struct mtd_partition *parts;
7129 + int nr_parts;
7130 + int (*nand_setup)(void __iomem *);
7131 + int (*dev_ready)(struct omap_nand_platform_data *);
7132 + int dma_channel;
7133 + void __iomem *gpmc_cs_baseaddr;
7134 + void __iomem *gpmc_baseaddr;
7135 +};
7136 --- /dev/null
7137 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap1510.h
7138 @@ -0,0 +1,50 @@
7139 +/* arch/arm/plat-omap/include/mach/omap1510.h
7140 + *
7141 + * Hardware definitions for TI OMAP1510 processor.
7142 + *
7143 + * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7144 + *
7145 + * This program is free software; you can redistribute it and/or modify it
7146 + * under the terms of the GNU General Public License as published by the
7147 + * Free Software Foundation; either version 2 of the License, or (at your
7148 + * option) any later version.
7149 + *
7150 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7151 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7152 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7153 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7154 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7155 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7156 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7157 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7158 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7159 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7160 + *
7161 + * You should have received a copy of the GNU General Public License along
7162 + * with this program; if not, write to the Free Software Foundation, Inc.,
7163 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7164 + */
7165 +
7166 +#ifndef __ASM_ARCH_OMAP15XX_H
7167 +#define __ASM_ARCH_OMAP15XX_H
7168 +
7169 +/*
7170 + * ----------------------------------------------------------------------------
7171 + * Base addresses
7172 + * ----------------------------------------------------------------------------
7173 + */
7174 +
7175 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7176 +
7177 +#define OMAP1510_DSP_BASE 0xE0000000
7178 +#define OMAP1510_DSP_SIZE 0x28000
7179 +#define OMAP1510_DSP_START 0xE0000000
7180 +
7181 +#define OMAP1510_DSPREG_BASE 0xE1000000
7182 +#define OMAP1510_DSPREG_SIZE SZ_128K
7183 +#define OMAP1510_DSPREG_START 0xE1000000
7184 +
7185 +#define OMAP1510_DSP_MMU_BASE (0xfffed200)
7186 +
7187 +#endif /* __ASM_ARCH_OMAP15XX_H */
7188 +
7189 --- /dev/null
7190 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap16xx.h
7191 @@ -0,0 +1,202 @@
7192 +/* arch/arm/plat-omap/include/mach/omap16xx.h
7193 + *
7194 + * Hardware definitions for TI OMAP1610/5912/1710 processors.
7195 + *
7196 + * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7197 + *
7198 + * This program is free software; you can redistribute it and/or modify it
7199 + * under the terms of the GNU General Public License as published by the
7200 + * Free Software Foundation; either version 2 of the License, or (at your
7201 + * option) any later version.
7202 + *
7203 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7204 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7205 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7206 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7207 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7208 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7209 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7210 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7211 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7212 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7213 + *
7214 + * You should have received a copy of the GNU General Public License along
7215 + * with this program; if not, write to the Free Software Foundation, Inc.,
7216 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7217 + */
7218 +
7219 +#ifndef __ASM_ARCH_OMAP16XX_H
7220 +#define __ASM_ARCH_OMAP16XX_H
7221 +
7222 +/*
7223 + * ----------------------------------------------------------------------------
7224 + * Base addresses
7225 + * ----------------------------------------------------------------------------
7226 + */
7227 +
7228 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7229 +
7230 +#define OMAP16XX_DSP_BASE 0xE0000000
7231 +#define OMAP16XX_DSP_SIZE 0x28000
7232 +#define OMAP16XX_DSP_START 0xE0000000
7233 +
7234 +#define OMAP16XX_DSPREG_BASE 0xE1000000
7235 +#define OMAP16XX_DSPREG_SIZE SZ_128K
7236 +#define OMAP16XX_DSPREG_START 0xE1000000
7237 +
7238 +#define OMAP16XX_SEC_BASE 0xFFFE4000
7239 +#define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000)
7240 +#define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800)
7241 +#define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000)
7242 +
7243 +/*
7244 + * ---------------------------------------------------------------------------
7245 + * Interrupts
7246 + * ---------------------------------------------------------------------------
7247 + */
7248 +#define OMAP_IH2_0_BASE (0xfffe0000)
7249 +#define OMAP_IH2_1_BASE (0xfffe0100)
7250 +#define OMAP_IH2_2_BASE (0xfffe0200)
7251 +#define OMAP_IH2_3_BASE (0xfffe0300)
7252 +
7253 +#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
7254 +#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
7255 +#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
7256 +#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
7257 +#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
7258 +#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
7259 +#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
7260 +
7261 +#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
7262 +#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
7263 +#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
7264 +#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
7265 +#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
7266 +#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
7267 +#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
7268 +
7269 +#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
7270 +#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
7271 +#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
7272 +#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
7273 +#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
7274 +#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
7275 +#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
7276 +
7277 +#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
7278 +#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
7279 +#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
7280 +#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
7281 +#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
7282 +#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
7283 +#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
7284 +
7285 +/*
7286 + * ----------------------------------------------------------------------------
7287 + * Clocks
7288 + * ----------------------------------------------------------------------------
7289 + */
7290 +#define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
7291 +
7292 +/*
7293 + * ----------------------------------------------------------------------------
7294 + * Pin configuration registers
7295 + * ----------------------------------------------------------------------------
7296 + */
7297 +#define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8)
7298 +#define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9)
7299 +#define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10)
7300 +#define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11)
7301 +#define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13)
7302 +
7303 +/*
7304 + * ----------------------------------------------------------------------------
7305 + * System control registers
7306 + * ----------------------------------------------------------------------------
7307 + */
7308 +#define OMAP1610_RESET_CONTROL 0xfffe1140
7309 +
7310 +/*
7311 + * ---------------------------------------------------------------------------
7312 + * TIPB bus interface
7313 + * ---------------------------------------------------------------------------
7314 + */
7315 +#define TIPB_SWITCH_BASE (0xfffbc800)
7316 +#define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160)
7317 +
7318 +/* UART3 Registers Mapping through MPU bus */
7319 +#define UART3_RHR (OMAP_UART3_BASE + 0)
7320 +#define UART3_THR (OMAP_UART3_BASE + 0)
7321 +#define UART3_DLL (OMAP_UART3_BASE + 0)
7322 +#define UART3_IER (OMAP_UART3_BASE + 4)
7323 +#define UART3_DLH (OMAP_UART3_BASE + 4)
7324 +#define UART3_IIR (OMAP_UART3_BASE + 8)
7325 +#define UART3_FCR (OMAP_UART3_BASE + 8)
7326 +#define UART3_EFR (OMAP_UART3_BASE + 8)
7327 +#define UART3_LCR (OMAP_UART3_BASE + 0x0C)
7328 +#define UART3_MCR (OMAP_UART3_BASE + 0x10)
7329 +#define UART3_XON1_ADDR1 (OMAP_UART3_BASE + 0x10)
7330 +#define UART3_XON2_ADDR2 (OMAP_UART3_BASE + 0x14)
7331 +#define UART3_LSR (OMAP_UART3_BASE + 0x14)
7332 +#define UART3_TCR (OMAP_UART3_BASE + 0x18)
7333 +#define UART3_MSR (OMAP_UART3_BASE + 0x18)
7334 +#define UART3_XOFF1 (OMAP_UART3_BASE + 0x18)
7335 +#define UART3_XOFF2 (OMAP_UART3_BASE + 0x1C)
7336 +#define UART3_SPR (OMAP_UART3_BASE + 0x1C)
7337 +#define UART3_TLR (OMAP_UART3_BASE + 0x1C)
7338 +#define UART3_MDR1 (OMAP_UART3_BASE + 0x20)
7339 +#define UART3_MDR2 (OMAP_UART3_BASE + 0x24)
7340 +#define UART3_SFLSR (OMAP_UART3_BASE + 0x28)
7341 +#define UART3_TXFLL (OMAP_UART3_BASE + 0x28)
7342 +#define UART3_RESUME (OMAP_UART3_BASE + 0x2C)
7343 +#define UART3_TXFLH (OMAP_UART3_BASE + 0x2C)
7344 +#define UART3_SFREGL (OMAP_UART3_BASE + 0x30)
7345 +#define UART3_RXFLL (OMAP_UART3_BASE + 0x30)
7346 +#define UART3_SFREGH (OMAP_UART3_BASE + 0x34)
7347 +#define UART3_RXFLH (OMAP_UART3_BASE + 0x34)
7348 +#define UART3_BLR (OMAP_UART3_BASE + 0x38)
7349 +#define UART3_ACREG (OMAP_UART3_BASE + 0x3C)
7350 +#define UART3_DIV16 (OMAP_UART3_BASE + 0x3C)
7351 +#define UART3_SCR (OMAP_UART3_BASE + 0x40)
7352 +#define UART3_SSR (OMAP_UART3_BASE + 0x44)
7353 +#define UART3_EBLR (OMAP_UART3_BASE + 0x48)
7354 +#define UART3_OSC_12M_SEL (OMAP_UART3_BASE + 0x4C)
7355 +#define UART3_MVR (OMAP_UART3_BASE + 0x50)
7356 +
7357 +/*
7358 + * ---------------------------------------------------------------------------
7359 + * Watchdog timer
7360 + * ---------------------------------------------------------------------------
7361 + */
7362 +
7363 +/* 32-bit Watchdog timer in OMAP 16XX */
7364 +#define OMAP_16XX_WATCHDOG_BASE (0xfffeb000)
7365 +#define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00)
7366 +#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
7367 +#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
7368 +#define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24)
7369 +#define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28)
7370 +#define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c)
7371 +#define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30)
7372 +#define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34)
7373 +#define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48)
7374 +
7375 +#define WCLR_PRE_SHIFT 5
7376 +#define WCLR_PTV_SHIFT 2
7377 +
7378 +#define WWPS_W_PEND_WSPR (1 << 4)
7379 +#define WWPS_W_PEND_WTGR (1 << 3)
7380 +#define WWPS_W_PEND_WLDR (1 << 2)
7381 +#define WWPS_W_PEND_WCRR (1 << 1)
7382 +#define WWPS_W_PEND_WCLR (1 << 0)
7383 +
7384 +#define WSPR_ENABLE_0 (0x0000bbbb)
7385 +#define WSPR_ENABLE_1 (0x00004444)
7386 +#define WSPR_DISABLE_0 (0x0000aaaa)
7387 +#define WSPR_DISABLE_1 (0x00005555)
7388 +
7389 +#define OMAP16XX_DSP_MMU_BASE (0xfffed200)
7390 +#define OMAP16XX_MAILBOX_BASE (0xfffcf000)
7391 +
7392 +#endif /* __ASM_ARCH_OMAP16XX_H */
7393 +
7394 --- /dev/null
7395 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap24xx.h
7396 @@ -0,0 +1,89 @@
7397 +/*
7398 + * arch/arm/plat-omap/include/mach/omap24xx.h
7399 + *
7400 + * This file contains the processor specific definitions
7401 + * of the TI OMAP24XX.
7402 + *
7403 + * Copyright (C) 2007 Texas Instruments.
7404 + * Copyright (C) 2007 Nokia Corporation.
7405 + *
7406 + * This program is free software; you can redistribute it and/or modify
7407 + * it under the terms of the GNU General Public License as published by
7408 + * the Free Software Foundation; either version 2 of the License, or
7409 + * (at your option) any later version.
7410 + *
7411 + * This program is distributed in the hope that it will be useful,
7412 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7413 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7414 + * GNU General Public License for more details.
7415 + *
7416 + * You should have received a copy of the GNU General Public License
7417 + * along with this program; if not, write to the Free Software
7418 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7419 + *
7420 + */
7421 +
7422 +#ifndef __ASM_ARCH_OMAP24XX_H
7423 +#define __ASM_ARCH_OMAP24XX_H
7424 +
7425 +/*
7426 + * Please place only base defines here and put the rest in device
7427 + * specific headers. Note also that some of these defines are needed
7428 + * for omap1 to compile without adding ifdefs.
7429 + */
7430 +
7431 +#define L4_24XX_BASE 0x48000000
7432 +#define L4_WK_243X_BASE 0x49000000
7433 +#define L3_24XX_BASE 0x68000000
7434 +
7435 +/* interrupt controller */
7436 +#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
7437 +#define OMAP24XX_IVA_INTC_BASE 0x40000000
7438 +
7439 +#define OMAP2420_CTRL_BASE L4_24XX_BASE
7440 +#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
7441 +#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
7442 +#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
7443 +#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
7444 +#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
7445 +#define OMAP2420_SMS_BASE 0x68008000
7446 +#define OMAP2420_GPMC_BASE 0x6800a000
7447 +
7448 +#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
7449 +#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
7450 +#define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000)
7451 +#define OMAP2430_PRM_BASE OMAP2430_CM_BASE
7452 +
7453 +#define OMAP243X_SMS_BASE 0x6C000000
7454 +#define OMAP243X_SDRC_BASE 0x6D000000
7455 +#define OMAP243X_GPMC_BASE 0x6E000000
7456 +#define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000)
7457 +#define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE
7458 +#define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000)
7459 +
7460 +/* DSP SS */
7461 +#define OMAP2420_DSP_BASE 0x58000000
7462 +#define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0)
7463 +#define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000)
7464 +#define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000)
7465 +
7466 +#define OMAP243X_DSP_BASE 0x5C000000
7467 +#define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0)
7468 +#define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000)
7469 +
7470 +/* Mailbox */
7471 +#define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000)
7472 +
7473 +/* Camera */
7474 +#define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000)
7475 +
7476 +/* Security */
7477 +#define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000)
7478 +#define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000)
7479 +#define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000)
7480 +#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
7481 +#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000)
7482 +#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000)
7483 +
7484 +#endif /* __ASM_ARCH_OMAP24XX_H */
7485 +
7486 --- /dev/null
7487 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap34xx.h
7488 @@ -0,0 +1,86 @@
7489 +/*
7490 + * arch/arm/plat-omap/include/mach/omap34xx.h
7491 + *
7492 + * This file contains the processor specific definitions of the TI OMAP34XX.
7493 + *
7494 + * Copyright (C) 2007 Texas Instruments.
7495 + * Copyright (C) 2007 Nokia Corporation.
7496 + *
7497 + * This program is free software; you can redistribute it and/or modify
7498 + * it under the terms of the GNU General Public License as published by
7499 + * the Free Software Foundation; either version 2 of the License, or
7500 + * (at your option) any later version.
7501 + *
7502 + * This program is distributed in the hope that it will be useful,
7503 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7504 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7505 + * GNU General Public License for more details.
7506 + *
7507 + * You should have received a copy of the GNU General Public License
7508 + * along with this program; if not, write to the Free Software
7509 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7510 + */
7511 +
7512 +#ifndef __ASM_ARCH_OMAP34XX_H
7513 +#define __ASM_ARCH_OMAP34XX_H
7514 +
7515 +/*
7516 + * Please place only base defines here and put the rest in device
7517 + * specific headers.
7518 + */
7519 +
7520 +#define L4_34XX_BASE 0x48000000
7521 +#define L4_WK_34XX_BASE 0x48300000
7522 +#define L4_PER_34XX_BASE 0x49000000
7523 +#define L4_EMU_34XX_BASE 0x54000000
7524 +#define L3_34XX_BASE 0x68000000
7525 +
7526 +#define OMAP3430_32KSYNCT_BASE 0x48320000
7527 +#define OMAP3430_CM_BASE 0x48004800
7528 +#define OMAP3430_PRM_BASE 0x48306800
7529 +#define OMAP343X_SMS_BASE 0x6C000000
7530 +#define OMAP343X_SDRC_BASE 0x6D000000
7531 +#define OMAP34XX_GPMC_BASE 0x6E000000
7532 +#define OMAP343X_SCM_BASE 0x48002000
7533 +#define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE
7534 +
7535 +#define OMAP34XX_IC_BASE 0x48200000
7536 +
7537 +#define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000)
7538 +#define OMAP3430_ISP_CBUFF_BASE (OMAP3430_ISP_BASE + 0x0100)
7539 +#define OMAP3430_ISP_CCP2_BASE (OMAP3430_ISP_BASE + 0x0400)
7540 +#define OMAP3430_ISP_CCDC_BASE (OMAP3430_ISP_BASE + 0x0600)
7541 +#define OMAP3430_ISP_HIST_BASE (OMAP3430_ISP_BASE + 0x0A00)
7542 +#define OMAP3430_ISP_H3A_BASE (OMAP3430_ISP_BASE + 0x0C00)
7543 +#define OMAP3430_ISP_PREV_BASE (OMAP3430_ISP_BASE + 0x0E00)
7544 +#define OMAP3430_ISP_RESZ_BASE (OMAP3430_ISP_BASE + 0x1000)
7545 +#define OMAP3430_ISP_SBL_BASE (OMAP3430_ISP_BASE + 0x1200)
7546 +#define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400)
7547 +#define OMAP3430_ISP_CSI2A_BASE (OMAP3430_ISP_BASE + 0x1800)
7548 +#define OMAP3430_ISP_CSI2PHY_BASE (OMAP3430_ISP_BASE + 0x1970)
7549 +
7550 +#define OMAP3430_ISP_END (OMAP3430_ISP_BASE + 0x06F)
7551 +#define OMAP3430_ISP_CBUFF_END (OMAP3430_ISP_CBUFF_BASE + 0x077)
7552 +#define OMAP3430_ISP_CCP2_END (OMAP3430_ISP_CCP2_BASE + 0x1EF)
7553 +#define OMAP3430_ISP_CCDC_END (OMAP3430_ISP_CCDC_BASE + 0x0A7)
7554 +#define OMAP3430_ISP_HIST_END (OMAP3430_ISP_HIST_BASE + 0x047)
7555 +#define OMAP3430_ISP_H3A_END (OMAP3430_ISP_H3A_BASE + 0x05F)
7556 +#define OMAP3430_ISP_PREV_END (OMAP3430_ISP_PREV_BASE + 0x09F)
7557 +#define OMAP3430_ISP_RESZ_END (OMAP3430_ISP_RESZ_BASE + 0x0AB)
7558 +#define OMAP3430_ISP_SBL_END (OMAP3430_ISP_SBL_BASE + 0x0FB)
7559 +#define OMAP3430_ISP_MMU_END (OMAP3430_ISP_MMU_BASE + 0x06F)
7560 +#define OMAP3430_ISP_CSI2A_END (OMAP3430_ISP_CSI2A_BASE + 0x16F)
7561 +#define OMAP3430_ISP_CSI2PHY_END (OMAP3430_ISP_CSI2PHY_BASE + 0x007)
7562 +
7563 +#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
7564 +#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
7565 +#define OMAP34XX_UHH_CONFIG_BASE (L4_34XX_BASE + 0x64000)
7566 +#define OMAP34XX_OHCI_BASE (L4_34XX_BASE + 0x64400)
7567 +#define OMAP34XX_EHCI_BASE (L4_34XX_BASE + 0x64800)
7568 +#define OMAP34XX_SR1_BASE 0x480C9000
7569 +#define OMAP34XX_SR2_BASE 0x480CB000
7570 +
7571 +#define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000)
7572 +
7573 +#endif /* __ASM_ARCH_OMAP34XX_H */
7574 +
7575 --- /dev/null
7576 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap44xx.h
7577 @@ -0,0 +1,48 @@
7578 +/*:
7579 + * Address mappings and base address for OMAP4 interconnects
7580 + * and peripherals.
7581 + *
7582 + * Copyright (C) 2009 Texas Instruments
7583 + *
7584 + * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
7585 + *
7586 + * This program is free software; you can redistribute it and/or modify
7587 + * it under the terms of the GNU General Public License version 2 as
7588 + * published by the Free Software Foundation.
7589 + */
7590 +#ifndef __ASM_ARCH_OMAP44XX_H
7591 +#define __ASM_ARCH_OMAP44XX_H
7592 +
7593 +/*
7594 + * Please place only base defines here and put the rest in device
7595 + * specific headers.
7596 + */
7597 +#define L4_44XX_BASE 0x4a000000
7598 +#define L4_WK_44XX_BASE 0x4a300000
7599 +#define L4_PER_44XX_BASE 0x48000000
7600 +#define L4_EMU_44XX_BASE 0x54000000
7601 +#define L3_44XX_BASE 0x44000000
7602 +#define OMAP44XX_EMIF1_BASE 0x4c000000
7603 +#define OMAP44XX_EMIF2_BASE 0x4d000000
7604 +#define OMAP44XX_DMM_BASE 0x4e000000
7605 +#define OMAP4430_32KSYNCT_BASE 0x4a304000
7606 +#define OMAP4430_CM1_BASE 0x4a004000
7607 +#define OMAP4430_CM_BASE OMAP4430_CM1_BASE
7608 +#define OMAP4430_CM2_BASE 0x4a008000
7609 +#define OMAP4430_PRM_BASE 0x4a306000
7610 +#define OMAP44XX_GPMC_BASE 0x50000000
7611 +#define OMAP443X_SCM_BASE 0x4a002000
7612 +#define OMAP443X_CTRL_BASE OMAP443X_SCM_BASE
7613 +#define OMAP44XX_IC_BASE 0x48200000
7614 +#define OMAP44XX_IVA_INTC_BASE 0x40000000
7615 +#define IRQ_SIR_IRQ 0x0040
7616 +#define OMAP44XX_GIC_DIST_BASE 0x48241000
7617 +#define OMAP44XX_GIC_CPU_BASE 0x48240100
7618 +#define OMAP44XX_SCU_BASE 0x48240000
7619 +#define OMAP44XX_LOCAL_TWD_BASE 0x48240600
7620 +#define OMAP44XX_WKUPGEN_BASE 0x48281000
7621 +
7622 +#define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000)
7623 +
7624 +#endif /* __ASM_ARCH_OMAP44XX_H */
7625 +
7626 --- /dev/null
7627 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap730.h
7628 @@ -0,0 +1,102 @@
7629 +/* arch/arm/plat-omap/include/mach/omap730.h
7630 + *
7631 + * Hardware definitions for TI OMAP730 processor.
7632 + *
7633 + * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7634 + *
7635 + * This program is free software; you can redistribute it and/or modify it
7636 + * under the terms of the GNU General Public License as published by the
7637 + * Free Software Foundation; either version 2 of the License, or (at your
7638 + * option) any later version.
7639 + *
7640 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7641 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7642 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7643 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7644 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7645 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7646 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7647 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7648 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7649 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7650 + *
7651 + * You should have received a copy of the GNU General Public License along
7652 + * with this program; if not, write to the Free Software Foundation, Inc.,
7653 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7654 + */
7655 +
7656 +#ifndef __ASM_ARCH_OMAP730_H
7657 +#define __ASM_ARCH_OMAP730_H
7658 +
7659 +/*
7660 + * ----------------------------------------------------------------------------
7661 + * Base addresses
7662 + * ----------------------------------------------------------------------------
7663 + */
7664 +
7665 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7666 +
7667 +#define OMAP730_DSP_BASE 0xE0000000
7668 +#define OMAP730_DSP_SIZE 0x50000
7669 +#define OMAP730_DSP_START 0xE0000000
7670 +
7671 +#define OMAP730_DSPREG_BASE 0xE1000000
7672 +#define OMAP730_DSPREG_SIZE SZ_128K
7673 +#define OMAP730_DSPREG_START 0xE1000000
7674 +
7675 +/*
7676 + * ----------------------------------------------------------------------------
7677 + * OMAP730 specific configuration registers
7678 + * ----------------------------------------------------------------------------
7679 + */
7680 +#define OMAP730_CONFIG_BASE 0xfffe1000
7681 +#define OMAP730_IO_CONF_0 0xfffe1070
7682 +#define OMAP730_IO_CONF_1 0xfffe1074
7683 +#define OMAP730_IO_CONF_2 0xfffe1078
7684 +#define OMAP730_IO_CONF_3 0xfffe107c
7685 +#define OMAP730_IO_CONF_4 0xfffe1080
7686 +#define OMAP730_IO_CONF_5 0xfffe1084
7687 +#define OMAP730_IO_CONF_6 0xfffe1088
7688 +#define OMAP730_IO_CONF_7 0xfffe108c
7689 +#define OMAP730_IO_CONF_8 0xfffe1090
7690 +#define OMAP730_IO_CONF_9 0xfffe1094
7691 +#define OMAP730_IO_CONF_10 0xfffe1098
7692 +#define OMAP730_IO_CONF_11 0xfffe109c
7693 +#define OMAP730_IO_CONF_12 0xfffe10a0
7694 +#define OMAP730_IO_CONF_13 0xfffe10a4
7695 +
7696 +#define OMAP730_MODE_1 0xfffe1010
7697 +#define OMAP730_MODE_2 0xfffe1014
7698 +
7699 +/* CSMI specials: in terms of base + offset */
7700 +#define OMAP730_MODE2_OFFSET 0x14
7701 +
7702 +/*
7703 + * ----------------------------------------------------------------------------
7704 + * OMAP730 traffic controller configuration registers
7705 + * ----------------------------------------------------------------------------
7706 + */
7707 +#define OMAP730_FLASH_CFG_0 0xfffecc10
7708 +#define OMAP730_FLASH_ACFG_0 0xfffecc50
7709 +#define OMAP730_FLASH_CFG_1 0xfffecc14
7710 +#define OMAP730_FLASH_ACFG_1 0xfffecc54
7711 +
7712 +/*
7713 + * ----------------------------------------------------------------------------
7714 + * OMAP730 DSP control registers
7715 + * ----------------------------------------------------------------------------
7716 + */
7717 +#define OMAP730_ICR_BASE 0xfffbb800
7718 +#define OMAP730_DSP_M_CTL 0xfffbb804
7719 +#define OMAP730_DSP_MMU_BASE 0xfffed200
7720 +
7721 +/*
7722 + * ----------------------------------------------------------------------------
7723 + * OMAP730 PCC_UPLD configuration registers
7724 + * ----------------------------------------------------------------------------
7725 + */
7726 +#define OMAP730_PCC_UPLD_CTRL_BASE (0xfffe0900)
7727 +#define OMAP730_PCC_UPLD_CTRL (OMAP730_PCC_UPLD_CTRL_BASE + 0x00)
7728 +
7729 +#endif /* __ASM_ARCH_OMAP730_H */
7730 +
7731 --- /dev/null
7732 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap7xx.h
7733 @@ -0,0 +1,104 @@
7734 +/* arch/arm/plat-omap/include/mach/omap7xx.h
7735 + *
7736 + * Hardware definitions for TI OMAP7XX processor.
7737 + *
7738 + * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7739 + * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>
7740 + * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>
7741 + *
7742 + * This program is free software; you can redistribute it and/or modify it
7743 + * under the terms of the GNU General Public License as published by the
7744 + * Free Software Foundation; either version 2 of the License, or (at your
7745 + * option) any later version.
7746 + *
7747 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7748 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7749 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7750 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7751 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7752 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7753 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7754 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7755 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7756 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7757 + *
7758 + * You should have received a copy of the GNU General Public License along
7759 + * with this program; if not, write to the Free Software Foundation, Inc.,
7760 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7761 + */
7762 +
7763 +#ifndef __ASM_ARCH_OMAP7XX_H
7764 +#define __ASM_ARCH_OMAP7XX_H
7765 +
7766 +/*
7767 + * ----------------------------------------------------------------------------
7768 + * Base addresses
7769 + * ----------------------------------------------------------------------------
7770 + */
7771 +
7772 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7773 +
7774 +#define OMAP7XX_DSP_BASE 0xE0000000
7775 +#define OMAP7XX_DSP_SIZE 0x50000
7776 +#define OMAP7XX_DSP_START 0xE0000000
7777 +
7778 +#define OMAP7XX_DSPREG_BASE 0xE1000000
7779 +#define OMAP7XX_DSPREG_SIZE SZ_128K
7780 +#define OMAP7XX_DSPREG_START 0xE1000000
7781 +
7782 +/*
7783 + * ----------------------------------------------------------------------------
7784 + * OMAP7XX specific configuration registers
7785 + * ----------------------------------------------------------------------------
7786 + */
7787 +#define OMAP7XX_CONFIG_BASE 0xfffe1000
7788 +#define OMAP7XX_IO_CONF_0 0xfffe1070
7789 +#define OMAP7XX_IO_CONF_1 0xfffe1074
7790 +#define OMAP7XX_IO_CONF_2 0xfffe1078
7791 +#define OMAP7XX_IO_CONF_3 0xfffe107c
7792 +#define OMAP7XX_IO_CONF_4 0xfffe1080
7793 +#define OMAP7XX_IO_CONF_5 0xfffe1084
7794 +#define OMAP7XX_IO_CONF_6 0xfffe1088
7795 +#define OMAP7XX_IO_CONF_7 0xfffe108c
7796 +#define OMAP7XX_IO_CONF_8 0xfffe1090
7797 +#define OMAP7XX_IO_CONF_9 0xfffe1094
7798 +#define OMAP7XX_IO_CONF_10 0xfffe1098
7799 +#define OMAP7XX_IO_CONF_11 0xfffe109c
7800 +#define OMAP7XX_IO_CONF_12 0xfffe10a0
7801 +#define OMAP7XX_IO_CONF_13 0xfffe10a4
7802 +
7803 +#define OMAP7XX_MODE_1 0xfffe1010
7804 +#define OMAP7XX_MODE_2 0xfffe1014
7805 +
7806 +/* CSMI specials: in terms of base + offset */
7807 +#define OMAP7XX_MODE2_OFFSET 0x14
7808 +
7809 +/*
7810 + * ----------------------------------------------------------------------------
7811 + * OMAP7XX traffic controller configuration registers
7812 + * ----------------------------------------------------------------------------
7813 + */
7814 +#define OMAP7XX_FLASH_CFG_0 0xfffecc10
7815 +#define OMAP7XX_FLASH_ACFG_0 0xfffecc50
7816 +#define OMAP7XX_FLASH_CFG_1 0xfffecc14
7817 +#define OMAP7XX_FLASH_ACFG_1 0xfffecc54
7818 +
7819 +/*
7820 + * ----------------------------------------------------------------------------
7821 + * OMAP7XX DSP control registers
7822 + * ----------------------------------------------------------------------------
7823 + */
7824 +#define OMAP7XX_ICR_BASE 0xfffbb800
7825 +#define OMAP7XX_DSP_M_CTL 0xfffbb804
7826 +#define OMAP7XX_DSP_MMU_BASE 0xfffed200
7827 +
7828 +/*
7829 + * ----------------------------------------------------------------------------
7830 + * OMAP7XX PCC_UPLD configuration registers
7831 + * ----------------------------------------------------------------------------
7832 + */
7833 +#define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900)
7834 +#define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)
7835 +
7836 +#endif /* __ASM_ARCH_OMAP7XX_H */
7837 +
7838 --- /dev/null
7839 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap850.h
7840 @@ -0,0 +1,102 @@
7841 +/* arch/arm/plat-omap/include/mach/omap850.h
7842 + *
7843 + * Hardware definitions for TI OMAP850 processor.
7844 + *
7845 + * Derived from omap730.h by Zebediah C. McClure <zmc@lurian.net>
7846 + *
7847 + * This program is free software; you can redistribute it and/or modify it
7848 + * under the terms of the GNU General Public License as published by the
7849 + * Free Software Foundation; either version 2 of the License, or (at your
7850 + * option) any later version.
7851 + *
7852 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7853 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7854 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7855 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7856 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7857 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7858 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7859 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7860 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7861 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7862 + *
7863 + * You should have received a copy of the GNU General Public License along
7864 + * with this program; if not, write to the Free Software Foundation, Inc.,
7865 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7866 + */
7867 +
7868 +#ifndef __ASM_ARCH_OMAP850_H
7869 +#define __ASM_ARCH_OMAP850_H
7870 +
7871 +/*
7872 + * ----------------------------------------------------------------------------
7873 + * Base addresses
7874 + * ----------------------------------------------------------------------------
7875 + */
7876 +
7877 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7878 +
7879 +#define OMAP850_DSP_BASE 0xE0000000
7880 +#define OMAP850_DSP_SIZE 0x50000
7881 +#define OMAP850_DSP_START 0xE0000000
7882 +
7883 +#define OMAP850_DSPREG_BASE 0xE1000000
7884 +#define OMAP850_DSPREG_SIZE SZ_128K
7885 +#define OMAP850_DSPREG_START 0xE1000000
7886 +
7887 +/*
7888 + * ----------------------------------------------------------------------------
7889 + * OMAP850 specific configuration registers
7890 + * ----------------------------------------------------------------------------
7891 + */
7892 +#define OMAP850_CONFIG_BASE 0xfffe1000
7893 +#define OMAP850_IO_CONF_0 0xfffe1070
7894 +#define OMAP850_IO_CONF_1 0xfffe1074
7895 +#define OMAP850_IO_CONF_2 0xfffe1078
7896 +#define OMAP850_IO_CONF_3 0xfffe107c
7897 +#define OMAP850_IO_CONF_4 0xfffe1080
7898 +#define OMAP850_IO_CONF_5 0xfffe1084
7899 +#define OMAP850_IO_CONF_6 0xfffe1088
7900 +#define OMAP850_IO_CONF_7 0xfffe108c
7901 +#define OMAP850_IO_CONF_8 0xfffe1090
7902 +#define OMAP850_IO_CONF_9 0xfffe1094
7903 +#define OMAP850_IO_CONF_10 0xfffe1098
7904 +#define OMAP850_IO_CONF_11 0xfffe109c
7905 +#define OMAP850_IO_CONF_12 0xfffe10a0
7906 +#define OMAP850_IO_CONF_13 0xfffe10a4
7907 +
7908 +#define OMAP850_MODE_1 0xfffe1010
7909 +#define OMAP850_MODE_2 0xfffe1014
7910 +
7911 +/* CSMI specials: in terms of base + offset */
7912 +#define OMAP850_MODE2_OFFSET 0x14
7913 +
7914 +/*
7915 + * ----------------------------------------------------------------------------
7916 + * OMAP850 traffic controller configuration registers
7917 + * ----------------------------------------------------------------------------
7918 + */
7919 +#define OMAP850_FLASH_CFG_0 0xfffecc10
7920 +#define OMAP850_FLASH_ACFG_0 0xfffecc50
7921 +#define OMAP850_FLASH_CFG_1 0xfffecc14
7922 +#define OMAP850_FLASH_ACFG_1 0xfffecc54
7923 +
7924 +/*
7925 + * ----------------------------------------------------------------------------
7926 + * OMAP850 DSP control registers
7927 + * ----------------------------------------------------------------------------
7928 + */
7929 +#define OMAP850_ICR_BASE 0xfffbb800
7930 +#define OMAP850_DSP_M_CTL 0xfffbb804
7931 +#define OMAP850_DSP_MMU_BASE 0xfffed200
7932 +
7933 +/*
7934 + * ----------------------------------------------------------------------------
7935 + * OMAP850 PCC_UPLD configuration registers
7936 + * ----------------------------------------------------------------------------
7937 + */
7938 +#define OMAP850_PCC_UPLD_CTRL_BASE (0xfffe0900)
7939 +#define OMAP850_PCC_UPLD_CTRL (OMAP850_PCC_UPLD_CTRL_BASE + 0x00)
7940 +
7941 +#endif /* __ASM_ARCH_OMAP850_H */
7942 +
7943 --- /dev/null
7944 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap-alsa.h
7945 @@ -0,0 +1,123 @@
7946 +/*
7947 + * arch/arm/plat-omap/include/mach/omap-alsa.h
7948 + *
7949 + * Alsa Driver for AIC23 and TSC2101 codecs on OMAP platform boards.
7950 + *
7951 + * Copyright (C) 2006 Mika Laitio <lamikr@cc.jyu.fi>
7952 + *
7953 + * Copyright (C) 2005 Instituto Nokia de Tecnologia - INdT - Manaus Brazil
7954 + * Written by Daniel Petrini, David Cohen, Anderson Briglia
7955 + * {daniel.petrini, david.cohen, anderson.briglia}@indt.org.br
7956 + *
7957 + * This program is free software; you can redistribute it and/or modify it
7958 + * under the terms of the GNU General Public License as published by the
7959 + * Free Software Foundation; either version 2 of the License, or (at your
7960 + * option) any later version.
7961 + *
7962 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7963 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7964 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7965 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7966 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7967 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7968 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7969 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7970 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7971 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7972 + *
7973 + * You should have received a copy of the GNU General Public License along
7974 + * with this program; if not, write to the Free Software Foundation, Inc.,
7975 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7976 + *
7977 + * History
7978 + * -------
7979 + *
7980 + * 2005/07/25 INdT-10LE Kernel Team - Alsa driver for omap osk,
7981 + * original version based in sa1100 driver
7982 + * and omap oss driver.
7983 + */
7984 +
7985 +#ifndef __OMAP_ALSA_H
7986 +#define __OMAP_ALSA_H
7987 +
7988 +#include <plat/dma.h>
7989 +#include <sound/core.h>
7990 +#include <sound/pcm.h>
7991 +#include <plat/mcbsp.h>
7992 +#include <linux/platform_device.h>
7993 +
7994 +#define DMA_BUF_SIZE (1024 * 8)
7995 +
7996 +/*
7997 + * Buffer management for alsa and dma
7998 + */
7999 +struct audio_stream {
8000 + char *id; /* identification string */
8001 + int stream_id; /* numeric identification */
8002 + int dma_dev; /* dma number of that device */
8003 + int *lch; /* Chain of channels this stream is linked to */
8004 + char started; /* to store if the chain was started or not */
8005 + int dma_q_head; /* DMA Channel Q Head */
8006 + int dma_q_tail; /* DMA Channel Q Tail */
8007 + char dma_q_count; /* DMA Channel Q Count */
8008 + int active:1; /* we are using this stream for transfer now */
8009 + int period; /* current transfer period */
8010 + int periods; /* current count of periods registerd in the DMA engine */
8011 + spinlock_t dma_lock; /* for locking in DMA operations */
8012 + struct snd_pcm_substream *stream; /* the pcm stream */
8013 + unsigned linked:1; /* dma channels linked */
8014 + int offset; /* store start position of the last period in the alsa buffer */
8015 + int (*hw_start)(void); /* interface to start HW interface, e.g. McBSP */
8016 + int (*hw_stop)(void); /* interface to stop HW interface, e.g. McBSP */
8017 +};
8018 +
8019 +/*
8020 + * Alsa card structure for aic23
8021 + */
8022 +struct snd_card_omap_codec {
8023 + struct snd_card *card;
8024 + struct snd_pcm *pcm;
8025 + long samplerate;
8026 + struct audio_stream s[2]; /* playback & capture */
8027 +};
8028 +
8029 +/* Codec specific information and function pointers.
8030 + * Codec (omap-alsa-aic23.c and omap-alsa-tsc2101.c)
8031 + * are responsible for defining the function pointers.
8032 + */
8033 +struct omap_alsa_codec_config {
8034 + char *name;
8035 + struct omap_mcbsp_reg_cfg *mcbsp_regs_alsa;
8036 + struct snd_pcm_hw_constraint_list *hw_constraints_rates;
8037 + struct snd_pcm_hardware *snd_omap_alsa_playback;
8038 + struct snd_pcm_hardware *snd_omap_alsa_capture;
8039 + void (*codec_configure_dev)(void);
8040 + void (*codec_set_samplerate)(long);
8041 + void (*codec_clock_setup)(void);
8042 + int (*codec_clock_on)(void);
8043 + int (*codec_clock_off)(void);
8044 + int (*get_default_samplerate)(void);
8045 +};
8046 +
8047 +/*********** Mixer function prototypes *************************/
8048 +int snd_omap_mixer(struct snd_card_omap_codec *);
8049 +void snd_omap_init_mixer(void);
8050 +
8051 +#ifdef CONFIG_PM
8052 +void snd_omap_suspend_mixer(void);
8053 +void snd_omap_resume_mixer(void);
8054 +#endif
8055 +
8056 +int snd_omap_alsa_post_probe(struct platform_device *pdev, struct omap_alsa_codec_config *config);
8057 +int snd_omap_alsa_remove(struct platform_device *pdev);
8058 +#ifdef CONFIG_PM
8059 +int snd_omap_alsa_suspend(struct platform_device *pdev, pm_message_t state);
8060 +int snd_omap_alsa_resume(struct platform_device *pdev);
8061 +#else
8062 +#define snd_omap_alsa_suspend NULL
8063 +#define snd_omap_alsa_resume NULL
8064 +#endif
8065 +
8066 +void callback_omap_alsa_sound_dma(void *);
8067 +
8068 +#endif
8069 --- /dev/null
8070 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap_device.h
8071 @@ -0,0 +1,143 @@
8072 +/*
8073 + * omap_device headers
8074 + *
8075 + * Copyright (C) 2009 Nokia Corporation
8076 + * Paul Walmsley
8077 + *
8078 + * Developed in collaboration with (alphabetical order): Benoit
8079 + * Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram
8080 + * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard
8081 + * Woodruff
8082 + *
8083 + * This program is free software; you can redistribute it and/or modify
8084 + * it under the terms of the GNU General Public License version 2 as
8085 + * published by the Free Software Foundation.
8086 + *
8087 + * Eventually this type of functionality should either be
8088 + * a) implemented via arch-specific pointers in platform_device
8089 + * or
8090 + * b) implemented as a proper omap_bus/omap_device in Linux, no more
8091 + * platform_device
8092 + *
8093 + * omap_device differs from omap_hwmod in that it includes external
8094 + * (e.g., board- and system-level) integration details. omap_hwmod
8095 + * stores hardware data that is invariant for a given OMAP chip.
8096 + *
8097 + * To do:
8098 + * - GPIO integration
8099 + * - regulator integration
8100 + *
8101 + */
8102 +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
8103 +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
8104 +
8105 +#include <linux/kernel.h>
8106 +#include <linux/platform_device.h>
8107 +
8108 +#include <plat/omap_hwmod.h>
8109 +
8110 +/* omap_device._state values */
8111 +#define OMAP_DEVICE_STATE_UNKNOWN 0
8112 +#define OMAP_DEVICE_STATE_ENABLED 1
8113 +#define OMAP_DEVICE_STATE_IDLE 2
8114 +#define OMAP_DEVICE_STATE_SHUTDOWN 3
8115 +
8116 +/**
8117 + * struct omap_device - omap_device wrapper for platform_devices
8118 + * @pdev: platform_device
8119 + * @hwmods: (one .. many per omap_device)
8120 + * @hwmods_cnt: ARRAY_SIZE() of @hwmods
8121 + * @pm_lats: ptr to an omap_device_pm_latency table
8122 + * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats
8123 + * @pm_lat_level: array index of the last odpl entry executed - -1 if never
8124 + * @dev_wakeup_lat: dev wakeup latency in nanoseconds
8125 + * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
8126 + * @_state: one of OMAP_DEVICE_STATE_* (see above)
8127 + * @flags: device flags
8128 + *
8129 + * Integrates omap_hwmod data into Linux platform_device.
8130 + *
8131 + * Field names beginning with underscores are for the internal use of
8132 + * the omap_device code.
8133 + *
8134 + */
8135 +struct omap_device {
8136 + struct platform_device pdev;
8137 + struct omap_hwmod **hwmods;
8138 + struct omap_device_pm_latency *pm_lats;
8139 + u32 dev_wakeup_lat;
8140 + u32 _dev_wakeup_lat_limit;
8141 + u8 pm_lats_cnt;
8142 + s8 pm_lat_level;
8143 + u8 hwmods_cnt;
8144 + u8 _state;
8145 +};
8146 +
8147 +/* Device driver interface (call via platform_data fn ptrs) */
8148 +
8149 +int omap_device_enable(struct platform_device *pdev);
8150 +int omap_device_idle(struct platform_device *pdev);
8151 +int omap_device_shutdown(struct platform_device *pdev);
8152 +
8153 +/* Core code interface */
8154 +
8155 +int omap_device_count_resources(struct omap_device *od);
8156 +int omap_device_fill_resources(struct omap_device *od, struct resource *res);
8157 +
8158 +struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
8159 + struct omap_hwmod *oh, void *pdata,
8160 + int pdata_len,
8161 + struct omap_device_pm_latency *pm_lats,
8162 + int pm_lats_cnt);
8163 +
8164 +struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
8165 + struct omap_hwmod **oh, int oh_cnt,
8166 + void *pdata, int pdata_len,
8167 + struct omap_device_pm_latency *pm_lats,
8168 + int pm_lats_cnt);
8169 +
8170 +int omap_device_register(struct omap_device *od);
8171 +
8172 +/* OMAP PM interface */
8173 +int omap_device_align_pm_lat(struct platform_device *pdev,
8174 + u32 new_wakeup_lat_limit);
8175 +struct powerdomain *omap_device_get_pwrdm(struct omap_device *od);
8176 +
8177 +/* Other */
8178 +
8179 +int omap_device_idle_hwmods(struct omap_device *od);
8180 +int omap_device_enable_hwmods(struct omap_device *od);
8181 +
8182 +int omap_device_disable_clocks(struct omap_device *od);
8183 +int omap_device_enable_clocks(struct omap_device *od);
8184 +
8185 +
8186 +/*
8187 + * Entries should be kept in latency order ascending
8188 + *
8189 + * deact_lat is the maximum number of microseconds required to complete
8190 + * deactivate_func() at the device's slowest OPP.
8191 + *
8192 + * act_lat is the maximum number of microseconds required to complete
8193 + * activate_func() at the device's slowest OPP.
8194 + *
8195 + * This will result in some suboptimal power management decisions at fast
8196 + * OPPs, but avoids having to recompute all device power management decisions
8197 + * if the system shifts from a fast OPP to a slow OPP (in order to meet
8198 + * latency requirements).
8199 + *
8200 + * XXX should deactivate_func/activate_func() take platform_device pointers
8201 + * rather than omap_device pointers?
8202 + */
8203 +struct omap_device_pm_latency {
8204 + u32 deactivate_lat;
8205 + int (*deactivate_func)(struct omap_device *od);
8206 + u32 activate_lat;
8207 + int (*activate_func)(struct omap_device *od);
8208 +};
8209 +
8210 +
8211 +/* Get omap_device pointer from platform_device pointer */
8212 +#define to_omap_device(x) container_of((x), struct omap_device, pdev)
8213 +
8214 +#endif
8215 --- /dev/null
8216 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap_hwmod.h
8217 @@ -0,0 +1,467 @@
8218 +/*
8219 + * omap_hwmod macros, structures
8220 + *
8221 + * Copyright (C) 2009 Nokia Corporation
8222 + * Paul Walmsley
8223 + *
8224 + * Created in collaboration with (alphabetical order): Benoit Cousson,
8225 + * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
8226 + * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
8227 + *
8228 + * This program is free software; you can redistribute it and/or modify
8229 + * it under the terms of the GNU General Public License version 2 as
8230 + * published by the Free Software Foundation.
8231 + *
8232 + * These headers and macros are used to define OMAP on-chip module
8233 + * data and their integration with other OMAP modules and Linux.
8234 + *
8235 + * References:
8236 + * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
8237 + * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
8238 + * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
8239 + * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
8240 + * - Open Core Protocol Specification 2.2
8241 + *
8242 + * To do:
8243 + * - add interconnect error log structures
8244 + * - add pinmuxing
8245 + * - init_conn_id_bit (CONNID_BIT_VECTOR)
8246 + * - implement default hwmod SMS/SDRC flags?
8247 + *
8248 + */
8249 +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
8250 +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
8251 +
8252 +#include <linux/kernel.h>
8253 +#include <linux/ioport.h>
8254 +
8255 +#include <plat/cpu.h>
8256 +
8257 +struct omap_device;
8258 +
8259 +/* OCP SYSCONFIG bit shifts/masks */
8260 +#define SYSC_MIDLEMODE_SHIFT 12
8261 +#define SYSC_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT)
8262 +#define SYSC_CLOCKACTIVITY_SHIFT 8
8263 +#define SYSC_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT)
8264 +#define SYSC_SIDLEMODE_SHIFT 3
8265 +#define SYSC_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT)
8266 +#define SYSC_ENAWAKEUP_SHIFT 2
8267 +#define SYSC_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT)
8268 +#define SYSC_SOFTRESET_SHIFT 1
8269 +#define SYSC_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT)
8270 +#define SYSC_AUTOIDLE_SHIFT 0
8271 +#define SYSC_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT)
8272 +
8273 +/* OCP SYSSTATUS bit shifts/masks */
8274 +#define SYSS_RESETDONE_SHIFT 0
8275 +#define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT)
8276 +
8277 +/* Master standby/slave idle mode flags */
8278 +#define HWMOD_IDLEMODE_FORCE (1 << 0)
8279 +#define HWMOD_IDLEMODE_NO (1 << 1)
8280 +#define HWMOD_IDLEMODE_SMART (1 << 2)
8281 +
8282 +
8283 +/**
8284 + * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
8285 + * @name: name of the IRQ channel (module local name)
8286 + * @irq_ch: IRQ channel ID
8287 + *
8288 + * @name should be something short, e.g., "tx" or "rx". It is for use
8289 + * by platform_get_resource_byname(). It is defined locally to the
8290 + * hwmod.
8291 + */
8292 +struct omap_hwmod_irq_info {
8293 + const char *name;
8294 + u16 irq;
8295 +};
8296 +
8297 +/**
8298 + * struct omap_hwmod_dma_info - DMA channels used by the hwmod
8299 + * @name: name of the DMA channel (module local name)
8300 + * @dma_ch: DMA channel ID
8301 + *
8302 + * @name should be something short, e.g., "tx" or "rx". It is for use
8303 + * by platform_get_resource_byname(). It is defined locally to the
8304 + * hwmod.
8305 + */
8306 +struct omap_hwmod_dma_info {
8307 + const char *name;
8308 + u16 dma_ch;
8309 +};
8310 +
8311 +/**
8312 + * struct omap_hwmod_opt_clk - optional clocks used by this hwmod
8313 + * @role: "sys", "32k", "tv", etc -- for use in clk_get()
8314 + * @clkdev_dev_id: opt clock: clkdev dev_id string
8315 + * @clkdev_con_id: opt clock: clkdev con_id string
8316 + * @_clk: pointer to the struct clk (filled in at runtime)
8317 + *
8318 + * The module's interface clock and main functional clock should not
8319 + * be added as optional clocks.
8320 + */
8321 +struct omap_hwmod_opt_clk {
8322 + const char *role;
8323 + const char *clkdev_dev_id;
8324 + const char *clkdev_con_id;
8325 + struct clk *_clk;
8326 +};
8327 +
8328 +
8329 +/* omap_hwmod_omap2_firewall.flags bits */
8330 +#define OMAP_FIREWALL_L3 (1 << 0)
8331 +#define OMAP_FIREWALL_L4 (1 << 1)
8332 +
8333 +/**
8334 + * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data
8335 + * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_*
8336 + * @l4_fw_region: L4 firewall region ID
8337 + * @l4_prot_group: L4 protection group ID
8338 + * @flags: (see omap_hwmod_omap2_firewall.flags macros above)
8339 + */
8340 +struct omap_hwmod_omap2_firewall {
8341 + u8 l3_perm_bit;
8342 + u8 l4_fw_region;
8343 + u8 l4_prot_group;
8344 + u8 flags;
8345 +};
8346 +
8347 +
8348 +/*
8349 + * omap_hwmod_addr_space.flags bits
8350 + *
8351 + * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init.
8352 + * ADDR_TYPE_RT: Address space contains module register target data.
8353 + */
8354 +#define ADDR_MAP_ON_INIT (1 << 0)
8355 +#define ADDR_TYPE_RT (1 << 1)
8356 +
8357 +/**
8358 + * struct omap_hwmod_addr_space - MPU address space handled by the hwmod
8359 + * @pa_start: starting physical address
8360 + * @pa_end: ending physical address
8361 + * @flags: (see omap_hwmod_addr_space.flags macros above)
8362 + *
8363 + * Address space doesn't necessarily follow physical interconnect
8364 + * structure. GPMC is one example.
8365 + */
8366 +struct omap_hwmod_addr_space {
8367 + u32 pa_start;
8368 + u32 pa_end;
8369 + u8 flags;
8370 +};
8371 +
8372 +
8373 +/*
8374 + * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this
8375 + * interface to interact with the hwmod. Used to add sleep dependencies
8376 + * when the module is enabled or disabled.
8377 + */
8378 +#define OCP_USER_MPU (1 << 0)
8379 +#define OCP_USER_SDMA (1 << 1)
8380 +
8381 +/* omap_hwmod_ocp_if.flags bits */
8382 +#define OCPIF_HAS_IDLEST (1 << 0)
8383 +#define OCPIF_SWSUP_IDLE (1 << 1)
8384 +#define OCPIF_CAN_BURST (1 << 2)
8385 +
8386 +/**
8387 + * struct omap_hwmod_ocp_if - OCP interface data
8388 + * @master: struct omap_hwmod that initiates OCP transactions on this link
8389 + * @slave: struct omap_hwmod that responds to OCP transactions on this link
8390 + * @addr: address space associated with this link
8391 + * @clkdev_dev_id: interface clock: clkdev dev_id string
8392 + * @clkdev_con_id: interface clock: clkdev con_id string
8393 + * @_clk: pointer to the interface struct clk (filled in at runtime)
8394 + * @fw: interface firewall data
8395 + * @addr_cnt: ARRAY_SIZE(@addr)
8396 + * @width: OCP data width
8397 + * @thread_cnt: number of threads
8398 + * @max_burst_len: maximum burst length in @width sized words (0 if unlimited)
8399 + * @user: initiators using this interface (see OCP_USER_* macros above)
8400 + * @flags: OCP interface flags (see OCPIF_* macros above)
8401 + *
8402 + * It may also be useful to add a tag_cnt field for OCP2.x devices.
8403 + *
8404 + * Parameter names beginning with an underscore are managed internally by
8405 + * the omap_hwmod code and should not be set during initialization.
8406 + */
8407 +struct omap_hwmod_ocp_if {
8408 + struct omap_hwmod *master;
8409 + struct omap_hwmod *slave;
8410 + struct omap_hwmod_addr_space *addr;
8411 + const char *clkdev_dev_id;
8412 + const char *clkdev_con_id;
8413 + struct clk *_clk;
8414 + union {
8415 + struct omap_hwmod_omap2_firewall omap2;
8416 + } fw;
8417 + u8 addr_cnt;
8418 + u8 width;
8419 + u8 thread_cnt;
8420 + u8 max_burst_len;
8421 + u8 user;
8422 + u8 flags;
8423 +};
8424 +
8425 +
8426 +/* Macros for use in struct omap_hwmod_sysconfig */
8427 +
8428 +/* Flags for use in omap_hwmod_sysconfig.idlemodes */
8429 +#define MASTER_STANDBY_SHIFT 2
8430 +#define SLAVE_IDLE_SHIFT 0
8431 +#define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT)
8432 +#define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT)
8433 +#define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT)
8434 +#define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
8435 +#define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
8436 +#define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
8437 +
8438 +/* omap_hwmod_sysconfig.sysc_flags capability flags */
8439 +#define SYSC_HAS_AUTOIDLE (1 << 0)
8440 +#define SYSC_HAS_SOFTRESET (1 << 1)
8441 +#define SYSC_HAS_ENAWAKEUP (1 << 2)
8442 +#define SYSC_HAS_EMUFREE (1 << 3)
8443 +#define SYSC_HAS_CLOCKACTIVITY (1 << 4)
8444 +#define SYSC_HAS_SIDLEMODE (1 << 5)
8445 +#define SYSC_HAS_MIDLEMODE (1 << 6)
8446 +#define SYSS_MISSING (1 << 7)
8447 +
8448 +/* omap_hwmod_sysconfig.clockact flags */
8449 +#define CLOCKACT_TEST_BOTH 0x0
8450 +#define CLOCKACT_TEST_MAIN 0x1
8451 +#define CLOCKACT_TEST_ICLK 0x2
8452 +#define CLOCKACT_TEST_NONE 0x3
8453 +
8454 +/**
8455 + * struct omap_hwmod_sysconfig - hwmod OCP_SYSCONFIG/OCP_SYSSTATUS data
8456 + * @rev_offs: IP block revision register offset (from module base addr)
8457 + * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
8458 + * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
8459 + * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
8460 + * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
8461 + * @clockact: the default value of the module CLOCKACTIVITY bits
8462 + *
8463 + * @clockact describes to the module which clocks are likely to be
8464 + * disabled when the PRCM issues its idle request to the module. Some
8465 + * modules have separate clockdomains for the interface clock and main
8466 + * functional clock, and can check whether they should acknowledge the
8467 + * idle request based on the internal module functionality that has
8468 + * been associated with the clocks marked in @clockact. This field is
8469 + * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below)
8470 + *
8471 + */
8472 +struct omap_hwmod_sysconfig {
8473 + u16 rev_offs;
8474 + u16 sysc_offs;
8475 + u16 syss_offs;
8476 + u8 idlemodes;
8477 + u8 sysc_flags;
8478 + u8 clockact;
8479 +};
8480 +
8481 +/**
8482 + * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data
8483 + * @module_offs: PRCM submodule offset from the start of the PRM/CM
8484 + * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3)
8485 + * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs
8486 + * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3)
8487 + * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit
8488 + * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit
8489 + *
8490 + * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST,
8491 + * WKEN, GRPSEL registers. In an ideal world, no extra information
8492 + * would be needed for IDLEST information, but alas, there are some
8493 + * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit
8494 + * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST)
8495 + */
8496 +struct omap_hwmod_omap2_prcm {
8497 + s16 module_offs;
8498 + u8 prcm_reg_id;
8499 + u8 module_bit;
8500 + u8 idlest_reg_id;
8501 + u8 idlest_idle_bit;
8502 + u8 idlest_stdby_bit;
8503 +};
8504 +
8505 +
8506 +/**
8507 + * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
8508 + * @module_offs: PRCM submodule offset from the start of the PRM/CM1/CM2
8509 + * @device_offs: device register offset from @module_offs
8510 + * @submodule_wkdep_bit: bit shift of the WKDEP range
8511 + */
8512 +struct omap_hwmod_omap4_prcm {
8513 + u32 module_offs;
8514 + u16 device_offs;
8515 + u8 submodule_wkdep_bit;
8516 +};
8517 +
8518 +
8519 +/*
8520 + * omap_hwmod.flags definitions
8521 + *
8522 + * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
8523 + * of idle, rather than relying on module smart-idle
8524 + * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
8525 + * of standby, rather than relying on module smart-standby
8526 + * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
8527 + * SDRAM controller, etc.
8528 + * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
8529 + * controller, etc.
8530 + * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
8531 + * when module is enabled, rather than the default, which is to
8532 + * enable autoidle
8533 + * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
8534 + */
8535 +#define HWMOD_SWSUP_SIDLE (1 << 0)
8536 +#define HWMOD_SWSUP_MSTANDBY (1 << 1)
8537 +#define HWMOD_INIT_NO_RESET (1 << 2)
8538 +#define HWMOD_INIT_NO_IDLE (1 << 3)
8539 +#define HWMOD_NO_OCP_AUTOIDLE (1 << 4)
8540 +#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5)
8541 +
8542 +/*
8543 + * omap_hwmod._int_flags definitions
8544 + * These are for internal use only and are managed by the omap_hwmod code.
8545 + *
8546 + * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
8547 + * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
8548 + * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
8549 + */
8550 +#define _HWMOD_NO_MPU_PORT (1 << 0)
8551 +#define _HWMOD_WAKEUP_ENABLED (1 << 1)
8552 +#define _HWMOD_SYSCONFIG_LOADED (1 << 2)
8553 +
8554 +/*
8555 + * omap_hwmod._state definitions
8556 + *
8557 + * INITIALIZED: reset (optionally), initialized, enabled, disabled
8558 + * (optionally)
8559 + *
8560 + *
8561 + */
8562 +#define _HWMOD_STATE_UNKNOWN 0
8563 +#define _HWMOD_STATE_REGISTERED 1
8564 +#define _HWMOD_STATE_CLKS_INITED 2
8565 +#define _HWMOD_STATE_INITIALIZED 3
8566 +#define _HWMOD_STATE_ENABLED 4
8567 +#define _HWMOD_STATE_IDLE 5
8568 +#define _HWMOD_STATE_DISABLED 6
8569 +
8570 +/**
8571 + * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
8572 + * @name: name of the hwmod
8573 + * @od: struct omap_device currently associated with this hwmod (internal use)
8574 + * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
8575 + * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt)
8576 + * @prcm: PRCM data pertaining to this hwmod
8577 + * @clkdev_dev_id: main clock: clkdev dev_id string
8578 + * @clkdev_con_id: main clock: clkdev con_id string
8579 + * @_clk: pointer to the main struct clk (filled in at runtime)
8580 + * @opt_clks: other device clocks that drivers can request (0..*)
8581 + * @masters: ptr to array of OCP ifs that this hwmod can initiate on
8582 + * @slaves: ptr to array of OCP ifs that this hwmod can respond on
8583 + * @sysconfig: device SYSCONFIG/SYSSTATUS register data
8584 + * @dev_attr: arbitrary device attributes that can be passed to the driver
8585 + * @_sysc_cache: internal-use hwmod flags
8586 + * @_rt_va: cached register target start address (internal use)
8587 + * @_mpu_port_index: cached MPU register target slave ID (internal use)
8588 + * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6)
8589 + * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift
8590 + * @mpu_irqs_cnt: number of @mpu_irqs
8591 + * @sdma_chs_cnt: number of @sdma_chs
8592 + * @opt_clks_cnt: number of @opt_clks
8593 + * @master_cnt: number of @master entries
8594 + * @slaves_cnt: number of @slave entries
8595 + * @response_lat: device OCP response latency (in interface clock cycles)
8596 + * @_int_flags: internal-use hwmod flags
8597 + * @_state: internal-use hwmod state
8598 + * @flags: hwmod flags (documented below)
8599 + * @omap_chip: OMAP chips this hwmod is present on
8600 + * @node: list node for hwmod list (internal use)
8601 + *
8602 + * @clkdev_dev_id, @clkdev_con_id, and @clk all refer to this module's "main
8603 + * clock," which for our purposes is defined as "the functional clock needed
8604 + * for register accesses to complete." Modules may not have a main clock if
8605 + * the interface clock also serves as a main clock.
8606 + *
8607 + * Parameter names beginning with an underscore are managed internally by
8608 + * the omap_hwmod code and should not be set during initialization.
8609 + */
8610 +struct omap_hwmod {
8611 + const char *name;
8612 + struct omap_device *od;
8613 + struct omap_hwmod_irq_info *mpu_irqs;
8614 + struct omap_hwmod_dma_info *sdma_chs;
8615 + union {
8616 + struct omap_hwmod_omap2_prcm omap2;
8617 + struct omap_hwmod_omap4_prcm omap4;
8618 + } prcm;
8619 + const char *clkdev_dev_id;
8620 + const char *clkdev_con_id;
8621 + struct clk *_clk;
8622 + struct omap_hwmod_opt_clk *opt_clks;
8623 + struct omap_hwmod_ocp_if **masters; /* connect to *_IA */
8624 + struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */
8625 + struct omap_hwmod_sysconfig *sysconfig;
8626 + void *dev_attr;
8627 + u32 _sysc_cache;
8628 + void __iomem *_rt_va;
8629 + struct list_head node;
8630 + u16 flags;
8631 + u8 _mpu_port_index;
8632 + u8 msuspendmux_reg_id;
8633 + u8 msuspendmux_shift;
8634 + u8 response_lat;
8635 + u8 mpu_irqs_cnt;
8636 + u8 sdma_chs_cnt;
8637 + u8 opt_clks_cnt;
8638 + u8 masters_cnt;
8639 + u8 slaves_cnt;
8640 + u8 hwmods_cnt;
8641 + u8 _int_flags;
8642 + u8 _state;
8643 + const struct omap_chip_id omap_chip;
8644 +};
8645 +
8646 +int omap_hwmod_init(struct omap_hwmod **ohs);
8647 +int omap_hwmod_register(struct omap_hwmod *oh);
8648 +int omap_hwmod_unregister(struct omap_hwmod *oh);
8649 +struct omap_hwmod *omap_hwmod_lookup(const char *name);
8650 +int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh));
8651 +int omap_hwmod_late_init(void);
8652 +
8653 +int omap_hwmod_enable(struct omap_hwmod *oh);
8654 +int omap_hwmod_idle(struct omap_hwmod *oh);
8655 +int omap_hwmod_shutdown(struct omap_hwmod *oh);
8656 +
8657 +int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
8658 +int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
8659 +
8660 +int omap_hwmod_reset(struct omap_hwmod *oh);
8661 +void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
8662 +
8663 +void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs);
8664 +u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs);
8665 +
8666 +int omap_hwmod_count_resources(struct omap_hwmod *oh);
8667 +int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
8668 +
8669 +struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
8670 +
8671 +int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
8672 + struct omap_hwmod *init_oh);
8673 +int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
8674 + struct omap_hwmod *init_oh);
8675 +
8676 +int omap_hwmod_set_clockact_both(struct omap_hwmod *oh);
8677 +int omap_hwmod_set_clockact_main(struct omap_hwmod *oh);
8678 +int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh);
8679 +int omap_hwmod_set_clockact_none(struct omap_hwmod *oh);
8680 +
8681 +int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
8682 +int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
8683 +
8684 +#endif
8685 --- /dev/null
8686 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/omap-pm.h
8687 @@ -0,0 +1,301 @@
8688 +/*
8689 + * omap-pm.h - OMAP power management interface
8690 + *
8691 + * Copyright (C) 2008-2009 Texas Instruments, Inc.
8692 + * Copyright (C) 2008-2009 Nokia Corporation
8693 + * Paul Walmsley
8694 + *
8695 + * Interface developed by (in alphabetical order): Karthik Dasu, Jouni
8696 + * Högander, Tony Lindgren, Rajendra Nayak, Sakari Poussa,
8697 + * Veeramanikandan Raju, Anand Sawant, Igor Stoppa, Paul Walmsley,
8698 + * Richard Woodruff
8699 + */
8700 +
8701 +#ifndef ASM_ARM_ARCH_OMAP_OMAP_PM_H
8702 +#define ASM_ARM_ARCH_OMAP_OMAP_PM_H
8703 +
8704 +#include <linux/device.h>
8705 +#include <linux/cpufreq.h>
8706 +
8707 +#include "powerdomain.h"
8708 +
8709 +/**
8710 + * struct omap_opp - clock frequency-to-OPP ID table for DSP, MPU
8711 + * @rate: target clock rate
8712 + * @opp_id: OPP ID
8713 + * @min_vdd: minimum VDD1 voltage (in millivolts) for this OPP
8714 + *
8715 + * Operating performance point data. Can vary by OMAP chip and board.
8716 + */
8717 +struct omap_opp {
8718 + unsigned long rate;
8719 + u8 opp_id;
8720 + u16 min_vdd;
8721 +};
8722 +
8723 +extern struct omap_opp *mpu_opps;
8724 +extern struct omap_opp *dsp_opps;
8725 +extern struct omap_opp *l3_opps;
8726 +
8727 +/*
8728 + * agent_id values for use with omap_pm_set_min_bus_tput():
8729 + *
8730 + * OCP_INITIATOR_AGENT is only valid for devices that can act as
8731 + * initiators -- it represents the device's L3 interconnect
8732 + * connection. OCP_TARGET_AGENT represents the device's L4
8733 + * interconnect connection.
8734 + */
8735 +#define OCP_TARGET_AGENT 1
8736 +#define OCP_INITIATOR_AGENT 2
8737 +
8738 +/**
8739 + * omap_pm_if_early_init - OMAP PM init code called before clock fw init
8740 + * @mpu_opp_table: array ptr to struct omap_opp for MPU
8741 + * @dsp_opp_table: array ptr to struct omap_opp for DSP
8742 + * @l3_opp_table : array ptr to struct omap_opp for CORE
8743 + *
8744 + * Initialize anything that must be configured before the clock
8745 + * framework starts. The "_if_" is to avoid name collisions with the
8746 + * PM idle-loop code.
8747 + */
8748 +int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
8749 + struct omap_opp *dsp_opp_table,
8750 + struct omap_opp *l3_opp_table);
8751 +
8752 +/**
8753 + * omap_pm_if_init - OMAP PM init code called after clock fw init
8754 + *
8755 + * The main initialization code. OPP tables are passed in here. The
8756 + * "_if_" is to avoid name collisions with the PM idle-loop code.
8757 + */
8758 +int __init omap_pm_if_init(void);
8759 +
8760 +/**
8761 + * omap_pm_if_exit - OMAP PM exit code
8762 + *
8763 + * Exit code; currently unused. The "_if_" is to avoid name
8764 + * collisions with the PM idle-loop code.
8765 + */
8766 +void omap_pm_if_exit(void);
8767 +
8768 +/*
8769 + * Device-driver-originated constraints (via board-*.c files, platform_data)
8770 + */
8771 +
8772 +
8773 +/**
8774 + * omap_pm_set_max_mpu_wakeup_lat - set the maximum MPU wakeup latency
8775 + * @dev: struct device * requesting the constraint
8776 + * @t: maximum MPU wakeup latency in microseconds
8777 + *
8778 + * Request that the maximum interrupt latency for the MPU to be no
8779 + * greater than 't' microseconds. "Interrupt latency" in this case is
8780 + * defined as the elapsed time from the occurrence of a hardware or
8781 + * timer interrupt to the time when the device driver's interrupt
8782 + * service routine has been entered by the MPU.
8783 + *
8784 + * It is intended that underlying PM code will use this information to
8785 + * determine what power state to put the MPU powerdomain into, and
8786 + * possibly the CORE powerdomain as well, since interrupt handling
8787 + * code currently runs from SDRAM. Advanced PM or board*.c code may
8788 + * also configure interrupt controller priorities, OCP bus priorities,
8789 + * CPU speed(s), etc.
8790 + *
8791 + * This function will not affect device wakeup latency, e.g., time
8792 + * elapsed from when a device driver enables a hardware device with
8793 + * clk_enable(), to when the device is ready for register access or
8794 + * other use. To control this device wakeup latency, use
8795 + * set_max_dev_wakeup_lat()
8796 + *
8797 + * Multiple calls to set_max_mpu_wakeup_lat() will replace the
8798 + * previous t value. To remove the latency target for the MPU, call
8799 + * with t = -1.
8800 + *
8801 + * No return value.
8802 + */
8803 +void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
8804 +
8805 +
8806 +/**
8807 + * omap_pm_set_min_bus_tput - set minimum bus throughput needed by device
8808 + * @dev: struct device * requesting the constraint
8809 + * @tbus_id: interconnect to operate on (OCP_{INITIATOR,TARGET}_AGENT)
8810 + * @r: minimum throughput (in KiB/s)
8811 + *
8812 + * Request that the minimum data throughput on the OCP interconnect
8813 + * attached to device 'dev' interconnect agent 'tbus_id' be no less
8814 + * than 'r' KiB/s.
8815 + *
8816 + * It is expected that the OMAP PM or bus code will use this
8817 + * information to set the interconnect clock to run at the lowest
8818 + * possible speed that satisfies all current system users. The PM or
8819 + * bus code will adjust the estimate based on its model of the bus, so
8820 + * device driver authors should attempt to specify an accurate
8821 + * quantity for their device use case, and let the PM or bus code
8822 + * overestimate the numbers as necessary to handle request/response
8823 + * latency, other competing users on the system, etc. On OMAP2/3, if
8824 + * a driver requests a minimum L4 interconnect speed constraint, the
8825 + * code will also need to add an minimum L3 interconnect speed
8826 + * constraint,
8827 + *
8828 + * Multiple calls to set_min_bus_tput() will replace the previous rate
8829 + * value for this device. To remove the interconnect throughput
8830 + * restriction for this device, call with r = 0.
8831 + *
8832 + * No return value.
8833 + */
8834 +void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r);
8835 +
8836 +
8837 +/**
8838 + * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency
8839 + * @dev: struct device *
8840 + * @t: maximum device wakeup latency in microseconds
8841 + *
8842 + * Request that the maximum amount of time necessary for a device to
8843 + * become accessible after its clocks are enabled should be no greater
8844 + * than 't' microseconds. Specifically, this represents the time from
8845 + * when a device driver enables device clocks with clk_enable(), to
8846 + * when the register reads and writes on the device will succeed.
8847 + * This function should be called before clk_disable() is called,
8848 + * since the power state transition decision may be made during
8849 + * clk_disable().
8850 + *
8851 + * It is intended that underlying PM code will use this information to
8852 + * determine what power state to put the powerdomain enclosing this
8853 + * device into.
8854 + *
8855 + * Multiple calls to set_max_dev_wakeup_lat() will replace the
8856 + * previous wakeup latency values for this device. To remove the wakeup
8857 + * latency restriction for this device, call with t = -1.
8858 + *
8859 + * No return value.
8860 + */
8861 +void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t);
8862 +
8863 +
8864 +/**
8865 + * omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency
8866 + * @dev: struct device *
8867 + * @t: maximum DMA transfer start latency in microseconds
8868 + *
8869 + * Request that the maximum system DMA transfer start latency for this
8870 + * device 'dev' should be no greater than 't' microseconds. "DMA
8871 + * transfer start latency" here is defined as the elapsed time from
8872 + * when a device (e.g., McBSP) requests that a system DMA transfer
8873 + * start or continue, to the time at which data starts to flow into
8874 + * that device from the system DMA controller.
8875 + *
8876 + * It is intended that underlying PM code will use this information to
8877 + * determine what power state to put the CORE powerdomain into.
8878 + *
8879 + * Since system DMA transfers may not involve the MPU, this function
8880 + * will not affect MPU wakeup latency. Use set_max_cpu_lat() to do
8881 + * so. Similarly, this function will not affect device wakeup latency
8882 + * -- use set_max_dev_wakeup_lat() to affect that.
8883 + *
8884 + * Multiple calls to set_max_sdma_lat() will replace the previous t
8885 + * value for this device. To remove the maximum DMA latency for this
8886 + * device, call with t = -1.
8887 + *
8888 + * No return value.
8889 + */
8890 +void omap_pm_set_max_sdma_lat(struct device *dev, long t);
8891 +
8892 +
8893 +/*
8894 + * DSP Bridge-specific constraints
8895 + */
8896 +
8897 +/**
8898 + * omap_pm_dsp_get_opp_table - get OPP->DSP clock frequency table
8899 + *
8900 + * Intended for use by DSPBridge. Returns an array of OPP->DSP clock
8901 + * frequency entries. The final item in the array should have .rate =
8902 + * .opp_id = 0.
8903 + */
8904 +const struct omap_opp *omap_pm_dsp_get_opp_table(void);
8905 +
8906 +/**
8907 + * omap_pm_dsp_set_min_opp - receive desired OPP target ID from DSP Bridge
8908 + * @opp_id: target DSP OPP ID
8909 + *
8910 + * Set a minimum OPP ID for the DSP. This is intended to be called
8911 + * only from the DSP Bridge MPU-side driver. Unfortunately, the only
8912 + * information that code receives from the DSP/BIOS load estimator is the
8913 + * target OPP ID; hence, this interface. No return value.
8914 + */
8915 +void omap_pm_dsp_set_min_opp(u8 opp_id);
8916 +
8917 +/**
8918 + * omap_pm_dsp_get_opp - report the current DSP OPP ID
8919 + *
8920 + * Report the current OPP for the DSP. Since on OMAP3, the DSP and
8921 + * MPU share a single voltage domain, the OPP ID returned back may
8922 + * represent a higher DSP speed than the OPP requested via
8923 + * omap_pm_dsp_set_min_opp().
8924 + *
8925 + * Returns the current VDD1 OPP ID, or 0 upon error.
8926 + */
8927 +u8 omap_pm_dsp_get_opp(void);
8928 +
8929 +
8930 +/*
8931 + * CPUFreq-originated constraint
8932 + *
8933 + * In the future, this should be handled by custom OPP clocktype
8934 + * functions.
8935 + */
8936 +
8937 +/**
8938 + * omap_pm_cpu_get_freq_table - return a cpufreq_frequency_table array ptr
8939 + *
8940 + * Provide a frequency table usable by CPUFreq for the current chip/board.
8941 + * Returns a pointer to a struct cpufreq_frequency_table array or NULL
8942 + * upon error.
8943 + */
8944 +struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void);
8945 +
8946 +/**
8947 + * omap_pm_cpu_set_freq - set the current minimum MPU frequency
8948 + * @f: MPU frequency in Hz
8949 + *
8950 + * Set the current minimum CPU frequency. The actual CPU frequency
8951 + * used could end up higher if the DSP requested a higher OPP.
8952 + * Intended to be called by plat-omap/cpu_omap.c:omap_target(). No
8953 + * return value.
8954 + */
8955 +void omap_pm_cpu_set_freq(unsigned long f);
8956 +
8957 +/**
8958 + * omap_pm_cpu_get_freq - report the current CPU frequency
8959 + *
8960 + * Returns the current MPU frequency, or 0 upon error.
8961 + */
8962 +unsigned long omap_pm_cpu_get_freq(void);
8963 +
8964 +
8965 +/*
8966 + * Device context loss tracking
8967 + */
8968 +
8969 +/**
8970 + * omap_pm_get_dev_context_loss_count - return count of times dev has lost ctx
8971 + * @dev: struct device *
8972 + *
8973 + * This function returns the number of times that the device @dev has
8974 + * lost its internal context. This generally occurs on a powerdomain
8975 + * transition to OFF. Drivers use this as an optimization to avoid restoring
8976 + * context if the device hasn't lost it. To use, drivers should initially
8977 + * call this in their context save functions and store the result. Early in
8978 + * the driver's context restore function, the driver should call this function
8979 + * again, and compare the result to the stored counter. If they differ, the
8980 + * driver must restore device context. If the number of context losses
8981 + * exceeds the maximum positive integer, the function will wrap to 0 and
8982 + * continue counting. Returns the number of context losses for this device,
8983 + * or -EINVAL upon error.
8984 + */
8985 +int omap_pm_get_dev_context_loss_count(struct device *dev);
8986 +
8987 +
8988 +#endif
8989 --- /dev/null
8990 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/onenand.h
8991 @@ -0,0 +1,43 @@
8992 +/*
8993 + * arch/arm/plat-omap/include/mach/onenand.h
8994 + *
8995 + * Copyright (C) 2006 Nokia Corporation
8996 + * Author: Juha Yrjola
8997 + *
8998 + * This program is free software; you can redistribute it and/or modify
8999 + * it under the terms of the GNU General Public License version 2 as
9000 + * published by the Free Software Foundation.
9001 + */
9002 +
9003 +#include <linux/mtd/mtd.h>
9004 +#include <linux/mtd/partitions.h>
9005 +
9006 +#define ONENAND_SYNC_READ (1 << 0)
9007 +#define ONENAND_SYNC_READWRITE (1 << 1)
9008 +
9009 +struct omap_onenand_platform_data {
9010 + int cs;
9011 + int gpio_irq;
9012 + struct mtd_partition *parts;
9013 + int nr_parts;
9014 + int (*onenand_setup)(void __iomem *, int freq);
9015 + int dma_channel;
9016 + u8 flags;
9017 +};
9018 +
9019 +#define ONENAND_MAX_PARTITIONS 8
9020 +
9021 +#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
9022 + defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
9023 +
9024 +extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
9025 +
9026 +#else
9027 +
9028 +#define board_onenand_data NULL
9029 +
9030 +static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
9031 +{
9032 +}
9033 +
9034 +#endif
9035 --- /dev/null
9036 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/param.h
9037 @@ -0,0 +1,8 @@
9038 +/*
9039 + * arch/arm/plat-omap/include/mach/param.h
9040 + *
9041 + */
9042 +
9043 +#ifdef CONFIG_OMAP_32K_TIMER_HZ
9044 +#define HZ CONFIG_OMAP_32K_TIMER_HZ
9045 +#endif
9046 --- /dev/null
9047 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/powerdomain.h
9048 @@ -0,0 +1,187 @@
9049 +/*
9050 + * OMAP2/3 powerdomain control
9051 + *
9052 + * Copyright (C) 2007-8 Texas Instruments, Inc.
9053 + * Copyright (C) 2007-8 Nokia Corporation
9054 + *
9055 + * Written by Paul Walmsley
9056 + *
9057 + * This program is free software; you can redistribute it and/or modify
9058 + * it under the terms of the GNU General Public License version 2 as
9059 + * published by the Free Software Foundation.
9060 + */
9061 +
9062 +#ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
9063 +#define ASM_ARM_ARCH_OMAP_POWERDOMAIN
9064 +
9065 +#include <linux/types.h>
9066 +#include <linux/list.h>
9067 +
9068 +#include <asm/atomic.h>
9069 +
9070 +#include <plat/cpu.h>
9071 +
9072 +
9073 +/* Powerdomain basic power states */
9074 +#define PWRDM_POWER_OFF 0x0
9075 +#define PWRDM_POWER_RET 0x1
9076 +#define PWRDM_POWER_INACTIVE 0x2
9077 +#define PWRDM_POWER_ON 0x3
9078 +
9079 +#define PWRDM_MAX_PWRSTS 4
9080 +
9081 +/* Powerdomain allowable state bitfields */
9082 +#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
9083 + (1 << PWRDM_POWER_ON))
9084 +
9085 +#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
9086 + (1 << PWRDM_POWER_RET))
9087 +
9088 +#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
9089 +
9090 +
9091 +/* Powerdomain flags */
9092 +#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
9093 +#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
9094 + * in MEM bank 1 position. This is
9095 + * true for OMAP3430
9096 + */
9097 +
9098 +/*
9099 + * Number of memory banks that are power-controllable. On OMAP3430, the
9100 + * maximum is 4.
9101 + */
9102 +#define PWRDM_MAX_MEM_BANKS 4
9103 +
9104 +/*
9105 + * Maximum number of clockdomains that can be associated with a powerdomain.
9106 + * CORE powerdomain on OMAP3 is the worst case
9107 + */
9108 +#define PWRDM_MAX_CLKDMS 4
9109 +
9110 +/* XXX A completely arbitrary number. What is reasonable here? */
9111 +#define PWRDM_TRANSITION_BAILOUT 100000
9112 +
9113 +struct clockdomain;
9114 +struct powerdomain;
9115 +
9116 +/* Encodes dependencies between powerdomains - statically defined */
9117 +struct pwrdm_dep {
9118 +
9119 + /* Powerdomain name */
9120 + const char *pwrdm_name;
9121 +
9122 + /* Powerdomain pointer - resolved by the powerdomain code */
9123 + struct powerdomain *pwrdm;
9124 +
9125 + /* Flags to mark OMAP chip restrictions, etc. */
9126 + const struct omap_chip_id omap_chip;
9127 +
9128 +};
9129 +
9130 +struct powerdomain {
9131 +
9132 + /* Powerdomain name */
9133 + const char *name;
9134 +
9135 + /* the address offset from CM_BASE/PRM_BASE */
9136 + const s16 prcm_offs;
9137 +
9138 + /* Used to represent the OMAP chip types containing this pwrdm */
9139 + const struct omap_chip_id omap_chip;
9140 +
9141 + /* Powerdomains that can be told to wake this powerdomain up */
9142 + struct pwrdm_dep *wkdep_srcs;
9143 +
9144 + /* Powerdomains that can be told to keep this pwrdm from inactivity */
9145 + struct pwrdm_dep *sleepdep_srcs;
9146 +
9147 + /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
9148 + const u8 dep_bit;
9149 +
9150 + /* Possible powerdomain power states */
9151 + const u8 pwrsts;
9152 +
9153 + /* Possible logic power states when pwrdm in RETENTION */
9154 + const u8 pwrsts_logic_ret;
9155 +
9156 + /* Powerdomain flags */
9157 + const u8 flags;
9158 +
9159 + /* Number of software-controllable memory banks in this powerdomain */
9160 + const u8 banks;
9161 +
9162 + /* Possible memory bank pwrstates when pwrdm in RETENTION */
9163 + const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
9164 +
9165 + /* Possible memory bank pwrstates when pwrdm is ON */
9166 + const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
9167 +
9168 + /* Clockdomains in this powerdomain */
9169 + struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
9170 +
9171 + struct list_head node;
9172 +
9173 + int state;
9174 + unsigned state_counter[PWRDM_MAX_PWRSTS];
9175 +
9176 +#ifdef CONFIG_PM_DEBUG
9177 + s64 timer;
9178 + s64 state_timer[PWRDM_MAX_PWRSTS];
9179 +#endif
9180 +};
9181 +
9182 +
9183 +void pwrdm_init(struct powerdomain **pwrdm_list);
9184 +
9185 +int pwrdm_register(struct powerdomain *pwrdm);
9186 +int pwrdm_unregister(struct powerdomain *pwrdm);
9187 +struct powerdomain *pwrdm_lookup(const char *name);
9188 +
9189 +int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
9190 + void *user);
9191 +int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
9192 + void *user);
9193 +
9194 +int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
9195 +int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
9196 +int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
9197 + int (*fn)(struct powerdomain *pwrdm,
9198 + struct clockdomain *clkdm));
9199 +
9200 +int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9201 +int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9202 +int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9203 +int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9204 +int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9205 +int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9206 +
9207 +int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
9208 +
9209 +int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
9210 +int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
9211 +int pwrdm_read_pwrst(struct powerdomain *pwrdm);
9212 +int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
9213 +int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
9214 +
9215 +int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
9216 +int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
9217 +int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
9218 +
9219 +int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
9220 +int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
9221 +int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
9222 +int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
9223 +
9224 +int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
9225 +int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
9226 +bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
9227 +
9228 +int pwrdm_wait_transition(struct powerdomain *pwrdm);
9229 +
9230 +int pwrdm_state_switch(struct powerdomain *pwrdm);
9231 +int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
9232 +int pwrdm_pre_transition(void);
9233 +int pwrdm_post_transition(void);
9234 +
9235 +#endif
9236 --- /dev/null
9237 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/prcm.h
9238 @@ -0,0 +1,39 @@
9239 +/*
9240 + * arch/arm/plat-omap/include/mach/prcm.h
9241 + *
9242 + * Access definations for use in OMAP24XX clock and power management
9243 + *
9244 + * Copyright (C) 2005 Texas Instruments, Inc.
9245 + *
9246 + * This program is free software; you can redistribute it and/or modify
9247 + * it under the terms of the GNU General Public License as published by
9248 + * the Free Software Foundation; either version 2 of the License, or
9249 + * (at your option) any later version.
9250 + *
9251 + * This program is distributed in the hope that it will be useful,
9252 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9253 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9254 + * GNU General Public License for more details.
9255 + *
9256 + * You should have received a copy of the GNU General Public License
9257 + * along with this program; if not, write to the Free Software
9258 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
9259 + */
9260 +
9261 +#ifndef __ASM_ARM_ARCH_OMAP_PRCM_H
9262 +#define __ASM_ARM_ARCH_OMAP_PRCM_H
9263 +
9264 +u32 omap_prcm_get_reset_sources(void);
9265 +void omap_prcm_arch_reset(char mode);
9266 +int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
9267 +
9268 +#define START_PADCONF_SAVE 0x2
9269 +#define PADCONF_SAVE_DONE 0x1
9270 +
9271 +void omap3_prcm_save_context(void);
9272 +void omap3_prcm_restore_context(void);
9273 +
9274 +#endif
9275 +
9276 +
9277 +
9278 --- /dev/null
9279 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/sdrc.h
9280 @@ -0,0 +1,158 @@
9281 +#ifndef ____ASM_ARCH_SDRC_H
9282 +#define ____ASM_ARCH_SDRC_H
9283 +
9284 +/*
9285 + * OMAP2/3 SDRC/SMS register definitions
9286 + *
9287 + * Copyright (C) 2007-2008 Texas Instruments, Inc.
9288 + * Copyright (C) 2007-2008 Nokia Corporation
9289 + *
9290 + * Tony Lindgren
9291 + * Paul Walmsley
9292 + * Richard Woodruff
9293 + *
9294 + * This program is free software; you can redistribute it and/or modify
9295 + * it under the terms of the GNU General Public License version 2 as
9296 + * published by the Free Software Foundation.
9297 + */
9298 +
9299 +#include <mach/io.h>
9300 +
9301 +/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
9302 +
9303 +#define SDRC_SYSCONFIG 0x010
9304 +#define SDRC_CS_CFG 0x040
9305 +#define SDRC_SHARING 0x044
9306 +#define SDRC_ERR_TYPE 0x04C
9307 +#define SDRC_DLLA_CTRL 0x060
9308 +#define SDRC_DLLA_STATUS 0x064
9309 +#define SDRC_DLLB_CTRL 0x068
9310 +#define SDRC_DLLB_STATUS 0x06C
9311 +#define SDRC_POWER 0x070
9312 +#define SDRC_MCFG_0 0x080
9313 +#define SDRC_MR_0 0x084
9314 +#define SDRC_EMR2_0 0x08c
9315 +#define SDRC_ACTIM_CTRL_A_0 0x09c
9316 +#define SDRC_ACTIM_CTRL_B_0 0x0a0
9317 +#define SDRC_RFR_CTRL_0 0x0a4
9318 +#define SDRC_MANUAL_0 0x0a8
9319 +#define SDRC_MCFG_1 0x0B0
9320 +#define SDRC_MR_1 0x0B4
9321 +#define SDRC_EMR2_1 0x0BC
9322 +#define SDRC_ACTIM_CTRL_A_1 0x0C4
9323 +#define SDRC_ACTIM_CTRL_B_1 0x0C8
9324 +#define SDRC_RFR_CTRL_1 0x0D4
9325 +#define SDRC_MANUAL_1 0x0D8
9326 +
9327 +#define SDRC_POWER_AUTOCOUNT_SHIFT 8
9328 +#define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
9329 +#define SDRC_POWER_CLKCTRL_SHIFT 4
9330 +#define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
9331 +#define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
9332 +
9333 +/*
9334 + * These values represent the number of memory clock cycles between
9335 + * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
9336 + * rows per device, and include a subtraction of a 50 cycle window in the
9337 + * event that the autorefresh command is delayed due to other SDRC activity.
9338 + * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
9339 + * counter reaches 0.
9340 + *
9341 + * These represent optimal values for common parts, it won't work for all.
9342 + * As long as you scale down, most parameters are still work, they just
9343 + * become sub-optimal. The RFR value goes in the opposite direction. If you
9344 + * don't adjust it down as your clock period increases the refresh interval
9345 + * will not be met. Setting all parameters for complete worst case may work,
9346 + * but may cut memory performance by 2x. Due to errata the DLLs need to be
9347 + * unlocked and their value needs run time calibration. A dynamic call is
9348 + * need for that as no single right value exists acorss production samples.
9349 + *
9350 + * Only the FULL speed values are given. Current code is such that rate
9351 + * changes must be made at DPLLoutx2. The actual value adjustment for low
9352 + * frequency operation will be handled by omap_set_performance()
9353 + *
9354 + * By having the boot loader boot up in the fastest L4 speed available likely
9355 + * will result in something which you can switch between.
9356 + */
9357 +#define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
9358 +#define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
9359 +#define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
9360 +#define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
9361 +#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
9362 +
9363 +
9364 +/*
9365 + * SMS register access
9366 + */
9367 +
9368 +#define OMAP242X_SMS_REGADDR(reg) \
9369 + (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
9370 +#define OMAP243X_SMS_REGADDR(reg) \
9371 + (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
9372 +#define OMAP343X_SMS_REGADDR(reg) \
9373 + (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
9374 +
9375 +/* SMS register offsets - read/write with sms_{read,write}_reg() */
9376 +
9377 +#define SMS_SYSCONFIG 0x010
9378 +#define SMS_ROT_CONTROL(context) (0x180 + 0x10 * context)
9379 +#define SMS_ROT_SIZE(context) (0x184 + 0x10 * context)
9380 +#define SMS_ROT_PHYSICAL_BA(context) (0x188 + 0x10 * context)
9381 +/* REVISIT: fill in other SMS registers here */
9382 +
9383 +
9384 +#ifndef __ASSEMBLER__
9385 +
9386 +/**
9387 + * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
9388 + * @rate: SDRC clock rate (in Hz)
9389 + * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
9390 + * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
9391 + * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
9392 + * @mr: Value to program to SDRC_MR for this rate
9393 + *
9394 + * This structure holds a pre-computed set of register values for the
9395 + * SDRC for a given SDRC clock rate and SDRAM chip. These are
9396 + * intended to be pre-computed and specified in an array in the board-*.c
9397 + * files. The structure is keyed off the 'rate' field.
9398 + */
9399 +struct omap_sdrc_params {
9400 + unsigned long rate;
9401 + u32 actim_ctrla;
9402 + u32 actim_ctrlb;
9403 + u32 rfr_ctrl;
9404 + u32 mr;
9405 +};
9406 +
9407 +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
9408 + struct omap_sdrc_params *sdrc_cs1);
9409 +int omap2_sdrc_get_params(unsigned long r,
9410 + struct omap_sdrc_params **sdrc_cs0,
9411 + struct omap_sdrc_params **sdrc_cs1);
9412 +void omap2_sms_save_context(void);
9413 +void omap2_sms_restore_context(void);
9414 +
9415 +void omap2_sms_write_rot_control(u32 val, unsigned ctx);
9416 +void omap2_sms_write_rot_size(u32 val, unsigned ctx);
9417 +void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx);
9418 +
9419 +#ifdef CONFIG_ARCH_OMAP2
9420 +
9421 +struct memory_timings {
9422 + u32 m_type; /* ddr = 1, sdr = 0 */
9423 + u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
9424 + u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
9425 + u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
9426 + u32 base_cs; /* base chip select to use for calculations */
9427 +};
9428 +
9429 +extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
9430 +
9431 +u32 omap2xxx_sdrc_dll_is_unlocked(void);
9432 +u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
9433 +
9434 +#endif /* CONFIG_ARCH_OMAP2 */
9435 +
9436 +#endif /* __ASSEMBLER__ */
9437 +
9438 +#endif
9439 --- /dev/null
9440 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/serial.h
9441 @@ -0,0 +1,65 @@
9442 +/*
9443 + * arch/arm/plat-omap/include/mach/serial.h
9444 + *
9445 + * Copyright (C) 2009 Texas Instruments
9446 + * Addded OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
9447 + *
9448 + * This program is distributed in the hope that it will be useful,
9449 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9450 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9451 + * GNU General Public License for more details.
9452 + */
9453 +
9454 +#ifndef __ASM_ARCH_SERIAL_H
9455 +#define __ASM_ARCH_SERIAL_H
9456 +
9457 +#include <linux/init.h>
9458 +
9459 +#if defined(CONFIG_ARCH_OMAP1)
9460 +/* OMAP1 serial ports */
9461 +#define OMAP_UART1_BASE 0xfffb0000
9462 +#define OMAP_UART2_BASE 0xfffb0800
9463 +#define OMAP_UART3_BASE 0xfffb9800
9464 +#elif defined(CONFIG_ARCH_OMAP2)
9465 +/* OMAP2 serial ports */
9466 +#define OMAP_UART1_BASE 0x4806a000
9467 +#define OMAP_UART2_BASE 0x4806c000
9468 +#define OMAP_UART3_BASE 0x4806e000
9469 +#elif defined(CONFIG_ARCH_OMAP3)
9470 +/* OMAP3 serial ports */
9471 +#define OMAP_UART1_BASE 0x4806a000
9472 +#define OMAP_UART2_BASE 0x4806c000
9473 +#define OMAP_UART3_BASE 0x49020000
9474 +#elif defined(CONFIG_ARCH_OMAP4)
9475 +/* OMAP4 serial ports */
9476 +#define OMAP_UART1_BASE 0x4806a000
9477 +#define OMAP_UART2_BASE 0x4806c000
9478 +#define OMAP_UART3_BASE 0x48020000
9479 +#define OMAP_UART4_BASE 0x4806e000
9480 +#endif
9481 +
9482 +#define OMAP1510_BASE_BAUD (12000000/16)
9483 +#define OMAP16XX_BASE_BAUD (48000000/16)
9484 +#define OMAP24XX_BASE_BAUD (48000000/16)
9485 +
9486 +#define is_omap_port(pt) ({int __ret = 0; \
9487 + if ((pt)->port.mapbase == OMAP_UART1_BASE || \
9488 + (pt)->port.mapbase == OMAP_UART2_BASE || \
9489 + (pt)->port.mapbase == OMAP_UART3_BASE) \
9490 + __ret = 1; \
9491 + __ret; \
9492 + })
9493 +
9494 +#ifndef __ASSEMBLER__
9495 +extern void __init omap_serial_early_init(void);
9496 +extern void omap_serial_init(void);
9497 +extern void omap_serial_init_port(int port);
9498 +extern int omap_uart_can_sleep(void);
9499 +extern void omap_uart_check_wakeup(void);
9500 +extern void omap_uart_prepare_suspend(void);
9501 +extern void omap_uart_prepare_idle(int num);
9502 +extern void omap_uart_resume_idle(int num);
9503 +extern void omap_uart_enable_irqs(int enable);
9504 +#endif
9505 +
9506 +#endif
9507 --- /dev/null
9508 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/smp.h
9509 @@ -0,0 +1,53 @@
9510 +/*
9511 + * OMAP4 machine specific smp.h
9512 + *
9513 + * Copyright (C) 2009 Texas Instruments, Inc.
9514 + *
9515 + * Author:
9516 + * Santosh Shilimkar <santosh.shilimkar@ti.com>
9517 + *
9518 + * Interface functions needed for the SMP. This file is based on arm
9519 + * realview smp platform.
9520 + * Copyright (c) 2003 ARM Limited.
9521 + *
9522 + * This program is free software; you can redistribute it and/or modify
9523 + * it under the terms of the GNU General Public License version 2 as
9524 + * published by the Free Software Foundation.
9525 + */
9526 +#ifndef OMAP_ARCH_SMP_H
9527 +#define OMAP_ARCH_SMP_H
9528 +
9529 +#include <asm/hardware/gic.h>
9530 +
9531 +/*
9532 + * set_event() is used to wake up secondary core from wfe using sev. ROM
9533 + * code puts the second core into wfe(standby).
9534 + *
9535 + */
9536 +#define set_event() __asm__ __volatile__ ("sev" : : : "memory")
9537 +
9538 +/* Needed for secondary core boot */
9539 +extern void omap_secondary_startup(void);
9540 +extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
9541 +extern void omap_auxcoreboot_addr(u32 cpu_addr);
9542 +
9543 +/*
9544 + * We use Soft IRQ1 as the IPI
9545 + */
9546 +static inline void smp_cross_call(const struct cpumask *mask)
9547 +{
9548 + gic_raise_softirq(mask, 1);
9549 +}
9550 +
9551 +/*
9552 + * Read MPIDR: Multiprocessor affinity register
9553 + */
9554 +#define hard_smp_processor_id() \
9555 + ({ \
9556 + unsigned int cpunum; \
9557 + __asm__("mrc p15, 0, %0, c0, c0, 5" \
9558 + : "=r" (cpunum)); \
9559 + cpunum &= 0x0F; \
9560 + })
9561 +
9562 +#endif
9563 --- /dev/null
9564 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/sram.h
9565 @@ -0,0 +1,78 @@
9566 +/*
9567 + * arch/arm/plat-omap/include/mach/sram.h
9568 + *
9569 + * Interface for functions that need to be run in internal SRAM
9570 + *
9571 + * This program is free software; you can redistribute it and/or modify
9572 + * it under the terms of the GNU General Public License version 2 as
9573 + * published by the Free Software Foundation.
9574 + */
9575 +
9576 +#ifndef __ARCH_ARM_OMAP_SRAM_H
9577 +#define __ARCH_ARM_OMAP_SRAM_H
9578 +
9579 +extern int __init omap_sram_init(void);
9580 +extern void * omap_sram_push(void * start, unsigned long size);
9581 +extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
9582 +
9583 +extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
9584 + u32 base_cs, u32 force_unlock);
9585 +extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
9586 + u32 mem_type);
9587 +extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
9588 +
9589 +extern u32 omap3_configure_core_dpll(
9590 + u32 m2, u32 unlock_dll, u32 f, u32 inc,
9591 + u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
9592 + u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
9593 + u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
9594 + u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
9595 +extern void omap3_sram_restore_context(void);
9596 +
9597 +/* Do not use these */
9598 +extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
9599 +extern unsigned long omap1_sram_reprogram_clock_sz;
9600 +
9601 +extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
9602 +extern unsigned long omap24xx_sram_reprogram_clock_sz;
9603 +
9604 +extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
9605 + u32 base_cs, u32 force_unlock);
9606 +extern unsigned long omap242x_sram_ddr_init_sz;
9607 +
9608 +extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
9609 + int bypass);
9610 +extern unsigned long omap242x_sram_set_prcm_sz;
9611 +
9612 +extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
9613 + u32 mem_type);
9614 +extern unsigned long omap242x_sram_reprogram_sdrc_sz;
9615 +
9616 +
9617 +extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
9618 + u32 base_cs, u32 force_unlock);
9619 +extern unsigned long omap243x_sram_ddr_init_sz;
9620 +
9621 +extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
9622 + int bypass);
9623 +extern unsigned long omap243x_sram_set_prcm_sz;
9624 +
9625 +extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
9626 + u32 mem_type);
9627 +extern unsigned long omap243x_sram_reprogram_sdrc_sz;
9628 +
9629 +extern u32 omap3_sram_configure_core_dpll(
9630 + u32 m2, u32 unlock_dll, u32 f, u32 inc,
9631 + u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
9632 + u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
9633 + u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
9634 + u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
9635 +extern unsigned long omap3_sram_configure_core_dpll_sz;
9636 +
9637 +#ifdef CONFIG_PM
9638 +extern void omap_push_sram_idle(void);
9639 +#else
9640 +static inline void omap_push_sram_idle(void) {}
9641 +#endif /* CONFIG_PM */
9642 +
9643 +#endif
9644 --- /dev/null
9645 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/system.h
9646 @@ -0,0 +1,51 @@
9647 +/*
9648 + * Copied from arch/arm/mach-sa1100/include/mach/system.h
9649 + * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
9650 + */
9651 +#ifndef __ASM_ARCH_SYSTEM_H
9652 +#define __ASM_ARCH_SYSTEM_H
9653 +#include <linux/clk.h>
9654 +
9655 +#include <asm/mach-types.h>
9656 +#include <mach/hardware.h>
9657 +
9658 +#include <plat/prcm.h>
9659 +
9660 +#ifndef CONFIG_MACH_VOICEBLUE
9661 +#define voiceblue_reset() do {} while (0)
9662 +#else
9663 +extern void voiceblue_reset(void);
9664 +#endif
9665 +
9666 +static inline void arch_idle(void)
9667 +{
9668 + cpu_do_idle();
9669 +}
9670 +
9671 +static inline void omap1_arch_reset(char mode)
9672 +{
9673 + /*
9674 + * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
9675 + * "Global Software Reset Affects Traffic Controller Frequency".
9676 + */
9677 + if (cpu_is_omap5912()) {
9678 + omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
9679 + DPLL_CTL);
9680 + omap_writew(0x8, ARM_RSTCT1);
9681 + }
9682 +
9683 + if (machine_is_voiceblue())
9684 + voiceblue_reset();
9685 + else
9686 + omap_writew(1, ARM_RSTCT1);
9687 +}
9688 +
9689 +static inline void arch_reset(char mode, const char *cmd)
9690 +{
9691 + if (!cpu_class_is_omap2())
9692 + omap1_arch_reset(mode);
9693 + else
9694 + omap_prcm_arch_reset(mode);
9695 +}
9696 +
9697 +#endif
9698 --- /dev/null
9699 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/tc.h
9700 @@ -0,0 +1,106 @@
9701 +/*
9702 + * arch/arm/plat-omap/include/mach/tc.h
9703 + *
9704 + * OMAP Traffic Controller
9705 + *
9706 + * Copyright (C) 2004 Nokia Corporation
9707 + * Author: Imre Deak <imre.deak@nokia.com>
9708 + *
9709 + * This program is free software; you can redistribute it and/or modify it
9710 + * under the terms of the GNU General Public License as published by the
9711 + * Free Software Foundation; either version 2 of the License, or (at your
9712 + * option) any later version.
9713 + *
9714 + * This program is distributed in the hope that it will be useful, but
9715 + * WITHOUT ANY WARRANTY; without even the implied warranty of
9716 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
9717 + * General Public License for more details.
9718 + *
9719 + * You should have received a copy of the GNU General Public License along
9720 + * with this program; if not, write to the Free Software Foundation, Inc.,
9721 + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
9722 + */
9723 +
9724 +#ifndef __ASM_ARCH_TC_H
9725 +#define __ASM_ARCH_TC_H
9726 +
9727 +#define TCMIF_BASE 0xfffecc00
9728 +#define OMAP_TC_OCPT1_PRIOR (TCMIF_BASE + 0x00)
9729 +#define OMAP_TC_EMIFS_PRIOR (TCMIF_BASE + 0x04)
9730 +#define OMAP_TC_EMIFF_PRIOR (TCMIF_BASE + 0x08)
9731 +#define EMIFS_CONFIG (TCMIF_BASE + 0x0c)
9732 +#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10)
9733 +#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14)
9734 +#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18)
9735 +#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c)
9736 +#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20)
9737 +#define EMIFF_MRS (TCMIF_BASE + 0x24)
9738 +#define TC_TIMEOUT1 (TCMIF_BASE + 0x28)
9739 +#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c)
9740 +#define TC_TIMEOUT3 (TCMIF_BASE + 0x30)
9741 +#define TC_ENDIANISM (TCMIF_BASE + 0x34)
9742 +#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c)
9743 +#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40)
9744 +#define EMIFS_ACS0 (TCMIF_BASE + 0x50)
9745 +#define EMIFS_ACS1 (TCMIF_BASE + 0x54)
9746 +#define EMIFS_ACS2 (TCMIF_BASE + 0x58)
9747 +#define EMIFS_ACS3 (TCMIF_BASE + 0x5c)
9748 +#define OMAP_TC_OCPT2_PRIOR (TCMIF_BASE + 0xd0)
9749 +
9750 +/* external EMIFS chipselect regions */
9751 +#define OMAP_CS0_PHYS 0x00000000
9752 +#define OMAP_CS0_SIZE SZ_64M
9753 +
9754 +#define OMAP_CS1_PHYS 0x04000000
9755 +#define OMAP_CS1_SIZE SZ_64M
9756 +
9757 +#define OMAP_CS1A_PHYS OMAP_CS1_PHYS
9758 +#define OMAP_CS1A_SIZE SZ_32M
9759 +
9760 +#define OMAP_CS1B_PHYS (OMAP_CS1A_PHYS + OMAP_CS1A_SIZE)
9761 +#define OMAP_CS1B_SIZE SZ_32M
9762 +
9763 +#define OMAP_CS2_PHYS 0x08000000
9764 +#define OMAP_CS2_SIZE SZ_64M
9765 +
9766 +#define OMAP_CS2A_PHYS OMAP_CS2_PHYS
9767 +#define OMAP_CS2A_SIZE SZ_32M
9768 +
9769 +#define OMAP_CS2B_PHYS (OMAP_CS2A_PHYS + OMAP_CS2A_SIZE)
9770 +#define OMAP_CS2B_SIZE SZ_32M
9771 +
9772 +#define OMAP_CS3_PHYS 0x0c000000
9773 +#define OMAP_CS3_SIZE SZ_64M
9774 +
9775 +#ifndef __ASSEMBLER__
9776 +
9777 +/* EMIF Slow Interface Configuration Register */
9778 +#define OMAP_EMIFS_CONFIG_FR (1 << 4)
9779 +#define OMAP_EMIFS_CONFIG_PDE (1 << 3)
9780 +#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2)
9781 +#define OMAP_EMIFS_CONFIG_BM (1 << 1)
9782 +#define OMAP_EMIFS_CONFIG_WP (1 << 0)
9783 +
9784 +#define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n)))
9785 +#define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n)))
9786 +
9787 +/* Almost all documentation for chip and board memory maps assumes
9788 + * BM is clear. Most devel boards have a switch to control booting
9789 + * from NOR flash (using external chipselect 3) rather than mask ROM,
9790 + * which uses BM to interchange the physical CS0 and CS3 addresses.
9791 + */
9792 +static inline u32 omap_cs0_phys(void)
9793 +{
9794 + return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
9795 + ? OMAP_CS3_PHYS : 0;
9796 +}
9797 +
9798 +static inline u32 omap_cs3_phys(void)
9799 +{
9800 + return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
9801 + ? 0 : OMAP_CS3_PHYS;
9802 +}
9803 +
9804 +#endif /* __ASSEMBLER__ */
9805 +
9806 +#endif /* __ASM_ARCH_TC_H */
9807 --- /dev/null
9808 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/timer-gp.h
9809 @@ -0,0 +1,17 @@
9810 +/*
9811 + * OMAP2/3 GPTIMER support.headers
9812 + *
9813 + * Copyright (C) 2009 Nokia Corporation
9814 + *
9815 + * This file is subject to the terms and conditions of the GNU General Public
9816 + * License. See the file "COPYING" in the main directory of this archive
9817 + * for more details.
9818 + */
9819 +
9820 +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
9821 +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
9822 +
9823 +int __init omap2_gp_clockevent_set_gptimer(u8 id);
9824 +
9825 +#endif
9826 +
9827 --- /dev/null
9828 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/timex.h
9829 @@ -0,0 +1,41 @@
9830 +/*
9831 + * arch/arm/plat-omap/include/mach/timex.h
9832 + *
9833 + * Copyright (C) 2000 RidgeRun, Inc.
9834 + * Author: Greg Lonnon <glonnon@ridgerun.com>
9835 + *
9836 + * This program is free software; you can redistribute it and/or modify it
9837 + * under the terms of the GNU General Public License as published by the
9838 + * Free Software Foundation; either version 2 of the License, or (at your
9839 + * option) any later version.
9840 + *
9841 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9842 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9843 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9844 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9845 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9846 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9847 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9848 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9849 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9850 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9851 + *
9852 + * You should have received a copy of the GNU General Public License along
9853 + * with this program; if not, write to the Free Software Foundation, Inc.,
9854 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9855 + */
9856 +
9857 +#if !defined(__ASM_ARCH_OMAP_TIMEX_H)
9858 +#define __ASM_ARCH_OMAP_TIMEX_H
9859 +
9860 +/*
9861 + * OMAP 32KHz timer updates time one jiffie at a time from a secondary timer,
9862 + * and that's why the CLOCK_TICK_RATE is not 32768.
9863 + */
9864 +#ifdef CONFIG_OMAP_32K_TIMER
9865 +#define CLOCK_TICK_RATE (CONFIG_OMAP_32K_TIMER_HZ)
9866 +#else
9867 +#define CLOCK_TICK_RATE (HZ * 100000UL)
9868 +#endif
9869 +
9870 +#endif /* __ASM_ARCH_OMAP_TIMEX_H */
9871 --- /dev/null
9872 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/uncompress.h
9873 @@ -0,0 +1,88 @@
9874 +/*
9875 + * arch/arm/plat-omap/include/mach/uncompress.h
9876 + *
9877 + * Serial port stubs for kernel decompress status messages
9878 + *
9879 + * Initially based on:
9880 + * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
9881 + * Copyright (C) 2000 RidgeRun, Inc.
9882 + * Author: Greg Lonnon <glonnon@ridgerun.com>
9883 + *
9884 + * Rewritten by:
9885 + * Author: <source@mvista.com>
9886 + * 2004 (c) MontaVista Software, Inc.
9887 + *
9888 + * This file is licensed under the terms of the GNU General Public License
9889 + * version 2. This program is licensed "as is" without any warranty of any
9890 + * kind, whether express or implied.
9891 + */
9892 +
9893 +#include <linux/types.h>
9894 +#include <linux/serial_reg.h>
9895 +#include <plat/serial.h>
9896 +
9897 +unsigned int system_rev;
9898 +
9899 +#define UART_OMAP_MDR1 0x08 /* mode definition register */
9900 +#define OMAP_ID_730 0x355F
9901 +#define OMAP_ID_850 0x362C
9902 +#define ID_MASK 0x7fff
9903 +#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
9904 +#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
9905 +
9906 +static void putc(int c)
9907 +{
9908 + volatile u8 * uart = 0;
9909 + int shift = 2;
9910 +
9911 +#ifdef CONFIG_MACH_OMAP_PALMTE
9912 + return;
9913 +#endif
9914 +
9915 +#ifdef CONFIG_ARCH_OMAP
9916 +#ifdef CONFIG_OMAP_LL_DEBUG_UART3
9917 + uart = (volatile u8 *)(OMAP_UART3_BASE);
9918 +#elif defined(CONFIG_OMAP_LL_DEBUG_UART2)
9919 + uart = (volatile u8 *)(OMAP_UART2_BASE);
9920 +#elif defined(CONFIG_OMAP_LL_DEBUG_UART1)
9921 + uart = (volatile u8 *)(OMAP_UART1_BASE);
9922 +#elif defined(CONFIG_OMAP_LL_DEBUG_NONE)
9923 + return;
9924 +#else
9925 + return;
9926 +#endif
9927 +
9928 +#ifdef CONFIG_ARCH_OMAP1
9929 + /* Determine which serial port to use */
9930 + do {
9931 + /* MMU is not on, so cpu_is_omapXXXX() won't work here */
9932 + unsigned int omap_id = omap_get_id();
9933 +
9934 + if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850)
9935 + shift = 0;
9936 +
9937 + if (check_port(uart, shift))
9938 + break;
9939 + /* Silent boot if no serial ports are enabled. */
9940 + return;
9941 + } while (0);
9942 +#endif /* CONFIG_ARCH_OMAP1 */
9943 +#endif
9944 +
9945 + /*
9946 + * Now, xmit each character
9947 + */
9948 + while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
9949 + barrier();
9950 + uart[UART_TX << shift] = c;
9951 +}
9952 +
9953 +static inline void flush(void)
9954 +{
9955 +}
9956 +
9957 +/*
9958 + * nothing to do
9959 + */
9960 +#define arch_decomp_setup()
9961 +#define arch_decomp_wdog()
9962 --- /dev/null
9963 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/usb.h
9964 @@ -0,0 +1,162 @@
9965 +// include/asm-arm/mach-omap/usb.h
9966 +
9967 +#ifndef __ASM_ARCH_OMAP_USB_H
9968 +#define __ASM_ARCH_OMAP_USB_H
9969 +
9970 +#include <plat/board.h>
9971 +
9972 +#define OMAP3_HS_USB_PORTS 3
9973 +enum ehci_hcd_omap_mode {
9974 + EHCI_HCD_OMAP_MODE_UNKNOWN,
9975 + EHCI_HCD_OMAP_MODE_PHY,
9976 + EHCI_HCD_OMAP_MODE_TLL,
9977 +};
9978 +
9979 +struct ehci_hcd_omap_platform_data {
9980 + enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS];
9981 + unsigned phy_reset:1;
9982 +
9983 + /* have to be valid if phy_reset is true and portx is in phy mode */
9984 + int reset_gpio_port[OMAP3_HS_USB_PORTS];
9985 +};
9986 +
9987 +/*-------------------------------------------------------------------------*/
9988 +
9989 +#define OMAP1_OTG_BASE 0xfffb0400
9990 +#define OMAP1_UDC_BASE 0xfffb4000
9991 +#define OMAP1_OHCI_BASE 0xfffba000
9992 +
9993 +#define OMAP2_OHCI_BASE 0x4805e000
9994 +#define OMAP2_UDC_BASE 0x4805e200
9995 +#define OMAP2_OTG_BASE 0x4805e300
9996 +
9997 +#ifdef CONFIG_ARCH_OMAP1
9998 +
9999 +#define OTG_BASE OMAP1_OTG_BASE
10000 +#define UDC_BASE OMAP1_UDC_BASE
10001 +#define OMAP_OHCI_BASE OMAP1_OHCI_BASE
10002 +
10003 +#else
10004 +
10005 +#define OTG_BASE OMAP2_OTG_BASE
10006 +#define UDC_BASE OMAP2_UDC_BASE
10007 +#define OMAP_OHCI_BASE OMAP2_OHCI_BASE
10008 +
10009 +extern void usb_musb_init(void);
10010 +
10011 +extern void usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata);
10012 +
10013 +#endif
10014 +
10015 +void omap_usb_init(struct omap_usb_config *pdata);
10016 +
10017 +/*-------------------------------------------------------------------------*/
10018 +
10019 +/*
10020 + * OTG and transceiver registers, for OMAPs starting with ARM926
10021 + */
10022 +#define OTG_REV (OTG_BASE + 0x00)
10023 +#define OTG_SYSCON_1 (OTG_BASE + 0x04)
10024 +# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
10025 +# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
10026 +# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
10027 +# define OTG_IDLE_EN (1 << 15)
10028 +# define HST_IDLE_EN (1 << 14)
10029 +# define DEV_IDLE_EN (1 << 13)
10030 +# define OTG_RESET_DONE (1 << 2)
10031 +# define OTG_SOFT_RESET (1 << 1)
10032 +#define OTG_SYSCON_2 (OTG_BASE + 0x08)
10033 +# define OTG_EN (1 << 31)
10034 +# define USBX_SYNCHRO (1 << 30)
10035 +# define OTG_MST16 (1 << 29)
10036 +# define SRP_GPDATA (1 << 28)
10037 +# define SRP_GPDVBUS (1 << 27)
10038 +# define SRP_GPUVBUS(w) (((w)>>24)&0x07)
10039 +# define A_WAIT_VRISE(w) (((w)>>20)&0x07)
10040 +# define B_ASE_BRST(w) (((w)>>16)&0x07)
10041 +# define SRP_DPW (1 << 14)
10042 +# define SRP_DATA (1 << 13)
10043 +# define SRP_VBUS (1 << 12)
10044 +# define OTG_PADEN (1 << 10)
10045 +# define HMC_PADEN (1 << 9)
10046 +# define UHOST_EN (1 << 8)
10047 +# define HMC_TLLSPEED (1 << 7)
10048 +# define HMC_TLLATTACH (1 << 6)
10049 +# define OTG_HMC(w) (((w)>>0)&0x3f)
10050 +#define OTG_CTRL (OTG_BASE + 0x0c)
10051 +# define OTG_USB2_EN (1 << 29)
10052 +# define OTG_USB2_DP (1 << 28)
10053 +# define OTG_USB2_DM (1 << 27)
10054 +# define OTG_USB1_EN (1 << 26)
10055 +# define OTG_USB1_DP (1 << 25)
10056 +# define OTG_USB1_DM (1 << 24)
10057 +# define OTG_USB0_EN (1 << 23)
10058 +# define OTG_USB0_DP (1 << 22)
10059 +# define OTG_USB0_DM (1 << 21)
10060 +# define OTG_ASESSVLD (1 << 20)
10061 +# define OTG_BSESSEND (1 << 19)
10062 +# define OTG_BSESSVLD (1 << 18)
10063 +# define OTG_VBUSVLD (1 << 17)
10064 +# define OTG_ID (1 << 16)
10065 +# define OTG_DRIVER_SEL (1 << 15)
10066 +# define OTG_A_SETB_HNPEN (1 << 12)
10067 +# define OTG_A_BUSREQ (1 << 11)
10068 +# define OTG_B_HNPEN (1 << 9)
10069 +# define OTG_B_BUSREQ (1 << 8)
10070 +# define OTG_BUSDROP (1 << 7)
10071 +# define OTG_PULLDOWN (1 << 5)
10072 +# define OTG_PULLUP (1 << 4)
10073 +# define OTG_DRV_VBUS (1 << 3)
10074 +# define OTG_PD_VBUS (1 << 2)
10075 +# define OTG_PU_VBUS (1 << 1)
10076 +# define OTG_PU_ID (1 << 0)
10077 +#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
10078 +# define DRIVER_SWITCH (1 << 15)
10079 +# define A_VBUS_ERR (1 << 13)
10080 +# define A_REQ_TMROUT (1 << 12)
10081 +# define A_SRP_DETECT (1 << 11)
10082 +# define B_HNP_FAIL (1 << 10)
10083 +# define B_SRP_TMROUT (1 << 9)
10084 +# define B_SRP_DONE (1 << 8)
10085 +# define B_SRP_STARTED (1 << 7)
10086 +# define OPRT_CHG (1 << 0)
10087 +#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
10088 + // same bits as in IRQ_EN
10089 +#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
10090 +# define OTGVPD (1 << 14)
10091 +# define OTGVPU (1 << 13)
10092 +# define OTGPUID (1 << 12)
10093 +# define USB2VDR (1 << 10)
10094 +# define USB2PDEN (1 << 9)
10095 +# define USB2PUEN (1 << 8)
10096 +# define USB1VDR (1 << 6)
10097 +# define USB1PDEN (1 << 5)
10098 +# define USB1PUEN (1 << 4)
10099 +# define USB0VDR (1 << 2)
10100 +# define USB0PDEN (1 << 1)
10101 +# define USB0PUEN (1 << 0)
10102 +#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
10103 +#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
10104 +
10105 +/*-------------------------------------------------------------------------*/
10106 +
10107 +/* OMAP1 */
10108 +#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
10109 +# define CONF_USB2_UNI_R (1 << 8)
10110 +# define CONF_USB1_UNI_R (1 << 7)
10111 +# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
10112 +# define CONF_USB0_ISOLATE_R (1 << 3)
10113 +# define CONF_USB_PWRDN_DM_R (1 << 2)
10114 +# define CONF_USB_PWRDN_DP_R (1 << 1)
10115 +
10116 +/* OMAP2 */
10117 +# define USB_UNIDIR 0x0
10118 +# define USB_UNIDIR_TLL 0x1
10119 +# define USB_BIDIR 0x2
10120 +# define USB_BIDIR_TLL 0x3
10121 +# define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2)))
10122 +# define USBT2TLL5PI (1 << 17)
10123 +# define USB0PUENACTLOI (1 << 16)
10124 +# define USBSTANDBYCTRL (1 << 15)
10125 +
10126 +#endif /* __ASM_ARCH_OMAP_USB_H */
10127 --- /dev/null
10128 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/vram.h
10129 @@ -0,0 +1,62 @@
10130 +/*
10131 + * VRAM manager for OMAP
10132 + *
10133 + * Copyright (C) 2009 Nokia Corporation
10134 + * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
10135 + *
10136 + * This program is free software; you can redistribute it and/or modify
10137 + * it under the terms of the GNU General Public License version 2 as
10138 + * published by the Free Software Foundation.
10139 + *
10140 + * This program is distributed in the hope that it will be useful, but
10141 + * WITHOUT ANY WARRANTY; without even the implied warranty of
10142 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
10143 + * General Public License for more details.
10144 + *
10145 + * You should have received a copy of the GNU General Public License along
10146 + * with this program; if not, write to the Free Software Foundation, Inc.,
10147 + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
10148 + */
10149 +
10150 +#ifndef __OMAP_VRAM_H__
10151 +#define __OMAP_VRAM_H__
10152 +
10153 +#include <linux/types.h>
10154 +
10155 +#define OMAP_VRAM_MEMTYPE_SDRAM 0
10156 +#define OMAP_VRAM_MEMTYPE_SRAM 1
10157 +#define OMAP_VRAM_MEMTYPE_MAX 1
10158 +
10159 +extern int omap_vram_add_region(unsigned long paddr, size_t size);
10160 +extern int omap_vram_free(unsigned long paddr, size_t size);
10161 +extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr);
10162 +extern int omap_vram_reserve(unsigned long paddr, size_t size);
10163 +extern void omap_vram_get_info(unsigned long *vram, unsigned long *free_vram,
10164 + unsigned long *largest_free_block);
10165 +
10166 +#ifdef CONFIG_OMAP2_VRAM
10167 +extern void omap_vram_set_sdram_vram(u32 size, u32 start);
10168 +extern void omap_vram_set_sram_vram(u32 size, u32 start);
10169 +
10170 +extern void omap_vram_reserve_sdram(void);
10171 +extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
10172 + unsigned long sram_vstart,
10173 + unsigned long sram_size,
10174 + unsigned long pstart_avail,
10175 + unsigned long size_avail);
10176 +#else
10177 +static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { }
10178 +static inline void omap_vram_set_sram_vram(u32 size, u32 start) { }
10179 +
10180 +static inline void omap_vram_reserve_sdram(void) { }
10181 +static inline unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
10182 + unsigned long sram_vstart,
10183 + unsigned long sram_size,
10184 + unsigned long pstart_avail,
10185 + unsigned long size_avail)
10186 +{
10187 + return 0;
10188 +}
10189 +#endif
10190 +
10191 +#endif
10192 --- /dev/null
10193 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/mach/vrfb.h
10194 @@ -0,0 +1,50 @@
10195 +/*
10196 + * VRFB Rotation Engine
10197 + *
10198 + * Copyright (C) 2009 Nokia Corporation
10199 + * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
10200 + *
10201 + * This program is free software; you can redistribute it and/or modify
10202 + * it under the terms of the GNU General Public License version 2 as
10203 + * published by the Free Software Foundation.
10204 + *
10205 + * This program is distributed in the hope that it will be useful, but
10206 + * WITHOUT ANY WARRANTY; without even the implied warranty of
10207 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
10208 + * General Public License for more details.
10209 + *
10210 + * You should have received a copy of the GNU General Public License along
10211 + * with this program; if not, write to the Free Software Foundation, Inc.,
10212 + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
10213 + */
10214 +
10215 +#ifndef __OMAP_VRFB_H__
10216 +#define __OMAP_VRFB_H__
10217 +
10218 +#define OMAP_VRFB_LINE_LEN 2048
10219 +
10220 +struct vrfb {
10221 + u8 context;
10222 + void __iomem *vaddr[4];
10223 + unsigned long paddr[4];
10224 + u16 xres;
10225 + u16 yres;
10226 + u16 xoffset;
10227 + u16 yoffset;
10228 + u8 bytespp;
10229 + bool yuv_mode;
10230 +};
10231 +
10232 +extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
10233 +extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
10234 +extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
10235 + u8 bytespp);
10236 +extern u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp);
10237 +extern u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp);
10238 +extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
10239 + u16 width, u16 height,
10240 + unsigned bytespp, bool yuv_mode);
10241 +extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot);
10242 +extern void omap_vrfb_restore_context(void);
10243 +
10244 +#endif /* __VRFB_H */
10245 --- /dev/null
10246 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/plat/cbus.h
10247 @@ -0,0 +1,31 @@
10248 +/*
10249 + * cbus.h - CBUS platform_data definition
10250 + *
10251 + * Copyright (C) 2004 - 2009 Nokia Corporation
10252 + *
10253 + * Written by Felipe Balbi <felipe.balbi@nokia.com>
10254 + *
10255 + * This file is subject to the terms and conditions of the GNU General
10256 + * Public License. See the file "COPYING" in the main directory of this
10257 + * archive for more details.
10258 + *
10259 + * This program is distributed in the hope that it will be useful,
10260 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
10261 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10262 + * GNU General Public License for more details.
10263 + *
10264 + * You should have received a copy of the GNU General Public License
10265 + * along with this program; if not, write to the Free Software
10266 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
10267 + */
10268 +
10269 +#ifndef __PLAT_CBUS_H
10270 +#define __PLAT_CBUS_H
10271 +
10272 +struct cbus_host_platform_data {
10273 + int dat_gpio;
10274 + int clk_gpio;
10275 + int sel_gpio;
10276 +};
10277 +
10278 +#endif /* __PLAT_CBUS_H */
10279 --- linux-2.6.36-rc4.orig/arch/arm/plat-omap/Kconfig
10280 +++ linux-2.6.36-rc4/arch/arm/plat-omap/Kconfig
10281 @@ -47,6 +47,38 @@ config OMAP_RESET_CLOCKS
10282 probably do not want this option enabled until your
10283 device drivers work properly.
10284
10285 +config OMAP_BOOT_TAG
10286 + bool "OMAP bootloader information passing"
10287 + depends on ARCH_OMAP
10288 + default n
10289 + help
10290 + Say Y, if you have a bootloader which passes information
10291 + about your board and its peripheral configuration.
10292 +
10293 +config OMAP_BOOT_REASON
10294 + bool "Support for boot reason"
10295 + depends on OMAP_BOOT_TAG
10296 + default n
10297 + help
10298 + Say Y, if you want to have a procfs entry for reading the boot
10299 + reason in user-space.
10300 +
10301 +config OMAP_COMPONENT_VERSION
10302 + bool "Support for component version display"
10303 + depends on OMAP_BOOT_TAG && PROC_FS
10304 + default n
10305 + help
10306 + Say Y, if you want to have a procfs entry for reading component
10307 + versions (supplied by the bootloader) in user-space.
10308 +
10309 +config OMAP_GPIO_SWITCH
10310 + bool "GPIO switch support"
10311 + help
10312 + Say Y, if you want to have support for reporting of GPIO
10313 + switches (e.g. cover switches) via sysfs. Your bootloader has
10314 + to provide information about the switches to the kernel via the
10315 + ATAG_BOARD mechanism if they're not defined by the board config.
10316 +
10317 config OMAP_MUX
10318 bool "OMAP multiplexing support"
10319 depends on ARCH_OMAP
10320 --- linux-2.6.36-rc4.orig/arch/arm/plat-omap/Makefile
10321 +++ linux-2.6.36-rc4/arch/arm/plat-omap/Makefile
10322 @@ -23,6 +23,9 @@ obj-$(CONFIG_OMAP_IOMMU_DEBUG) += iommu-
10323
10324 obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
10325 obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
10326 +obj-$(CONFIG_OMAP_BOOT_REASON) += bootreason.o
10327 +obj-$(CONFIG_OMAP_COMPONENT_VERSION) += component-version.o
10328 +obj-$(CONFIG_OMAP_GPIO_SWITCH) += gpio-switch.o
10329 obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
10330 obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
10331 i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
10332 @@ -31,4 +34,4 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y)
10333 # OMAP mailbox framework
10334 obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o
10335
10336 -obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
10337 \ No newline at end of file
10338 +obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
10339 --- linux-2.6.36-rc4.orig/arch/arm/include/asm/setup.h
10340 +++ linux-2.6.36-rc4/arch/arm/include/asm/setup.h
10341 @@ -136,6 +136,13 @@ struct tag_acorn {
10342 __u8 adfsdrives;
10343 };
10344
10345 +/* TI OMAP specific information */
10346 +#define ATAG_BOARD 0x414f4d50
10347 +
10348 +struct tag_omap {
10349 + u8 data[0];
10350 +};
10351 +
10352 /* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */
10353 #define ATAG_MEMCLK 0x41000402
10354
10355 @@ -162,6 +169,11 @@ struct tag {
10356 struct tag_acorn acorn;
10357
10358 /*
10359 + * OMAP specific
10360 + */
10361 + struct tag_omap omap;
10362 +
10363 + /*
10364 * DC21285 specific
10365 */
10366 struct tag_memclk memclk;
10367 --- /dev/null
10368 +++ linux-2.6.36-rc4/arch/arm/plat-omap/gpio-switch.c
10369 @@ -0,0 +1,554 @@
10370 +/*
10371 + * linux/arch/arm/plat-omap/gpio-switch.c
10372 + *
10373 + * Copyright (C) 2004-2006 Nokia Corporation
10374 + * Written by Juha Yrjölä <juha.yrjola@nokia.com>
10375 + * and Paul Mundt <paul.mundt@nokia.com>
10376 + *
10377 + * This program is free software; you can redistribute it and/or modify
10378 + * it under the terms of the GNU General Public License version 2 as
10379 + * published by the Free Software Foundation.
10380 + */
10381 +
10382 +#include <linux/sched.h>
10383 +#include <linux/init.h>
10384 +#include <linux/list.h>
10385 +#include <linux/irq.h>
10386 +#include <linux/interrupt.h>
10387 +#include <linux/module.h>
10388 +#include <linux/platform_device.h>
10389 +#include <linux/timer.h>
10390 +#include <linux/err.h>
10391 +#include <linux/slab.h>
10392 +#include <linux/gpio.h>
10393 +#include <plat/hardware.h>
10394 +#include <plat/irqs.h>
10395 +#include <plat/mux.h>
10396 +#include <plat/board.h>
10397 +#include <plat/gpio-switch.h>
10398 +
10399 +struct gpio_switch {
10400 + char name[14];
10401 + u16 gpio;
10402 + unsigned flags:4;
10403 + unsigned type:4;
10404 + unsigned state:1;
10405 + unsigned both_edges:1;
10406 +
10407 + u16 debounce_rising;
10408 + u16 debounce_falling;
10409 +
10410 + void (* notify)(void *data, int state);
10411 + void *notify_data;
10412 +
10413 + struct work_struct work;
10414 + struct timer_list timer;
10415 + struct platform_device pdev;
10416 +
10417 + struct list_head node;
10418 +};
10419 +
10420 +static LIST_HEAD(gpio_switches);
10421 +static struct platform_device *gpio_sw_platform_dev;
10422 +static struct platform_driver gpio_sw_driver;
10423 +
10424 +static const struct omap_gpio_switch *board_gpio_sw_table;
10425 +static int board_gpio_sw_count;
10426 +
10427 +static const char *cover_str[2] = { "open", "closed" };
10428 +static const char *connection_str[2] = { "disconnected", "connected" };
10429 +static const char *activity_str[2] = { "inactive", "active" };
10430 +
10431 +/*
10432 + * GPIO switch state default debounce delay in ms
10433 + */
10434 +#define OMAP_GPIO_SW_DEFAULT_DEBOUNCE 10
10435 +
10436 +static const char **get_sw_str(struct gpio_switch *sw)
10437 +{
10438 + switch (sw->type) {
10439 + case OMAP_GPIO_SWITCH_TYPE_COVER:
10440 + return cover_str;
10441 + case OMAP_GPIO_SWITCH_TYPE_CONNECTION:
10442 + return connection_str;
10443 + case OMAP_GPIO_SWITCH_TYPE_ACTIVITY:
10444 + return activity_str;
10445 + default:
10446 + BUG();
10447 + return NULL;
10448 + }
10449 +}
10450 +
10451 +static const char *get_sw_type(struct gpio_switch *sw)
10452 +{
10453 + switch (sw->type) {
10454 + case OMAP_GPIO_SWITCH_TYPE_COVER:
10455 + return "cover";
10456 + case OMAP_GPIO_SWITCH_TYPE_CONNECTION:
10457 + return "connection";
10458 + case OMAP_GPIO_SWITCH_TYPE_ACTIVITY:
10459 + return "activity";
10460 + default:
10461 + BUG();
10462 + return NULL;
10463 + }
10464 +}
10465 +
10466 +static void print_sw_state(struct gpio_switch *sw, int state)
10467 +{
10468 + const char **str;
10469 +
10470 + str = get_sw_str(sw);
10471 + if (str != NULL)
10472 + printk(KERN_INFO "%s (GPIO %d) is now %s\n", sw->name, sw->gpio, str[state]);
10473 +}
10474 +
10475 +static int gpio_sw_get_state(struct gpio_switch *sw)
10476 +{
10477 + int state;
10478 +
10479 + state = gpio_get_value(sw->gpio);
10480 + if (sw->flags & OMAP_GPIO_SWITCH_FLAG_INVERTED)
10481 + state = !state;
10482 +
10483 + return state;
10484 +}
10485 +
10486 +static ssize_t gpio_sw_state_store(struct device *dev,
10487 + struct device_attribute *attr,
10488 + const char *buf,
10489 + size_t count)
10490 +{
10491 + struct gpio_switch *sw = dev_get_drvdata(dev);
10492 + const char **str;
10493 + char state[16];
10494 + int enable;
10495 +
10496 + if (!(sw->flags & OMAP_GPIO_SWITCH_FLAG_OUTPUT))
10497 + return -EPERM;
10498 +
10499 + if (sscanf(buf, "%15s", state) != 1)
10500 + return -EINVAL;
10501 +
10502 + str = get_sw_str(sw);
10503 + if (strcmp(state, str[0]) == 0)
10504 + sw->state = enable = 0;
10505 + else if (strcmp(state, str[1]) == 0)
10506 + sw->state = enable = 1;
10507 + else
10508 + return -EINVAL;
10509 +
10510 + if (sw->flags & OMAP_GPIO_SWITCH_FLAG_INVERTED)
10511 + enable = !enable;
10512 + gpio_set_value(sw->gpio, enable);
10513 +
10514 + return count;
10515 +}
10516 +
10517 +static ssize_t gpio_sw_state_show(struct device *dev,
10518 + struct device_attribute *attr,
10519 + char *buf)
10520 +{
10521 + struct gpio_switch *sw = dev_get_drvdata(dev);
10522 + const char **str;
10523 +
10524 + str = get_sw_str(sw);
10525 + return sprintf(buf, "%s\n", str[sw->state]);
10526 +}
10527 +
10528 +static DEVICE_ATTR(state, S_IRUGO | S_IWUSR, gpio_sw_state_show,
10529 + gpio_sw_state_store);
10530 +
10531 +static ssize_t gpio_sw_type_show(struct device *dev,
10532 + struct device_attribute *attr,
10533 + char *buf)
10534 +{
10535 + struct gpio_switch *sw = dev_get_drvdata(dev);
10536 +
10537 + return sprintf(buf, "%s\n", get_sw_type(sw));
10538 +}
10539 +
10540 +static DEVICE_ATTR(type, S_IRUGO, gpio_sw_type_show, NULL);
10541 +
10542 +static ssize_t gpio_sw_direction_show(struct device *dev,
10543 + struct device_attribute *attr,
10544 + char *buf)
10545 +{
10546 + struct gpio_switch *sw = dev_get_drvdata(dev);
10547 + int is_output;
10548 +
10549 + is_output = sw->flags & OMAP_GPIO_SWITCH_FLAG_OUTPUT;
10550 + return sprintf(buf, "%s\n", is_output ? "output" : "input");
10551 +}
10552 +
10553 +static DEVICE_ATTR(direction, S_IRUGO, gpio_sw_direction_show, NULL);
10554 +
10555 +
10556 +static irqreturn_t gpio_sw_irq_handler(int irq, void *arg)
10557 +{
10558 + struct gpio_switch *sw = arg;
10559 + unsigned long timeout;
10560 + int state;
10561 +
10562 + if (!sw->both_edges) {
10563 + if (gpio_get_value(sw->gpio))
10564 + set_irq_type(OMAP_GPIO_IRQ(sw->gpio), IRQ_TYPE_EDGE_FALLING);
10565 + else
10566 + set_irq_type(OMAP_GPIO_IRQ(sw->gpio), IRQ_TYPE_EDGE_RISING);
10567 + }
10568 +
10569 + state = gpio_sw_get_state(sw);
10570 + if (sw->state == state)
10571 + return IRQ_HANDLED;
10572 +
10573 + if (state)
10574 + timeout = sw->debounce_rising;
10575 + else
10576 + timeout = sw->debounce_falling;
10577 + if (!timeout)
10578 + schedule_work(&sw->work);
10579 + else
10580 + mod_timer(&sw->timer, jiffies + msecs_to_jiffies(timeout));
10581 +
10582 + return IRQ_HANDLED;
10583 +}
10584 +
10585 +static void gpio_sw_timer(unsigned long arg)
10586 +{
10587 + struct gpio_switch *sw = (struct gpio_switch *) arg;
10588 +
10589 + schedule_work(&sw->work);
10590 +}
10591 +
10592 +static void gpio_sw_handler(struct work_struct *work)
10593 +{
10594 + struct gpio_switch *sw = container_of(work, struct gpio_switch, work);
10595 + int state;
10596 +
10597 + state = gpio_sw_get_state(sw);
10598 + if (sw->state == state)
10599 + return;
10600 +
10601 + sw->state = state;
10602 + if (sw->notify != NULL)
10603 + sw->notify(sw->notify_data, state);
10604 + sysfs_notify(&sw->pdev.dev.kobj, NULL, "state");
10605 + print_sw_state(sw, state);
10606 +}
10607 +
10608 +static int __init can_do_both_edges(struct gpio_switch *sw)
10609 +{
10610 + if (!cpu_class_is_omap1())
10611 + return 1;
10612 + if (OMAP_GPIO_IS_MPUIO(sw->gpio))
10613 + return 0;
10614 + else
10615 + return 1;
10616 +}
10617 +
10618 +static void gpio_sw_release(struct device *dev)
10619 +{
10620 +}
10621 +
10622 +static int __init new_switch(struct gpio_switch *sw)
10623 +{
10624 + int r, direction, trigger;
10625 +
10626 + switch (sw->type) {
10627 + case OMAP_GPIO_SWITCH_TYPE_COVER:
10628 + case OMAP_GPIO_SWITCH_TYPE_CONNECTION:
10629 + case OMAP_GPIO_SWITCH_TYPE_ACTIVITY:
10630 + break;
10631 + default:
10632 + printk(KERN_ERR "invalid GPIO switch type: %d\n", sw->type);
10633 + return -EINVAL;
10634 + }
10635 +
10636 + sw->pdev.name = sw->name;
10637 + sw->pdev.id = -1;
10638 +
10639 + sw->pdev.dev.parent = &gpio_sw_platform_dev->dev;
10640 + sw->pdev.dev.driver = &gpio_sw_driver.driver;
10641 + sw->pdev.dev.release = gpio_sw_release;
10642 +
10643 + r = platform_device_register(&sw->pdev);
10644 + if (r) {
10645 + printk(KERN_ERR "gpio-switch: platform device registration "
10646 + "failed for %s", sw->name);
10647 + return r;
10648 + }
10649 + dev_set_drvdata(&sw->pdev.dev, sw);
10650 +
10651 + r = gpio_request(sw->gpio, "gpio-switch");
10652 + if (r < 0) {
10653 + platform_device_unregister(&sw->pdev);
10654 + return r;
10655 + }
10656 +
10657 + /* input: 1, output: 0 */
10658 + direction = !(sw->flags & OMAP_GPIO_SWITCH_FLAG_OUTPUT);
10659 + if (direction)
10660 + gpio_direction_input(sw->gpio);
10661 + else
10662 + gpio_direction_output(sw->gpio, 0);
10663 +
10664 + sw->state = gpio_sw_get_state(sw);
10665 +
10666 + r = 0;
10667 + r |= device_create_file(&sw->pdev.dev, &dev_attr_state);
10668 + r |= device_create_file(&sw->pdev.dev, &dev_attr_type);
10669 + r |= device_create_file(&sw->pdev.dev, &dev_attr_direction);
10670 + if (r)
10671 + printk(KERN_ERR "gpio-switch: attribute file creation "
10672 + "failed for %s\n", sw->name);
10673 +
10674 + if (!direction)
10675 + return 0;
10676 +
10677 + if (can_do_both_edges(sw)) {
10678 + trigger = IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING;
10679 + sw->both_edges = 1;
10680 + } else {
10681 + if (gpio_get_value(sw->gpio))
10682 + trigger = IRQF_TRIGGER_FALLING;
10683 + else
10684 + trigger = IRQF_TRIGGER_RISING;
10685 + }
10686 + r = request_irq(OMAP_GPIO_IRQ(sw->gpio), gpio_sw_irq_handler,
10687 + IRQF_SHARED | trigger, sw->name, sw);
10688 + if (r < 0) {
10689 + printk(KERN_ERR "gpio-switch: request_irq() failed "
10690 + "for GPIO %d\n", sw->gpio);
10691 + platform_device_unregister(&sw->pdev);
10692 + gpio_free(sw->gpio);
10693 + return r;
10694 + }
10695 +
10696 + INIT_WORK(&sw->work, gpio_sw_handler);
10697 + init_timer(&sw->timer);
10698 +
10699 + sw->timer.function = gpio_sw_timer;
10700 + sw->timer.data = (unsigned long)sw;
10701 +
10702 + list_add(&sw->node, &gpio_switches);
10703 +
10704 + return 0;
10705 +}
10706 +
10707 +static int __init add_atag_switches(void)
10708 +{
10709 + const struct omap_gpio_switch_config *cfg;
10710 + struct gpio_switch *sw;
10711 + int i, r;
10712 +
10713 + for (i = 0; ; i++) {
10714 + cfg = omap_get_nr_config(OMAP_TAG_GPIO_SWITCH,
10715 + struct omap_gpio_switch_config, i);
10716 + if (cfg == NULL)
10717 + break;
10718 + sw = kzalloc(sizeof(*sw), GFP_KERNEL);
10719 + if (sw == NULL) {
10720 + printk(KERN_ERR "gpio-switch: kmalloc failed\n");
10721 + return -ENOMEM;
10722 + }
10723 + strncpy(sw->name, cfg->name, sizeof(cfg->name));
10724 + sw->gpio = cfg->gpio;
10725 + sw->flags = cfg->flags;
10726 + sw->type = cfg->type;
10727 + sw->debounce_rising = OMAP_GPIO_SW_DEFAULT_DEBOUNCE;
10728 + sw->debounce_falling = OMAP_GPIO_SW_DEFAULT_DEBOUNCE;
10729 + if ((r = new_switch(sw)) < 0) {
10730 + kfree(sw);
10731 + return r;
10732 + }
10733 + }
10734 + return 0;
10735 +}
10736 +
10737 +static struct gpio_switch * __init find_switch(int gpio, const char *name)
10738 +{
10739 + struct gpio_switch *sw;
10740 +
10741 + list_for_each_entry(sw, &gpio_switches, node) {
10742 + if ((gpio < 0 || sw->gpio != gpio) &&
10743 + (name == NULL || strcmp(sw->name, name) != 0))
10744 + continue;
10745 +
10746 + if (gpio < 0 || name == NULL)
10747 + goto no_check;
10748 +
10749 + if (strcmp(sw->name, name) != 0)
10750 + printk("gpio-switch: name mismatch for %d (%s, %s)\n",
10751 + gpio, name, sw->name);
10752 + else if (sw->gpio != gpio)
10753 + printk("gpio-switch: GPIO mismatch for %s (%d, %d)\n",
10754 + name, gpio, sw->gpio);
10755 +no_check:
10756 + return sw;
10757 + }
10758 + return NULL;
10759 +}
10760 +
10761 +static int __init add_board_switches(void)
10762 +{
10763 + int i;
10764 +
10765 + for (i = 0; i < board_gpio_sw_count; i++) {
10766 + const struct omap_gpio_switch *cfg;
10767 + struct gpio_switch *sw;
10768 + int r;
10769 +
10770 + cfg = board_gpio_sw_table + i;
10771 + if (strlen(cfg->name) > sizeof(sw->name) - 1)
10772 + return -EINVAL;
10773 + /* Check whether we only update an existing switch
10774 + * or add a new switch. */
10775 + sw = find_switch(cfg->gpio, cfg->name);
10776 + if (sw != NULL) {
10777 + sw->debounce_rising = cfg->debounce_rising;
10778 + sw->debounce_falling = cfg->debounce_falling;
10779 + sw->notify = cfg->notify;
10780 + sw->notify_data = cfg->notify_data;
10781 + continue;
10782 + } else {
10783 + if (cfg->gpio < 0 || cfg->name == NULL) {
10784 + printk("gpio-switch: required switch not "
10785 + "found (%d, %s)\n", cfg->gpio,
10786 + cfg->name);
10787 + continue;
10788 + }
10789 + }
10790 + sw = kzalloc(sizeof(*sw), GFP_KERNEL);
10791 + if (sw == NULL) {
10792 + printk(KERN_ERR "gpio-switch: kmalloc failed\n");
10793 + return -ENOMEM;
10794 + }
10795 + strlcpy(sw->name, cfg->name, sizeof(sw->name));
10796 + sw->gpio = cfg->gpio;
10797 + sw->flags = cfg->flags;
10798 + sw->type = cfg->type;
10799 + sw->debounce_rising = cfg->debounce_rising;
10800 + sw->debounce_falling = cfg->debounce_falling;
10801 + sw->notify = cfg->notify;
10802 + sw->notify_data = cfg->notify_data;
10803 + if ((r = new_switch(sw)) < 0) {
10804 + kfree(sw);
10805 + return r;
10806 + }
10807 + }
10808 + return 0;
10809 +}
10810 +
10811 +static void gpio_sw_cleanup(void)
10812 +{
10813 + struct gpio_switch *sw = NULL, *old = NULL;
10814 +
10815 + list_for_each_entry(sw, &gpio_switches, node) {
10816 + if (old != NULL)
10817 + kfree(old);
10818 + flush_scheduled_work();
10819 + del_timer_sync(&sw->timer);
10820 +
10821 + free_irq(OMAP_GPIO_IRQ(sw->gpio), sw);
10822 +
10823 + device_remove_file(&sw->pdev.dev, &dev_attr_state);
10824 + device_remove_file(&sw->pdev.dev, &dev_attr_type);
10825 + device_remove_file(&sw->pdev.dev, &dev_attr_direction);
10826 +
10827 + platform_device_unregister(&sw->pdev);
10828 + gpio_free(sw->gpio);
10829 + old = sw;
10830 + }
10831 + kfree(old);
10832 +}
10833 +
10834 +static void __init report_initial_state(void)
10835 +{
10836 + struct gpio_switch *sw;
10837 +
10838 + list_for_each_entry(sw, &gpio_switches, node) {
10839 + int state;
10840 +
10841 + state = gpio_get_value(sw->gpio);
10842 + if (sw->flags & OMAP_GPIO_SWITCH_FLAG_INVERTED)
10843 + state = !state;
10844 + if (sw->notify != NULL)
10845 + sw->notify(sw->notify_data, state);
10846 + print_sw_state(sw, state);
10847 + }
10848 +}
10849 +
10850 +static int gpio_sw_remove(struct platform_device *dev)
10851 +{
10852 + return 0;
10853 +}
10854 +
10855 +static struct platform_driver gpio_sw_driver = {
10856 + .remove = gpio_sw_remove,
10857 + .driver = {
10858 + .name = "gpio-switch",
10859 + },
10860 +};
10861 +
10862 +void __init omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
10863 + int count)
10864 +{
10865 + BUG_ON(board_gpio_sw_table != NULL);
10866 +
10867 + board_gpio_sw_table = tbl;
10868 + board_gpio_sw_count = count;
10869 +}
10870 +
10871 +static int __init gpio_sw_init(void)
10872 +{
10873 + int r;
10874 +
10875 + printk(KERN_INFO "OMAP GPIO switch handler initializing\n");
10876 +
10877 + r = platform_driver_register(&gpio_sw_driver);
10878 + if (r)
10879 + return r;
10880 +
10881 + gpio_sw_platform_dev = platform_device_register_simple("gpio-switch",
10882 + -1, NULL, 0);
10883 + if (IS_ERR(gpio_sw_platform_dev)) {
10884 + r = PTR_ERR(gpio_sw_platform_dev);
10885 + goto err1;
10886 + }
10887 +
10888 + r = add_atag_switches();
10889 + if (r < 0)
10890 + goto err2;
10891 +
10892 + r = add_board_switches();
10893 + if (r < 0)
10894 + goto err2;
10895 +
10896 + report_initial_state();
10897 +
10898 + return 0;
10899 +err2:
10900 + gpio_sw_cleanup();
10901 + platform_device_unregister(gpio_sw_platform_dev);
10902 +err1:
10903 + platform_driver_unregister(&gpio_sw_driver);
10904 + return r;
10905 +}
10906 +
10907 +static void __exit gpio_sw_exit(void)
10908 +{
10909 + gpio_sw_cleanup();
10910 + platform_device_unregister(gpio_sw_platform_dev);
10911 + platform_driver_unregister(&gpio_sw_driver);
10912 +}
10913 +
10914 +#ifndef MODULE
10915 +late_initcall(gpio_sw_init);
10916 +#else
10917 +module_init(gpio_sw_init);
10918 +#endif
10919 +module_exit(gpio_sw_exit);
10920 +
10921 +MODULE_AUTHOR("Juha Yrjölä <juha.yrjola@nokia.com>, Paul Mundt <paul.mundt@nokia.com");
10922 +MODULE_DESCRIPTION("GPIO switch driver");
10923 +MODULE_LICENSE("GPL");
10924 --- linux-2.6.36-rc4.orig/arch/arm/plat-omap/include/plat/board.h
10925 +++ linux-2.6.36-rc4/arch/arm/plat-omap/include/plat/board.h
10926 @@ -151,6 +151,14 @@ struct omap_board_config_kernel {
10927 const void *data;
10928 };
10929
10930 +struct omap_gpio_switch_config {
10931 + char name[12];
10932 + u16 gpio;
10933 + int flags:4;
10934 + int type:4;
10935 + int key_code:24; /* Linux key code */
10936 +};
10937 +
10938 extern const void *__omap_get_config(u16 tag, size_t len, int nr);
10939
10940 #define omap_get_config(tag, type) \
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