[x86] Allow gzipping of squashfs images with padded jffs2 partition
[openwrt.git] / target / linux / generic / patches-3.2 / 025-bcma_backport.patch
1 --- a/drivers/bcma/host_pci.c
2 +++ b/drivers/bcma/host_pci.c
3 @@ -21,48 +21,58 @@ static void bcma_host_pci_switch_core(st
4 pr_debug("Switched to core: 0x%X\n", core->id.id);
5 }
6
7 -static u8 bcma_host_pci_read8(struct bcma_device *core, u16 offset)
8 +/* Provides access to the requested core. Returns base offset that has to be
9 + * used. It makes use of fixed windows when possible. */
10 +static u16 bcma_host_pci_provide_access_to_core(struct bcma_device *core)
11 {
12 + switch (core->id.id) {
13 + case BCMA_CORE_CHIPCOMMON:
14 + return 3 * BCMA_CORE_SIZE;
15 + case BCMA_CORE_PCIE:
16 + return 2 * BCMA_CORE_SIZE;
17 + }
18 +
19 if (core->bus->mapped_core != core)
20 bcma_host_pci_switch_core(core);
21 + return 0;
22 +}
23 +
24 +static u8 bcma_host_pci_read8(struct bcma_device *core, u16 offset)
25 +{
26 + offset += bcma_host_pci_provide_access_to_core(core);
27 return ioread8(core->bus->mmio + offset);
28 }
29
30 static u16 bcma_host_pci_read16(struct bcma_device *core, u16 offset)
31 {
32 - if (core->bus->mapped_core != core)
33 - bcma_host_pci_switch_core(core);
34 + offset += bcma_host_pci_provide_access_to_core(core);
35 return ioread16(core->bus->mmio + offset);
36 }
37
38 static u32 bcma_host_pci_read32(struct bcma_device *core, u16 offset)
39 {
40 - if (core->bus->mapped_core != core)
41 - bcma_host_pci_switch_core(core);
42 + offset += bcma_host_pci_provide_access_to_core(core);
43 return ioread32(core->bus->mmio + offset);
44 }
45
46 static void bcma_host_pci_write8(struct bcma_device *core, u16 offset,
47 u8 value)
48 {
49 - if (core->bus->mapped_core != core)
50 - bcma_host_pci_switch_core(core);
51 + offset += bcma_host_pci_provide_access_to_core(core);
52 iowrite8(value, core->bus->mmio + offset);
53 }
54
55 static void bcma_host_pci_write16(struct bcma_device *core, u16 offset,
56 u16 value)
57 {
58 - if (core->bus->mapped_core != core)
59 - bcma_host_pci_switch_core(core);
60 + offset += bcma_host_pci_provide_access_to_core(core);
61 iowrite16(value, core->bus->mmio + offset);
62 }
63
64 static void bcma_host_pci_write32(struct bcma_device *core, u16 offset,
65 u32 value)
66 {
67 - if (core->bus->mapped_core != core)
68 - bcma_host_pci_switch_core(core);
69 + offset += bcma_host_pci_provide_access_to_core(core);
70 iowrite32(value, core->bus->mmio + offset);
71 }
72
73 --- a/drivers/bcma/sprom.c
74 +++ b/drivers/bcma/sprom.c
75 @@ -129,6 +129,9 @@ static void bcma_sprom_extract_r8(struct
76 u16 v;
77 int i;
78
79 + bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
80 + SSB_SPROM_REVISION_REV;
81 +
82 for (i = 0; i < 3; i++) {
83 v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
84 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
85 @@ -136,12 +139,70 @@ static void bcma_sprom_extract_r8(struct
86
87 bus->sprom.board_rev = sprom[SPOFF(SSB_SPROM8_BOARDREV)];
88
89 + bus->sprom.txpid2g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
90 + SSB_SPROM4_TXPID2G0) >> SSB_SPROM4_TXPID2G0_SHIFT;
91 + bus->sprom.txpid2g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
92 + SSB_SPROM4_TXPID2G1) >> SSB_SPROM4_TXPID2G1_SHIFT;
93 + bus->sprom.txpid2g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
94 + SSB_SPROM4_TXPID2G2) >> SSB_SPROM4_TXPID2G2_SHIFT;
95 + bus->sprom.txpid2g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
96 + SSB_SPROM4_TXPID2G3) >> SSB_SPROM4_TXPID2G3_SHIFT;
97 +
98 + bus->sprom.txpid5gl[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
99 + SSB_SPROM4_TXPID5GL0) >> SSB_SPROM4_TXPID5GL0_SHIFT;
100 + bus->sprom.txpid5gl[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
101 + SSB_SPROM4_TXPID5GL1) >> SSB_SPROM4_TXPID5GL1_SHIFT;
102 + bus->sprom.txpid5gl[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
103 + SSB_SPROM4_TXPID5GL2) >> SSB_SPROM4_TXPID5GL2_SHIFT;
104 + bus->sprom.txpid5gl[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
105 + SSB_SPROM4_TXPID5GL3) >> SSB_SPROM4_TXPID5GL3_SHIFT;
106 +
107 + bus->sprom.txpid5g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
108 + SSB_SPROM4_TXPID5G0) >> SSB_SPROM4_TXPID5G0_SHIFT;
109 + bus->sprom.txpid5g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
110 + SSB_SPROM4_TXPID5G1) >> SSB_SPROM4_TXPID5G1_SHIFT;
111 + bus->sprom.txpid5g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
112 + SSB_SPROM4_TXPID5G2) >> SSB_SPROM4_TXPID5G2_SHIFT;
113 + bus->sprom.txpid5g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
114 + SSB_SPROM4_TXPID5G3) >> SSB_SPROM4_TXPID5G3_SHIFT;
115 +
116 + bus->sprom.txpid5gh[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
117 + SSB_SPROM4_TXPID5GH0) >> SSB_SPROM4_TXPID5GH0_SHIFT;
118 + bus->sprom.txpid5gh[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
119 + SSB_SPROM4_TXPID5GH1) >> SSB_SPROM4_TXPID5GH1_SHIFT;
120 + bus->sprom.txpid5gh[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
121 + SSB_SPROM4_TXPID5GH2) >> SSB_SPROM4_TXPID5GH2_SHIFT;
122 + bus->sprom.txpid5gh[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
123 + SSB_SPROM4_TXPID5GH3) >> SSB_SPROM4_TXPID5GH3_SHIFT;
124 +
125 bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)];
126 bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)];
127 bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)];
128 bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)];
129
130 bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)];
131 +
132 + bus->sprom.fem.ghz2.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
133 + SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
134 + bus->sprom.fem.ghz2.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
135 + SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
136 + bus->sprom.fem.ghz2.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
137 + SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
138 + bus->sprom.fem.ghz2.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
139 + SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
140 + bus->sprom.fem.ghz2.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
141 + SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
142 +
143 + bus->sprom.fem.ghz5.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
144 + SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
145 + bus->sprom.fem.ghz5.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
146 + SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
147 + bus->sprom.fem.ghz5.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
148 + SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
149 + bus->sprom.fem.ghz5.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
150 + SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
151 + bus->sprom.fem.ghz5.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
152 + SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
153 }
154
155 int bcma_sprom_get(struct bcma_bus *bus)
156 --- a/include/linux/bcma/bcma_driver_chipcommon.h
157 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
158 @@ -203,6 +203,7 @@
159 #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
160 #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
161 #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
162 +#define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
163 #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
164 #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
165 #define BCMA_CC_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
166 --- a/include/linux/bcma/bcma.h
167 +++ b/include/linux/bcma/bcma.h
168 @@ -205,61 +205,82 @@ struct bcma_bus {
169 struct ssb_sprom sprom;
170 };
171
172 -extern inline u32 bcma_read8(struct bcma_device *core, u16 offset)
173 +static inline u32 bcma_read8(struct bcma_device *core, u16 offset)
174 {
175 return core->bus->ops->read8(core, offset);
176 }
177 -extern inline u32 bcma_read16(struct bcma_device *core, u16 offset)
178 +static inline u32 bcma_read16(struct bcma_device *core, u16 offset)
179 {
180 return core->bus->ops->read16(core, offset);
181 }
182 -extern inline u32 bcma_read32(struct bcma_device *core, u16 offset)
183 +static inline u32 bcma_read32(struct bcma_device *core, u16 offset)
184 {
185 return core->bus->ops->read32(core, offset);
186 }
187 -extern inline
188 +static inline
189 void bcma_write8(struct bcma_device *core, u16 offset, u32 value)
190 {
191 core->bus->ops->write8(core, offset, value);
192 }
193 -extern inline
194 +static inline
195 void bcma_write16(struct bcma_device *core, u16 offset, u32 value)
196 {
197 core->bus->ops->write16(core, offset, value);
198 }
199 -extern inline
200 +static inline
201 void bcma_write32(struct bcma_device *core, u16 offset, u32 value)
202 {
203 core->bus->ops->write32(core, offset, value);
204 }
205 #ifdef CONFIG_BCMA_BLOCKIO
206 -extern inline void bcma_block_read(struct bcma_device *core, void *buffer,
207 +static inline void bcma_block_read(struct bcma_device *core, void *buffer,
208 size_t count, u16 offset, u8 reg_width)
209 {
210 core->bus->ops->block_read(core, buffer, count, offset, reg_width);
211 }
212 -extern inline void bcma_block_write(struct bcma_device *core, const void *buffer,
213 - size_t count, u16 offset, u8 reg_width)
214 +static inline void bcma_block_write(struct bcma_device *core,
215 + const void *buffer, size_t count,
216 + u16 offset, u8 reg_width)
217 {
218 core->bus->ops->block_write(core, buffer, count, offset, reg_width);
219 }
220 #endif
221 -extern inline u32 bcma_aread32(struct bcma_device *core, u16 offset)
222 +static inline u32 bcma_aread32(struct bcma_device *core, u16 offset)
223 {
224 return core->bus->ops->aread32(core, offset);
225 }
226 -extern inline
227 +static inline
228 void bcma_awrite32(struct bcma_device *core, u16 offset, u32 value)
229 {
230 core->bus->ops->awrite32(core, offset, value);
231 }
232
233 -#define bcma_mask32(cc, offset, mask) \
234 - bcma_write32(cc, offset, bcma_read32(cc, offset) & (mask))
235 -#define bcma_set32(cc, offset, set) \
236 - bcma_write32(cc, offset, bcma_read32(cc, offset) | (set))
237 -#define bcma_maskset32(cc, offset, mask, set) \
238 - bcma_write32(cc, offset, (bcma_read32(cc, offset) & (mask)) | (set))
239 +static inline void bcma_mask32(struct bcma_device *cc, u16 offset, u32 mask)
240 +{
241 + bcma_write32(cc, offset, bcma_read32(cc, offset) & mask);
242 +}
243 +static inline void bcma_set32(struct bcma_device *cc, u16 offset, u32 set)
244 +{
245 + bcma_write32(cc, offset, bcma_read32(cc, offset) | set);
246 +}
247 +static inline void bcma_maskset32(struct bcma_device *cc,
248 + u16 offset, u32 mask, u32 set)
249 +{
250 + bcma_write32(cc, offset, (bcma_read32(cc, offset) & mask) | set);
251 +}
252 +static inline void bcma_mask16(struct bcma_device *cc, u16 offset, u16 mask)
253 +{
254 + bcma_write16(cc, offset, bcma_read16(cc, offset) & mask);
255 +}
256 +static inline void bcma_set16(struct bcma_device *cc, u16 offset, u16 set)
257 +{
258 + bcma_write16(cc, offset, bcma_read16(cc, offset) | set);
259 +}
260 +static inline void bcma_maskset16(struct bcma_device *cc,
261 + u16 offset, u16 mask, u16 set)
262 +{
263 + bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
264 +}
265
266 extern bool bcma_core_is_enabled(struct bcma_device *core);
267 extern void bcma_core_disable(struct bcma_device *core, u32 flags);
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