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Fix small typo in the ethernet driver
[openwrt.git] / target / linux / rdc / files / drivers / net / r6040.c
1 /*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/version.h>
28 #include <linux/moduleparam.h>
29 #include <linux/string.h>
30 #include <linux/timer.h>
31 #include <linux/errno.h>
32 #include <linux/ioport.h>
33 #include <linux/slab.h>
34 #include <linux/interrupt.h>
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/skbuff.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/mii.h>
42 #include <linux/ethtool.h>
43 #include <linux/crc32.h>
44 #include <linux/spinlock.h>
45 #include <linux/bitops.h>
46 #include <linux/io.h>
47 #include <linux/irq.h>
48 #include <linux/uaccess.h>
49
50 #include <asm/processor.h>
51
52 #define DRV_NAME "r6040"
53 #define DRV_VERSION "0.19"
54 #define DRV_RELDATE "16Jun2008"
55
56 /* define bits of a debug mask */
57 #define DBG_PHY 0x00000001 /*!< show PHY read/write */
58 #define DBG_FREE_BUFS 0x00000002 /*!< show calls to r6040_free_*bufs */
59 #define DBG_RING 0x00000004 /*!< debug init./freeing of descr rings */
60 #define DBG_RX_BUF 0x00000008 /*!< show alloc. of new rx buf (in IRQ context !) */
61 #define DBG_TX_BUF 0x00000010 /*!< show arrival of new tx buf */
62 #define DBG_TX_DONE 0x00000020 /*!< debug TX done */
63 #define DBG_RX_DESCR 0x00000040 /*!< debug rx descr to be processed */
64 #define DBG_RX_DATA 0x00000080 /*!< show some user data of incoming packet */
65 #define DBG_EXIT 0x00000100 /*!< show exit code calls */
66 #define DBG_INIT 0x00000200 /*!< show init. code calls */
67 #define DBG_TX_RING_DUMP 0x00000400 /*!< dump the tx ring after creation */
68 #define DBG_RX_RING_DUMP 0x00000800 /*!< dump the rx ring after creation */
69 #define DBG_TX_DESCR 0x00001000 /*!< dump the setting of a descr for tx */
70 #define DBG_TX_DATA 0x00002000 /*!< dump some tx data */
71 #define DBG_IRQ 0x00004000 /*!< print inside the irq handler */
72 #define DBG_POLL 0x00008000 /*!< dump info on poll procedure */
73 #define DBG_MAC_ADDR 0x00010000 /*!< debug mac address setting */
74 #define DBG_OPEN 0x00020000 /*!< debug open proc. */
75
76 static int debug = 0;
77 module_param(debug, int, 0);
78 MODULE_PARM_DESC(debug, "debug mask (-1 for all)");
79
80 /* define which debugs are left in the code during compilation */
81 #define DEBUG (-1) /* all debugs */
82
83 #define dbg(l, f, ...) \
84 do { \
85 if ((DEBUG & l) && (debug & l)) { \
86 printk(KERN_INFO DRV_NAME " %s: " f, __FUNCTION__, ## __VA_ARGS__); \
87 } \
88 } while (0)
89
90 #define err(f, ...) printk(KERN_WARNING DRV_NAME " %s: " f, __FUNCTION__, ## __VA_ARGS__)
91
92 /* PHY CHIP Address */
93 #define PHY1_ADDR 1 /* For MAC1 */
94 #define PHY2_ADDR 2 /* For MAC2 */
95 #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
96 #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
97
98 /* Time in jiffies before concluding the transmitter is hung. */
99 #define TX_TIMEOUT (6000 * HZ / 1000)
100
101 /* RDC MAC I/O Size */
102 #define R6040_IO_SIZE 256
103
104 /* MAX RDC MAC */
105 #define MAX_MAC 2
106
107 /* MAC registers */
108 #define MCR0 0x00 /* Control register 0 */
109 #define MCR1 0x04 /* Control register 1 */
110 #define MAC_RST 0x0001 /* Reset the MAC */
111 #define MBCR 0x08 /* Bus control */
112 #define MT_ICR 0x0C /* TX interrupt control */
113 #define MR_ICR 0x10 /* RX interrupt control */
114 #define MTPR 0x14 /* TX poll command register */
115 #define MR_BSR 0x18 /* RX buffer size */
116 #define MR_DCR 0x1A /* RX descriptor control */
117 #define MLSR 0x1C /* Last status */
118 #define MMDIO 0x20 /* MDIO control register */
119 #define MDIO_WRITE 0x4000 /* MDIO write */
120 #define MDIO_READ 0x2000 /* MDIO read */
121 #define MMRD 0x24 /* MDIO read data register */
122 #define MMWD 0x28 /* MDIO write data register */
123 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
124 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
125 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
126 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
127 #define MISR 0x3C /* Status register */
128 #define MIER 0x40 /* INT enable register */
129 #define MSK_INT 0x0000 /* Mask off interrupts */
130 #define RX_FINISH 0x0001 /* rx finished irq */
131 #define RX_NO_DESC 0x0002 /* rx no descr. avail. irq */
132 #define RX_FIFO_FULL 0x0004 /* rx fifo full irq */
133 #define RX_EARLY 0x0008 /* rx early irq */
134 #define TX_FINISH 0x0010 /* tx finished irq */
135 #define TX_EARLY 0x0080 /* tx early irq */
136 #define EVENT_OVRFL 0x0100 /* event counter overflow irq */
137 #define LINK_CHANGED 0x0200 /* PHY link changed irq */
138
139 #define ME_CISR 0x44 /* Event counter INT status */
140 #define ME_CIER 0x48 /* Event counter INT enable */
141 #define MR_CNT 0x50 /* Successfully received packet counter */
142 #define ME_CNT0 0x52 /* Event counter 0 */
143 #define ME_CNT1 0x54 /* Event counter 1 */
144 #define ME_CNT2 0x56 /* Event counter 2 */
145 #define ME_CNT3 0x58 /* Event counter 3 */
146 #define MT_CNT 0x5A /* Successfully transmit packet counter */
147 #define ME_CNT4 0x5C /* Event counter 4 */
148 #define MP_CNT 0x5E /* Pause frame counter register */
149 #define MAR0 0x60 /* Hash table 0 */
150 #define MAR1 0x62 /* Hash table 1 */
151 #define MAR2 0x64 /* Hash table 2 */
152 #define MAR3 0x66 /* Hash table 3 */
153 #define MID_0L 0x68 /* Multicast address MID0 Low */
154 #define MID_0M 0x6A /* Multicast address MID0 Medium */
155 #define MID_0H 0x6C /* Multicast address MID0 High */
156 #define MID_1L 0x70 /* MID1 Low */
157 #define MID_1M 0x72 /* MID1 Medium */
158 #define MID_1H 0x74 /* MID1 High */
159 #define MID_2L 0x78 /* MID2 Low */
160 #define MID_2M 0x7A /* MID2 Medium */
161 #define MID_2H 0x7C /* MID2 High */
162 #define MID_3L 0x80 /* MID3 Low */
163 #define MID_3M 0x82 /* MID3 Medium */
164 #define MID_3H 0x84 /* MID3 High */
165 #define PHY_CC 0x88 /* PHY status change configuration register */
166 #define PHY_ST 0x8A /* PHY status register */
167 #define MAC_SM 0xAC /* MAC status machine */
168 #define MAC_ID 0xBE /* Identifier register */
169
170 #define TX_DCNT 0x80 /* TX descriptor count */
171 #define RX_DCNT 0x80 /* RX descriptor count */
172 #define MAX_BUF_SIZE 0x600
173 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
174 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
175 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register:
176 - wait 1 host clock until SDRAM bus request
177 becomes high priority
178 - RX FIFO: 32 byte
179 - TX FIFO: 64 byte
180 - FIFO transfer length: 16 byte */
181 #define MCAST_MAX 4 /* Max number multicast addresses to filter */
182
183 /* PHY settings */
184 #define ICPLUS_PHY_ID 0x0243
185
186 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
187 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
188 "Florian Fainelli <florian@openwrt.org>");
189 MODULE_LICENSE("GPL");
190 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
191
192 /*! which rx interrupts do we allow */
193 #define RX_INTS (RX_FIFO_FULL|RX_NO_DESC|RX_FINISH)
194 /*! which tx interrupts do we allow */
195 #define TX_INTS (TX_FINISH)
196 #define INT_MASK (RX_INTS | TX_INTS)
197
198 struct r6040_descriptor {
199 u16 status, len; /* 0-3 */
200 __le32 buf; /* 4-7 */
201 __le32 ndesc; /* 8-B */
202 u32 rev1; /* C-F */
203 char *vbufp; /* 10-13 */
204 struct r6040_descriptor *vndescp; /* 14-17 */
205 struct sk_buff *skb_ptr; /* 18-1B */
206 u32 rev2; /* 1C-1F */
207 } __attribute__((aligned(32)));
208
209 /*! defines for the status field in the r6040_descriptor */
210 #define DESC_STATUS_OWNER_MAC (1<<15) /*!< if set the MAC is the owner of this descriptor */
211 #define DESC_STATUS_RX_OK (1<<14) /*!< rx was successful */
212 #define DESC_STATUS_RX_ERR (1<<11) /*!< rx PHY error */
213 #define DESC_STATUS_RX_ERR_DRIBBLE (1<<10) /*!< rx dribble packet */
214 #define DESC_STATUS_RX_ERR_BUFLEN (1<< 9) /*!< rx length exceeded buffer size */
215 #define DESC_STATUS_RX_ERR_LONG (1<< 8) /*!< rx length > maximum packet length */
216 #define DESC_STATUS_RX_ERR_RUNT (1<< 7) /*!< rx: packet length < 64 byte */
217 #define DESC_STATUS_RX_ERR_CRC (1<< 6) /*!< rx: crc error */
218 #define DESC_STATUS_RX_BROADCAST (1<< 5) /*!< rx: broadcast (no error) */
219 #define DESC_STATUS_RX_MULTICAST (1<< 4) /*!< rx: multicast (no error) */
220 #define DESC_STATUS_RX_MCH_HIT (1<< 3) /*!< rx: multicast hit in hash table (no error) */
221 #define DESC_STATUS_RX_MIDH_HIT (1<< 2) /*!< rx: MID table hit (no error) */
222 #define DESC_STATUS_RX_IDX_MID_MASK 3 /*!< rx: mask for the index of matched MIDx */
223
224 struct r6040_private {
225 spinlock_t lock; /* driver lock */
226 struct timer_list timer;
227 struct pci_dev *pdev;
228 struct r6040_descriptor *rx_insert_ptr;
229 struct r6040_descriptor *rx_remove_ptr;
230 struct r6040_descriptor *tx_insert_ptr;
231 struct r6040_descriptor *tx_remove_ptr;
232 struct r6040_descriptor *rx_ring;
233 struct r6040_descriptor *tx_ring;
234 dma_addr_t rx_ring_dma;
235 dma_addr_t tx_ring_dma;
236 u16 tx_free_desc, phy_addr, phy_mode;
237 u16 mcr0, mcr1;
238 u16 switch_sig;
239 struct net_device *dev;
240 struct mii_if_info mii_if;
241 struct napi_struct napi;
242 void __iomem *base;
243 };
244
245 static char *parent = "wlan0";
246 module_param(parent, charp, 0444);
247 MODULE_PARM_DESC(parent, "Parent network device name to get the MAC address from");
248
249 static u8 mac_base[ETH_ALEN] = {0,0x50,0xfc,2,3,4};
250 module_param_array(mac_base, byte, NULL, 0444);
251 MODULE_PARM_DESC(mac_base, "Starting MAC address");
252
253 static int reverse = 1;
254 module_param(reverse, invbool, 0444);
255 MODULE_PARM_DESC(reverse, "Reverse card indices");
256
257 static char version[] __devinitdata = DRV_NAME
258 ": RDC R6040 NAPI net driver,"
259 "version "DRV_VERSION " (" DRV_RELDATE ")";
260
261 static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
262
263 /* forward declarations */
264 void r6040_multicast_list(struct net_device *dev);
265
266 /* jal2: comment out to get more symbols for debugging */
267 //#define STATIC static
268 #define STATIC
269
270 #if DEBUG
271 /*! hexdump an memory area into a string. delim is taken as the delimiter between two bytes.
272 It is omitted if delim == '\0' */
273 STATIC char *hex2str(void *addr, char *buf, int nr_bytes, int delim)
274 {
275 unsigned char *src = addr;
276 char *outb = buf;
277
278 #define BIN2HEXDIGIT(x) ((x) < 10 ? '0'+(x) : 'A'-10+(x))
279
280 while (nr_bytes > 0) {
281 *outb++ = BIN2HEXDIGIT(*src>>4);
282 *outb++ = BIN2HEXDIGIT(*src&0xf);
283 if (delim)
284 *outb++ = delim;
285 nr_bytes--;
286 src++;
287 }
288
289 if (delim)
290 outb--;
291 *outb = '\0';
292 return buf;
293 }
294
295 #endif /* #if DEBUG */
296
297 /* Read a word data from PHY Chip */
298 STATIC int phy_read(void __iomem *ioaddr, int phy_addr, int reg)
299 {
300 int limit = 2048;
301 u16 cmd;
302 int rc;
303
304 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
305 /* Wait for the read bit to be cleared */
306 while (limit--) {
307 cmd = ioread16(ioaddr + MMDIO);
308 if (cmd & MDIO_READ)
309 break;
310 }
311
312 if (limit <= 0)
313 err("phy addr x%x reg x%x timed out\n",
314 phy_addr, reg);
315
316 rc=ioread16(ioaddr + MMRD);
317
318 dbg(DBG_PHY, "phy addr x%x reg x%x val x%x\n", phy_addr, reg, rc);
319 return rc;
320 }
321
322 /* Write a word data from PHY Chip */
323 STATIC void phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
324 {
325 int limit = 2048;
326 u16 cmd;
327
328 dbg(DBG_PHY, "phy addr x%x reg x%x val x%x\n", phy_addr, reg, val);
329
330 iowrite16(val, ioaddr + MMWD);
331 /* Write the command to the MDIO bus */
332 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
333 /* Wait for the write bit to be cleared */
334 while (limit--) {
335 cmd = ioread16(ioaddr + MMDIO);
336 if (cmd & MDIO_WRITE)
337 break;
338 }
339 if (limit <= 0)
340 err("phy addr x%x reg x%x val x%x timed out\n",
341 phy_addr, reg, val);
342 }
343
344 STATIC int mdio_read(struct net_device *dev, int mii_id, int reg)
345 {
346 struct r6040_private *lp = netdev_priv(dev);
347 void __iomem *ioaddr = lp->base;
348
349 return (phy_read(ioaddr, lp->phy_addr, reg));
350 }
351
352 STATIC void mdio_write(struct net_device *dev, int mii_id, int reg, int val)
353 {
354 struct r6040_private *lp = netdev_priv(dev);
355 void __iomem *ioaddr = lp->base;
356
357 phy_write(ioaddr, lp->phy_addr, reg, val);
358 }
359
360 void r6040_free_txbufs(struct net_device *dev)
361 {
362 struct r6040_private *lp = netdev_priv(dev);
363 int i;
364
365 dbg(DBG_FREE_BUFS, "ENTER\n");
366 for (i = 0; i < TX_DCNT; i++) {
367 if (lp->tx_insert_ptr->skb_ptr) {
368 pci_unmap_single(lp->pdev,
369 le32_to_cpu(lp->tx_insert_ptr->buf),
370 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
371 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
372 lp->tx_insert_ptr->skb_ptr = NULL;
373 }
374 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
375 }
376 dbg(DBG_FREE_BUFS, "EXIT\n");
377 }
378
379 /*! unmap and free all rx skb */
380 void r6040_free_rxbufs(struct net_device *dev)
381 {
382 struct r6040_private *lp = netdev_priv(dev);
383 int i;
384
385 dbg(DBG_FREE_BUFS, "ENTER\n");
386 for (i = 0; i < RX_DCNT; i++) {
387 if (lp->rx_insert_ptr->skb_ptr) {
388 pci_unmap_single(lp->pdev,
389 le32_to_cpu(lp->rx_insert_ptr->buf),
390 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
391 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
392 lp->rx_insert_ptr->skb_ptr = NULL;
393 }
394 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
395 }
396 dbg(DBG_FREE_BUFS, "EXIT\n");
397
398 }
399
400 void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
401 dma_addr_t desc_dma, int size)
402 {
403 struct r6040_descriptor *desc = desc_ring;
404 dma_addr_t mapping = desc_dma;
405
406 dbg(DBG_RING, "desc_ring %p desc_dma %08x size x%x\n",
407 desc_ring, desc_dma, size);
408
409
410 while (size-- > 0) {
411 mapping += sizeof(*desc);
412 memset(desc, 0, sizeof(*desc));
413 desc->ndesc = cpu_to_le32(mapping);
414 desc->vndescp = desc + 1;
415 desc++;
416 }
417
418 /* last descriptor points to first one to close the descriptor ring */
419 desc--;
420 desc->ndesc = cpu_to_le32(desc_dma);
421 desc->vndescp = desc_ring;
422 }
423
424 #if (DEBUG & DBG_TX_RING_DUMP)
425 /*! dump the tx ring to syslog */
426 STATIC void
427 dump_tx_ring(struct r6040_private *lp)
428 {
429 int i;
430 struct r6040_descriptor *ptr;
431
432 printk(KERN_INFO "%s: nr_desc x%x tx_ring %p tx_ring_dma %08x "
433 "tx_insert %p tx_remove %p\n",
434 DRV_NAME, TX_DCNT, lp->tx_ring, lp->tx_ring_dma,
435 lp->tx_insert_ptr, lp->tx_remove_ptr);
436
437 if (lp->tx_ring) {
438 for(i=0, ptr=lp->tx_ring; i < TX_DCNT; i++, ptr++) {
439 printk(KERN_INFO "%s: %d. descr: status x%x len x%x "
440 "ndesc %08x vbufp %p vndescp %p skb_ptr %p\n",
441 DRV_NAME, i, ptr->status, ptr->len,
442 ptr->ndesc, ptr->vbufp, ptr->vndescp, ptr->skb_ptr);
443 }
444 }
445 }
446 #endif /* #if (DEBUG & DBG_TX_RING_DUMP) */
447
448 void r6040_init_txbufs(struct net_device *dev)
449 {
450 struct r6040_private *lp = netdev_priv(dev);
451
452 lp->tx_free_desc = TX_DCNT;
453
454 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
455 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
456
457 #if (DEBUG & DBG_TX_RING_DUMP)
458 if (debug & DBG_TX_RING_DUMP) {
459 dump_tx_ring(lp);
460 }
461 #endif
462 }
463
464 #if (DEBUG & DBG_RX_RING_DUMP)
465 /*! dump the rx ring to syslog */
466 STATIC void
467 dump_rx_ring(struct r6040_private *lp)
468 {
469 int i;
470 struct r6040_descriptor *ptr;
471
472 printk(KERN_INFO "%s: nr_desc x%x rx_ring %p rx_ring_dma %08x "
473 "rx_insert %p rx_remove %p\n",
474 DRV_NAME, RX_DCNT, lp->rx_ring, lp->rx_ring_dma,
475 lp->rx_insert_ptr, lp->rx_remove_ptr);
476
477 if (lp->rx_ring) {
478 for(i=0, ptr=lp->rx_ring; i < RX_DCNT; i++, ptr++) {
479 printk(KERN_INFO "%s: %d. descr: status x%x len x%x "
480 "ndesc %08x vbufp %p vndescp %p skb_ptr %p\n",
481 DRV_NAME, i, ptr->status, ptr->len,
482 ptr->ndesc, ptr->vbufp, ptr->vndescp, ptr->skb_ptr);
483 }
484 }
485 }
486 #endif /* #if (DEBUG & DBG_TX_RING_DUMP) */
487
488 int r6040_alloc_rxbufs(struct net_device *dev)
489 {
490 struct r6040_private *lp = netdev_priv(dev);
491 struct r6040_descriptor *desc;
492 struct sk_buff *skb;
493 int rc;
494
495 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
496 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
497
498 /* alloc skbs for the rx descriptors */
499 desc = lp->rx_ring;
500 do {
501 if (!(skb=netdev_alloc_skb(dev, MAX_BUF_SIZE))) {
502 err("failed to alloc skb for rx\n");
503 rc = -ENOMEM;
504 goto err_exit;
505 }
506 desc->skb_ptr = skb;
507 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
508 desc->skb_ptr->data,
509 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
510 desc->status = DESC_STATUS_OWNER_MAC;
511 desc = desc->vndescp;
512 } while (desc != lp->rx_ring);
513
514 #if (DEBUG & DBG_RX_RING_DUMP)
515 if (debug & DBG_RX_RING_DUMP) {
516 dump_rx_ring(lp);
517 }
518 #endif
519
520 return 0;
521
522 err_exit:
523 /* dealloc all previously allocated skb */
524 r6040_free_rxbufs(dev);
525 return rc;
526 }
527
528 /*! reset MAC and set all registers */
529 void r6040_init_mac_regs(struct r6040_private *lp)
530 {
531 void __iomem *ioaddr = lp->base;
532 int limit;
533 char obuf[3*ETH_ALEN] __attribute__ ((unused));
534
535 /* Mask Off Interrupt */
536 iowrite16(MSK_INT, ioaddr + MIER);
537
538 /* reset MAC */
539 iowrite16(MAC_RST, ioaddr + MCR1);
540 udelay(100);
541 limit=2048;
542 while ((ioread16(ioaddr + MCR1) & MAC_RST) && limit-- > 0);
543
544 /* Reset internal state machine */
545 iowrite16(2, ioaddr + MAC_SM);
546 iowrite16(0, ioaddr + MAC_SM);
547 udelay(5000);
548
549 /* Restore MAC Addresses */
550 r6040_multicast_list(lp->dev);
551
552 /* TODO: restore multcast and hash table */
553
554 /* MAC Bus Control Register */
555 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
556
557 /* Buffer Size Register */
558 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
559
560 /* write tx ring start address */
561 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
562 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
563
564 /* write rx ring start address */
565 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
566 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
567
568 /* set interrupt waiting time and packet numbers */
569 iowrite16(0, ioaddr + MT_ICR);
570 iowrite16(0, ioaddr + MR_ICR);
571
572 /* enable interrupts */
573 iowrite16(INT_MASK, ioaddr + MIER);
574
575 /* enable tx and rx */
576 iowrite16(lp->mcr0 | 0x0002, ioaddr);
577
578 /* let TX poll the descriptors - we may got called by r6040_tx_timeout which has left
579 some unsent tx buffers */
580 iowrite16(0x01, ioaddr + MTPR);
581 }
582
583 void r6040_tx_timeout(struct net_device *dev)
584 {
585 struct r6040_private *priv = netdev_priv(dev);
586 void __iomem *ioaddr = priv->base;
587
588 /* we read MISR, which clears on read (i.e. we may loose an RX interupt,
589 but this is an error anyhow ... */
590 printk(KERN_WARNING "%s: transmit timed out, int enable %4.4x "
591 "status %4.4x, PHY status %4.4x\n",
592 dev->name, ioread16(ioaddr + MIER),
593 ioread16(ioaddr + MISR),
594 mdio_read(dev, priv->mii_if.phy_id, MII_BMSR));
595
596 dev->stats.tx_errors++;
597
598 /* Reset MAC and re-init all registers */
599 r6040_init_mac_regs(priv);
600 }
601
602 struct net_device_stats *r6040_get_stats(struct net_device *dev)
603 {
604 struct r6040_private *priv = netdev_priv(dev);
605 void __iomem *ioaddr = priv->base;
606 unsigned long flags;
607
608 spin_lock_irqsave(&priv->lock, flags);
609 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
610 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
611 spin_unlock_irqrestore(&priv->lock, flags);
612
613 return &dev->stats;
614 }
615
616 /* Stop RDC MAC and Free the allocated resource */
617 void r6040_down(struct net_device *dev)
618 {
619 struct r6040_private *lp = netdev_priv(dev);
620 void __iomem *ioaddr = lp->base;
621 struct pci_dev *pdev = lp->pdev;
622 int limit = 2048;
623
624 dbg(DBG_EXIT, "ENTER\n");
625
626 /* Stop MAC */
627 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
628 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
629 udelay(100);
630 while ((ioread16(ioaddr+MCR1) & 1) && limit-- > 0);
631
632 if (limit <= 0)
633 err("timeout while waiting for reset done.\n");
634
635 free_irq(dev->irq, dev);
636
637 /* Free RX buffer */
638 r6040_free_rxbufs(dev);
639
640 /* Free TX buffer */
641 r6040_free_txbufs(dev);
642
643 /* Free Descriptor memory */
644 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
645 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
646
647 dbg(DBG_EXIT, "EXIT\n");
648 }
649
650 int r6040_close(struct net_device *dev)
651 {
652 struct r6040_private *lp = netdev_priv(dev);
653
654 dbg(DBG_EXIT, "ENTER\n");
655
656 /* deleted timer */
657 del_timer_sync(&lp->timer);
658 spin_lock_irq(&lp->lock);
659 napi_disable(&lp->napi);
660 netif_stop_queue(dev);
661 r6040_down(dev);
662 spin_unlock_irq(&lp->lock);
663
664 dbg(DBG_EXIT, "EXIT\n");
665 return 0;
666 }
667
668 /* Status of PHY CHIP. Returns 0x8000 for full duplex, 0 for half duplex */
669 STATIC int phy_mode_chk(struct net_device *dev)
670 {
671 struct r6040_private *lp = netdev_priv(dev);
672 void __iomem *ioaddr = lp->base;
673 int phy_dat;
674
675 /* PHY Link Status Check */
676 phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
677 if (!(phy_dat & 0x4))
678 phy_dat = 0x8000; /* Link Failed, full duplex */
679
680 /* PHY Chip Auto-Negotiation Status */
681 phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
682 if (phy_dat & 0x0020) {
683 /* Auto Negotiation Mode */
684 phy_dat = phy_read(ioaddr, lp->phy_addr, 5);
685 phy_dat &= phy_read(ioaddr, lp->phy_addr, 4);
686 if (phy_dat & 0x140)
687 /* Force full duplex */
688 phy_dat = 0x8000;
689 else
690 phy_dat = 0;
691 } else {
692 /* Force Mode */
693 phy_dat = phy_read(ioaddr, lp->phy_addr, 0);
694 if (phy_dat & 0x100)
695 phy_dat = 0x8000;
696 else
697 phy_dat = 0x0000;
698 }
699
700 dbg(DBG_PHY, "RETURN x%x\n", phy_dat);
701 return phy_dat;
702 };
703
704 void r6040_set_carrier(struct mii_if_info *mii)
705 {
706 if (phy_mode_chk(mii->dev)) {
707 /* autoneg is off: Link is always assumed to be up */
708 if (!netif_carrier_ok(mii->dev))
709 netif_carrier_on(mii->dev);
710 } else
711 phy_mode_chk(mii->dev);
712 }
713
714 int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
715 {
716 struct r6040_private *lp = netdev_priv(dev);
717 struct mii_ioctl_data *data = if_mii(rq);
718 int rc;
719
720 if (!netif_running(dev))
721 return -EINVAL;
722 spin_lock_irq(&lp->lock);
723 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
724 spin_unlock_irq(&lp->lock);
725 r6040_set_carrier(&lp->mii_if);
726 return rc;
727 }
728
729 int r6040_rx(struct net_device *dev, int limit)
730 {
731 struct r6040_private *priv = netdev_priv(dev);
732 int count=0;
733 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
734 struct sk_buff *skb_ptr, *new_skb;
735 char obuf[2*32+1] __attribute__ ((unused)); /* for debugging */
736
737 while (count < limit && !(descptr->status & DESC_STATUS_OWNER_MAC)) {
738 /* limit not reached and the descriptor belongs to the CPU */
739
740 dbg(DBG_RX_DESCR, "descptr %p status x%x data len x%x\n",
741 descptr, descptr->status, descptr->len);
742
743 /* Check for errors */
744 if (descptr->status & DESC_STATUS_RX_ERR) {
745
746 dev->stats.rx_errors++;
747
748 if (descptr->status & (DESC_STATUS_RX_ERR_DRIBBLE|
749 DESC_STATUS_RX_ERR_BUFLEN|
750 DESC_STATUS_RX_ERR_LONG|
751 DESC_STATUS_RX_ERR_RUNT)) {
752 /* packet too long or too short*/
753 dev->stats.rx_length_errors++;
754 }
755
756 if (descptr->status & DESC_STATUS_RX_ERR_CRC) {
757 dev->stats.rx_crc_errors++;
758 }
759 goto next_descr;
760 }
761
762 /* successful received packet */
763
764 /* first try to allocate new skb. If this fails
765 we drop the packet and leave the old skb there.*/
766 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
767 if (!new_skb) {
768 dev->stats.rx_dropped++;
769 goto next_descr;
770 }
771 skb_ptr = descptr->skb_ptr;
772 skb_ptr->dev = priv->dev;
773 /* Do not count the CRC */
774 skb_put(skb_ptr, descptr->len - 4);
775 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
776 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
777 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
778
779 dbg(DBG_RX_DATA, "rx len x%x: %s...\n",
780 descptr->len,
781 hex2str(skb_ptr->data, obuf, sizeof(obuf)/2, '\0'));
782
783 /* Send to upper layer */
784 netif_receive_skb(skb_ptr);
785 dev->last_rx = jiffies;
786 dev->stats.rx_packets++;
787 dev->stats.rx_bytes += (descptr->len-4);
788
789 /* put new skb into descriptor */
790 descptr->skb_ptr = new_skb;
791 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
792 descptr->skb_ptr->data,
793 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
794
795 next_descr:
796 /* put the descriptor back to the MAC */
797 descptr->status = DESC_STATUS_OWNER_MAC;
798 descptr = descptr->vndescp;
799 count++; /* shall we count errors and dropped packets as well? */
800 } /* while (limit && !(descptr->status & DESC_STATUS_OWNER_MAC)) */
801
802 /* remember next descriptor to check for rx */
803 priv->rx_remove_ptr = descptr;
804
805 return count;
806 }
807
808 void r6040_tx(struct net_device *dev)
809 {
810 struct r6040_private *priv = netdev_priv(dev);
811 struct r6040_descriptor *descptr;
812 void __iomem *ioaddr = priv->base;
813 struct sk_buff *skb_ptr;
814 u16 err;
815
816 spin_lock(&priv->lock);
817 descptr = priv->tx_remove_ptr;
818 while (priv->tx_free_desc < TX_DCNT) {
819 /* Check for errors */
820 err = ioread16(ioaddr + MLSR);
821
822 if (err & 0x0200)
823 dev->stats.rx_fifo_errors++;
824 if (err & (0x2000 | 0x4000))
825 dev->stats.tx_carrier_errors++;
826
827 dbg(DBG_TX_DONE, "descptr %p status x%x err x%x jiffies %lu\n",
828 descptr, descptr->status, err, jiffies);
829
830 if (descptr->status & 0x8000)
831 break; /* Not complete */
832 skb_ptr = descptr->skb_ptr;
833 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
834 skb_ptr->len, PCI_DMA_TODEVICE);
835 /* Free buffer */
836 dev_kfree_skb_irq(skb_ptr);
837 descptr->skb_ptr = NULL;
838 /* To next descriptor */
839 descptr = descptr->vndescp;
840 priv->tx_free_desc++;
841 }
842 priv->tx_remove_ptr = descptr;
843
844 if (priv->tx_free_desc)
845 netif_wake_queue(dev);
846 spin_unlock(&priv->lock);
847 }
848
849 int r6040_poll(struct napi_struct *napi, int budget)
850 {
851 struct r6040_private *priv =
852 container_of(napi, struct r6040_private, napi);
853 struct net_device *dev = priv->dev;
854 void __iomem *ioaddr = priv->base;
855 int work_done;
856
857 work_done = r6040_rx(dev, budget);
858
859 dbg(DBG_POLL, "budget x%x done x%x\n", budget, work_done);
860
861 if (work_done < budget) {
862 netif_rx_complete(dev, napi);
863 /* Enable RX interrupt */
864 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
865 }
866 return work_done;
867 }
868
869 /* The RDC interrupt handler. */
870 irqreturn_t r6040_interrupt(int irq, void *dev_id)
871 {
872 struct net_device *dev = dev_id;
873 struct r6040_private *lp = netdev_priv(dev);
874 void __iomem *ioaddr = lp->base;
875 u16 status;
876
877 /* Read MISR status and clear */
878 status = ioread16(ioaddr + MISR);
879
880 dbg(DBG_IRQ, "status x%x jiffies %lu\n", status, jiffies);
881
882 if (status == 0x0000 || status == 0xffff)
883 return IRQ_NONE;
884
885 /* rx early / rx finish interrupt
886 or rx descriptor unavail. */
887 if (status & RX_INTS) {
888 if (status & RX_NO_DESC) {
889 /* rx descriptor unavail. */
890 dev->stats.rx_dropped++;
891 dev->stats.rx_missed_errors++;
892 }
893 /* Mask off RX interrupts */
894 iowrite16(ioread16(ioaddr + MIER) & ~RX_INTS, ioaddr + MIER);
895 netif_rx_schedule(dev, &lp->napi);
896 }
897
898 /* rx FIFO full */
899 if (status & RX_FIFO_FULL) {
900 dev->stats.rx_fifo_errors++;
901 }
902
903 /* TX interrupt request */
904 if (status & 0x10)
905 r6040_tx(dev);
906
907 return IRQ_HANDLED;
908 }
909
910 #ifdef CONFIG_NET_POLL_CONTROLLER
911 void r6040_poll_controller(struct net_device *dev)
912 {
913 disable_irq(dev->irq);
914 r6040_interrupt(dev->irq, dev);
915 enable_irq(dev->irq);
916 }
917 #endif
918
919 /* Init RDC MAC */
920 int r6040_up(struct net_device *dev)
921 {
922 struct r6040_private *lp = netdev_priv(dev);
923 void __iomem *ioaddr = lp->base;
924 int rc;
925
926 dbg(DBG_INIT, "ENTER\n");
927
928 /* Initialise and alloc RX/TX buffers */
929 r6040_init_txbufs(dev);
930 if ((rc=r6040_alloc_rxbufs(dev)))
931 return rc;
932
933 /* Read the PHY ID */
934 lp->switch_sig = phy_read(ioaddr, 0, 2);
935
936 if (lp->switch_sig == ICPLUS_PHY_ID) {
937 phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
938 lp->phy_mode = 0x8000;
939 } else {
940 /* PHY Mode Check */
941 phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
942 phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
943
944 if (PHY_MODE == 0x3100)
945 lp->phy_mode = phy_mode_chk(dev);
946 else
947 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
948 }
949
950 /* configure duplex mode */
951 lp->mcr0 |= lp->phy_mode;
952
953 /* improve performance (by RDC guys) */
954 phy_write(ioaddr, 30, 17, (phy_read(ioaddr, 30, 17) | 0x4000));
955 phy_write(ioaddr, 30, 17, ~((~phy_read(ioaddr, 30, 17)) | 0x2000));
956 phy_write(ioaddr, 0, 19, 0x0000);
957 phy_write(ioaddr, 0, 30, 0x01F0);
958
959 /* Reset MAC and init all registers */
960 r6040_init_mac_regs(lp);
961
962 return 0;
963 }
964
965 /*
966 A periodic timer routine
967 Polling PHY Chip Link Status
968 */
969 void r6040_timer(unsigned long data)
970 {
971 struct net_device *dev = (struct net_device *)data;
972 struct r6040_private *lp = netdev_priv(dev);
973 void __iomem *ioaddr = lp->base;
974 u16 phy_mode;
975
976 /* Polling PHY Chip Status */
977 if (PHY_MODE == 0x3100)
978 phy_mode = phy_mode_chk(dev);
979 else
980 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
981
982 if (phy_mode != lp->phy_mode) {
983 lp->phy_mode = phy_mode;
984 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
985 iowrite16(lp->mcr0, ioaddr);
986 printk(KERN_INFO "Link Change x%x \n", ioread16(ioaddr));
987 }
988
989 /* Timer active again */
990 mod_timer(&lp->timer, jiffies + round_jiffies(HZ));
991 }
992
993 int r6040_open(struct net_device *dev)
994 {
995 struct r6040_private *lp = netdev_priv(dev);
996 int ret;
997
998 dbg(DBG_OPEN, "ENTER\n");
999 /* Request IRQ and Register interrupt handler */
1000 ret = request_irq(dev->irq, &r6040_interrupt,
1001 IRQF_SHARED, dev->name, dev);
1002 if (ret)
1003 return ret;
1004
1005 dbg(DBG_OPEN, "got irq %d\n", dev->irq);
1006
1007 /* Allocate Descriptor memory */
1008 lp->rx_ring =
1009 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
1010 if (!lp->rx_ring)
1011 return -ENOMEM;
1012
1013 dbg(DBG_OPEN, "allocated rx ring\n");
1014
1015 lp->tx_ring =
1016 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
1017 if (!lp->tx_ring) {
1018 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
1019 lp->rx_ring_dma);
1020 return -ENOMEM;
1021 }
1022
1023 dbg(DBG_OPEN, "allocated tx ring\n");
1024
1025 if ((ret=r6040_up(dev))) {
1026 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
1027 lp->tx_ring_dma);
1028 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
1029 lp->rx_ring_dma);
1030 return ret;
1031 }
1032
1033 napi_enable(&lp->napi);
1034 netif_start_queue(dev);
1035
1036 /* set and active a timer process */
1037 setup_timer(&lp->timer, r6040_timer, (unsigned long) dev);
1038 if (lp->switch_sig != ICPLUS_PHY_ID)
1039 mod_timer(&lp->timer, jiffies + HZ);
1040 return 0;
1041 }
1042
1043 int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev)
1044 {
1045 struct r6040_private *lp = netdev_priv(dev);
1046 struct r6040_descriptor *descptr;
1047 void __iomem *ioaddr = lp->base;
1048 unsigned long flags;
1049 int ret = NETDEV_TX_OK;
1050
1051 /* Critical Section */
1052 spin_lock_irqsave(&lp->lock, flags);
1053
1054 /* TX resource check */
1055 if (!lp->tx_free_desc) {
1056 spin_unlock_irqrestore(&lp->lock, flags);
1057 netif_stop_queue(dev);
1058 printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
1059 ret = NETDEV_TX_BUSY;
1060 return ret;
1061 }
1062
1063 /* Statistic Counter */
1064 dev->stats.tx_packets++;
1065 dev->stats.tx_bytes += skb->len;
1066 /* Set TX descriptor & Transmit it */
1067 lp->tx_free_desc--;
1068 descptr = lp->tx_insert_ptr;
1069 if (skb->len < MISR)
1070 descptr->len = MISR;
1071 else
1072 descptr->len = skb->len;
1073
1074 descptr->skb_ptr = skb;
1075 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
1076 skb->data, skb->len, PCI_DMA_TODEVICE));
1077
1078 dbg(DBG_TX_DESCR, "desc @ %p: len x%x buf %08x skb->data %p skb->len x%x jiffies %lu\n",
1079 descptr, descptr->len, descptr->buf, skb->data, skb->len, jiffies);
1080
1081 {
1082 char obuf[2*32+1];
1083 dbg(DBG_TX_DATA, "tx len x%x: %s\n",
1084 descptr->len, hex2str(skb->data, obuf, sizeof(obuf)/2, '\0'));
1085 }
1086
1087 descptr->status = 0x8000;
1088 /* Trigger the MAC to check the TX descriptor */
1089 iowrite16(0x01, ioaddr + MTPR);
1090 lp->tx_insert_ptr = descptr->vndescp;
1091
1092 /* If no tx resource, stop */
1093 if (!lp->tx_free_desc)
1094 netif_stop_queue(dev);
1095
1096 dev->trans_start = jiffies;
1097 spin_unlock_irqrestore(&lp->lock, flags);
1098 return ret;
1099 }
1100
1101 /*! set MAC addresses and promiscous mode */
1102 void r6040_multicast_list(struct net_device *dev)
1103 {
1104 struct r6040_private *lp = netdev_priv(dev);
1105 void __iomem *ioaddr = lp->base;
1106 u16 *adrp;
1107 u16 reg;
1108 unsigned long flags;
1109 struct dev_mc_list *dmi = dev->mc_list;
1110 int i;
1111 char obuf[3*ETH_ALEN] __attribute__ ((unused));
1112
1113 /* MAC Address */
1114 adrp = (u16 *)dev->dev_addr;
1115 iowrite16(adrp[0], ioaddr + MID_0L);
1116 iowrite16(adrp[1], ioaddr + MID_0M);
1117 iowrite16(adrp[2], ioaddr + MID_0H);
1118
1119 dbg(DBG_MAC_ADDR, "%s: set MAC addr %s\n",
1120 dev->name, hex2str(dev->dev_addr, obuf, ETH_ALEN, ':'));
1121
1122 /* Promiscous Mode */
1123 spin_lock_irqsave(&lp->lock, flags);
1124
1125 /* Clear AMCP & PROM bits */
1126 reg = ioread16(ioaddr) & ~0x0120;
1127 if (dev->flags & IFF_PROMISC) {
1128 reg |= 0x0020;
1129 lp->mcr0 |= 0x0020;
1130 }
1131 /* Too many multicast addresses
1132 * accept all traffic */
1133 else if ((dev->mc_count > MCAST_MAX)
1134 || (dev->flags & IFF_ALLMULTI))
1135 reg |= 0x0020;
1136
1137 iowrite16(reg, ioaddr);
1138 spin_unlock_irqrestore(&lp->lock, flags);
1139
1140 /* Build the hash table */
1141 if (dev->mc_count > MCAST_MAX) {
1142 u16 hash_table[4];
1143 u32 crc;
1144
1145 for (i = 0; i < 4; i++)
1146 hash_table[i] = 0;
1147
1148 for (i = 0; i < dev->mc_count; i++) {
1149 char *addrs = dmi->dmi_addr;
1150
1151 dmi = dmi->next;
1152
1153 if (!(*addrs & 1))
1154 continue;
1155
1156 crc = ether_crc_le(6, addrs);
1157 crc >>= 26;
1158 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1159 }
1160 /* Write the index of the hash table */
1161 for (i = 0; i < 4; i++)
1162 iowrite16(hash_table[i] << 14, ioaddr + MCR1);
1163 /* Fill the MAC hash tables with their values */
1164 iowrite16(hash_table[0], ioaddr + MAR0);
1165 iowrite16(hash_table[1], ioaddr + MAR1);
1166 iowrite16(hash_table[2], ioaddr + MAR2);
1167 iowrite16(hash_table[3], ioaddr + MAR3);
1168 }
1169 /* Multicast Address 1~4 case */
1170 for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) {
1171 adrp = (u16 *)dmi->dmi_addr;
1172 iowrite16(adrp[0], ioaddr + MID_1L + 8*i);
1173 iowrite16(adrp[1], ioaddr + MID_1M + 8*i);
1174 iowrite16(adrp[2], ioaddr + MID_1H + 8*i);
1175 dmi = dmi->next;
1176 }
1177 for (i = dev->mc_count; i < MCAST_MAX; i++) {
1178 iowrite16(0xffff, ioaddr + MID_0L + 8*i);
1179 iowrite16(0xffff, ioaddr + MID_0M + 8*i);
1180 iowrite16(0xffff, ioaddr + MID_0H + 8*i);
1181 }
1182 }
1183
1184 STATIC void netdev_get_drvinfo(struct net_device *dev,
1185 struct ethtool_drvinfo *info)
1186 {
1187 struct r6040_private *rp = netdev_priv(dev);
1188
1189 strcpy(info->driver, DRV_NAME);
1190 strcpy(info->version, DRV_VERSION);
1191 strcpy(info->bus_info, pci_name(rp->pdev));
1192 }
1193
1194 STATIC int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1195 {
1196 struct r6040_private *rp = netdev_priv(dev);
1197 int rc;
1198
1199 spin_lock_irq(&rp->lock);
1200 rc = mii_ethtool_gset(&rp->mii_if, cmd);
1201 spin_unlock_irq(&rp->lock);
1202
1203 return rc;
1204 }
1205
1206 STATIC int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1207 {
1208 struct r6040_private *rp = netdev_priv(dev);
1209 int rc;
1210
1211 spin_lock_irq(&rp->lock);
1212 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1213 spin_unlock_irq(&rp->lock);
1214 r6040_set_carrier(&rp->mii_if);
1215
1216 return rc;
1217 }
1218
1219 STATIC u32 netdev_get_link(struct net_device *dev)
1220 {
1221 struct r6040_private *rp = netdev_priv(dev);
1222
1223 return mii_link_ok(&rp->mii_if);
1224 }
1225
1226 static struct ethtool_ops netdev_ethtool_ops = {
1227 .get_drvinfo = netdev_get_drvinfo,
1228 .get_settings = netdev_get_settings,
1229 .set_settings = netdev_set_settings,
1230 .get_link = netdev_get_link,
1231 };
1232
1233 int __devinit r6040_init_one(struct pci_dev *pdev,
1234 const struct pci_device_id *ent)
1235 {
1236 struct net_device *dev, *parent_dev;
1237 struct r6040_private *lp;
1238 void __iomem *ioaddr;
1239 int err, io_size = R6040_IO_SIZE;
1240 static int card_idx = -1;
1241 long pioaddr;
1242
1243 printk(KERN_INFO "%s\n", version);
1244 printk(KERN_INFO DRV_NAME ": debug %x\n", debug);
1245
1246 err = pci_enable_device(pdev);
1247 if (err)
1248 return err;
1249
1250 /* this should always be supported */
1251 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1252 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1253 "not supported by the card\n");
1254 return -ENODEV;
1255 }
1256 if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1257 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1258 "not supported by the card\n");
1259 return -ENODEV;
1260 }
1261
1262 /* IO Size check */
1263 if (pci_resource_len(pdev, 0) < io_size) {
1264 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
1265 return -EIO;
1266 }
1267
1268 pioaddr = pci_resource_start(pdev, 0); /* IO map base address */
1269 pci_set_master(pdev);
1270
1271 dev = alloc_etherdev(sizeof(struct r6040_private));
1272 if (!dev) {
1273 printk(KERN_ERR "Failed to allocate etherdev\n");
1274 return -ENOMEM;
1275 }
1276 SET_NETDEV_DEV(dev, &pdev->dev);
1277 lp = netdev_priv(dev);
1278
1279 if (pci_request_regions(pdev, DRV_NAME)) {
1280 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
1281 err = -ENODEV;
1282 goto err_out_disable;
1283 }
1284
1285 ioaddr = pci_iomap(pdev, 0, io_size);
1286 if (!ioaddr) {
1287 printk(KERN_ERR "ioremap failed for device %s\n",
1288 pci_name(pdev));
1289 return -EIO;
1290 }
1291
1292 /* Init system & device */
1293 lp->base = ioaddr;
1294 dev->irq = pdev->irq;
1295
1296 spin_lock_init(&lp->lock);
1297 pci_set_drvdata(pdev, dev);
1298
1299 card_idx++;
1300
1301 /* Link new device into r6040_root_dev */
1302 lp->pdev = pdev;
1303
1304 lp->dev = dev;
1305
1306 /* Init RDC private data */
1307 lp->mcr0 = 0x1002;
1308 lp->phy_addr = phy_table[card_idx];
1309 lp->switch_sig = 0;
1310
1311 /* The RDC-specific entries in the device structure. */
1312 dev->open = &r6040_open;
1313 dev->hard_start_xmit = &r6040_start_xmit;
1314 dev->stop = &r6040_close;
1315 dev->get_stats = r6040_get_stats;
1316 dev->set_multicast_list = &r6040_multicast_list;
1317 dev->do_ioctl = &r6040_ioctl;
1318 dev->ethtool_ops = &netdev_ethtool_ops;
1319 dev->tx_timeout = &r6040_tx_timeout;
1320 dev->watchdog_timeo = TX_TIMEOUT;
1321
1322 /*
1323 You must specify a netdevice with a "parent=" parameter, whose address
1324 is copied, or an array of bytes comprising a literal address; otherwise
1325 the (default) address of the Sitecom WL-153 bootloader is used.
1326 */
1327 memcpy(dev->dev_addr, mac_base, ETH_ALEN);
1328 if (parent) {
1329 parent_dev = __dev_get_by_name(&init_net, parent);
1330 if (parent_dev)
1331 memcpy(dev->dev_addr, parent_dev->dev_addr, ETH_ALEN);
1332 }
1333 dev->dev_addr[ETH_ALEN-1] += card_idx ^ reverse; /* + 0 or 1 */
1334
1335 #ifdef CONFIG_NET_POLL_CONTROLLER
1336 dev->poll_controller = r6040_poll_controller;
1337 #endif
1338 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1339 lp->mii_if.dev = dev;
1340 lp->mii_if.mdio_read = mdio_read;
1341 lp->mii_if.mdio_write = mdio_write;
1342 lp->mii_if.phy_id = lp->phy_addr;
1343 lp->mii_if.phy_id_mask = 0x1f;
1344 lp->mii_if.reg_num_mask = 0x1f;
1345
1346 if (reverse && ((card_idx & 1) == 0) && (dev_alloc_name(dev, dev->name)
1347 >= 0))
1348 for (err = strlen(dev->name); err; err--) {
1349 if (dev->name[err - 1]++ != '9')
1350 break;
1351 dev->name[err - 1] = '0';
1352 }
1353
1354 /* Register net device. After this dev->name assign */
1355 err = register_netdev(dev);
1356 if (err) {
1357 printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
1358 goto err_out_res;
1359 }
1360
1361 dbg(DBG_INIT, "%s successfully registered\n", dev->name);
1362 return 0;
1363
1364 err_out_res:
1365 pci_release_regions(pdev);
1366 err_out_disable:
1367 pci_disable_device(pdev);
1368 pci_set_drvdata(pdev, NULL);
1369 free_netdev(dev);
1370
1371 return err;
1372 }
1373
1374 void __devexit r6040_remove_one(struct pci_dev *pdev)
1375 {
1376 struct net_device *dev = pci_get_drvdata(pdev);
1377
1378 unregister_netdev(dev);
1379 pci_release_regions(pdev);
1380 free_netdev(dev);
1381 pci_disable_device(pdev);
1382 pci_set_drvdata(pdev, NULL);
1383 }
1384
1385
1386 static struct pci_device_id r6040_pci_tbl[] = {
1387 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1388 { 0 }
1389 };
1390 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1391
1392 static struct pci_driver r6040_driver = {
1393 .name = DRV_NAME,
1394 .id_table = r6040_pci_tbl,
1395 .probe = r6040_init_one,
1396 .remove = __devexit_p(r6040_remove_one),
1397 };
1398
1399
1400 static int __init r6040_init(void)
1401 {
1402 return pci_register_driver(&r6040_driver);
1403 }
1404
1405
1406 static void __exit r6040_cleanup(void)
1407 {
1408 pci_unregister_driver(&r6040_driver);
1409 }
1410
1411 module_init(r6040_init);
1412 module_exit(r6040_cleanup);
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