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[package] mac80211: update compat-wireless to 2009-01-19
[openwrt.git] / package / mac80211 / patches / 303-rt2x00-Implement-support-for-rt2800usb.patch
1 From 22592b5df5bef2754f56e165ee0828777a95fdfd Mon Sep 17 00:00:00 2001
2 From: Ivo van Doorn <IvDoorn@gmail.com>
3 Date: Sat, 10 Jan 2009 11:05:41 +0100
4 Subject: [PATCH] rt2x00: Implement support for rt2800usb
5
6 Add support for the rt2800usb chipset.
7
8 Includes various patches from Mattias and Felix.
9
10 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
11 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
12 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
13 ---
14 drivers/net/wireless/rt2x00/Kconfig | 14 +
15 drivers/net/wireless/rt2x00/Makefile | 1 +
16 drivers/net/wireless/rt2x00/rt2800usb.c | 2540 +++++++++++++++++++++++++++++++
17 drivers/net/wireless/rt2x00/rt2800usb.h | 1892 +++++++++++++++++++++++
18 drivers/net/wireless/rt2x00/rt2x00.h | 1 +
19 5 files changed, 4448 insertions(+), 0 deletions(-)
20 create mode 100644 drivers/net/wireless/rt2x00/rt2800usb.c
21 create mode 100644 drivers/net/wireless/rt2x00/rt2800usb.h
22
23 --- a/drivers/net/wireless/rt2x00/Makefile
24 +++ b/drivers/net/wireless/rt2x00/Makefile
25 @@ -19,3 +19,4 @@ obj-$(CONFIG_RT61PCI) += rt61pci.o
26 obj-$(CONFIG_RT2800PCI) += rt2800pci.o
27 obj-$(CONFIG_RT2500USB) += rt2500usb.o
28 obj-$(CONFIG_RT73USB) += rt73usb.o
29 +obj-$(CONFIG_RT2800USB) += rt2800usb.o
30 --- /dev/null
31 +++ b/drivers/net/wireless/rt2x00/rt2800usb.c
32 @@ -0,0 +1,2540 @@
33 +/*
34 + Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
35 + <http://rt2x00.serialmonkey.com>
36 +
37 + This program is free software; you can redistribute it and/or modify
38 + it under the terms of the GNU General Public License as published by
39 + the Free Software Foundation; either version 2 of the License, or
40 + (at your option) any later version.
41 +
42 + This program is distributed in the hope that it will be useful,
43 + but WITHOUT ANY WARRANTY; without even the implied warranty of
44 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
45 + GNU General Public License for more details.
46 +
47 + You should have received a copy of the GNU General Public License
48 + along with this program; if not, write to the
49 + Free Software Foundation, Inc.,
50 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
51 + */
52 +
53 +/*
54 + Module: rt2800usb
55 + Abstract: rt2800usb device specific routines.
56 + Supported chipsets: RT2800U.
57 + */
58 +
59 +#include <linux/crc-ccitt.h>
60 +#include <linux/delay.h>
61 +#include <linux/etherdevice.h>
62 +#include <linux/init.h>
63 +#include <linux/kernel.h>
64 +#include <linux/module.h>
65 +#include <linux/usb.h>
66 +
67 +#include "rt2x00.h"
68 +#include "rt2x00usb.h"
69 +#include "rt2800usb.h"
70 +
71 +/*
72 + * Allow hardware encryption to be disabled.
73 + */
74 +static int modparam_nohwcrypt = 0;
75 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
76 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
77 +
78 +/*
79 + * Register access.
80 + * All access to the CSR registers will go through the methods
81 + * rt2x00usb_register_read and rt2x00usb_register_write.
82 + * BBP and RF register require indirect register access,
83 + * and use the CSR registers BBPCSR and RFCSR to achieve this.
84 + * These indirect registers work with busy bits,
85 + * and we will try maximal REGISTER_BUSY_COUNT times to access
86 + * the register while taking a REGISTER_BUSY_DELAY us delay
87 + * between each attampt. When the busy bit is still set at that time,
88 + * the access attempt is considered to have failed,
89 + * and we will print an error.
90 + * The _lock versions must be used if you already hold the csr_mutex
91 + */
92 +#define WAIT_FOR_BBP(__dev, __reg) \
93 + rt2x00usb_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
94 +#define WAIT_FOR_RF(__dev, __reg) \
95 + rt2x00usb_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
96 +#define WAIT_FOR_MCU(__dev, __reg) \
97 + rt2x00usb_regbusy_read((__dev), H2M_MAILBOX_CSR, \
98 + H2M_MAILBOX_CSR_OWNER, (__reg))
99 +
100 +static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
101 + const unsigned int word, const u8 value)
102 +{
103 + u32 reg;
104 +
105 + mutex_lock(&rt2x00dev->csr_mutex);
106 +
107 + /*
108 + * Wait until the BBP becomes available, afterwards we
109 + * can safely write the new data into the register.
110 + */
111 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
112 + reg = 0;
113 + rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
114 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
115 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
116 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
117 +
118 + rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
119 + }
120 +
121 + mutex_unlock(&rt2x00dev->csr_mutex);
122 +}
123 +
124 +static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
125 + const unsigned int word, u8 *value)
126 +{
127 + u32 reg;
128 +
129 + mutex_lock(&rt2x00dev->csr_mutex);
130 +
131 + /*
132 + * Wait until the BBP becomes available, afterwards we
133 + * can safely write the read request into the register.
134 + * After the data has been written, we wait until hardware
135 + * returns the correct value, if at any time the register
136 + * doesn't become available in time, reg will be 0xffffffff
137 + * which means we return 0xff to the caller.
138 + */
139 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
140 + reg = 0;
141 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
142 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
143 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
144 +
145 + rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
146 +
147 + WAIT_FOR_BBP(rt2x00dev, &reg);
148 + }
149 +
150 + *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
151 +
152 + mutex_unlock(&rt2x00dev->csr_mutex);
153 +}
154 +
155 +static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
156 + const unsigned int word, const u32 value)
157 +{
158 + u32 reg;
159 +
160 + if (!word)
161 + return;
162 +
163 + mutex_lock(&rt2x00dev->csr_mutex);
164 +
165 + /*
166 + * Wait until the RF becomes available, afterwards we
167 + * can safely write the new data into the register.
168 + */
169 + if (WAIT_FOR_RF(rt2x00dev, &reg)) {
170 + reg = 0;
171 + rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
172 + rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
173 + rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
174 + rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
175 +
176 + rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
177 + rt2x00_rf_write(rt2x00dev, word, value);
178 + }
179 +
180 + mutex_unlock(&rt2x00dev->csr_mutex);
181 +}
182 +
183 +static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
184 + const u8 command, const u8 token,
185 + const u8 arg0, const u8 arg1)
186 +{
187 + u32 reg;
188 +
189 + mutex_lock(&rt2x00dev->csr_mutex);
190 +
191 + /*
192 + * Wait until the MCU becomes available, afterwards we
193 + * can safely write the new data into the register.
194 + */
195 + if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
196 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
197 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
198 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
199 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
200 + rt2x00usb_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
201 +
202 + reg = 0;
203 + rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
204 + rt2x00usb_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
205 + }
206 +
207 + mutex_unlock(&rt2x00dev->csr_mutex);
208 +}
209 +
210 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
211 +static const struct rt2x00debug rt2800usb_rt2x00debug = {
212 + .owner = THIS_MODULE,
213 + .csr = {
214 + .read = rt2x00usb_register_read,
215 + .write = rt2x00usb_register_write,
216 + .flags = RT2X00DEBUGFS_OFFSET,
217 + .word_base = CSR_REG_BASE,
218 + .word_size = sizeof(u32),
219 + .word_count = CSR_REG_SIZE / sizeof(u32),
220 + },
221 + .eeprom = {
222 + .read = rt2x00_eeprom_read,
223 + .write = rt2x00_eeprom_write,
224 + .word_base = EEPROM_BASE,
225 + .word_size = sizeof(u16),
226 + .word_count = EEPROM_SIZE / sizeof(u16),
227 + },
228 + .bbp = {
229 + .read = rt2800usb_bbp_read,
230 + .write = rt2800usb_bbp_write,
231 + .word_base = BBP_BASE,
232 + .word_size = sizeof(u8),
233 + .word_count = BBP_SIZE / sizeof(u8),
234 + },
235 + .rf = {
236 + .read = rt2x00_rf_read,
237 + .write = rt2800usb_rf_write,
238 + .word_base = RF_BASE,
239 + .word_size = sizeof(u32),
240 + .word_count = RF_SIZE / sizeof(u32),
241 + },
242 +};
243 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
244 +
245 +#ifdef CONFIG_RT2X00_LIB_RFKILL
246 +static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
247 +{
248 + u32 reg;
249 +
250 + rt2x00usb_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
251 + return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
252 +}
253 +#else
254 +#define rt2800usb_rfkill_poll NULL
255 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
256 +
257 +#ifdef CONFIG_RT2X00_LIB_LEDS
258 +static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
259 + enum led_brightness brightness)
260 +{
261 + struct rt2x00_led *led =
262 + container_of(led_cdev, struct rt2x00_led, led_dev);
263 + unsigned int enabled = brightness != LED_OFF;
264 + unsigned int bg_mode =
265 + (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
266 + unsigned int polarity =
267 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
268 + EEPROM_FREQ_LED_POLARITY);
269 + unsigned int ledmode =
270 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
271 + EEPROM_FREQ_LED_MODE);
272 +
273 + if (led->type == LED_TYPE_RADIO) {
274 + rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
275 + enabled ? 0x20 : 0);
276 + } else if (led->type == LED_TYPE_ASSOC) {
277 + rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
278 + enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
279 + } else if (led->type == LED_TYPE_QUALITY) {
280 + /*
281 + * The brightness is divided into 6 levels (0 - 5),
282 + * The specs tell us the following levels:
283 + * 0, 1 ,3, 7, 15, 31
284 + * to determine the level in a simple way we can simply
285 + * work with bitshifting:
286 + * (1 << level) - 1
287 + */
288 + rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
289 + (1 << brightness / (LED_FULL / 6)) - 1,
290 + polarity);
291 + }
292 +}
293 +
294 +static int rt2800usb_blink_set(struct led_classdev *led_cdev,
295 + unsigned long *delay_on,
296 + unsigned long *delay_off)
297 +{
298 + struct rt2x00_led *led =
299 + container_of(led_cdev, struct rt2x00_led, led_dev);
300 + u32 reg;
301 +
302 + rt2x00usb_register_read(led->rt2x00dev, LED_CFG, &reg);
303 + rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
304 + rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
305 + rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
306 + rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
307 + rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
308 + rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
309 + rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
310 + rt2x00usb_register_write(led->rt2x00dev, LED_CFG, reg);
311 +
312 + return 0;
313 +}
314 +
315 +static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
316 + struct rt2x00_led *led,
317 + enum led_type type)
318 +{
319 + led->rt2x00dev = rt2x00dev;
320 + led->type = type;
321 + led->led_dev.brightness_set = rt2800usb_brightness_set;
322 + led->led_dev.blink_set = rt2800usb_blink_set;
323 + led->flags = LED_INITIALIZED;
324 +}
325 +#endif /* CONFIG_RT2X00_LIB_LEDS */
326 +
327 +/*
328 + * Configuration handlers.
329 + */
330 +static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
331 + struct rt2x00lib_crypto *crypto,
332 + struct ieee80211_key_conf *key)
333 +{
334 + u32 offset;
335 + u32 reg;
336 +
337 + offset = MAC_WCID_ATTR_ENTRY(crypto->aid);
338 +
339 + reg = 0;
340 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
341 + !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
342 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_PAIRKEY_MODE,
343 + crypto->cipher);
344 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
345 + (crypto->cmd == SET_KEY) ? crypto->bssidx : 0);
346 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
347 + rt2x00usb_register_write(rt2x00dev, offset, reg);
348 +}
349 +
350 +static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
351 + struct rt2x00lib_crypto *crypto,
352 + struct ieee80211_key_conf *key)
353 +{
354 + struct hw_key_entry key_entry;
355 + struct rt2x00_field32 field;
356 + int timeout;
357 + u32 offset;
358 + u32 mask;
359 + u32 reg;
360 +
361 + if (crypto->cmd == SET_KEY) {
362 + memcpy(key_entry.key, crypto->key,
363 + sizeof(key_entry.key));
364 + memcpy(key_entry.tx_mic, crypto->tx_mic,
365 + sizeof(key_entry.tx_mic));
366 + memcpy(key_entry.rx_mic, crypto->rx_mic,
367 + sizeof(key_entry.rx_mic));
368 +
369 + offset = SHARED_KEY_ENTRY(key->hw_key_idx);
370 + timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
371 + rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
372 + USB_VENDOR_REQUEST_OUT,
373 + offset, &key_entry,
374 + sizeof(key_entry),
375 + timeout);
376 +
377 + /*
378 + * The driver does not support the IV/EIV generation
379 + * in hardware. However it doesn't support the IV/EIV
380 + * inside the ieee80211 frame either, but requires it
381 + * to be provided seperately for the descriptor.
382 + * rt2x00lib will cut the IV/EIV data out of all frames
383 + * given to us by mac80211, but we must tell mac80211
384 + * to generate the IV/EIV data.
385 + */
386 + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
387 + }
388 +
389 + /*
390 + * The cipher types are stored over multiple registers
391 + * starting with SHARED_KEY_MODE_BASE each word will have
392 + * 32 bits and contains the cipher types for 2 modes each.
393 + * Using the correct defines correctly will cause overhead,
394 + * so just calculate the correct offset.
395 + */
396 + mask = key->hw_key_idx % 8;
397 + field.bit_offset = (3 * mask);
398 + field.bit_mask = 0x7 << field.bit_offset;
399 +
400 + offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
401 + rt2x00usb_register_read(rt2x00dev, offset, &reg);
402 + rt2x00_set_field32(&reg, field,
403 + (crypto->cmd == SET_KEY) ? crypto->cipher : 0);
404 + rt2x00usb_register_write(rt2x00dev, offset, reg);
405 +
406 + /*
407 + * Update WCID information
408 + */
409 + rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
410 +
411 + return 0;
412 +}
413 +
414 +static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
415 + struct rt2x00lib_crypto *crypto,
416 + struct ieee80211_key_conf *key)
417 +{
418 + struct hw_key_entry key_entry;
419 + int timeout;
420 + u32 offset;
421 +
422 + /*
423 + * 1 pairwise key is possible per AID, this means that the AID
424 + * equals our hw_key_idx.
425 + */
426 + key->hw_key_idx = crypto->aid;
427 +
428 + if (crypto->cmd == SET_KEY) {
429 + memcpy(key_entry.key, crypto->key,
430 + sizeof(key_entry.key));
431 + memcpy(key_entry.tx_mic, crypto->tx_mic,
432 + sizeof(key_entry.tx_mic));
433 + memcpy(key_entry.rx_mic, crypto->rx_mic,
434 + sizeof(key_entry.rx_mic));
435 +
436 + offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
437 + timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
438 + rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
439 + USB_VENDOR_REQUEST_OUT,
440 + offset, &key_entry,
441 + sizeof(key_entry),
442 + timeout);
443 +
444 + /*
445 + * The driver does not support the IV/EIV generation
446 + * in hardware. However it doesn't support the IV/EIV
447 + * inside the ieee80211 frame either, but requires it
448 + * to be provided seperately for the descriptor.
449 + * rt2x00lib will cut the IV/EIV data out of all frames
450 + * given to us by mac80211, but we must tell mac80211
451 + * to generate the IV/EIV data.
452 + */
453 + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
454 + }
455 +
456 + /*
457 + * Update WCID information
458 + */
459 + rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
460 +
461 + return 0;
462 +}
463 +
464 +static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
465 + const unsigned int filter_flags)
466 +{
467 + u32 reg;
468 +
469 + /*
470 + * Start configuration steps.
471 + * Note that the version error will always be dropped
472 + * and broadcast frames will always be accepted since
473 + * there is no filter for it at this time.
474 + */
475 + rt2x00usb_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
476 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
477 + !(filter_flags & FIF_FCSFAIL));
478 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
479 + !(filter_flags & FIF_PLCPFAIL));
480 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
481 + !(filter_flags & FIF_PROMISC_IN_BSS));
482 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD,
483 + !(filter_flags & FIF_OTHER_BSS));
484 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
485 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
486 + !(filter_flags & FIF_ALLMULTI));
487 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
488 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
489 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
490 + !(filter_flags & FIF_CONTROL));
491 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
492 + !(filter_flags & FIF_CONTROL));
493 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
494 + !(filter_flags & FIF_CONTROL));
495 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
496 + !(filter_flags & FIF_CONTROL));
497 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
498 + !(filter_flags & FIF_CONTROL));
499 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
500 + !(filter_flags & FIF_CONTROL));
501 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
502 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 1);
503 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
504 + !(filter_flags & FIF_CONTROL));
505 + rt2x00usb_register_write(rt2x00dev, RX_FILTER_CFG, reg);
506 +}
507 +
508 +static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
509 + struct rt2x00_intf *intf,
510 + struct rt2x00intf_conf *conf,
511 + const unsigned int flags)
512 +{
513 + unsigned int beacon_base;
514 + u32 reg;
515 +
516 + if (flags & CONFIG_UPDATE_TYPE) {
517 + /*
518 + * Clear current synchronisation setup.
519 + * For the Beacon base registers we only need to clear
520 + * the first byte since that byte contains the VALID and OWNER
521 + * bits which (when set to 0) will invalidate the entire beacon.
522 + */
523 + beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
524 + rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
525 +
526 + /*
527 + * Enable synchronisation.
528 + */
529 + rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
530 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
531 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
532 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
533 + rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
534 + }
535 +
536 + if (flags & CONFIG_UPDATE_MAC) {
537 + reg = le32_to_cpu(conf->mac[1]);
538 + rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
539 + conf->mac[1] = cpu_to_le32(reg);
540 +
541 + rt2x00usb_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
542 + conf->mac, sizeof(conf->mac));
543 + }
544 +
545 + if (flags & CONFIG_UPDATE_BSSID) {
546 + reg = le32_to_cpu(conf->bssid[1]);
547 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
548 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
549 + conf->bssid[1] = cpu_to_le32(reg);
550 +
551 + rt2x00usb_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
552 + conf->bssid, sizeof(conf->bssid));
553 + }
554 +}
555 +
556 +static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
557 + struct rt2x00lib_erp *erp)
558 +{
559 + u32 reg;
560 +
561 + rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
562 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
563 + erp->ack_timeout);
564 + rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
565 +
566 + rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
567 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
568 + !!erp->short_preamble);
569 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
570 + !!erp->short_preamble);
571 + rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
572 +
573 + rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
574 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
575 + erp->cts_protection ? 2 : 0);
576 + rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
577 +
578 + rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE,
579 + erp->basic_rates);
580 + rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE,
581 + erp->basic_rates >> 32);
582 +
583 + rt2x00usb_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
584 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
585 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
586 + rt2x00usb_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
587 +
588 + rt2x00usb_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
589 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
590 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
591 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
592 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
593 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
594 + rt2x00usb_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
595 +}
596 +
597 +static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
598 + struct antenna_setup *ant)
599 +{
600 + u16 eeprom;
601 + u8 r1;
602 + u8 r3;
603 +
604 + /*
605 + * FIXME: Use requested antenna configuration.
606 + */
607 +
608 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
609 +
610 + rt2800usb_bbp_read(rt2x00dev, 1, &r1);
611 + rt2800usb_bbp_read(rt2x00dev, 3, &r3);
612 +
613 + /*
614 + * Configure the TX antenna.
615 + */
616 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
617 + case 1:
618 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
619 + break;
620 + case 2:
621 + case 3:
622 + /* Do nothing */
623 + break;
624 + }
625 +
626 + /*
627 + * Configure the RX antenna.
628 + */
629 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
630 + case 1:
631 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
632 + break;
633 + case 2:
634 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
635 + break;
636 + case 3:
637 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
638 + break;
639 + }
640 +
641 + rt2800usb_bbp_write(rt2x00dev, 3, r3);
642 + rt2800usb_bbp_write(rt2x00dev, 1, r1);
643 +}
644 +
645 +static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
646 + struct rt2x00lib_conf *libconf)
647 +{
648 + u16 eeprom;
649 + short lna_gain;
650 +
651 + if (libconf->rf.channel <= 14) {
652 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
653 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
654 + } else if (libconf->rf.channel <= 64) {
655 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
656 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
657 + } else if (libconf->rf.channel <= 128) {
658 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
659 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
660 + } else {
661 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
662 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
663 + }
664 +
665 + rt2x00dev->lna_gain = lna_gain;
666 +}
667 +
668 +static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
669 + struct rf_channel *rf,
670 + struct channel_info *info)
671 +{
672 + u32 reg;
673 + unsigned int tx_pin;
674 + u16 eeprom;
675 +
676 + tx_pin = 0;
677 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
678 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
679 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
680 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
681 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
682 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
683 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
684 +
685 + rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
686 +
687 + /*
688 + * Determine antenna settings from EEPROM
689 + */
690 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
691 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
692 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
693 + /* Turn off unused PA or LNA when only 1T or 1R */
694 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 0);
695 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 0);
696 + }
697 +
698 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
699 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
700 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
701 + /* Turn off unused PA or LNA when only 1T or 1R */
702 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 0);
703 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 0);
704 + } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
705 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
706 +
707 + if (rf->channel > 14) {
708 + /*
709 + * When TX power is below 0, we should increase it by 7 to
710 + * make it a positive value (Minumum value is -7).
711 + * However this means that values between 0 and 7 have
712 + * double meaning, and we should set a 7DBm boost flag.
713 + */
714 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
715 + (info->tx_power1 >= 0));
716 +
717 + if (info->tx_power1 < 0)
718 + info->tx_power1 += 7;
719 +
720 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
721 + TXPOWER_A_TO_DEV(info->tx_power1));
722 +
723 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
724 + (info->tx_power2 >= 0));
725 +
726 + if (info->tx_power2 < 0)
727 + info->tx_power2 += 7;
728 +
729 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
730 + TXPOWER_A_TO_DEV(info->tx_power2));
731 +
732 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
733 + } else {
734 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
735 + TXPOWER_G_TO_DEV(info->tx_power1));
736 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
737 + TXPOWER_G_TO_DEV(info->tx_power2));
738 +
739 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
740 + }
741 +
742 + rt2x00_set_field32(&rf->rf4, RF4_BW40,
743 + test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
744 +
745 + rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
746 + rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
747 + rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
748 + rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
749 +
750 + udelay(200);
751 +
752 + rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
753 + rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
754 + rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
755 + rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
756 +
757 + udelay(200);
758 +
759 + rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
760 + rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
761 + rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
762 + rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
763 +
764 + /*
765 + * Change BBP settings
766 + */
767 + rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
768 + rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
769 + rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
770 + rt2800usb_bbp_write(rt2x00dev, 86, 0);
771 +
772 + if (rf->channel <= 14) {
773 + if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
774 + rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
775 + rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
776 + } else {
777 + rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
778 + rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
779 + }
780 +
781 + rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
782 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 0);
783 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 1);
784 + rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
785 + } else {
786 + rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
787 +
788 + if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
789 + rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
790 + else
791 + rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
792 +
793 + rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
794 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 1);
795 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 0);
796 + rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
797 + }
798 +
799 + rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
800 +
801 + msleep(1);
802 +}
803 +
804 +static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
805 + const int txpower)
806 +{
807 + u32 reg;
808 + u32 value = TXPOWER_G_TO_DEV(txpower);
809 + u8 r1;
810 +
811 + rt2800usb_bbp_read(rt2x00dev, 1, &r1);
812 + rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
813 + rt2800usb_bbp_write(rt2x00dev, 1, r1);
814 +
815 + rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
816 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
817 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
818 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
819 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
820 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
821 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
822 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
823 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
824 + rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
825 +
826 + rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
827 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
828 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
829 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
830 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
831 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
832 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
833 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
834 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
835 + rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
836 +
837 + rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
838 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
839 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
840 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
841 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
842 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
843 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
844 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
845 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
846 + rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
847 +
848 + rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
849 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
850 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
851 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
852 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
853 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
854 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
855 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
856 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
857 + rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
858 +
859 + rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
860 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
861 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
862 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
863 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
864 + rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
865 +}
866 +
867 +static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
868 + struct rt2x00lib_conf *libconf)
869 +{
870 + u32 reg;
871 +
872 + rt2x00usb_register_read(rt2x00dev, TX_RTY_CFG, &reg);
873 + rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
874 + libconf->conf->short_frame_max_tx_count);
875 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
876 + libconf->conf->long_frame_max_tx_count);
877 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
878 + rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
879 + rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
880 + rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
881 + rt2x00usb_register_write(rt2x00dev, TX_RTY_CFG, reg);
882 +}
883 +
884 +static void rt2800usb_config_duration(struct rt2x00_dev *rt2x00dev,
885 + struct rt2x00lib_conf *libconf)
886 +{
887 + u32 reg;
888 +
889 + rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
890 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
891 + libconf->conf->beacon_int * 16);
892 + rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
893 +}
894 +
895 +static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
896 + struct rt2x00lib_conf *libconf,
897 + const unsigned int flags)
898 +{
899 + /* Always recalculate LNA gain before changing configuration */
900 + rt2800usb_config_lna_gain(rt2x00dev, libconf);
901 +
902 + if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
903 + rt2800usb_config_channel(rt2x00dev, &libconf->rf,
904 + &libconf->channel);
905 + if (flags & IEEE80211_CONF_CHANGE_POWER)
906 + rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
907 + if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
908 + rt2800usb_config_retry_limit(rt2x00dev, libconf);
909 + if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
910 + rt2800usb_config_duration(rt2x00dev, libconf);
911 +}
912 +
913 +/*
914 + * Link tuning
915 + */
916 +static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
917 + struct link_qual *qual)
918 +{
919 + u32 reg;
920 +
921 + /*
922 + * Update FCS error count from register.
923 + */
924 + rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
925 + qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
926 +
927 + /*
928 + * Update False CCA count from register.
929 + */
930 + rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
931 + qual->false_cca = rt2x00_get_field32(reg, RX_STA_CNT1_FALSE_CCA);
932 +}
933 +
934 +static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
935 +{
936 + if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
937 + return 0x2e + rt2x00dev->lna_gain;
938 +
939 + if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
940 + return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
941 + else
942 + return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
943 +}
944 +
945 +static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
946 + struct link_qual *qual, u8 vgc_level)
947 +{
948 + if (qual->vgc_level != vgc_level) {
949 + rt2800usb_bbp_write(rt2x00dev, 66, vgc_level);
950 + qual->vgc_level = vgc_level;
951 + qual->vgc_level_reg = vgc_level;
952 + }
953 +}
954 +
955 +static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
956 + struct link_qual *qual)
957 +{
958 + rt2800usb_set_vgc(rt2x00dev, qual,
959 + rt2800usb_get_default_vgc(rt2x00dev));
960 +}
961 +
962 +static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
963 + struct link_qual *qual, const u32 count)
964 +{
965 + if (rt2x00_rev(&rt2x00dev->chip) == RT2870_VERSION_C)
966 + return;
967 +
968 + /*
969 + * When RSSI is better then -80 increase VGC level with 0x10
970 + */
971 + rt2800usb_set_vgc(rt2x00dev, qual,
972 + rt2800usb_get_default_vgc(rt2x00dev) +
973 + ((qual->rssi > -80) * 0x10));
974 +}
975 +
976 +/*
977 + * Firmware functions
978 + */
979 +static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
980 +{
981 + return FIRMWARE_RT2870;
982 +}
983 +
984 +static u16 rt2800usb_get_firmware_crc(const void *data, const size_t len)
985 +{
986 + u16 crc;
987 +
988 + /*
989 + * Use the crc ccitt algorithm.
990 + * This will return the same value as the legacy driver which
991 + * used bit ordering reversion on the both the firmware bytes
992 + * before input input as well as on the final output.
993 + * Obviously using crc ccitt directly is much more efficient.
994 + * The last 2 bytes in the firmware array are the crc checksum itself,
995 + * this means that we should never pass those 2 bytes to the crc
996 + * algorithm.
997 + */
998 + crc = crc_ccitt(~0, data, len - 2);
999 +
1000 + /*
1001 + * There is a small difference between the crc-itu-t + bitrev and
1002 + * the crc-ccitt crc calculation. In the latter method the 2 bytes
1003 + * will be swapped, use swab16 to convert the crc to the correct
1004 + * value.
1005 + */
1006 + return swab16(crc);
1007 +}
1008 +
1009 +static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1010 + const void *data, const size_t len)
1011 +{
1012 + unsigned int i;
1013 + int status;
1014 + u32 reg;
1015 +
1016 + /*
1017 + * Wait for stable hardware.
1018 + */
1019 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1020 + rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1021 + if (reg && reg != ~0)
1022 + break;
1023 + msleep(1);
1024 + }
1025 +
1026 + if (i == REGISTER_BUSY_COUNT) {
1027 + ERROR(rt2x00dev, "Unstable hardware.\n");
1028 + return -EBUSY;
1029 + }
1030 +
1031 + /*
1032 + * Write firmware to device.
1033 + */
1034 + rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1035 + USB_VENDOR_REQUEST_OUT,
1036 + FIRMWARE_IMAGE_BASE,
1037 + data, len,
1038 + REGISTER_TIMEOUT32(len));
1039 +
1040 + rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1041 + rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1042 +
1043 + /*
1044 + * Send firmware request to device to load firmware,
1045 + * we need to specify a long timeout time.
1046 + */
1047 + status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1048 + 0, USB_MODE_FIRMWARE,
1049 + REGISTER_TIMEOUT_FIRMWARE);
1050 + if (status < 0) {
1051 + ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1052 + return status;
1053 + }
1054 +
1055 + /*
1056 + * Wait for device to stabilize.
1057 + */
1058 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1059 + rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1060 + if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1061 + break;
1062 + msleep(1);
1063 + }
1064 +
1065 + if (i == REGISTER_BUSY_COUNT) {
1066 + ERROR(rt2x00dev, "PBF system register not ready.\n");
1067 + return -EBUSY;
1068 + }
1069 +
1070 + /*
1071 + * Initialize firmware.
1072 + */
1073 + rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1074 + rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1075 + msleep(1);
1076 +
1077 + return 0;
1078 +}
1079 +
1080 +/*
1081 + * Initialization functions.
1082 + */
1083 +static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1084 +{
1085 + u32 reg;
1086 + unsigned int i;
1087 +
1088 + /*
1089 + * Wait untill BBP and RF are ready.
1090 + */
1091 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1092 + rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1093 + if (reg && reg != ~0)
1094 + break;
1095 + msleep(1);
1096 + }
1097 +
1098 + if (i == REGISTER_BUSY_COUNT) {
1099 + ERROR(rt2x00dev, "Unstable hardware.\n");
1100 + return -EBUSY;
1101 + }
1102 +
1103 + rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1104 + rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1105 +
1106 + rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1107 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1108 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1109 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1110 +
1111 + rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1112 +
1113 + rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1114 + USB_MODE_RESET, REGISTER_TIMEOUT);
1115 +
1116 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1117 +
1118 + rt2x00usb_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1119 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1120 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1121 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1122 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1123 + rt2x00usb_register_write(rt2x00dev, BCN_OFFSET0, reg);
1124 +
1125 + rt2x00usb_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1126 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1127 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1128 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1129 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1130 + rt2x00usb_register_write(rt2x00dev, BCN_OFFSET1, reg);
1131 +
1132 + rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1133 + rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1134 +
1135 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1136 +
1137 + rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1138 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1139 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1140 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1141 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1142 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1143 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1144 + rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1145 +
1146 + rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00040a06);
1147 + rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1148 +
1149 + rt2x00usb_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1150 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1151 + rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1152 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1153 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1154 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1155 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1156 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1157 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1158 + rt2x00usb_register_write(rt2x00dev, TX_LINK_CFG, reg);
1159 +
1160 + rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1161 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1162 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1163 + rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1164 +
1165 + rt2x00usb_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1166 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1167 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1168 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1169 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1170 + rt2x00usb_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1171 +
1172 + rt2x00usb_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1173 +
1174 + rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1175 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1176 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1177 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1178 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1179 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1180 + rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1181 +
1182 + rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1183 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1184 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1185 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1186 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1187 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1188 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1189 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1190 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1191 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1192 + rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1193 +
1194 + rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1195 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1196 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1197 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1198 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1199 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1200 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1201 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1202 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1203 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1204 + rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1205 +
1206 + rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1207 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1208 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1209 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1210 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1211 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1212 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1213 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1214 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1215 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1216 + rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1217 +
1218 + rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1219 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1220 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1221 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1222 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1223 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1224 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1225 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1226 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1227 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1228 + rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1229 +
1230 + rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1231 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1232 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1233 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1234 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1235 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1236 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1237 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1238 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1239 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1240 + rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1241 +
1242 + rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1243 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1244 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1245 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1246 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1247 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1248 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1249 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1250 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1251 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1252 + rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1253 +
1254 + rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1255 +
1256 + rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1257 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1258 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1259 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1260 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1261 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1262 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1263 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1264 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1265 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1266 + rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1267 +
1268 + rt2x00usb_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1269 + rt2x00usb_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1270 +
1271 + rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1272 + rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1273 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1274 + rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
1275 +
1276 + rt2x00usb_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1277 + rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1278 +
1279 + /*
1280 + * ASIC will keep garbage value after boot, clear encryption keys.
1281 + */
1282 + for (i = 0; i < 254; i++) {
1283 + u32 wcid[2] = { 0xffffffff, 0x0000ffff };
1284 + rt2x00usb_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1285 + wcid, sizeof(wcid));
1286 + }
1287 +
1288 + for (i = 0; i < 4; i++)
1289 + rt2x00usb_register_write(rt2x00dev,
1290 + SHARED_KEY_MODE_ENTRY(i), 0);
1291 +
1292 + for (i = 0; i < 256; i++)
1293 + rt2x00usb_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1294 +
1295 + /*
1296 + * Clear all beacons
1297 + * For the Beacon base registers we only need to clear
1298 + * the first byte since that byte contains the VALID and OWNER
1299 + * bits which (when set to 0) will invalidate the entire beacon.
1300 + */
1301 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1302 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1303 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1304 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1305 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1306 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1307 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1308 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1309 +
1310 + rt2x00usb_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1311 + rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1312 + rt2x00usb_register_write(rt2x00dev, USB_CYC_CFG, reg);
1313 +
1314 + rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1315 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1316 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1317 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1318 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1319 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1320 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1321 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1322 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1323 + rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1324 +
1325 + rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1326 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1327 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1328 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1329 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1330 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1331 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1332 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1333 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1334 + rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1335 +
1336 + rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1337 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1338 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1339 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 10);
1340 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 11);
1341 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 12);
1342 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 13);
1343 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 14);
1344 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 15);
1345 + rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1346 +
1347 + rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1348 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1349 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1350 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1351 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1352 + rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1353 +
1354 + /*
1355 + * We must clear the error counters.
1356 + * These registers are cleared on read,
1357 + * so we may pass a useless variable to store the value.
1358 + */
1359 + rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1360 + rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1361 + rt2x00usb_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1362 + rt2x00usb_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1363 + rt2x00usb_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1364 + rt2x00usb_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1365 +
1366 + return 0;
1367 +}
1368 +
1369 +static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1370 +{
1371 + unsigned int i;
1372 + u32 reg;
1373 +
1374 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1375 + rt2x00usb_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1376 + if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1377 + return 0;
1378 +
1379 + udelay(REGISTER_BUSY_DELAY);
1380 + }
1381 +
1382 + ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1383 + return -EACCES;
1384 +}
1385 +
1386 +static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1387 +{
1388 + unsigned int i;
1389 + u8 value;
1390 +
1391 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1392 + rt2800usb_bbp_read(rt2x00dev, 0, &value);
1393 + if ((value != 0xff) && (value != 0x00))
1394 + return 0;
1395 + udelay(REGISTER_BUSY_DELAY);
1396 + }
1397 +
1398 + ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1399 + return -EACCES;
1400 +}
1401 +
1402 +static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1403 +{
1404 + unsigned int i;
1405 + u16 eeprom;
1406 + u8 reg_id;
1407 + u8 value;
1408 +
1409 + if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1410 + rt2800usb_wait_bbp_ready(rt2x00dev)))
1411 + return -EACCES;
1412 +
1413 + rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
1414 + rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
1415 + rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
1416 + rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1417 + rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
1418 + rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
1419 + rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
1420 + rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
1421 + rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1422 + rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
1423 + rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
1424 + rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
1425 + rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1426 +
1427 + if (rt2x00_rev(&rt2x00dev->chip) == RT2870_VERSION_C) {
1428 + rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
1429 + rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
1430 + }
1431 +
1432 + if (rt2x00_rev(&rt2x00dev->chip) != RT2870_VERSION_D)
1433 + rt2800usb_bbp_write(rt2x00dev, 84, 0x19);
1434 +
1435 + for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1436 + rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1437 +
1438 + if (eeprom != 0xffff && eeprom != 0x0000) {
1439 + reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1440 + value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1441 + rt2800usb_bbp_write(rt2x00dev, reg_id, value);
1442 + }
1443 + }
1444 +
1445 + return 0;
1446 +}
1447 +
1448 +/*
1449 + * Device state switch handlers.
1450 + */
1451 +static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1452 + enum dev_state state)
1453 +{
1454 + u32 reg;
1455 +
1456 + rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1457 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1458 + (state == STATE_RADIO_RX_ON) ||
1459 + (state == STATE_RADIO_RX_ON_LINK));
1460 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1461 +}
1462 +
1463 +static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1464 +{
1465 + unsigned int i;
1466 + u32 reg;
1467 +
1468 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1469 + rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1470 + if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1471 + !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1472 + return 0;
1473 +
1474 + msleep(1);
1475 + }
1476 +
1477 + ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1478 + return -EACCES;
1479 +}
1480 +
1481 +static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1482 +{
1483 + u32 reg;
1484 + u16 word;
1485 +
1486 + /*
1487 + * Initialize all registers.
1488 + */
1489 + if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
1490 + rt2800usb_init_registers(rt2x00dev) ||
1491 + rt2800usb_init_bbp(rt2x00dev)))
1492 + return -EIO;
1493 +
1494 + rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1495 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1496 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1497 +
1498 + udelay(50);
1499 +
1500 + rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1501 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1502 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1503 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1504 + rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1505 +
1506 +
1507 + rt2x00usb_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1508 + rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1509 + /* Don't use bulk in aggregation when working with USB 1.1 */
1510 + rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
1511 + (rt2x00dev->rx->usb_maxpacket == 512));
1512 + rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
1513 + /* FIXME: Calculate this value based on Aggregation defines */
1514 + rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT, 21);
1515 + rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1516 + rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1517 + rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg);
1518 +
1519 + rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1520 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1521 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1522 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1523 +
1524 + /*
1525 + * Send signal to firmware during boot time.
1526 + */
1527 + rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1528 +
1529 + /*
1530 + * Initialize LED control
1531 + */
1532 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1533 + rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1534 + word & 0xff, (word >> 8) & 0xff);
1535 +
1536 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1537 + rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1538 + word & 0xff, (word >> 8) & 0xff);
1539 +
1540 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1541 + rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1542 + word & 0xff, (word >> 8) & 0xff);
1543 +
1544 + return 0;
1545 +}
1546 +
1547 +static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1548 +{
1549 + u32 reg;
1550 +
1551 + rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1552 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1553 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1554 + rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1555 +
1556 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1557 + rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1558 + rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, 0);
1559 +
1560 + /* Wait for DMA, ignore error */
1561 + rt2800usb_wait_wpdma_ready(rt2x00dev);
1562 +
1563 + rt2x00usb_disable_radio(rt2x00dev);
1564 +}
1565 +
1566 +static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1567 + enum dev_state state)
1568 +{
1569 + rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1570 +
1571 + if (state == STATE_AWAKE)
1572 + rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1573 + else
1574 + rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1575 +
1576 + return 0;
1577 +}
1578 +
1579 +static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1580 + enum dev_state state)
1581 +{
1582 + int retval = 0;
1583 +
1584 + switch (state) {
1585 + case STATE_RADIO_ON:
1586 + /*
1587 + * Before the radio can be enabled, the device first has
1588 + * to be woken up. After that it needs a bit of time
1589 + * to be fully awake and the radio can be enabled.
1590 + */
1591 + rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
1592 + msleep(1);
1593 + retval = rt2800usb_enable_radio(rt2x00dev);
1594 + break;
1595 + case STATE_RADIO_OFF:
1596 + /*
1597 + * After the radio has been disablee, the device should
1598 + * be put to sleep for powersaving.
1599 + */
1600 + rt2800usb_disable_radio(rt2x00dev);
1601 + rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
1602 + break;
1603 + case STATE_RADIO_RX_ON:
1604 + case STATE_RADIO_RX_ON_LINK:
1605 + case STATE_RADIO_RX_OFF:
1606 + case STATE_RADIO_RX_OFF_LINK:
1607 + rt2800usb_toggle_rx(rt2x00dev, state);
1608 + break;
1609 + case STATE_RADIO_IRQ_ON:
1610 + case STATE_RADIO_IRQ_OFF:
1611 + /* No support, but no error either */
1612 + break;
1613 + case STATE_DEEP_SLEEP:
1614 + case STATE_SLEEP:
1615 + case STATE_STANDBY:
1616 + case STATE_AWAKE:
1617 + retval = rt2800usb_set_state(rt2x00dev, state);
1618 + break;
1619 + default:
1620 + retval = -ENOTSUPP;
1621 + break;
1622 + }
1623 +
1624 + if (unlikely(retval))
1625 + ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1626 + state, retval);
1627 +
1628 + return retval;
1629 +}
1630 +
1631 +/*
1632 + * TX descriptor initialization
1633 + */
1634 +static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1635 + struct sk_buff *skb,
1636 + struct txentry_desc *txdesc)
1637 +{
1638 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1639 + __le32 *txd = skbdesc->desc;
1640 + __le32 *txwi = txd + TXD_DESC_SIZE;
1641 + u32 word;
1642 +
1643 + /*
1644 + * Initialize TX Info descriptor
1645 + */
1646 + rt2x00_desc_read(txwi, 0, &word);
1647 + rt2x00_set_field32(&word, TXWI_W0_FRAG,
1648 + test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags) ||
1649 + test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1650 + rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1651 + rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1652 + rt2x00_set_field32(&word, TXWI_W0_TS,
1653 + test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1654 + rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1655 + test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1656 + rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1657 + rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1658 + rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1659 + rt2x00_set_field32(&word, TXWI_W0_BW,
1660 + test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1661 + rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1662 + test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1663 + rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1664 + rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1665 + rt2x00_desc_write(txwi, 0, word);
1666 +
1667 + rt2x00_desc_read(txwi, 1, &word);
1668 + rt2x00_set_field32(&word, TXWI_W1_ACK,
1669 + test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1670 + rt2x00_set_field32(&word, TXWI_W1_NSEQ,
1671 + test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1672 + rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
1673 + rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 0xff);
1674 + rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
1675 + rt2x00_set_field32(&word, TXWI_W1_PACKETID,
1676 + skbdesc->entry->entry_idx);
1677 + rt2x00_desc_write(txwi, 1, word);
1678 +
1679 + if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1680 + _rt2x00_desc_write(txwi, 2, skbdesc->iv[0]);
1681 + _rt2x00_desc_write(txwi, 3, skbdesc->iv[1]);
1682 + }
1683 +
1684 + /*
1685 + * Initialize TX descriptor
1686 + */
1687 + rt2x00_desc_read(txd, 0, &word);
1688 + rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
1689 + rt2x00_desc_write(txd, 0, word);
1690 +
1691 + rt2x00_desc_read(txd, 1, &word);
1692 + rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
1693 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 1);
1694 + rt2x00_set_field32(&word, TXD_W1_BURST,
1695 + test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1696 + rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
1697 + rt2x00dev->hw->extra_tx_headroom);
1698 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC0,
1699 + !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1700 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
1701 + rt2x00_desc_write(txd, 1, word);
1702 +
1703 + rt2x00_desc_read(txd, 2, &word);
1704 + rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
1705 + skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
1706 + rt2x00_desc_write(txd, 2, word);
1707 +
1708 + rt2x00_desc_read(txd, 3, &word);
1709 + rt2x00_set_field32(&word, TXD_W3_WIV, 1);
1710 + rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
1711 + rt2x00_desc_write(txd, 3, word);
1712 +}
1713 +
1714 +/*
1715 + * TX data initialization
1716 + */
1717 +static void rt2800usb_write_beacon(struct queue_entry *entry)
1718 +{
1719 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1720 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1721 + unsigned int beacon_base;
1722 + u32 reg;
1723 +
1724 + /*
1725 + * Add the descriptor in front of the skb.
1726 + */
1727 + skb_push(entry->skb, entry->queue->desc_size);
1728 + memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1729 + skbdesc->desc = entry->skb->data;
1730 +
1731 + /*
1732 + * Disable beaconing while we are reloading the beacon data,
1733 + * otherwise we might be sending out invalid data.
1734 + */
1735 + rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1736 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1737 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1738 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1739 + rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1740 +
1741 + /*
1742 + * Write entire beacon with descriptor to register.
1743 + */
1744 + beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1745 + rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1746 + USB_VENDOR_REQUEST_OUT, beacon_base,
1747 + entry->skb->data, entry->skb->len,
1748 + REGISTER_TIMEOUT32(entry->skb->len));
1749 +
1750 + /*
1751 + * Clean up the beacon skb.
1752 + */
1753 + dev_kfree_skb(entry->skb);
1754 + entry->skb = NULL;
1755 +}
1756 +
1757 +static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
1758 +{
1759 + int length;
1760 +
1761 + /*
1762 + * The length _must_ be a multiple of 4,
1763 + * but it must _not_ be a multiple of the USB packet size.
1764 + */
1765 + length = roundup(entry->skb->len, 4);
1766 + length += (4 * !(length % entry->queue->usb_maxpacket));
1767 +
1768 + return length;
1769 +}
1770 +
1771 +static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1772 + const enum data_queue_qid queue)
1773 +{
1774 + u32 reg;
1775 +
1776 + if (queue != QID_BEACON) {
1777 + rt2x00usb_kick_tx_queue(rt2x00dev, queue);
1778 + return;
1779 + }
1780 +
1781 + rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1782 + if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
1783 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1784 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
1785 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1786 + rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1787 + }
1788 +}
1789 +
1790 +/*
1791 + * RX control handlers
1792 + */
1793 +static void rt2800usb_fill_rxdone(struct queue_entry *entry,
1794 + struct rxdone_entry_desc *rxdesc)
1795 +{
1796 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1797 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1798 + __le32 *rxd = (__le32 *)entry->skb->data;
1799 + __le32 *rxwi = (__le32 *)(entry->skb->data + skbdesc->desc_len);
1800 + u32 rxd0;
1801 + u32 rxwi0;
1802 + u32 rxwi1;
1803 + u32 rxwi2;
1804 + u32 rxwi3;
1805 +
1806 + /*
1807 + * Copy descriptor to the skbdesc->desc buffer, making it safe from
1808 + * moving of frame data in rt2x00usb.
1809 + */
1810 + memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
1811 + rxd = (__le32 *)skbdesc->desc;
1812 +
1813 + /*
1814 + * It is now safe to read the descriptor on all architectures.
1815 + */
1816 + rt2x00_desc_read(rxd, 0, &rxd0);
1817 + rt2x00_desc_read(rxwi, 0, &rxwi0);
1818 + rt2x00_desc_read(rxwi, 1, &rxwi1);
1819 + rt2x00_desc_read(rxwi, 2, &rxwi2);
1820 + rt2x00_desc_read(rxwi, 3, &rxwi3);
1821 +
1822 + if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
1823 + rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1824 +
1825 + if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1826 + /*
1827 + * Unfortunately we don't know the cipher type used during
1828 + * decryption. This prevents us from correct providing
1829 + * correct statistics through debugfs.
1830 + */
1831 + rxdesc->cipher = CIPHER_NONE;
1832 + rxdesc->cipher_status =
1833 + rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
1834 + }
1835 +
1836 + if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) {
1837 + /*
1838 + * Hardware has stripped IV/EIV data from 802.11 frame during
1839 + * decryption. Unfortunately the descriptor doesn't contain
1840 + * any fields with the EIV/IV data either, so they can't
1841 + * be restored by rt2x00lib.
1842 + */
1843 + rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1844 +
1845 + if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1846 + rxdesc->flags |= RX_FLAG_DECRYPTED;
1847 + else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1848 + rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1849 + }
1850 +
1851 + if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
1852 + rxdesc->dev_flags |= RXDONE_MY_BSS;
1853 +
1854 + if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
1855 + rxdesc->flags |= RX_FLAG_SHORT_GI;
1856 +
1857 + if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
1858 + rxdesc->flags |= RX_FLAG_40MHZ;
1859 +
1860 + /*
1861 + * Detect RX rate, always use MCS as signal type.
1862 + */
1863 + rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
1864 + rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
1865 + rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
1866 +
1867 + /*
1868 + * Mask of 0x8 bit to remove the short preamble flag.
1869 + */
1870 + if (rxdesc->dev_flags == RATE_MODE_CCK)
1871 + rxdesc->signal &= ~0x8;
1872 +
1873 + rxdesc->rssi =
1874 + (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
1875 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1) +
1876 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI2)) / 3;
1877 +
1878 + rxdesc->noise =
1879 + (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
1880 + rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
1881 +
1882 + rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
1883 +
1884 + /*
1885 + * Remove TXWI descriptor from start of buffer.
1886 + */
1887 + skb_pull(entry->skb, TXWI_DESC_SIZE + skbdesc->desc_len);
1888 + skb_trim(entry->skb, rxdesc->size);
1889 +}
1890 +
1891 +/*
1892 + * Device probe functions.
1893 + */
1894 +static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1895 +{
1896 + u16 word;
1897 + u8 *mac;
1898 + u8 default_lna_gain;
1899 +
1900 + rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1901 +
1902 + /*
1903 + * Start validation of the data that has been read.
1904 + */
1905 + mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1906 + if (!is_valid_ether_addr(mac)) {
1907 + DECLARE_MAC_BUF(macbuf);
1908 +
1909 + random_ether_addr(mac);
1910 + EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1911 + }
1912 +
1913 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1914 + if (word == 0xffff) {
1915 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1916 + rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
1917 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
1918 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1919 + EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1920 + }
1921 +
1922 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1923 + if (word != 0) {
1924 + /* NIC configuration must always be 0. */
1925 + word = 0;
1926 + rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1927 + EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1928 + }
1929 +
1930 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1931 + if ((word & 0x00ff) == 0x00ff) {
1932 + rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1933 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
1934 + LED_MODE_TXRX_ACTIVITY);
1935 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
1936 + rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1937 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
1938 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
1939 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
1940 + EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1941 + }
1942 +
1943 + /*
1944 + * During the LNA validation we are going to use
1945 + * lna0 as correct value. Note that EEPROM_LNA
1946 + * is never validated.
1947 + */
1948 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
1949 + default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
1950 +
1951 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
1952 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
1953 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
1954 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
1955 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
1956 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
1957 +
1958 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
1959 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
1960 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
1961 + if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
1962 + rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
1963 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
1964 + default_lna_gain);
1965 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
1966 +
1967 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
1968 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
1969 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
1970 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
1971 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
1972 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
1973 +
1974 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
1975 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
1976 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
1977 + if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
1978 + rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
1979 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
1980 + default_lna_gain);
1981 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
1982 +
1983 + return 0;
1984 +}
1985 +
1986 +static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1987 +{
1988 + u32 reg;
1989 + u16 rev;
1990 + u16 value;
1991 + u16 eeprom;
1992 +
1993 + /*
1994 + * Read EEPROM word for configuration.
1995 + */
1996 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1997 +
1998 + /*
1999 + * Identify RF chipset.
2000 + */
2001 + value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2002 + rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
2003 + rev = rt2x00_get_field32(reg, MAC_CSR0_ASIC_REV);
2004 + rt2x00_set_chip(rt2x00dev, RT2870, value, rev);
2005 +
2006 + /*
2007 + * The check for rt2860 is not a typo, some rt2870 hardware
2008 + * identifies itself as rt2860 in the CSR register.
2009 + */
2010 + if ((rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2860) &&
2011 + (rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2870)) {
2012 + ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2013 + return -ENODEV;
2014 + }
2015 +
2016 + if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2017 + !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2018 + !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2019 + !rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2020 + ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2021 + return -ENODEV;
2022 + }
2023 +
2024 + /*
2025 + * Read frequency offset and RF programming sequence.
2026 + */
2027 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2028 + rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2029 +
2030 + /*
2031 + * Read external LNA informations.
2032 + */
2033 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2034 +
2035 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2036 + __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2037 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2038 + __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2039 +
2040 + /*
2041 + * Detect if this device has an hardware controlled radio.
2042 + */
2043 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2044 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2045 + __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2046 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2047 +
2048 + /*
2049 + * Store led settings, for correct led behaviour.
2050 + */
2051 +#ifdef CONFIG_RT2X00_LIB_LEDS
2052 + rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2053 + rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2054 + rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2055 +
2056 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
2057 + &rt2x00dev->led_mcu_reg);
2058 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2059 +
2060 + return 0;
2061 +}
2062 +
2063 +/*
2064 + * RF value list for rt2870
2065 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2066 + */
2067 +static const struct rf_channel rf_vals[] = {
2068 + { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2069 + { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2070 + { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2071 + { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2072 + { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2073 + { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2074 + { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2075 + { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2076 + { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2077 + { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2078 + { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2079 + { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2080 + { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2081 + { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2082 +
2083 + /* 802.11 UNI / HyperLan 2 */
2084 + { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2085 + { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2086 + { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2087 + { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2088 + { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2089 + { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2090 + { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2091 + { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2092 + { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2093 + { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2094 + { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2095 + { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2096 +
2097 + /* 802.11 HyperLan 2 */
2098 + { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2099 + { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2100 + { 104, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed1a3 },
2101 + { 108, 0x18402ecc, 0x184c0a32, 0x18578a55, 0x180ed193 },
2102 + { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2103 + { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2104 + { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2105 + { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2106 + { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2107 + { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2108 + { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2109 + { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2110 + { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2111 + { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2112 + { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2113 + { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2114 +
2115 + /* 802.11 UNII */
2116 + { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2117 + { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2118 + { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2119 + { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2120 + { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2121 + { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2122 + { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2123 +
2124 + /* 802.11 Japan */
2125 + { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2126 + { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2127 + { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2128 + { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2129 + { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2130 + { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2131 + { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2132 +};
2133 +
2134 +static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2135 +{
2136 + struct hw_mode_spec *spec = &rt2x00dev->spec;
2137 + struct channel_info *info;
2138 + char *tx_power1;
2139 + char *tx_power2;
2140 + unsigned int i;
2141 +
2142 + /*
2143 + * Initialize all hw fields.
2144 + */
2145 + rt2x00dev->hw->flags =
2146 + IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2147 + IEEE80211_HW_SIGNAL_DBM;
2148 + rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE + TXINFO_DESC_SIZE;
2149 +
2150 + SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2151 + SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2152 + rt2x00_eeprom_addr(rt2x00dev,
2153 + EEPROM_MAC_ADDR_0));
2154 +
2155 + /*
2156 + * Initialize HT information.
2157 + */
2158 + spec->ht.ht_supported = true;
2159 + spec->ht.cap =
2160 + IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2161 + IEEE80211_HT_CAP_GRN_FLD |
2162 + IEEE80211_HT_CAP_SGI_20 |
2163 + IEEE80211_HT_CAP_SGI_40 |
2164 + IEEE80211_HT_CAP_TX_STBC |
2165 + IEEE80211_HT_CAP_RX_STBC |
2166 + IEEE80211_HT_CAP_PSMP_SUPPORT;
2167 + spec->ht.ampdu_factor = 3;
2168 + spec->ht.ampdu_density = 4;
2169 + spec->ht.mcs.rx_mask[0] = 0xff;
2170 + spec->ht.mcs.rx_mask[1] = 0xff;
2171 + spec->ht.mcs.tx_params =
2172 + IEEE80211_HT_MCS_TX_DEFINED;
2173 +
2174 + /*
2175 + * Initialize hw_mode information.
2176 + */
2177 + spec->supported_bands = SUPPORT_BAND_2GHZ;
2178 + spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2179 +
2180 + if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2181 + rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2182 + spec->num_channels = 14;
2183 + spec->channels = rf_vals;
2184 + } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2185 + rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2186 + spec->supported_bands |= SUPPORT_BAND_5GHZ;
2187 + spec->num_channels = ARRAY_SIZE(rf_vals);
2188 + spec->channels = rf_vals;
2189 + }
2190 +
2191 + /*
2192 + * Create channel information array
2193 + */
2194 + info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2195 + if (!info)
2196 + return -ENOMEM;
2197 +
2198 + spec->channels_info = info;
2199 +
2200 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2201 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2202 +
2203 + for (i = 0; i < 14; i++) {
2204 + info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2205 + info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2206 + }
2207 +
2208 + if (spec->num_channels > 14) {
2209 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2210 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2211 +
2212 + for (i = 14; i < spec->num_channels; i++) {
2213 + info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2214 + info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2215 + }
2216 + }
2217 +
2218 + return 0;
2219 +}
2220 +
2221 +static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2222 +{
2223 + int retval;
2224 +
2225 + /*
2226 + * Allocate eeprom data.
2227 + */
2228 + retval = rt2800usb_validate_eeprom(rt2x00dev);
2229 + if (retval)
2230 + return retval;
2231 +
2232 + retval = rt2800usb_init_eeprom(rt2x00dev);
2233 + if (retval)
2234 + return retval;
2235 +
2236 + /*
2237 + * Initialize hw specifications.
2238 + */
2239 + retval = rt2800usb_probe_hw_mode(rt2x00dev);
2240 + if (retval)
2241 + return retval;
2242 +
2243 + /*
2244 + * This device requires firmware.
2245 + */
2246 + __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2247 + __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
2248 + if (!modparam_nohwcrypt)
2249 + __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2250 +
2251 + /*
2252 + * Set the rssi offset.
2253 + */
2254 + rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2255 +
2256 + return 0;
2257 +}
2258 +
2259 +/*
2260 + * IEEE80211 stack callback functions.
2261 + */
2262 +static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2263 +{
2264 + struct rt2x00_dev *rt2x00dev = hw->priv;
2265 + u32 reg;
2266 +
2267 + rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2268 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2269 + rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
2270 +
2271 + rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2272 + rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2273 + rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2274 +
2275 + rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2276 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2277 + rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2278 +
2279 + rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2280 + rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 1);
2281 + rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2282 +
2283 + rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2284 + rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 1);
2285 + rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2286 +
2287 + rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2288 + rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 1);
2289 + rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2290 +
2291 + rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2292 + rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 1);
2293 + rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2294 +
2295 + return 0;
2296 +}
2297 +
2298 +static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2299 + const struct ieee80211_tx_queue_params *params)
2300 +{
2301 + struct rt2x00_dev *rt2x00dev = hw->priv;
2302 + struct data_queue *queue;
2303 + struct rt2x00_field32 field;
2304 + int retval;
2305 + u32 reg;
2306 + u32 offset;
2307 +
2308 + /*
2309 + * First pass the configuration through rt2x00lib, that will
2310 + * update the queue settings and validate the input. After that
2311 + * we are free to update the registers based on the value
2312 + * in the queue parameter.
2313 + */
2314 + retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2315 + if (retval)
2316 + return retval;
2317 +
2318 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2319 +
2320 + /* Update WMM TXOP register */
2321 + if (queue_idx < 2) {
2322 + field.bit_offset = queue_idx * 16;
2323 + field.bit_mask = 0xffff << field.bit_offset;
2324 +
2325 + rt2x00usb_register_read(rt2x00dev, WMM_TXOP0_CFG, &reg);
2326 + rt2x00_set_field32(&reg, field, queue->txop);
2327 + rt2x00usb_register_write(rt2x00dev, WMM_TXOP0_CFG, reg);
2328 + } else if (queue_idx < 4) {
2329 + field.bit_offset = (queue_idx - 2) * 16;
2330 + field.bit_mask = 0xffff << field.bit_offset;
2331 +
2332 + rt2x00usb_register_read(rt2x00dev, WMM_TXOP1_CFG, &reg);
2333 + rt2x00_set_field32(&reg, field, queue->txop);
2334 + rt2x00usb_register_write(rt2x00dev, WMM_TXOP1_CFG, reg);
2335 + }
2336 +
2337 + /* Update WMM registers */
2338 + field.bit_offset = queue_idx * 4;
2339 + field.bit_mask = 0xf << field.bit_offset;
2340 +
2341 + rt2x00usb_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2342 + rt2x00_set_field32(&reg, field, queue->aifs);
2343 + rt2x00usb_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2344 +
2345 + rt2x00usb_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2346 + rt2x00_set_field32(&reg, field, queue->cw_min);
2347 + rt2x00usb_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2348 +
2349 + rt2x00usb_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2350 + rt2x00_set_field32(&reg, field, queue->cw_max);
2351 + rt2x00usb_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2352 +
2353 + /* Update EDCA registers */
2354 + if (queue_idx < 4) {
2355 + offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2356 +
2357 + rt2x00usb_register_read(rt2x00dev, offset, &reg);
2358 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2359 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2360 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2361 + rt2x00usb_register_write(rt2x00dev, offset, reg);
2362 + }
2363 +
2364 + return 0;
2365 +}
2366 +
2367 +#if 0
2368 +/*
2369 + * Mac80211 demands get_tsf must be atomic.
2370 + * This is not possible for rt2800usb since all register access
2371 + * functions require sleeping. Untill mac80211 no longer needs
2372 + * get_tsf to be atomic, this function should be disabled.
2373 + */
2374 +static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2375 +{
2376 + struct rt2x00_dev *rt2x00dev = hw->priv;
2377 + u64 tsf;
2378 + u32 reg;
2379 +
2380 + rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2381 + tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2382 + rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2383 + tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2384 +
2385 + return tsf;
2386 +}
2387 +#else
2388 +#define rt2800usb_get_tsf NULL
2389 +#endif
2390 +
2391 +static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2392 + .tx = rt2x00mac_tx,
2393 + .start = rt2x00mac_start,
2394 + .stop = rt2x00mac_stop,
2395 + .add_interface = rt2x00mac_add_interface,
2396 + .remove_interface = rt2x00mac_remove_interface,
2397 + .config = rt2x00mac_config,
2398 + .config_interface = rt2x00mac_config_interface,
2399 + .configure_filter = rt2x00mac_configure_filter,
2400 + .set_key = rt2x00mac_set_key,
2401 + .get_stats = rt2x00mac_get_stats,
2402 + .set_rts_threshold = rt2800usb_set_rts_threshold,
2403 + .bss_info_changed = rt2x00mac_bss_info_changed,
2404 + .conf_tx = rt2800usb_conf_tx,
2405 + .get_tx_stats = rt2x00mac_get_tx_stats,
2406 + .get_tsf = rt2800usb_get_tsf,
2407 +};
2408 +
2409 +static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2410 + .probe_hw = rt2800usb_probe_hw,
2411 + .get_firmware_name = rt2800usb_get_firmware_name,
2412 + .get_firmware_crc = rt2800usb_get_firmware_crc,
2413 + .load_firmware = rt2800usb_load_firmware,
2414 + .initialize = rt2x00usb_initialize,
2415 + .uninitialize = rt2x00usb_uninitialize,
2416 + .clear_entry = rt2x00usb_clear_entry,
2417 + .set_device_state = rt2800usb_set_device_state,
2418 + .rfkill_poll = rt2800usb_rfkill_poll,
2419 + .link_stats = rt2800usb_link_stats,
2420 + .reset_tuner = rt2800usb_reset_tuner,
2421 + .link_tuner = rt2800usb_link_tuner,
2422 + .write_tx_desc = rt2800usb_write_tx_desc,
2423 + .write_tx_data = rt2x00usb_write_tx_data,
2424 + .write_beacon = rt2800usb_write_beacon,
2425 + .get_tx_data_len = rt2800usb_get_tx_data_len,
2426 + .kick_tx_queue = rt2800usb_kick_tx_queue,
2427 + .fill_rxdone = rt2800usb_fill_rxdone,
2428 + .config_shared_key = rt2800usb_config_shared_key,
2429 + .config_pairwise_key = rt2800usb_config_pairwise_key,
2430 + .config_filter = rt2800usb_config_filter,
2431 + .config_intf = rt2800usb_config_intf,
2432 + .config_erp = rt2800usb_config_erp,
2433 + .config_ant = rt2800usb_config_ant,
2434 + .config = rt2800usb_config,
2435 +};
2436 +
2437 +static const struct data_queue_desc rt2800usb_queue_rx = {
2438 + .entry_num = RX_ENTRIES,
2439 + .data_size = DATA_FRAME_SIZE,
2440 + .desc_size = RXD_DESC_SIZE,
2441 + .priv_size = sizeof(struct queue_entry_priv_usb),
2442 +};
2443 +
2444 +static const struct data_queue_desc rt2800usb_queue_tx = {
2445 + .entry_num = TX_ENTRIES,
2446 + .data_size = DATA_FRAME_SIZE,
2447 + .desc_size = TXD_DESC_SIZE,
2448 + .priv_size = sizeof(struct queue_entry_priv_usb),
2449 +};
2450 +
2451 +static const struct data_queue_desc rt2800usb_queue_bcn = {
2452 + .entry_num = 8 * BEACON_ENTRIES,
2453 + .data_size = MGMT_FRAME_SIZE,
2454 + .desc_size = TXWI_DESC_SIZE,
2455 + .priv_size = sizeof(struct queue_entry_priv_usb),
2456 +};
2457 +
2458 +static const struct rt2x00_ops rt2800usb_ops = {
2459 + .name = KBUILD_MODNAME,
2460 + .max_sta_intf = 1,
2461 + .max_ap_intf = 8,
2462 + .eeprom_size = EEPROM_SIZE,
2463 + .rf_size = RF_SIZE,
2464 + .tx_queues = NUM_TX_QUEUES,
2465 + .rx = &rt2800usb_queue_rx,
2466 + .tx = &rt2800usb_queue_tx,
2467 + .bcn = &rt2800usb_queue_bcn,
2468 + .lib = &rt2800usb_rt2x00_ops,
2469 + .hw = &rt2800usb_mac80211_ops,
2470 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2471 + .debugfs = &rt2800usb_rt2x00debug,
2472 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2473 +};
2474 +
2475 +/*
2476 + * rt2800usb module information.
2477 + */
2478 +static struct usb_device_id rt2800usb_device_table[] = {
2479 + /* Amit */
2480 + { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2481 + /* ASUS */
2482 + { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
2483 + { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
2484 + { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
2485 + /* AzureWave */
2486 + { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
2487 + /* Belkin */
2488 + { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
2489 + /* Conceptronic */
2490 + { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
2491 + { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
2492 + { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
2493 + { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
2494 + { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
2495 + { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
2496 + /* Corega */
2497 + { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
2498 + { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2499 + { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2500 + /* D-Link */
2501 + { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2502 + { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2503 + /* EnGenius */
2504 + { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
2505 + { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
2506 + /* Gigabyte */
2507 + { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
2508 + /* Hawking */
2509 + { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
2510 + { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
2511 + /* Linksys */
2512 + { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
2513 + /* Philips */
2514 + { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
2515 + /* Planex */
2516 + { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
2517 + /* Ralink */
2518 + { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2519 + { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2520 + /* Siemens */
2521 + { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
2522 + /* Sitecom */
2523 + { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
2524 + { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
2525 + { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
2526 + { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
2527 + /* SMC */
2528 + { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
2529 + { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
2530 + { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
2531 + { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
2532 + /* Sparklan */
2533 + { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
2534 + /* U-Media*/
2535 + { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
2536 + /* ZCOM */
2537 + { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
2538 + { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
2539 + /* Zyxel */
2540 + { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
2541 + { 0, }
2542 +};
2543 +
2544 +MODULE_AUTHOR(DRV_PROJECT);
2545 +MODULE_VERSION(DRV_VERSION);
2546 +MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
2547 +MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
2548 +MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
2549 +MODULE_FIRMWARE(FIRMWARE_RT2870);
2550 +MODULE_LICENSE("GPL");
2551 +
2552 +static struct usb_driver rt2800usb_driver = {
2553 + .name = KBUILD_MODNAME,
2554 + .id_table = rt2800usb_device_table,
2555 + .probe = rt2x00usb_probe,
2556 + .disconnect = rt2x00usb_disconnect,
2557 + .suspend = rt2x00usb_suspend,
2558 + .resume = rt2x00usb_resume,
2559 +};
2560 +
2561 +static int __init rt2800usb_init(void)
2562 +{
2563 + return usb_register(&rt2800usb_driver);
2564 +}
2565 +
2566 +static void __exit rt2800usb_exit(void)
2567 +{
2568 + usb_deregister(&rt2800usb_driver);
2569 +}
2570 +
2571 +module_init(rt2800usb_init);
2572 +module_exit(rt2800usb_exit);
2573 --- /dev/null
2574 +++ b/drivers/net/wireless/rt2x00/rt2800usb.h
2575 @@ -0,0 +1,1892 @@
2576 +/*
2577 + Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
2578 + <http://rt2x00.serialmonkey.com>
2579 +
2580 + This program is free software; you can redistribute it and/or modify
2581 + it under the terms of the GNU General Public License as published by
2582 + the Free Software Foundation; either version 2 of the License, or
2583 + (at your option) any later version.
2584 +
2585 + This program is distributed in the hope that it will be useful,
2586 + but WITHOUT ANY WARRANTY; without even the implied warranty of
2587 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2588 + GNU General Public License for more details.
2589 +
2590 + You should have received a copy of the GNU General Public License
2591 + along with this program; if not, write to the
2592 + Free Software Foundation, Inc.,
2593 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
2594 + */
2595 +
2596 +/*
2597 + Module: rt2800usb
2598 + Abstract: Data structures and registers for the rt2800usb module.
2599 + Supported chipsets: RT2800U.
2600 + */
2601 +
2602 +#ifndef RT2800USB_H
2603 +#define RT2800USB_H
2604 +
2605 +/*
2606 + * RF chip defines.
2607 + *
2608 + * RF2820 2.4G 2T3R
2609 + * RF2850 2.4G/5G 2T3R
2610 + * RF2720 2.4G 1T2R
2611 + * RF2750 2.4G/5G 1T2R
2612 + * RF3020 2.4G 1T1R
2613 + * RF2020 2.4G B/G
2614 + */
2615 +#define RF2820 0x0001
2616 +#define RF2850 0x0002
2617 +#define RF2720 0x0003
2618 +#define RF2750 0x0004
2619 +#define RF3020 0x0005
2620 +#define RF2020 0x0006
2621 +
2622 +/*
2623 + * RT2870 version
2624 + */
2625 +#define RT2870_VERSION_C 0x0100
2626 +#define RT2870_VERSION_D 0x0101
2627 +#define RT2870_VERSION_E 0x0200
2628 +
2629 +/*
2630 + * Signal information.
2631 + * Defaul offset is required for RSSI <-> dBm conversion.
2632 + */
2633 +#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
2634 +
2635 +/*
2636 + * Register layout information.
2637 + */
2638 +#define CSR_REG_BASE 0x1000
2639 +#define CSR_REG_SIZE 0x0800
2640 +#define EEPROM_BASE 0x0000
2641 +#define EEPROM_SIZE 0x0110
2642 +#define BBP_BASE 0x0000
2643 +#define BBP_SIZE 0x0080
2644 +#define RF_BASE 0x0000
2645 +#define RF_SIZE 0x0014
2646 +
2647 +/*
2648 + * Number of TX queues.
2649 + */
2650 +#define NUM_TX_QUEUES 4
2651 +
2652 +/*
2653 + * USB registers.
2654 + */
2655 +
2656 +/*
2657 + * HOST-MCU shared memory
2658 + */
2659 +#define HOST_CMD_CSR 0x0404
2660 +#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
2661 +
2662 +/*
2663 + * INT_SOURCE_CSR: Interrupt source register.
2664 + * Write one to clear corresponding bit.
2665 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
2666 + */
2667 +#define INT_SOURCE_CSR 0x0200
2668 +#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
2669 +#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
2670 +#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
2671 +#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
2672 +#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
2673 +#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
2674 +#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
2675 +#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
2676 +#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
2677 +#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
2678 +#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
2679 +#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
2680 +#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
2681 +#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
2682 +#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
2683 +#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
2684 +#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
2685 +#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
2686 +
2687 +/*
2688 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
2689 + */
2690 +#define INT_MASK_CSR 0x0204
2691 +#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
2692 +#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
2693 +#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
2694 +#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
2695 +#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
2696 +#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
2697 +#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
2698 +#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
2699 +#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
2700 +#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
2701 +#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
2702 +#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
2703 +#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
2704 +#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
2705 +#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
2706 +#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
2707 +#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
2708 +#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
2709 +
2710 +/*
2711 + * WPDMA_GLO_CFG
2712 + */
2713 +#define WPDMA_GLO_CFG 0x0208
2714 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
2715 +#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
2716 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
2717 +#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
2718 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
2719 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
2720 +#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
2721 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
2722 +#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
2723 +
2724 +/*
2725 + * WPDMA_RST_IDX
2726 + */
2727 +#define WPDMA_RST_IDX 0x020c
2728 +#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
2729 +#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
2730 +#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
2731 +#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
2732 +#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
2733 +#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
2734 +#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
2735 +
2736 +/*
2737 + * DELAY_INT_CFG
2738 + */
2739 +#define DELAY_INT_CFG 0x0210
2740 +#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
2741 +#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
2742 +#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
2743 +#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
2744 +#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
2745 +#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
2746 +
2747 +/*
2748 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
2749 + * AIFSN0: AC_BE
2750 + * AIFSN1: AC_BK
2751 + * AIFSN1: AC_VI
2752 + * AIFSN1: AC_VO
2753 + */
2754 +#define WMM_AIFSN_CFG 0x0214
2755 +#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
2756 +#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
2757 +#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
2758 +#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
2759 +
2760 +/*
2761 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
2762 + * CWMIN0: AC_BE
2763 + * CWMIN1: AC_BK
2764 + * CWMIN1: AC_VI
2765 + * CWMIN1: AC_VO
2766 + */
2767 +#define WMM_CWMIN_CFG 0x0218
2768 +#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
2769 +#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
2770 +#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
2771 +#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
2772 +
2773 +/*
2774 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
2775 + * CWMAX0: AC_BE
2776 + * CWMAX1: AC_BK
2777 + * CWMAX1: AC_VI
2778 + * CWMAX1: AC_VO
2779 + */
2780 +#define WMM_CWMAX_CFG 0x021c
2781 +#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
2782 +#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
2783 +#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
2784 +#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
2785 +
2786 +/*
2787 + * AC_TXOP0: AC_BK/AC_BE TXOP register
2788 + * AC0TXOP: AC_BK in unit of 32us
2789 + * AC1TXOP: AC_BE in unit of 32us
2790 + */
2791 +#define WMM_TXOP0_CFG 0x0220
2792 +#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
2793 +#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
2794 +
2795 +/*
2796 + * AC_TXOP1: AC_VO/AC_VI TXOP register
2797 + * AC2TXOP: AC_VI in unit of 32us
2798 + * AC3TXOP: AC_VO in unit of 32us
2799 + */
2800 +#define WMM_TXOP1_CFG 0x0224
2801 +#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
2802 +#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
2803 +
2804 +/*
2805 + * RINGREG_DIFF
2806 + */
2807 +#define RINGREG_DIFF 0x0010
2808 +
2809 +/*
2810 + * GPIO_CTRL_CFG:
2811 + */
2812 +#define GPIO_CTRL_CFG 0x0228
2813 +#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
2814 +#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
2815 +#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
2816 +#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
2817 +#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
2818 +#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
2819 +#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
2820 +#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
2821 +#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
2822 +
2823 +/*
2824 + * MCU_CMD_CFG
2825 + */
2826 +#define MCU_CMD_CFG 0x022c
2827 +
2828 +/*
2829 + * AC_BK register offsets
2830 + */
2831 +#define TX_BASE_PTR0 0x0230
2832 +#define TX_MAX_CNT0 0x0234
2833 +#define TX_CTX_IDX0 0x0238
2834 +#define TX_DTX_IDX0 0x023c
2835 +
2836 +/*
2837 + * AC_BE register offsets
2838 + */
2839 +#define TX_BASE_PTR1 0x0240
2840 +#define TX_MAX_CNT1 0x0244
2841 +#define TX_CTX_IDX1 0x0248
2842 +#define TX_DTX_IDX1 0x024c
2843 +
2844 +/*
2845 + * AC_VI register offsets
2846 + */
2847 +#define TX_BASE_PTR2 0x0250
2848 +#define TX_MAX_CNT2 0x0254
2849 +#define TX_CTX_IDX2 0x0258
2850 +#define TX_DTX_IDX2 0x025c
2851 +
2852 +/*
2853 + * AC_VO register offsets
2854 + */
2855 +#define TX_BASE_PTR3 0x0260
2856 +#define TX_MAX_CNT3 0x0264
2857 +#define TX_CTX_IDX3 0x0268
2858 +#define TX_DTX_IDX3 0x026c
2859 +
2860 +/*
2861 + * HCCA register offsets
2862 + */
2863 +#define TX_BASE_PTR4 0x0270
2864 +#define TX_MAX_CNT4 0x0274
2865 +#define TX_CTX_IDX4 0x0278
2866 +#define TX_DTX_IDX4 0x027c
2867 +
2868 +/*
2869 + * MGMT register offsets
2870 + */
2871 +#define TX_BASE_PTR5 0x0280
2872 +#define TX_MAX_CNT5 0x0284
2873 +#define TX_CTX_IDX5 0x0288
2874 +#define TX_DTX_IDX5 0x028c
2875 +
2876 +/*
2877 + * RX register offsets
2878 + */
2879 +#define RX_BASE_PTR 0x0290
2880 +#define RX_MAX_CNT 0x0294
2881 +#define RX_CRX_IDX 0x0298
2882 +#define RX_DRX_IDX 0x029c
2883 +
2884 +/*
2885 + * USB_DMA_CFG
2886 + * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
2887 + * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
2888 + * PHY_CLEAR: phy watch dog enable.
2889 + * TX_CLEAR: Clear USB DMA TX path.
2890 + * TXOP_HALT: Halt TXOP count down when TX buffer is full.
2891 + * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
2892 + * RX_BULK_EN: Enable USB DMA Rx.
2893 + * TX_BULK_EN: Enable USB DMA Tx.
2894 + * EP_OUT_VALID: OUT endpoint data valid.
2895 + * RX_BUSY: USB DMA RX FSM busy.
2896 + * TX_BUSY: USB DMA TX FSM busy.
2897 + */
2898 +#define USB_DMA_CFG 0x02a0
2899 +#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
2900 +#define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
2901 +#define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
2902 +#define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
2903 +#define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
2904 +#define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
2905 +#define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
2906 +#define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
2907 +#define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
2908 +#define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
2909 +#define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
2910 +
2911 +/*
2912 + * USB_CYC_CFG
2913 + */
2914 +#define USB_CYC_CFG 0x02a4
2915 +#define USB_CYC_CFG_CLOCK_CYCLE FIELD32(0x000000ff)
2916 +
2917 +/*
2918 + * PBF_SYS_CTRL
2919 + * HOST_RAM_WRITE: enable Host program ram write selection
2920 + */
2921 +#define PBF_SYS_CTRL 0x0400
2922 +#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
2923 +#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
2924 +
2925 +/*
2926 + * PBF registers
2927 + * Most are for debug. Driver doesn't touch PBF register.
2928 + */
2929 +#define PBF_CFG 0x0408
2930 +#define PBF_MAX_PCNT 0x040c
2931 +#define PBF_CTRL 0x0410
2932 +#define PBF_INT_STA 0x0414
2933 +#define PBF_INT_ENA 0x0418
2934 +
2935 +/*
2936 + * BCN_OFFSET0:
2937 + */
2938 +#define BCN_OFFSET0 0x042c
2939 +#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
2940 +#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
2941 +#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
2942 +#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
2943 +
2944 +/*
2945 + * BCN_OFFSET1:
2946 + */
2947 +#define BCN_OFFSET1 0x0430
2948 +#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
2949 +#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
2950 +#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
2951 +#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
2952 +
2953 +/*
2954 + * PBF registers
2955 + * Most are for debug. Driver doesn't touch PBF register.
2956 + */
2957 +#define TXRXQ_PCNT 0x0438
2958 +#define PBF_DBG 0x043c
2959 +
2960 +/*
2961 + * MAC Control/Status Registers(CSR).
2962 + * Some values are set in TU, whereas 1 TU == 1024 us.
2963 + */
2964 +
2965 +/*
2966 + * MAC_CSR0: ASIC revision number.
2967 + * ASIC_REV: 0
2968 + * ASIC_VER: 2870
2969 + */
2970 +#define MAC_CSR0 0x1000
2971 +#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
2972 +#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
2973 +
2974 +/*
2975 + * MAC_SYS_CTRL:
2976 + */
2977 +#define MAC_SYS_CTRL 0x1004
2978 +#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
2979 +#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
2980 +#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
2981 +#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
2982 +#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
2983 +#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
2984 +#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
2985 +#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
2986 +
2987 +/*
2988 + * MAC_ADDR_DW0: STA MAC register 0
2989 + */
2990 +#define MAC_ADDR_DW0 0x1008
2991 +#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
2992 +#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
2993 +#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
2994 +#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
2995 +
2996 +/*
2997 + * MAC_ADDR_DW1: STA MAC register 1
2998 + * UNICAST_TO_ME_MASK:
2999 + * Used to mask off bits from byte 5 of the MAC address
3000 + * to determine the UNICAST_TO_ME bit for RX frames.
3001 + * The full mask is complemented by BSS_ID_MASK:
3002 + * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3003 + */
3004 +#define MAC_ADDR_DW1 0x100c
3005 +#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
3006 +#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
3007 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
3008 +
3009 +/*
3010 + * MAC_BSSID_DW0: BSSID register 0
3011 + */
3012 +#define MAC_BSSID_DW0 0x1010
3013 +#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
3014 +#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
3015 +#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
3016 +#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
3017 +
3018 +/*
3019 + * MAC_BSSID_DW1: BSSID register 1
3020 + * BSS_ID_MASK:
3021 + * 0: 1-BSSID mode (BSS index = 0)
3022 + * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
3023 + * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3024 + * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3025 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3026 + * BSSID. This will make sure that those bits will be ignored
3027 + * when determining the MY_BSS of RX frames.
3028 + */
3029 +#define MAC_BSSID_DW1 0x1014
3030 +#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
3031 +#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
3032 +#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
3033 +#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
3034 +
3035 +/*
3036 + * MAX_LEN_CFG: Maximum frame length register.
3037 + * MAX_MPDU: rt2860b max 16k bytes
3038 + * MAX_PSDU: Maximum PSDU length
3039 + * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3040 + */
3041 +#define MAX_LEN_CFG 0x1018
3042 +#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
3043 +#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
3044 +#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
3045 +#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
3046 +
3047 +/*
3048 + * BBP_CSR_CFG: BBP serial control register
3049 + * VALUE: Register value to program into BBP
3050 + * REG_NUM: Selected BBP register
3051 + * READ_CONTROL: 0 write BBP, 1 read BBP
3052 + * BUSY: ASIC is busy executing BBP commands
3053 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3054 + * BBP_RW_MODE: 0 serial, 1 paralell
3055 + */
3056 +#define BBP_CSR_CFG 0x101c
3057 +#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
3058 +#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
3059 +#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
3060 +#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
3061 +#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
3062 +#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
3063 +
3064 +/*
3065 + * RF_CSR_CFG0: RF control register
3066 + * REGID_AND_VALUE: Register value to program into RF
3067 + * BITWIDTH: Selected RF register
3068 + * STANDBYMODE: 0 high when standby, 1 low when standby
3069 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3070 + * BUSY: ASIC is busy executing RF commands
3071 + */
3072 +#define RF_CSR_CFG0 0x1020
3073 +#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
3074 +#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
3075 +#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
3076 +#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
3077 +#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
3078 +#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
3079 +
3080 +/*
3081 + * RF_CSR_CFG1: RF control register
3082 + * REGID_AND_VALUE: Register value to program into RF
3083 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3084 + * 0: 3 system clock cycle (37.5usec)
3085 + * 1: 5 system clock cycle (62.5usec)
3086 + */
3087 +#define RF_CSR_CFG1 0x1024
3088 +#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
3089 +#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
3090 +
3091 +/*
3092 + * RF_CSR_CFG2: RF control register
3093 + * VALUE: Register value to program into RF
3094 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3095 + * 0: 3 system clock cycle (37.5usec)
3096 + * 1: 5 system clock cycle (62.5usec)
3097 + */
3098 +#define RF_CSR_CFG2 0x1028
3099 +#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
3100 +
3101 +/*
3102 + * LED_CFG: LED control
3103 + * color LED's:
3104 + * 0: off
3105 + * 1: blinking upon TX2
3106 + * 2: periodic slow blinking
3107 + * 3: always on
3108 + * LED polarity:
3109 + * 0: active low
3110 + * 1: active high
3111 + */
3112 +#define LED_CFG 0x102c
3113 +#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
3114 +#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
3115 +#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
3116 +#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
3117 +#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
3118 +#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
3119 +#define LED_CFG_LED_POLAR FIELD32(0x40000000)
3120 +
3121 +/*
3122 + * XIFS_TIME_CFG: MAC timing
3123 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3124 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3125 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3126 + * when MAC doesn't reference BBP signal BBRXEND
3127 + * EIFS: unit 1us
3128 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3129 + *
3130 + */
3131 +#define XIFS_TIME_CFG 0x1100
3132 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
3133 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
3134 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
3135 +#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
3136 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
3137 +
3138 +/*
3139 + * BKOFF_SLOT_CFG:
3140 + */
3141 +#define BKOFF_SLOT_CFG 0x1104
3142 +#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
3143 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
3144 +
3145 +/*
3146 + * NAV_TIME_CFG:
3147 + */
3148 +#define NAV_TIME_CFG 0x1108
3149 +#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
3150 +#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
3151 +#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
3152 +#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
3153 +
3154 +/*
3155 + * CH_TIME_CFG: count as channel busy
3156 + */
3157 +#define CH_TIME_CFG 0x110c
3158 +
3159 +/*
3160 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3161 + */
3162 +#define PBF_LIFE_TIMER 0x1110
3163 +
3164 +/*
3165 + * BCN_TIME_CFG:
3166 + * BEACON_INTERVAL: in unit of 1/16 TU
3167 + * TSF_TICKING: Enable TSF auto counting
3168 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3169 + * BEACON_GEN: Enable beacon generator
3170 + */
3171 +#define BCN_TIME_CFG 0x1114
3172 +#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
3173 +#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
3174 +#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
3175 +#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
3176 +#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
3177 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
3178 +
3179 +/*
3180 + * TBTT_SYNC_CFG:
3181 + */
3182 +#define TBTT_SYNC_CFG 0x1118
3183 +
3184 +/*
3185 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3186 + */
3187 +#define TSF_TIMER_DW0 0x111c
3188 +#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
3189 +
3190 +/*
3191 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3192 + */
3193 +#define TSF_TIMER_DW1 0x1120
3194 +#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
3195 +
3196 +/*
3197 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3198 + */
3199 +#define TBTT_TIMER 0x1124
3200 +
3201 +/*
3202 + * INT_TIMER_CFG:
3203 + */
3204 +#define INT_TIMER_CFG 0x1128
3205 +
3206 +/*
3207 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3208 + */
3209 +#define INT_TIMER_EN 0x112c
3210 +
3211 +/*
3212 + * CH_IDLE_STA: channel idle time
3213 + */
3214 +#define CH_IDLE_STA 0x1130
3215 +
3216 +/*
3217 + * CH_BUSY_STA: channel busy time
3218 + */
3219 +#define CH_BUSY_STA 0x1134
3220 +
3221 +/*
3222 + * MAC_STATUS_CFG:
3223 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3224 + * if 1 or higher one of the 2 registers is busy.
3225 + */
3226 +#define MAC_STATUS_CFG 0x1200
3227 +#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
3228 +
3229 +/*
3230 + * PWR_PIN_CFG:
3231 + */
3232 +#define PWR_PIN_CFG 0x1204
3233 +
3234 +/*
3235 + * AUTOWAKEUP_CFG: Manual power control / status register
3236 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3237 + * AUTOWAKE: 0:sleep, 1:awake
3238 + */
3239 +#define AUTOWAKEUP_CFG 0x1208
3240 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
3241 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
3242 +#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
3243 +
3244 +/*
3245 + * EDCA_AC0_CFG:
3246 + */
3247 +#define EDCA_AC0_CFG 0x1300
3248 +#define EDCA_AC0_CFG_AC_TX_OP FIELD32(0x000000ff)
3249 +#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
3250 +#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
3251 +#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
3252 +
3253 +/*
3254 + * EDCA_AC1_CFG:
3255 + */
3256 +#define EDCA_AC1_CFG 0x1304
3257 +#define EDCA_AC1_CFG_AC_TX_OP FIELD32(0x000000ff)
3258 +#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
3259 +#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
3260 +#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
3261 +
3262 +/*
3263 + * EDCA_AC2_CFG:
3264 + */
3265 +#define EDCA_AC2_CFG 0x1308
3266 +#define EDCA_AC2_CFG_AC_TX_OP FIELD32(0x000000ff)
3267 +#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
3268 +#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
3269 +#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
3270 +
3271 +/*
3272 + * EDCA_AC3_CFG:
3273 + */
3274 +#define EDCA_AC3_CFG 0x130c
3275 +#define EDCA_AC3_CFG_AC_TX_OP FIELD32(0x000000ff)
3276 +#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
3277 +#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
3278 +#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
3279 +
3280 +/*
3281 + * EDCA_TID_AC_MAP:
3282 + */
3283 +#define EDCA_TID_AC_MAP 0x1310
3284 +
3285 +/*
3286 + * TX_PWR_CFG_0:
3287 + */
3288 +#define TX_PWR_CFG_0 0x1314
3289 +#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
3290 +#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
3291 +#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
3292 +#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
3293 +#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
3294 +#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
3295 +#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
3296 +#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
3297 +
3298 +/*
3299 + * TX_PWR_CFG_1:
3300 + */
3301 +#define TX_PWR_CFG_1 0x1318
3302 +#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
3303 +#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
3304 +#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
3305 +#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
3306 +#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
3307 +#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
3308 +#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
3309 +#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
3310 +
3311 +/*
3312 + * TX_PWR_CFG_2:
3313 + */
3314 +#define TX_PWR_CFG_2 0x131c
3315 +#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
3316 +#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
3317 +#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
3318 +#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
3319 +#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
3320 +#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
3321 +#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
3322 +#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
3323 +
3324 +/*
3325 + * TX_PWR_CFG_3:
3326 + */
3327 +#define TX_PWR_CFG_3 0x1320
3328 +#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
3329 +#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
3330 +#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
3331 +#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
3332 +#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
3333 +#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
3334 +#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
3335 +#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
3336 +
3337 +/*
3338 + * TX_PWR_CFG_4:
3339 + */
3340 +#define TX_PWR_CFG_4 0x1324
3341 +#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
3342 +#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
3343 +#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
3344 +#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
3345 +
3346 +/*
3347 + * TX_PIN_CFG:
3348 + */
3349 +#define TX_PIN_CFG 0x1328
3350 +#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
3351 +#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
3352 +#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
3353 +#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
3354 +#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
3355 +#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
3356 +#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
3357 +#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
3358 +#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
3359 +#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
3360 +#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
3361 +#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
3362 +#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
3363 +#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
3364 +#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
3365 +#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
3366 +#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
3367 +#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
3368 +#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
3369 +#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
3370 +
3371 +/*
3372 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
3373 + */
3374 +#define TX_BAND_CFG 0x132c
3375 +#define TX_BAND_CFG_A FIELD32(0x00000002)
3376 +#define TX_BAND_CFG_BG FIELD32(0x00000004)
3377 +
3378 +/*
3379 + * TX_SW_CFG0:
3380 + */
3381 +#define TX_SW_CFG0 0x1330
3382 +
3383 +/*
3384 + * TX_SW_CFG1:
3385 + */
3386 +#define TX_SW_CFG1 0x1334
3387 +
3388 +/*
3389 + * TX_SW_CFG2:
3390 + */
3391 +#define TX_SW_CFG2 0x1338
3392 +
3393 +/*
3394 + * TXOP_THRES_CFG:
3395 + */
3396 +#define TXOP_THRES_CFG 0x133c
3397 +
3398 +/*
3399 + * TXOP_CTRL_CFG:
3400 + */
3401 +#define TXOP_CTRL_CFG 0x1340
3402 +
3403 +/*
3404 + * TX_RTS_CFG:
3405 + * RTS_THRES: unit:byte
3406 + * RTS_FBK_EN: enable rts rate fallback
3407 + */
3408 +#define TX_RTS_CFG 0x1344
3409 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
3410 +#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
3411 +#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
3412 +
3413 +/*
3414 + * TX_TIMEOUT_CFG:
3415 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
3416 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
3417 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
3418 + * it is recommended that:
3419 + * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
3420 + */
3421 +#define TX_TIMEOUT_CFG 0x1348
3422 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
3423 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
3424 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
3425 +
3426 +/*
3427 + * TX_RTY_CFG:
3428 + * SHORT_RTY_LIMIT: short retry limit
3429 + * LONG_RTY_LIMIT: long retry limit
3430 + * LONG_RTY_THRE: Long retry threshoold
3431 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
3432 + * 0:expired by retry limit, 1: expired by mpdu life timer
3433 + * AGG_RTY_MODE: Aggregate MPDU retry mode
3434 + * 0:expired by retry limit, 1: expired by mpdu life timer
3435 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
3436 + */
3437 +#define TX_RTY_CFG 0x134c
3438 +#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
3439 +#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
3440 +#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
3441 +#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
3442 +#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
3443 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
3444 +
3445 +/*
3446 + * TX_LINK_CFG:
3447 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
3448 + * MFB_ENABLE: TX apply remote MFB 1:enable
3449 + * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
3450 + * 0: not apply remote remote unsolicit (MFS=7)
3451 + * TX_MRQ_EN: MCS request TX enable
3452 + * TX_RDG_EN: RDG TX enable
3453 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
3454 + * REMOTE_MFB: remote MCS feedback
3455 + * REMOTE_MFS: remote MCS feedback sequence number
3456 + */
3457 +#define TX_LINK_CFG 0x1350
3458 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
3459 +#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
3460 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
3461 +#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
3462 +#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
3463 +#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
3464 +#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
3465 +#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
3466 +
3467 +/*
3468 + * HT_FBK_CFG0:
3469 + */
3470 +#define HT_FBK_CFG0 0x1354
3471 +#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
3472 +#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
3473 +#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
3474 +#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
3475 +#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
3476 +#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
3477 +#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
3478 +#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
3479 +
3480 +/*
3481 + * HT_FBK_CFG1:
3482 + */
3483 +#define HT_FBK_CFG1 0x1358
3484 +#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
3485 +#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
3486 +#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
3487 +#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
3488 +#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
3489 +#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
3490 +#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
3491 +#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
3492 +
3493 +/*
3494 + * LG_FBK_CFG0:
3495 + */
3496 +#define LG_FBK_CFG0 0x135c
3497 +#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
3498 +#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
3499 +#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
3500 +#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
3501 +#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
3502 +#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
3503 +#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
3504 +#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
3505 +
3506 +/*
3507 + * LG_FBK_CFG1:
3508 + */
3509 +#define LG_FBK_CFG1 0x1360
3510 +#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
3511 +#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
3512 +#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
3513 +#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
3514 +
3515 +/*
3516 + * CCK_PROT_CFG: CCK Protection
3517 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
3518 + * PROTECT_CTRL: Protection control frame type for CCK TX
3519 + * 0:none, 1:RTS/CTS, 2:CTS-to-self
3520 + * PROTECT_NAV: TXOP protection type for CCK TX
3521 + * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
3522 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
3523 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
3524 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
3525 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
3526 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
3527 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
3528 + * RTS_TH_EN: RTS threshold enable on CCK TX
3529 + */
3530 +#define CCK_PROT_CFG 0x1364
3531 +#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3532 +#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3533 +#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3534 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3535 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3536 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3537 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3538 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3539 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3540 +#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3541 +
3542 +/*
3543 + * OFDM_PROT_CFG: OFDM Protection
3544 + */
3545 +#define OFDM_PROT_CFG 0x1368
3546 +#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3547 +#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3548 +#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3549 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3550 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3551 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3552 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3553 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3554 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3555 +#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3556 +
3557 +/*
3558 + * MM20_PROT_CFG: MM20 Protection
3559 + */
3560 +#define MM20_PROT_CFG 0x136c
3561 +#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3562 +#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3563 +#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3564 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3565 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3566 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3567 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3568 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3569 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3570 +#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3571 +
3572 +/*
3573 + * MM40_PROT_CFG: MM40 Protection
3574 + */
3575 +#define MM40_PROT_CFG 0x1370
3576 +#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3577 +#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3578 +#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3579 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3580 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3581 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3582 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3583 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3584 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3585 +#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3586 +
3587 +/*
3588 + * GF20_PROT_CFG: GF20 Protection
3589 + */
3590 +#define GF20_PROT_CFG 0x1374
3591 +#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3592 +#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3593 +#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3594 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3595 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3596 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3597 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3598 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3599 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3600 +#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3601 +
3602 +/*
3603 + * GF40_PROT_CFG: GF40 Protection
3604 + */
3605 +#define GF40_PROT_CFG 0x1378
3606 +#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3607 +#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3608 +#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3609 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3610 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3611 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3612 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3613 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3614 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3615 +#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3616 +
3617 +/*
3618 + * EXP_CTS_TIME:
3619 + */
3620 +#define EXP_CTS_TIME 0x137c
3621 +
3622 +/*
3623 + * EXP_ACK_TIME:
3624 + */
3625 +#define EXP_ACK_TIME 0x1380
3626 +
3627 +/*
3628 + * RX_FILTER_CFG: RX configuration register.
3629 + */
3630 +#define RX_FILTER_CFG 0x1400
3631 +#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
3632 +#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
3633 +#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
3634 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
3635 +#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
3636 +#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
3637 +#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
3638 +#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
3639 +#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
3640 +#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
3641 +#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
3642 +#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
3643 +#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
3644 +#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
3645 +#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
3646 +#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
3647 +#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
3648 +
3649 +/*
3650 + * AUTO_RSP_CFG:
3651 + * AUTORESPONDER: 0: disable, 1: enable
3652 + * BAC_ACK_POLICY: 0:long, 1:short preamble
3653 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
3654 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
3655 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
3656 + * DUAL_CTS_EN: Power bit value in control frame
3657 + * ACK_CTS_PSM_BIT:Power bit value in control frame
3658 + */
3659 +#define AUTO_RSP_CFG 0x1404
3660 +#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
3661 +#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
3662 +#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
3663 +#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
3664 +#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
3665 +#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
3666 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
3667 +
3668 +/*
3669 + * LEGACY_BASIC_RATE:
3670 + */
3671 +#define LEGACY_BASIC_RATE 0x1408
3672 +
3673 +/*
3674 + * HT_BASIC_RATE:
3675 + */
3676 +#define HT_BASIC_RATE 0x140c
3677 +
3678 +/*
3679 + * HT_CTRL_CFG:
3680 + */
3681 +#define HT_CTRL_CFG 0x1410
3682 +
3683 +/*
3684 + * SIFS_COST_CFG:
3685 + */
3686 +#define SIFS_COST_CFG 0x1414
3687 +
3688 +/*
3689 + * RX_PARSER_CFG:
3690 + * Set NAV for all received frames
3691 + */
3692 +#define RX_PARSER_CFG 0x1418
3693 +
3694 +/*
3695 + * TX_SEC_CNT0:
3696 + */
3697 +#define TX_SEC_CNT0 0x1500
3698 +
3699 +/*
3700 + * RX_SEC_CNT0:
3701 + */
3702 +#define RX_SEC_CNT0 0x1504
3703 +
3704 +/*
3705 + * CCMP_FC_MUTE:
3706 + */
3707 +#define CCMP_FC_MUTE 0x1508
3708 +
3709 +/*
3710 + * TXOP_HLDR_ADDR0:
3711 + */
3712 +#define TXOP_HLDR_ADDR0 0x1600
3713 +
3714 +/*
3715 + * TXOP_HLDR_ADDR1:
3716 + */
3717 +#define TXOP_HLDR_ADDR1 0x1604
3718 +
3719 +/*
3720 + * TXOP_HLDR_ET:
3721 + */
3722 +#define TXOP_HLDR_ET 0x1608
3723 +
3724 +/*
3725 + * QOS_CFPOLL_RA_DW0:
3726 + */
3727 +#define QOS_CFPOLL_RA_DW0 0x160c
3728 +
3729 +/*
3730 + * QOS_CFPOLL_RA_DW1:
3731 + */
3732 +#define QOS_CFPOLL_RA_DW1 0x1610
3733 +
3734 +/*
3735 + * QOS_CFPOLL_QC:
3736 + */
3737 +#define QOS_CFPOLL_QC 0x1614
3738 +
3739 +/*
3740 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
3741 + */
3742 +#define RX_STA_CNT0 0x1700
3743 +#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
3744 +#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
3745 +
3746 +/*
3747 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
3748 + */
3749 +#define RX_STA_CNT1 0x1704
3750 +#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
3751 +#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
3752 +
3753 +/*
3754 + * RX_STA_CNT2:
3755 + */
3756 +#define RX_STA_CNT2 0x1708
3757 +#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
3758 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
3759 +
3760 +/*
3761 + * TX_STA_CNT0: TX Beacon count
3762 + */
3763 +#define TX_STA_CNT0 0x170c
3764 +#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
3765 +#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
3766 +
3767 +/*
3768 + * TX_STA_CNT1: TX tx count
3769 + */
3770 +#define TX_STA_CNT1 0x1710
3771 +#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
3772 +#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
3773 +
3774 +/*
3775 + * TX_STA_CNT2: TX tx count
3776 + */
3777 +#define TX_STA_CNT2 0x1714
3778 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
3779 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
3780 +
3781 +/*
3782 + * TX_STA_FIFO: TX Result for specific PID status fifo register
3783 + */
3784 +#define TX_STA_FIFO 0x1718
3785 +#define TX_STA_FIFO_B_VALID FIELD32(0x00000001)
3786 +#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
3787 +#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
3788 +#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
3789 +#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
3790 +#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
3791 +#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
3792 +
3793 +/*
3794 + * TX_AGG_CNT: Debug counter
3795 + */
3796 +#define TX_AGG_CNT 0x171c
3797 +#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
3798 +#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
3799 +
3800 +/*
3801 + * TX_AGG_CNT0:
3802 + */
3803 +#define TX_AGG_CNT0 0x1720
3804 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
3805 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
3806 +
3807 +/*
3808 + * TX_AGG_CNT1:
3809 + */
3810 +#define TX_AGG_CNT1 0x1724
3811 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
3812 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
3813 +
3814 +/*
3815 + * TX_AGG_CNT2:
3816 + */
3817 +#define TX_AGG_CNT2 0x1728
3818 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
3819 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
3820 +
3821 +/*
3822 + * TX_AGG_CNT3:
3823 + */
3824 +#define TX_AGG_CNT3 0x172c
3825 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
3826 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
3827 +
3828 +/*
3829 + * TX_AGG_CNT4:
3830 + */
3831 +#define TX_AGG_CNT4 0x1730
3832 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
3833 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
3834 +
3835 +/*
3836 + * TX_AGG_CNT5:
3837 + */
3838 +#define TX_AGG_CNT5 0x1734
3839 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
3840 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
3841 +
3842 +/*
3843 + * TX_AGG_CNT6:
3844 + */
3845 +#define TX_AGG_CNT6 0x1738
3846 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
3847 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
3848 +
3849 +/*
3850 + * TX_AGG_CNT7:
3851 + */
3852 +#define TX_AGG_CNT7 0x173c
3853 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
3854 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
3855 +
3856 +/*
3857 + * MPDU_DENSITY_CNT:
3858 + * TX_ZERO_DEL: TX zero length delimiter count
3859 + * RX_ZERO_DEL: RX zero length delimiter count
3860 + */
3861 +#define MPDU_DENSITY_CNT 0x1740
3862 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
3863 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
3864 +
3865 +/*
3866 + * Security key table memory, base address = 0x1800
3867 + */
3868 +struct hw_pairwise_ta_entry {
3869 + u8 address[6];
3870 + u8 reserved[2];
3871 +} __attribute__ ((packed));
3872 +
3873 +struct wcid_entry {
3874 + u8 rx_ba_bitmat7;
3875 + u8 rx_ba_bitmat0;
3876 + u8 mac[6];
3877 +} __attribute__ ((packed));
3878 +
3879 +struct hw_key_entry {
3880 + u8 key[16];
3881 + u8 tx_mic[8];
3882 + u8 rx_mic[8];
3883 +} __attribute__ ((packed));
3884 +
3885 +/*
3886 + * Security key table memory.
3887 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
3888 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
3889 + * PAIRWISE_IVEIV_TABLE_BASE: 8-byte * 256-entry
3890 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
3891 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
3892 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
3893 + * SHARED_KEY_MODE_BASE: 32-byte * 16-entry
3894 + */
3895 +#define MAC_WCID_BASE 0x1800
3896 +#define PAIRWISE_KEY_TABLE_BASE 0x4000
3897 +#define PAIRWISE_IVEIV_TABLE_BASE 0x6000
3898 +#define MAC_IVEIV_TABLE_BASE 0x6000
3899 +#define MAC_WCID_ATTRIBUTE_BASE 0x6800
3900 +#define SHARED_KEY_TABLE_BASE 0x6c00
3901 +#define SHARED_KEY_MODE_BASE 0x7000
3902 +
3903 +#define SHARED_KEY_ENTRY(__idx) \
3904 + ( SHARED_KEY_TABLE_BASE + \
3905 + ((__idx) * sizeof(struct hw_key_entry)) )
3906 +#define SHARED_KEY_MODE_ENTRY(__idx) \
3907 + ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
3908 +#define PAIRWISE_KEY_ENTRY(__idx) \
3909 + ( PAIRWISE_KEY_TABLE_BASE + \
3910 + ((__idx) * sizeof(struct hw_key_entry)) )
3911 +
3912 +#define MAC_WCID_ENTRY(__idx) \
3913 + ( MAC_WCID_BASE + (2 * sizeof(u32) * (__idx)) )
3914 +#define MAC_WCID_ATTR_ENTRY(__idx) \
3915 + ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
3916 +
3917 +/*
3918 + * MAC_WCID_ATTRIBUTE:
3919 + * KEYTAB: 0: shared key table, 1: pairwise key table
3920 + * BSS_IDX: multipleBSS index for the WCID
3921 + */
3922 +#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
3923 +#define MAC_WCID_ATTRIBUTE_PAIRKEY_MODE FIELD32(0x0000000e)
3924 +#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
3925 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
3926 +
3927 +/*
3928 + * SHARED_KEY_MODE:
3929 + */
3930 +#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
3931 +#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
3932 +#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
3933 +#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
3934 +#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
3935 +#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
3936 +#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
3937 +#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
3938 +
3939 +/*
3940 + * HOST-MCU communication
3941 + */
3942 +
3943 +/*
3944 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
3945 + */
3946 +#define H2M_MAILBOX_CSR 0x7010
3947 +#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
3948 +#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
3949 +#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
3950 +#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
3951 +
3952 +/*
3953 + * H2M_MAILBOX_CID:
3954 + */
3955 +#define H2M_MAILBOX_CID 0x7014
3956 +
3957 +/*
3958 + * H2M_MAILBOX_STATUS:
3959 + */
3960 +#define H2M_MAILBOX_STATUS 0x701c
3961 +
3962 +/*
3963 + * H2M_INT_SRC:
3964 + */
3965 +#define H2M_INT_SRC 0x7024
3966 +
3967 +/*
3968 + * H2M_BBP_AGENT:
3969 + */
3970 +#define H2M_BBP_AGENT 0x7028
3971 +
3972 +/*
3973 + * MCU_LEDCS: LED control for MCU Mailbox.
3974 + */
3975 +#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
3976 +#define MCU_LEDCS_POLARITY FIELD8(0x01)
3977 +
3978 +/*
3979 + * HW_CS_CTS_BASE:
3980 + * Carrier-sense CTS frame base address.
3981 + * It's where mac stores carrier-sense frame for carrier-sense function.
3982 + */
3983 +#define HW_CS_CTS_BASE 0x7700
3984 +
3985 +/*
3986 + * HW_DFS_CTS_BASE:
3987 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
3988 + */
3989 +#define HW_DFS_CTS_BASE 0x7780
3990 +
3991 +/*
3992 + * TXRX control registers - base address 0x3000
3993 + */
3994 +
3995 +/*
3996 + * TXRX_CSR1:
3997 + * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
3998 + */
3999 +#define TXRX_CSR1 0x77d0
4000 +
4001 +/*
4002 + * HW_DEBUG_SETTING_BASE:
4003 + * since NULL frame won't be that long (256 byte)
4004 + * We steal 16 tail bytes to save debugging settings
4005 + */
4006 +#define HW_DEBUG_SETTING_BASE 0x77f0
4007 +#define HW_DEBUG_SETTING_BASE2 0x7770
4008 +
4009 +/*
4010 + * HW_BEACON_BASE
4011 + * In order to support maximum 8 MBSS and its maximum length
4012 + * is 512 bytes for each beacon
4013 + * Three section discontinue memory segments will be used.
4014 + * 1. The original region for BCN 0~3
4015 + * 2. Extract memory from FCE table for BCN 4~5
4016 + * 3. Extract memory from Pair-wise key table for BCN 6~7
4017 + * It occupied those memory of wcid 238~253 for BCN 6
4018 + * and wcid 222~237 for BCN 7
4019 + *
4020 + * IMPORTANT NOTE: Not sure why legacy driver does this,
4021 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
4022 + */
4023 +#define HW_BEACON_BASE0 0x7800
4024 +#define HW_BEACON_BASE1 0x7a00
4025 +#define HW_BEACON_BASE2 0x7c00
4026 +#define HW_BEACON_BASE3 0x7e00
4027 +#define HW_BEACON_BASE4 0x7200
4028 +#define HW_BEACON_BASE5 0x7400
4029 +#define HW_BEACON_BASE6 0x5dc0
4030 +#define HW_BEACON_BASE7 0x5bc0
4031 +
4032 +#define HW_BEACON_OFFSET(__index) \
4033 + ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
4034 + (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
4035 + (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
4036 +
4037 +/*
4038 + * 8051 firmware image.
4039 + */
4040 +#define FIRMWARE_RT2870 "rt2870.bin"
4041 +#define FIRMWARE_IMAGE_BASE 0x3000
4042 +
4043 +/*
4044 + * BBP registers.
4045 + * The wordsize of the BBP is 8 bits.
4046 + */
4047 +
4048 +/*
4049 + * BBP 1: TX Antenna
4050 + */
4051 +#define BBP1_TX_POWER FIELD8(0x07)
4052 +#define BBP1_TX_ANTENNA FIELD8(0x18)
4053 +
4054 +/*
4055 + * BBP 3: RX Antenna
4056 + */
4057 +#define BBP3_RX_ANTENNA FIELD8(0x18)
4058 +
4059 +/*
4060 + * RF registers
4061 + */
4062 +
4063 +/*
4064 + * RF 2
4065 + */
4066 +#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
4067 +#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
4068 +#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
4069 +
4070 +/*
4071 + * RF 3
4072 + */
4073 +#define RF3_TXPOWER_G FIELD32(0x00003e00)
4074 +#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
4075 +#define RF3_TXPOWER_A FIELD32(0x00003c00)
4076 +
4077 +/*
4078 + * RF 4
4079 + */
4080 +#define RF4_TXPOWER_G FIELD32(0x000007c0)
4081 +#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
4082 +#define RF4_TXPOWER_A FIELD32(0x00000780)
4083 +#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
4084 +#define RF4_BW40 FIELD32(0x00200000)
4085 +
4086 +/*
4087 + * EEPROM content.
4088 + * The wordsize of the EEPROM is 16 bits.
4089 + */
4090 +
4091 +/*
4092 + * EEPROM Version
4093 + */
4094 +#define EEPROM_VERSION 0x0001
4095 +#define EEPROM_VERSION_FAE FIELD16(0x00ff)
4096 +#define EEPROM_VERSION_VERSION FIELD16(0xff00)
4097 +
4098 +/*
4099 + * HW MAC address.
4100 + */
4101 +#define EEPROM_MAC_ADDR_0 0x0002
4102 +#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
4103 +#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
4104 +#define EEPROM_MAC_ADDR_1 0x0003
4105 +#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
4106 +#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
4107 +#define EEPROM_MAC_ADDR_2 0x0004
4108 +#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
4109 +#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
4110 +
4111 +/*
4112 + * EEPROM ANTENNA config
4113 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
4114 + * TXPATH: 1: 1T, 2: 2T
4115 + */
4116 +#define EEPROM_ANTENNA 0x001a
4117 +#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
4118 +#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
4119 +#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
4120 +
4121 +/*
4122 + * EEPROM NIC config
4123 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
4124 + */
4125 +#define EEPROM_NIC 0x001b
4126 +#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
4127 +#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
4128 +#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
4129 +#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
4130 +#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
4131 +#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
4132 +#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
4133 +#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
4134 +#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
4135 +#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
4136 +
4137 +/*
4138 + * EEPROM frequency
4139 + */
4140 +#define EEPROM_FREQ 0x001d
4141 +#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
4142 +#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
4143 +#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
4144 +
4145 +/*
4146 + * EEPROM LED
4147 + * POLARITY_RDY_G: Polarity RDY_G setting.
4148 + * POLARITY_RDY_A: Polarity RDY_A setting.
4149 + * POLARITY_ACT: Polarity ACT setting.
4150 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
4151 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
4152 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
4153 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
4154 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
4155 + * LED_MODE: Led mode.
4156 + */
4157 +#define EEPROM_LED1 0x001e
4158 +#define EEPROM_LED2 0x001f
4159 +#define EEPROM_LED3 0x0020
4160 +#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
4161 +#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
4162 +#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
4163 +#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
4164 +#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
4165 +#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
4166 +#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
4167 +#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
4168 +#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
4169 +
4170 +/*
4171 + * EEPROM LNA
4172 + */
4173 +#define EEPROM_LNA 0x0022
4174 +#define EEPROM_LNA_BG FIELD16(0x00ff)
4175 +#define EEPROM_LNA_A0 FIELD16(0xff00)
4176 +
4177 +/*
4178 + * EEPROM RSSI BG offset
4179 + */
4180 +#define EEPROM_RSSI_BG 0x0023
4181 +#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
4182 +#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
4183 +
4184 +/*
4185 + * EEPROM RSSI BG2 offset
4186 + */
4187 +#define EEPROM_RSSI_BG2 0x0024
4188 +#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
4189 +#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
4190 +
4191 +/*
4192 + * EEPROM RSSI A offset
4193 + */
4194 +#define EEPROM_RSSI_A 0x0025
4195 +#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
4196 +#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
4197 +
4198 +/*
4199 + * EEPROM RSSI A2 offset
4200 + */
4201 +#define EEPROM_RSSI_A2 0x0026
4202 +#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
4203 +#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
4204 +
4205 +/*
4206 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
4207 + * This is delta in 40MHZ.
4208 + * VALUE: Tx Power dalta value (MAX=4)
4209 + * TYPE: 1: Plus the delta value, 0: minus the delta value
4210 + * TXPOWER: Enable:
4211 + */
4212 +#define EEPROM_TXPOWER_DELTA 0x0028
4213 +#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
4214 +#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
4215 +#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
4216 +
4217 +/*
4218 + * EEPROM TXPOWER 802.11BG
4219 + */
4220 +#define EEPROM_TXPOWER_BG1 0x0029
4221 +#define EEPROM_TXPOWER_BG2 0x0030
4222 +#define EEPROM_TXPOWER_BG_SIZE 7
4223 +#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
4224 +#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
4225 +
4226 +/*
4227 + * EEPROM TXPOWER 802.11A
4228 + */
4229 +#define EEPROM_TXPOWER_A1 0x003c
4230 +#define EEPROM_TXPOWER_A2 0x0053
4231 +#define EEPROM_TXPOWER_A_SIZE 6
4232 +#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
4233 +#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
4234 +
4235 +/*
4236 + * EEPROM TXpower byrate: 20MHZ power
4237 + */
4238 +#define EEPROM_TXPOWER_BYRATE 0x006f
4239 +
4240 +/*
4241 + * EEPROM BBP.
4242 + */
4243 +#define EEPROM_BBP_START 0x0078
4244 +#define EEPROM_BBP_SIZE 16
4245 +#define EEPROM_BBP_VALUE FIELD16(0x00ff)
4246 +#define EEPROM_BBP_REG_ID FIELD16(0xff00)
4247 +
4248 +/*
4249 + * MCU mailbox commands.
4250 + */
4251 +#define MCU_SLEEP 0x30
4252 +#define MCU_WAKEUP 0x31
4253 +#define MCU_LED 0x50
4254 +#define MCU_LED_STRENGTH 0x51
4255 +#define MCU_LED_1 0x52
4256 +#define MCU_LED_2 0x53
4257 +#define MCU_LED_3 0x54
4258 +#define MCU_RADAR 0x60
4259 +#define MCU_BOOT_SIGNAL 0x72
4260 +
4261 +/*
4262 + * DMA descriptor defines.
4263 + */
4264 +#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
4265 +#define TXINFO_DESC_SIZE ( 1 * sizeof(__le32) )
4266 +#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
4267 +#define RXD_DESC_SIZE ( 1 * sizeof(__le32) )
4268 +#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
4269 +
4270 +/*
4271 + * TX descriptor format for TX, PRIO and Beacon Ring.
4272 + */
4273 +
4274 +/*
4275 + * Word0
4276 + */
4277 +#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
4278 +
4279 +/*
4280 + * Word1
4281 + */
4282 +#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
4283 +#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
4284 +#define TXD_W1_BURST FIELD32(0x00008000)
4285 +#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
4286 +#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
4287 +#define TXD_W1_DMA_DONE FIELD32(0x80000000)
4288 +
4289 +/*
4290 + * Word2
4291 + */
4292 +#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
4293 +
4294 +/*
4295 + * Word3
4296 + * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
4297 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4298 + * 0:MGMT, 1:HCCA 2:EDCA
4299 + */
4300 +#define TXD_W3_WIV FIELD32(0x01000000)
4301 +#define TXD_W3_QSEL FIELD32(0x06000000)
4302 +#define TXD_W3_TCO FIELD32(0x20000000)
4303 +#define TXD_W3_UCO FIELD32(0x40000000)
4304 +#define TXD_W3_ICO FIELD32(0x80000000)
4305 +
4306 +/*
4307 + * TX Info structure
4308 + */
4309 +
4310 +/*
4311 + * Word0
4312 + * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
4313 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4314 + * 0:MGMT, 1:HCCA 2:EDCA
4315 + * USB_DMA_NEXT_VALID: Used ONLY in USB bulk Aggregation, NextValid
4316 + * DMA_TX_BURST: used ONLY in USB bulk Aggregation.
4317 + * Force USB DMA transmit frame from current selected endpoint
4318 + */
4319 +#define TXINFO_W0_USB_DMA_TX_PKT_LEN FIELD32(0x0000ffff)
4320 +#define TXINFO_W0_WIV FIELD32(0x01000000)
4321 +#define TXINFO_W0_QSEL FIELD32(0x06000000)
4322 +#define TXINFO_W0_USB_DMA_NEXT_VALID FIELD32(0x40000000)
4323 +#define TXINFO_W0_USB_DMA_TX_BURST FIELD32(0x80000000)
4324 +
4325 +/*
4326 + * TX WI structure
4327 + */
4328 +
4329 +/*
4330 + * Word0
4331 + * FRAG: 1 To inform TKIP engine this is a fragment.
4332 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
4333 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
4334 + * BW: Channel bandwidth 20MHz or 40 MHz
4335 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
4336 + */
4337 +#define TXWI_W0_FRAG FIELD32(0x00000001)
4338 +#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
4339 +#define TXWI_W0_CF_ACK FIELD32(0x00000004)
4340 +#define TXWI_W0_TS FIELD32(0x00000008)
4341 +#define TXWI_W0_AMPDU FIELD32(0x00000010)
4342 +#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
4343 +#define TXWI_W0_TX_OP FIELD32(0x00000300)
4344 +#define TXWI_W0_MCS FIELD32(0x007f0000)
4345 +#define TXWI_W0_BW FIELD32(0x00800000)
4346 +#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
4347 +#define TXWI_W0_STBC FIELD32(0x06000000)
4348 +#define TXWI_W0_IFS FIELD32(0x08000000)
4349 +#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
4350 +
4351 +/*
4352 + * Word1
4353 + */
4354 +#define TXWI_W1_ACK FIELD32(0x00000001)
4355 +#define TXWI_W1_NSEQ FIELD32(0x00000002)
4356 +#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
4357 +#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
4358 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
4359 +#define TXWI_W1_PACKETID FIELD32(0xf0000000)
4360 +
4361 +/*
4362 + * Word2
4363 + */
4364 +#define TXWI_W2_IV FIELD32(0xffffffff)
4365 +
4366 +/*
4367 + * Word3
4368 + */
4369 +#define TXWI_W3_EIV FIELD32(0xffffffff)
4370 +
4371 +/*
4372 + * RX descriptor format for RX Ring.
4373 + */
4374 +
4375 +/*
4376 + * Word0
4377 + * UNICAST_TO_ME: This RX frame is unicast to me.
4378 + * MULTICAST: This is a multicast frame.
4379 + * BROADCAST: This is a broadcast frame.
4380 + * MY_BSS: this frame belongs to the same BSSID.
4381 + * CRC_ERROR: CRC error.
4382 + * CIPHER_ERROR: 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid.
4383 + * AMSDU: rx with 802.3 header, not 802.11 header.
4384 + */
4385 +
4386 +#define RXD_W0_BA FIELD32(0x00000001)
4387 +#define RXD_W0_DATA FIELD32(0x00000002)
4388 +#define RXD_W0_NULLDATA FIELD32(0x00000004)
4389 +#define RXD_W0_FRAG FIELD32(0x00000008)
4390 +#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000010)
4391 +#define RXD_W0_MULTICAST FIELD32(0x00000020)
4392 +#define RXD_W0_BROADCAST FIELD32(0x00000040)
4393 +#define RXD_W0_MY_BSS FIELD32(0x00000080)
4394 +#define RXD_W0_CRC_ERROR FIELD32(0x00000100)
4395 +#define RXD_W0_CIPHER_ERROR FIELD32(0x00000600)
4396 +#define RXD_W0_AMSDU FIELD32(0x00000800)
4397 +#define RXD_W0_HTC FIELD32(0x00001000)
4398 +#define RXD_W0_RSSI FIELD32(0x00002000)
4399 +#define RXD_W0_L2PAD FIELD32(0x00004000)
4400 +#define RXD_W0_AMPDU FIELD32(0x00008000)
4401 +#define RXD_W0_DECRYPTED FIELD32(0x00010000)
4402 +#define RXD_W0_PLCP_RSSI FIELD32(0x00020000)
4403 +#define RXD_W0_CIPHER_ALG FIELD32(0x00040000)
4404 +#define RXD_W0_LAST_AMSDU FIELD32(0x00080000)
4405 +#define RXD_W0_PLCP_SIGNAL FIELD32(0xfff00000)
4406 +
4407 +/*
4408 + * RX WI structure
4409 + */
4410 +
4411 +/*
4412 + * Word0
4413 + */
4414 +#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
4415 +#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
4416 +#define RXWI_W0_BSSID FIELD32(0x00001c00)
4417 +#define RXWI_W0_UDF FIELD32(0x0000e000)
4418 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
4419 +#define RXWI_W0_TID FIELD32(0xf0000000)
4420 +
4421 +/*
4422 + * Word1
4423 + */
4424 +#define RXWI_W1_FRAG FIELD32(0x0000000f)
4425 +#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
4426 +#define RXWI_W1_MCS FIELD32(0x007f0000)
4427 +#define RXWI_W1_BW FIELD32(0x00800000)
4428 +#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
4429 +#define RXWI_W1_STBC FIELD32(0x06000000)
4430 +#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
4431 +
4432 +/*
4433 + * Word2
4434 + */
4435 +#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
4436 +#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
4437 +#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
4438 +
4439 +/*
4440 + * Word3
4441 + */
4442 +#define RXWI_W3_SNR0 FIELD32(0x000000ff)
4443 +#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
4444 +
4445 +/*
4446 + * Macro's for converting txpower from EEPROM to mac80211 value
4447 + * and from mac80211 value to register value.
4448 + */
4449 +#define MIN_G_TXPOWER 0
4450 +#define MIN_A_TXPOWER -7
4451 +#define MAX_G_TXPOWER 31
4452 +#define MAX_A_TXPOWER 15
4453 +#define DEFAULT_TXPOWER 5
4454 +
4455 +#define TXPOWER_G_FROM_DEV(__txpower) \
4456 + ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4457 +
4458 +#define TXPOWER_G_TO_DEV(__txpower) \
4459 + clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
4460 +
4461 +#define TXPOWER_A_FROM_DEV(__txpower) \
4462 + ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4463 +
4464 +#define TXPOWER_A_TO_DEV(__txpower) \
4465 + clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
4466 +
4467 +#endif /* RT2800USB_H */
4468 --- a/drivers/net/wireless/rt2x00/rt2x00.h
4469 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
4470 @@ -143,6 +143,7 @@ struct rt2x00_chip {
4471 #define RT2860D 0x0681 /* 2.4GHz, 5GHz PCI/CB */
4472 #define RT2890 0x0701 /* 2.4GHz PCIe */
4473 #define RT2890D 0x0781 /* 2.4GHz, 5GHz PCIe */
4474 +#define RT2870 0x1600
4475
4476 u16 rf;
4477 u32 rev;
Personal OpenWRT clone
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