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ar71xx: preliminary Ubiquiti Bullet M support
[openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx.h
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __AG71XX_H
15 #define __AG71XX_H
16
17 #include <linux/kernel.h>
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/random.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/ethtool.h>
27 #include <linux/etherdevice.h>
28 #include <linux/phy.h>
29 #include <linux/skbuff.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32
33 #include <linux/bitops.h>
34
35 #include <asm/mach-ar71xx/ar71xx.h>
36 #include <asm/mach-ar71xx/platform.h>
37
38 #define ETH_FCS_LEN 4
39
40 #define AG71XX_DRV_NAME "ag71xx"
41 #define AG71XX_DRV_VERSION "0.5.23"
42
43 #define AG71XX_NAPI_WEIGHT 64
44 #define AG71XX_OOM_REFILL (1 + HZ/10)
45
46 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
47 #define AG71XX_INT_TX (AG71XX_INT_TX_PS)
48 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
49
50 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
51 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
52
53 #define AG71XX_TX_FIFO_LEN 2048
54 #define AG71XX_TX_MTU_LEN 1536
55 #define AG71XX_RX_PKT_RESERVE 64
56 #define AG71XX_RX_PKT_SIZE \
57 (AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN)
58
59 #define AG71XX_TX_RING_SIZE 64
60 #define AG71XX_TX_THRES_STOP (AG71XX_TX_RING_SIZE - 4)
61 #define AG71XX_TX_THRES_WAKEUP \
62 (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
63
64 #define AG71XX_RX_RING_SIZE 128
65
66 #ifdef CONFIG_AG71XX_DEBUG
67 #define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
68 #else
69 #define DBG(fmt, args...) do {} while (0)
70 #endif
71
72 #define ag71xx_assert(_cond) \
73 do { \
74 if (_cond) \
75 break; \
76 printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
77 BUG(); \
78 } while (0)
79
80 struct ag71xx_desc {
81 u32 data;
82 u32 ctrl;
83 #define DESC_EMPTY BIT(31)
84 #define DESC_MORE BIT(24)
85 #define DESC_PKTLEN_M 0xfff
86 u32 next;
87 u32 pad;
88 } __attribute__((aligned(4)));
89
90 struct ag71xx_buf {
91 struct sk_buff *skb;
92 struct ag71xx_desc *desc;
93 };
94
95 struct ag71xx_ring {
96 struct ag71xx_buf *buf;
97 u8 *descs_cpu;
98 dma_addr_t descs_dma;
99 unsigned int desc_size;
100 unsigned int curr;
101 unsigned int dirty;
102 unsigned int size;
103 };
104
105 struct ag71xx_mdio {
106 struct mii_bus *mii_bus;
107 int mii_irq[PHY_MAX_ADDR];
108 void __iomem *mdio_base;
109 };
110
111 struct ag71xx {
112 void __iomem *mac_base;
113 void __iomem *mac_base2;
114 void __iomem *mii_ctrl;
115
116 spinlock_t lock;
117 struct platform_device *pdev;
118 struct net_device *dev;
119 struct napi_struct napi;
120 u32 msg_enable;
121
122 struct ag71xx_ring rx_ring;
123 struct ag71xx_ring tx_ring;
124
125 struct mii_bus *mii_bus;
126 struct phy_device *phy_dev;
127
128 unsigned int link;
129 unsigned int speed;
130 int duplex;
131
132 struct work_struct restart_work;
133 struct timer_list oom_timer;
134 };
135
136 extern struct ethtool_ops ag71xx_ethtool_ops;
137
138 extern struct ag71xx_mdio *ag71xx_mdio_bus;
139 extern int ag71xx_mdio_driver_init(void) __init;
140 extern void ag71xx_mdio_driver_exit(void);
141
142 extern int ag71xx_phy_connect(struct ag71xx *ag);
143 extern void ag71xx_phy_disconnect(struct ag71xx *ag);
144 extern void ag71xx_phy_start(struct ag71xx *ag);
145 extern void ag71xx_phy_stop(struct ag71xx *ag);
146
147 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
148 {
149 return ag->pdev->dev.platform_data;
150 }
151
152 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
153 {
154 return ((desc->ctrl & DESC_EMPTY) != 0);
155 }
156
157 static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
158 {
159 return (desc->ctrl & DESC_PKTLEN_M);
160 }
161
162 /* Register offsets */
163 #define AG71XX_REG_MAC_CFG1 0x0000
164 #define AG71XX_REG_MAC_CFG2 0x0004
165 #define AG71XX_REG_MAC_IPG 0x0008
166 #define AG71XX_REG_MAC_HDX 0x000c
167 #define AG71XX_REG_MAC_MFL 0x0010
168 #define AG71XX_REG_MII_CFG 0x0020
169 #define AG71XX_REG_MII_CMD 0x0024
170 #define AG71XX_REG_MII_ADDR 0x0028
171 #define AG71XX_REG_MII_CTRL 0x002c
172 #define AG71XX_REG_MII_STATUS 0x0030
173 #define AG71XX_REG_MII_IND 0x0034
174 #define AG71XX_REG_MAC_IFCTL 0x0038
175 #define AG71XX_REG_MAC_ADDR1 0x0040
176 #define AG71XX_REG_MAC_ADDR2 0x0044
177 #define AG71XX_REG_FIFO_CFG0 0x0048
178 #define AG71XX_REG_FIFO_CFG1 0x004c
179 #define AG71XX_REG_FIFO_CFG2 0x0050
180 #define AG71XX_REG_FIFO_CFG3 0x0054
181 #define AG71XX_REG_FIFO_CFG4 0x0058
182 #define AG71XX_REG_FIFO_CFG5 0x005c
183 #define AG71XX_REG_FIFO_RAM0 0x0060
184 #define AG71XX_REG_FIFO_RAM1 0x0064
185 #define AG71XX_REG_FIFO_RAM2 0x0068
186 #define AG71XX_REG_FIFO_RAM3 0x006c
187 #define AG71XX_REG_FIFO_RAM4 0x0070
188 #define AG71XX_REG_FIFO_RAM5 0x0074
189 #define AG71XX_REG_FIFO_RAM6 0x0078
190 #define AG71XX_REG_FIFO_RAM7 0x007c
191
192 #define AG71XX_REG_TX_CTRL 0x0180
193 #define AG71XX_REG_TX_DESC 0x0184
194 #define AG71XX_REG_TX_STATUS 0x0188
195 #define AG71XX_REG_RX_CTRL 0x018c
196 #define AG71XX_REG_RX_DESC 0x0190
197 #define AG71XX_REG_RX_STATUS 0x0194
198 #define AG71XX_REG_INT_ENABLE 0x0198
199 #define AG71XX_REG_INT_STATUS 0x019c
200
201 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
202 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
203 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
204 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
205 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
206 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
207 #define MAC_CFG1_LB BIT(8) /* Loopback mode */
208 #define MAC_CFG1_SR BIT(31) /* Soft Reset */
209
210 #define MAC_CFG2_FDX BIT(0)
211 #define MAC_CFG2_CRC_EN BIT(1)
212 #define MAC_CFG2_PAD_CRC_EN BIT(2)
213 #define MAC_CFG2_LEN_CHECK BIT(4)
214 #define MAC_CFG2_HUGE_FRAME_EN BIT(5)
215 #define MAC_CFG2_IF_1000 BIT(9)
216 #define MAC_CFG2_IF_10_100 BIT(8)
217
218 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
219 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
220 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
221 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
222 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
223 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
224 | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
225
226 #define FIFO_CFG0_ENABLE_SHIFT 8
227
228 #define FIFO_CFG4_DE BIT(0) /* Drop Event */
229 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
230 #define FIFO_CFG4_FC BIT(2) /* False Carrier */
231 #define FIFO_CFG4_CE BIT(3) /* Code Error */
232 #define FIFO_CFG4_CR BIT(4) /* CRC error */
233 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
234 #define FIFO_CFG4_LO BIT(6) /* Length out of range */
235 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */
236 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
237 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
238 #define FIFO_CFG4_DR BIT(10) /* Dribble */
239 #define FIFO_CFG4_LE BIT(11) /* Long Event */
240 #define FIFO_CFG4_CF BIT(12) /* Control Frame */
241 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */
242 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
243 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
244 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
245 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
246
247 #define FIFO_CFG5_DE BIT(0) /* Drop Event */
248 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
249 #define FIFO_CFG5_FC BIT(2) /* False Carrier */
250 #define FIFO_CFG5_CE BIT(3) /* Code Error */
251 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
252 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
253 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */
254 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
255 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
256 #define FIFO_CFG5_DR BIT(9) /* Dribble */
257 #define FIFO_CFG5_CF BIT(10) /* Control Frame */
258 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */
259 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
260 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
261 #define FIFO_CFG5_LE BIT(14) /* Long Event */
262 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
263 #define FIFO_CFG5_16 BIT(16) /* unknown */
264 #define FIFO_CFG5_17 BIT(17) /* unknown */
265 #define FIFO_CFG5_SF BIT(18) /* Short Frame */
266 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
267
268 #define AG71XX_INT_TX_PS BIT(0)
269 #define AG71XX_INT_TX_UR BIT(1)
270 #define AG71XX_INT_TX_BE BIT(3)
271 #define AG71XX_INT_RX_PR BIT(4)
272 #define AG71XX_INT_RX_OF BIT(6)
273 #define AG71XX_INT_RX_BE BIT(7)
274
275 #define MAC_IFCTL_SPEED BIT(16)
276
277 #define MII_CFG_CLK_DIV_4 0
278 #define MII_CFG_CLK_DIV_6 2
279 #define MII_CFG_CLK_DIV_8 3
280 #define MII_CFG_CLK_DIV_10 4
281 #define MII_CFG_CLK_DIV_14 5
282 #define MII_CFG_CLK_DIV_20 6
283 #define MII_CFG_CLK_DIV_28 7
284 #define MII_CFG_RESET BIT(31)
285
286 #define MII_CMD_WRITE 0x0
287 #define MII_CMD_READ 0x1
288 #define MII_ADDR_SHIFT 8
289 #define MII_IND_BUSY BIT(0)
290 #define MII_IND_INVALID BIT(2)
291
292 #define TX_CTRL_TXE BIT(0) /* Tx Enable */
293
294 #define TX_STATUS_PS BIT(0) /* Packet Sent */
295 #define TX_STATUS_UR BIT(1) /* Tx Underrun */
296 #define TX_STATUS_BE BIT(3) /* Bus Error */
297
298 #define RX_CTRL_RXE BIT(0) /* Rx Enable */
299
300 #define RX_STATUS_PR BIT(0) /* Packet Received */
301 #define RX_STATUS_OF BIT(2) /* Rx Overflow */
302 #define RX_STATUS_BE BIT(3) /* Bus Error */
303
304 #define MII_CTRL_IF_MASK 3
305 #define MII_CTRL_SPEED_SHIFT 4
306 #define MII_CTRL_SPEED_MASK 3
307 #define MII_CTRL_SPEED_10 0
308 #define MII_CTRL_SPEED_100 1
309 #define MII_CTRL_SPEED_1000 2
310
311 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
312 {
313 void __iomem *r;
314
315 switch (reg) {
316 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
317 r = ag->mac_base + reg;
318 __raw_writel(value, r);
319 __raw_readl(r);
320 break;
321 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
322 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
323 __raw_writel(value, r);
324 __raw_readl(r);
325 break;
326 default:
327 BUG();
328 }
329 }
330
331 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
332 {
333 void __iomem *r;
334 u32 ret;
335
336 switch (reg) {
337 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
338 r = ag->mac_base + reg;
339 ret = __raw_readl(r);
340 break;
341 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
342 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
343 ret = __raw_readl(r);
344 break;
345 default:
346 BUG();
347 }
348
349 return ret;
350 }
351
352 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
353 {
354 void __iomem *r;
355
356 switch (reg) {
357 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
358 r = ag->mac_base + reg;
359 __raw_writel(__raw_readl(r) | mask, r);
360 __raw_readl(r);
361 break;
362 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
363 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
364 __raw_writel(__raw_readl(r) | mask, r);
365 __raw_readl(r);
366 break;
367 default:
368 BUG();
369 }
370 }
371
372 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
373 {
374 void __iomem *r;
375
376 switch (reg) {
377 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
378 r = ag->mac_base + reg;
379 __raw_writel(__raw_readl(r) & ~mask, r);
380 __raw_readl(r);
381 break;
382 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
383 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
384 __raw_writel(__raw_readl(r) & ~mask, r);
385 __raw_readl(r);
386 break;
387 default:
388 BUG();
389 }
390 }
391
392 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
393 {
394 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
395 }
396
397 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
398 {
399 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
400 }
401
402 static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
403 {
404 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
405
406 if (pdata->is_ar724x)
407 return;
408
409 __raw_writel(value, ag->mii_ctrl);
410 __raw_readl(ag->mii_ctrl);
411 }
412
413 static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
414 {
415 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
416
417 if (pdata->is_ar724x)
418 return 0xffffffff;
419
420 return __raw_readl(ag->mii_ctrl);
421 }
422
423 static void inline ag71xx_mii_ctrl_set_if(struct ag71xx *ag,
424 unsigned int mii_if)
425 {
426 u32 t;
427
428 t = ag71xx_mii_ctrl_rr(ag);
429 t &= ~(MII_CTRL_IF_MASK);
430 t |= (mii_if & MII_CTRL_IF_MASK);
431 ag71xx_mii_ctrl_wr(ag, t);
432 }
433
434 static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
435 unsigned int speed)
436 {
437 u32 t;
438
439 t = ag71xx_mii_ctrl_rr(ag);
440 t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
441 t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
442 ag71xx_mii_ctrl_wr(ag, t);
443 }
444
445 #ifdef CONFIG_AG71XX_AR8216_SUPPORT
446 void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
447 int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
448 #else
449 static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
450 struct sk_buff *skb)
451 {
452 }
453
454 static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
455 struct sk_buff *skb)
456 {
457 return 0;
458 }
459 #endif
460
461 #endif /* _AG71XX_H */
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