ar71xx: prebuild all loaders in Image/Prepare stage
[openwrt.git] / target / linux / cns3xxx / patches / 105-cns3xxx_pcie_io.patch
1 --- a/arch/arm/mach-cns3xxx/core.c
2 +++ b/arch/arm/mach-cns3xxx/core.c
3 @@ -78,6 +78,16 @@ static struct map_desc cns3xxx_io_desc[]
4 .pfn = __phys_to_pfn(CNS3XXX_L2C_BASE),
5 .length = SZ_4K,
6 .type = MT_DEVICE,
7 + }, {
8 + .virtual = CNS3XXX_PCIE0_IO_BASE_VIRT,
9 + .pfn = __phys_to_pfn(CNS3XXX_PCIE0_IO_BASE),
10 + .length = SZ_16M,
11 + .type = MT_DEVICE,
12 + }, {
13 + .virtual = CNS3XXX_PCIE1_IO_BASE_VIRT,
14 + .pfn = __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE),
15 + .length = SZ_16M,
16 + .type = MT_DEVICE,
17 },
18 };
19
20 @@ -184,13 +194,13 @@ void __init cns3xxx_common_init(void)
21 /* used by entry-macro.S */
22 void __init cns3xxx_init_irq(void)
23 {
24 - gic_init(0, 29, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
25 - __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
26 + gic_init(0, 29, (void __iomem *) CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT,
27 + (void __iomem *) CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT);
28 }
29
30 void cns3xxx_power_off(void)
31 {
32 - u32 __iomem *pm_base = __io(CNS3XXX_PM_BASE_VIRT);
33 + u32 __iomem *pm_base = (void __iomem *) CNS3XXX_PM_BASE_VIRT;
34 u32 clkctrl;
35
36 printk(KERN_INFO "powering system down...\n");
37 @@ -364,7 +374,7 @@ static void __init __cns3xxx_timer_init(
38
39 static void __init cns3xxx_timer_init(void)
40 {
41 - cns3xxx_tmr1 = __io(CNS3XXX_TIMER1_2_3_BASE_VIRT);
42 + cns3xxx_tmr1 = (void __iomem *) CNS3XXX_TIMER1_2_3_BASE_VIRT;
43
44 __cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
45 }
46 --- a/arch/arm/mach-cns3xxx/devices.c
47 +++ b/arch/arm/mach-cns3xxx/devices.c
48 @@ -98,7 +98,7 @@ static struct platform_device cns3xxx_sd
49
50 void __init cns3xxx_sdhci_init(void)
51 {
52 - u32 __iomem *gpioa = __io(CNS3XXX_MISC_BASE_VIRT + 0x0014);
53 + u32 __iomem *gpioa = (void __iomem *) (CNS3XXX_MISC_BASE_VIRT + 0x0014);
54 u32 gpioa_pins = __raw_readl(gpioa);
55
56 /* MMC/SD pins share with GPIOA */
57 --- a/arch/arm/mach-cns3xxx/include/mach/io.h
58 +++ b/arch/arm/mach-cns3xxx/include/mach/io.h
59 @@ -9,9 +9,17 @@
60 #ifndef __MACH_IO_H
61 #define __MACH_IO_H
62
63 +#include "cns3xxx.h"
64 +
65 #define IO_SPACE_LIMIT 0xffffffff
66
67 -#define __io(a) __typesafe_io(a)
68 +static inline void __iomem *__io(unsigned long addr)
69 +{
70 + return (void __iomem *)((addr - CNS3XXX_PCIE0_IO_BASE)
71 + + CNS3XXX_PCIE0_IO_BASE_VIRT);
72 +}
73 +
74 +#define __io(a) __io(a)
75 #define __mem_pci(a) (a)
76
77 #endif
78 --- a/drivers/spi/spi_cns3xxx.c
79 +++ b/drivers/spi/spi_cns3xxx.c
80 @@ -273,7 +273,7 @@ done:
81
82 static void __init cns3xxx_spi_initial(void)
83 {
84 - u32 __iomem *gpiob = __io(CNS3XXX_MISC_BASE_VIRT + 0x0018);
85 + u32 __iomem *gpiob = (void __iomem *) (CNS3XXX_MISC_BASE_VIRT + 0x0018);
86 u32 gpiob_pins = __raw_readl(gpiob);
87
88 /* MMC/SD pins share with GPIOA */
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