3 #include <linux/interrupt.h>
6 #include <linux/ssb/ssb.h>
7 #include <linux/ssb/ssb_driver_chipcommon.h>
8 #include <linux/ssb/ssb_driver_extif.h>
10 extern struct ssb_bus ssb
;
12 #define gpio_op(op, param...) \
15 return ssb_chipco_gpio_##op(&ssb.chipco, param); \
16 else if (ssb.extif.dev) \
17 return ssb_extif_gpio_##op(&ssb.extif, param); \
23 static inline u32
gpio_in(void)
28 static inline u32
gpio_out(u32 mask
, u32 value
)
30 gpio_op(out
, mask
, value
);
33 static inline u32
gpio_outen(u32 mask
, u32 value
)
35 gpio_op(outen
, mask
, value
);
38 static inline u32
gpio_control(u32 mask
, u32 value
)
41 return ssb_chipco_gpio_control(&ssb
.chipco
, mask
, value
);
46 static inline u32
gpio_intmask(u32 mask
, u32 value
)
48 gpio_op(intmask
, mask
, value
);
51 static inline u32
gpio_intpolarity(u32 mask
, u32 value
)
53 gpio_op(polarity
, mask
, value
);
56 static void gpio_set_irqenable(int enabled
, irqreturn_t (*handler
)(int, void *))
61 irq
= ssb_mips_irq(ssb
.chipco
.dev
) + 2;
62 else if (ssb
.extif
.dev
)
63 irq
= ssb_mips_irq(ssb
.extif
.dev
) + 2;
67 if (request_irq(irq
, handler
, IRQF_SHARED
| IRQF_SAMPLE_RANDOM
, "gpio", handler
))
70 free_irq(irq
, handler
);
74 ssb_write32_masked(ssb
.chipco
.dev
, SSB_CHIPCO_IRQMASK
, SSB_CHIPCO_IRQ_GPIO
, (enabled
? SSB_CHIPCO_IRQ_GPIO
: 0));
85 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
91 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
92 #define sbh bcm947xx_sbh
93 #define sbh_lock bcm947xx_sbh_lock
97 extern spinlock_t sbh_lock
;
99 #define gpio_in() sb_gpioin(sbh)
100 #define gpio_out(mask, value) sb_gpioout(sbh, mask, ((value) & (mask)), GPIO_DRV_PRIORITY)
101 #define gpio_outen(mask, value) sb_gpioouten(sbh, mask, value, GPIO_DRV_PRIORITY)
102 #define gpio_control(mask, value) sb_gpiocontrol(sbh, mask, value, GPIO_DRV_PRIORITY)
103 #define gpio_intmask(mask, value) sb_gpiointmask(sbh, mask, value, GPIO_DRV_PRIORITY)
104 #define gpio_intpolarity(mask, value) sb_gpiointpolarity(sbh, mask, value, GPIO_DRV_PRIORITY)
106 static void gpio_set_irqenable(int enabled
, irqreturn_t (*handler
)(int, void *, struct pt_regs
*))
108 unsigned int coreidx
;
113 spin_lock_irqsave(sbh_lock
, flags
);
114 coreidx
= sb_coreidx(sbh
);
116 irq
= sb_irq(sbh
) + 2;
118 request_irq(irq
, handler
, SA_SHIRQ
| SA_SAMPLE_RANDOM
, "gpio", handler
);
120 free_irq(irq
, handler
);
122 if ((cc
= sb_setcore(sbh
, SB_CC
, 0))) {
125 intmask
= readl(&cc
->intmask
);
130 writel(intmask
, &cc
->intmask
);
132 sb_setcoreidx(sbh
, coreidx
);
133 spin_unlock_irqrestore(sbh_lock
, flags
);
136 #endif /* BCMDRIVER */
138 #define EXTIF_ADDR 0x1f000000
139 #define EXTIF_UART (EXTIF_ADDR + 0x00800000)
141 #define GPIO_TYPE_NORMAL (0x0 << 24)
142 #define GPIO_TYPE_EXTIF (0x1 << 24)
143 #define GPIO_TYPE_MASK (0xf << 24)
145 static inline void gpio_set_extif(int gpio
, int value
)
147 volatile u8
*addr
= (volatile u8
*) KSEG1ADDR(EXTIF_UART
) + (gpio
& ~GPIO_TYPE_MASK
);
154 #endif /* __DIAG_GPIO_H */
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