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enable wlc by default
[openwrt.git] / target / linux / brcm-2.4 / patches / 001-bcm47xx.patch
1 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
2 --- linux.old/arch/mips/Makefile 2006-04-27 18:04:37.000000000 +0200
3 +++ linux.dev/arch/mips/Makefile 2006-04-27 19:24:19.000000000 +0200
4 @@ -726,6 +726,19 @@
5 endif
6
7 #
8 +# Broadcom BCM947XX variants
9 +#
10 +ifdef CONFIG_BCM947XX
11 +LIBS += arch/mips/bcm947xx/generic/brcm.o arch/mips/bcm947xx/bcm947xx.o
12 +SUBDIRS += arch/mips/bcm947xx/generic arch/mips/bcm947xx
13 +LOADADDR := 0x80001000
14 +
15 +zImage: vmlinux
16 + $(MAKE) -C arch/$(ARCH)/bcm947xx/compressed
17 +export LOADADDR
18 +endif
19 +
20 +#
21 # Choosing incompatible machines durings configuration will result in
22 # error messages during linking. Select a default linkscript if
23 # none has been choosen above.
24 @@ -778,6 +791,7 @@
25 $(MAKE) -C arch/$(ARCH)/tools clean
26 $(MAKE) -C arch/mips/baget clean
27 $(MAKE) -C arch/mips/lasat clean
28 + $(MAKE) -C arch/mips/bcm947xx/compressed clean
29
30 archmrproper:
31 @$(MAKEBOOT) mrproper
32 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
33 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
34 +++ linux.dev/arch/mips/bcm947xx/Makefile 2006-05-02 17:46:22.000000000 +0200
35 @@ -0,0 +1,17 @@
36 +#
37 +# Makefile for the BCM947xx specific kernel interface routines
38 +# under Linux.
39 +#
40 +
41 +EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
42 +
43 +O_TARGET := bcm947xx.o
44 +
45 +export-objs := export.o
46 +obj-y := prom.o setup.o time.o sbmips.o gpio.o
47 +obj-y += nvram.o nvram_linux.o sflash.o cfe_env.o
48 +obj-y += sbutils.o bcmutils.o bcmsrom.o hndchipc.o
49 +obj-$(CONFIG_PCI) += sbpci.o pcibios.o
50 +obj-y += export.o
51 +
52 +include $(TOPDIR)/Rules.make
53 diff -urN linux.old/arch/mips/bcm947xx/bcmsrom.c linux.dev/arch/mips/bcm947xx/bcmsrom.c
54 --- linux.old/arch/mips/bcm947xx/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
55 +++ linux.dev/arch/mips/bcm947xx/bcmsrom.c 2006-04-27 20:32:48.000000000 +0200
56 @@ -0,0 +1,1212 @@
57 +/*
58 + * Misc useful routines to access NIC SROM/OTP .
59 + *
60 + * Copyright 2006, Broadcom Corporation
61 + * All Rights Reserved.
62 + *
63 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
64 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
65 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
66 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
67 + * $Id: bcmsrom.c,v 1.1.1.14 2006/04/15 01:28:25 michael Exp $
68 + */
69 +
70 +#include <typedefs.h>
71 +#include <bcmdefs.h>
72 +#include <osl.h>
73 +#include <bcmutils.h>
74 +#include <bcmsrom.h>
75 +#include <bcmdevs.h>
76 +#include <bcmendian.h>
77 +#include <sbpcmcia.h>
78 +#include <pcicfg.h>
79 +#include <sbutils.h>
80 +#include <bcmnvram.h>
81 +
82 +/* debug/trace */
83 +#if defined(WLTEST)
84 +#define BS_ERROR(args) printf args
85 +#else
86 +#define BS_ERROR(args)
87 +#endif /* BCMDBG_ERR || WLTEST */
88 +
89 +#define VARS_MAX 4096 /* should be reduced */
90 +
91 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
92 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
93 +
94 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, uint *count);
95 +static int initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, uint *count);
96 +static int initvars_flash_sb(void *sbh, char **vars, uint *count);
97 +static int srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, char **vars, uint *count);
98 +static int sprom_cmd_pcmcia(osl_t *osh, uint8 cmd);
99 +static int sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data);
100 +static int sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data);
101 +static int sprom_read_pci(osl_t *osh, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords,
102 + bool check_crc);
103 +
104 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
105 +static int initvars_flash(osl_t *osh, char **vp, uint len, char *devpath);
106 +
107 +/*
108 + * Initialize local vars from the right source for this platform.
109 + * Return 0 on success, nonzero on error.
110 + */
111 +int
112 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, uint *count)
113 +{
114 + ASSERT(bustype == BUSTYPE(bustype));
115 + if (vars == NULL || count == NULL)
116 + return (0);
117 +
118 + switch (BUSTYPE(bustype)) {
119 + case SB_BUS:
120 + case JTAG_BUS:
121 + return initvars_flash_sb(sbh, vars, count);
122 +
123 + case PCI_BUS:
124 + ASSERT(curmap); /* can not be NULL */
125 + return initvars_srom_pci(sbh, curmap, vars, count);
126 +
127 + case PCMCIA_BUS:
128 + return initvars_cis_pcmcia(sbh, osh, vars, count);
129 +
130 +
131 + default:
132 + ASSERT(0);
133 + }
134 + return (-1);
135 +}
136 +
137 +/* support only 16-bit word read from srom */
138 +int
139 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
140 +{
141 + void *srom;
142 + uint i, off, nw;
143 +
144 + ASSERT(bustype == BUSTYPE(bustype));
145 +
146 + /* check input - 16-bit access only */
147 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
148 + return 1;
149 +
150 + off = byteoff / 2;
151 + nw = nbytes / 2;
152 +
153 + if (BUSTYPE(bustype) == PCI_BUS) {
154 + if (!curmap)
155 + return 1;
156 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
157 + if (sprom_read_pci(osh, srom, off, buf, nw, FALSE))
158 + return 1;
159 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
160 + for (i = 0; i < nw; i++) {
161 + if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
162 + return 1;
163 + }
164 + } else {
165 + return 1;
166 + }
167 +
168 + return 0;
169 +}
170 +
171 +/* support only 16-bit word write into srom */
172 +int
173 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
174 +{
175 + uint16 *srom;
176 + uint i, nw, crc_range;
177 + uint16 image[SPROM_SIZE];
178 + uint8 crc;
179 + volatile uint32 val32;
180 +
181 + ASSERT(bustype == BUSTYPE(bustype));
182 +
183 + /* check input - 16-bit access only */
184 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
185 + return 1;
186 +
187 + /* Are we writing the whole thing at once? */
188 + if ((byteoff == 0) &&
189 + ((nbytes == SPROM_SIZE) ||
190 + (nbytes == (SPROM_CRC_RANGE * 2)) ||
191 + (nbytes == (SROM4_WORDS * 2)))) {
192 + crc_range = nbytes;
193 + bcopy((void*)buf, (void*)image, nbytes);
194 + nw = nbytes / 2;
195 + } else {
196 + if ((BUSTYPE(bustype) == PCMCIA_BUS) || (BUSTYPE(bustype) == SDIO_BUS))
197 + crc_range = SPROM_SIZE;
198 + else
199 + crc_range = SPROM_CRC_RANGE * 2; /* Tentative */
200 +
201 + nw = crc_range / 2;
202 + /* read first 64 words from srom */
203 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
204 + return 1;
205 + if (image[SROM4_SIGN] == SROM4_SIGNATURE) {
206 + crc_range = SROM4_WORDS;
207 + nw = crc_range / 2;
208 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
209 + return 1;
210 + }
211 + /* make changes */
212 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
213 + }
214 +
215 + /* calculate crc */
216 + htol16_buf(image, crc_range);
217 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
218 + ltoh16_buf(image, crc_range);
219 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
220 +
221 + if (BUSTYPE(bustype) == PCI_BUS) {
222 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
223 + /* enable writes to the SPROM */
224 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
225 + val32 |= SPROM_WRITEEN;
226 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
227 + bcm_mdelay(WRITE_ENABLE_DELAY);
228 + /* write srom */
229 + for (i = 0; i < nw; i++) {
230 + W_REG(osh, &srom[i], image[i]);
231 + bcm_mdelay(WRITE_WORD_DELAY);
232 + }
233 + /* disable writes to the SPROM */
234 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 &
235 + ~SPROM_WRITEEN);
236 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
237 + /* enable writes to the SPROM */
238 + if (sprom_cmd_pcmcia(osh, SROM_WEN))
239 + return 1;
240 + bcm_mdelay(WRITE_ENABLE_DELAY);
241 + /* write srom */
242 + for (i = 0; i < nw; i++) {
243 + sprom_write_pcmcia(osh, (uint16)(i), image[i]);
244 + bcm_mdelay(WRITE_WORD_DELAY);
245 + }
246 + /* disable writes to the SPROM */
247 + if (sprom_cmd_pcmcia(osh, SROM_WDS))
248 + return 1;
249 + } else {
250 + return 1;
251 + }
252 +
253 + bcm_mdelay(WRITE_ENABLE_DELAY);
254 + return 0;
255 +}
256 +
257 +
258 +static int
259 +srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, char **vars, uint *count)
260 +{
261 + char eabuf[32];
262 + char *vp, *base;
263 + uint8 *cis, tup, tlen, sromrev = 1;
264 + int i, j;
265 + uint varsize;
266 + bool ag_init = FALSE;
267 + uint32 w32;
268 +
269 + ASSERT(vars);
270 + ASSERT(count);
271 +
272 + base = vp = MALLOC(osh, VARS_MAX);
273 + ASSERT(vp);
274 + if (!vp)
275 + return -2;
276 +
277 + while (ciscnt--) {
278 + cis = *pcis++;
279 + i = 0;
280 + do {
281 + tup = cis[i++];
282 + tlen = cis[i++];
283 + if ((i + tlen) >= CIS_SIZE)
284 + break;
285 +
286 + switch (tup) {
287 + case CISTPL_MANFID:
288 + vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
289 + vp++;
290 + vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
291 + vp++;
292 + break;
293 +
294 + case CISTPL_FUNCE:
295 + switch (cis[i]) {
296 + case LAN_NID:
297 + ASSERT(cis[i + 1] == 6);
298 + bcm_ether_ntoa((struct ether_addr *)&cis[i + 2], eabuf);
299 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
300 + vp++;
301 + break;
302 + case 1: /* SDIO Extended Data */
303 + vp += sprintf(vp, "sdmaxblk=%d",
304 + (cis[i + 13] << 8) | cis[i + 12]);
305 + vp++;
306 + break;
307 + }
308 + break;
309 +
310 + case CISTPL_CFTABLE:
311 + vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
312 + vp++;
313 + break;
314 +
315 + case CISTPL_BRCM_HNBU:
316 + switch (cis[i]) {
317 + case HNBU_SROMREV:
318 + sromrev = cis[i + 1];
319 + break;
320 +
321 + case HNBU_CHIPID:
322 + vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) +
323 + cis[i + 1]);
324 + vp++;
325 + vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) +
326 + cis[i + 3]);
327 + vp++;
328 + if (tlen == 7) {
329 + vp += sprintf(vp, "chiprev=%d",
330 + (cis[i + 6] << 8) + cis[i + 5]);
331 + vp++;
332 + }
333 + break;
334 +
335 + case HNBU_BOARDREV:
336 + vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
337 + vp++;
338 + break;
339 +
340 + case HNBU_AA:
341 + vp += sprintf(vp, "aa2g=%d", cis[i + 1]);
342 + vp++;
343 + break;
344 +
345 + case HNBU_AG:
346 + vp += sprintf(vp, "ag0=%d", cis[i + 1]);
347 + vp++;
348 + ag_init = TRUE;
349 + break;
350 +
351 + case HNBU_CC:
352 + ASSERT(sromrev == 1);
353 + vp += sprintf(vp, "cc=%d", cis[i + 1]);
354 + vp++;
355 + break;
356 +
357 + case HNBU_PAPARMS:
358 + if (tlen == 2) {
359 + ASSERT(sromrev == 1);
360 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 1]);
361 + vp++;
362 + } else if (tlen >= 9) {
363 + if (tlen == 10) {
364 + ASSERT(sromrev == 2);
365 + vp += sprintf(vp, "opo=%d", cis[i + 9]);
366 + vp++;
367 + } else
368 + ASSERT(tlen == 9);
369 +
370 + for (j = 0; j < 3; j++) {
371 + vp += sprintf(vp, "pa0b%d=%d", j,
372 + (cis[i + (j * 2) + 2] << 8) +
373 + cis[i + (j * 2) + 1]);
374 + vp++;
375 + }
376 + vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
377 + vp++;
378 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 8]);
379 + vp++;
380 + } else
381 + ASSERT(tlen >= 9);
382 + break;
383 +
384 + case HNBU_OEM:
385 + ASSERT(sromrev == 1);
386 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
387 + cis[i + 1], cis[i + 2],
388 + cis[i + 3], cis[i + 4],
389 + cis[i + 5], cis[i + 6],
390 + cis[i + 7], cis[i + 8]);
391 + vp++;
392 + break;
393 +
394 + case HNBU_BOARDFLAGS:
395 + w32 = (cis[i + 2] << 8) + cis[i + 1];
396 + if (tlen == 5)
397 + w32 |= (cis[i + 4] << 24) + (cis[i + 3] << 16);
398 + vp += sprintf(vp, "boardflags=0x%x", w32);
399 + vp++;
400 + break;
401 +
402 + case HNBU_LEDS:
403 + if (cis[i + 1] != 0xff) {
404 + vp += sprintf(vp, "ledbh0=%d", cis[i + 1]);
405 + vp++;
406 + }
407 + if (cis[i + 2] != 0xff) {
408 + vp += sprintf(vp, "ledbh1=%d", cis[i + 2]);
409 + vp++;
410 + }
411 + if (cis[i + 3] != 0xff) {
412 + vp += sprintf(vp, "ledbh2=%d", cis[i + 3]);
413 + vp++;
414 + }
415 + if (cis[i + 4] != 0xff) {
416 + vp += sprintf(vp, "ledbh3=%d", cis[i + 4]);
417 + vp++;
418 + }
419 + break;
420 +
421 + case HNBU_CCODE:
422 + {
423 + char str[3];
424 + ASSERT(sromrev > 1);
425 + str[0] = cis[i + 1];
426 + str[1] = cis[i + 2];
427 + str[2] = 0;
428 + vp += sprintf(vp, "ccode=%s", str);
429 + vp++;
430 + vp += sprintf(vp, "cctl=0x%x", cis[i + 3]);
431 + vp++;
432 + break;
433 + }
434 +
435 + case HNBU_CCKPO:
436 + ASSERT(sromrev > 2);
437 + vp += sprintf(vp, "cckpo=0x%x",
438 + (cis[i + 2] << 8) | cis[i + 1]);
439 + vp++;
440 + break;
441 +
442 + case HNBU_OFDMPO:
443 + ASSERT(sromrev > 2);
444 + vp += sprintf(vp, "ofdmpo=0x%x",
445 + (cis[i + 4] << 24) |
446 + (cis[i + 3] << 16) |
447 + (cis[i + 2] << 8) |
448 + cis[i + 1]);
449 + vp++;
450 + break;
451 + }
452 + break;
453 +
454 + }
455 + i += tlen;
456 + } while (tup != 0xff);
457 + }
458 +
459 + /* Set the srom version */
460 + vp += sprintf(vp, "sromrev=%d", sromrev);
461 + vp++;
462 +
463 + /* if there is no antenna gain field, set default */
464 + if (ag_init == FALSE) {
465 + ASSERT(sromrev == 1);
466 + vp += sprintf(vp, "ag0=%d", 0xff);
467 + vp++;
468 + }
469 +
470 + /* final nullbyte terminator */
471 + *vp++ = '\0';
472 + varsize = (uint)(vp - base);
473 +
474 + ASSERT((vp - base) < VARS_MAX);
475 +
476 + if (varsize == VARS_MAX) {
477 + *vars = base;
478 + } else {
479 + vp = MALLOC(osh, varsize);
480 + ASSERT(vp);
481 + if (vp)
482 + bcopy(base, vp, varsize);
483 + MFREE(osh, base, VARS_MAX);
484 + *vars = vp;
485 + if (!vp) {
486 + *count = 0;
487 + return -2;
488 + }
489 + }
490 + *count = varsize;
491 +
492 + return (0);
493 +}
494 +
495 +
496 +/* set PCMCIA sprom command register */
497 +static int
498 +sprom_cmd_pcmcia(osl_t *osh, uint8 cmd)
499 +{
500 + uint8 status = 0;
501 + uint wait_cnt = 1000;
502 +
503 + /* write sprom command register */
504 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
505 +
506 + /* wait status */
507 + while (wait_cnt--) {
508 + OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
509 + if (status & SROM_DONE)
510 + return 0;
511 + }
512 +
513 + return 1;
514 +}
515 +
516 +/* read a word from the PCMCIA srom */
517 +static int
518 +sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data)
519 +{
520 + uint8 addr_l, addr_h, data_l, data_h;
521 +
522 + addr_l = (uint8)((addr * 2) & 0xff);
523 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
524 +
525 + /* set address */
526 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
527 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
528 +
529 + /* do read */
530 + if (sprom_cmd_pcmcia(osh, SROM_READ))
531 + return 1;
532 +
533 + /* read data */
534 + data_h = data_l = 0;
535 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
536 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
537 +
538 + *data = (data_h << 8) | data_l;
539 + return 0;
540 +}
541 +
542 +/* write a word to the PCMCIA srom */
543 +static int
544 +sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data)
545 +{
546 + uint8 addr_l, addr_h, data_l, data_h;
547 +
548 + addr_l = (uint8)((addr * 2) & 0xff);
549 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
550 + data_l = (uint8)(data & 0xff);
551 + data_h = (uint8)((data >> 8) & 0xff);
552 +
553 + /* set address */
554 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
555 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
556 +
557 + /* write data */
558 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
559 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
560 +
561 + /* do write */
562 + return sprom_cmd_pcmcia(osh, SROM_WRITE);
563 +}
564 +
565 +/*
566 + * Read in and validate sprom.
567 + * Return 0 on success, nonzero on error.
568 + */
569 +static int
570 +sprom_read_pci(osl_t *osh, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
571 +{
572 + int err = 0;
573 + uint i;
574 +
575 + /* read the sprom */
576 + for (i = 0; i < nwords; i++)
577 + buf[i] = R_REG(osh, &sprom[wordoff + i]);
578 +
579 + if (check_crc) {
580 + /* fixup the endianness so crc8 will pass */
581 + htol16_buf(buf, nwords * 2);
582 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
583 + err = 1;
584 + /* now correct the endianness of the byte array */
585 + ltoh16_buf(buf, nwords * 2);
586 + }
587 +
588 + return err;
589 +}
590 +
591 +/*
592 +* Create variable table from memory.
593 +* Return 0 on success, nonzero on error.
594 +*/
595 +static int
596 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
597 +{
598 + int c = (int)(end - start);
599 +
600 + /* do it only when there is more than just the null string */
601 + if (c > 1) {
602 + char *vp = MALLOC(osh, c);
603 + ASSERT(vp);
604 + if (!vp)
605 + return BCME_NOMEM;
606 + bcopy(start, vp, c);
607 + *vars = vp;
608 + *count = c;
609 + }
610 + else {
611 + *vars = NULL;
612 + *count = 0;
613 + }
614 +
615 + return 0;
616 +}
617 +
618 +/*
619 + * Find variables with <devpath> from flash. 'base' points to the beginning
620 + * of the table upon enter and to the end of the table upon exit when success.
621 + * Return 0 on success, nonzero on error.
622 + */
623 +static int
624 +initvars_flash(osl_t *osh, char **base, uint len, char *devpath)
625 +{
626 + char *vp = *base;
627 + char *flash;
628 + int err;
629 + char *s;
630 + uint l, dl, copy_len;
631 +
632 + /* allocate memory and read in flash */
633 + if (!(flash = MALLOC(osh, NVRAM_SPACE)))
634 + return BCME_NOMEM;
635 + if ((err = nvram_getall(flash, NVRAM_SPACE)))
636 + goto exit;
637 +
638 + /* grab vars with the <devpath> prefix in name */
639 + dl = strlen(devpath);
640 + for (s = flash; s && *s; s += l + 1) {
641 + l = strlen(s);
642 +
643 + /* skip non-matching variable */
644 + if (strncmp(s, devpath, dl))
645 + continue;
646 +
647 + /* is there enough room to copy? */
648 + copy_len = l - dl + 1;
649 + if (len < copy_len) {
650 + err = BCME_BUFTOOSHORT;
651 + goto exit;
652 + }
653 +
654 + /* no prefix, just the name=value */
655 + strcpy(vp, &s[dl]);
656 + vp += copy_len;
657 + len -= copy_len;
658 + }
659 +
660 + /* add null string as terminator */
661 + if (len < 1) {
662 + err = BCME_BUFTOOSHORT;
663 + goto exit;
664 + }
665 + *vp++ = '\0';
666 +
667 + *base = vp;
668 +
669 +exit: MFREE(osh, flash, NVRAM_SPACE);
670 + return err;
671 +}
672 +
673 +/*
674 + * Initialize nonvolatile variable table from flash.
675 + * Return 0 on success, nonzero on error.
676 + */
677 +static int
678 +initvars_flash_sb(void *sbh, char **vars, uint *count)
679 +{
680 + osl_t *osh = sb_osh(sbh);
681 + char devpath[SB_DEVPATH_BUFSZ];
682 + char *vp, *base;
683 + int err;
684 +
685 + ASSERT(vars);
686 + ASSERT(count);
687 +
688 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
689 + return err;
690 +
691 + base = vp = MALLOC(osh, VARS_MAX);
692 + ASSERT(vp);
693 + if (!vp)
694 + return BCME_NOMEM;
695 +
696 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
697 + goto err;
698 +
699 + err = initvars_table(osh, base, vp, vars, count);
700 +
701 +err: MFREE(osh, base, VARS_MAX);
702 + return err;
703 +}
704 +
705 +#ifdef WLTEST
706 +char mfgsromvars[256];
707 +char *defaultsromvars = "il0macaddr=00:11:22:33:44:51\0"
708 + "et0macaddr=00:11:22:33:44:52\0"
709 + "et1macaddr=00:11:22:33:44:53\0"
710 + "boardtype=0xffff\0"
711 + "boardrev=0x10\0"
712 + "boardflags=8\0"
713 + "sromrev=2\0"
714 + "aa2g=3";
715 +#define MFGSROM_DEFVARSLEN 147 /* default srom len */
716 +#endif /* WL_TEST */
717 +
718 +/*
719 + * Initialize nonvolatile variable table from sprom.
720 + * Return 0 on success, nonzero on error.
721 + */
722 +static int
723 +initvars_srom_pci(void *sbh, void *curmap, char **vars, uint *count)
724 +{
725 + uint16 w, *b;
726 + uint8 sromrev = 0;
727 + struct ether_addr ea;
728 + char eabuf[32];
729 + uint32 w32;
730 + int woff, i;
731 + char *vp, *base;
732 + osl_t *osh = sb_osh(sbh);
733 + bool flash = FALSE;
734 + char name[SB_DEVPATH_BUFSZ+16], *value;
735 + char devpath[SB_DEVPATH_BUFSZ];
736 + int err;
737 +
738 + /*
739 + * Apply CRC over SROM content regardless SROM is present or not,
740 + * and use variable <devpath>sromrev's existance in flash to decide
741 + * if we should return an error when CRC fails or read SROM variables
742 + * from flash.
743 + */
744 + b = MALLOC(osh, SROM_MAX);
745 + ASSERT(b);
746 + if (!b)
747 + return -2;
748 +
749 + err = sprom_read_pci(osh, (void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b,
750 + 64, TRUE);
751 + if (err == 0) {
752 + /* srom is good and is rev < 4 */
753 + /* top word of sprom contains version and crc8 */
754 + sromrev = b[63] & 0xff;
755 + /* bcm4401 sroms misprogrammed */
756 + if (sromrev == 0x10)
757 + sromrev = 1;
758 + } else if (b[SROM4_SIGN] == SROM4_SIGNATURE) {
759 + /* If sromrev >= 4, read more */
760 + err = sprom_read_pci(osh, (void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b,
761 + SROM4_WORDS, TRUE);
762 + sromrev = b[SROM4_WORDS - 1] & 0xff;
763 + }
764 +
765 + if (err) {
766 +#ifdef WLTEST
767 + BS_ERROR(("SROM Crc Error, so see if we could use a default\n"));
768 + w32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
769 + if (w32 & SPROM_OTPIN_USE) {
770 + BS_ERROR(("srom crc failed with OTP, use default vars....\n"));
771 + vp = base = mfgsromvars;
772 + if (sb_chip(sbh) == BCM4311_CHIP_ID) {
773 + BS_ERROR(("setting the devid to be 4311\n"));
774 + vp += sprintf(vp, "devid=0x4311");
775 + vp++;
776 + }
777 + bcopy(defaultsromvars, vp, MFGSROM_DEFVARSLEN);
778 + vp += MFGSROM_DEFVARSLEN;
779 + goto varsdone;
780 + } else {
781 + BS_ERROR(("srom crc failed with SPROM....\n"));
782 +#endif /* WLTEST */
783 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
784 + return err;
785 + sprintf(name, "%ssromrev", devpath);
786 + if (!(value = getvar(NULL, name)))
787 + return (-1);
788 + sromrev = (uint8)bcm_strtoul(value, NULL, 0);
789 + flash = TRUE;
790 +#ifdef WLTEST
791 + }
792 +#endif /* WLTEST */
793 + }
794 +
795 + /* srom version check */
796 + if (sromrev > 4)
797 + return (-2);
798 +
799 + ASSERT(vars);
800 + ASSERT(count);
801 +
802 + base = vp = MALLOC(osh, VARS_MAX);
803 + ASSERT(vp);
804 + if (!vp)
805 + return -2;
806 +
807 + /* read variables from flash */
808 + if (flash) {
809 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
810 + goto err;
811 + goto varsdone;
812 + }
813 +
814 + vp += sprintf(vp, "sromrev=%d", sromrev);
815 + vp++;
816 +
817 + if (sromrev >= 4) {
818 + uint path, pathbase;
819 + const uint pathbases[MAX_PATH] = {SROM4_PATH0, SROM4_PATH1,
820 + SROM4_PATH2, SROM4_PATH3};
821 +
822 + vp += sprintf(vp, "boardrev=%d", b[SROM4_BREV]);
823 + vp++;
824 +
825 + vp += sprintf(vp, "boardflags=%d", (b[SROM4_BFL1] << 16) | b[SROM4_BFL0]);
826 + vp++;
827 +
828 + vp += sprintf(vp, "boardflags2=%d", (b[SROM4_BFL3] << 16) | b[SROM4_BFL2]);
829 + vp++;
830 +
831 + /* The macaddr */
832 + ea.octet[0] = (b[SROM4_MACHI] >> 8) & 0xff;
833 + ea.octet[1] = b[SROM4_MACHI] & 0xff;
834 + ea.octet[2] = (b[SROM4_MACMID] >> 8) & 0xff;
835 + ea.octet[3] = b[SROM4_MACMID] & 0xff;
836 + ea.octet[4] = (b[SROM4_MACLO] >> 8) & 0xff;
837 + ea.octet[5] = b[SROM4_MACLO] & 0xff;
838 + bcm_ether_ntoa(&ea, eabuf);
839 + vp += sprintf(vp, "macaddr=%s", eabuf);
840 + vp++;
841 +
842 + w = b[SROM4_CCODE];
843 + if (w == 0)
844 + vp += sprintf(vp, "ccode=");
845 + else
846 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
847 + vp++;
848 + vp += sprintf(vp, "regrev=%d", b[SROM4_REGREV]);
849 + vp++;
850 +
851 + w = b[SROM4_LEDBH10];
852 + if ((w != 0) && (w != 0xffff)) {
853 + /* ledbh0 */
854 + vp += sprintf(vp, "ledbh0=%d", (w & 0xff));
855 + vp++;
856 +
857 + /* ledbh1 */
858 + vp += sprintf(vp, "ledbh1=%d", (w >> 8) & 0xff);
859 + vp++;
860 + }
861 + w = b[SROM4_LEDBH32];
862 + if ((w != 0) && (w != 0xffff)) {
863 + /* ledbh2 */
864 + vp += sprintf(vp, "ledbh2=%d", w & 0xff);
865 + vp++;
866 +
867 + /* ledbh3 */
868 + vp += sprintf(vp, "ledbh3=%d", (w >> 8) & 0xff);
869 + vp++;
870 + }
871 + /* LED Powersave duty cycle (oncount >> 24) (offcount >> 8) */
872 + w = b[SROM4_LEDDC];
873 + w32 = ((uint32)((unsigned char)(w >> 8) & 0xff) << 24) | /* oncount */
874 + ((uint32)((unsigned char)(w & 0xff)) << 8); /* offcount */
875 + vp += sprintf(vp, "leddc=%d", w32);
876 + vp++;
877 +
878 + w = b[SROM4_AA];
879 + vp += sprintf(vp, "aa2g=%d", w & SROM4_AA2G_MASK);
880 + vp++;
881 + vp += sprintf(vp, "aa5g=%d", w >> SROM4_AA5G_SHIFT);
882 + vp++;
883 +
884 + w = b[SROM4_AG10];
885 + vp += sprintf(vp, "ag0=%d", w & 0xff);
886 + vp++;
887 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
888 + vp++;
889 + w = b[SROM4_AG32];
890 + vp += sprintf(vp, "ag2=%d", w & 0xff);
891 + vp++;
892 + vp += sprintf(vp, "ag3=%d", (w >> 8) & 0xff);
893 + vp++;
894 +
895 + /* Fixed power indices when power control is disabled */
896 + for (i = 0; i < 2; i++) {
897 + w = b[SROM4_TXPID2G + i];
898 + vp += sprintf(vp, "txpid2ga%d=%d", 2 * i, w & 0xff);
899 + vp++;
900 + vp += sprintf(vp, "txpid2ga%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
901 + vp++;
902 + w = b[SROM4_TXPID5G + i];
903 + vp += sprintf(vp, "txpid5ga%d=%d", 2 * i, w & 0xff);
904 + vp++;
905 + vp += sprintf(vp, "txpid5ga%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
906 + vp++;
907 + w = b[SROM4_TXPID5GL + i];
908 + vp += sprintf(vp, "txpid5gla%d=%d", 2 * i, w & 0xff);
909 + vp++;
910 + vp += sprintf(vp, "txpid5gla%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
911 + vp++;
912 + w = b[SROM4_TXPID5GH + i];
913 + vp += sprintf(vp, "txpid5gha%d=%d", 2 * i, w & 0xff);
914 + vp++;
915 + vp += sprintf(vp, "txpid5gha%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
916 + vp++;
917 + }
918 +
919 + /* Per path variables */
920 + for (path = 0; path < MAX_PATH; path++) {
921 + pathbase = pathbases[path];
922 + w = b[pathbase + SROM4_2G_ITT_MAXP];
923 + vp += sprintf(vp, "itt2ga%d=%d", path, w >> B2G_ITT_SHIFT);
924 + vp++;
925 + vp += sprintf(vp, "maxp2ga%d=%d", path, w & B2G_MAXP_MASK);
926 + vp++;
927 +
928 + for (i = 0; i < 4; i++) {
929 + vp += sprintf(vp, "pa2gw%da%d=%d", i, path,
930 + b[pathbase + SROM4_2G_PA + i]);
931 + vp++;
932 + }
933 +
934 + w = b[pathbase + SROM4_5G_ITT_MAXP];
935 + vp += sprintf(vp, "itt5ga%d=%d", path, w >> B5G_ITT_SHIFT);
936 + vp++;
937 + vp += sprintf(vp, "maxp5ga%d=%d", path, w & B5G_MAXP_MASK);
938 + vp++;
939 +
940 + w = b[pathbase + SROM4_5GLH_MAXP];
941 + vp += sprintf(vp, "maxp5lga%d=%d", path, w >> B5GL_MAXP_SHIFT);
942 + vp++;
943 + vp += sprintf(vp, "maxp5gha%d=%d", path, w & B5GH_MAXP_MASK);
944 + vp++;
945 +
946 + for (i = 0; i < 4; i++) {
947 + vp += sprintf(vp, "pa5gw%da%d=%d", i, path,
948 + b[pathbase + SROM4_5G_PA + i]);
949 + vp++;
950 + vp += sprintf(vp, "pa5glw%da%d=%d", i, path,
951 + b[pathbase + SROM4_5GL_PA + i]);
952 + vp++;
953 + vp += sprintf(vp, "pa5hgw%da%d=%d", i, path,
954 + b[pathbase + SROM4_5GH_PA + i]);
955 + vp++;
956 + }
957 + }
958 +
959 + vp += sprintf(vp, "cck2gpo=%d", b[SROM4_2G_CCKPO]);
960 + vp++;
961 +
962 + w32 = ((uint32)b[SROM4_2G_OFDMPO + 1] << 16) | b[SROM4_2G_OFDMPO];
963 + vp += sprintf(vp, "ofdm2gpo=%d", w32);
964 + vp++;
965 +
966 + w32 = ((uint32)b[SROM4_5G_OFDMPO + 1] << 16) | b[SROM4_5G_OFDMPO];
967 + vp += sprintf(vp, "ofdm5gpo=%d", w32);
968 + vp++;
969 +
970 + w32 = ((uint32)b[SROM4_5GL_OFDMPO + 1] << 16) | b[SROM4_5GL_OFDMPO];
971 + vp += sprintf(vp, "ofdm5glpo=%d", w32);
972 + vp++;
973 +
974 + w32 = ((uint32)b[SROM4_5GH_OFDMPO + 1] << 16) | b[SROM4_5GH_OFDMPO];
975 + vp += sprintf(vp, "ofdm5ghpo=%d", w32);
976 + vp++;
977 +
978 + for (i = 0; i < 8; i++) {
979 + vp += sprintf(vp, "mcs2gpo%d=%d", i, b[SROM4_2G_MCSPO]);
980 + vp++;
981 + vp += sprintf(vp, "mcs5gpo%d=%d", i, b[SROM4_5G_MCSPO]);
982 + vp++;
983 + vp += sprintf(vp, "mcs5glpo%d=%d", i, b[SROM4_5GL_MCSPO]);
984 + vp++;
985 + vp += sprintf(vp, "mcs5ghpo%d=%d", i, b[SROM4_5GH_MCSPO]);
986 + vp++;
987 + }
988 +
989 + vp += sprintf(vp, "ccdpo%d=%d", i, b[SROM4_CCDPO]);
990 + vp++;
991 + vp += sprintf(vp, "stbcpo%d=%d", i, b[SROM4_STBCPO]);
992 + vp++;
993 + vp += sprintf(vp, "bw40po%d=%d", i, b[SROM4_BW40PO]);
994 + vp++;
995 + vp += sprintf(vp, "bwduppo%d=%d", i, b[SROM4_BWDUPPO]);
996 + vp++;
997 +
998 + goto done;
999 + }
1000 + if (sromrev >= 3) {
1001 + /* New section takes over the 3th hardware function space */
1002 +
1003 + /* Words 22+23 are 11a (mid) ofdm power offsets */
1004 + w32 = ((uint32)b[23] << 16) | b[22];
1005 + vp += sprintf(vp, "ofdmapo=%d", w32);
1006 + vp++;
1007 +
1008 + /* Words 24+25 are 11a (low) ofdm power offsets */
1009 + w32 = ((uint32)b[25] << 16) | b[24];
1010 + vp += sprintf(vp, "ofdmalpo=%d", w32);
1011 + vp++;
1012 +
1013 + /* Words 26+27 are 11a (high) ofdm power offsets */
1014 + w32 = ((uint32)b[27] << 16) | b[26];
1015 + vp += sprintf(vp, "ofdmahpo=%d", w32);
1016 + vp++;
1017 +
1018 + /* LED Powersave duty cycle (oncount >> 24) (offcount >> 8) */
1019 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xff) << 24) | /* oncount */
1020 + ((uint32)((unsigned char)(b[21] & 0xff)) << 8); /* offcount */
1021 + vp += sprintf(vp, "leddc=%d", w32);
1022 +
1023 + vp++;
1024 + }
1025 +
1026 + if (sromrev >= 2) {
1027 + /* New section takes over the 4th hardware function space */
1028 +
1029 + /* Word 29 is max power 11a high/low */
1030 + w = b[29];
1031 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
1032 + vp++;
1033 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
1034 + vp++;
1035 +
1036 + /* Words 30-32 set the 11alow pa settings,
1037 + * 33-35 are the 11ahigh ones.
1038 + */
1039 + for (i = 0; i < 3; i++) {
1040 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
1041 + vp++;
1042 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
1043 + vp++;
1044 + }
1045 + w = b[59];
1046 + if (w == 0)
1047 + vp += sprintf(vp, "ccode=");
1048 + else
1049 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
1050 + vp++;
1051 +
1052 + }
1053 +
1054 + /* parameter section of sprom starts at byte offset 72 */
1055 + woff = 72/2;
1056 +
1057 + /* first 6 bytes are il0macaddr */
1058 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1059 + ea.octet[1] = b[woff] & 0xff;
1060 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1061 + ea.octet[3] = b[woff+1] & 0xff;
1062 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1063 + ea.octet[5] = b[woff+2] & 0xff;
1064 + woff += 3;
1065 + bcm_ether_ntoa(&ea, eabuf);
1066 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
1067 + vp++;
1068 +
1069 + /* next 6 bytes are et0macaddr */
1070 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1071 + ea.octet[1] = b[woff] & 0xff;
1072 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1073 + ea.octet[3] = b[woff+1] & 0xff;
1074 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1075 + ea.octet[5] = b[woff+2] & 0xff;
1076 + woff += 3;
1077 + bcm_ether_ntoa(&ea, eabuf);
1078 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
1079 + vp++;
1080 +
1081 + /* next 6 bytes are et1macaddr */
1082 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1083 + ea.octet[1] = b[woff] & 0xff;
1084 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1085 + ea.octet[3] = b[woff+1] & 0xff;
1086 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1087 + ea.octet[5] = b[woff+2] & 0xff;
1088 + woff += 3;
1089 + bcm_ether_ntoa(&ea, eabuf);
1090 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
1091 + vp++;
1092 +
1093 + /*
1094 + * Enet phy settings one or two singles or a dual
1095 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
1096 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
1097 + * Bit 14 : Mdio for enet0
1098 + * Bit 15 : Mdio for enet1
1099 + */
1100 + w = b[woff];
1101 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
1102 + vp++;
1103 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
1104 + vp++;
1105 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
1106 + vp++;
1107 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
1108 + vp++;
1109 +
1110 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
1111 + w = b[46];
1112 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
1113 + vp++;
1114 +
1115 + if (sromrev > 1)
1116 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
1117 + else
1118 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
1119 + vp++;
1120 +
1121 + vp += sprintf(vp, "aa2g=%d", (w >> 12) & 0x3);
1122 + vp++;
1123 +
1124 + vp += sprintf(vp, "aa5g=%d", (w >> 14) & 0x3);
1125 + vp++;
1126 +
1127 + /* Words 47-49 set the (wl) pa settings */
1128 + woff = 47;
1129 +
1130 + for (i = 0; i < 3; i++) {
1131 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
1132 + vp++;
1133 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
1134 + vp++;
1135 + }
1136 +
1137 + /*
1138 + * Words 50-51 set the customer-configured wl led behavior.
1139 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
1140 + * LED behavior values defined in wlioctl.h .
1141 + */
1142 + w = b[50];
1143 + if ((w != 0) && (w != 0xffff)) {
1144 + /* ledbh0 */
1145 + vp += sprintf(vp, "ledbh0=%d", (w & 0xff));
1146 + vp++;
1147 +
1148 + /* ledbh1 */
1149 + vp += sprintf(vp, "ledbh1=%d", (w >> 8) & 0xff);
1150 + vp++;
1151 + }
1152 + w = b[51];
1153 + if ((w != 0) && (w != 0xffff)) {
1154 + /* ledbh2 */
1155 + vp += sprintf(vp, "ledbh2=%d", w & 0xff);
1156 + vp++;
1157 +
1158 + /* ledbh */
1159 + vp += sprintf(vp, "ledbh3=%d", (w >> 8) & 0xff);
1160 + vp++;
1161 + }
1162 +
1163 + /* Word 52 is max power 0/1 */
1164 + w = b[52];
1165 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
1166 + vp++;
1167 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
1168 + vp++;
1169 +
1170 + /* Word 56 is idle tssi target 0/1 */
1171 + w = b[56];
1172 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
1173 + vp++;
1174 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
1175 + vp++;
1176 +
1177 + /* Word 57 is boardflags, if not programmed make it zero */
1178 + w32 = (uint32)b[57];
1179 + if (w32 == 0xffff) w32 = 0;
1180 + if (sromrev > 1) {
1181 + /* Word 28 is the high bits of boardflags */
1182 + w32 |= (uint32)b[28] << 16;
1183 + }
1184 + vp += sprintf(vp, "boardflags=%d", w32);
1185 + vp++;
1186 +
1187 + /* Word 58 is antenna gain 0/1 */
1188 + w = b[58];
1189 + vp += sprintf(vp, "ag0=%d", w & 0xff);
1190 + vp++;
1191 +
1192 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
1193 + vp++;
1194 +
1195 + if (sromrev == 1) {
1196 + /* set the oem string */
1197 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
1198 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
1199 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
1200 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
1201 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
1202 + vp++;
1203 + } else if (sromrev == 2) {
1204 + /* Word 60 OFDM tx power offset from CCK level */
1205 + /* OFDM Power Offset - opo */
1206 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
1207 + vp++;
1208 + } else {
1209 + /* Word 60: cck power offsets */
1210 + vp += sprintf(vp, "cckpo=%d", b[60]);
1211 + vp++;
1212 +
1213 + /* Words 61+62: 11g ofdm power offsets */
1214 + w32 = ((uint32)b[62] << 16) | b[61];
1215 + vp += sprintf(vp, "ofdmgpo=%d", w32);
1216 + vp++;
1217 + }
1218 +
1219 + /* final nullbyte terminator */
1220 +done: *vp++ = '\0';
1221 +
1222 + ASSERT((vp - base) <= VARS_MAX);
1223 +
1224 +varsdone:
1225 + err = initvars_table(osh, base, vp, vars, count);
1226 +
1227 +err:
1228 +#ifdef WLTEST
1229 + if (base != mfgsromvars)
1230 +#endif
1231 + MFREE(osh, base, VARS_MAX);
1232 + MFREE(osh, b, SROM_MAX);
1233 + return err;
1234 +}
1235 +
1236 +/*
1237 + * Read the cis and call parsecis to initialize the vars.
1238 + * Return 0 on success, nonzero on error.
1239 + */
1240 +static int
1241 +initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, uint *count)
1242 +{
1243 + uint8 *cis = NULL;
1244 + int rc;
1245 + uint data_sz;
1246 +
1247 + data_sz = (sb_pcmciarev(sbh) == 1) ? (SPROM_SIZE * 2) : CIS_SIZE;
1248 +
1249 + if ((cis = MALLOC(osh, data_sz)) == NULL)
1250 + return (-2);
1251 +
1252 + if (sb_pcmciarev(sbh) == 1) {
1253 + if (srom_read(PCMCIA_BUS, (void *)NULL, osh, 0, data_sz, (uint16 *)cis)) {
1254 + MFREE(osh, cis, data_sz);
1255 + return (-1);
1256 + }
1257 + /* fix up endianess for 16-bit data vs 8-bit parsing */
1258 + ltoh16_buf((uint16 *)cis, data_sz);
1259 + } else
1260 + OSL_PCMCIA_READ_ATTR(osh, 0, cis, data_sz);
1261 +
1262 + rc = srom_parsecis(osh, &cis, 1, vars, count);
1263 +
1264 + MFREE(osh, cis, data_sz);
1265 +
1266 + return (rc);
1267 +}
1268 +
1269 diff -urN linux.old/arch/mips/bcm947xx/bcmutils.c linux.dev/arch/mips/bcm947xx/bcmutils.c
1270 --- linux.old/arch/mips/bcm947xx/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
1271 +++ linux.dev/arch/mips/bcm947xx/bcmutils.c 2006-04-28 00:34:02.000000000 +0200
1272 @@ -0,0 +1,247 @@
1273 +/*
1274 + * Misc useful OS-independent routines.
1275 + *
1276 + * Copyright 2006, Broadcom Corporation
1277 + * All Rights Reserved.
1278 + *
1279 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1280 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1281 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1282 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1283 + * $Id: bcmutils.c,v 1.1.1.12 2006/02/27 03:43:16 honor Exp $
1284 + */
1285 +
1286 +#include <typedefs.h>
1287 +#include <bcmdefs.h>
1288 +#include <stdarg.h>
1289 +#include <bcmutils.h>
1290 +#include <osl.h>
1291 +#include <sbutils.h>
1292 +#include <bcmnvram.h>
1293 +#include <bcmendian.h>
1294 +#include <bcmdevs.h>
1295 +
1296 +unsigned char bcm_ctype[] = {
1297 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
1298 + _BCM_C, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C,
1299 + _BCM_C, /* 8-15 */
1300 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
1301 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
1302 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
1303 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
1304 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
1305 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
1306 + _BCM_P, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X,
1307 + _BCM_U|_BCM_X, _BCM_U, /* 64-71 */
1308 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
1309 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
1310 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
1311 + _BCM_P, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X,
1312 + _BCM_L|_BCM_X, _BCM_L, /* 96-103 */
1313 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
1314 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
1315 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
1316 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 128-143 */
1317 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 144-159 */
1318 + _BCM_S|_BCM_SP, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
1319 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 160-175 */
1320 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
1321 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 176-191 */
1322 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U,
1323 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, /* 192-207 */
1324 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_P, _BCM_U, _BCM_U, _BCM_U,
1325 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_L, /* 208-223 */
1326 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L,
1327 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, /* 224-239 */
1328 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_P, _BCM_L, _BCM_L, _BCM_L,
1329 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L /* 240-255 */
1330 +};
1331 +
1332 +
1333 +ulong
1334 +bcm_strtoul(char *cp, char **endp, uint base)
1335 +{
1336 + ulong result, value;
1337 + bool minus;
1338 +
1339 + minus = FALSE;
1340 +
1341 + while (bcm_isspace(*cp))
1342 + cp++;
1343 +
1344 + if (cp[0] == '+')
1345 + cp++;
1346 + else if (cp[0] == '-') {
1347 + minus = TRUE;
1348 + cp++;
1349 + }
1350 +
1351 + if (base == 0) {
1352 + if (cp[0] == '0') {
1353 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
1354 + base = 16;
1355 + cp = &cp[2];
1356 + } else {
1357 + base = 8;
1358 + cp = &cp[1];
1359 + }
1360 + } else
1361 + base = 10;
1362 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
1363 + cp = &cp[2];
1364 + }
1365 +
1366 + result = 0;
1367 +
1368 + while (bcm_isxdigit(*cp) &&
1369 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
1370 + result = result*base + value;
1371 + cp++;
1372 + }
1373 +
1374 + if (minus)
1375 + result = (ulong)(result * -1);
1376 +
1377 + if (endp)
1378 + *endp = (char *)cp;
1379 +
1380 + return (result);
1381 +}
1382 +
1383 +uchar
1384 +bcm_toupper(uchar c)
1385 +{
1386 + if (bcm_islower(c))
1387 + c -= 'a'-'A';
1388 + return (c);
1389 +}
1390 +
1391 +char*
1392 +bcm_ether_ntoa(struct ether_addr *ea, char *buf)
1393 +{
1394 + sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
1395 + ea->octet[0]&0xff, ea->octet[1]&0xff, ea->octet[2]&0xff,
1396 + ea->octet[3]&0xff, ea->octet[4]&0xff, ea->octet[5]&0xff);
1397 + return (buf);
1398 +}
1399 +
1400 +
1401 +/*
1402 + * Search the name=value vars for a specific one and return its value.
1403 + * Returns NULL if not found.
1404 + */
1405 +char*
1406 +getvar(char *vars, char *name)
1407 +{
1408 + char *s;
1409 + int len;
1410 +
1411 + len = strlen(name);
1412 +
1413 + /* first look in vars[] */
1414 + for (s = vars; s && *s;) {
1415 + /* CSTYLED */
1416 + if ((memcmp(s, name, len) == 0) && (s[len] == '='))
1417 + return (&s[len+1]);
1418 +
1419 + while (*s++)
1420 + ;
1421 + }
1422 +
1423 + /* then query nvram */
1424 + return (nvram_get(name));
1425 +}
1426 +
1427 +/*
1428 + * Search the vars for a specific one and return its value as
1429 + * an integer. Returns 0 if not found.
1430 + */
1431 +int
1432 +getintvar(char *vars, char *name)
1433 +{
1434 + char *val;
1435 +
1436 + if ((val = getvar(vars, name)) == NULL)
1437 + return (0);
1438 +
1439 + return (bcm_strtoul(val, NULL, 0));
1440 +}
1441 +
1442 +
1443 +/*******************************************************************************
1444 + * crc8
1445 + *
1446 + * Computes a crc8 over the input data using the polynomial:
1447 + *
1448 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
1449 + *
1450 + * The caller provides the initial value (either CRC8_INIT_VALUE
1451 + * or the previous returned value) to allow for processing of
1452 + * discontiguous blocks of data. When generating the CRC the
1453 + * caller is responsible for complementing the final return value
1454 + * and inserting it into the byte stream. When checking, a final
1455 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
1456 + *
1457 + * Reference: Dallas Semiconductor Application Note 27
1458 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
1459 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
1460 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
1461 + *
1462 + * ****************************************************************************
1463 + */
1464 +
1465 +static uint8 crc8_table[256] = {
1466 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
1467 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
1468 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
1469 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
1470 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
1471 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
1472 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
1473 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
1474 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
1475 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
1476 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
1477 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
1478 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
1479 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
1480 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
1481 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
1482 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
1483 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
1484 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
1485 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
1486 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
1487 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
1488 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
1489 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
1490 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
1491 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
1492 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
1493 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
1494 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
1495 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
1496 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
1497 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
1498 +};
1499 +
1500 +#define CRC_INNER_LOOP(n, c, x) \
1501 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
1502 +
1503 +uint8
1504 +hndcrc8(
1505 + uint8 *pdata, /* pointer to array of data to process */
1506 + uint nbytes, /* number of input data bytes to process */
1507 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
1508 +)
1509 +{
1510 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
1511 + * to avoid the undefined and unnecessary (uint8 >> 8) operation.
1512 + */
1513 + while (nbytes-- > 0)
1514 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
1515 +
1516 + return crc;
1517 +}
1518 +
1519 +
1520 diff -urN linux.old/arch/mips/bcm947xx/cfe_env.c linux.dev/arch/mips/bcm947xx/cfe_env.c
1521 --- linux.old/arch/mips/bcm947xx/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
1522 +++ linux.dev/arch/mips/bcm947xx/cfe_env.c 2006-04-27 19:24:19.000000000 +0200
1523 @@ -0,0 +1,234 @@
1524 +/*
1525 + * NVRAM variable manipulation (Linux kernel half)
1526 + *
1527 + * Copyright 2001-2003, Broadcom Corporation
1528 + * All Rights Reserved.
1529 + *
1530 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1531 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1532 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1533 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1534 + *
1535 + * $Id$
1536 + */
1537 +
1538 +#include <linux/config.h>
1539 +#include <linux/init.h>
1540 +#include <linux/module.h>
1541 +#include <linux/kernel.h>
1542 +#include <linux/string.h>
1543 +#include <asm/io.h>
1544 +#include <asm/uaccess.h>
1545 +
1546 +#include <typedefs.h>
1547 +#include <osl.h>
1548 +#include <bcmendian.h>
1549 +#include <bcmutils.h>
1550 +
1551 +#define NVRAM_SIZE (0x1ff0)
1552 +static char _nvdata[NVRAM_SIZE] __initdata;
1553 +static char _valuestr[256] __initdata;
1554 +
1555 +/*
1556 + * TLV types. These codes are used in the "type-length-value"
1557 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
1558 + *
1559 + * The layout of the flash/nvram is as follows:
1560 + *
1561 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
1562 + *
1563 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
1564 + * The "length" field marks the length of the data section, not
1565 + * including the type and length fields.
1566 + *
1567 + * Environment variables are stored as follows:
1568 + *
1569 + * <type_env> <length> <flags> <name> = <value>
1570 + *
1571 + * If bit 0 (low bit) is set, the length is an 8-bit value.
1572 + * If bit 0 (low bit) is clear, the length is a 16-bit value
1573 + *
1574 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
1575 + * indicates the size of the length field.
1576 + *
1577 + * Flags are from the constants below:
1578 + *
1579 + */
1580 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
1581 +#define ENV_LENGTH_8BITS 0x01
1582 +
1583 +#define ENV_TYPE_USER 0x80
1584 +
1585 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
1586 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
1587 +
1588 +/*
1589 + * The actual TLV types we support
1590 + */
1591 +
1592 +#define ENV_TLV_TYPE_END 0x00
1593 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
1594 +
1595 +/*
1596 + * Environment variable flags
1597 + */
1598 +
1599 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
1600 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
1601 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
1602 +
1603 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
1604 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
1605 +
1606 +
1607 +/* *********************************************************************
1608 + * _nvram_read(buffer,offset,length)
1609 + *
1610 + * Read data from the NVRAM device
1611 + *
1612 + * Input parameters:
1613 + * buffer - destination buffer
1614 + * offset - offset of data to read
1615 + * length - number of bytes to read
1616 + *
1617 + * Return value:
1618 + * number of bytes read, or <0 if error occured
1619 + ********************************************************************* */
1620 +static int
1621 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
1622 +{
1623 + int i;
1624 + if (offset > NVRAM_SIZE)
1625 + return -1;
1626 +
1627 + for ( i = 0; i < length; i++) {
1628 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
1629 + }
1630 + return length;
1631 +}
1632 +
1633 +
1634 +static char*
1635 +_strnchr(const char *dest,int c,size_t cnt)
1636 +{
1637 + while (*dest && (cnt > 0)) {
1638 + if (*dest == c) return (char *) dest;
1639 + dest++;
1640 + cnt--;
1641 + }
1642 + return NULL;
1643 +}
1644 +
1645 +
1646 +
1647 +/*
1648 + * Core support API: Externally visible.
1649 + */
1650 +
1651 +/*
1652 + * Get the value of an NVRAM variable
1653 + * @param name name of variable to get
1654 + * @return value of variable or NULL if undefined
1655 + */
1656 +
1657 +char*
1658 +cfe_env_get(unsigned char *nv_buf, char* name)
1659 +{
1660 + int size;
1661 + unsigned char *buffer;
1662 + unsigned char *ptr;
1663 + unsigned char *envval;
1664 + unsigned int reclen;
1665 + unsigned int rectype;
1666 + int offset;
1667 + int flg;
1668 +
1669 + size = NVRAM_SIZE;
1670 + buffer = &_nvdata[0];
1671 +
1672 + ptr = buffer;
1673 + offset = 0;
1674 +
1675 + /* Read the record type and length */
1676 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1677 + goto error;
1678 + }
1679 +
1680 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
1681 +
1682 + /* Adjust pointer for TLV type */
1683 + rectype = *(ptr);
1684 + offset++;
1685 + size--;
1686 +
1687 + /*
1688 + * Read the length. It can be either 1 or 2 bytes
1689 + * depending on the code
1690 + */
1691 + if (rectype & ENV_LENGTH_8BITS) {
1692 + /* Read the record type and length - 8 bits */
1693 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1694 + goto error;
1695 + }
1696 + reclen = *(ptr);
1697 + size--;
1698 + offset++;
1699 + }
1700 + else {
1701 + /* Read the record type and length - 16 bits, MSB first */
1702 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
1703 + goto error;
1704 + }
1705 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
1706 + size -= 2;
1707 + offset += 2;
1708 + }
1709 +
1710 + if (reclen > size)
1711 + break; /* should not happen, bad NVRAM */
1712 +
1713 + switch (rectype) {
1714 + case ENV_TLV_TYPE_ENV:
1715 + /* Read the TLV data */
1716 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
1717 + goto error;
1718 + flg = *ptr++;
1719 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
1720 + if (envval) {
1721 + *envval++ = '\0';
1722 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
1723 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
1724 +#if 0
1725 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
1726 +#endif
1727 + if(!strcmp(ptr, name)){
1728 + return _valuestr;
1729 + }
1730 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
1731 + return _valuestr;
1732 + }
1733 + break;
1734 +
1735 + default:
1736 + /* Unknown TLV type, skip it. */
1737 + break;
1738 + }
1739 +
1740 + /*
1741 + * Advance to next TLV
1742 + */
1743 +
1744 + size -= (int)reclen;
1745 + offset += reclen;
1746 +
1747 + /* Read the next record type */
1748 + ptr = buffer;
1749 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
1750 + goto error;
1751 + }
1752 +
1753 +error:
1754 + return NULL;
1755 +
1756 +}
1757 +
1758 diff -urN linux.old/arch/mips/bcm947xx/compressed/Makefile linux.dev/arch/mips/bcm947xx/compressed/Makefile
1759 --- linux.old/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
1760 +++ linux.dev/arch/mips/bcm947xx/compressed/Makefile 2006-04-27 19:24:19.000000000 +0200
1761 @@ -0,0 +1,33 @@
1762 +#
1763 +# Makefile for Broadcom BCM947XX boards
1764 +#
1765 +# Copyright 2001-2003, Broadcom Corporation
1766 +# All Rights Reserved.
1767 +#
1768 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1769 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1770 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1771 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1772 +#
1773 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
1774 +#
1775 +
1776 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
1777 +SYSTEM ?= $(TOPDIR)/vmlinux
1778 +
1779 +all: vmlinuz
1780 +
1781 +# Don't build dependencies, this may die if $(CC) isn't gcc
1782 +dep:
1783 +
1784 +# Create a gzipped version named vmlinuz for compatibility
1785 +vmlinuz: piggy
1786 + gzip -c9 $< > $@
1787 +
1788 +piggy: $(SYSTEM)
1789 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
1790 +
1791 +mrproper: clean
1792 +
1793 +clean:
1794 + rm -f vmlinuz piggy
1795 diff -urN linux.old/arch/mips/bcm947xx/export.c linux.dev/arch/mips/bcm947xx/export.c
1796 --- linux.old/arch/mips/bcm947xx/export.c 1970-01-01 01:00:00.000000000 +0100
1797 +++ linux.dev/arch/mips/bcm947xx/export.c 2006-04-28 02:57:34.000000000 +0200
1798 @@ -0,0 +1,62 @@
1799 +#include <linux/module.h>
1800 +
1801 +#define _export(n) \
1802 + void n(void); \
1803 + EXPORT_SYMBOL(n);
1804 +
1805 +_export(bcm947xx_sbh)
1806 +
1807 +_export(sb_attach)
1808 +_export(sb_boardtype)
1809 +_export(sb_boardvendor)
1810 +_export(sb_btcgpiowar)
1811 +_export(sb_bus)
1812 +_export(sb_chip)
1813 +_export(sb_chiprev)
1814 +_export(sb_chipcrev)
1815 +_export(sb_chippkg)
1816 +_export(sb_clkctl_clk)
1817 +_export(sb_clkctl_fast_pwrup_delay)
1818 +_export(sb_clkctl_init)
1819 +_export(sb_clkctl_xtal)
1820 +_export(sb_core_disable)
1821 +_export(sb_core_reset)
1822 +_export(sb_core_tofixup)
1823 +_export(sb_coreflags)
1824 +_export(sb_coreflagshi)
1825 +_export(sb_coreidx)
1826 +_export(sb_corerev)
1827 +_export(sb_coreunit)
1828 +_export(sb_detach)
1829 +_export(sb_deviceremoved)
1830 +_export(sb_gpiocontrol)
1831 +_export(sb_gpioled)
1832 +_export(sb_gpioin)
1833 +_export(sb_gpioout)
1834 +_export(sb_gpioouten)
1835 +_export(sb_gpiotimerval)
1836 +_export(sb_iscoreup)
1837 +_export(sb_pci_setup)
1838 +_export(sb_pcirev)
1839 +_export(sb_pcmcia_init)
1840 +_export(sb_pcmciarev)
1841 +_export(sb_register_intr_callback)
1842 +_export(sb_setcore)
1843 +_export(sb_war16165)
1844 +_export(sb_osh)
1845 +
1846 +_export(getvar)
1847 +_export(getintvar)
1848 +_export(bcm_strtoul)
1849 +_export(bcm_ctype)
1850 +_export(bcm_toupper)
1851 +_export(bcm_ether_ntoa)
1852 +
1853 +_export(nvram_get)
1854 +_export(nvram_getall)
1855 +_export(nvram_set)
1856 +_export(nvram_unset)
1857 +_export(nvram_commit)
1858 +
1859 +_export(srom_read)
1860 +_export(srom_write)
1861 diff -urN linux.old/arch/mips/bcm947xx/generic/Makefile linux.dev/arch/mips/bcm947xx/generic/Makefile
1862 --- linux.old/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
1863 +++ linux.dev/arch/mips/bcm947xx/generic/Makefile 2006-04-27 19:24:19.000000000 +0200
1864 @@ -0,0 +1,15 @@
1865 +#
1866 +# Makefile for the BCM947xx specific kernel interface routines
1867 +# under Linux.
1868 +#
1869 +
1870 +.S.s:
1871 + $(CPP) $(AFLAGS) $< -o $*.s
1872 +.S.o:
1873 + $(CC) $(AFLAGS) -c $< -o $*.o
1874 +
1875 +O_TARGET := brcm.o
1876 +
1877 +obj-y := int-handler.o irq.o
1878 +
1879 +include $(TOPDIR)/Rules.make
1880 diff -urN linux.old/arch/mips/bcm947xx/generic/int-handler.S linux.dev/arch/mips/bcm947xx/generic/int-handler.S
1881 --- linux.old/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
1882 +++ linux.dev/arch/mips/bcm947xx/generic/int-handler.S 2006-04-27 19:24:19.000000000 +0200
1883 @@ -0,0 +1,51 @@
1884 +/*
1885 + * Generic interrupt handler for Broadcom MIPS boards
1886 + *
1887 + * Copyright 2004, Broadcom Corporation
1888 + * All Rights Reserved.
1889 + *
1890 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1891 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1892 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1893 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1894 + *
1895 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
1896 + */
1897 +
1898 +#include <linux/config.h>
1899 +
1900 +#include <asm/asm.h>
1901 +#include <asm/mipsregs.h>
1902 +#include <asm/regdef.h>
1903 +#include <asm/stackframe.h>
1904 +
1905 +/*
1906 + * MIPS IRQ Source
1907 + * -------- ------
1908 + * 0 Software (ignored)
1909 + * 1 Software (ignored)
1910 + * 2 Combined hardware interrupt (hw0)
1911 + * 3 Hardware
1912 + * 4 Hardware
1913 + * 5 Hardware
1914 + * 6 Hardware
1915 + * 7 R4k timer
1916 + */
1917 +
1918 + .text
1919 + .set noreorder
1920 + .set noat
1921 + .align 5
1922 + NESTED(brcmIRQ, PT_SIZE, sp)
1923 + SAVE_ALL
1924 + CLI
1925 + .set at
1926 + .set noreorder
1927 +
1928 + jal brcm_irq_dispatch
1929 + move a0, sp
1930 +
1931 + j ret_from_irq
1932 + nop
1933 +
1934 + END(brcmIRQ)
1935 diff -urN linux.old/arch/mips/bcm947xx/generic/irq.c linux.dev/arch/mips/bcm947xx/generic/irq.c
1936 --- linux.old/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
1937 +++ linux.dev/arch/mips/bcm947xx/generic/irq.c 2006-04-27 19:24:19.000000000 +0200
1938 @@ -0,0 +1,130 @@
1939 +/*
1940 + * Generic interrupt control functions for Broadcom MIPS boards
1941 + *
1942 + * Copyright 2004, Broadcom Corporation
1943 + * All Rights Reserved.
1944 + *
1945 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1946 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1947 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1948 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1949 + *
1950 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
1951 + */
1952 +
1953 +#include <linux/config.h>
1954 +#include <linux/init.h>
1955 +#include <linux/kernel.h>
1956 +#include <linux/types.h>
1957 +#include <linux/interrupt.h>
1958 +#include <linux/irq.h>
1959 +
1960 +#include <asm/irq.h>
1961 +#include <asm/mipsregs.h>
1962 +#include <asm/gdb-stub.h>
1963 +
1964 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
1965 +
1966 +extern asmlinkage void brcmIRQ(void);
1967 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
1968 +
1969 +void
1970 +brcm_irq_dispatch(struct pt_regs *regs)
1971 +{
1972 + u32 cause;
1973 +
1974 + cause = read_c0_cause() &
1975 + read_c0_status() &
1976 + CAUSEF_IP;
1977 +
1978 +#ifdef CONFIG_KERNPROF
1979 + change_c0_status(cause | 1, 1);
1980 +#else
1981 + clear_c0_status(cause);
1982 +#endif
1983 +
1984 + if (cause & CAUSEF_IP7)
1985 + do_IRQ(7, regs);
1986 + if (cause & CAUSEF_IP2)
1987 + do_IRQ(2, regs);
1988 + if (cause & CAUSEF_IP3)
1989 + do_IRQ(3, regs);
1990 + if (cause & CAUSEF_IP4)
1991 + do_IRQ(4, regs);
1992 + if (cause & CAUSEF_IP5)
1993 + do_IRQ(5, regs);
1994 + if (cause & CAUSEF_IP6)
1995 + do_IRQ(6, regs);
1996 +}
1997 +
1998 +static void
1999 +enable_brcm_irq(unsigned int irq)
2000 +{
2001 + if (irq < 8)
2002 + set_c0_status(1 << (irq + 8));
2003 + else
2004 + set_c0_status(IE_IRQ0);
2005 +}
2006 +
2007 +static void
2008 +disable_brcm_irq(unsigned int irq)
2009 +{
2010 + if (irq < 8)
2011 + clear_c0_status(1 << (irq + 8));
2012 + else
2013 + clear_c0_status(IE_IRQ0);
2014 +}
2015 +
2016 +static void
2017 +ack_brcm_irq(unsigned int irq)
2018 +{
2019 + /* Already done in brcm_irq_dispatch */
2020 +}
2021 +
2022 +static unsigned int
2023 +startup_brcm_irq(unsigned int irq)
2024 +{
2025 + enable_brcm_irq(irq);
2026 +
2027 + return 0; /* never anything pending */
2028 +}
2029 +
2030 +static void
2031 +end_brcm_irq(unsigned int irq)
2032 +{
2033 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
2034 + enable_brcm_irq(irq);
2035 +}
2036 +
2037 +static struct hw_interrupt_type brcm_irq_type = {
2038 + typename: "MIPS",
2039 + startup: startup_brcm_irq,
2040 + shutdown: disable_brcm_irq,
2041 + enable: enable_brcm_irq,
2042 + disable: disable_brcm_irq,
2043 + ack: ack_brcm_irq,
2044 + end: end_brcm_irq,
2045 + NULL
2046 +};
2047 +
2048 +void __init
2049 +init_IRQ(void)
2050 +{
2051 + int i;
2052 +
2053 + for (i = 0; i < NR_IRQS; i++) {
2054 + irq_desc[i].status = IRQ_DISABLED;
2055 + irq_desc[i].action = 0;
2056 + irq_desc[i].depth = 1;
2057 + irq_desc[i].handler = &brcm_irq_type;
2058 + }
2059 +
2060 + set_except_vector(0, brcmIRQ);
2061 + change_c0_status(ST0_IM, ALLINTS);
2062 +
2063 +#ifdef CONFIG_REMOTE_DEBUG
2064 + printk("Breaking into debugger...\n");
2065 + set_debug_traps();
2066 + breakpoint();
2067 +#endif
2068 +}
2069 diff -urN linux.old/arch/mips/bcm947xx/gpio.c linux.dev/arch/mips/bcm947xx/gpio.c
2070 --- linux.old/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
2071 +++ linux.dev/arch/mips/bcm947xx/gpio.c 2006-04-27 23:09:33.000000000 +0200
2072 @@ -0,0 +1,159 @@
2073 +/*
2074 + * GPIO char driver
2075 + *
2076 + * Copyright 2005, Broadcom Corporation
2077 + * All Rights Reserved.
2078 + *
2079 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2080 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2081 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2082 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2083 + *
2084 + * $Id$
2085 + */
2086 +
2087 +#include <linux/module.h>
2088 +#include <linux/init.h>
2089 +#include <linux/fs.h>
2090 +#include <linux/miscdevice.h>
2091 +#include <asm/uaccess.h>
2092 +
2093 +#include <typedefs.h>
2094 +#include <osl.h>
2095 +#include <bcmutils.h>
2096 +#include <sbutils.h>
2097 +#include <bcmdevs.h>
2098 +
2099 +static sb_t *gpio_sbh;
2100 +static int gpio_major;
2101 +static devfs_handle_t gpio_dir;
2102 +static struct {
2103 + char *name;
2104 + devfs_handle_t handle;
2105 +} gpio_file[] = {
2106 + { "in", NULL },
2107 + { "out", NULL },
2108 + { "outen", NULL },
2109 + { "control", NULL }
2110 +};
2111 +
2112 +static int
2113 +gpio_open(struct inode *inode, struct file * file)
2114 +{
2115 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
2116 + return -ENODEV;
2117 +
2118 + MOD_INC_USE_COUNT;
2119 + return 0;
2120 +}
2121 +
2122 +static int
2123 +gpio_release(struct inode *inode, struct file * file)
2124 +{
2125 + MOD_DEC_USE_COUNT;
2126 + return 0;
2127 +}
2128 +
2129 +static ssize_t
2130 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
2131 +{
2132 + u32 val;
2133 +
2134 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
2135 + case 0:
2136 + val = sb_gpioin(gpio_sbh);
2137 + break;
2138 + case 1:
2139 + val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2140 + break;
2141 + case 2:
2142 + val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2143 + break;
2144 + case 3:
2145 + val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2146 + break;
2147 + default:
2148 + return -ENODEV;
2149 + }
2150 +
2151 + if (put_user(val, (u32 *) buf))
2152 + return -EFAULT;
2153 +
2154 + return sizeof(val);
2155 +}
2156 +
2157 +static ssize_t
2158 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
2159 +{
2160 + u32 val;
2161 +
2162 + if (get_user(val, (u32 *) buf))
2163 + return -EFAULT;
2164 +
2165 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
2166 + case 0:
2167 + return -EACCES;
2168 + case 1:
2169 + sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2170 + break;
2171 + case 2:
2172 + sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2173 + break;
2174 + case 3:
2175 + sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2176 + break;
2177 + default:
2178 + return -ENODEV;
2179 + }
2180 +
2181 + return sizeof(val);
2182 +}
2183 +
2184 +static struct file_operations gpio_fops = {
2185 + owner: THIS_MODULE,
2186 + open: gpio_open,
2187 + release: gpio_release,
2188 + read: gpio_read,
2189 + write: gpio_write,
2190 +};
2191 +
2192 +static int __init
2193 +gpio_init(void)
2194 +{
2195 + int i;
2196 +
2197 + if (!(gpio_sbh = sb_kattach()))
2198 + return -ENODEV;
2199 +
2200 + sb_gpiosetcore(gpio_sbh);
2201 +
2202 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
2203 + return gpio_major;
2204 +
2205 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
2206 +
2207 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
2208 + gpio_file[i].handle = devfs_register(gpio_dir,
2209 + gpio_file[i].name,
2210 + DEVFS_FL_DEFAULT, gpio_major, i,
2211 + S_IFCHR | S_IRUGO | S_IWUGO,
2212 + &gpio_fops, NULL);
2213 + }
2214 +
2215 + return 0;
2216 +}
2217 +
2218 +static void __exit
2219 +gpio_exit(void)
2220 +{
2221 + int i;
2222 +
2223 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
2224 + devfs_unregister(gpio_file[i].handle);
2225 + devfs_unregister(gpio_dir);
2226 + devfs_unregister_chrdev(gpio_major, "gpio");
2227 + sb_detach(gpio_sbh);
2228 +}
2229 +
2230 +module_init(gpio_init);
2231 +module_exit(gpio_exit);
2232 diff -urN linux.old/arch/mips/bcm947xx/hndchipc.c linux.dev/arch/mips/bcm947xx/hndchipc.c
2233 --- linux.old/arch/mips/bcm947xx/hndchipc.c 1970-01-01 01:00:00.000000000 +0100
2234 +++ linux.dev/arch/mips/bcm947xx/hndchipc.c 2006-04-28 00:33:05.000000000 +0200
2235 @@ -0,0 +1,158 @@
2236 +/*
2237 + * BCM47XX support code for some chipcommon (old extif) facilities (uart)
2238 + *
2239 + * Copyright 2006, Broadcom Corporation
2240 + * All Rights Reserved.
2241 + *
2242 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2243 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2244 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2245 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2246 + *
2247 + * $Id: hndchipc.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
2248 + */
2249 +
2250 +#include <typedefs.h>
2251 +#include <bcmdefs.h>
2252 +#include <osl.h>
2253 +#include <bcmutils.h>
2254 +#include <sbutils.h>
2255 +#include <bcmdevs.h>
2256 +#include <bcmnvram.h>
2257 +#include <sbconfig.h>
2258 +#include <sbextif.h>
2259 +#include <sbchipc.h>
2260 +#include <hndcpu.h>
2261 +
2262 +/*
2263 + * Returns TRUE if an external UART exists at the given base
2264 + * register.
2265 + */
2266 +static bool
2267 +BCMINITFN(serial_exists)(osl_t *osh, uint8 *regs)
2268 +{
2269 + uint8 save_mcr, status1;
2270 +
2271 + save_mcr = R_REG(osh, &regs[UART_MCR]);
2272 + W_REG(osh, &regs[UART_MCR], UART_MCR_LOOP | 0x0a);
2273 + status1 = R_REG(osh, &regs[UART_MSR]) & 0xf0;
2274 + W_REG(osh, &regs[UART_MCR], save_mcr);
2275 +
2276 + return (status1 == 0x90);
2277 +}
2278 +
2279 +/*
2280 + * Initializes UART access. The callback function will be called once
2281 + * per found UART.
2282 + */
2283 +void
2284 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base,
2285 + uint reg_shift))
2286 +{
2287 + osl_t *osh;
2288 + void *regs;
2289 + ulong base;
2290 + uint irq;
2291 + int i, n;
2292 +
2293 + osh = sb_osh(sbh);
2294 +
2295 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
2296 + extifregs_t *eir = (extifregs_t *) regs;
2297 + sbconfig_t *sb;
2298 +
2299 + /* Determine external UART register base */
2300 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
2301 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(osh, &sb->sbadmatch1)));
2302 +
2303 + /* Determine IRQ */
2304 + irq = sb_irq(sbh);
2305 +
2306 + /* Disable GPIO interrupt initially */
2307 + W_REG(osh, &eir->gpiointpolarity, 0);
2308 + W_REG(osh, &eir->gpiointmask, 0);
2309 +
2310 + /* Search for external UARTs */
2311 + n = 2;
2312 + for (i = 0; i < 2; i++) {
2313 + regs = (void *) REG_MAP(base + (i * 8), 8);
2314 + if (serial_exists(osh, regs)) {
2315 + /* Set GPIO 1 to be the external UART IRQ */
2316 + W_REG(osh, &eir->gpiointmask, 2);
2317 + /* XXXDetermine external UART clock */
2318 + if (add)
2319 + add(regs, irq, 13500000, 0);
2320 + }
2321 + }
2322 +
2323 + /* Add internal UART if enabled */
2324 + if (R_REG(osh, &eir->corecontrol) & CC_UE)
2325 + if (add)
2326 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
2327 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
2328 + chipcregs_t *cc = (chipcregs_t *) regs;
2329 + uint32 rev, cap, pll, baud_base, div;
2330 +
2331 + /* Determine core revision and capabilities */
2332 + rev = sb_corerev(sbh);
2333 + cap = R_REG(osh, &cc->capabilities);
2334 + pll = cap & CAP_PLL_MASK;
2335 +
2336 + /* Determine IRQ */
2337 + irq = sb_irq(sbh);
2338 +
2339 + if (pll == PLL_TYPE1) {
2340 + /* PLL clock */
2341 + baud_base = sb_clock_rate(pll,
2342 + R_REG(osh, &cc->clockcontrol_n),
2343 + R_REG(osh, &cc->clockcontrol_m2));
2344 + div = 1;
2345 + } else {
2346 + /* Fixed ALP clock */
2347 + if (rev >= 11 && rev != 15) {
2348 + baud_base = 20000000;
2349 + div = 1;
2350 + /* Set the override bit so we don't divide it */
2351 + W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
2352 + }
2353 + /* Internal backplane clock */
2354 + else if (rev >= 3) {
2355 + baud_base = sb_clock(sbh);
2356 + div = 2; /* Minimum divisor */
2357 + W_REG(osh, &cc->clkdiv,
2358 + ((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
2359 + }
2360 + /* Fixed internal backplane clock */
2361 + else {
2362 + baud_base = 88000000;
2363 + div = 48;
2364 + }
2365 +
2366 + /* Clock source depends on strapping if UartClkOverride is unset */
2367 + if ((rev > 0) &&
2368 + ((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0)) {
2369 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
2370 + /* Internal divided backplane clock */
2371 + baud_base /= div;
2372 + } else {
2373 + /* Assume external clock of 1.8432 MHz */
2374 + baud_base = 1843200;
2375 + }
2376 + }
2377 + }
2378 +
2379 + /* Add internal UARTs */
2380 + n = cap & CAP_UARTS_MASK;
2381 + for (i = 0; i < n; i++) {
2382 + /* Register offset changed after revision 0 */
2383 + if (rev)
2384 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
2385 + else
2386 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
2387 +
2388 + if (add)
2389 + add(regs, irq, baud_base, 0);
2390 + }
2391 + }
2392 +}
2393 +
2394 diff -urN linux.old/arch/mips/bcm947xx/include/bcm4710.h linux.dev/arch/mips/bcm947xx/include/bcm4710.h
2395 --- linux.old/arch/mips/bcm947xx/include/bcm4710.h 1970-01-01 01:00:00.000000000 +0100
2396 +++ linux.dev/arch/mips/bcm947xx/include/bcm4710.h 2006-04-27 22:30:01.000000000 +0200
2397 @@ -0,0 +1,91 @@
2398 +/*
2399 + * BCM4710 address space map and definitions
2400 + * Think twice before adding to this file, this is not the kitchen sink
2401 + * These definitions are not guaranteed for all 47xx chips, only the 4710
2402 + *
2403 + * Copyright 2004, Broadcom Corporation
2404 + * All Rights Reserved.
2405 + *
2406 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2407 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2408 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2409 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2410 + *
2411 + * $Id: bcm4710.h,v 1.3 2004/09/27 07:23:30 tallest Exp $
2412 + */
2413 +
2414 +#ifndef _bcm4710_h_
2415 +#define _bcm4710_h_
2416 +
2417 +/* Address map */
2418 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
2419 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
2420 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
2421 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
2422 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
2423 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
2424 +
2425 +/* Core register space */
2426 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
2427 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
2428 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
2429 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
2430 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
2431 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
2432 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
2433 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
2434 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
2435 +
2436 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
2437 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
2438 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
2439 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
2440 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
2441 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
2442 +
2443 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
2444 +
2445 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
2446 +
2447 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
2448 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
2449 +
2450 +#define SBFLAG_PCI 0
2451 +#define SBFLAG_ENET0 1
2452 +#define SBFLAG_ILINE20 2
2453 +#define SBFLAG_CODEC 3
2454 +#define SBFLAG_USB 4
2455 +#define SBFLAG_EXTIF 5
2456 +#define SBFLAG_ENET1 6
2457 +
2458 +#ifdef CONFIG_HWSIM
2459 +#define BCM4710_TRACE(trval) do { *((int *)0xa0000f18) = (trval); } while (0)
2460 +#else
2461 +#define BCM4710_TRACE(trval)
2462 +#endif
2463 +
2464 +
2465 +/* BCM94702 CPCI -ExtIF used for LocalBus devs */
2466 +
2467 +#define BCM94702_CPCI_RESET_ADDR BCM4710_EXTIF
2468 +#define BCM94702_CPCI_BOARDID_ADDR (BCM4710_EXTIF | 0x4000)
2469 +#define BCM94702_CPCI_DOC_ADDR (BCM4710_EXTIF | 0x6000)
2470 +#define BCM94702_DOC_ADDR BCM94702_CPCI_DOC_ADDR
2471 +#define BCM94702_CPCI_LED_ADDR (BCM4710_EXTIF | 0xc000)
2472 +#define BCM94702_CPCI_NVRAM_ADDR (BCM4710_EXTIF | 0xe000)
2473 +#define BCM94702_CPCI_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
2474 +#define BCM94702_CPCI_TOD_REG_BASE (BCM94702_CPCI_NVRAM_ADDR | 0x1ff0)
2475 +
2476 +#define LED_REG(x) \
2477 + (*(volatile unsigned char *) (KSEG1ADDR(BCM94702_CPCI_LED_ADDR) + (x)))
2478 +
2479 +/*
2480 + * Reset function implemented in PLD. Read or write should trigger hard reset
2481 + */
2482 +#define SYS_HARD_RESET() \
2483 + { for (;;) \
2484 + *( (volatile unsigned char *)\
2485 + KSEG1ADDR(BCM94702_CPCI_RESET_ADDR) ) = 0x80; \
2486 + }
2487 +
2488 +#endif /* _bcm4710_h_ */
2489 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdefs.h linux.dev/arch/mips/bcm947xx/include/bcmdefs.h
2490 --- linux.old/arch/mips/bcm947xx/include/bcmdefs.h 1970-01-01 01:00:00.000000000 +0100
2491 +++ linux.dev/arch/mips/bcm947xx/include/bcmdefs.h 2006-04-27 20:12:21.000000000 +0200
2492 @@ -0,0 +1,106 @@
2493 +/*
2494 + * Misc system wide definitions
2495 + *
2496 + * Copyright 2006, Broadcom Corporation
2497 + * All Rights Reserved.
2498 + *
2499 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2500 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2501 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2502 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2503 + * $Id: bcmdefs.h,v 1.1.1.3 2006/04/08 06:13:39 honor Exp $
2504 + */
2505 +
2506 +#ifndef _bcmdefs_h_
2507 +#define _bcmdefs_h_
2508 +
2509 +/*
2510 + * One doesn't need to include this file explicitly, gets included automatically if
2511 + * typedefs.h is included.
2512 + */
2513 +
2514 +/* Reclaiming text and data :
2515 + * The following macros specify special linker sections that can be reclaimed
2516 + * after a system is considered 'up'.
2517 + */
2518 +#if defined(__GNUC__) && defined(BCMRECLAIM)
2519 +extern bool bcmreclaimed;
2520 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data
2521 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn
2522 +#else /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
2523 +#define BCMINITDATA(_data) _data
2524 +#define BCMINITFN(_fn) _fn
2525 +#define bcmreclaimed 0
2526 +#endif /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
2527 +
2528 +/* Reclaim uninit functions if BCMNODOWN is defined */
2529 +/* and if they are not already removed by -gc-sections */
2530 +#ifdef BCMNODOWN
2531 +#define BCMUNINITFN(_fn) BCMINITFN(_fn)
2532 +#else
2533 +#define BCMUNINITFN(_fn) _fn
2534 +#endif
2535 +
2536 +#ifdef BCMRECLAIM
2537 +#define CONST
2538 +#else
2539 +#define CONST const
2540 +#endif /* BCMRECLAIM */
2541 +
2542 +/* Compatibility with old-style BCMRECLAIM */
2543 +#define BCMINIT(_id) _id
2544 +
2545 +
2546 +/* Put some library data/code into ROM to reduce RAM requirements */
2547 +#if defined(__GNUC__) && defined(BCMROMOFFLOAD)
2548 +#define BCMROMDATA(_data) __attribute__ ((__section__ (".datarom." #_data))) _data
2549 +#define BCMROMFN(_fn) __attribute__ ((__section__ (".textrom." #_fn))) _fn
2550 +#else
2551 +#define BCMROMDATA(_data) _data
2552 +#define BCMROMFN(_fn) _fn
2553 +#endif
2554 +
2555 +/* Bus types */
2556 +#define SB_BUS 0 /* Silicon Backplane */
2557 +#define PCI_BUS 1 /* PCI target */
2558 +#define PCMCIA_BUS 2 /* PCMCIA target */
2559 +#define SDIO_BUS 3 /* SDIO target */
2560 +#define JTAG_BUS 4 /* JTAG */
2561 +#define NO_BUS 0xFF /* Bus that does not support R/W REG */
2562 +
2563 +/* Allows optimization for single-bus support */
2564 +#ifdef BCMBUSTYPE
2565 +#define BUSTYPE(bus) (BCMBUSTYPE)
2566 +#else
2567 +#define BUSTYPE(bus) (bus)
2568 +#endif
2569 +
2570 +/* Defines for DMA Address Width - Shared between OSL and HNDDMA */
2571 +#define DMADDR_MASK_32 0x0 /* Address mask for 32-bits */
2572 +#define DMADDR_MASK_30 0xc0000000 /* Address mask for 30-bits */
2573 +#define DMADDR_MASK_0 0xffffffff /* Address mask for 0-bits (hi-part) */
2574 +
2575 +#define DMADDRWIDTH_30 30 /* 30-bit addressing capability */
2576 +#define DMADDRWIDTH_32 32 /* 32-bit addressing capability */
2577 +#define DMADDRWIDTH_63 63 /* 64-bit addressing capability */
2578 +#define DMADDRWIDTH_64 64 /* 64-bit addressing capability */
2579 +
2580 +/* packet headroom necessary to accomodate the largest header in the system, (i.e TXOFF).
2581 + * By doing, we avoid the need to allocate an extra buffer for the header when bridging to WL.
2582 + * There is a compile time check in wlc.c which ensure that this value is at least as big
2583 + * as TXOFF. This value is used in dma_rxfill (hnddma.c).
2584 + */
2585 +#define BCMEXTRAHDROOM 160
2586 +
2587 +/* Headroom required for dongle-to-host communication. Packets allocated
2588 + * locally in the dongle (e.g. for CDC ioctls or RNDIS messages) should
2589 + * leave this much room in front for low-level message headers which may
2590 + * be needed to get across the dongle bus to the host. (These messages
2591 + * don't go over the network, so room for the full WL header above would
2592 + * be a waste.)
2593 + */
2594 +#define BCMDONGLEHDRSZ 8
2595 +
2596 +
2597 +
2598 +#endif /* _bcmdefs_h_ */
2599 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
2600 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
2601 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2006-04-27 22:30:25.000000000 +0200
2602 @@ -0,0 +1,369 @@
2603 +/*
2604 + * Broadcom device-specific manifest constants.
2605 + *
2606 + * Copyright 2006, Broadcom Corporation
2607 + * All Rights Reserved.
2608 + *
2609 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2610 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2611 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2612 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2613 + * $Id: bcmdevs.h,v 1.1.1.17 2006/04/15 01:29:08 michael Exp $
2614 + */
2615 +
2616 +#ifndef _BCMDEVS_H
2617 +#define _BCMDEVS_H
2618 +
2619 +#include "bcm4710.h"
2620 +
2621 +/* Known PCI vendor Id's */
2622 +#define VENDOR_EPIGRAM 0xfeda
2623 +#define VENDOR_BROADCOM 0x14e4
2624 +#define VENDOR_3COM 0x10b7
2625 +#define VENDOR_NETGEAR 0x1385
2626 +#define VENDOR_DIAMOND 0x1092
2627 +#define VENDOR_DELL 0x1028
2628 +#define VENDOR_HP 0x0e11
2629 +#define VENDOR_APPLE 0x106b
2630 +
2631 +/* PCI Device Id's */
2632 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
2633 +#define BCM4211_DEVICE_ID 0x4211
2634 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
2635 +#define BCM4231_DEVICE_ID 0x4231
2636 +
2637 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
2638 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
2639 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
2640 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
2641 +
2642 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
2643 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
2644 +
2645 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
2646 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
2647 +
2648 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
2649 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
2650 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
2651 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
2652 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
2653 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
2654 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
2655 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
2656 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
2657 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
2658 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
2659 +#define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */
2660 +#define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */
2661 +#define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */
2662 +
2663 +#define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */
2664 +#define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */
2665 +
2666 +#define BCM4710_CHIP_ID 0x4710 /* 4710 chipid returned by sb_chip() */
2667 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
2668 +
2669 +#define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */
2670 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
2671 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
2672 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
2673 +
2674 +#define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */
2675 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
2676 +#define BCM4306_D11G_ID2 0x4325
2677 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
2678 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
2679 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
2680 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
2681 +
2682 +#define BCM4309_PKG_ID 1 /* 4309 package id */
2683 +
2684 +#define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */
2685 +#define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */
2686 +#define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */
2687 +#define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */
2688 +
2689 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
2690 +#define BCM4303_PKG_ID 2 /* 4303 package id */
2691 +
2692 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
2693 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
2694 +
2695 +#define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */
2696 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
2697 +
2698 +#define BCM4318_CHIP_ID 0x4318 /* 4318 chip common chipid */
2699 +#define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */
2700 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */
2701 +#define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */
2702 +
2703 +#define BCM4321_CHIP_ID 0x4321 /* 4321 chip common chipid */
2704 +#define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */
2705 +#define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Hgz band id */
2706 +#define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */
2707 +
2708 +#define BCM4331_CHIP_ID 0x4331 /* 4331 chip common chipid */
2709 +#define BCM4331_D11N2G_ID 0x4330 /* 4331 802.11n 2.4Ghz band id */
2710 +#define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */
2711 +#define BCM4331_D11N5G_ID 0x4332 /* 4331 802.11n 5Ghz band id */
2712 +
2713 +#define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */
2714 +#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
2715 +#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
2716 +
2717 +#define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */
2718 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
2719 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
2720 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
2721 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
2722 +
2723 +#define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
2724 +#define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */
2725 +#define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */
2726 +
2727 +#define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */
2728 +
2729 +#define BCM4328_CHIP_ID 0x4328 /* bcm4328 chipcommon chipid */
2730 +
2731 +#define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */
2732 +#define BCM43XX_JTAGM_ID 0x43f1 /* 43xx jtagm device id */
2733 +#define BCM43XXOLD_JTAGM_ID 0x4331 /* 43xx old jtagm device id */
2734 +
2735 +#define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */
2736 +#define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */
2737 +
2738 +#define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */
2739 +
2740 +#define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */
2741 +
2742 +/* PCMCIA vendor Id's */
2743 +
2744 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
2745 +
2746 +/* SDIO vendor Id's */
2747 +#define VENDOR_BROADCOM_SDIO 0x00BF
2748 +
2749 +
2750 +/* boardflags */
2751 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
2752 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
2753 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
2754 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
2755 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
2756 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
2757 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
2758 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
2759 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
2760 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
2761 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
2762 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
2763 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
2764 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
2765 +
2766 +/* boardflags2 */
2767 +#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* This board has an external rxbb regulator */
2768 +#define BFL2_SSWITCH_AVAIL 0x00000002 /* This board has a superswitch for > 2 antennas */
2769 +#define BFL2_TXPWRCTRL_EN 0x00000004 /* This board permits TX Power Control to be enabled */
2770 +
2771 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
2772 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
2773 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
2774 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
2775 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
2776 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
2777 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
2778 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
2779 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
2780 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
2781 +
2782 +/* power control defines */
2783 +#define PLL_DELAY 150 /* us pll on delay */
2784 +#define FREF_DELAY 200 /* us fref change delay */
2785 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
2786 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
2787 +
2788 +/* Reference Board Types */
2789 +
2790 +#define BU4710_BOARD 0x0400
2791 +#define VSIM4710_BOARD 0x0401
2792 +#define QT4710_BOARD 0x0402
2793 +
2794 +#define BU4309_BOARD 0x040a
2795 +#define BCM94309CB_BOARD 0x040b
2796 +#define BCM94309MP_BOARD 0x040c
2797 +#define BCM4309AP_BOARD 0x040d
2798 +
2799 +#define BCM94302MP_BOARD 0x040e
2800 +
2801 +#define BU4306_BOARD 0x0416
2802 +#define BCM94306CB_BOARD 0x0417
2803 +#define BCM94306MP_BOARD 0x0418
2804 +
2805 +#define BCM94710D_BOARD 0x041a
2806 +#define BCM94710R1_BOARD 0x041b
2807 +#define BCM94710R4_BOARD 0x041c
2808 +#define BCM94710AP_BOARD 0x041d
2809 +
2810 +#define BU2050_BOARD 0x041f
2811 +
2812 +
2813 +#define BCM94309G_BOARD 0x0421
2814 +
2815 +#define BU4704_BOARD 0x0423
2816 +#define BU4702_BOARD 0x0424
2817 +
2818 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
2819 +
2820 +
2821 +#define BCM94702MN_BOARD 0x0428
2822 +
2823 +/* BCM4702 1U CompactPCI Board */
2824 +#define BCM94702CPCI_BOARD 0x0429
2825 +
2826 +/* BCM4702 with BCM95380 VLAN Router */
2827 +#define BCM95380RR_BOARD 0x042a
2828 +
2829 +/* cb4306 with SiGe PA */
2830 +#define BCM94306CBSG_BOARD 0x042b
2831 +
2832 +/* cb4306 with SiGe PA */
2833 +#define PCSG94306_BOARD 0x042d
2834 +
2835 +/* bu4704 with sdram */
2836 +#define BU4704SD_BOARD 0x042e
2837 +
2838 +/* Dual 11a/11g Router */
2839 +#define BCM94704AGR_BOARD 0x042f
2840 +
2841 +/* 11a-only minipci */
2842 +#define BCM94308MP_BOARD 0x0430
2843 +
2844 +
2845 +
2846 +#define BU4712_BOARD 0x0444
2847 +#define BU4712SD_BOARD 0x045d
2848 +#define BU4712L_BOARD 0x045f
2849 +
2850 +/* BCM4712 boards */
2851 +#define BCM94712AP_BOARD 0x0445
2852 +#define BCM94712P_BOARD 0x0446
2853 +
2854 +/* BCM4318 boards */
2855 +#define BU4318_BOARD 0x0447
2856 +#define CB4318_BOARD 0x0448
2857 +#define MPG4318_BOARD 0x0449
2858 +#define MP4318_BOARD 0x044a
2859 +#define SD4318_BOARD 0x044b
2860 +
2861 +/* BCM63XX boards */
2862 +#define BCM96338_BOARD 0x6338
2863 +#define BCM96348_BOARD 0x6348
2864 +
2865 +/* Another mp4306 with SiGe */
2866 +#define BCM94306P_BOARD 0x044c
2867 +
2868 +/* mp4303 */
2869 +#define BCM94303MP_BOARD 0x044e
2870 +
2871 +/* mpsgh4306 */
2872 +#define BCM94306MPSGH_BOARD 0x044f
2873 +
2874 +/* BRCM 4306 w/ Front End Modules */
2875 +#define BCM94306MPM 0x0450
2876 +#define BCM94306MPL 0x0453
2877 +
2878 +/* 4712agr */
2879 +#define BCM94712AGR_BOARD 0x0451
2880 +
2881 +/* pcmcia 4303 */
2882 +#define PC4303_BOARD 0x0454
2883 +
2884 +/* 5350K */
2885 +#define BCM95350K_BOARD 0x0455
2886 +
2887 +/* 5350R */
2888 +#define BCM95350R_BOARD 0x0456
2889 +
2890 +/* 4306mplna */
2891 +#define BCM94306MPLNA_BOARD 0x0457
2892 +
2893 +/* 4320 boards */
2894 +#define BU4320_BOARD 0x0458
2895 +#define BU4320S_BOARD 0x0459
2896 +#define BCM94320PH_BOARD 0x045a
2897 +
2898 +/* 4306mph */
2899 +#define BCM94306MPH_BOARD 0x045b
2900 +
2901 +/* 4306pciv */
2902 +#define BCM94306PCIV_BOARD 0x045c
2903 +
2904 +#define BU4712SD_BOARD 0x045d
2905 +
2906 +#define BCM94320PFLSH_BOARD 0x045e
2907 +
2908 +#define BU4712L_BOARD 0x045f
2909 +#define BCM94712LGR_BOARD 0x0460
2910 +#define BCM94320R_BOARD 0x0461
2911 +
2912 +#define BU5352_BOARD 0x0462
2913 +
2914 +#define BCM94318MPGH_BOARD 0x0463
2915 +
2916 +#define BU4311_BOARD 0x0464
2917 +#define BCM94311MC_BOARD 0x0465
2918 +#define BCM94311MCAG_BOARD 0x0466
2919 +
2920 +#define BCM95352GR_BOARD 0x0467
2921 +
2922 +/* bcm95351agr */
2923 +#define BCM95351AGR_BOARD 0x0470
2924 +
2925 +/* bcm94704mpcb */
2926 +#define BCM94704MPCB_BOARD 0x0472
2927 +
2928 +/* 4785 boards */
2929 +#define BU4785_BOARD 0x0478
2930 +
2931 +/* 4321 boards */
2932 +#define BU4321_BOARD 0x046b
2933 +#define BU4321E_BOARD 0x047c
2934 +#define MP4321_BOARD 0x046c
2935 +#define CB2_4321_BOARD 0x046d
2936 +#define MC4321_BOARD 0x046e
2937 +
2938 +/* # of GPIO pins */
2939 +#define GPIO_NUMPINS 16
2940 +
2941 +/* radio ID codes */
2942 +#define NORADIO_ID 0xe4f5
2943 +#define NORADIO_IDCODE 0x4e4f5246
2944 +
2945 +#define BCM2050_ID 0x2050
2946 +#define BCM2050_IDCODE 0x02050000
2947 +#define BCM2050A0_IDCODE 0x1205017f
2948 +#define BCM2050A1_IDCODE 0x2205017f
2949 +#define BCM2050R8_IDCODE 0x8205017f
2950 +
2951 +#define BCM2055_ID 0x2055
2952 +#define BCM2055_IDCODE 0x02055000
2953 +#define BCM2055A0_IDCODE 0x1205517f
2954 +
2955 +#define BCM2060_ID 0x2060
2956 +#define BCM2060_IDCODE 0x02060000
2957 +#define BCM2060WW_IDCODE 0x1206017f
2958 +
2959 +#define BCM2062_ID 0x2062
2960 +#define BCM2062_IDCODE 0x02062000
2961 +#define BCM2062A0_IDCODE 0x0206217f
2962 +
2963 +/* parts of an idcode: */
2964 +#define IDCODE_MFG_MASK 0x00000fff
2965 +#define IDCODE_MFG_SHIFT 0
2966 +#define IDCODE_ID_MASK 0x0ffff000
2967 +#define IDCODE_ID_SHIFT 12
2968 +#define IDCODE_REV_MASK 0xf0000000
2969 +#define IDCODE_REV_SHIFT 28
2970 +
2971 +#endif /* _BCMDEVS_H */
2972 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs1.h linux.dev/arch/mips/bcm947xx/include/bcmdevs1.h
2973 --- linux.old/arch/mips/bcm947xx/include/bcmdevs1.h 1970-01-01 01:00:00.000000000 +0100
2974 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs1.h 2006-05-02 04:32:03.000000000 +0200
2975 @@ -0,0 +1,391 @@
2976 +/*
2977 + * Broadcom device-specific manifest constants.
2978 + *
2979 + * Copyright 2005, Broadcom Corporation
2980 + * All Rights Reserved.
2981 + *
2982 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2983 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2984 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2985 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2986 + * $Id$
2987 + */
2988 +
2989 +#ifndef _BCMDEVS_H
2990 +#define _BCMDEVS_H
2991 +
2992 +
2993 +/* Known PCI vendor Id's */
2994 +#define VENDOR_EPIGRAM 0xfeda
2995 +#define VENDOR_BROADCOM 0x14e4
2996 +#define VENDOR_3COM 0x10b7
2997 +#define VENDOR_NETGEAR 0x1385
2998 +#define VENDOR_DIAMOND 0x1092
2999 +#define VENDOR_DELL 0x1028
3000 +#define VENDOR_HP 0x0e11
3001 +#define VENDOR_APPLE 0x106b
3002 +
3003 +/* PCI Device Id's */
3004 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
3005 +#define BCM4211_DEVICE_ID 0x4211
3006 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
3007 +#define BCM4231_DEVICE_ID 0x4231
3008 +
3009 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
3010 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
3011 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
3012 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
3013 +
3014 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
3015 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
3016 +
3017 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
3018 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
3019 +
3020 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
3021 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
3022 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
3023 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
3024 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
3025 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
3026 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
3027 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
3028 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
3029 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
3030 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
3031 +
3032 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
3033 +
3034 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
3035 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
3036 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
3037 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
3038 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
3039 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
3040 +
3041 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
3042 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
3043 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
3044 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
3045 +
3046 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
3047 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
3048 +
3049 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
3050 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
3051 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
3052 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
3053 +
3054 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
3055 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
3056 +#define BCM4306_D11G_ID2 0x4325
3057 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
3058 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
3059 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
3060 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
3061 +
3062 +#define BCM4309_PKG_ID 1 /* 4309 package id */
3063 +
3064 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
3065 +#define BCM4303_PKG_ID 2 /* 4303 package id */
3066 +
3067 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
3068 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
3069 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
3070 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
3071 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
3072 +
3073 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
3074 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
3075 +
3076 +
3077 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
3078 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
3079 +
3080 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
3081 +
3082 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
3083 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
3084 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
3085 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
3086 +
3087 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
3088 +
3089 +/* Address map */
3090 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
3091 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
3092 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
3093 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
3094 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
3095 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
3096 +
3097 +/* Core register space */
3098 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
3099 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
3100 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
3101 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
3102 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
3103 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
3104 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
3105 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
3106 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
3107 +
3108 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
3109 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
3110 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
3111 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
3112 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
3113 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
3114 +
3115 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
3116 +
3117 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
3118 +
3119 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
3120 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
3121 +
3122 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
3123 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
3124 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
3125 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
3126 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
3127 +
3128 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
3129 +
3130 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
3131 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
3132 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
3133 +
3134 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
3135 +
3136 +/* PCMCIA vendor Id's */
3137 +
3138 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
3139 +
3140 +/* SDIO vendor Id's */
3141 +#define VENDOR_BROADCOM_SDIO 0x00BF
3142 +
3143 +
3144 +/* boardflags */
3145 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
3146 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
3147 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
3148 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
3149 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
3150 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
3151 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
3152 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
3153 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
3154 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
3155 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
3156 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
3157 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
3158 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
3159 +
3160 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
3161 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
3162 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
3163 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
3164 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
3165 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
3166 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
3167 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
3168 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
3169 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
3170 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
3171 +
3172 +/* Bus types */
3173 +#define SB_BUS 0 /* Silicon Backplane */
3174 +#define PCI_BUS 1 /* PCI target */
3175 +#define PCMCIA_BUS 2 /* PCMCIA target */
3176 +#define SDIO_BUS 3 /* SDIO target */
3177 +#define JTAG_BUS 4 /* JTAG */
3178 +
3179 +/* Allows optimization for single-bus support */
3180 +#ifdef BCMBUSTYPE
3181 +#define BUSTYPE(bus) (BCMBUSTYPE)
3182 +#else
3183 +#define BUSTYPE(bus) (bus)
3184 +#endif
3185 +
3186 +/* power control defines */
3187 +#define PLL_DELAY 150 /* us pll on delay */
3188 +#define FREF_DELAY 200 /* us fref change delay */
3189 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
3190 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
3191 +
3192 +/* Reference Board Types */
3193 +
3194 +#define BU4710_BOARD 0x0400
3195 +#define VSIM4710_BOARD 0x0401
3196 +#define QT4710_BOARD 0x0402
3197 +
3198 +#define BU4610_BOARD 0x0403
3199 +#define VSIM4610_BOARD 0x0404
3200 +
3201 +#define BU4307_BOARD 0x0405
3202 +#define BCM94301CB_BOARD 0x0406
3203 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
3204 +#define BCM94301MP_BOARD 0x0407
3205 +#define BCM94307MP_BOARD 0x0408
3206 +#define BCMAP4307_BOARD 0x0409
3207 +
3208 +#define BU4309_BOARD 0x040a
3209 +#define BCM94309CB_BOARD 0x040b
3210 +#define BCM94309MP_BOARD 0x040c
3211 +#define BCM4309AP_BOARD 0x040d
3212 +
3213 +#define BCM94302MP_BOARD 0x040e
3214 +
3215 +#define VSIM4310_BOARD 0x040f
3216 +#define BU4711_BOARD 0x0410
3217 +#define BCM94310U_BOARD 0x0411
3218 +#define BCM94310AP_BOARD 0x0412
3219 +#define BCM94310MP_BOARD 0x0414
3220 +
3221 +#define BU4306_BOARD 0x0416
3222 +#define BCM94306CB_BOARD 0x0417
3223 +#define BCM94306MP_BOARD 0x0418
3224 +
3225 +#define BCM94710D_BOARD 0x041a
3226 +#define BCM94710R1_BOARD 0x041b
3227 +#define BCM94710R4_BOARD 0x041c
3228 +#define BCM94710AP_BOARD 0x041d
3229 +
3230 +
3231 +#define BU2050_BOARD 0x041f
3232 +
3233 +
3234 +#define BCM94309G_BOARD 0x0421
3235 +
3236 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
3237 +
3238 +#define BU4704_BOARD 0x0423
3239 +#define BU4702_BOARD 0x0424
3240 +
3241 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
3242 +
3243 +#define BU4317_BOARD 0x0426
3244 +
3245 +
3246 +#define BCM94702MN_BOARD 0x0428
3247 +
3248 +/* BCM4702 1U CompactPCI Board */
3249 +#define BCM94702CPCI_BOARD 0x0429
3250 +
3251 +/* BCM4702 with BCM95380 VLAN Router */
3252 +#define BCM95380RR_BOARD 0x042a
3253 +
3254 +/* cb4306 with SiGe PA */
3255 +#define BCM94306CBSG_BOARD 0x042b
3256 +
3257 +/* mp4301 with 2050 radio */
3258 +#define BCM94301MPL_BOARD 0x042c
3259 +
3260 +/* cb4306 with SiGe PA */
3261 +#define PCSG94306_BOARD 0x042d
3262 +
3263 +/* bu4704 with sdram */
3264 +#define BU4704SD_BOARD 0x042e
3265 +
3266 +/* Dual 11a/11g Router */
3267 +#define BCM94704AGR_BOARD 0x042f
3268 +
3269 +/* 11a-only minipci */
3270 +#define BCM94308MP_BOARD 0x0430
3271 +
3272 +
3273 +
3274 +/* BCM94317 boards */
3275 +#define BCM94317CB_BOARD 0x0440
3276 +#define BCM94317MP_BOARD 0x0441
3277 +#define BCM94317PCMCIA_BOARD 0x0442
3278 +#define BCM94317SDIO_BOARD 0x0443
3279 +
3280 +#define BU4712_BOARD 0x0444
3281 +#define BU4712SD_BOARD 0x045d
3282 +#define BU4712L_BOARD 0x045f
3283 +
3284 +/* BCM4712 boards */
3285 +#define BCM94712AP_BOARD 0x0445
3286 +#define BCM94712P_BOARD 0x0446
3287 +
3288 +/* BCM4318 boards */
3289 +#define BU4318_BOARD 0x0447
3290 +#define CB4318_BOARD 0x0448
3291 +#define MPG4318_BOARD 0x0449
3292 +#define MP4318_BOARD 0x044a
3293 +#define SD4318_BOARD 0x044b
3294 +
3295 +/* BCM63XX boards */
3296 +#define BCM96338_BOARD 0x6338
3297 +#define BCM96345_BOARD 0x6345
3298 +#define BCM96348_BOARD 0x6348
3299 +
3300 +/* Another mp4306 with SiGe */
3301 +#define BCM94306P_BOARD 0x044c
3302 +
3303 +/* CF-like 4317 modules */
3304 +#define BCM94317CF_BOARD 0x044d
3305 +
3306 +/* mp4303 */
3307 +#define BCM94303MP_BOARD 0x044e
3308 +
3309 +/* mpsgh4306 */
3310 +#define BCM94306MPSGH_BOARD 0x044f
3311 +
3312 +/* BRCM 4306 w/ Front End Modules */
3313 +#define BCM94306MPM 0x0450
3314 +#define BCM94306MPL 0x0453
3315 +
3316 +/* 4712agr */
3317 +#define BCM94712AGR_BOARD 0x0451
3318 +
3319 +/* The real CF 4317 board */
3320 +#define CFI4317_BOARD 0x0452
3321 +
3322 +/* pcmcia 4303 */
3323 +#define PC4303_BOARD 0x0454
3324 +
3325 +/* 5350K */
3326 +#define BCM95350K_BOARD 0x0455
3327 +
3328 +/* 5350R */
3329 +#define BCM95350R_BOARD 0x0456
3330 +
3331 +/* 4306mplna */
3332 +#define BCM94306MPLNA_BOARD 0x0457
3333 +
3334 +/* 4320 boards */
3335 +#define BU4320_BOARD 0x0458
3336 +#define BU4320S_BOARD 0x0459
3337 +#define BCM94320PH_BOARD 0x045a
3338 +
3339 +/* 4306mph */
3340 +#define BCM94306MPH_BOARD 0x045b
3341 +
3342 +/* 4306pciv */
3343 +#define BCM94306PCIV_BOARD 0x045c
3344 +
3345 +#define BU4712SD_BOARD 0x045d
3346 +
3347 +#define BCM94320PFLSH_BOARD 0x045e
3348 +
3349 +#define BU4712L_BOARD 0x045f
3350 +#define BCM94712LGR_BOARD 0x0460
3351 +#define BCM94320R_BOARD 0x0461
3352 +
3353 +#define BU5352_BOARD 0x0462
3354 +
3355 +#define BCM94318MPGH_BOARD 0x0463
3356 +
3357 +
3358 +#define BCM95352GR_BOARD 0x0467
3359 +
3360 +/* bcm95351agr */
3361 +#define BCM95351AGR_BOARD 0x0470
3362 +
3363 +/* # of GPIO pins */
3364 +#define GPIO_NUMPINS 16
3365 +
3366 +#endif /* _BCMDEVS_H */
3367 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
3368 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
3369 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2006-04-27 20:08:35.000000000 +0200
3370 @@ -0,0 +1,198 @@
3371 +/*
3372 + * local version of endian.h - byte order defines
3373 + *
3374 + * Copyright 2006, Broadcom Corporation
3375 + * All Rights Reserved.
3376 + *
3377 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3378 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3379 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3380 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3381 + *
3382 + * $Id: bcmendian.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
3383 +*/
3384 +
3385 +#ifndef _BCMENDIAN_H_
3386 +#define _BCMENDIAN_H_
3387 +
3388 +#include <typedefs.h>
3389 +
3390 +/* Byte swap a 16 bit value */
3391 +#define BCMSWAP16(val) \
3392 + ((uint16)(\
3393 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
3394 + (((uint16)(val) & (uint16)0xff00U) >> 8)))
3395 +
3396 +/* Byte swap a 32 bit value */
3397 +#define BCMSWAP32(val) \
3398 + ((uint32)(\
3399 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
3400 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
3401 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
3402 + (((uint32)(val) & (uint32)0xff000000UL) >> 24)))
3403 +
3404 +/* 2 Byte swap a 32 bit value */
3405 +#define BCMSWAP32BY16(val) \
3406 + ((uint32)(\
3407 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
3408 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16)))
3409 +
3410 +
3411 +static INLINE uint16
3412 +bcmswap16(uint16 val)
3413 +{
3414 + return BCMSWAP16(val);
3415 +}
3416 +
3417 +static INLINE uint32
3418 +bcmswap32(uint32 val)
3419 +{
3420 + return BCMSWAP32(val);
3421 +}
3422 +
3423 +static INLINE uint32
3424 +bcmswap32by16(uint32 val)
3425 +{
3426 + return BCMSWAP32BY16(val);
3427 +}
3428 +
3429 +/* buf - start of buffer of shorts to swap */
3430 +/* len - byte length of buffer */
3431 +static INLINE void
3432 +bcmswap16_buf(uint16 *buf, uint len)
3433 +{
3434 + len = len/2;
3435 +
3436 + while (len--) {
3437 + *buf = bcmswap16(*buf);
3438 + buf++;
3439 + }
3440 +}
3441 +
3442 +#ifndef hton16
3443 +#ifndef IL_BIGENDIAN
3444 +#define HTON16(i) BCMSWAP16(i)
3445 +#define hton16(i) bcmswap16(i)
3446 +#define hton32(i) bcmswap32(i)
3447 +#define ntoh16(i) bcmswap16(i)
3448 +#define ntoh32(i) bcmswap32(i)
3449 +#define ltoh16(i) (i)
3450 +#define ltoh32(i) (i)
3451 +#define htol16(i) (i)
3452 +#define htol32(i) (i)
3453 +#else
3454 +#define HTON16(i) (i)
3455 +#define hton16(i) (i)
3456 +#define hton32(i) (i)
3457 +#define ntoh16(i) (i)
3458 +#define ntoh32(i) (i)
3459 +#define ltoh16(i) bcmswap16(i)
3460 +#define ltoh32(i) bcmswap32(i)
3461 +#define htol16(i) bcmswap16(i)
3462 +#define htol32(i) bcmswap32(i)
3463 +#endif /* IL_BIGENDIAN */
3464 +#endif /* hton16 */
3465 +
3466 +#ifndef IL_BIGENDIAN
3467 +#define ltoh16_buf(buf, i)
3468 +#define htol16_buf(buf, i)
3469 +#else
3470 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
3471 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
3472 +#endif /* IL_BIGENDIAN */
3473 +
3474 +/*
3475 +* store 16-bit value to unaligned little endian byte array.
3476 +*/
3477 +static INLINE void
3478 +htol16_ua_store(uint16 val, uint8 *bytes)
3479 +{
3480 + bytes[0] = val&0xff;
3481 + bytes[1] = val>>8;
3482 +}
3483 +
3484 +/*
3485 +* store 32-bit value to unaligned little endian byte array.
3486 +*/
3487 +static INLINE void
3488 +htol32_ua_store(uint32 val, uint8 *bytes)
3489 +{
3490 + bytes[0] = val&0xff;
3491 + bytes[1] = (val>>8)&0xff;
3492 + bytes[2] = (val>>16)&0xff;
3493 + bytes[3] = val>>24;
3494 +}
3495 +
3496 +/*
3497 +* store 16-bit value to unaligned network(big) endian byte array.
3498 +*/
3499 +static INLINE void
3500 +hton16_ua_store(uint16 val, uint8 *bytes)
3501 +{
3502 + bytes[1] = val&0xff;
3503 + bytes[0] = val>>8;
3504 +}
3505 +
3506 +/*
3507 +* store 32-bit value to unaligned network(big) endian byte array.
3508 +*/
3509 +static INLINE void
3510 +hton32_ua_store(uint32 val, uint8 *bytes)
3511 +{
3512 + bytes[3] = val&0xff;
3513 + bytes[2] = (val>>8)&0xff;
3514 + bytes[1] = (val>>16)&0xff;
3515 + bytes[0] = val>>24;
3516 +}
3517 +
3518 +/*
3519 +* load 16-bit value from unaligned little endian byte array.
3520 +*/
3521 +static INLINE uint16
3522 +ltoh16_ua(void *bytes)
3523 +{
3524 + return (((uint8*)bytes)[1]<<8)+((uint8 *)bytes)[0];
3525 +}
3526 +
3527 +/*
3528 +* load 32-bit value from unaligned little endian byte array.
3529 +*/
3530 +static INLINE uint32
3531 +ltoh32_ua(void *bytes)
3532 +{
3533 + return (((uint8*)bytes)[3]<<24)+(((uint8*)bytes)[2]<<16)+
3534 + (((uint8*)bytes)[1]<<8)+((uint8*)bytes)[0];
3535 +}
3536 +
3537 +/*
3538 +* load 16-bit value from unaligned big(network) endian byte array.
3539 +*/
3540 +static INLINE uint16
3541 +ntoh16_ua(void *bytes)
3542 +{
3543 + return (((uint8*)bytes)[0]<<8)+((uint8*)bytes)[1];
3544 +}
3545 +
3546 +/*
3547 +* load 32-bit value from unaligned big(network) endian byte array.
3548 +*/
3549 +static INLINE uint32
3550 +ntoh32_ua(void *bytes)
3551 +{
3552 + return (((uint8*)bytes)[0]<<24)+(((uint8*)bytes)[1]<<16)+
3553 + (((uint8*)bytes)[2]<<8)+((uint8*)bytes)[3];
3554 +}
3555 +
3556 +#define ltoh_ua(ptr) (\
3557 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
3558 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
3559 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
3560 +)
3561 +
3562 +#define ntoh_ua(ptr) (\
3563 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
3564 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
3565 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
3566 +)
3567 +
3568 +#endif /* _BCMENDIAN_H_ */
3569 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
3570 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
3571 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2006-04-27 23:29:18.000000000 +0200
3572 @@ -0,0 +1,159 @@
3573 +/*
3574 + * NVRAM variable manipulation
3575 + *
3576 + * Copyright 2006, Broadcom Corporation
3577 + * All Rights Reserved.
3578 + *
3579 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3580 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3581 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3582 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3583 + *
3584 + * $Id: bcmnvram.h,v 1.17 2006/03/02 12:33:44 honor Exp $
3585 + */
3586 +
3587 +#ifndef _bcmnvram_h_
3588 +#define _bcmnvram_h_
3589 +
3590 +#ifndef _LANGUAGE_ASSEMBLY
3591 +
3592 +#include <typedefs.h>
3593 +#include <bcmdefs.h>
3594 +
3595 +struct nvram_header {
3596 + uint32 magic;
3597 + uint32 len;
3598 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
3599 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
3600 + uint32 config_ncdl; /* ncdl values for memc */
3601 +};
3602 +
3603 +struct nvram_tuple {
3604 + char *name;
3605 + char *value;
3606 + struct nvram_tuple *next;
3607 +};
3608 +
3609 +/*
3610 + * Initialize NVRAM access. May be unnecessary or undefined on certain
3611 + * platforms.
3612 + */
3613 +extern int nvram_init(void *sbh);
3614 +
3615 +/*
3616 + * Disable NVRAM access. May be unnecessary or undefined on certain
3617 + * platforms.
3618 + */
3619 +extern void nvram_exit(void *sbh);
3620 +
3621 +/*
3622 + * Get the value of an NVRAM variable. The pointer returned may be
3623 + * invalid after a set.
3624 + * @param name name of variable to get
3625 + * @return value of variable or NULL if undefined
3626 + */
3627 +extern char * nvram_get(const char *name);
3628 +
3629 +/*
3630 + * Read the reset GPIO value from the nvram and set the GPIO
3631 + * as input
3632 + */
3633 +extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
3634 +extern int BCMINITFN(nvram_gpio_init)(const char *name, void *sbh);
3635 +extern int BCMINITFN(nvram_gpio_set)(const char *name, void *sbh, int type);
3636 +
3637 +/*
3638 + * Get the value of an NVRAM variable.
3639 + * @param name name of variable to get
3640 + * @return value of variable or NUL if undefined
3641 + */
3642 +#define nvram_safe_get(name) (nvram_get(name) ? : "")
3643 +
3644 +#define nvram_safe_unset(name) ({ \
3645 + if(nvram_get(name)) \
3646 + nvram_unset(name); \
3647 +})
3648 +
3649 +#define nvram_safe_set(name, value) ({ \
3650 + if(!nvram_get(name) || strcmp(nvram_get(name), value)) \
3651 + nvram_set(name, value); \
3652 +})
3653 +
3654 +/*
3655 + * Match an NVRAM variable.
3656 + * @param name name of variable to match
3657 + * @param match value to compare against value of variable
3658 + * @return TRUE if variable is defined and its value is string equal
3659 + * to match or FALSE otherwise
3660 + */
3661 +static INLINE int
3662 +nvram_match(char *name, char *match) {
3663 + const char *value = nvram_get(name);
3664 + return (value && !strcmp(value, match));
3665 +}
3666 +
3667 +/*
3668 + * Inversely match an NVRAM variable.
3669 + * @param name name of variable to match
3670 + * @param match value to compare against value of variable
3671 + * @return TRUE if variable is defined and its value is not string
3672 + * equal to invmatch or FALSE otherwise
3673 + */
3674 +static INLINE int
3675 +nvram_invmatch(char *name, char *invmatch) {
3676 + const char *value = nvram_get(name);
3677 + return (value && strcmp(value, invmatch));
3678 +}
3679 +
3680 +/*
3681 + * Set the value of an NVRAM variable. The name and value strings are
3682 + * copied into private storage. Pointers to previously set values
3683 + * may become invalid. The new value may be immediately
3684 + * retrieved but will not be permanently stored until a commit.
3685 + * @param name name of variable to set
3686 + * @param value value of variable
3687 + * @return 0 on success and errno on failure
3688 + */
3689 +extern int nvram_set(const char *name, const char *value);
3690 +
3691 +/*
3692 + * Unset an NVRAM variable. Pointers to previously set values
3693 + * remain valid until a set.
3694 + * @param name name of variable to unset
3695 + * @return 0 on success and errno on failure
3696 + * NOTE: use nvram_commit to commit this change to flash.
3697 + */
3698 +extern int nvram_unset(const char *name);
3699 +
3700 +/*
3701 + * Commit NVRAM variables to permanent storage. All pointers to values
3702 + * may be invalid after a commit.
3703 + * NVRAM values are undefined after a commit.
3704 + * @return 0 on success and errno on failure
3705 + */
3706 +extern int nvram_commit(void);
3707 +
3708 +/*
3709 + * Get all NVRAM variables (format name=value\0 ... \0\0).
3710 + * @param buf buffer to store variables
3711 + * @param count size of buffer in bytes
3712 + * @return 0 on success and errno on failure
3713 + */
3714 +extern int nvram_getall(char *buf, int count);
3715 +
3716 +extern int file2nvram(char *filename, char *varname);
3717 +extern int nvram2file(char *varname, char *filename);
3718 +
3719 +#endif /* _LANGUAGE_ASSEMBLY */
3720 +
3721 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
3722 +#define NVRAM_CLEAR_MAGIC 0x0
3723 +#define NVRAM_INVALID_MAGIC 0xFFFFFFFF
3724 +#define NVRAM_VERSION 1
3725 +#define NVRAM_HEADER_SIZE 20
3726 +#define NVRAM_SPACE 0x8000
3727 +
3728 +#define NVRAM_MAX_VALUE_LEN 255
3729 +#define NVRAM_MAX_PARAM_LEN 64
3730 +
3731 +#endif /* _bcmnvram_h_ */
3732 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
3733 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
3734 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2006-04-27 20:27:33.000000000 +0200
3735 @@ -0,0 +1,108 @@
3736 +/*
3737 + * Misc useful routines to access NIC local SROM/OTP .
3738 + *
3739 + * Copyright 2006, Broadcom Corporation
3740 + * All Rights Reserved.
3741 + *
3742 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3743 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3744 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3745 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3746 + *
3747 + * $Id: bcmsrom.h,v 1.1.1.13 2006/04/15 01:29:08 michael Exp $
3748 + */
3749 +
3750 +#ifndef _bcmsrom_h_
3751 +#define _bcmsrom_h_
3752 +
3753 +/* Maximum srom: 4 Kilobits == 512 bytes */
3754 +#define SROM_MAX 512
3755 +
3756 +/* SROM Rev 4: Reallocate the software part of the srom to accomodate
3757 + * MIMO features. It assumes up to two PCIE functions and 440 bytes
3758 + * of useable srom i.e. the useable storage in chips with OTP that
3759 + * implements hardware redundancy.
3760 + */
3761 +
3762 +#define SROM4_WORDS 220
3763 +
3764 +#define SROM4_SIGN 32
3765 +#define SROM4_SIGNATURE 0x5372
3766 +
3767 +#define SROM4_BREV 33
3768 +
3769 +#define SROM4_BFL0 34
3770 +#define SROM4_BFL1 35
3771 +#define SROM4_BFL2 36
3772 +#define SROM4_BFL3 37
3773 +
3774 +#define SROM4_MACHI 38
3775 +#define SROM4_MACMID 39
3776 +#define SROM4_MACLO 40
3777 +
3778 +#define SROM4_CCODE 41
3779 +#define SROM4_REGREV 42
3780 +
3781 +#define SROM4_LEDBH10 43
3782 +#define SROM4_LEDBH32 44
3783 +
3784 +#define SROM4_LEDDC 45
3785 +
3786 +#define SROM4_AA 46
3787 +#define SROM4_AA2G_MASK 0x00ff
3788 +#define SROM4_AA2G_SHIFT 0
3789 +#define SROM4_AA5G_MASK 0xff00
3790 +#define SROM4_AA5G_SHIFT 8
3791 +
3792 +#define SROM4_AG10 47
3793 +#define SROM4_AG32 48
3794 +
3795 +#define SROM4_TXPID2G 49
3796 +#define SROM4_TXPID5G 51
3797 +#define SROM4_TXPID5GL 53
3798 +#define SROM4_TXPID5GH 55
3799 +
3800 +/* Per-path fields */
3801 +#define MAX_PATH 4
3802 +#define SROM4_PATH0 64
3803 +#define SROM4_PATH1 87
3804 +#define SROM4_PATH2 110
3805 +#define SROM4_PATH3 133
3806 +
3807 +#define SROM4_2G_ITT_MAXP 0
3808 +#define SROM4_2G_PA 1
3809 +#define SROM4_5G_ITT_MAXP 5
3810 +#define SROM4_5GLH_MAXP 6
3811 +#define SROM4_5G_PA 7
3812 +#define SROM4_5GL_PA 11
3813 +#define SROM4_5GH_PA 15
3814 +
3815 +/* Fields in the ITT_MAXP and 5GLH_MAXP words */
3816 +#define B2G_MAXP_MASK 0xff
3817 +#define B2G_ITT_SHIFT 8
3818 +#define B5G_MAXP_MASK 0xff
3819 +#define B5G_ITT_SHIFT 8
3820 +#define B5GH_MAXP_MASK 0xff
3821 +#define B5GL_MAXP_SHIFT 8
3822 +
3823 +/* All the miriad power offsets */
3824 +#define SROM4_2G_CCKPO 156
3825 +#define SROM4_2G_OFDMPO 157
3826 +#define SROM4_5G_OFDMPO 159
3827 +#define SROM4_5GL_OFDMPO 161
3828 +#define SROM4_5GH_OFDMPO 163
3829 +#define SROM4_2G_MCSPO 165
3830 +#define SROM4_5G_MCSPO 173
3831 +#define SROM4_5GL_MCSPO 181
3832 +#define SROM4_5GH_MCSPO 189
3833 +#define SROM4_CCDPO 197
3834 +#define SROM4_STBCPO 198
3835 +#define SROM4_BW40PO 199
3836 +#define SROM4_BWDUPPO 200
3837 +
3838 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, uint *count);
3839 +
3840 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
3841 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
3842 +
3843 +#endif /* _bcmsrom_h_ */
3844 diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
3845 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
3846 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2006-05-02 01:52:12.000000000 +0200
3847 @@ -0,0 +1,433 @@
3848 +/*
3849 + * Misc useful os-independent macros and functions.
3850 + *
3851 + * Copyright 2006, Broadcom Corporation
3852 + * All Rights Reserved.
3853 + *
3854 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3855 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3856 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3857 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3858 + * $Id: bcmutils.h,v 1.1.1.16 2006/04/08 06:13:39 honor Exp $
3859 + */
3860 +
3861 +#ifndef _bcmutils_h_
3862 +#define _bcmutils_h_
3863 +
3864 +/* ** driver-only section ** */
3865 +#ifdef BCMDRIVER
3866 +
3867 +#define _BCM_U 0x01 /* upper */
3868 +#define _BCM_L 0x02 /* lower */
3869 +#define _BCM_D 0x04 /* digit */
3870 +#define _BCM_C 0x08 /* cntrl */
3871 +#define _BCM_P 0x10 /* punct */
3872 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
3873 +#define _BCM_X 0x40 /* hex digit */
3874 +#define _BCM_SP 0x80 /* hard space (0x20) */
3875 +
3876 +#define GPIO_PIN_NOTDEFINED 0x20 /* Pin not defined */
3877 +
3878 +extern unsigned char bcm_ctype[];
3879 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
3880 +
3881 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
3882 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
3883 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
3884 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
3885 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
3886 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
3887 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
3888 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
3889 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
3890 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
3891 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
3892 +
3893 +/*
3894 + * Spin at most 'us' microseconds while 'exp' is true.
3895 + * Caller should explicitly test 'exp' when this completes
3896 + * and take appropriate error action if 'exp' is still true.
3897 + */
3898 +#define SPINWAIT(exp, us) { \
3899 + uint countdown = (us) + 9; \
3900 + while ((exp) && (countdown >= 10)) {\
3901 + OSL_DELAY(10); \
3902 + countdown -= 10; \
3903 + } \
3904 +}
3905 +
3906 +struct ether_addr {
3907 + uint8 octet[6];
3908 +} __attribute__((packed));
3909 +
3910 +/* string */
3911 +extern uchar bcm_toupper(uchar c);
3912 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
3913 +extern char *bcmstrstr(char *haystack, char *needle);
3914 +extern char *bcmstrcat(char *dest, const char *src);
3915 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
3916 +/* ethernet address */
3917 +extern char *bcm_ether_ntoa(struct ether_addr *ea, char *buf);
3918 +/* variable access */
3919 +extern char *getvar(char *vars, char *name);
3920 +extern int getintvar(char *vars, char *name);
3921 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
3922 +#ifdef BCMPERFSTATS
3923 +extern void bcm_perf_enable(void);
3924 +extern void bcmstats(char *fmt);
3925 +extern void bcmlog(char *fmt, uint a1, uint a2);
3926 +extern void bcmdumplog(char *buf, int size);
3927 +extern int bcmdumplogent(char *buf, uint idx);
3928 +#else
3929 +#define bcm_perf_enable()
3930 +#define bcmstats(fmt)
3931 +#define bcmlog(fmt, a1, a2)
3932 +#define bcmdumplog(buf, size) *buf = '\0'
3933 +#define bcmdumplogent(buf, idx) -1
3934 +#endif /* BCMPERFSTATS */
3935 +extern char *bcm_nvram_vars(uint *length);
3936 +extern int bcm_nvram_cache(void *sbh);
3937 +
3938 +/* Support for sharing code across in-driver iovar implementations.
3939 + * The intent is that a driver use this structure to map iovar names
3940 + * to its (private) iovar identifiers, and the lookup function to
3941 + * find the entry. Macros are provided to map ids and get/set actions
3942 + * into a single number space for a switch statement.
3943 + */
3944 +
3945 +/* iovar structure */
3946 +typedef struct bcm_iovar {
3947 + const char *name; /* name for lookup and display */
3948 + uint16 varid; /* id for switch */
3949 + uint16 flags; /* driver-specific flag bits */
3950 + uint16 type; /* base type of argument */
3951 + uint16 minlen; /* min length for buffer vars */
3952 +} bcm_iovar_t;
3953 +
3954 +/* varid definitions are per-driver, may use these get/set bits */
3955 +
3956 +/* IOVar action bits for id mapping */
3957 +#define IOV_GET 0 /* Get an iovar */
3958 +#define IOV_SET 1 /* Set an iovar */
3959 +
3960 +/* Varid to actionid mapping */
3961 +#define IOV_GVAL(id) ((id)*2)
3962 +#define IOV_SVAL(id) (((id)*2)+IOV_SET)
3963 +#define IOV_ISSET(actionid) ((actionid & IOV_SET) == IOV_SET)
3964 +
3965 +/* flags are per-driver based on driver attributes */
3966 +
3967 +/* Base type definitions */
3968 +#define IOVT_VOID 0 /* no value (implictly set only) */
3969 +#define IOVT_BOOL 1 /* any value ok (zero/nonzero) */
3970 +#define IOVT_INT8 2 /* integer values are range-checked */
3971 +#define IOVT_UINT8 3 /* unsigned int 8 bits */
3972 +#define IOVT_INT16 4 /* int 16 bits */
3973 +#define IOVT_UINT16 5 /* unsigned int 16 bits */
3974 +#define IOVT_INT32 6 /* int 32 bits */
3975 +#define IOVT_UINT32 7 /* unsigned int 32 bits */
3976 +#define IOVT_BUFFER 8 /* buffer is size-checked as per minlen */
3977 +
3978 +extern const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name);
3979 +extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool set);
3980 +
3981 +#endif /* #ifdef BCMDRIVER */
3982 +
3983 +/* ** driver/apps-shared section ** */
3984 +
3985 +#define BCME_STRLEN 64 /* Max string length for BCM errors */
3986 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
3987 +
3988 +
3989 +/*
3990 + * error codes could be added but the defined ones shouldn't be changed/deleted
3991 + * these error codes are exposed to the user code
3992 + * when ever a new error code is added to this list
3993 + * please update errorstring table with the related error string and
3994 + * update osl files with os specific errorcode map
3995 +*/
3996 +
3997 +#define BCME_OK 0 /* Success */
3998 +#define BCME_ERROR -1 /* Error generic */
3999 +#define BCME_BADARG -2 /* Bad Argument */
4000 +#define BCME_BADOPTION -3 /* Bad option */
4001 +#define BCME_NOTUP -4 /* Not up */
4002 +#define BCME_NOTDOWN -5 /* Not down */
4003 +#define BCME_NOTAP -6 /* Not AP */
4004 +#define BCME_NOTSTA -7 /* Not STA */
4005 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
4006 +#define BCME_RADIOOFF -9 /* Radio Off */
4007 +#define BCME_NOTBANDLOCKED -10 /* Not band locked */
4008 +#define BCME_NOCLK -11 /* No Clock */
4009 +#define BCME_BADRATESET -12 /* BAD Rate valueset */
4010 +#define BCME_BADBAND -13 /* BAD Band */
4011 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
4012 +#define BCME_BUFTOOLONG -15 /* Buffer too long */
4013 +#define BCME_BUSY -16 /* Busy */
4014 +#define BCME_NOTASSOCIATED -17 /* Not Associated */
4015 +#define BCME_BADSSIDLEN -18 /* Bad SSID len */
4016 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel */
4017 +#define BCME_BADCHAN -20 /* Bad Channel */
4018 +#define BCME_BADADDR -21 /* Bad Address */
4019 +#define BCME_NORESOURCE -22 /* Not Enough Resources */
4020 +#define BCME_UNSUPPORTED -23 /* Unsupported */
4021 +#define BCME_BADLEN -24 /* Bad length */
4022 +#define BCME_NOTREADY -25 /* Not Ready */
4023 +#define BCME_EPERM -26 /* Not Permitted */
4024 +#define BCME_NOMEM -27 /* No Memory */
4025 +#define BCME_ASSOCIATED -28 /* Associated */
4026 +#define BCME_RANGE -29 /* Not In Range */
4027 +#define BCME_NOTFOUND -30 /* Not Found */
4028 +#define BCME_WME_NOT_ENABLED -31 /* WME Not Enabled */
4029 +#define BCME_TSPEC_NOTFOUND -32 /* TSPEC Not Found */
4030 +#define BCME_ACM_NOTSUPPORTED -33 /* ACM Not Supported */
4031 +#define BCME_NOT_WME_ASSOCIATION -34 /* Not WME Association */
4032 +#define BCME_SDIO_ERROR -35 /* SDIO Bus Error */
4033 +#define BCME_DONGLE_DOWN -36 /* Dongle Not Accessible */
4034 +#define BCME_LAST BCME_DONGLE_DOWN
4035 +
4036 +/* These are collection of BCME Error strings */
4037 +#define BCMERRSTRINGTABLE { \
4038 + "OK", \
4039 + "Undefined error", \
4040 + "Bad Argument", \
4041 + "Bad Option", \
4042 + "Not up", \
4043 + "Not down", \
4044 + "Not AP", \
4045 + "Not STA", \
4046 + "Bad Key Index", \
4047 + "Radio Off", \
4048 + "Not band locked", \
4049 + "No clock", \
4050 + "Bad Rate valueset", \
4051 + "Bad Band", \
4052 + "Buffer too short", \
4053 + "Buffer too long", \
4054 + "Busy", \
4055 + "Not Associated", \
4056 + "Bad SSID len", \
4057 + "Out of Range Channel", \
4058 + "Bad Channel", \
4059 + "Bad Address", \
4060 + "Not Enough Resources", \
4061 + "Unsupported", \
4062 + "Bad length", \
4063 + "Not Ready", \
4064 + "Not Permitted", \
4065 + "No Memory", \
4066 + "Associated", \
4067 + "Not In Range", \
4068 + "Not Found", \
4069 + "WME Not Enabled", \
4070 + "TSPEC Not Found", \
4071 + "ACM Not Supported", \
4072 + "Not WME Association", \
4073 + "SDIO Bus Error", \
4074 + "Dongle Not Accessible" \
4075 +}
4076 +
4077 +#ifndef ABS
4078 +#define ABS(a) (((a) < 0)?-(a):(a))
4079 +#endif /* ABS */
4080 +
4081 +#ifndef MIN
4082 +#define MIN(a, b) (((a) < (b))?(a):(b))
4083 +#endif /* MIN */
4084 +
4085 +#ifndef MAX
4086 +#define MAX(a, b) (((a) > (b))?(a):(b))
4087 +#endif /* MAX */
4088 +
4089 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
4090 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
4091 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
4092 +#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0)
4093 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
4094 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
4095 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
4096 +
4097 +/* bit map related macros */
4098 +#ifndef setbit
4099 +#ifndef NBBY /* the BSD family defines NBBY */
4100 +#define NBBY 8 /* 8 bits per byte */
4101 +#endif /* #ifndef NBBY */
4102 +#define setbit(a, i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
4103 +#define clrbit(a, i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
4104 +#define isset(a, i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
4105 +#define isclr(a, i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
4106 +#endif /* setbit */
4107 +
4108 +#define NBITS(type) (sizeof(type) * 8)
4109 +#define NBITVAL(nbits) (1 << (nbits))
4110 +#define MAXBITVAL(nbits) ((1 << (nbits)) - 1)
4111 +#define NBITMASK(nbits) MAXBITVAL(nbits)
4112 +#define MAXNBVAL(nbyte) MAXBITVAL((nbyte) * 8)
4113 +
4114 +/* basic mux operation - can be optimized on several architectures */
4115 +#define MUX(pred, true, false) ((pred) ? (true) : (false))
4116 +
4117 +/* modulo inc/dec - assumes x E [0, bound - 1] */
4118 +#define MODDEC(x, bound) MUX((x) == 0, (bound) - 1, (x) - 1)
4119 +#define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
4120 +
4121 +/* modulo inc/dec, bound = 2^k */
4122 +#define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1))
4123 +#define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1))
4124 +
4125 +/* modulo add/sub - assumes x, y E [0, bound - 1] */
4126 +#define MODADD(x, y, bound) \
4127 + MUX((x) + (y) >= (bound), (x) + (y) - (bound), (x) + (y))
4128 +#define MODSUB(x, y, bound) \
4129 + MUX(((int)(x)) - ((int)(y)) < 0, (x) - (y) + (bound), (x) - (y))
4130 +
4131 +/* module add/sub, bound = 2^k */
4132 +#define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
4133 +#define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
4134 +
4135 +/* crc defines */
4136 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
4137 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
4138 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
4139 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
4140 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
4141 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
4142 +
4143 +/* bcm_format_flags() bit description structure */
4144 +typedef struct bcm_bit_desc {
4145 + uint32 bit;
4146 + char* name;
4147 +} bcm_bit_desc_t;
4148 +
4149 +/* tag_ID/length/value_buffer tuple */
4150 +typedef struct bcm_tlv {
4151 + uint8 id;
4152 + uint8 len;
4153 + uint8 data[1];
4154 +} bcm_tlv_t;
4155 +
4156 +/* Check that bcm_tlv_t fits into the given buflen */
4157 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
4158 +
4159 +/* buffer length for ethernet address from bcm_ether_ntoa() */
4160 +#define ETHER_ADDR_STR_LEN 18 /* 18-bytes of Ethernet address buffer length */
4161 +
4162 +/* unaligned load and store macros */
4163 +#ifdef IL_BIGENDIAN
4164 +static INLINE uint32
4165 +load32_ua(uint8 *a)
4166 +{
4167 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
4168 +}
4169 +
4170 +static INLINE void
4171 +store32_ua(uint8 *a, uint32 v)
4172 +{
4173 + a[0] = (v >> 24) & 0xff;
4174 + a[1] = (v >> 16) & 0xff;
4175 + a[2] = (v >> 8) & 0xff;
4176 + a[3] = v & 0xff;
4177 +}
4178 +
4179 +static INLINE uint16
4180 +load16_ua(uint8 *a)
4181 +{
4182 + return ((a[0] << 8) | a[1]);
4183 +}
4184 +
4185 +static INLINE void
4186 +store16_ua(uint8 *a, uint16 v)
4187 +{
4188 + a[0] = (v >> 8) & 0xff;
4189 + a[1] = v & 0xff;
4190 +}
4191 +
4192 +#else
4193 +
4194 +static INLINE uint32
4195 +load32_ua(uint8 *a)
4196 +{
4197 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
4198 +}
4199 +
4200 +static INLINE void
4201 +store32_ua(uint8 *a, uint32 v)
4202 +{
4203 + a[3] = (v >> 24) & 0xff;
4204 + a[2] = (v >> 16) & 0xff;
4205 + a[1] = (v >> 8) & 0xff;
4206 + a[0] = v & 0xff;
4207 +}
4208 +
4209 +static INLINE uint16
4210 +load16_ua(uint8 *a)
4211 +{
4212 + return ((a[1] << 8) | a[0]);
4213 +}
4214 +
4215 +static INLINE void
4216 +store16_ua(uint8 *a, uint16 v)
4217 +{
4218 + a[1] = (v >> 8) & 0xff;
4219 + a[0] = v & 0xff;
4220 +}
4221 +
4222 +#endif /* IL_BIGENDIAN */
4223 +
4224 +/* externs */
4225 +/* crc */
4226 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
4227 +extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
4228 +extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
4229 +/* format/print */
4230 +extern void printfbig(char *buf);
4231 +
4232 +/* IE parsing */
4233 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
4234 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
4235 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
4236 +
4237 +/* bcmerror */
4238 +extern const char *bcmerrorstr(int bcmerror);
4239 +
4240 +/* multi-bool data type: set of bools, mbool is true if any is set */
4241 +typedef uint32 mbool;
4242 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
4243 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
4244 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
4245 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
4246 +
4247 +/* power conversion */
4248 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
4249 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
4250 +
4251 +/* generic datastruct to help dump routines */
4252 +struct fielddesc {
4253 + char *nameandfmt;
4254 + uint32 offset;
4255 + uint32 len;
4256 +};
4257 +
4258 +/* Buffer structure for collecting string-formatted data
4259 +* using bcm_bprintf() API.
4260 +* Use bcm_binit() to initialize before use
4261 +*/
4262 +struct bcmstrbuf
4263 +{
4264 + char *buf; /* pointer to current position in origbuf */
4265 + uint size; /* current (residual) size in bytes */
4266 + char *origbuf; /* unmodified pointer to orignal buffer */
4267 + uint origsize; /* unmodified orignal buffer size in bytes */
4268 +};
4269 +
4270 +extern void bcm_binit(struct bcmstrbuf *b, char *buf, uint size);
4271 +extern int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...);
4272 +
4273 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
4274 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str,
4275 + char *buf, uint32 bufsize);
4276 +
4277 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
4278 +extern uint bcm_bitcount(uint8 *bitmap, uint bytelength);
4279 +
4280 +#endif /* _bcmutils_h_ */
4281 diff -urN linux.old/arch/mips/bcm947xx/include/hndcpu.h linux.dev/arch/mips/bcm947xx/include/hndcpu.h
4282 --- linux.old/arch/mips/bcm947xx/include/hndcpu.h 1970-01-01 01:00:00.000000000 +0100
4283 +++ linux.dev/arch/mips/bcm947xx/include/hndcpu.h 2006-04-27 22:14:38.000000000 +0200
4284 @@ -0,0 +1,28 @@
4285 +/*
4286 + * HND SiliconBackplane MIPS/ARM cores software interface.
4287 + *
4288 + * Copyright 2006, Broadcom Corporation
4289 + * All Rights Reserved.
4290 + *
4291 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4292 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4293 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4294 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4295 + *
4296 + * $Id: hndcpu.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
4297 + */
4298 +
4299 +#ifndef _hndcpu_h_
4300 +#define _hndcpu_h_
4301 +
4302 +#if defined(mips)
4303 +#include <hndmips.h>
4304 +#elif defined(__ARM_ARCH_4T__)
4305 +#include <hndarm.h>
4306 +#endif
4307 +
4308 +extern uint sb_irq(sb_t *sbh);
4309 +extern uint32 sb_cpu_clock(sb_t *sbh);
4310 +extern void sb_cpu_wait(void);
4311 +
4312 +#endif /* _hndcpu_h_ */
4313 diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
4314 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
4315 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2006-04-27 20:43:42.000000000 +0200
4316 @@ -0,0 +1,45 @@
4317 +/*
4318 + * HND SiliconBackplane MIPS core software interface.
4319 + *
4320 + * Copyright 2006, Broadcom Corporation
4321 + * All Rights Reserved.
4322 + *
4323 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4324 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4325 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4326 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4327 + *
4328 + * $Id: hndmips.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
4329 + */
4330 +
4331 +#ifndef _hndmips_h_
4332 +#define _hndmips_h_
4333 +
4334 +extern void sb_mips_init(sb_t *sbh, uint shirq_map_base);
4335 +extern bool sb_mips_setclock(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
4336 +extern void enable_pfc(uint32 mode);
4337 +extern uint32 sb_memc_get_ncdl(sb_t *sbh);
4338 +
4339 +#if defined(BCMPERFSTATS)
4340 +/* enable counting - exclusive version. Only one set of counters allowed at a time */
4341 +extern void hndmips_perf_instrcount_enable(void);
4342 +extern void hndmips_perf_icachecount_enable(void);
4343 +extern void hndmips_perf_dcachecount_enable(void);
4344 +/* start and stop counting */
4345 +#define hndmips_perf_start01() \
4346 + MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) | 0x80008000)
4347 +#define hndmips_perf_stop01() \
4348 + MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) & ~0x80008000)
4349 +/* retrieve coutners - counters *decrement* */
4350 +#define hndmips_perf_read0() -(long)(MFC0(C0_PERFORMANCE, 0))
4351 +#define hndmips_perf_read1() -(long)(MFC0(C0_PERFORMANCE, 1))
4352 +#define hndmips_perf_read2() -(long)(MFC0(C0_PERFORMANCE, 2))
4353 +/* enable counting - modular version. Each counters can be enabled separately. */
4354 +extern void hndmips_perf_icache_hit_enable(void);
4355 +extern void hndmips_perf_icache_miss_enable(void);
4356 +extern uint32 hndmips_perf_read_instrcount(void);
4357 +extern uint32 hndmips_perf_read_cache_miss(void);
4358 +extern uint32 hndmips_perf_read_cache_hit(void);
4359 +#endif /* defined(BCMINTERNAL) || defined (BCMPERFSTATS) */
4360 +
4361 +#endif /* _hndmips_h_ */
4362 diff -urN linux.old/arch/mips/bcm947xx/include/hndpci.h linux.dev/arch/mips/bcm947xx/include/hndpci.h
4363 --- linux.old/arch/mips/bcm947xx/include/hndpci.h 1970-01-01 01:00:00.000000000 +0100
4364 +++ linux.dev/arch/mips/bcm947xx/include/hndpci.h 2006-04-27 20:36:48.000000000 +0200
4365 @@ -0,0 +1,30 @@
4366 +/*
4367 + * HND SiliconBackplane PCI core software interface.
4368 + *
4369 + * $Id: hndpci.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
4370 + * Copyright 2006, Broadcom Corporation
4371 + * All Rights Reserved.
4372 + *
4373 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4374 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4375 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4376 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4377 + */
4378 +
4379 +#ifndef _hndpci_h_
4380 +#define _hndpci_h_
4381 +
4382 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4383 + int len);
4384 +extern int extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4385 + int len);
4386 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4387 + int len);
4388 +extern int extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4389 + int len);
4390 +extern void sbpci_ban(uint16 core);
4391 +extern int sbpci_init(sb_t *sbh);
4392 +extern int sbpci_init_pci(sb_t *sbh);
4393 +extern void sbpci_check(sb_t *sbh);
4394 +
4395 +#endif /* _hndpci_h_ */
4396 diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
4397 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
4398 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2006-04-27 20:10:08.000000000 +0200
4399 @@ -0,0 +1,417 @@
4400 +/*
4401 + * Linux-specific abstractions to gain some independence from linux kernel versions.
4402 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
4403 + *
4404 + * Copyright 2006, Broadcom Corporation
4405 + * All Rights Reserved.
4406 + *
4407 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4408 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4409 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4410 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4411 + *
4412 + * $Id: linuxver.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
4413 + */
4414 +
4415 +#ifndef _linuxver_h_
4416 +#define _linuxver_h_
4417 +
4418 +#include <linux/config.h>
4419 +#include <linux/version.h>
4420 +
4421 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0))
4422 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
4423 +#ifdef __UNDEF_NO_VERSION__
4424 +#undef __NO_VERSION__
4425 +#else
4426 +#define __NO_VERSION__
4427 +#endif
4428 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0) */
4429 +
4430 +#if defined(MODULE) && defined(MODVERSIONS)
4431 +#include <linux/modversions.h>
4432 +#endif
4433 +
4434 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 0)
4435 +#include <linux/moduleparam.h>
4436 +#endif
4437 +
4438 +
4439 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)
4440 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
4441 +#define module_param_string(_name_, _string_, _size_, _perm_) \
4442 + MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
4443 +#endif
4444 +
4445 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
4446 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 9))
4447 +#include <linux/malloc.h>
4448 +#else
4449 +#include <linux/slab.h>
4450 +#endif
4451 +
4452 +#include <linux/types.h>
4453 +#include <linux/init.h>
4454 +#include <linux/mm.h>
4455 +#include <linux/string.h>
4456 +#include <linux/pci.h>
4457 +#include <linux/interrupt.h>
4458 +#include <linux/netdevice.h>
4459 +#include <asm/io.h>
4460 +
4461 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
4462 +#include <linux/workqueue.h>
4463 +#else
4464 +#include <linux/tqueue.h>
4465 +#ifndef work_struct
4466 +#define work_struct tq_struct
4467 +#endif
4468 +#ifndef INIT_WORK
4469 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
4470 +#endif
4471 +#ifndef schedule_work
4472 +#define schedule_work(_work) schedule_task((_work))
4473 +#endif
4474 +#ifndef flush_scheduled_work
4475 +#define flush_scheduled_work() flush_scheduled_tasks()
4476 +#endif
4477 +#endif /* LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41) */
4478 +
4479 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
4480 +/* Some distributions have their own 2.6.x compatibility layers */
4481 +#ifndef IRQ_NONE
4482 +typedef void irqreturn_t;
4483 +#define IRQ_NONE
4484 +#define IRQ_HANDLED
4485 +#define IRQ_RETVAL(x)
4486 +#endif
4487 +#else
4488 +typedef irqreturn_t(*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
4489 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0) */
4490 +
4491 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
4492 +
4493 +#include <pcmcia/version.h>
4494 +#include <pcmcia/cs_types.h>
4495 +#include <pcmcia/cs.h>
4496 +#include <pcmcia/cistpl.h>
4497 +#include <pcmcia/cisreg.h>
4498 +#include <pcmcia/ds.h>
4499 +
4500 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 69))
4501 +/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
4502 + * does this, but it's not in 2.4 so we do our own for now.
4503 + */
4504 +static inline void
4505 +cs_error(client_handle_t handle, int func, int ret)
4506 +{
4507 + error_info_t err = { func, ret };
4508 + CardServices(ReportError, handle, &err);
4509 +}
4510 +#endif
4511 +
4512 +#endif /* CONFIG_PCMCIA */
4513 +
4514 +#ifndef __exit
4515 +#define __exit
4516 +#endif
4517 +#ifndef __devexit
4518 +#define __devexit
4519 +#endif
4520 +#ifndef __devinit
4521 +#define __devinit __init
4522 +#endif
4523 +#ifndef __devinitdata
4524 +#define __devinitdata
4525 +#endif
4526 +#ifndef __devexit_p
4527 +#define __devexit_p(x) x
4528 +#endif
4529 +
4530 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0))
4531 +
4532 +#define pci_get_drvdata(dev) (dev)->sysdata
4533 +#define pci_set_drvdata(dev, value) (dev)->sysdata = (value)
4534 +
4535 +/*
4536 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
4537 + */
4538 +
4539 +struct pci_device_id {
4540 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
4541 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
4542 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
4543 + unsigned long driver_data; /* Data private to the driver */
4544 +};
4545 +
4546 +struct pci_driver {
4547 + struct list_head node;
4548 + char *name;
4549 + const struct pci_device_id *id_table; /* NULL if wants all devices */
4550 + int (*probe)(struct pci_dev *dev,
4551 + const struct pci_device_id *id); /* New device inserted */
4552 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug
4553 + * capable driver)
4554 + */
4555 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
4556 + void (*resume)(struct pci_dev *dev); /* Device woken up */
4557 +};
4558 +
4559 +#define MODULE_DEVICE_TABLE(type, name)
4560 +#define PCI_ANY_ID (~0)
4561 +
4562 +/* compatpci.c */
4563 +#define pci_module_init pci_register_driver
4564 +extern int pci_register_driver(struct pci_driver *drv);
4565 +extern void pci_unregister_driver(struct pci_driver *drv);
4566 +
4567 +#endif /* PCI registration */
4568 +
4569 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18))
4570 +#ifdef MODULE
4571 +#define module_init(x) int init_module(void) { return x(); }
4572 +#define module_exit(x) void cleanup_module(void) { x(); }
4573 +#else
4574 +#define module_init(x) __initcall(x);
4575 +#define module_exit(x) __exitcall(x);
4576 +#endif
4577 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18) */
4578 +
4579 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 48))
4580 +#define list_for_each(pos, head) \
4581 + for (pos = (head)->next; pos != (head); pos = pos->next)
4582 +#endif
4583 +
4584 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 13))
4585 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
4586 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 44))
4587 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
4588 +#endif
4589 +
4590 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 23))
4591 +#define pci_enable_device(dev) do { } while (0)
4592 +#endif
4593 +
4594 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 14))
4595 +#define net_device device
4596 +#endif
4597 +
4598 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 42))
4599 +
4600 +/*
4601 + * DMA mapping
4602 + *
4603 + * See linux/Documentation/DMA-mapping.txt
4604 + */
4605 +
4606 +#ifndef PCI_DMA_TODEVICE
4607 +#define PCI_DMA_TODEVICE 1
4608 +#define PCI_DMA_FROMDEVICE 2
4609 +#endif
4610 +
4611 +typedef u32 dma_addr_t;
4612 +
4613 +/* Pure 2^n version of get_order */
4614 +static inline int get_order(unsigned long size)
4615 +{
4616 + int order;
4617 +
4618 + size = (size-1) >> (PAGE_SHIFT-1);
4619 + order = -1;
4620 + do {
4621 + size >>= 1;
4622 + order++;
4623 + } while (size);
4624 + return order;
4625 +}
4626 +
4627 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
4628 + dma_addr_t *dma_handle)
4629 +{
4630 + void *ret;
4631 + int gfp = GFP_ATOMIC | GFP_DMA;
4632 +
4633 + ret = (void *)__get_free_pages(gfp, get_order(size));
4634 +
4635 + if (ret != NULL) {
4636 + memset(ret, 0, size);
4637 + *dma_handle = virt_to_bus(ret);
4638 + }
4639 + return ret;
4640 +}
4641 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
4642 + void *vaddr, dma_addr_t dma_handle)
4643 +{
4644 + free_pages((unsigned long)vaddr, get_order(size));
4645 +}
4646 +#ifdef ILSIM
4647 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
4648 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
4649 +#else
4650 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
4651 +#define pci_unmap_single(cookie, address, size, dir)
4652 +#endif
4653 +
4654 +#endif /* DMA mapping */
4655 +
4656 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 43))
4657 +
4658 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
4659 +#define netif_down(dev) do { (dev)->start = 0; } while (0)
4660 +
4661 +/* pcmcia-cs provides its own netdevice compatibility layer */
4662 +#ifndef _COMPAT_NETDEVICE_H
4663 +
4664 +/*
4665 + * SoftNet
4666 + *
4667 + * For pre-softnet kernels we need to tell the upper layer not to
4668 + * re-enter start_xmit() while we are in there. However softnet
4669 + * guarantees not to enter while we are in there so there is no need
4670 + * to do the netif_stop_queue() dance unless the transmit queue really
4671 + * gets stuck. This should also improve performance according to tests
4672 + * done by Aman Singla.
4673 + */
4674 +
4675 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
4676 +#define netif_wake_queue(dev) \
4677 + do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while (0)
4678 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
4679 +
4680 +static inline void netif_start_queue(struct net_device *dev)
4681 +{
4682 + dev->tbusy = 0;
4683 + dev->interrupt = 0;
4684 + dev->start = 1;
4685 +}
4686 +
4687 +#define netif_queue_stopped(dev) (dev)->tbusy
4688 +#define netif_running(dev) (dev)->start
4689 +
4690 +#endif /* _COMPAT_NETDEVICE_H */
4691 +
4692 +#define netif_device_attach(dev) netif_start_queue(dev)
4693 +#define netif_device_detach(dev) netif_stop_queue(dev)
4694 +
4695 +/* 2.4.x renamed bottom halves to tasklets */
4696 +#define tasklet_struct tq_struct
4697 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
4698 +{
4699 + queue_task(tasklet, &tq_immediate);
4700 + mark_bh(IMMEDIATE_BH);
4701 +}
4702 +
4703 +static inline void tasklet_init(struct tasklet_struct *tasklet,
4704 + void (*func)(unsigned long),
4705 + unsigned long data)
4706 +{
4707 + tasklet->next = NULL;
4708 + tasklet->sync = 0;
4709 + tasklet->routine = (void (*)(void *))func;
4710 + tasklet->data = (void *)data;
4711 +}
4712 +#define tasklet_kill(tasklet) { do{} while (0); }
4713 +
4714 +/* 2.4.x introduced del_timer_sync() */
4715 +#define del_timer_sync(timer) del_timer(timer)
4716 +
4717 +#else
4718 +
4719 +#define netif_down(dev)
4720 +
4721 +#endif /* SoftNet */
4722 +
4723 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3))
4724 +
4725 +/*
4726 + * Emit code to initialise a tq_struct's routine and data pointers
4727 + */
4728 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
4729 + do { \
4730 + (_tq)->routine = _routine; \
4731 + (_tq)->data = _data; \
4732 + } while (0)
4733 +
4734 +/*
4735 + * Emit code to initialise all of a tq_struct
4736 + */
4737 +#define INIT_TQUEUE(_tq, _routine, _data) \
4738 + do { \
4739 + INIT_LIST_HEAD(&(_tq)->list); \
4740 + (_tq)->sync = 0; \
4741 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
4742 + } while (0)
4743 +
4744 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3) */
4745 +
4746 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 6))
4747 +
4748 +/* Power management related routines */
4749 +
4750 +static inline int
4751 +pci_save_state(struct pci_dev *dev, u32 *buffer)
4752 +{
4753 + int i;
4754 + if (buffer) {
4755 + for (i = 0; i < 16; i++)
4756 + pci_read_config_dword(dev, i * 4, &buffer[i]);
4757 + }
4758 + return 0;
4759 +}
4760 +
4761 +static inline int
4762 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
4763 +{
4764 + int i;
4765 +
4766 + if (buffer) {
4767 + for (i = 0; i < 16; i++)
4768 + pci_write_config_dword(dev, i * 4, buffer[i]);
4769 + }
4770 + /*
4771 + * otherwise, write the context information we know from bootup.
4772 + * This works around a problem where warm-booting from Windows
4773 + * combined with a D3(hot)->D0 transition causes PCI config
4774 + * header data to be forgotten.
4775 + */
4776 + else {
4777 + for (i = 0; i < 6; i ++)
4778 + pci_write_config_dword(dev,
4779 + PCI_BASE_ADDRESS_0 + (i * 4),
4780 + pci_resource_start(dev, i));
4781 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
4782 + }
4783 + return 0;
4784 +}
4785 +
4786 +#endif /* PCI power management */
4787 +
4788 +/* Old cp0 access macros deprecated in 2.4.19 */
4789 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 19))
4790 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
4791 +#endif
4792 +
4793 +/* Module refcount handled internally in 2.6.x */
4794 +#ifndef SET_MODULE_OWNER
4795 +#define SET_MODULE_OWNER(dev) do {} while (0)
4796 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
4797 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
4798 +#else
4799 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
4800 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
4801 +#endif
4802 +
4803 +#ifndef SET_NETDEV_DEV
4804 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
4805 +#endif
4806 +
4807 +#ifndef HAVE_FREE_NETDEV
4808 +#define free_netdev(dev) kfree(dev)
4809 +#endif
4810 +
4811 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
4812 +/* struct packet_type redefined in 2.6.x */
4813 +#define af_packet_priv data
4814 +#endif
4815 +
4816 +#endif /* _linuxver_h_ */
4817 diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
4818 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
4819 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2006-04-27 22:12:20.000000000 +0200
4820 @@ -0,0 +1,541 @@
4821 +/*
4822 + * HND Run Time Environment for standalone MIPS programs.
4823 + *
4824 + * Copyright 2006, Broadcom Corporation
4825 + * All Rights Reserved.
4826 + *
4827 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4828 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4829 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4830 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4831 + *
4832 + * $Id: mipsinc.h,v 1.1.1.5 2006/02/27 03:43:16 honor Exp $
4833 + */
4834 +
4835 +#ifndef _MISPINC_H
4836 +#define _MISPINC_H
4837 +
4838 +
4839 +/* MIPS defines */
4840 +
4841 +#ifdef _LANGUAGE_ASSEMBLY
4842 +
4843 +/*
4844 + * Symbolic register names for 32 bit ABI
4845 + */
4846 +#define zero $0 /* wired zero */
4847 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
4848 +#define v0 $2 /* return value */
4849 +#define v1 $3
4850 +#define a0 $4 /* argument registers */
4851 +#define a1 $5
4852 +#define a2 $6
4853 +#define a3 $7
4854 +#define t0 $8 /* caller saved */
4855 +#define t1 $9
4856 +#define t2 $10
4857 +#define t3 $11
4858 +#define t4 $12
4859 +#define t5 $13
4860 +#define t6 $14
4861 +#define t7 $15
4862 +#define s0 $16 /* callee saved */
4863 +#define s1 $17
4864 +#define s2 $18
4865 +#define s3 $19
4866 +#define s4 $20
4867 +#define s5 $21
4868 +#define s6 $22
4869 +#define s7 $23
4870 +#define t8 $24 /* caller saved */
4871 +#define t9 $25
4872 +#define jp $25 /* PIC jump register */
4873 +#define k0 $26 /* kernel scratch */
4874 +#define k1 $27
4875 +#define gp $28 /* global pointer */
4876 +#define sp $29 /* stack pointer */
4877 +#define fp $30 /* frame pointer */
4878 +#define s8 $30 /* same like fp! */
4879 +#define ra $31 /* return address */
4880 +
4881 +
4882 +/* CP0 Registers */
4883 +
4884 +#define C0_INX $0
4885 +#define C0_RAND $1
4886 +#define C0_TLBLO0 $2
4887 +#define C0_TLBLO C0_TLBLO0
4888 +#define C0_TLBLO1 $3
4889 +#define C0_CTEXT $4
4890 +#define C0_PGMASK $5
4891 +#define C0_WIRED $6
4892 +#define C0_BADVADDR $8
4893 +#define C0_COUNT $9
4894 +#define C0_TLBHI $10
4895 +#define C0_COMPARE $11
4896 +#define C0_SR $12
4897 +#define C0_STATUS C0_SR
4898 +#define C0_CAUSE $13
4899 +#define C0_EPC $14
4900 +#define C0_PRID $15
4901 +#define C0_CONFIG $16
4902 +#define C0_LLADDR $17
4903 +#define C0_WATCHLO $18
4904 +#define C0_WATCHHI $19
4905 +#define C0_XCTEXT $20
4906 +#define C0_DIAGNOSTIC $22
4907 +#define C0_BROADCOM C0_DIAGNOSTIC
4908 +#define C0_PERFORMANCE $25
4909 +#define C0_ECC $26
4910 +#define C0_CACHEERR $27
4911 +#define C0_TAGLO $28
4912 +#define C0_TAGHI $29
4913 +#define C0_ERREPC $30
4914 +#define C0_DESAVE $31
4915 +
4916 +/*
4917 + * LEAF - declare leaf routine
4918 + */
4919 +#define LEAF(symbol) \
4920 + .globl symbol; \
4921 + .align 2; \
4922 + .type symbol, @function; \
4923 + .ent symbol, 0; \
4924 +symbol: .frame sp, 0, ra
4925 +
4926 +/*
4927 + * END - mark end of function
4928 + */
4929 +#define END(function) \
4930 + .end function; \
4931 + .size function, . - function
4932 +
4933 +#define _ULCAST_
4934 +
4935 +#define MFC0_SEL(dst, src, sel) \
4936 + .word\t(0x40000000 | ((dst) << 16) | ((src) << 11) | (sel))
4937 +
4938 +
4939 +#define MTC0_SEL(dst, src, sel) \
4940 + .word\t(0x40800000 | ((dst) << 16) | ((src) << 11) | (sel))
4941 +
4942 +#else
4943 +
4944 +/*
4945 + * The following macros are especially useful for __asm__
4946 + * inline assembler.
4947 + */
4948 +#ifndef __STR
4949 +#define __STR(x) #x
4950 +#endif
4951 +#ifndef STR
4952 +#define STR(x) __STR(x)
4953 +#endif
4954 +
4955 +#define _ULCAST_ (unsigned long)
4956 +
4957 +
4958 +/* CP0 Registers */
4959 +
4960 +#define C0_INX 0 /* CP0: TLB Index */
4961 +#define C0_RAND 1 /* CP0: TLB Random */
4962 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
4963 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
4964 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
4965 +#define C0_CTEXT 4 /* CP0: Context */
4966 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
4967 +#define C0_WIRED 6 /* CP0: TLB Wired */
4968 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
4969 +#define C0_COUNT 9 /* CP0: Count */
4970 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
4971 +#define C0_COMPARE 11 /* CP0: Compare */
4972 +#define C0_SR 12 /* CP0: Processor Status */
4973 +#define C0_STATUS C0_SR /* CP0: Processor Status */
4974 +#define C0_CAUSE 13 /* CP0: Exception Cause */
4975 +#define C0_EPC 14 /* CP0: Exception PC */
4976 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
4977 +#define C0_CONFIG 16 /* CP0: Config */
4978 +#define C0_LLADDR 17 /* CP0: LLAddr */
4979 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
4980 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
4981 +#define C0_XCTEXT 20 /* CP0: XContext */
4982 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
4983 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
4984 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
4985 +#define C0_ECC 26 /* CP0: ECC */
4986 +#define C0_CACHEERR 27 /* CP0: CacheErr */
4987 +#define C0_TAGLO 28 /* CP0: TagLo */
4988 +#define C0_TAGHI 29 /* CP0: TagHi */
4989 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
4990 +#define C0_DESAVE 31 /* CP0: DebugSave */
4991 +
4992 +#endif /* _LANGUAGE_ASSEMBLY */
4993 +
4994 +/*
4995 + * Memory segments (32bit kernel mode addresses)
4996 + */
4997 +#undef KUSEG
4998 +#undef KSEG0
4999 +#undef KSEG1
5000 +#undef KSEG2
5001 +#undef KSEG3
5002 +#define KUSEG 0x00000000
5003 +#define KSEG0 0x80000000
5004 +#define KSEG1 0xa0000000
5005 +#define KSEG2 0xc0000000
5006 +#define KSEG3 0xe0000000
5007 +#define PHYSADDR_MASK 0x1fffffff
5008 +
5009 +/*
5010 + * Map an address to a certain kernel segment
5011 + */
5012 +#undef PHYSADDR
5013 +#undef KSEG0ADDR
5014 +#undef KSEG1ADDR
5015 +#undef KSEG2ADDR
5016 +#undef KSEG3ADDR
5017 +
5018 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
5019 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
5020 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
5021 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
5022 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
5023 +
5024 +
5025 +#ifndef Index_Invalidate_I
5026 +/*
5027 + * Cache Operations
5028 + */
5029 +#define Index_Invalidate_I 0x00
5030 +#define Index_Writeback_Inv_D 0x01
5031 +#define Index_Invalidate_SI 0x02
5032 +#define Index_Writeback_Inv_SD 0x03
5033 +#define Index_Load_Tag_I 0x04
5034 +#define Index_Load_Tag_D 0x05
5035 +#define Index_Load_Tag_SI 0x06
5036 +#define Index_Load_Tag_SD 0x07
5037 +#define Index_Store_Tag_I 0x08
5038 +#define Index_Store_Tag_D 0x09
5039 +#define Index_Store_Tag_SI 0x0A
5040 +#define Index_Store_Tag_SD 0x0B
5041 +#define Create_Dirty_Excl_D 0x0d
5042 +#define Create_Dirty_Excl_SD 0x0f
5043 +#define Hit_Invalidate_I 0x10
5044 +#define Hit_Invalidate_D 0x11
5045 +#define Hit_Invalidate_SI 0x12
5046 +#define Hit_Invalidate_SD 0x13
5047 +#define Fill_I 0x14
5048 +#define Hit_Writeback_Inv_D 0x15
5049 + /* 0x16 is unused */
5050 +#define Hit_Writeback_Inv_SD 0x17
5051 +#define R5K_Page_Invalidate_S 0x17
5052 +#define Hit_Writeback_I 0x18
5053 +#define Hit_Writeback_D 0x19
5054 + /* 0x1a is unused */
5055 +#define Hit_Writeback_SD 0x1b
5056 + /* 0x1c is unused */
5057 + /* 0x1e is unused */
5058 +#define Hit_Set_Virtual_SI 0x1e
5059 +#define Hit_Set_Virtual_SD 0x1f
5060 +#endif /* !Index_Invalidate_I */
5061 +
5062 +
5063 +/*
5064 + * R4x00 interrupt enable / cause bits
5065 + */
5066 +#define IE_SW0 (_ULCAST_(1) << 8)
5067 +#define IE_SW1 (_ULCAST_(1) << 9)
5068 +#define IE_IRQ0 (_ULCAST_(1) << 10)
5069 +#define IE_IRQ1 (_ULCAST_(1) << 11)
5070 +#define IE_IRQ2 (_ULCAST_(1) << 12)
5071 +#define IE_IRQ3 (_ULCAST_(1) << 13)
5072 +#define IE_IRQ4 (_ULCAST_(1) << 14)
5073 +#define IE_IRQ5 (_ULCAST_(1) << 15)
5074 +
5075 +#ifndef ST0_UM
5076 +/*
5077 + * Bitfields in the mips32 cp0 status register
5078 + */
5079 +#define ST0_IE 0x00000001
5080 +#define ST0_EXL 0x00000002
5081 +#define ST0_ERL 0x00000004
5082 +#define ST0_UM 0x00000010
5083 +#define ST0_SWINT0 0x00000100
5084 +#define ST0_SWINT1 0x00000200
5085 +#define ST0_HWINT0 0x00000400
5086 +#define ST0_HWINT1 0x00000800
5087 +#define ST0_HWINT2 0x00001000
5088 +#define ST0_HWINT3 0x00002000
5089 +#define ST0_HWINT4 0x00004000
5090 +#define ST0_HWINT5 0x00008000
5091 +#define ST0_IM 0x0000ff00
5092 +#define ST0_NMI 0x00080000
5093 +#define ST0_SR 0x00100000
5094 +#define ST0_TS 0x00200000
5095 +#define ST0_BEV 0x00400000
5096 +#define ST0_RE 0x02000000
5097 +#define ST0_RP 0x08000000
5098 +#define ST0_CU 0xf0000000
5099 +#define ST0_CU0 0x10000000
5100 +#define ST0_CU1 0x20000000
5101 +#define ST0_CU2 0x40000000
5102 +#define ST0_CU3 0x80000000
5103 +#endif /* !ST0_UM */
5104 +
5105 +
5106 +/*
5107 + * Bitfields in the mips32 cp0 cause register
5108 + */
5109 +#define C_EXC 0x0000007c
5110 +#define C_EXC_SHIFT 2
5111 +#define C_INT 0x0000ff00
5112 +#define C_INT_SHIFT 8
5113 +#define C_SW0 (_ULCAST_(1) << 8)
5114 +#define C_SW1 (_ULCAST_(1) << 9)
5115 +#define C_IRQ0 (_ULCAST_(1) << 10)
5116 +#define C_IRQ1 (_ULCAST_(1) << 11)
5117 +#define C_IRQ2 (_ULCAST_(1) << 12)
5118 +#define C_IRQ3 (_ULCAST_(1) << 13)
5119 +#define C_IRQ4 (_ULCAST_(1) << 14)
5120 +#define C_IRQ5 (_ULCAST_(1) << 15)
5121 +#define C_WP 0x00400000
5122 +#define C_IV 0x00800000
5123 +#define C_CE 0x30000000
5124 +#define C_CE_SHIFT 28
5125 +#define C_BD 0x80000000
5126 +
5127 +/* Values in C_EXC */
5128 +#define EXC_INT 0
5129 +#define EXC_TLBM 1
5130 +#define EXC_TLBL 2
5131 +#define EXC_TLBS 3
5132 +#define EXC_AEL 4
5133 +#define EXC_AES 5
5134 +#define EXC_IBE 6
5135 +#define EXC_DBE 7
5136 +#define EXC_SYS 8
5137 +#define EXC_BPT 9
5138 +#define EXC_RI 10
5139 +#define EXC_CU 11
5140 +#define EXC_OV 12
5141 +#define EXC_TR 13
5142 +#define EXC_WATCH 23
5143 +#define EXC_MCHK 24
5144 +
5145 +
5146 +/*
5147 + * Bits in the cp0 config register.
5148 + */
5149 +#define CONF_CM_CACHABLE_NO_WA 0
5150 +#define CONF_CM_CACHABLE_WA 1
5151 +#define CONF_CM_UNCACHED 2
5152 +#define CONF_CM_CACHABLE_NONCOHERENT 3
5153 +#define CONF_CM_CACHABLE_CE 4
5154 +#define CONF_CM_CACHABLE_COW 5
5155 +#define CONF_CM_CACHABLE_CUW 6
5156 +#define CONF_CM_CACHABLE_ACCELERATED 7
5157 +#define CONF_CM_CMASK 7
5158 +#define CONF_CU (_ULCAST_(1) << 3)
5159 +#define CONF_DB (_ULCAST_(1) << 4)
5160 +#define CONF_IB (_ULCAST_(1) << 5)
5161 +#define CONF_SE (_ULCAST_(1) << 12)
5162 +#ifndef CONF_BE /* duplicate in mipsregs.h */
5163 +#define CONF_BE (_ULCAST_(1) << 15)
5164 +#endif
5165 +#define CONF_SC (_ULCAST_(1) << 17)
5166 +#define CONF_AC (_ULCAST_(1) << 23)
5167 +#define CONF_HALT (_ULCAST_(1) << 25)
5168 +#ifndef CONF_M /* duplicate in mipsregs.h */
5169 +#define CONF_M (_ULCAST_(1) << 31)
5170 +#endif
5171 +
5172 +
5173 +/*
5174 + * Bits in the cp0 config register select 1.
5175 + */
5176 +#define CONF1_FP 0x00000001 /* FPU present */
5177 +#define CONF1_EP 0x00000002 /* EJTAG present */
5178 +#define CONF1_CA 0x00000004 /* mips16 implemented */
5179 +#define CONF1_WR 0x00000008 /* Watch registers present */
5180 +#define CONF1_PC 0x00000010 /* Performance counters present */
5181 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
5182 +#define CONF1_DA_MASK 0x00000380
5183 +#define CONF1_DA_BASE 1
5184 +#define CONF1_DL_SHIFT 10 /* D$ line size */
5185 +#define CONF1_DL_MASK 0x00001c00
5186 +#define CONF1_DL_BASE 2
5187 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
5188 +#define CONF1_DS_MASK 0x0000e000
5189 +#define CONF1_DS_BASE 64
5190 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
5191 +#define CONF1_IA_MASK 0x00070000
5192 +#define CONF1_IA_BASE 1
5193 +#define CONF1_IL_SHIFT 19 /* I$ line size */
5194 +#define CONF1_IL_MASK 0x00380000
5195 +#define CONF1_IL_BASE 2
5196 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
5197 +#define CONF1_IS_MASK 0x01c00000
5198 +#define CONF1_IS_BASE 64
5199 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
5200 +#define CONF1_MS_SHIFT 25
5201 +
5202 +/* PRID register */
5203 +#define PRID_COPT_MASK 0xff000000
5204 +#define PRID_COMP_MASK 0x00ff0000
5205 +#define PRID_IMP_MASK 0x0000ff00
5206 +#define PRID_REV_MASK 0x000000ff
5207 +
5208 +#define PRID_COMP_LEGACY 0x000000
5209 +#define PRID_COMP_MIPS 0x010000
5210 +#define PRID_COMP_BROADCOM 0x020000
5211 +#define PRID_COMP_ALCHEMY 0x030000
5212 +#define PRID_COMP_SIBYTE 0x040000
5213 +#define PRID_IMP_BCM4710 0x4000
5214 +#define PRID_IMP_BCM3302 0x9000
5215 +#define PRID_IMP_BCM3303 0x9100
5216 +
5217 +#define PRID_IMP_UNKNOWN 0xff00
5218 +
5219 +#define BCM330X(id) \
5220 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
5221 + (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) || \
5222 + ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
5223 + (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
5224 +
5225 +/* Bits in C0_BROADCOM */
5226 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
5227 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
5228 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
5229 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
5230 +#define BRCM_CLF_ENABLE 0x00100000 /* Enable cache line first feature */
5231 +
5232 +/* PreFetch Cache aka Read Ahead Cache */
5233 +
5234 +#define PFC_CR0 0xff400000 /* control reg 0 */
5235 +#define PFC_CR1 0xff400004 /* control reg 1 */
5236 +
5237 +/* PFC operations */
5238 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
5239 +#define PFC_D 0x00000002 /* Enable PFC use for data */
5240 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
5241 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
5242 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
5243 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
5244 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
5245 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
5246 +#define PFC_BRR 0x40000000 /* Bus error indication */
5247 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
5248 +
5249 +/* Handy defaults */
5250 +#define PFC_DISABLED 0
5251 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
5252 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
5253 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
5254 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
5255 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
5256 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
5257 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
5258 +
5259 +#ifndef _LANGUAGE_ASSEMBLY
5260 +
5261 +/*
5262 + * Macros to access the system control coprocessor
5263 + */
5264 +
5265 +#define MFC0(source, sel) \
5266 +({ \
5267 + int __res; \
5268 + __asm__ __volatile__(" \
5269 + .set\tnoreorder; \
5270 + .set\tnoat; \
5271 + .word\t"STR(0x40010000 | ((source) << 11) | (sel))"; \
5272 + move\t%0, $1; \
5273 + .set\tat; \
5274 + .set\treorder" \
5275 + :"=r" (__res) \
5276 + : \
5277 + :"$1"); \
5278 + __res; \
5279 +})
5280 +
5281 +#define MTC0(source, sel, value) \
5282 +do { \
5283 + __asm__ __volatile__(" \
5284 + .set\tnoreorder; \
5285 + .set\tnoat; \
5286 + move\t$1, %z0; \
5287 + .word\t"STR(0x40810000 | ((source) << 11) | (sel))"; \
5288 + .set\tat; \
5289 + .set\treorder" \
5290 + : \
5291 + :"jr" (value) \
5292 + :"$1"); \
5293 +} while (0)
5294 +
5295 +#define get_c0_count() \
5296 +({ \
5297 + int __res; \
5298 + __asm__ __volatile__(" \
5299 + .set\tnoreorder; \
5300 + .set\tnoat; \
5301 + mfc0\t%0, $9; \
5302 + .set\tat; \
5303 + .set\treorder" \
5304 + :"=r" (__res)); \
5305 + __res; \
5306 +})
5307 +
5308 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
5309 +{
5310 + uint lsz, sets, ways;
5311 +
5312 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
5313 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
5314 + lsz = CONF1_IL_BASE << lsz;
5315 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
5316 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
5317 + *size = lsz * sets * ways;
5318 + *lsize = lsz;
5319 +}
5320 +
5321 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
5322 +{
5323 + uint lsz, sets, ways;
5324 +
5325 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
5326 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
5327 + lsz = CONF1_DL_BASE << lsz;
5328 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
5329 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
5330 + *size = lsz * sets * ways;
5331 + *lsize = lsz;
5332 +}
5333 +
5334 +#define cache_op(base, op) \
5335 + __asm__ __volatile__(" \
5336 + .set noreorder; \
5337 + .set mips3; \
5338 + cache %1, (%0); \
5339 + .set mips0; \
5340 + .set reorder" \
5341 + : \
5342 + : "r" (base), \
5343 + "i" (op));
5344 +
5345 +#define cache_unroll4(base, delta, op) \
5346 + __asm__ __volatile__(" \
5347 + .set noreorder; \
5348 + .set mips3; \
5349 + cache %1, 0(%0); \
5350 + cache %1, delta(%0); \
5351 + cache %1, (2 * delta)(%0); \
5352 + cache %1, (3 * delta)(%0); \
5353 + .set mips0; \
5354 + .set reorder" \
5355 + : \
5356 + : "r" (base), \
5357 + "i" (op));
5358 +
5359 +#endif /* !_LANGUAGE_ASSEMBLY */
5360 +
5361 +#endif /* _MISPINC_H */
5362 diff -urN linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
5363 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
5364 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2006-05-02 17:40:43.000000000 +0200
5365 @@ -0,0 +1,179 @@
5366 +#ifndef __osl_h
5367 +#define __osl_h
5368 +
5369 +#include <linux/delay.h>
5370 +#include <typedefs.h>
5371 +#include <linuxver.h>
5372 +#include <bcmutils.h>
5373 +#include <pcicfg.h>
5374 +
5375 +#define ASSERT(n)
5376 +
5377 +/* Pkttag flag should be part of public information */
5378 +struct osl_pubinfo {
5379 + bool pkttag;
5380 + uint pktalloced; /* Number of allocated packet buffers */
5381 +};
5382 +
5383 +struct osl_info {
5384 + struct osl_pubinfo pub;
5385 + uint magic;
5386 + void *pdev;
5387 + uint malloced;
5388 + uint failed;
5389 + void *dbgmem_list;
5390 +};
5391 +
5392 +typedef struct osl_info osl_t;
5393 +
5394 +#define PCI_CFG_RETRY 10
5395 +
5396 +/* map/unmap direction */
5397 +#define DMA_TX 1 /* TX direction for DMA */
5398 +#define DMA_RX 2 /* RX direction for DMA */
5399 +
5400 +#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v))
5401 +#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v))
5402 +#define SET_REG(osh, r, mask, val) W_REG((osh), (r), ((R_REG((osh), r) & ~(mask)) | (val)))
5403 +
5404 +/* bcopy, bcmp, and bzero */
5405 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
5406 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
5407 +#define bzero(b, len) memset((b), '\0', (len))
5408 +
5409 +/* uncached virtual address */
5410 +#ifdef mips
5411 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
5412 +#include <asm/addrspace.h>
5413 +#else
5414 +#define OSL_UNCACHED(va) (va)
5415 +#endif /* mips */
5416 +
5417 +
5418 +#ifndef IL_BIGENDIAN
5419 +#define R_REG(osh, r) (\
5420 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
5421 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
5422 + readl((volatile uint32*)(r)) \
5423 +)
5424 +#define W_REG(osh, r, v) do { \
5425 + switch (sizeof(*(r))) { \
5426 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
5427 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
5428 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
5429 + } \
5430 +} while (0)
5431 +#else /* IL_BIGENDIAN */
5432 +#define R_REG(osh, r) ({ \
5433 + __typeof(*(r)) __osl_v; \
5434 + switch (sizeof(*(r))) { \
5435 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
5436 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
5437 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
5438 + } \
5439 + __osl_v; \
5440 +})
5441 +#define W_REG(osh, r, v) do { \
5442 + switch (sizeof(*(r))) { \
5443 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
5444 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
5445 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
5446 + } \
5447 +} while (0)
5448 +#endif /* IL_BIGENDIAN */
5449 +
5450 +/* dereference an address that may cause a bus exception */
5451 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
5452 +#include <asm/paccess.h>
5453 +
5454 +/* map/unmap physical to virtual I/O */
5455 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
5456 +#define REG_UNMAP(va) iounmap((void *)(va))
5457 +
5458 +/* shared (dma-able) memory access macros */
5459 +#define R_SM(r) *(r)
5460 +#define W_SM(r, v) (*(r) = (v))
5461 +#define BZERO_SM(r, len) memset((r), '\0', (len))
5462 +
5463 +#define MALLOC(osh, size) kmalloc((size), GFP_ATOMIC)
5464 +#define MFREE(osh, addr, size) kfree((addr))
5465 +#define MALLOCED(osh) (0)
5466 +
5467 +#define osl_delay OSL_DELAY
5468 +static inline void OSL_DELAY(uint usec)
5469 +{
5470 + uint d;
5471 +
5472 + while (usec > 0) {
5473 + d = MIN(usec, 1000);
5474 + udelay(d);
5475 + usec -= d;
5476 + }
5477 +}
5478 +
5479 +static inline void
5480 +bcm_mdelay(uint ms)
5481 +{
5482 + uint i;
5483 +
5484 + for (i = 0; i < ms; i++) {
5485 + OSL_DELAY(1000);
5486 + }
5487 +}
5488 +
5489 +
5490 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size)
5491 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size)
5492 +
5493 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
5494 + osl_pci_read_config((osh), (offset), (size))
5495 +
5496 +static inline uint32
5497 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
5498 +{
5499 + uint val;
5500 + uint retry = PCI_CFG_RETRY;
5501 +
5502 + do {
5503 + pci_read_config_dword(osh->pdev, offset, &val);
5504 + if (val != 0xffffffff)
5505 + break;
5506 + } while (retry--);
5507 +
5508 + return (val);
5509 +}
5510 +
5511 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
5512 + osl_pci_write_config((osh), (offset), (size), (val))
5513 +static inline void
5514 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
5515 +{
5516 + uint retry = PCI_CFG_RETRY;
5517 +
5518 + do {
5519 + pci_write_config_dword(osh->pdev, offset, val);
5520 + if (offset != PCI_BAR0_WIN)
5521 + break;
5522 + if (osl_pci_read_config(osh, offset, size) == val)
5523 + break;
5524 + } while (retry--);
5525 +}
5526 +
5527 +
5528 +/* return bus # for the pci device pointed by osh->pdev */
5529 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
5530 +static inline uint
5531 +osl_pci_bus(osl_t *osh)
5532 +{
5533 + return ((struct pci_dev *)osh->pdev)->bus->number;
5534 +}
5535 +
5536 +/* return slot # for the pci device pointed by osh->pdev */
5537 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
5538 +static inline uint
5539 +osl_pci_slot(osl_t *osh)
5540 +{
5541 + return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
5542 +}
5543 +
5544 +#endif
5545 diff -urN linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
5546 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
5547 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2006-04-27 20:31:41.000000000 +0200
5548 @@ -0,0 +1,495 @@
5549 +/*
5550 + * pcicfg.h: PCI configuration constants and structures.
5551 + *
5552 + * Copyright 2006, Broadcom Corporation
5553 + * All Rights Reserved.
5554 + *
5555 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5556 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5557 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5558 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5559 + *
5560 + * $Id: pcicfg.h,v 1.1.1.11 2006/04/08 06:13:40 honor Exp $
5561 + */
5562 +
5563 +#ifndef _h_pcicfg_
5564 +#define _h_pcicfg_
5565 +
5566 +/* The following inside ifndef's so we don't collide with NTDDK.H */
5567 +#ifndef PCI_MAX_BUS
5568 +#define PCI_MAX_BUS 0x100
5569 +#endif
5570 +#ifndef PCI_MAX_DEVICES
5571 +#define PCI_MAX_DEVICES 0x20
5572 +#endif
5573 +#ifndef PCI_MAX_FUNCTION
5574 +#define PCI_MAX_FUNCTION 0x8
5575 +#endif
5576 +
5577 +#ifndef PCI_INVALID_VENDORID
5578 +#define PCI_INVALID_VENDORID 0xffff
5579 +#endif
5580 +#ifndef PCI_INVALID_DEVICEID
5581 +#define PCI_INVALID_DEVICEID 0xffff
5582 +#endif
5583 +
5584 +
5585 +/* Convert between bus-slot-function-register and config addresses */
5586 +
5587 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
5588 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
5589 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
5590 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
5591 +
5592 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
5593 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
5594 +#define PCICFG_FUN_MASK 7 /* Function mask */
5595 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
5596 +
5597 +#define PCI_CONFIG_ADDR(b, s, f, o) \
5598 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
5599 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
5600 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
5601 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
5602 +
5603 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
5604 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
5605 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
5606 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
5607 +
5608 +/* PCIE Config space accessing MACROS */
5609 +
5610 +#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
5611 +#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
5612 +#define PCIECFG_FUN_SHIFT 16 /* Function shift */
5613 +#define PCIECFG_OFF_SHIFT 0 /* Register shift */
5614 +
5615 +#define PCIECFG_BUS_MASK 0xff /* Bus mask */
5616 +#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
5617 +#define PCIECFG_FUN_MASK 7 /* Function mask */
5618 +#define PCIECFG_OFF_MASK 0x3ff /* Register mask */
5619 +
5620 +#define PCIE_CONFIG_ADDR(b, s, f, o) \
5621 + ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
5622 + | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
5623 + | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
5624 + | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
5625 +
5626 +#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
5627 +#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
5628 +#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
5629 +#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
5630 +
5631 +/* The actual config space */
5632 +
5633 +#define PCI_BAR_MAX 6
5634 +
5635 +#define PCI_ROM_BAR 8
5636 +
5637 +#define PCR_RSVDA_MAX 2
5638 +
5639 +/* Bits in PCI bars' flags */
5640 +
5641 +#define PCIBAR_FLAGS 0xf
5642 +#define PCIBAR_IO 0x1
5643 +#define PCIBAR_MEM1M 0x2
5644 +#define PCIBAR_MEM64 0x4
5645 +#define PCIBAR_PREFETCH 0x8
5646 +#define PCIBAR_MEM32_MASK 0xFFFFFF80
5647 +
5648 +/* pci config status reg has a bit to indicate that capability ptr is present */
5649 +
5650 +#define PCI_CAPPTR_PRESENT 0x0010
5651 +
5652 +typedef struct _pci_config_regs {
5653 + unsigned short vendor;
5654 + unsigned short device;
5655 + unsigned short command;
5656 + unsigned short status;
5657 + unsigned char rev_id;
5658 + unsigned char prog_if;
5659 + unsigned char sub_class;
5660 + unsigned char base_class;
5661 + unsigned char cache_line_size;
5662 + unsigned char latency_timer;
5663 + unsigned char header_type;
5664 + unsigned char bist;
5665 + unsigned long base[PCI_BAR_MAX];
5666 + unsigned long cardbus_cis;
5667 + unsigned short subsys_vendor;
5668 + unsigned short subsys_id;
5669 + unsigned long baserom;
5670 + unsigned long rsvd_a[PCR_RSVDA_MAX];
5671 + unsigned char int_line;
5672 + unsigned char int_pin;
5673 + unsigned char min_gnt;
5674 + unsigned char max_lat;
5675 + unsigned char dev_dep[192];
5676 +} pci_config_regs;
5677 +
5678 +#define SZPCR (sizeof (pci_config_regs))
5679 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
5680 +
5681 +/* A structure for the config registers is nice, but in most
5682 + * systems the config space is not memory mapped, so we need
5683 + * filed offsetts. :-(
5684 + */
5685 +#define PCI_CFG_VID 0
5686 +#define PCI_CFG_DID 2
5687 +#define PCI_CFG_CMD 4
5688 +#define PCI_CFG_STAT 6
5689 +#define PCI_CFG_REV 8
5690 +#define PCI_CFG_PROGIF 9
5691 +#define PCI_CFG_SUBCL 0xa
5692 +#define PCI_CFG_BASECL 0xb
5693 +#define PCI_CFG_CLSZ 0xc
5694 +#define PCI_CFG_LATTIM 0xd
5695 +#define PCI_CFG_HDR 0xe
5696 +#define PCI_CFG_BIST 0xf
5697 +#define PCI_CFG_BAR0 0x10
5698 +#define PCI_CFG_BAR1 0x14
5699 +#define PCI_CFG_BAR2 0x18
5700 +#define PCI_CFG_BAR3 0x1c
5701 +#define PCI_CFG_BAR4 0x20
5702 +#define PCI_CFG_BAR5 0x24
5703 +#define PCI_CFG_CIS 0x28
5704 +#define PCI_CFG_SVID 0x2c
5705 +#define PCI_CFG_SSID 0x2e
5706 +#define PCI_CFG_ROMBAR 0x30
5707 +#define PCI_CFG_CAPPTR 0x34
5708 +#define PCI_CFG_INT 0x3c
5709 +#define PCI_CFG_PIN 0x3d
5710 +#define PCI_CFG_MINGNT 0x3e
5711 +#define PCI_CFG_MAXLAT 0x3f
5712 +
5713 +#ifdef __NetBSD__
5714 +#undef PCI_CLASS_DISPLAY
5715 +#undef PCI_CLASS_MEMORY
5716 +#undef PCI_CLASS_BRIDGE
5717 +#undef PCI_CLASS_INPUT
5718 +#undef PCI_CLASS_DOCK
5719 +#endif /* __NetBSD__ */
5720 +
5721 +/* Classes and subclasses */
5722 +
5723 +typedef enum {
5724 + PCI_CLASS_OLD = 0,
5725 + PCI_CLASS_DASDI,
5726 + PCI_CLASS_NET,
5727 + PCI_CLASS_DISPLAY,
5728 + PCI_CLASS_MMEDIA,
5729 + PCI_CLASS_MEMORY,
5730 + PCI_CLASS_BRIDGE,
5731 + PCI_CLASS_COMM,
5732 + PCI_CLASS_BASE,
5733 + PCI_CLASS_INPUT,
5734 + PCI_CLASS_DOCK,
5735 + PCI_CLASS_CPU,
5736 + PCI_CLASS_SERIAL,
5737 + PCI_CLASS_INTELLIGENT = 0xe,
5738 + PCI_CLASS_SATELLITE,
5739 + PCI_CLASS_CRYPT,
5740 + PCI_CLASS_DSP,
5741 + PCI_CLASS_XOR = 0xfe
5742 +} pci_classes;
5743 +
5744 +typedef enum {
5745 + PCI_DASDI_SCSI,
5746 + PCI_DASDI_IDE,
5747 + PCI_DASDI_FLOPPY,
5748 + PCI_DASDI_IPI,
5749 + PCI_DASDI_RAID,
5750 + PCI_DASDI_OTHER = 0x80
5751 +} pci_dasdi_subclasses;
5752 +
5753 +typedef enum {
5754 + PCI_NET_ETHER,
5755 + PCI_NET_TOKEN,
5756 + PCI_NET_FDDI,
5757 + PCI_NET_ATM,
5758 + PCI_NET_OTHER = 0x80
5759 +} pci_net_subclasses;
5760 +
5761 +typedef enum {
5762 + PCI_DISPLAY_VGA,
5763 + PCI_DISPLAY_XGA,
5764 + PCI_DISPLAY_3D,
5765 + PCI_DISPLAY_OTHER = 0x80
5766 +} pci_display_subclasses;
5767 +
5768 +typedef enum {
5769 + PCI_MMEDIA_VIDEO,
5770 + PCI_MMEDIA_AUDIO,
5771 + PCI_MMEDIA_PHONE,
5772 + PCI_MEDIA_OTHER = 0x80
5773 +} pci_mmedia_subclasses;
5774 +
5775 +typedef enum {
5776 + PCI_MEMORY_RAM,
5777 + PCI_MEMORY_FLASH,
5778 + PCI_MEMORY_OTHER = 0x80
5779 +} pci_memory_subclasses;
5780 +
5781 +typedef enum {
5782 + PCI_BRIDGE_HOST,
5783 + PCI_BRIDGE_ISA,
5784 + PCI_BRIDGE_EISA,
5785 + PCI_BRIDGE_MC,
5786 + PCI_BRIDGE_PCI,
5787 + PCI_BRIDGE_PCMCIA,
5788 + PCI_BRIDGE_NUBUS,
5789 + PCI_BRIDGE_CARDBUS,
5790 + PCI_BRIDGE_RACEWAY,
5791 + PCI_BRIDGE_OTHER = 0x80
5792 +} pci_bridge_subclasses;
5793 +
5794 +typedef enum {
5795 + PCI_COMM_UART,
5796 + PCI_COMM_PARALLEL,
5797 + PCI_COMM_MULTIUART,
5798 + PCI_COMM_MODEM,
5799 + PCI_COMM_OTHER = 0x80
5800 +} pci_comm_subclasses;
5801 +
5802 +typedef enum {
5803 + PCI_BASE_PIC,
5804 + PCI_BASE_DMA,
5805 + PCI_BASE_TIMER,
5806 + PCI_BASE_RTC,
5807 + PCI_BASE_PCI_HOTPLUG,
5808 + PCI_BASE_OTHER = 0x80
5809 +} pci_base_subclasses;
5810 +
5811 +typedef enum {
5812 + PCI_INPUT_KBD,
5813 + PCI_INPUT_PEN,
5814 + PCI_INPUT_MOUSE,
5815 + PCI_INPUT_SCANNER,
5816 + PCI_INPUT_GAMEPORT,
5817 + PCI_INPUT_OTHER = 0x80
5818 +} pci_input_subclasses;
5819 +
5820 +typedef enum {
5821 + PCI_DOCK_GENERIC,
5822 + PCI_DOCK_OTHER = 0x80
5823 +} pci_dock_subclasses;
5824 +
5825 +typedef enum {
5826 + PCI_CPU_386,
5827 + PCI_CPU_486,
5828 + PCI_CPU_PENTIUM,
5829 + PCI_CPU_ALPHA = 0x10,
5830 + PCI_CPU_POWERPC = 0x20,
5831 + PCI_CPU_MIPS = 0x30,
5832 + PCI_CPU_COPROC = 0x40,
5833 + PCI_CPU_OTHER = 0x80
5834 +} pci_cpu_subclasses;
5835 +
5836 +typedef enum {
5837 + PCI_SERIAL_IEEE1394,
5838 + PCI_SERIAL_ACCESS,
5839 + PCI_SERIAL_SSA,
5840 + PCI_SERIAL_USB,
5841 + PCI_SERIAL_FIBER,
5842 + PCI_SERIAL_SMBUS,
5843 + PCI_SERIAL_OTHER = 0x80
5844 +} pci_serial_subclasses;
5845 +
5846 +typedef enum {
5847 + PCI_INTELLIGENT_I2O
5848 +} pci_intelligent_subclasses;
5849 +
5850 +typedef enum {
5851 + PCI_SATELLITE_TV,
5852 + PCI_SATELLITE_AUDIO,
5853 + PCI_SATELLITE_VOICE,
5854 + PCI_SATELLITE_DATA,
5855 + PCI_SATELLITE_OTHER = 0x80
5856 +} pci_satellite_subclasses;
5857 +
5858 +typedef enum {
5859 + PCI_CRYPT_NETWORK,
5860 + PCI_CRYPT_ENTERTAINMENT,
5861 + PCI_CRYPT_OTHER = 0x80
5862 +} pci_crypt_subclasses;
5863 +
5864 +typedef enum {
5865 + PCI_DSP_DPIO,
5866 + PCI_DSP_OTHER = 0x80
5867 +} pci_dsp_subclasses;
5868 +
5869 +typedef enum {
5870 + PCI_XOR_QDMA,
5871 + PCI_XOR_OTHER = 0x80
5872 +} pci_xor_subclasses;
5873 +
5874 +/* Header types */
5875 +typedef enum {
5876 + PCI_HEADER_NORMAL,
5877 + PCI_HEADER_BRIDGE,
5878 + PCI_HEADER_CARDBUS
5879 +} pci_header_types;
5880 +
5881 +
5882 +/* Overlay for a PCI-to-PCI bridge */
5883 +
5884 +#define PPB_RSVDA_MAX 2
5885 +#define PPB_RSVDD_MAX 8
5886 +
5887 +typedef struct _ppb_config_regs {
5888 + unsigned short vendor;
5889 + unsigned short device;
5890 + unsigned short command;
5891 + unsigned short status;
5892 + unsigned char rev_id;
5893 + unsigned char prog_if;
5894 + unsigned char sub_class;
5895 + unsigned char base_class;
5896 + unsigned char cache_line_size;
5897 + unsigned char latency_timer;
5898 + unsigned char header_type;
5899 + unsigned char bist;
5900 + unsigned long rsvd_a[PPB_RSVDA_MAX];
5901 + unsigned char prim_bus;
5902 + unsigned char sec_bus;
5903 + unsigned char sub_bus;
5904 + unsigned char sec_lat;
5905 + unsigned char io_base;
5906 + unsigned char io_lim;
5907 + unsigned short sec_status;
5908 + unsigned short mem_base;
5909 + unsigned short mem_lim;
5910 + unsigned short pf_mem_base;
5911 + unsigned short pf_mem_lim;
5912 + unsigned long pf_mem_base_hi;
5913 + unsigned long pf_mem_lim_hi;
5914 + unsigned short io_base_hi;
5915 + unsigned short io_lim_hi;
5916 + unsigned short subsys_vendor;
5917 + unsigned short subsys_id;
5918 + unsigned long rsvd_b;
5919 + unsigned char rsvd_c;
5920 + unsigned char int_pin;
5921 + unsigned short bridge_ctrl;
5922 + unsigned char chip_ctrl;
5923 + unsigned char diag_ctrl;
5924 + unsigned short arb_ctrl;
5925 + unsigned long rsvd_d[PPB_RSVDD_MAX];
5926 + unsigned char dev_dep[192];
5927 +} ppb_config_regs;
5928 +
5929 +
5930 +/* PCI CAPABILITY DEFINES */
5931 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
5932 +#define PCI_CAP_MSICAP_ID 0x05
5933 +#define PCI_CAP_PCIECAP_ID 0x10
5934 +
5935 +/* Data structure to define the Message Signalled Interrupt facility
5936 + * Valid for PCI and PCIE configurations
5937 + */
5938 +typedef struct _pciconfig_cap_msi {
5939 + unsigned char capID;
5940 + unsigned char nextptr;
5941 + unsigned short msgctrl;
5942 + unsigned int msgaddr;
5943 +} pciconfig_cap_msi;
5944 +
5945 +/* Data structure to define the Power managment facility
5946 + * Valid for PCI and PCIE configurations
5947 + */
5948 +typedef struct _pciconfig_cap_pwrmgmt {
5949 + unsigned char capID;
5950 + unsigned char nextptr;
5951 + unsigned short pme_cap;
5952 + unsigned short pme_sts_ctrl;
5953 + unsigned char pme_bridge_ext;
5954 + unsigned char data;
5955 +} pciconfig_cap_pwrmgmt;
5956 +
5957 +/* Data structure to define the PCIE capability */
5958 +typedef struct _pciconfig_cap_pcie {
5959 + unsigned char capID;
5960 + unsigned char nextptr;
5961 + unsigned short pcie_cap;
5962 + unsigned int dev_cap;
5963 + unsigned short dev_ctrl;
5964 + unsigned short dev_status;
5965 + unsigned int link_cap;
5966 + unsigned short link_ctrl;
5967 + unsigned short link_status;
5968 +} pciconfig_cap_pcie;
5969 +
5970 +/* PCIE Enhanced CAPABILITY DEFINES */
5971 +#define PCIE_EXTCFG_OFFSET 0x100
5972 +#define PCIE_ADVERRREP_CAPID 0x0001
5973 +#define PCIE_VC_CAPID 0x0002
5974 +#define PCIE_DEVSNUM_CAPID 0x0003
5975 +#define PCIE_PWRBUDGET_CAPID 0x0004
5976 +
5977 +/* Header to define the PCIE specific capabilities in the extended config space */
5978 +typedef struct _pcie_enhanced_caphdr {
5979 + unsigned short capID;
5980 + unsigned short cap_ver : 4;
5981 + unsigned short next_ptr : 12;
5982 +} pcie_enhanced_caphdr;
5983 +
5984 +
5985 +/* Everything below is BRCM HND proprietary */
5986 +
5987 +
5988 +/* Brcm PCI configuration registers */
5989 +#define cap_list rsvd_a[0]
5990 +#define bar0_window dev_dep[0x80 - 0x40]
5991 +#define bar1_window dev_dep[0x84 - 0x40]
5992 +#define sprom_control dev_dep[0x88 - 0x40]
5993 +
5994 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
5995 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
5996 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
5997 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
5998 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
5999 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
6000 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
6001 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
6002 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address */
6003 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
6004 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
6005 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
6006 +
6007 +#define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */
6008 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
6009 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
6010 +#define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the
6011 + * 8KB window, so their address is the "regular"
6012 + * address plus 4K
6013 + */
6014 +#define PCI_BAR0_WINSZ 8192 /* bar0 window size */
6015 +
6016 +/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
6017 +#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */
6018 +#define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */
6019 +#define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */
6020 +
6021 +/* PCI_INT_STATUS */
6022 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
6023 +
6024 +/* PCI_INT_MASK */
6025 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
6026 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
6027 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
6028 +
6029 +/* PCI_SPROM_CONTROL */
6030 +#define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */
6031 +#define SPROM_LOCKED 0x08 /* SPROM Locked */
6032 +#define SPROM_BLANK 0x04 /* indicating a blank SPROM */
6033 +#define SPROM_WRITEEN 0x10 /* SPROM write enable */
6034 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
6035 +#define SPROM_OTPIN_USE 0x80 /* device OTP In use */
6036 +
6037 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
6038 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
6039 +
6040 +/* PCI_CFG_CMD_STAT */
6041 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
6042 +
6043 +#endif /* _h_pcicfg_ */
6044 diff -urN linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
6045 --- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
6046 +++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2006-04-27 22:11:01.000000000 +0200
6047 @@ -0,0 +1,516 @@
6048 +/*
6049 + * SiliconBackplane Chipcommon core hardware definitions.
6050 + *
6051 + * The chipcommon core provides chip identification, SB control,
6052 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
6053 + * gpio interface, extbus, and support for serial and parallel flashes.
6054 + *
6055 + * $Id: sbchipc.h,v 1.1.1.14 2006/04/15 01:29:08 michael Exp $
6056 + * Copyright 2006, Broadcom Corporation
6057 + * All Rights Reserved.
6058 + *
6059 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6060 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6061 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6062 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6063 + *
6064 + */
6065 +
6066 +#ifndef _SBCHIPC_H
6067 +#define _SBCHIPC_H
6068 +
6069 +
6070 +#ifndef _LANGUAGE_ASSEMBLY
6071 +
6072 +/* cpp contortions to concatenate w/arg prescan */
6073 +#ifndef PAD
6074 +#define _PADLINE(line) pad ## line
6075 +#define _XSTR(line) _PADLINE(line)
6076 +#define PAD _XSTR(__LINE__)
6077 +#endif /* PAD */
6078 +
6079 +typedef volatile struct {
6080 + uint32 chipid; /* 0x0 */
6081 + uint32 capabilities;
6082 + uint32 corecontrol; /* corerev >= 1 */
6083 + uint32 bist;
6084 +
6085 + /* OTP */
6086 + uint32 otpstatus; /* 0x10, corerev >= 10 */
6087 + uint32 otpcontrol;
6088 + uint32 otpprog;
6089 + uint32 PAD;
6090 +
6091 + /* Interrupt control */
6092 + uint32 intstatus; /* 0x20 */
6093 + uint32 intmask;
6094 + uint32 chipcontrol; /* 0x28, rev >= 11 */
6095 + uint32 chipstatus; /* 0x2c, rev >= 11 */
6096 +
6097 + /* Jtag Master */
6098 + uint32 jtagcmd; /* 0x30, rev >= 10 */
6099 + uint32 jtagir;
6100 + uint32 jtagdr;
6101 + uint32 jtagctrl;
6102 +
6103 + /* serial flash interface registers */
6104 + uint32 flashcontrol; /* 0x40 */
6105 + uint32 flashaddress;
6106 + uint32 flashdata;
6107 + uint32 PAD[1];
6108 +
6109 + /* Silicon backplane configuration broadcast control */
6110 + uint32 broadcastaddress; /* 0x50 */
6111 + uint32 broadcastdata;
6112 + uint32 PAD[2];
6113 +
6114 + /* gpio - cleared only by power-on-reset */
6115 + uint32 gpioin; /* 0x60 */
6116 + uint32 gpioout;
6117 + uint32 gpioouten;
6118 + uint32 gpiocontrol;
6119 + uint32 gpiointpolarity;
6120 + uint32 gpiointmask;
6121 + uint32 PAD[2];
6122 +
6123 + /* Watchdog timer */
6124 + uint32 watchdog; /* 0x80 */
6125 + uint32 PAD[1];
6126 +
6127 + /* GPIO based LED powersave registers corerev >= 16 */
6128 + uint32 gpiotimerval; /* 0x88 */
6129 + uint32 gpiotimeroutmask;
6130 +
6131 + /* clock control */
6132 + uint32 clockcontrol_n; /* 0x90 */
6133 + uint32 clockcontrol_sb; /* aka m0 */
6134 + uint32 clockcontrol_pci; /* aka m1 */
6135 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
6136 + uint32 clockcontrol_m3; /* cpu */
6137 + uint32 clkdiv; /* corerev >= 3 */
6138 + uint32 PAD[2];
6139 +
6140 + /* pll delay registers (corerev >= 4) */
6141 + uint32 pll_on_delay; /* 0xb0 */
6142 + uint32 fref_sel_delay;
6143 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
6144 + uint32 PAD[1];
6145 +
6146 + /* Instaclock registers (corerev >= 10) */
6147 + uint32 system_clk_ctl; /* 0xc0 */
6148 + uint32 clkstatestretch;
6149 + uint32 PAD[14];
6150 +
6151 + /* ExtBus control registers (corerev >= 3) */
6152 + uint32 pcmcia_config; /* 0x100 */
6153 + uint32 pcmcia_memwait;
6154 + uint32 pcmcia_attrwait;
6155 + uint32 pcmcia_iowait;
6156 + uint32 ide_config;
6157 + uint32 ide_memwait;
6158 + uint32 ide_attrwait;
6159 + uint32 ide_iowait;
6160 + uint32 prog_config;
6161 + uint32 prog_waitcount;
6162 + uint32 flash_config;
6163 + uint32 flash_waitcount;
6164 + uint32 PAD[44];
6165 +
6166 + /* Clock control and hardware workarounds */
6167 + uint32 clk_ctl_st;
6168 + uint32 hw_war;
6169 + uint32 PAD[70];
6170 +
6171 + /* uarts */
6172 + uint8 uart0data; /* 0x300 */
6173 + uint8 uart0imr;
6174 + uint8 uart0fcr;
6175 + uint8 uart0lcr;
6176 + uint8 uart0mcr;
6177 + uint8 uart0lsr;
6178 + uint8 uart0msr;
6179 + uint8 uart0scratch;
6180 + uint8 PAD[248]; /* corerev >= 1 */
6181 +
6182 + uint8 uart1data; /* 0x400 */
6183 + uint8 uart1imr;
6184 + uint8 uart1fcr;
6185 + uint8 uart1lcr;
6186 + uint8 uart1mcr;
6187 + uint8 uart1lsr;
6188 + uint8 uart1msr;
6189 + uint8 uart1scratch;
6190 +} chipcregs_t;
6191 +
6192 +#endif /* _LANGUAGE_ASSEMBLY */
6193 +
6194 +#define CC_CHIPID 0
6195 +#define CC_CAPABILITIES 4
6196 +#define CC_JTAGCMD 0x30
6197 +#define CC_JTAGIR 0x34
6198 +#define CC_JTAGDR 0x38
6199 +#define CC_JTAGCTRL 0x3c
6200 +#define CC_WATCHDOG 0x80
6201 +#define CC_CLKC_N 0x90
6202 +#define CC_CLKC_M0 0x94
6203 +#define CC_CLKC_M1 0x98
6204 +#define CC_CLKC_M2 0x9c
6205 +#define CC_CLKC_M3 0xa0
6206 +#define CC_CLKDIV 0xa4
6207 +#define CC_SYS_CLK_CTL 0xc0
6208 +#define CC_OTP 0x800
6209 +
6210 +/* chipid */
6211 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
6212 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
6213 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
6214 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
6215 +#define CID_PKG_SHIFT 20 /* Package Option shift */
6216 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
6217 +#define CID_CC_SHIFT 24
6218 +
6219 +/* capabilities */
6220 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
6221 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
6222 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
6223 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
6224 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
6225 +#define CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
6226 +#define CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
6227 +#define CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
6228 +#define CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
6229 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
6230 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
6231 +#define CAP_PWR_CTL 0x00040000 /* Power control */
6232 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
6233 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
6234 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
6235 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
6236 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
6237 +#define CAP_BKPLN64 0x08000000 /* 64-bit backplane */
6238 +
6239 +/* PLL type */
6240 +#define PLL_NONE 0x00000000
6241 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
6242 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
6243 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
6244 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
6245 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
6246 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
6247 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
6248 +
6249 +/* corecontrol */
6250 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
6251 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
6252 +
6253 +/* chipcontrol */
6254 +#define CHIPCTRL_4321A0_DEFAULT 0x3a4
6255 +#define CHIPCTRL_4321A1_DEFAULT 0x0a4
6256 +
6257 +/* Fields in the otpstatus register */
6258 +#define OTPS_PROGFAIL 0x80000000
6259 +#define OTPS_PROTECT 0x00000007
6260 +#define OTPS_HW_PROTECT 0x00000001
6261 +#define OTPS_SW_PROTECT 0x00000002
6262 +#define OTPS_CID_PROTECT 0x00000004
6263 +
6264 +/* Fields in the otpcontrol register */
6265 +#define OTPC_RECWAIT 0xff000000
6266 +#define OTPC_PROGWAIT 0x00ffff00
6267 +#define OTPC_PRW_SHIFT 8
6268 +#define OTPC_MAXFAIL 0x00000038
6269 +#define OTPC_VSEL 0x00000006
6270 +#define OTPC_SELVL 0x00000001
6271 +
6272 +/* Fields in otpprog */
6273 +#define OTPP_COL_MASK 0x000000ff
6274 +#define OTPP_ROW_MASK 0x0000ff00
6275 +#define OTPP_ROW_SHIFT 8
6276 +#define OTPP_READERR 0x10000000
6277 +#define OTPP_VALUE 0x20000000
6278 +#define OTPP_VALUE_SHIFT 29
6279 +#define OTPP_READ 0x40000000
6280 +#define OTPP_START 0x80000000
6281 +#define OTPP_BUSY 0x80000000
6282 +
6283 +/* jtagcmd */
6284 +#define JCMD_START 0x80000000
6285 +#define JCMD_BUSY 0x80000000
6286 +#define JCMD_PAUSE 0x40000000
6287 +#define JCMD0_ACC_MASK 0x0000f000
6288 +#define JCMD0_ACC_IRDR 0x00000000
6289 +#define JCMD0_ACC_DR 0x00001000
6290 +#define JCMD0_ACC_IR 0x00002000
6291 +#define JCMD0_ACC_RESET 0x00003000
6292 +#define JCMD0_ACC_IRPDR 0x00004000
6293 +#define JCMD0_ACC_PDR 0x00005000
6294 +#define JCMD0_IRW_MASK 0x00000f00
6295 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
6296 +#define JCMD_ACC_IRDR 0x00000000
6297 +#define JCMD_ACC_DR 0x00010000
6298 +#define JCMD_ACC_IR 0x00020000
6299 +#define JCMD_ACC_RESET 0x00030000
6300 +#define JCMD_ACC_IRPDR 0x00040000
6301 +#define JCMD_ACC_PDR 0x00050000
6302 +#define JCMD_IRW_MASK 0x00001f00
6303 +#define JCMD_IRW_SHIFT 8
6304 +#define JCMD_DRW_MASK 0x0000003f
6305 +
6306 +/* jtagctrl */
6307 +#define JCTRL_FORCE_CLK 4 /* Force clock */
6308 +#define JCTRL_EXT_EN 2 /* Enable external targets */
6309 +#define JCTRL_EN 1 /* Enable Jtag master */
6310 +
6311 +/* Fields in clkdiv */
6312 +#define CLKD_SFLASH 0x0f000000
6313 +#define CLKD_SFLASH_SHIFT 24
6314 +#define CLKD_OTP 0x000f0000
6315 +#define CLKD_OTP_SHIFT 16
6316 +#define CLKD_JTAG 0x00000f00
6317 +#define CLKD_JTAG_SHIFT 8
6318 +#define CLKD_UART 0x000000ff
6319 +
6320 +/* intstatus/intmask */
6321 +#define CI_GPIO 0x00000001 /* gpio intr */
6322 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
6323 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
6324 +
6325 +/* slow_clk_ctl */
6326 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
6327 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
6328 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
6329 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
6330 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
6331 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled,
6332 + * 0: LPO is enabled
6333 + */
6334 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock,
6335 + * 0: power logic control
6336 + */
6337 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors
6338 + * PLL clock disable requests from core
6339 + */
6340 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't
6341 + * disable crystal when appropriate
6342 + */
6343 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
6344 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
6345 +#define SCC_CD_SHIFT 16
6346 +
6347 +/* system_clk_ctl */
6348 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
6349 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
6350 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
6351 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
6352 +#define SYCC_HR 0x00000010 /* Force HT */
6353 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
6354 +#define SYCC_CD_SHIFT 16
6355 +
6356 +/* gpiotimerval */
6357 +#define GPIO_ONTIME_SHIFT 16
6358 +
6359 +/* clockcontrol_n */
6360 +#define CN_N1_MASK 0x3f /* n1 control */
6361 +#define CN_N2_MASK 0x3f00 /* n2 control */
6362 +#define CN_N2_SHIFT 8
6363 +#define CN_PLLC_MASK 0xf0000 /* pll control */
6364 +#define CN_PLLC_SHIFT 16
6365 +
6366 +/* clockcontrol_sb/pci/uart */
6367 +#define CC_M1_MASK 0x3f /* m1 control */
6368 +#define CC_M2_MASK 0x3f00 /* m2 control */
6369 +#define CC_M2_SHIFT 8
6370 +#define CC_M3_MASK 0x3f0000 /* m3 control */
6371 +#define CC_M3_SHIFT 16
6372 +#define CC_MC_MASK 0x1f000000 /* mux control */
6373 +#define CC_MC_SHIFT 24
6374 +
6375 +/* N3M Clock control magic field values */
6376 +#define CC_F6_2 0x02 /* A factor of 2 in */
6377 +#define CC_F6_3 0x03 /* 6-bit fields like */
6378 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
6379 +#define CC_F6_5 0x09
6380 +#define CC_F6_6 0x11
6381 +#define CC_F6_7 0x21
6382 +
6383 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
6384 +
6385 +#define CC_MC_BYPASS 0x08
6386 +#define CC_MC_M1 0x04
6387 +#define CC_MC_M1M2 0x02
6388 +#define CC_MC_M1M2M3 0x01
6389 +#define CC_MC_M1M3 0x11
6390 +
6391 +/* Type 2 Clock control magic field values */
6392 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
6393 +#define CC_T2M2_BIAS 3 /* m2 bias */
6394 +
6395 +#define CC_T2MC_M1BYP 1
6396 +#define CC_T2MC_M2BYP 2
6397 +#define CC_T2MC_M3BYP 4
6398 +
6399 +/* Type 6 Clock control magic field values */
6400 +#define CC_T6_MMASK 1 /* bits of interest in m */
6401 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
6402 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
6403 +#define SB2MIPS_T6(sb) (2 * (sb))
6404 +
6405 +/* Common clock base */
6406 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
6407 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
6408 +
6409 +/* Clock control values for 200Mhz in 5350 */
6410 +#define CLKC_5350_N 0x0311
6411 +#define CLKC_5350_M 0x04020009
6412 +
6413 +/* Flash types in the chipcommon capabilities register */
6414 +#define FLASH_NONE 0x000 /* No flash */
6415 +#define SFLASH_ST 0x100 /* ST serial flash */
6416 +#define SFLASH_AT 0x200 /* Atmel serial flash */
6417 +#define PFLASH 0x700 /* Parallel flash */
6418 +
6419 +/* Bits in the ExtBus config registers */
6420 +#define CC_CFG_EN 0x0001 /* Enable */
6421 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
6422 +#define CC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */
6423 +#define CC_CFG_EM_SYNC 0x0002 /* Synchronous */
6424 +#define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */
6425 +#define CC_CFG_EM_IDE 0x0006 /* IDE */
6426 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
6427 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
6428 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
6429 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
6430 +
6431 +/* ExtBus address space */
6432 +#define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */
6433 +#define CC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */
6434 +#define CC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */
6435 +#define CC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */
6436 +#define CC_EB_IDE 0x1a800000 /* IDE memory base */
6437 +#define CC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */
6438 +#define CC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */
6439 +#define CC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */
6440 +#define CC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */
6441 +
6442 +
6443 +/* Start/busy bit in flashcontrol */
6444 +#define SFLASH_OPCODE 0x000000ff
6445 +#define SFLASH_ACTION 0x00000700
6446 +#define SFLASH_START 0x80000000
6447 +#define SFLASH_BUSY SFLASH_START
6448 +
6449 +/* flashcontrol action codes */
6450 +#define SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */
6451 +#define SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */
6452 +#define SFLASH_ACT_OP3A 0x0200 /* opcode + 3 address bytes */
6453 +#define SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addres & 1 data bytes */
6454 +#define SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addres & 4 data bytes */
6455 +#define SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addres, 4 don't care & 4 data bytes */
6456 +#define SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addres, 1 don't care & 4 data bytes */
6457 +
6458 +/* flashcontrol action+opcodes for ST flashes */
6459 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
6460 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
6461 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
6462 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
6463 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
6464 +#define SFLASH_ST_PP 0x0302 /* Page Program */
6465 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
6466 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
6467 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
6468 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
6469 +
6470 +/* Status register bits for ST flashes */
6471 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
6472 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
6473 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
6474 +#define SFLASH_ST_BP_SHIFT 2
6475 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
6476 +
6477 +/* flashcontrol action+opcodes for Atmel flashes */
6478 +#define SFLASH_AT_READ 0x07e8
6479 +#define SFLASH_AT_PAGE_READ 0x07d2
6480 +#define SFLASH_AT_BUF1_READ
6481 +#define SFLASH_AT_BUF2_READ
6482 +#define SFLASH_AT_STATUS 0x01d7
6483 +#define SFLASH_AT_BUF1_WRITE 0x0384
6484 +#define SFLASH_AT_BUF2_WRITE 0x0387
6485 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
6486 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
6487 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
6488 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
6489 +#define SFLASH_AT_PAGE_ERASE 0x0281
6490 +#define SFLASH_AT_BLOCK_ERASE 0x0250
6491 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
6492 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
6493 +#define SFLASH_AT_BUF1_LOAD 0x0253
6494 +#define SFLASH_AT_BUF2_LOAD 0x0255
6495 +#define SFLASH_AT_BUF1_COMPARE 0x0260
6496 +#define SFLASH_AT_BUF2_COMPARE 0x0261
6497 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
6498 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
6499 +
6500 +/* Status register bits for Atmel flashes */
6501 +#define SFLASH_AT_READY 0x80
6502 +#define SFLASH_AT_MISMATCH 0x40
6503 +#define SFLASH_AT_ID_MASK 0x38
6504 +#define SFLASH_AT_ID_SHIFT 3
6505 +
6506 +/* OTP regions */
6507 +#define OTP_HW_REGION OTPS_HW_PROTECT
6508 +#define OTP_SW_REGION OTPS_SW_PROTECT
6509 +#define OTP_CID_REGION OTPS_CID_PROTECT
6510 +
6511 +/* OTP regions (Byte offsets from otp size) */
6512 +#define OTP_SWLIM_OFF (-8)
6513 +#define OTP_CIDBASE_OFF 0
6514 +#define OTP_CIDLIM_OFF 8
6515 +
6516 +/* Predefined OTP words (Word offset from otp size) */
6517 +#define OTP_BOUNDARY_OFF (-4)
6518 +#define OTP_HWSIGN_OFF (-3)
6519 +#define OTP_SWSIGN_OFF (-2)
6520 +#define OTP_CIDSIGN_OFF (-1)
6521 +
6522 +#define OTP_CID_OFF 0
6523 +#define OTP_PKG_OFF 1
6524 +#define OTP_FID_OFF 2
6525 +#define OTP_RSV_OFF 3
6526 +#define OTP_LIM_OFF 4
6527 +
6528 +#define OTP_SIGNATURE 0x578a
6529 +#define OTP_MAGIC 0x4e56
6530 +
6531 +/*
6532 + * These are the UART port assignments, expressed as offsets from the base
6533 + * register. These assignments should hold for any serial port based on
6534 + * a 8250, 16450, or 16550(A).
6535 + */
6536 +
6537 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
6538 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
6539 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
6540 +#define UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */
6541 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
6542 +#define UART_IIR 2 /* In: Interrupt Identity Register */
6543 +#define UART_FCR 2 /* Out: FIFO Control Register */
6544 +#define UART_LCR 3 /* Out: Line Control Register */
6545 +#define UART_MCR 4 /* Out: Modem Control Register */
6546 +#define UART_LSR 5 /* In: Line Status Register */
6547 +#define UART_MSR 6 /* In: Modem Status Register */
6548 +#define UART_SCR 7 /* I/O: Scratch Register */
6549 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
6550 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
6551 +#define UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */
6552 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
6553 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
6554 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
6555 +#define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */
6556 +
6557 +/* Interrupt Enable Register (IER) bits */
6558 +#define UART_IER_EDSSI 8 /* enable modem status interrupt */
6559 +#define UART_IER_ELSI 4 /* enable receiver line status interrupt */
6560 +#define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */
6561 +#define UART_IER_ERBFI 1 /* enable data available interrupt */
6562 +
6563 +#endif /* _SBCHIPC_H */
6564 diff -urN linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
6565 --- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
6566 +++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2006-04-27 22:14:11.000000000 +0200
6567 @@ -0,0 +1,369 @@
6568 +/*
6569 + * Broadcom SiliconBackplane hardware register definitions.
6570 + *
6571 + * Copyright 2006, Broadcom Corporation
6572 + * All Rights Reserved.
6573 + *
6574 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6575 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6576 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6577 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6578 + *
6579 + * $Id: sbconfig.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
6580 + */
6581 +
6582 +#ifndef _SBCONFIG_H
6583 +#define _SBCONFIG_H
6584 +
6585 +/* cpp contortions to concatenate w/arg prescan */
6586 +#ifndef PAD
6587 +#define _PADLINE(line) pad ## line
6588 +#define _XSTR(line) _PADLINE(line)
6589 +#define PAD _XSTR(__LINE__)
6590 +#endif
6591 +
6592 +/*
6593 + * SiliconBackplane Address Map.
6594 + * All regions may not exist on all chips.
6595 + */
6596 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
6597 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
6598 +#define SB_PCI_MEM_SZ (64 * 1024 * 1024)
6599 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
6600 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
6601 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
6602 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
6603 +
6604 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
6605 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
6606 +
6607 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
6608 +#define SB_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
6609 +#define SB_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
6610 +
6611 +#define SB_ROM 0x20000000 /* ARM ROM */
6612 +#define SB_SRAM2 0x80000000 /* ARM SRAM Region 2 */
6613 +#define SB_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */
6614 +#define SB_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */
6615 +
6616 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
6617 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
6618 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2
6619 + * (2 ZettaBytes), low 32 bits
6620 + */
6621 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2
6622 + * (2 ZettaBytes), high 32 bits
6623 + */
6624 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
6625 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
6626 +
6627 +
6628 +/* enumeration space related defs */
6629 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
6630 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
6631 +#define SB_MAXFUNCS 4 /* max. # functions per core */
6632 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
6633 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
6634 +
6635 +/* mips address */
6636 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
6637 +
6638 +/*
6639 + * Sonics Configuration Space Registers.
6640 + */
6641 +#define SBIPSFLAG 0x08
6642 +#define SBTPSFLAG 0x18
6643 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
6644 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
6645 +#define SBADMATCH3 0x60
6646 +#define SBADMATCH2 0x68
6647 +#define SBADMATCH1 0x70
6648 +#define SBIMSTATE 0x90
6649 +#define SBINTVEC 0x94
6650 +#define SBTMSTATELOW 0x98
6651 +#define SBTMSTATEHIGH 0x9c
6652 +#define SBBWA0 0xa0
6653 +#define SBIMCONFIGLOW 0xa8
6654 +#define SBIMCONFIGHIGH 0xac
6655 +#define SBADMATCH0 0xb0
6656 +#define SBTMCONFIGLOW 0xb8
6657 +#define SBTMCONFIGHIGH 0xbc
6658 +#define SBBCONFIG 0xc0
6659 +#define SBBSTATE 0xc8
6660 +#define SBACTCNFG 0xd8
6661 +#define SBFLAGST 0xe8
6662 +#define SBIDLOW 0xf8
6663 +#define SBIDHIGH 0xfc
6664 +
6665 +/* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have
6666 + * a few registers *below* that line. I think it would be very confusing to try
6667 + * and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here,
6668 + */
6669 +
6670 +#define SBIMERRLOGA 0xea8
6671 +#define SBIMERRLOG 0xeb0
6672 +#define SBTMPORTCONNID0 0xed8
6673 +#define SBTMPORTLOCK0 0xef8
6674 +
6675 +#ifndef _LANGUAGE_ASSEMBLY
6676 +
6677 +typedef volatile struct _sbconfig {
6678 + uint32 PAD[2];
6679 + uint32 sbipsflag; /* initiator port ocp slave flag */
6680 + uint32 PAD[3];
6681 + uint32 sbtpsflag; /* target port ocp slave flag */
6682 + uint32 PAD[11];
6683 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
6684 + uint32 PAD;
6685 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
6686 + uint32 PAD[3];
6687 + uint32 sbadmatch3; /* address match3 */
6688 + uint32 PAD;
6689 + uint32 sbadmatch2; /* address match2 */
6690 + uint32 PAD;
6691 + uint32 sbadmatch1; /* address match1 */
6692 + uint32 PAD[7];
6693 + uint32 sbimstate; /* initiator agent state */
6694 + uint32 sbintvec; /* interrupt mask */
6695 + uint32 sbtmstatelow; /* target state */
6696 + uint32 sbtmstatehigh; /* target state */
6697 + uint32 sbbwa0; /* bandwidth allocation table0 */
6698 + uint32 PAD;
6699 + uint32 sbimconfiglow; /* initiator configuration */
6700 + uint32 sbimconfighigh; /* initiator configuration */
6701 + uint32 sbadmatch0; /* address match0 */
6702 + uint32 PAD;
6703 + uint32 sbtmconfiglow; /* target configuration */
6704 + uint32 sbtmconfighigh; /* target configuration */
6705 + uint32 sbbconfig; /* broadcast configuration */
6706 + uint32 PAD;
6707 + uint32 sbbstate; /* broadcast state */
6708 + uint32 PAD[3];
6709 + uint32 sbactcnfg; /* activate configuration */
6710 + uint32 PAD[3];
6711 + uint32 sbflagst; /* current sbflags */
6712 + uint32 PAD[3];
6713 + uint32 sbidlow; /* identification */
6714 + uint32 sbidhigh; /* identification */
6715 +} sbconfig_t;
6716 +
6717 +#endif /* _LANGUAGE_ASSEMBLY */
6718 +
6719 +/* sbipsflag */
6720 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
6721 +#define SBIPS_INT1_SHIFT 0
6722 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
6723 +#define SBIPS_INT2_SHIFT 8
6724 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
6725 +#define SBIPS_INT3_SHIFT 16
6726 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
6727 +#define SBIPS_INT4_SHIFT 24
6728 +
6729 +/* sbtpsflag */
6730 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
6731 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
6732 +
6733 +/* sbtmerrlog */
6734 +#define SBTMEL_CM 0x00000007 /* command */
6735 +#define SBTMEL_CI 0x0000ff00 /* connection id */
6736 +#define SBTMEL_EC 0x0f000000 /* error code */
6737 +#define SBTMEL_ME 0x80000000 /* multiple error */
6738 +
6739 +/* sbimstate */
6740 +#define SBIM_PC 0xf /* pipecount */
6741 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
6742 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
6743 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
6744 +#define SBIM_AP_TK 0x20 /* use token only */
6745 +#define SBIM_AP_RSV 0x30 /* reserved */
6746 +#define SBIM_IBE 0x20000 /* inbanderror */
6747 +#define SBIM_TO 0x40000 /* timeout */
6748 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
6749 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
6750 +
6751 +/* sbtmstatelow */
6752 +#define SBTML_RESET 0x1 /* reset */
6753 +#define SBTML_REJ_MASK 0x6 /* reject */
6754 +#define SBTML_REJ_SHIFT 1
6755 +#define SBTML_CLK 0x10000 /* clock enable */
6756 +#define SBTML_FGC 0x20000 /* force gated clocks on */
6757 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
6758 +#define SBTML_PE 0x40000000 /* pme enable */
6759 +#define SBTML_BE 0x80000000 /* bist enable */
6760 +
6761 +/* sbtmstatehigh */
6762 +#define SBTMH_SERR 0x1 /* serror */
6763 +#define SBTMH_INT 0x2 /* interrupt */
6764 +#define SBTMH_BUSY 0x4 /* busy */
6765 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
6766 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
6767 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
6768 +#define SBTMH_GCR 0x20000000 /* gated clock request */
6769 +#define SBTMH_BISTF 0x40000000 /* bist failed */
6770 +#define SBTMH_BISTD 0x80000000 /* bist done */
6771 +
6772 +
6773 +/* sbbwa0 */
6774 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
6775 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
6776 +#define SBBWA_TAB1_SHIFT 16
6777 +
6778 +/* sbimconfiglow */
6779 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
6780 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
6781 +#define SBIMCL_RTO_SHIFT 4
6782 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
6783 +#define SBIMCL_CID_SHIFT 16
6784 +
6785 +/* sbimconfighigh */
6786 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
6787 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
6788 +#define SBIMCH_TEM_SHIFT 4
6789 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
6790 +#define SBIMCH_BEM_SHIFT 6
6791 +
6792 +/* sbadmatch0 */
6793 +#define SBAM_TYPE_MASK 0x3 /* address type */
6794 +#define SBAM_AD64 0x4 /* reserved */
6795 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
6796 +#define SBAM_ADINT0_SHIFT 3
6797 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
6798 +#define SBAM_ADINT1_SHIFT 3
6799 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
6800 +#define SBAM_ADINT2_SHIFT 3
6801 +#define SBAM_ADEN 0x400 /* enable */
6802 +#define SBAM_ADNEG 0x800 /* negative decode */
6803 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
6804 +#define SBAM_BASE0_SHIFT 8
6805 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
6806 +#define SBAM_BASE1_SHIFT 12
6807 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
6808 +#define SBAM_BASE2_SHIFT 16
6809 +
6810 +/* sbtmconfiglow */
6811 +#define SBTMCL_CD_MASK 0xff /* clock divide */
6812 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
6813 +#define SBTMCL_CO_SHIFT 11
6814 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
6815 +#define SBTMCL_IF_SHIFT 18
6816 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
6817 +#define SBTMCL_IM_SHIFT 24
6818 +
6819 +/* sbtmconfighigh */
6820 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
6821 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
6822 +#define SBTMCH_RM_SHIFT 2
6823 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
6824 +#define SBTMCH_SM_SHIFT 4
6825 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
6826 +#define SBTMCH_EM_SHIFT 8
6827 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
6828 +#define SBTMCH_IM_SHIFT 10
6829 +
6830 +/* sbbconfig */
6831 +#define SBBC_LAT_MASK 0x3 /* sb latency */
6832 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
6833 +#define SBBC_MAX0_SHIFT 16
6834 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
6835 +#define SBBC_MAX1_SHIFT 20
6836 +
6837 +/* sbbstate */
6838 +#define SBBS_SRD 0x1 /* st reg disable */
6839 +#define SBBS_HRD 0x2 /* hold reg disable */
6840 +
6841 +/* sbidlow */
6842 +#define SBIDL_CS_MASK 0x3 /* config space */
6843 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
6844 +#define SBIDL_AR_SHIFT 3
6845 +#define SBIDL_SYNCH 0x40 /* sync */
6846 +#define SBIDL_INIT 0x80 /* initiator */
6847 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
6848 +#define SBIDL_MINLAT_SHIFT 8
6849 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
6850 +#define SBIDL_MAXLAT_SHIFT 12
6851 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
6852 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
6853 +#define SBIDL_CW_SHIFT 18
6854 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
6855 +#define SBIDL_TP_SHIFT 20
6856 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
6857 +#define SBIDL_IP_SHIFT 24
6858 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
6859 +#define SBIDL_RV_SHIFT 28
6860 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
6861 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
6862 +
6863 +/* sbidhigh */
6864 +#define SBIDH_RC_MASK 0x000f /* revision code */
6865 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
6866 +#define SBIDH_RCE_SHIFT 8
6867 +#define SBCOREREV(sbidh) \
6868 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
6869 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
6870 +#define SBIDH_CC_SHIFT 4
6871 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
6872 +#define SBIDH_VC_SHIFT 16
6873 +
6874 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
6875 +
6876 +/* vendor codes */
6877 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
6878 +
6879 +/* core codes */
6880 +#define SB_NODEV 0x700 /* Invalid coreid */
6881 +#define SB_CC 0x800 /* chipcommon core */
6882 +#define SB_ILINE20 0x801 /* iline20 core */
6883 +#define SB_SDRAM 0x803 /* sdram core */
6884 +#define SB_PCI 0x804 /* pci core */
6885 +#define SB_MIPS 0x805 /* mips core */
6886 +#define SB_ENET 0x806 /* enet mac core */
6887 +#define SB_CODEC 0x807 /* v90 codec core */
6888 +#define SB_USB 0x808 /* usb 1.1 host/device core */
6889 +#define SB_ADSL 0x809 /* ADSL core */
6890 +#define SB_ILINE100 0x80a /* iline100 core */
6891 +#define SB_IPSEC 0x80b /* ipsec core */
6892 +#define SB_PCMCIA 0x80d /* pcmcia core */
6893 +#define SB_SDIOD SB_PCMCIA /* pcmcia core has sdio device */
6894 +#define SB_SOCRAM 0x80e /* internal memory core */
6895 +#define SB_MEMC 0x80f /* memc sdram core */
6896 +#define SB_EXTIF 0x811 /* external interface core */
6897 +#define SB_D11 0x812 /* 802.11 MAC core */
6898 +#define SB_MIPS33 0x816 /* mips3302 core */
6899 +#define SB_USB11H 0x817 /* usb 1.1 host core */
6900 +#define SB_USB11D 0x818 /* usb 1.1 device core */
6901 +#define SB_USB20H 0x819 /* usb 2.0 host core */
6902 +#define SB_USB20D 0x81a /* usb 2.0 device core */
6903 +#define SB_SDIOH 0x81b /* sdio host core */
6904 +#define SB_ROBO 0x81c /* roboswitch core */
6905 +#define SB_ATA100 0x81d /* parallel ATA core */
6906 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
6907 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
6908 +#define SB_PCIE 0x820 /* pci express core */
6909 +#define SB_MIMO 0x821 /* MIMO phy core */
6910 +#define SB_SRAMC 0x822 /* SRAM controller core */
6911 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
6912 +#define SB_ARM11 0x824 /* ARM 1176 core */
6913 +#define SB_ARM7 0x825 /* ARM 7tdmi core */
6914 +
6915 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
6916 +
6917 +/* Not really related to Silicon Backplane, but a couple of software
6918 + * conventions for the use the flash space:
6919 + */
6920 +
6921 +/* Minumum amount of flash we support */
6922 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
6923 +
6924 +/* A boot/binary may have an embedded block that describes its size */
6925 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
6926 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
6927 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
6928 +#define BISZ_TXTST_IDX 1 /* 1: text start */
6929 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
6930 +#define BISZ_DATAST_IDX 3 /* 3: text start */
6931 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
6932 +#define BISZ_BSSST_IDX 5 /* 5: text start */
6933 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
6934 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
6935 +
6936 +#endif /* _SBCONFIG_H */
6937 diff -urN linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
6938 --- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
6939 +++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2006-04-27 22:13:03.000000000 +0200
6940 @@ -0,0 +1,243 @@
6941 +/*
6942 + * Hardware-specific External Interface I/O core definitions
6943 + * for the BCM47xx family of SiliconBackplane-based chips.
6944 + *
6945 + * The External Interface core supports a total of three external chip selects
6946 + * supporting external interfaces. One of the external chip selects is
6947 + * used for Flash, one is used for PCMCIA, and the other may be
6948 + * programmed to support either a synchronous interface or an
6949 + * asynchronous interface. The asynchronous interface can be used to
6950 + * support external devices such as UARTs and the BCM2019 Bluetooth
6951 + * baseband processor.
6952 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
6953 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
6954 + *
6955 + * Copyright 2006, Broadcom Corporation
6956 + * All Rights Reserved.
6957 + *
6958 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6959 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6960 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6961 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6962 + *
6963 + * $Id: sbextif.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
6964 + */
6965 +
6966 +#ifndef _SBEXTIF_H
6967 +#define _SBEXTIF_H
6968 +
6969 +/* external interface address space */
6970 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
6971 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
6972 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
6973 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
6974 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
6975 +
6976 +/* cpp contortions to concatenate w/arg prescan */
6977 +#ifndef PAD
6978 +#define _PADLINE(line) pad ## line
6979 +#define _XSTR(line) _PADLINE(line)
6980 +#define PAD _XSTR(__LINE__)
6981 +#endif /* PAD */
6982 +
6983 +/*
6984 + * The multiple instances of output and output enable registers
6985 + * are present to allow driver software for multiple cores to control
6986 + * gpio outputs without needing to share a single register pair.
6987 + */
6988 +struct gpiouser {
6989 + uint32 out;
6990 + uint32 outen;
6991 +};
6992 +#define NGPIOUSER 5
6993 +
6994 +typedef volatile struct {
6995 + uint32 corecontrol;
6996 + uint32 extstatus;
6997 + uint32 PAD[2];
6998 +
6999 + /* pcmcia control registers */
7000 + uint32 pcmcia_config;
7001 + uint32 pcmcia_memwait;
7002 + uint32 pcmcia_attrwait;
7003 + uint32 pcmcia_iowait;
7004 +
7005 + /* programmable interface control registers */
7006 + uint32 prog_config;
7007 + uint32 prog_waitcount;
7008 +
7009 + /* flash control registers */
7010 + uint32 flash_config;
7011 + uint32 flash_waitcount;
7012 + uint32 PAD[4];
7013 +
7014 + uint32 watchdog;
7015 +
7016 + /* clock control */
7017 + uint32 clockcontrol_n;
7018 + uint32 clockcontrol_sb;
7019 + uint32 clockcontrol_pci;
7020 + uint32 clockcontrol_mii;
7021 + uint32 PAD[3];
7022 +
7023 + /* gpio */
7024 + uint32 gpioin;
7025 + struct gpiouser gpio[NGPIOUSER];
7026 + uint32 PAD;
7027 + uint32 ejtagouten;
7028 + uint32 gpiointpolarity;
7029 + uint32 gpiointmask;
7030 + uint32 PAD[153];
7031 +
7032 + uint8 uartdata;
7033 + uint8 PAD[3];
7034 + uint8 uartimer;
7035 + uint8 PAD[3];
7036 + uint8 uartfcr;
7037 + uint8 PAD[3];
7038 + uint8 uartlcr;
7039 + uint8 PAD[3];
7040 + uint8 uartmcr;
7041 + uint8 PAD[3];
7042 + uint8 uartlsr;
7043 + uint8 PAD[3];
7044 + uint8 uartmsr;
7045 + uint8 PAD[3];
7046 + uint8 uartscratch;
7047 + uint8 PAD[3];
7048 +} extifregs_t;
7049 +
7050 +/* corecontrol */
7051 +#define CC_UE (1 << 0) /* uart enable */
7052 +
7053 +/* extstatus */
7054 +#define ES_EM (1 << 0) /* endian mode (ro) */
7055 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
7056 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
7057 +
7058 +/* gpio bit mask */
7059 +#define GPIO_BIT0 (1 << 0)
7060 +#define GPIO_BIT1 (1 << 1)
7061 +#define GPIO_BIT2 (1 << 2)
7062 +#define GPIO_BIT3 (1 << 3)
7063 +#define GPIO_BIT4 (1 << 4)
7064 +#define GPIO_BIT5 (1 << 5)
7065 +#define GPIO_BIT6 (1 << 6)
7066 +#define GPIO_BIT7 (1 << 7)
7067 +
7068 +
7069 +/* pcmcia/prog/flash_config */
7070 +#define CF_EN (1 << 0) /* enable */
7071 +#define CF_EM_MASK 0xe /* mode */
7072 +#define CF_EM_SHIFT 1
7073 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
7074 +#define CF_EM_SYNC 0x2 /* synchronous mode */
7075 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
7076 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
7077 +#define CF_BS (1 << 5) /* byteswap */
7078 +#define CF_CD_MASK 0xc0 /* clock divider */
7079 +#define CF_CD_SHIFT 6
7080 +#define CF_CD_DIV2 0x0 /* backplane/2 */
7081 +#define CF_CD_DIV3 0x40 /* backplane/3 */
7082 +#define CF_CD_DIV4 0x80 /* backplane/4 */
7083 +#define CF_CE (1 << 8) /* clock enable */
7084 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
7085 +
7086 +/* pcmcia_memwait */
7087 +#define PM_W0_MASK 0x3f /* waitcount0 */
7088 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
7089 +#define PM_W1_SHIFT 8
7090 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
7091 +#define PM_W2_SHIFT 16
7092 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
7093 +#define PM_W3_SHIFT 24
7094 +
7095 +/* pcmcia_attrwait */
7096 +#define PA_W0_MASK 0x3f /* waitcount0 */
7097 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
7098 +#define PA_W1_SHIFT 8
7099 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
7100 +#define PA_W2_SHIFT 16
7101 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
7102 +#define PA_W3_SHIFT 24
7103 +
7104 +/* pcmcia_iowait */
7105 +#define PI_W0_MASK 0x3f /* waitcount0 */
7106 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
7107 +#define PI_W1_SHIFT 8
7108 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
7109 +#define PI_W2_SHIFT 16
7110 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
7111 +#define PI_W3_SHIFT 24
7112 +
7113 +/* prog_waitcount */
7114 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
7115 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
7116 +#define PW_W1_SHIFT 8
7117 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
7118 +#define PW_W2_SHIFT 16
7119 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
7120 +#define PW_W3_SHIFT 24
7121 +
7122 +#define PW_W0 0x0000000c
7123 +#define PW_W1 0x00000a00
7124 +#define PW_W2 0x00020000
7125 +#define PW_W3 0x01000000
7126 +
7127 +/* flash_waitcount */
7128 +#define FW_W0_MASK 0x1f /* waitcount0 */
7129 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
7130 +#define FW_W1_SHIFT 8
7131 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
7132 +#define FW_W2_SHIFT 16
7133 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
7134 +#define FW_W3_SHIFT 24
7135 +
7136 +/* watchdog */
7137 +#define WATCHDOG_CLOCK 48000000 /* Hz */
7138 +
7139 +/* clockcontrol_n */
7140 +#define CN_N1_MASK 0x3f /* n1 control */
7141 +#define CN_N2_MASK 0x3f00 /* n2 control */
7142 +#define CN_N2_SHIFT 8
7143 +
7144 +/* clockcontrol_sb/pci/mii */
7145 +#define CC_M1_MASK 0x3f /* m1 control */
7146 +#define CC_M2_MASK 0x3f00 /* m2 control */
7147 +#define CC_M2_SHIFT 8
7148 +#define CC_M3_MASK 0x3f0000 /* m3 control */
7149 +#define CC_M3_SHIFT 16
7150 +#define CC_MC_MASK 0x1f000000 /* mux control */
7151 +#define CC_MC_SHIFT 24
7152 +
7153 +/* Clock control default values */
7154 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
7155 +#define CC_DEF_100 0x04020011
7156 +#define CC_DEF_33 0x11030011
7157 +#define CC_DEF_25 0x11050011
7158 +
7159 +/* Clock control values for 125Mhz */
7160 +#define CC_125_N 0x0802
7161 +#define CC_125_M 0x04020009
7162 +#define CC_125_M25 0x11090009
7163 +#define CC_125_M33 0x11090005
7164 +
7165 +/* Clock control magic field values */
7166 +#define CC_F6_2 0x02 /* A factor of 2 in */
7167 +#define CC_F6_3 0x03 /* 6-bit fields like */
7168 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
7169 +#define CC_F6_5 0x09
7170 +#define CC_F6_6 0x11
7171 +#define CC_F6_7 0x21
7172 +
7173 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
7174 +
7175 +#define CC_MC_BYPASS 0x08
7176 +#define CC_MC_M1 0x04
7177 +#define CC_MC_M1M2 0x02
7178 +#define CC_MC_M1M2M3 0x01
7179 +#define CC_MC_M1M3 0x11
7180 +
7181 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
7182 +
7183 +#endif /* _SBEXTIF_H */
7184 diff -urN linux.old/arch/mips/bcm947xx/include/sbhndmips.h linux.dev/arch/mips/bcm947xx/include/sbhndmips.h
7185 --- linux.old/arch/mips/bcm947xx/include/sbhndmips.h 1970-01-01 01:00:00.000000000 +0100
7186 +++ linux.dev/arch/mips/bcm947xx/include/sbhndmips.h 2006-04-27 20:43:56.000000000 +0200
7187 @@ -0,0 +1,47 @@
7188 +/*
7189 + * Broadcom SiliconBackplane MIPS definitions
7190 + *
7191 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
7192 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
7193 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
7194 + * interface. The core revision is stored in the SB ID register in SB
7195 + * configuration space.
7196 + *
7197 + * Copyright 2006, Broadcom Corporation
7198 + * All Rights Reserved.
7199 + *
7200 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7201 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7202 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7203 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7204 + *
7205 + * $Id: sbhndmips.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
7206 + */
7207 +
7208 +#ifndef _sbhndmips_h_
7209 +#define _sbhndmips_h_
7210 +
7211 +#include <mipsinc.h>
7212 +
7213 +#ifndef _LANGUAGE_ASSEMBLY
7214 +
7215 +/* cpp contortions to concatenate w/arg prescan */
7216 +#ifndef PAD
7217 +#define _PADLINE(line) pad ## line
7218 +#define _XSTR(line) _PADLINE(line)
7219 +#define PAD _XSTR(__LINE__)
7220 +#endif /* PAD */
7221 +
7222 +typedef volatile struct {
7223 + uint32 corecontrol;
7224 + uint32 PAD[2];
7225 + uint32 biststatus;
7226 + uint32 PAD[4];
7227 + uint32 intstatus;
7228 + uint32 intmask;
7229 + uint32 timer;
7230 +} mipsregs_t;
7231 +
7232 +#endif /* _LANGUAGE_ASSEMBLY */
7233 +
7234 +#endif /* _sbhndmips_h_ */
7235 diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
7236 --- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
7237 +++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2006-04-27 22:12:41.000000000 +0200
7238 @@ -0,0 +1,147 @@
7239 +/*
7240 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
7241 + *
7242 + * Copyright 2006, Broadcom Corporation
7243 + * All Rights Reserved.
7244 + *
7245 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7246 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7247 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7248 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7249 + *
7250 + * $Id: sbmemc.h,v 1.6 2006/03/02 12:33:44 honor Exp $
7251 + */
7252 +
7253 +#ifndef _SBMEMC_H
7254 +#define _SBMEMC_H
7255 +
7256 +#ifdef _LANGUAGE_ASSEMBLY
7257 +
7258 +#define MEMC_CONTROL 0x00
7259 +#define MEMC_CONFIG 0x04
7260 +#define MEMC_REFRESH 0x08
7261 +#define MEMC_BISTSTAT 0x0c
7262 +#define MEMC_MODEBUF 0x10
7263 +#define MEMC_BKCLS 0x14
7264 +#define MEMC_PRIORINV 0x18
7265 +#define MEMC_DRAMTIM 0x1c
7266 +#define MEMC_INTSTAT 0x20
7267 +#define MEMC_INTMASK 0x24
7268 +#define MEMC_INTINFO 0x28
7269 +#define MEMC_NCDLCTL 0x30
7270 +#define MEMC_RDNCDLCOR 0x34
7271 +#define MEMC_WRNCDLCOR 0x38
7272 +#define MEMC_MISCDLYCTL 0x3c
7273 +#define MEMC_DQSGATENCDL 0x40
7274 +#define MEMC_SPARE 0x44
7275 +#define MEMC_TPADDR 0x48
7276 +#define MEMC_TPDATA 0x4c
7277 +#define MEMC_BARRIER 0x50
7278 +#define MEMC_CORE 0x54
7279 +
7280 +#else /* !_LANGUAGE_ASSEMBLY */
7281 +
7282 +/* Sonics side: MEMC core registers */
7283 +typedef volatile struct sbmemcregs {
7284 + uint32 control;
7285 + uint32 config;
7286 + uint32 refresh;
7287 + uint32 biststat;
7288 + uint32 modebuf;
7289 + uint32 bkcls;
7290 + uint32 priorinv;
7291 + uint32 dramtim;
7292 + uint32 intstat;
7293 + uint32 intmask;
7294 + uint32 intinfo;
7295 + uint32 reserved1;
7296 + uint32 ncdlctl;
7297 + uint32 rdncdlcor;
7298 + uint32 wrncdlcor;
7299 + uint32 miscdlyctl;
7300 + uint32 dqsgatencdl;
7301 + uint32 spare;
7302 + uint32 tpaddr;
7303 + uint32 tpdata;
7304 + uint32 barrier;
7305 + uint32 core;
7306 +} sbmemcregs_t;
7307 +
7308 +#endif /* _LANGUAGE_ASSEMBLY */
7309 +
7310 +/* MEMC Core Init values (OCP ID 0x80f) */
7311 +
7312 +/* For sdr: */
7313 +#define MEMC_SD_CONFIG_INIT 0x00048000
7314 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
7315 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
7316 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
7317 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
7318 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
7319 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
7320 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
7321 +#define MEMC_SD_CONTROL_INIT0 0x00000002
7322 +#define MEMC_SD_CONTROL_INIT1 0x00000008
7323 +#define MEMC_SD_CONTROL_INIT2 0x00000004
7324 +#define MEMC_SD_CONTROL_INIT3 0x00000010
7325 +#define MEMC_SD_CONTROL_INIT4 0x00000001
7326 +#define MEMC_SD_MODEBUF_INIT 0x00000000
7327 +#define MEMC_SD_REFRESH_INIT 0x0000840f
7328 +
7329 +
7330 +/* This is for SDRM8X8X4 */
7331 +#define MEMC_SDR_INIT 0x0008
7332 +#define MEMC_SDR_MODE 0x32
7333 +#define MEMC_SDR_NCDL 0x00020032
7334 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
7335 +
7336 +/* For ddr: */
7337 +#define MEMC_CONFIG_INIT 0x00048000
7338 +#define MEMC_DRAMTIM2_INIT 0x000754d8
7339 +#define MEMC_DRAMTIM25_INIT 0x000754d9
7340 +#define MEMC_RDNCDLCOR_INIT 0x00000000
7341 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
7342 +#define MEMC_WRNCDLCOR_INIT 0x49351200
7343 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
7344 +#define MEMC_DQSGATENCDL_INIT 0x00030000
7345 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
7346 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
7347 +#define MEMC_NCDLCTL_INIT 0x00002001
7348 +#define MEMC_CONTROL_INIT0 0x00000002
7349 +#define MEMC_CONTROL_INIT1 0x00000008
7350 +#define MEMC_MODEBUF_INIT0 0x00004000
7351 +#define MEMC_CONTROL_INIT2 0x00000010
7352 +#define MEMC_MODEBUF_INIT1 0x00000100
7353 +#define MEMC_CONTROL_INIT3 0x00000010
7354 +#define MEMC_CONTROL_INIT4 0x00000008
7355 +#define MEMC_REFRESH_INIT 0x0000840f
7356 +#define MEMC_CONTROL_INIT5 0x00000004
7357 +#define MEMC_MODEBUF_INIT2 0x00000000
7358 +#define MEMC_CONTROL_INIT6 0x00000010
7359 +#define MEMC_CONTROL_INIT7 0x00000001
7360 +
7361 +
7362 +/* This is for DDRM16X16X2 */
7363 +#define MEMC_DDR_INIT 0x0009
7364 +#define MEMC_DDR_MODE 0x62
7365 +#define MEMC_DDR_NCDL 0x0005050a
7366 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
7367 +
7368 +/* mask for sdr/ddr calibration registers */
7369 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
7370 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
7371 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
7372 +
7373 +/* masks for miscdlyctl registers */
7374 +#define MEMC_MISC_SM_MASK 0x30000000
7375 +#define MEMC_MISC_SM_SHIFT 28
7376 +#define MEMC_MISC_SD_MASK 0x0f000000
7377 +#define MEMC_MISC_SD_SHIFT 24
7378 +
7379 +/* hw threshhold for calculating wr/rd for sdr memc */
7380 +#define MEMC_CD_THRESHOLD 128
7381 +
7382 +/* Low bit of init register says if memc is ddr or sdr */
7383 +#define MEMC_CONFIG_DDR 0x00000001
7384 +
7385 +#endif /* _SBMEMC_H */
7386 diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
7387 --- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
7388 +++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2006-05-02 17:20:14.000000000 +0200
7389 @@ -0,0 +1,114 @@
7390 +/*
7391 + * HND SiliconBackplane PCI core hardware definitions.
7392 + *
7393 + * Copyright 2006, Broadcom Corporation
7394 + * All Rights Reserved.
7395 + *
7396 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7397 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7398 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7399 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7400 + *
7401 + * $Id: sbpci.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
7402 + */
7403 +
7404 +#ifndef _sbpci_h_
7405 +#define _sbpci_h_
7406 +
7407 +#ifndef _LANGUAGE_ASSEMBLY
7408 +
7409 +/* cpp contortions to concatenate w/arg prescan */
7410 +#ifndef PAD
7411 +#define _PADLINE(line) pad ## line
7412 +#define _XSTR(line) _PADLINE(line)
7413 +#define PAD _XSTR(__LINE__)
7414 +#endif
7415 +
7416 +/* Sonics side: PCI core and host control registers */
7417 +typedef struct sbpciregs {
7418 + uint32 control; /* PCI control */
7419 + uint32 PAD[3];
7420 + uint32 arbcontrol; /* PCI arbiter control */
7421 + uint32 PAD[3];
7422 + uint32 intstatus; /* Interrupt status */
7423 + uint32 intmask; /* Interrupt mask */
7424 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
7425 + uint32 PAD[9];
7426 + uint32 bcastaddr; /* Sonics broadcast address */
7427 + uint32 bcastdata; /* Sonics broadcast data */
7428 + uint32 PAD[2];
7429 + uint32 gpioin; /* ro: gpio input (>=rev2) */
7430 + uint32 gpioout; /* rw: gpio output (>=rev2) */
7431 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
7432 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
7433 + uint32 PAD[36];
7434 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
7435 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
7436 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
7437 + uint32 PAD[189];
7438 + uint32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
7439 + uint16 sprom[36]; /* SPROM shadow Area */
7440 + uint32 PAD[46];
7441 +} sbpciregs_t;
7442 +
7443 +#endif /* _LANGUAGE_ASSEMBLY */
7444 +
7445 +/* PCI control */
7446 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
7447 +#define PCI_RST 0x02 /* Value driven out to pin */
7448 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
7449 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
7450 +
7451 +/* PCI arbiter control */
7452 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
7453 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
7454 +/* ParkID - for PCI corerev >= 8 */
7455 +#define PCI_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */
7456 +#define PCI_PARKID_SHIFT 2
7457 +#define PCI_PARKID_EXT0 0 /* External master 0 */
7458 +#define PCI_PARKID_EXT1 1 /* External master 1 */
7459 +#define PCI_PARKID_EXT2 2 /* External master 2 */
7460 +#define PCI_PARKID_INT 3 /* Internal master */
7461 +#define PCI_PARKID_LAST 4 /* Last active master */
7462 +
7463 +/* Interrupt status/mask */
7464 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
7465 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
7466 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
7467 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
7468 +#define PCI_PME 0x10 /* PCI PME# is asserted */
7469 +
7470 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
7471 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
7472 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
7473 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
7474 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
7475 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
7476 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
7477 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
7478 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
7479 +
7480 +/* Sonics broadcast address */
7481 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
7482 +
7483 +/* Sonics to PCI translation types */
7484 +#define SBTOPCI0_MASK 0xfc000000
7485 +#define SBTOPCI1_MASK 0xfc000000
7486 +#define SBTOPCI2_MASK 0xc0000000
7487 +#define SBTOPCI_MEM 0
7488 +#define SBTOPCI_IO 1
7489 +#define SBTOPCI_CFG0 2
7490 +#define SBTOPCI_CFG1 3
7491 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
7492 +#define SBTOPCI_BURST 0x8 /* burst enable */
7493 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
7494 +#define SBTOPCI_RC_READ 0x00 /* memory read */
7495 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
7496 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
7497 +
7498 +/* PCI core index in SROM shadow area */
7499 +#define SRSH_PI_OFFSET 0 /* first word */
7500 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
7501 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
7502 +
7503 +#endif /* _sbpci_h_ */
7504 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcie.h linux.dev/arch/mips/bcm947xx/include/sbpcie.h
7505 --- linux.old/arch/mips/bcm947xx/include/sbpcie.h 1970-01-01 01:00:00.000000000 +0100
7506 +++ linux.dev/arch/mips/bcm947xx/include/sbpcie.h 2006-04-27 20:42:22.000000000 +0200
7507 @@ -0,0 +1,200 @@
7508 +/*
7509 + * BCM43XX SiliconBackplane PCIE core hardware definitions.
7510 + *
7511 + * Copyright 2006, Broadcom Corporation
7512 + * All Rights Reserved.
7513 + *
7514 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7515 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7516 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7517 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7518 + *
7519 + * $Id: sbpcie.h,v 1.1.1.2 2006/02/27 03:43:16 honor Exp $
7520 + */
7521 +
7522 +#ifndef _SBPCIE_H
7523 +#define _SBPCIE_H
7524 +
7525 +/* cpp contortions to concatenate w/arg prescan */
7526 +#ifndef PAD
7527 +#define _PADLINE(line) pad ## line
7528 +#define _XSTR(line) _PADLINE(line)
7529 +#define PAD _XSTR(__LINE__)
7530 +#endif
7531 +
7532 +/* PCIE Enumeration space offsets */
7533 +#define PCIE_CORE_CONFIG_OFFSET 0x0
7534 +#define PCIE_FUNC0_CONFIG_OFFSET 0x400
7535 +#define PCIE_FUNC1_CONFIG_OFFSET 0x500
7536 +#define PCIE_FUNC2_CONFIG_OFFSET 0x600
7537 +#define PCIE_FUNC3_CONFIG_OFFSET 0x700
7538 +#define PCIE_SPROM_SHADOW_OFFSET 0x800
7539 +#define PCIE_SBCONFIG_OFFSET 0xE00
7540 +
7541 +/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
7542 +#define PCIE_DEV_BAR0_SIZE 0x4000
7543 +#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0
7544 +#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000
7545 +#define PCIE_BAR0_PCIECORE_OFFSET 0x2000
7546 +#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
7547 +
7548 +/* SB side: PCIE core and host control registers */
7549 +typedef struct sbpcieregs {
7550 + uint32 PAD[3];
7551 + uint32 biststatus; /* bist Status: 0x00C */
7552 + uint32 PAD[6];
7553 + uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */
7554 + uint32 PAD[54];
7555 + uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
7556 + uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
7557 + uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
7558 + uint32 PAD[4];
7559 +
7560 + /* pcie core supports in direct access to config space */
7561 + uint32 configaddr; /* pcie config space access: Address field: 0x120 */
7562 + uint32 configdata; /* pcie config space access: Data field: 0x124 */
7563 +
7564 + /* mdio access to serdes */
7565 + uint32 mdiocontrol; /* controls the mdio access: 0x128 */
7566 + uint32 mdiodata; /* Data to the mdio access: 0x12c */
7567 +
7568 + /* pcie protocol phy/dllp/tlp register access mechanism */
7569 + uint32 pcieaddr; /* address of the internal registeru: 0x130 */
7570 + uint32 pciedata; /* Data to/from the internal regsiter: 0x134 */
7571 +
7572 + uint32 PAD[434];
7573 + uint16 sprom[36]; /* SPROM shadow Area */
7574 +} sbpcieregs_t;
7575 +
7576 +/* SB to PCIE translation masks */
7577 +#define SBTOPCIE0_MASK 0xfc000000
7578 +#define SBTOPCIE1_MASK 0xfc000000
7579 +#define SBTOPCIE2_MASK 0xc0000000
7580 +
7581 +/* Access type bits (0:1) */
7582 +#define SBTOPCIE_MEM 0
7583 +#define SBTOPCIE_IO 1
7584 +#define SBTOPCIE_CFG0 2
7585 +#define SBTOPCIE_CFG1 3
7586 +
7587 +/* Prefetch enable bit 2 */
7588 +#define SBTOPCIE_PF 4
7589 +
7590 +/* Write Burst enable for memory write bit 3 */
7591 +#define SBTOPCIE_WR_BURST 8
7592 +
7593 +/* config access */
7594 +#define CONFIGADDR_FUNC_MASK 0x7000
7595 +#define CONFIGADDR_FUNC_SHF 12
7596 +#define CONFIGADDR_REG_MASK 0x0FFF
7597 +#define CONFIGADDR_REG_SHF 0
7598 +
7599 +/* PCIE protocol regs Indirect Address */
7600 +#define PCIEADDR_PROT_MASK 0x300
7601 +#define PCIEADDR_PROT_SHF 8
7602 +#define PCIEADDR_PL_TLP 0
7603 +#define PCIEADDR_PL_DLLP 1
7604 +#define PCIEADDR_PL_PLP 2
7605 +
7606 +/* PCIE protocol PHY diagnostic registers */
7607 +#define PCIE_PLP_MODEREG 0x200 /* Mode */
7608 +#define PCIE_PLP_STATUSREG 0x204 /* Status */
7609 +#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
7610 +#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
7611 +#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
7612 +#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
7613 +#define PCIE_PLP_ATTNREG 0x218 /* Attention */
7614 +#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */
7615 +#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */
7616 +#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
7617 +#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
7618 +#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg */
7619 +#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
7620 +#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
7621 +#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
7622 +#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
7623 +
7624 +/* PCIE protocol DLLP diagnostic registers */
7625 +#define PCIE_DLLP_LCREG 0x100 /* Link Control */
7626 +#define PCIE_DLLP_LSREG 0x104 /* Link Status */
7627 +#define PCIE_DLLP_LAREG 0x108 /* Link Attention */
7628 +#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
7629 +#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
7630 +#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
7631 +#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
7632 +#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
7633 +#define PCIE_DLLP_LRREG 0x120 /* Link Replay */
7634 +#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
7635 +#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
7636 +#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
7637 +#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
7638 +#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
7639 +#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
7640 +#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
7641 +#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
7642 +#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter */
7643 +#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
7644 +#define PCIE_DLLP_TESTREG 0x14C /* Test */
7645 +#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */
7646 +
7647 +/* PCIE protocol TLP diagnostic registers */
7648 +#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
7649 +#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
7650 +#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address */
7651 +#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address */
7652 +#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req */
7653 +#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address */
7654 +#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address */
7655 +#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req */
7656 +#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address */
7657 +#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address */
7658 +#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req */
7659 +#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len */
7660 +#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs */
7661 +#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req */
7662 +#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len */
7663 +#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0 */
7664 +#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1 */
7665 +#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2 */
7666 +#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */
7667 +#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */
7668 +#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */
7669 +#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len */
7670 +#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0 */
7671 +#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1 */
7672 +#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func */
7673 +#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter */
7674 +#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value */
7675 +#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1 */
7676 +#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2 */
7677 +#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3 */
7678 +#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4 */
7679 +
7680 +/* MDIO control */
7681 +#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
7682 +#define MDIOCTL_DIVISOR_VAL 0x2
7683 +#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
7684 +#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
7685 +
7686 +/* MDIO Data */
7687 +#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
7688 +#define MDIODATA_TA 0x00020000 /* Turnaround */
7689 +#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
7690 +#define MDIODATA_REGADDR_MASK 0x003c0000 /* Regaddr Mask */
7691 +#define MDIODATA_DEVADDR_SHF 22 /* Physmedia devaddr shift */
7692 +#define MDIODATA_DEVADDR_MASK 0x0fc00000 /* Physmedia devaddr Mask */
7693 +#define MDIODATA_WRITE 0x10000000 /* write Transaction */
7694 +#define MDIODATA_READ 0x20000000 /* Read Transaction */
7695 +#define MDIODATA_START 0x40000000 /* start of Transaction */
7696 +
7697 +/* MDIO devices (SERDES modules) */
7698 +#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
7699 +#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
7700 +#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
7701 +
7702 +/* SERDES registers */
7703 +#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
7704 +#define SERDES_RX_CDR 6 /* CDR */
7705 +#define SERDES_RX_CDRBW 7 /* CDR BW */
7706 +
7707 +#endif /* _SBPCIE_H */
7708 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcmcia.h linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h
7709 --- linux.old/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
7710 +++ linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h 2006-04-27 20:29:47.000000000 +0200
7711 @@ -0,0 +1,147 @@
7712 +/*
7713 + * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
7714 + *
7715 + * Copyright 2006, Broadcom Corporation
7716 + * All Rights Reserved.
7717 + *
7718 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7719 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7720 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7721 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7722 + *
7723 + * $Id: sbpcmcia.h,v 1.1.1.9 2006/02/27 03:43:16 honor Exp $
7724 + */
7725 +
7726 +#ifndef _SBPCMCIA_H
7727 +#define _SBPCMCIA_H
7728 +
7729 +
7730 +/* All the addresses that are offsets in attribute space are divided
7731 + * by two to account for the fact that odd bytes are invalid in
7732 + * attribute space and our read/write routines make the space appear
7733 + * as if they didn't exist. Still we want to show the original numbers
7734 + * as documented in the hnd_pcmcia core manual.
7735 + */
7736 +
7737 +/* PCMCIA Function Configuration Registers */
7738 +#define PCMCIA_FCR (0x700 / 2)
7739 +
7740 +#define FCR0_OFF 0
7741 +#define FCR1_OFF (0x40 / 2)
7742 +#define FCR2_OFF (0x80 / 2)
7743 +#define FCR3_OFF (0xc0 / 2)
7744 +
7745 +#define PCMCIA_FCR0 (0x700 / 2)
7746 +#define PCMCIA_FCR1 (0x740 / 2)
7747 +#define PCMCIA_FCR2 (0x780 / 2)
7748 +#define PCMCIA_FCR3 (0x7c0 / 2)
7749 +
7750 +/* Standard PCMCIA FCR registers */
7751 +
7752 +#define PCMCIA_COR 0
7753 +
7754 +#define COR_RST 0x80
7755 +#define COR_LEV 0x40
7756 +#define COR_IRQEN 0x04
7757 +#define COR_BLREN 0x01
7758 +#define COR_FUNEN 0x01
7759 +
7760 +
7761 +#define PCICIA_FCSR (2 / 2)
7762 +#define PCICIA_PRR (4 / 2)
7763 +#define PCICIA_SCR (6 / 2)
7764 +#define PCICIA_ESR (8 / 2)
7765 +
7766 +
7767 +#define PCM_MEMOFF 0x0000
7768 +#define F0_MEMOFF 0x1000
7769 +#define F1_MEMOFF 0x2000
7770 +#define F2_MEMOFF 0x3000
7771 +#define F3_MEMOFF 0x4000
7772 +
7773 +/* Memory base in the function fcr's */
7774 +#define MEM_ADDR0 (0x728 / 2)
7775 +#define MEM_ADDR1 (0x72a / 2)
7776 +#define MEM_ADDR2 (0x72c / 2)
7777 +
7778 +/* PCMCIA base plus Srom access in fcr0: */
7779 +#define PCMCIA_ADDR0 (0x072e / 2)
7780 +#define PCMCIA_ADDR1 (0x0730 / 2)
7781 +#define PCMCIA_ADDR2 (0x0732 / 2)
7782 +
7783 +#define MEM_SEG (0x0734 / 2)
7784 +#define SROM_CS (0x0736 / 2)
7785 +#define SROM_DATAL (0x0738 / 2)
7786 +#define SROM_DATAH (0x073a / 2)
7787 +#define SROM_ADDRL (0x073c / 2)
7788 +#define SROM_ADDRH (0x073e / 2)
7789 +
7790 +/* Values for srom_cs: */
7791 +#define SROM_IDLE 0
7792 +#define SROM_WRITE 1
7793 +#define SROM_READ 2
7794 +#define SROM_WEN 4
7795 +#define SROM_WDS 7
7796 +#define SROM_DONE 8
7797 +
7798 +/* CIS stuff */
7799 +
7800 +/* The CIS stops where the FCRs start */
7801 +#define CIS_SIZE PCMCIA_FCR
7802 +
7803 +/* Standard tuples we know about */
7804 +
7805 +#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
7806 +#define CISTPL_FUNCE 0x22 /* Function extensions */
7807 +#define CISTPL_CFTABLE 0x1b /* Config table entry */
7808 +
7809 +/* Function extensions for LANs */
7810 +
7811 +#define LAN_TECH 1 /* Technology type */
7812 +#define LAN_SPEED 2 /* Raw bit rate */
7813 +#define LAN_MEDIA 3 /* Transmission media */
7814 +#define LAN_NID 4 /* Node identification (aka MAC addr) */
7815 +#define LAN_CONN 5 /* Connector standard */
7816 +
7817 +
7818 +/* CFTable */
7819 +#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
7820 +#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
7821 +#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
7822 +
7823 +/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
7824 + * take one for HNBU, and use "extensions" (a la FUNCE) within it.
7825 + */
7826 +
7827 +#define CISTPL_BRCM_HNBU 0x80
7828 +
7829 +/* Subtypes of BRCM_HNBU: */
7830 +
7831 +#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */
7832 +#define HNBU_CHIPID 0x01 /* Two 16bit values: PCI vendor & device id */
7833 +#define HNBU_BOARDREV 0x02 /* One byte board revision */
7834 +#define HNBU_PAPARMS 0x03 /* PA parameters: 8 (sromrev == 1)
7835 + * or 9 (sromrev > 1) bytes
7836 + */
7837 +#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */
7838 +#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */
7839 +#define HNBU_AA 0x06 /* Antennas available */
7840 +#define HNBU_AG 0x07 /* Antenna gain */
7841 +#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */
7842 +#define HNBU_LEDS 0x09 /* LED set */
7843 +#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl)
7844 + * in rev 2
7845 + */
7846 +#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
7847 +#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
7848 +#define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */
7849 +
7850 +
7851 +/* sbtmstatelow */
7852 +#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
7853 +#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
7854 +
7855 +/* sbtmstatehigh */
7856 +#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
7857 +
7858 +#endif /* _SBPCMCIA_H */
7859 diff -urN linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
7860 --- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
7861 +++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2006-04-27 20:36:08.000000000 +0200
7862 @@ -0,0 +1,85 @@
7863 +/*
7864 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
7865 + *
7866 + * Copyright 2006, Broadcom Corporation
7867 + * All Rights Reserved.
7868 + *
7869 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7870 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7871 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7872 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7873 + *
7874 + * $Id: sbsdram.h,v 1.1.1.9 2006/03/02 13:03:52 honor Exp $
7875 + */
7876 +
7877 +#ifndef _SBSDRAM_H
7878 +#define _SBSDRAM_H
7879 +
7880 +#ifndef _LANGUAGE_ASSEMBLY
7881 +
7882 +/* Sonics side: SDRAM core registers */
7883 +typedef volatile struct sbsdramregs {
7884 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
7885 + uint32 config; /* Initializes external SDRAM mode register */
7886 + uint32 refresh; /* Controls external SDRAM refresh rate */
7887 + uint32 pad1;
7888 + uint32 pad2;
7889 +} sbsdramregs_t;
7890 +
7891 +/* SDRAM simulation */
7892 +#ifdef RAMSZ
7893 +#define SDRAMSZ RAMSZ
7894 +#else
7895 +#define SDRAMSZ (4 * 1024 * 1024)
7896 +#endif
7897 +
7898 +extern uchar sdrambuf[SDRAMSZ];
7899 +
7900 +#endif /* _LANGUAGE_ASSEMBLY */
7901 +
7902 +/* SDRAM initialization control (initcontrol) register bits */
7903 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
7904 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
7905 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
7906 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
7907 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
7908 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
7909 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
7910 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
7911 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
7912 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
7913 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
7914 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
7915 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
7916 +
7917 +/* SDRAM configuration (config) register bits */
7918 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
7919 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
7920 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
7921 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
7922 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
7923 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
7924 +
7925 +/* SDRAM refresh control (refresh) register bits */
7926 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
7927 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
7928 +
7929 +/* SDRAM Core default Init values (OCP ID 0x803) */
7930 +#define SDRAM_INIT MEM4MX16X2
7931 +#define SDRAM_CONFIG SDRAM_BURSTFULL
7932 +#define SDRAM_REFRESH SDRAM_REF(0x40)
7933 +
7934 +#define MEM1MX16 0x009 /* 2 MB */
7935 +#define MEM1MX16X2 0x409 /* 4 MB */
7936 +#define MEM2MX8X2 0x809 /* 4 MB */
7937 +#define MEM2MX8X4 0xc09 /* 8 MB */
7938 +#define MEM2MX32 0x439 /* 8 MB */
7939 +#define MEM4MX16 0x019 /* 8 MB */
7940 +#define MEM4MX16X2 0x419 /* 16 MB */
7941 +#define MEM8MX8X2 0x819 /* 16 MB */
7942 +#define MEM8MX16 0x829 /* 16 MB */
7943 +#define MEM4MX32 0x429 /* 16 MB */
7944 +#define MEM8MX8X4 0xc19 /* 32 MB */
7945 +#define MEM8MX16X2 0xc29 /* 32 MB */
7946 +
7947 +#endif /* _SBSDRAM_H */
7948 diff -urN linux.old/arch/mips/bcm947xx/include/sbsocram.h linux.dev/arch/mips/bcm947xx/include/sbsocram.h
7949 --- linux.old/arch/mips/bcm947xx/include/sbsocram.h 1970-01-01 01:00:00.000000000 +0100
7950 +++ linux.dev/arch/mips/bcm947xx/include/sbsocram.h 2006-04-27 22:13:19.000000000 +0200
7951 @@ -0,0 +1,64 @@
7952 +/*
7953 + * BCM47XX Sonics SiliconBackplane embedded ram core
7954 + *
7955 + * Copyright 2006, Broadcom Corporation
7956 + * All Rights Reserved.
7957 + *
7958 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7959 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7960 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7961 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7962 + *
7963 + * $Id: sbsocram.h,v 1.1.1.3 2006/02/27 03:43:16 honor Exp $
7964 + */
7965 +
7966 +#ifndef _SBSOCRAM_H
7967 +#define _SBSOCRAM_H
7968 +
7969 +#define SR_COREINFO 0x00
7970 +#define SR_BWALLOC 0x04
7971 +#define SR_BISTSTAT 0x0c
7972 +#define SR_BANKINDEX 0x10
7973 +#define SR_BANKSTBYCTL 0x14
7974 +
7975 +
7976 +#ifndef _LANGUAGE_ASSEMBLY
7977 +
7978 +/* Memcsocram core registers */
7979 +typedef volatile struct sbsocramregs {
7980 + uint32 coreinfo;
7981 + uint32 bwalloc;
7982 + uint32 PAD;
7983 + uint32 biststat;
7984 + uint32 bankidx;
7985 + uint32 standbyctrl;
7986 +} sbsocramregs_t;
7987 +
7988 +#endif
7989 +
7990 +/* Coreinfo register */
7991 +#define SRCI_PT_MASK 0x30000
7992 +#define SRCI_PT_SHIFT 16
7993 +
7994 +/* In corerev 0, the memory size is 2 to the power of the
7995 + * base plus 16 plus to the contents of the memsize field plus 1.
7996 + */
7997 +#define SRCI_MS0_MASK 0xf
7998 +#define SR_MS0_BASE 16
7999 +
8000 +/*
8001 + * In corerev 1 the bank size is 2 ^ the bank size field plus 14,
8002 + * the memory size is number of banks times bank size.
8003 + * The same applies to rom size.
8004 + */
8005 +#define SRCI_ROMNB_MASK 0xf000
8006 +#define SRCI_ROMNB_SHIFT 12
8007 +#define SRCI_ROMBSZ_MASK 0xf00
8008 +#define SRCI_ROMBSZ_SHIFT 8
8009 +#define SRCI_SRNB_MASK 0xf0
8010 +#define SRCI_SRNB_SHIFT 4
8011 +#define SRCI_SRBSZ_MASK 0xf
8012 +#define SRCI_SRBSZ_SHIFT 0
8013 +
8014 +#define SR_BSZ_BASE 14
8015 +#endif /* _SBSOCRAM_H */
8016 diff -urN linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
8017 --- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
8018 +++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2006-04-27 23:09:25.000000000 +0200
8019 @@ -0,0 +1,150 @@
8020 +/*
8021 + * Misc utility routines for accessing chip-specific features
8022 + * of Broadcom HNBU SiliconBackplane-based chips.
8023 + *
8024 + * Copyright 2006, Broadcom Corporation
8025 + * All Rights Reserved.
8026 + *
8027 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8028 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8029 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8030 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8031 + *
8032 + * $Id: sbutils.h,v 1.4 2006/04/08 07:12:42 honor Exp $
8033 + */
8034 +
8035 +#ifndef _sbutils_h_
8036 +#define _sbutils_h_
8037 +
8038 +/*
8039 + * Datastructure to export all chip specific common variables
8040 + * public (read-only) portion of sbutils handle returned by
8041 + * sb_attach()/sb_kattach()
8042 +*/
8043 +
8044 +struct sb_pub {
8045 +
8046 + uint bustype; /* SB_BUS, PCI_BUS */
8047 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE */
8048 + uint buscorerev; /* buscore rev */
8049 + uint buscoreidx; /* buscore index */
8050 + int ccrev; /* chip common core rev */
8051 + uint boardtype; /* board type */
8052 + uint boardvendor; /* board vendor */
8053 + uint chip; /* chip number */
8054 + uint chiprev; /* chip revision */
8055 + uint chippkg; /* chip package option */
8056 + uint sonicsrev; /* sonics backplane rev */
8057 +};
8058 +
8059 +typedef const struct sb_pub sb_t;
8060 +
8061 +/*
8062 + * Many of the routines below take an 'sbh' handle as their first arg.
8063 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
8064 + * At any one time, the sbh is logically focused on one particular sb core
8065 + * (the "current core").
8066 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
8067 + */
8068 +
8069 +#define SB_OSH NULL /* Use for sb_kattach when no osh is available */
8070 +/* exported externs */
8071 +extern sb_t *sb_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
8072 + void *sdh, char **vars, uint *varsz);
8073 +extern sb_t *sb_kattach(void);
8074 +extern void sb_detach(sb_t *sbh);
8075 +extern uint sb_chip(sb_t *sbh);
8076 +extern uint sb_chiprev(sb_t *sbh);
8077 +extern uint sb_chipcrev(sb_t *sbh);
8078 +extern uint sb_chippkg(sb_t *sbh);
8079 +extern uint sb_pcirev(sb_t *sbh);
8080 +extern bool sb_war16165(sb_t *sbh);
8081 +extern uint sb_pcmciarev(sb_t *sbh);
8082 +extern uint sb_boardvendor(sb_t *sbh);
8083 +extern uint sb_boardtype(sb_t *sbh);
8084 +extern uint sb_bus(sb_t *sbh);
8085 +extern uint sb_buscoretype(sb_t *sbh);
8086 +extern uint sb_buscorerev(sb_t *sbh);
8087 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
8088 +extern uint sb_coreid(sb_t *sbh);
8089 +extern uint sb_coreidx(sb_t *sbh);
8090 +extern uint sb_coreunit(sb_t *sbh);
8091 +extern uint sb_corevendor(sb_t *sbh);
8092 +extern uint sb_corerev(sb_t *sbh);
8093 +extern void *sb_osh(sb_t *sbh);
8094 +extern void sb_setosh(sb_t *sbh, osl_t *osh);
8095 +extern void *sb_coreregs(sb_t *sbh);
8096 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
8097 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
8098 +extern bool sb_iscoreup(sb_t *sbh);
8099 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
8100 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
8101 +extern int sb_corebist(sb_t *sbh);
8102 +extern void sb_commit(sb_t *sbh);
8103 +extern uint32 sb_base(uint32 admatch);
8104 +extern uint32 sb_size(uint32 admatch);
8105 +extern void sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits);
8106 +extern void sb_core_tofixup(sb_t *sbh);
8107 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
8108 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
8109 +extern uint32 sb_clock(sb_t *sbh);
8110 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
8111 +extern void sb_pcmcia_init(sb_t *sbh);
8112 +extern void sb_watchdog(sb_t *sbh, uint ticks);
8113 +extern void *sb_gpiosetcore(sb_t *sbh);
8114 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8115 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8116 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8117 +extern uint32 sb_gpioin(sb_t *sbh);
8118 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8119 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8120 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
8121 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
8122 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
8123 +
8124 +extern void sb_clkctl_init(sb_t *sbh);
8125 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
8126 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
8127 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
8128 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
8129 + void *intrsenabled_fn, void *intr_arg);
8130 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
8131 +extern int sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
8132 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
8133 + uint8 *pciheader);
8134 +extern uint sb_pcie_readreg(void *sbh, void* arg1, uint offset);
8135 +extern uint sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val);
8136 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
8137 +extern bool sb_backplane64(sb_t *sbh);
8138 +extern void sb_btcgpiowar(sb_t *sbh);
8139 +
8140 +
8141 +
8142 +
8143 +extern bool sb_deviceremoved(sb_t *sbh);
8144 +extern uint32 sb_socram_size(sb_t *sbh);
8145 +
8146 +/*
8147 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
8148 +* The returned path is NULL terminated and has trailing '/'.
8149 +* Return 0 on success, nonzero otherwise.
8150 +*/
8151 +extern int sb_devpath(sb_t *sbh, char *path, int size);
8152 +
8153 +/* clkctl xtal what flags */
8154 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
8155 +#define PLL 0x2 /* main chip pll */
8156 +
8157 +/* clkctl clk mode */
8158 +#define CLK_FAST 0 /* force fast (pll) clock */
8159 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
8160 +
8161 +
8162 +/* GPIO usage priorities */
8163 +#define GPIO_DRV_PRIORITY 0 /* Driver */
8164 +#define GPIO_APP_PRIORITY 1 /* Application */
8165 +
8166 +/* device path */
8167 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
8168 +
8169 +#endif /* _sbutils_h_ */
8170 diff -urN linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
8171 --- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
8172 +++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2006-04-27 22:13:51.000000000 +0200
8173 @@ -0,0 +1,36 @@
8174 +/*
8175 + * Broadcom SiliconBackplane chipcommon serial flash interface
8176 + *
8177 + * Copyright 2006, Broadcom Corporation
8178 + * All Rights Reserved.
8179 + *
8180 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8181 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8182 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8183 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8184 + *
8185 + * $Id: sflash.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
8186 + */
8187 +
8188 +#ifndef _sflash_h_
8189 +#define _sflash_h_
8190 +
8191 +#include <typedefs.h>
8192 +#include <sbchipc.h>
8193 +
8194 +struct sflash {
8195 + uint blocksize; /* Block size */
8196 + uint numblocks; /* Number of blocks */
8197 + uint32 type; /* Type */
8198 + uint size; /* Total size in bytes */
8199 +};
8200 +
8201 +/* Utility functions */
8202 +extern int sflash_poll(chipcregs_t *cc, uint offset);
8203 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
8204 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8205 +extern int sflash_erase(chipcregs_t *cc, uint offset);
8206 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8207 +extern struct sflash * sflash_init(chipcregs_t *cc);
8208 +
8209 +#endif /* _sflash_h_ */
8210 diff -urN linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
8211 --- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
8212 +++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2006-04-27 19:24:19.000000000 +0200
8213 @@ -0,0 +1,33 @@
8214 +/*
8215 + * TRX image file header format.
8216 + *
8217 + * Copyright 2005, Broadcom Corporation
8218 + * All Rights Reserved.
8219 + *
8220 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8221 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8222 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8223 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8224 + *
8225 + * $Id$
8226 + */
8227 +
8228 +#include <typedefs.h>
8229 +
8230 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
8231 +#define TRX_VERSION 1
8232 +#define TRX_MAX_LEN 0x3A0000
8233 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
8234 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
8235 +#define TRX_MAX_OFFSET 3
8236 +
8237 +struct trx_header {
8238 + uint32 magic; /* "HDR0" */
8239 + uint32 len; /* Length of file including header */
8240 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
8241 + uint32 flag_version; /* 0:15 flags, 16:31 version */
8242 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
8243 +};
8244 +
8245 +/* Compatibility */
8246 +typedef struct trx_header TRXHDR, *PTRXHDR;
8247 diff -urN linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
8248 --- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
8249 +++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2006-04-27 23:47:30.000000000 +0200
8250 @@ -0,0 +1,361 @@
8251 +/*
8252 + * Copyright 2006, Broadcom Corporation
8253 + * All Rights Reserved.
8254 + *
8255 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8256 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8257 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8258 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8259 + * $Id: typedefs.h,v 1.1.1.12 2006/04/08 06:13:40 honor Exp $
8260 + */
8261 +
8262 +#ifndef _TYPEDEFS_H_
8263 +#define _TYPEDEFS_H_
8264 +
8265 +
8266 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
8267 + * typedef file "site_typedefs.h".
8268 + *
8269 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
8270 + * section of this file makes inferences about the compile environment
8271 + * based on defined symbols and possibly compiler pragmas.
8272 + *
8273 + * Following these two sections is the "Default Typedefs"
8274 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
8275 + * defined. This section has a default set of typedefs and a few
8276 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
8277 + */
8278 +
8279 +#ifdef SITE_TYPEDEFS
8280 +
8281 +/*
8282 + * Site Specific Typedefs
8283 + *
8284 + */
8285 +
8286 +#include "site_typedefs.h"
8287 +
8288 +#else
8289 +
8290 +/*
8291 + * Inferred Typedefs
8292 + *
8293 + */
8294 +
8295 +/* Infer the compile environment based on preprocessor symbols and pramas.
8296 + * Override type definitions as needed, and include configuration dependent
8297 + * header files to define types.
8298 + */
8299 +
8300 +#ifdef __cplusplus
8301 +
8302 +#define TYPEDEF_BOOL
8303 +#ifndef FALSE
8304 +#define FALSE false
8305 +#endif
8306 +#ifndef TRUE
8307 +#define TRUE true
8308 +#endif
8309 +
8310 +#else /* ! __cplusplus */
8311 +
8312 +#if defined(_WIN32)
8313 +
8314 +#define TYPEDEF_BOOL
8315 +typedef unsigned char bool; /* consistent w/BOOL */
8316 +
8317 +#endif /* _WIN32 */
8318 +
8319 +#endif /* ! __cplusplus */
8320 +
8321 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
8322 +#if defined(_WIN64)
8323 +#include <basetsd.h>
8324 +#define TYPEDEF_UINTPTR
8325 +typedef ULONG_PTR uintptr;
8326 +#endif
8327 +
8328 +
8329 +#if defined(_MINOSL_)
8330 +#define _NEED_SIZE_T_
8331 +#endif
8332 +
8333 +#if defined(_NEED_SIZE_T_)
8334 +typedef long unsigned int size_t;
8335 +#endif
8336 +
8337 +#ifdef __DJGPP__
8338 +typedef long unsigned int size_t;
8339 +#endif /* __DJGPP__ */
8340 +
8341 +#ifdef _MSC_VER /* Microsoft C */
8342 +#define TYPEDEF_INT64
8343 +#define TYPEDEF_UINT64
8344 +typedef signed __int64 int64;
8345 +typedef unsigned __int64 uint64;
8346 +#endif
8347 +
8348 +#if defined(MACOSX)
8349 +#define TYPEDEF_BOOL
8350 +#endif
8351 +
8352 +#if defined(__NetBSD__)
8353 +#define TYPEDEF_ULONG
8354 +#endif
8355 +
8356 +
8357 +#if defined(linux)
8358 +#define TYPEDEF_UINT
8359 +#define TYPEDEF_USHORT
8360 +#define TYPEDEF_ULONG
8361 +#endif
8362 +
8363 +#if !defined(linux) && !defined(_WIN32) && !defined(_CFE_) && \
8364 + !defined(_HNDRTE_) && !defined(_MINOSL_) && !defined(__DJGPP__)
8365 +#define TYPEDEF_UINT
8366 +#define TYPEDEF_USHORT
8367 +#endif
8368 +
8369 +
8370 +/* Do not support the (u)int64 types with strict ansi for GNU C */
8371 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
8372 +#define TYPEDEF_INT64
8373 +#define TYPEDEF_UINT64
8374 +#endif
8375 +
8376 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
8377 + * for singned or unsigned
8378 + */
8379 +#if defined(__ICL)
8380 +
8381 +#define TYPEDEF_INT64
8382 +
8383 +#if defined(__STDC__)
8384 +#define TYPEDEF_UINT64
8385 +#endif
8386 +
8387 +#endif /* __ICL */
8388 +
8389 +#if !defined(_WIN32) && !defined(_CFE_) && !defined(_MINOSL_) && \
8390 + !defined(__DJGPP__)
8391 +
8392 +/* pick up ushort & uint from standard types.h */
8393 +#if defined(linux) && defined(__KERNEL__)
8394 +
8395 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
8396 +
8397 +#else
8398 +
8399 +#include <sys/types.h>
8400 +
8401 +#endif
8402 +
8403 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ && !__DJGPP__ */
8404 +
8405 +#if defined(MACOSX)
8406 +
8407 +#ifdef __BIG_ENDIAN__
8408 +#define IL_BIGENDIAN
8409 +#else
8410 +#ifdef IL_BIGENDIAN
8411 +#error "IL_BIGENDIAN was defined for a little-endian compile"
8412 +#endif
8413 +#endif /* __BIG_ENDIAN__ */
8414 +
8415 +#if !defined(__cplusplus)
8416 +
8417 +#if defined(__i386__)
8418 +typedef unsigned char bool;
8419 +#else
8420 +typedef unsigned int bool;
8421 +#endif
8422 +#define TYPE_BOOL 1
8423 +enum {
8424 + false = 0,
8425 + true = 1
8426 +};
8427 +
8428 +#if defined(KERNEL)
8429 +#include <IOKit/IOTypes.h>
8430 +#endif /* KERNEL */
8431 +
8432 +#endif /* __cplusplus */
8433 +
8434 +#endif /* MACOSX */
8435 +
8436 +
8437 +/* use the default typedefs in the next section of this file */
8438 +#define USE_TYPEDEF_DEFAULTS
8439 +
8440 +#endif /* SITE_TYPEDEFS */
8441 +
8442 +
8443 +/*
8444 + * Default Typedefs
8445 + *
8446 + */
8447 +
8448 +#ifdef USE_TYPEDEF_DEFAULTS
8449 +#undef USE_TYPEDEF_DEFAULTS
8450 +
8451 +#ifndef TYPEDEF_BOOL
8452 +typedef /* @abstract@ */ unsigned char bool;
8453 +#endif
8454 +
8455 +/* define uchar, ushort, uint, ulong */
8456 +
8457 +#ifndef TYPEDEF_UCHAR
8458 +typedef unsigned char uchar;
8459 +#endif
8460 +
8461 +#ifndef TYPEDEF_USHORT
8462 +typedef unsigned short ushort;
8463 +#endif
8464 +
8465 +#ifndef TYPEDEF_UINT
8466 +typedef unsigned int uint;
8467 +#endif
8468 +
8469 +#ifndef TYPEDEF_ULONG
8470 +typedef unsigned long ulong;
8471 +#endif
8472 +
8473 +/* define [u]int8/16/32/64, uintptr */
8474 +
8475 +#ifndef TYPEDEF_UINT8
8476 +typedef unsigned char uint8;
8477 +#endif
8478 +
8479 +#ifndef TYPEDEF_UINT16
8480 +typedef unsigned short uint16;
8481 +#endif
8482 +
8483 +#ifndef TYPEDEF_UINT32
8484 +typedef unsigned int uint32;
8485 +#endif
8486 +
8487 +#ifndef TYPEDEF_UINT64
8488 +typedef unsigned long long uint64;
8489 +#endif
8490 +
8491 +#ifndef TYPEDEF_UINTPTR
8492 +typedef unsigned int uintptr;
8493 +#endif
8494 +
8495 +#ifndef TYPEDEF_INT8
8496 +typedef signed char int8;
8497 +#endif
8498 +
8499 +#ifndef TYPEDEF_INT16
8500 +typedef signed short int16;
8501 +#endif
8502 +
8503 +#ifndef TYPEDEF_INT32
8504 +typedef signed int int32;
8505 +#endif
8506 +
8507 +#ifndef TYPEDEF_INT64
8508 +typedef signed long long int64;
8509 +#endif
8510 +
8511 +/* define float32/64, float_t */
8512 +
8513 +#ifndef TYPEDEF_FLOAT32
8514 +typedef float float32;
8515 +#endif
8516 +
8517 +#ifndef TYPEDEF_FLOAT64
8518 +typedef double float64;
8519 +#endif
8520 +
8521 +/*
8522 + * abstracted floating point type allows for compile time selection of
8523 + * single or double precision arithmetic. Compiling with -DFLOAT32
8524 + * selects single precision; the default is double precision.
8525 + */
8526 +
8527 +#ifndef TYPEDEF_FLOAT_T
8528 +
8529 +#if defined(FLOAT32)
8530 +typedef float32 float_t;
8531 +#else /* default to double precision floating point */
8532 +typedef float64 float_t;
8533 +#endif
8534 +
8535 +#endif /* TYPEDEF_FLOAT_T */
8536 +
8537 +/* define macro values */
8538 +
8539 +#ifndef FALSE
8540 +#define FALSE 0
8541 +#endif
8542 +
8543 +#ifndef TRUE
8544 +#define TRUE 1 /* TRUE */
8545 +#endif
8546 +
8547 +#ifndef NULL
8548 +#define NULL 0
8549 +#endif
8550 +
8551 +#ifndef OFF
8552 +#define OFF 0
8553 +#endif
8554 +
8555 +#ifndef ON
8556 +#define ON 1 /* ON = 1 */
8557 +#endif
8558 +
8559 +#define AUTO (-1) /* Auto = -1 */
8560 +
8561 +/* define PTRSZ, INLINE */
8562 +
8563 +#ifndef PTRSZ
8564 +#define PTRSZ sizeof(char*)
8565 +#endif
8566 +
8567 +#ifndef INLINE
8568 +
8569 +#ifdef _MSC_VER
8570 +
8571 +#define INLINE __inline
8572 +
8573 +#elif __GNUC__
8574 +
8575 +#define INLINE __inline__
8576 +
8577 +#else
8578 +
8579 +#define INLINE
8580 +
8581 +#endif /* _MSC_VER */
8582 +
8583 +#endif /* INLINE */
8584 +
8585 +#undef TYPEDEF_BOOL
8586 +#undef TYPEDEF_UCHAR
8587 +#undef TYPEDEF_USHORT
8588 +#undef TYPEDEF_UINT
8589 +#undef TYPEDEF_ULONG
8590 +#undef TYPEDEF_UINT8
8591 +#undef TYPEDEF_UINT16
8592 +#undef TYPEDEF_UINT32
8593 +#undef TYPEDEF_UINT64
8594 +#undef TYPEDEF_UINTPTR
8595 +#undef TYPEDEF_INT8
8596 +#undef TYPEDEF_INT16
8597 +#undef TYPEDEF_INT32
8598 +#undef TYPEDEF_INT64
8599 +#undef TYPEDEF_FLOAT32
8600 +#undef TYPEDEF_FLOAT64
8601 +#undef TYPEDEF_FLOAT_T
8602 +
8603 +#endif /* USE_TYPEDEF_DEFAULTS */
8604 +
8605 +/*
8606 + * Including the bcmdefs.h here, to make sure everyone including typedefs.h
8607 + * gets this automatically
8608 +*/
8609 +#include "bcmdefs.h"
8610 +
8611 +#endif /* _TYPEDEFS_H_ */
8612 diff -urN linux.old/arch/mips/bcm947xx/nvram.c linux.dev/arch/mips/bcm947xx/nvram.c
8613 --- linux.old/arch/mips/bcm947xx/nvram.c 1970-01-01 01:00:00.000000000 +0100
8614 +++ linux.dev/arch/mips/bcm947xx/nvram.c 2006-04-27 23:11:58.000000000 +0200
8615 @@ -0,0 +1,315 @@
8616 +/*
8617 + * NVRAM variable manipulation (common)
8618 + *
8619 + * Copyright 2004, Broadcom Corporation
8620 + * All Rights Reserved.
8621 + *
8622 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8623 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8624 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8625 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8626 + *
8627 + */
8628 +
8629 +#include <typedefs.h>
8630 +#include <osl.h>
8631 +#include <bcmendian.h>
8632 +#include <bcmnvram.h>
8633 +#include <bcmutils.h>
8634 +#include <sbsdram.h>
8635 +
8636 +extern struct nvram_tuple * BCMINIT(_nvram_realloc)(struct nvram_tuple *t, const char *name, const char *value);
8637 +extern void BCMINIT(_nvram_free)(struct nvram_tuple *t);
8638 +extern int BCMINIT(_nvram_read)(void *buf);
8639 +
8640 +char * BCMINIT(_nvram_get)(const char *name);
8641 +int BCMINIT(_nvram_set)(const char *name, const char *value);
8642 +int BCMINIT(_nvram_unset)(const char *name);
8643 +int BCMINIT(_nvram_getall)(char *buf, int count);
8644 +int BCMINIT(_nvram_commit)(struct nvram_header *header);
8645 +int BCMINIT(_nvram_init)(void);
8646 +void BCMINIT(_nvram_exit)(void);
8647 +
8648 +static struct nvram_tuple * BCMINITDATA(nvram_hash)[257];
8649 +static struct nvram_tuple * nvram_dead;
8650 +
8651 +/* Free all tuples. Should be locked. */
8652 +static void
8653 +BCMINITFN(nvram_free)(void)
8654 +{
8655 + uint i;
8656 + struct nvram_tuple *t, *next;
8657 +
8658 + /* Free hash table */
8659 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8660 + for (t = BCMINIT(nvram_hash)[i]; t; t = next) {
8661 + next = t->next;
8662 + BCMINIT(_nvram_free)(t);
8663 + }
8664 + BCMINIT(nvram_hash)[i] = NULL;
8665 + }
8666 +
8667 + /* Free dead table */
8668 + for (t = nvram_dead; t; t = next) {
8669 + next = t->next;
8670 + BCMINIT(_nvram_free)(t);
8671 + }
8672 + nvram_dead = NULL;
8673 +
8674 + /* Indicate to per-port code that all tuples have been freed */
8675 + BCMINIT(_nvram_free)(NULL);
8676 +}
8677 +
8678 +/* String hash */
8679 +static INLINE uint
8680 +hash(const char *s)
8681 +{
8682 + uint hash = 0;
8683 +
8684 + while (*s)
8685 + hash = 31 * hash + *s++;
8686 +
8687 + return hash;
8688 +}
8689 +
8690 +/* (Re)initialize the hash table. Should be locked. */
8691 +static int
8692 +BCMINITFN(nvram_rehash)(struct nvram_header *header)
8693 +{
8694 + char buf[] = "0xXXXXXXXX", *name, *value, *end, *eq;
8695 +
8696 + /* (Re)initialize hash table */
8697 + BCMINIT(nvram_free)();
8698 +
8699 + /* Parse and set "name=value\0 ... \0\0" */
8700 + name = (char *) &header[1];
8701 + end = (char *) header + NVRAM_SPACE - 2;
8702 + end[0] = end[1] = '\0';
8703 + for (; *name; name = value + strlen(value) + 1) {
8704 + if (!(eq = strchr(name, '=')))
8705 + break;
8706 + *eq = '\0';
8707 + value = eq + 1;
8708 + BCMINIT(_nvram_set)(name, value);
8709 + *eq = '=';
8710 + }
8711 +
8712 + /* Set special SDRAM parameters */
8713 + if (!BCMINIT(_nvram_get)("sdram_init")) {
8714 + sprintf(buf, "0x%04X", (uint16)(header->crc_ver_init >> 16));
8715 + BCMINIT(_nvram_set)("sdram_init", buf);
8716 + }
8717 + if (!BCMINIT(_nvram_get)("sdram_config")) {
8718 + sprintf(buf, "0x%04X", (uint16)(header->config_refresh & 0xffff));
8719 + BCMINIT(_nvram_set)("sdram_config", buf);
8720 + }
8721 + if (!BCMINIT(_nvram_get)("sdram_refresh")) {
8722 + sprintf(buf, "0x%04X", (uint16)((header->config_refresh >> 16) & 0xffff));
8723 + BCMINIT(_nvram_set)("sdram_refresh", buf);
8724 + }
8725 + if (!BCMINIT(_nvram_get)("sdram_ncdl")) {
8726 + sprintf(buf, "0x%08X", header->config_ncdl);
8727 + BCMINIT(_nvram_set)("sdram_ncdl", buf);
8728 + }
8729 +
8730 + return 0;
8731 +}
8732 +
8733 +/* Get the value of an NVRAM variable. Should be locked. */
8734 +char *
8735 +BCMINITFN(_nvram_get)(const char *name)
8736 +{
8737 + uint i;
8738 + struct nvram_tuple *t;
8739 + char *value;
8740 +
8741 + if (!name)
8742 + return NULL;
8743 +
8744 + /* Hash the name */
8745 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8746 +
8747 + /* Find the associated tuple in the hash table */
8748 + for (t = BCMINIT(nvram_hash)[i]; t && strcmp(t->name, name); t = t->next);
8749 +
8750 + value = t ? t->value : NULL;
8751 +
8752 + return value;
8753 +}
8754 +
8755 +/* Get the value of an NVRAM variable. Should be locked. */
8756 +int
8757 +BCMINITFN(_nvram_set)(const char *name, const char *value)
8758 +{
8759 + uint i;
8760 + struct nvram_tuple *t, *u, **prev;
8761 +
8762 + /* Hash the name */
8763 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8764 +
8765 + /* Find the associated tuple in the hash table */
8766 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
8767 +
8768 + /* (Re)allocate tuple */
8769 + if (!(u = BCMINIT(_nvram_realloc)(t, name, value)))
8770 + return -12; /* -ENOMEM */
8771 +
8772 + /* Value reallocated */
8773 + if (t && t == u)
8774 + return 0;
8775 +
8776 + /* Move old tuple to the dead table */
8777 + if (t) {
8778 + *prev = t->next;
8779 + t->next = nvram_dead;
8780 + nvram_dead = t;
8781 + }
8782 +
8783 + /* Add new tuple to the hash table */
8784 + u->next = BCMINIT(nvram_hash)[i];
8785 + BCMINIT(nvram_hash)[i] = u;
8786 +
8787 + return 0;
8788 +}
8789 +
8790 +/* Unset the value of an NVRAM variable. Should be locked. */
8791 +int
8792 +BCMINITFN(_nvram_unset)(const char *name)
8793 +{
8794 + uint i;
8795 + struct nvram_tuple *t, **prev;
8796 +
8797 + if (!name)
8798 + return 0;
8799 +
8800 + /* Hash the name */
8801 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8802 +
8803 + /* Find the associated tuple in the hash table */
8804 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
8805 +
8806 + /* Move it to the dead table */
8807 + if (t) {
8808 + *prev = t->next;
8809 + t->next = nvram_dead;
8810 + nvram_dead = t;
8811 + }
8812 +
8813 + return 0;
8814 +}
8815 +
8816 +/* Get all NVRAM variables. Should be locked. */
8817 +int
8818 +BCMINITFN(_nvram_getall)(char *buf, int count)
8819 +{
8820 + uint i;
8821 + struct nvram_tuple *t;
8822 + int len = 0;
8823 +
8824 + bzero(buf, count);
8825 +
8826 + /* Write name=value\0 ... \0\0 */
8827 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8828 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
8829 + if ((count - len) > (strlen(t->name) + 1 + strlen(t->value) + 1))
8830 + len += sprintf(buf + len, "%s=%s", t->name, t->value) + 1;
8831 + else
8832 + break;
8833 + }
8834 + }
8835 +
8836 + return 0;
8837 +}
8838 +
8839 +/* Regenerate NVRAM. Should be locked. */
8840 +int
8841 +BCMINITFN(_nvram_commit)(struct nvram_header *header)
8842 +{
8843 + char *init, *config, *refresh, *ncdl;
8844 + char *ptr, *end;
8845 + int i;
8846 + struct nvram_tuple *t;
8847 + struct nvram_header tmp;
8848 + uint8 crc;
8849 +
8850 + /* Regenerate header */
8851 + header->magic = NVRAM_MAGIC;
8852 + header->crc_ver_init = (NVRAM_VERSION << 8);
8853 + if (!(init = BCMINIT(_nvram_get)("sdram_init")) ||
8854 + !(config = BCMINIT(_nvram_get)("sdram_config")) ||
8855 + !(refresh = BCMINIT(_nvram_get)("sdram_refresh")) ||
8856 + !(ncdl = BCMINIT(_nvram_get)("sdram_ncdl"))) {
8857 + header->crc_ver_init |= SDRAM_INIT << 16;
8858 + header->config_refresh = SDRAM_CONFIG;
8859 + header->config_refresh |= SDRAM_REFRESH << 16;
8860 + header->config_ncdl = 0;
8861 + } else {
8862 + header->crc_ver_init |= (bcm_strtoul(init, NULL, 0) & 0xffff) << 16;
8863 + header->config_refresh = bcm_strtoul(config, NULL, 0) & 0xffff;
8864 + header->config_refresh |= (bcm_strtoul(refresh, NULL, 0) & 0xffff) << 16;
8865 + header->config_ncdl = bcm_strtoul(ncdl, NULL, 0);
8866 + }
8867 +
8868 + /* Clear data area */
8869 + ptr = (char *) header + sizeof(struct nvram_header);
8870 + bzero(ptr, NVRAM_SPACE - sizeof(struct nvram_header));
8871 +
8872 + /* Leave space for a double NUL at the end */
8873 + end = (char *) header + NVRAM_SPACE - 2;
8874 +
8875 + /* Write out all tuples */
8876 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8877 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
8878 + if ((ptr + strlen(t->name) + 1 + strlen(t->value) + 1) > end)
8879 + break;
8880 + ptr += sprintf(ptr, "%s=%s", t->name, t->value) + 1;
8881 + }
8882 + }
8883 +
8884 + /* End with a double NUL */
8885 + ptr += 2;
8886 +
8887 + /* Set new length */
8888 + header->len = ROUNDUP(ptr - (char *) header, 4);
8889 +
8890 + /* Little-endian CRC8 over the last 11 bytes of the header */
8891 + tmp.crc_ver_init = htol32(header->crc_ver_init);
8892 + tmp.config_refresh = htol32(header->config_refresh);
8893 + tmp.config_ncdl = htol32(header->config_ncdl);
8894 + crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, CRC8_INIT_VALUE);
8895 +
8896 + /* Continue CRC8 over data bytes */
8897 + crc = hndcrc8((char *) &header[1], header->len - sizeof(struct nvram_header), crc);
8898 +
8899 + /* Set new CRC8 */
8900 + header->crc_ver_init |= crc;
8901 +
8902 + /* Reinitialize hash table */
8903 + return BCMINIT(nvram_rehash)(header);
8904 +}
8905 +
8906 +/* Initialize hash table. Should be locked. */
8907 +int
8908 +BCMINITFN(_nvram_init)(void)
8909 +{
8910 + struct nvram_header *header;
8911 + int ret;
8912 +
8913 + if (!(header = (struct nvram_header *) kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
8914 + return -12; /* -ENOMEM */
8915 + }
8916 +
8917 + if ((ret = BCMINIT(_nvram_read)(header)) == 0 &&
8918 + header->magic == NVRAM_MAGIC)
8919 + BCMINIT(nvram_rehash)(header);
8920 +
8921 + kfree(header);
8922 + return ret;
8923 +}
8924 +
8925 +/* Free hash table. Should be locked. */
8926 +void
8927 +BCMINITFN(_nvram_exit)(void)
8928 +{
8929 + BCMINIT(nvram_free)();
8930 +}
8931 diff -urN linux.old/arch/mips/bcm947xx/nvram_linux.c linux.dev/arch/mips/bcm947xx/nvram_linux.c
8932 --- linux.old/arch/mips/bcm947xx/nvram_linux.c 1970-01-01 01:00:00.000000000 +0100
8933 +++ linux.dev/arch/mips/bcm947xx/nvram_linux.c 2006-04-27 23:30:07.000000000 +0200
8934 @@ -0,0 +1,723 @@
8935 +/*
8936 + * NVRAM variable manipulation (Linux kernel half)
8937 + *
8938 + * Copyright 2006, Broadcom Corporation
8939 + * All Rights Reserved.
8940 + *
8941 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8942 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8943 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8944 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8945 + *
8946 + * $Id: nvram_linux.c,v 1.19 2006/04/08 07:12:42 honor Exp $
8947 + */
8948 +
8949 +#include <linux/config.h>
8950 +#include <linux/init.h>
8951 +#include <linux/module.h>
8952 +#include <linux/kernel.h>
8953 +#include <linux/string.h>
8954 +#include <linux/interrupt.h>
8955 +#include <linux/spinlock.h>
8956 +#include <linux/slab.h>
8957 +#include <linux/bootmem.h>
8958 +#include <linux/wrapper.h>
8959 +#include <linux/fs.h>
8960 +#include <linux/miscdevice.h>
8961 +#include <linux/mtd/mtd.h>
8962 +#include <asm/addrspace.h>
8963 +#include <asm/io.h>
8964 +#include <asm/uaccess.h>
8965 +
8966 +#include <typedefs.h>
8967 +#include <osl.h>
8968 +#include <bcmendian.h>
8969 +#include <bcmnvram.h>
8970 +#include <bcmutils.h>
8971 +#include <sbconfig.h>
8972 +#include <sbchipc.h>
8973 +#include <sbutils.h>
8974 +#include <hndmips.h>
8975 +#include <sflash.h>
8976 +
8977 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
8978 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
8979 +
8980 +#ifdef MODULE
8981 +
8982 +#define early_nvram_get(name) nvram_get(name)
8983 +
8984 +#else /* !MODULE */
8985 +
8986 +/* Global SB handle */
8987 +extern void *bcm947xx_sbh;
8988 +extern spinlock_t bcm947xx_sbh_lock;
8989 +
8990 +static int cfe_env;
8991 +extern char *cfe_env_get(char *nv_buf, const char *name);
8992 +
8993 +/* Convenience */
8994 +#define sbh bcm947xx_sbh
8995 +#define sbh_lock bcm947xx_sbh_lock
8996 +#define KB * 1024
8997 +#define MB * 1024 * 1024
8998 +
8999 +/* Probe for NVRAM header */
9000 +static void __init
9001 +early_nvram_init(void)
9002 +{
9003 + struct nvram_header *header;
9004 + chipcregs_t *cc;
9005 + struct sflash *info = NULL;
9006 + int i;
9007 + uint32 base, off, lim;
9008 + u32 *src, *dst;
9009 +
9010 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
9011 + base = KSEG1ADDR(SB_FLASH2);
9012 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
9013 + case PFLASH:
9014 + lim = SB_FLASH2_SZ;
9015 + break;
9016 +
9017 + case SFLASH_ST:
9018 + case SFLASH_AT:
9019 + if ((info = sflash_init(cc)) == NULL)
9020 + return;
9021 + lim = info->size;
9022 + break;
9023 +
9024 + case FLASH_NONE:
9025 + default:
9026 + return;
9027 + }
9028 + } else {
9029 + /* extif assumed, Stop at 4 MB */
9030 + base = KSEG1ADDR(SB_FLASH1);
9031 + lim = SB_FLASH1_SZ;
9032 + }
9033 +
9034 + /* XXX: hack for supporting the CFE environment stuff on WGT634U */
9035 + src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
9036 + dst = (u32 *) nvram_buf;
9037 + if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) {
9038 + printk("early_nvram_init: WGT634U NVRAM found.\n");
9039 +
9040 + for (i = 0; i < 0x1ff0; i++) {
9041 + if (*src == 0xFFFFFFFF)
9042 + break;
9043 + *dst++ = *src++;
9044 + }
9045 + cfe_env = 1;
9046 + return;
9047 + }
9048 +
9049 + off = FLASH_MIN;
9050 + while (off <= lim) {
9051 + /* Windowed flash access */
9052 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
9053 + if (header->magic == NVRAM_MAGIC)
9054 + goto found;
9055 + off <<= 1;
9056 + }
9057 +
9058 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
9059 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
9060 + if (header->magic == NVRAM_MAGIC)
9061 + goto found;
9062 +
9063 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
9064 + if (header->magic == NVRAM_MAGIC)
9065 + goto found;
9066 +
9067 + printk("early_nvram_init: NVRAM not found\n");
9068 + return;
9069 +
9070 +found:
9071 + src = (u32 *) header;
9072 + dst = (u32 *) nvram_buf;
9073 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
9074 + *dst++ = *src++;
9075 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
9076 + *dst++ = ltoh32(*src++);
9077 +}
9078 +
9079 +/* Early (before mm or mtd) read-only access to NVRAM */
9080 +static char * __init
9081 +early_nvram_get(const char *name)
9082 +{
9083 + char *var, *value, *end, *eq;
9084 +
9085 + if (!name)
9086 + return NULL;
9087 +
9088 + /* Too early? */
9089 + if (sbh == NULL)
9090 + return NULL;
9091 +
9092 + if (!nvram_buf[0])
9093 + early_nvram_init();
9094 +
9095 + if (cfe_env)
9096 + return cfe_env_get(nvram_buf, name);
9097 +
9098 + /* Look for name=value and return value */
9099 + var = &nvram_buf[sizeof(struct nvram_header)];
9100 + end = nvram_buf + sizeof(nvram_buf) - 2;
9101 + end[0] = end[1] = '\0';
9102 + for (; *var; var = value + strlen(value) + 1) {
9103 + if (!(eq = strchr(var, '=')))
9104 + break;
9105 + value = eq + 1;
9106 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
9107 + return value;
9108 + }
9109 +
9110 + return NULL;
9111 +}
9112 +
9113 +static int __init
9114 +early_nvram_getall(char *buf, int count)
9115 +{
9116 + char *var, *end;
9117 + int len = 0;
9118 +
9119 + /* Too early? */
9120 + if (sbh == NULL)
9121 + return -1;
9122 +
9123 + if (!nvram_buf[0])
9124 + early_nvram_init();
9125 +
9126 + bzero(buf, count);
9127 +
9128 + /* Write name=value\0 ... \0\0 */
9129 + var = &nvram_buf[sizeof(struct nvram_header)];
9130 + end = nvram_buf + sizeof(nvram_buf) - 2;
9131 + end[0] = end[1] = '\0';
9132 + for (; *var; var += strlen(var) + 1) {
9133 + if ((count - len) <= (strlen(var) + 1))
9134 + break;
9135 + len += sprintf(buf + len, "%s", var) + 1;
9136 + }
9137 +
9138 + return 0;
9139 +}
9140 +#endif /* !MODULE */
9141 +
9142 +extern char * _nvram_get(const char *name);
9143 +extern int _nvram_set(const char *name, const char *value);
9144 +extern int _nvram_unset(const char *name);
9145 +extern int _nvram_getall(char *buf, int count);
9146 +extern int _nvram_commit(struct nvram_header *header);
9147 +extern int _nvram_init(void *sbh);
9148 +extern void _nvram_exit(void);
9149 +
9150 +/* Globals */
9151 +static spinlock_t nvram_lock = SPIN_LOCK_UNLOCKED;
9152 +static struct semaphore nvram_sem;
9153 +static unsigned long nvram_offset = 0;
9154 +static int nvram_major = -1;
9155 +static devfs_handle_t nvram_handle = NULL;
9156 +static struct mtd_info *nvram_mtd = NULL;
9157 +
9158 +int
9159 +_nvram_read(char *buf)
9160 +{
9161 + struct nvram_header *header = (struct nvram_header *) buf;
9162 + size_t len;
9163 +
9164 + if (!nvram_mtd ||
9165 + MTD_READ(nvram_mtd, nvram_mtd->size - NVRAM_SPACE, NVRAM_SPACE, &len, buf) ||
9166 + len != NVRAM_SPACE ||
9167 + header->magic != NVRAM_MAGIC) {
9168 + /* Maybe we can recover some data from early initialization */
9169 + memcpy(buf, nvram_buf, NVRAM_SPACE);
9170 + }
9171 +
9172 + return 0;
9173 +}
9174 +
9175 +struct nvram_tuple *
9176 +_nvram_realloc(struct nvram_tuple *t, const char *name, const char *value)
9177 +{
9178 + if ((nvram_offset + strlen(value) + 1) > NVRAM_SPACE)
9179 + return NULL;
9180 +
9181 + if (!t) {
9182 + if (!(t = kmalloc(sizeof(struct nvram_tuple) + strlen(name) + 1, GFP_ATOMIC)))
9183 + return NULL;
9184 +
9185 + /* Copy name */
9186 + t->name = (char *) &t[1];
9187 + strcpy(t->name, name);
9188 +
9189 + t->value = NULL;
9190 + }
9191 +
9192 + /* Copy value */
9193 + if (!t->value || strcmp(t->value, value)) {
9194 + t->value = &nvram_buf[nvram_offset];
9195 + strcpy(t->value, value);
9196 + nvram_offset += strlen(value) + 1;
9197 + }
9198 +
9199 + return t;
9200 +}
9201 +
9202 +void
9203 +_nvram_free(struct nvram_tuple *t)
9204 +{
9205 + if (!t)
9206 + nvram_offset = 0;
9207 + else
9208 + kfree(t);
9209 +}
9210 +
9211 +int
9212 +nvram_set(const char *name, const char *value)
9213 +{
9214 + unsigned long flags;
9215 + int ret;
9216 + struct nvram_header *header;
9217 +
9218 + spin_lock_irqsave(&nvram_lock, flags);
9219 + if ((ret = _nvram_set(name, value))) {
9220 + /* Consolidate space and try again */
9221 + if ((header = kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
9222 + if (_nvram_commit(header) == 0)
9223 + ret = _nvram_set(name, value);
9224 + kfree(header);
9225 + }
9226 + }
9227 + spin_unlock_irqrestore(&nvram_lock, flags);
9228 +
9229 + return ret;
9230 +}
9231 +
9232 +char *
9233 +real_nvram_get(const char *name)
9234 +{
9235 + unsigned long flags;
9236 + char *value;
9237 +
9238 + spin_lock_irqsave(&nvram_lock, flags);
9239 + value = _nvram_get(name);
9240 + spin_unlock_irqrestore(&nvram_lock, flags);
9241 +
9242 + return value;
9243 +}
9244 +
9245 +char *
9246 +nvram_get(const char *name)
9247 +{
9248 + if (nvram_major >= 0)
9249 + return real_nvram_get(name);
9250 + else
9251 + return early_nvram_get(name);
9252 +}
9253 +
9254 +int
9255 +nvram_unset(const char *name)
9256 +{
9257 + unsigned long flags;
9258 + int ret;
9259 +
9260 + spin_lock_irqsave(&nvram_lock, flags);
9261 + ret = _nvram_unset(name);
9262 + spin_unlock_irqrestore(&nvram_lock, flags);
9263 +
9264 + return ret;
9265 +}
9266 +
9267 +static void
9268 +erase_callback(struct erase_info *done)
9269 +{
9270 + wait_queue_head_t *wait_q = (wait_queue_head_t *) done->priv;
9271 + wake_up(wait_q);
9272 +}
9273 +
9274 +int
9275 +nvram_commit(void)
9276 +{
9277 + char *buf;
9278 + size_t erasesize, len, magic_len;
9279 + unsigned int i;
9280 + int ret;
9281 + struct nvram_header *header;
9282 + unsigned long flags;
9283 + u_int32_t offset;
9284 + DECLARE_WAITQUEUE(wait, current);
9285 + wait_queue_head_t wait_q;
9286 + struct erase_info erase;
9287 + u_int32_t magic_offset = 0; /* Offset for writing MAGIC # */
9288 +
9289 + if (!nvram_mtd) {
9290 + printk("nvram_commit: NVRAM not found\n");
9291 + return -ENODEV;
9292 + }
9293 +
9294 + if (in_interrupt()) {
9295 + printk("nvram_commit: not committing in interrupt\n");
9296 + return -EINVAL;
9297 + }
9298 +
9299 + /* Backup sector blocks to be erased */
9300 + erasesize = ROUNDUP(NVRAM_SPACE, nvram_mtd->erasesize);
9301 + if (!(buf = kmalloc(erasesize, GFP_KERNEL))) {
9302 + printk("nvram_commit: out of memory\n");
9303 + return -ENOMEM;
9304 + }
9305 +
9306 + down(&nvram_sem);
9307 +
9308 + if ((i = erasesize - NVRAM_SPACE) > 0) {
9309 + offset = nvram_mtd->size - erasesize;
9310 + len = 0;
9311 + ret = MTD_READ(nvram_mtd, offset, i, &len, buf);
9312 + if (ret || len != i) {
9313 + printk("nvram_commit: read error ret = %d, len = %d/%d\n", ret, len, i);
9314 + ret = -EIO;
9315 + goto done;
9316 + }
9317 + header = (struct nvram_header *)(buf + i);
9318 + magic_offset = i + ((void *)&header->magic - (void *)header);
9319 + } else {
9320 + offset = nvram_mtd->size - NVRAM_SPACE;
9321 + magic_offset = ((void *)&header->magic - (void *)header);
9322 + header = (struct nvram_header *)buf;
9323 + }
9324 +
9325 + /* clear the existing magic # to mark the NVRAM as unusable
9326 + we can pull MAGIC bits low without erase */
9327 + header->magic = NVRAM_CLEAR_MAGIC; /* All zeros magic */
9328 +
9329 + /* Unlock sector blocks (for Intel 28F320C3B flash) , 20060309 */
9330 + if(nvram_mtd->unlock)
9331 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
9332 +
9333 + ret = MTD_WRITE(nvram_mtd, offset + magic_offset, sizeof(header->magic),
9334 + &magic_len, (char *)&header->magic);
9335 + if (ret || magic_len != sizeof(header->magic)) {
9336 + printk("nvram_commit: clear MAGIC error\n");
9337 + ret = -EIO;
9338 + goto done;
9339 + }
9340 +
9341 + header->magic = NVRAM_MAGIC; /* reset MAGIC before we regenerate the NVRAM,
9342 + otherwise we'll have an incorrect CRC */
9343 + /* Regenerate NVRAM */
9344 + spin_lock_irqsave(&nvram_lock, flags);
9345 + ret = _nvram_commit(header);
9346 + spin_unlock_irqrestore(&nvram_lock, flags);
9347 + if (ret)
9348 + goto done;
9349 +
9350 + /* Erase sector blocks */
9351 + init_waitqueue_head(&wait_q);
9352 + for (; offset < nvram_mtd->size - NVRAM_SPACE + header->len; offset += nvram_mtd->erasesize) {
9353 + erase.mtd = nvram_mtd;
9354 + erase.addr = offset;
9355 + erase.len = nvram_mtd->erasesize;
9356 + erase.callback = erase_callback;
9357 + erase.priv = (u_long) &wait_q;
9358 +
9359 + set_current_state(TASK_INTERRUPTIBLE);
9360 + add_wait_queue(&wait_q, &wait);
9361 +
9362 + /* Unlock sector blocks */
9363 + if (nvram_mtd->unlock)
9364 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
9365 +
9366 + if ((ret = MTD_ERASE(nvram_mtd, &erase))) {
9367 + set_current_state(TASK_RUNNING);
9368 + remove_wait_queue(&wait_q, &wait);
9369 + printk("nvram_commit: erase error\n");
9370 + goto done;
9371 + }
9372 +
9373 + /* Wait for erase to finish */
9374 + schedule();
9375 + remove_wait_queue(&wait_q, &wait);
9376 + }
9377 +
9378 + /* Write partition up to end of data area */
9379 + header->magic = NVRAM_INVALID_MAGIC; /* All ones magic */
9380 + offset = nvram_mtd->size - erasesize;
9381 + i = erasesize - NVRAM_SPACE + header->len;
9382 + ret = MTD_WRITE(nvram_mtd, offset, i, &len, buf);
9383 + if (ret || len != i) {
9384 + printk("nvram_commit: write error\n");
9385 + ret = -EIO;
9386 + goto done;
9387 + }
9388 +
9389 + /* Now mark the NVRAM in flash as "valid" by setting the correct
9390 + MAGIC # */
9391 + header->magic = NVRAM_MAGIC;
9392 + ret = MTD_WRITE(nvram_mtd, offset + magic_offset, sizeof(header->magic),
9393 + &magic_len, (char *)&header->magic);
9394 + if (ret || magic_len != sizeof(header->magic)) {
9395 + printk("nvram_commit: write MAGIC error\n");
9396 + ret = -EIO;
9397 + goto done;
9398 + }
9399 +
9400 + /*
9401 + * Reading a few bytes back here will put the device
9402 + * back to the correct mode on certain flashes */
9403 + offset = nvram_mtd->size - erasesize;
9404 + ret = MTD_READ(nvram_mtd, offset, 4, &len, buf);
9405 +
9406 + done:
9407 + up(&nvram_sem);
9408 + kfree(buf);
9409 +
9410 + return ret;
9411 +}
9412 +
9413 +int
9414 +nvram_getall(char *buf, int count)
9415 +{
9416 + unsigned long flags;
9417 + int ret;
9418 +
9419 + spin_lock_irqsave(&nvram_lock, flags);
9420 + if (nvram_major >= 0)
9421 + ret = _nvram_getall(buf, count);
9422 + else
9423 + ret = early_nvram_getall(buf, count);
9424 + spin_unlock_irqrestore(&nvram_lock, flags);
9425 +
9426 + return ret;
9427 +}
9428 +
9429 +
9430 +
9431 +
9432 +
9433 +
9434 +
9435 +/* User mode interface below */
9436 +
9437 +static ssize_t
9438 +dev_nvram_read(struct file *file, char *buf, size_t count, loff_t *ppos)
9439 +{
9440 + char tmp[100], *name = tmp, *value;
9441 + ssize_t ret;
9442 + unsigned long off;
9443 +
9444 + if (count > sizeof(tmp)) {
9445 + if (!(name = kmalloc(count, GFP_KERNEL)))
9446 + return -ENOMEM;
9447 + }
9448 +
9449 + if (copy_from_user(name, buf, count)) {
9450 + ret = -EFAULT;
9451 + goto done;
9452 + }
9453 +
9454 + if (*name == '\0') {
9455 + /* Get all variables */
9456 + ret = nvram_getall(name, count);
9457 + if (ret == 0) {
9458 + if (copy_to_user(buf, name, count)) {
9459 + ret = -EFAULT;
9460 + goto done;
9461 + }
9462 + ret = count;
9463 + }
9464 + } else {
9465 + if (!(value = nvram_get(name))) {
9466 + ret = 0;
9467 + goto done;
9468 + }
9469 +
9470 + /* Provide the offset into mmap() space */
9471 + off = (unsigned long) value - (unsigned long) nvram_buf;
9472 +
9473 + if (put_user(off, (unsigned long *) buf)) {
9474 + ret = -EFAULT;
9475 + goto done;
9476 + }
9477 +
9478 + ret = sizeof(unsigned long);
9479 + }
9480 +
9481 + flush_cache_all();
9482 +
9483 +done:
9484 + if (name != tmp)
9485 + kfree(name);
9486 +
9487 + return ret;
9488 +}
9489 +
9490 +static ssize_t
9491 +dev_nvram_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
9492 +{
9493 + char tmp[100], *name = tmp, *value;
9494 + ssize_t ret;
9495 +
9496 + if (count > sizeof(tmp)) {
9497 + if (!(name = kmalloc(count, GFP_KERNEL)))
9498 + return -ENOMEM;
9499 + }
9500 +
9501 + if (copy_from_user(name, buf, count)) {
9502 + ret = -EFAULT;
9503 + goto done;
9504 + }
9505 +
9506 + value = name;
9507 + name = strsep(&value, "=");
9508 + if (value)
9509 + ret = nvram_set(name, value) ? : count;
9510 + else
9511 + ret = nvram_unset(name) ? : count;
9512 +
9513 + done:
9514 + if (name != tmp)
9515 + kfree(name);
9516 +
9517 + return ret;
9518 +}
9519 +
9520 +static int
9521 +dev_nvram_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
9522 +{
9523 + if (cmd != NVRAM_MAGIC)
9524 + return -EINVAL;
9525 +
9526 + return nvram_commit();
9527 +}
9528 +
9529 +static int
9530 +dev_nvram_mmap(struct file *file, struct vm_area_struct *vma)
9531 +{
9532 + unsigned long offset = virt_to_phys(nvram_buf);
9533 +
9534 + if (remap_page_range(vma->vm_start, offset, vma->vm_end-vma->vm_start,
9535 + vma->vm_page_prot))
9536 + return -EAGAIN;
9537 +
9538 + return 0;
9539 +}
9540 +
9541 +static int
9542 +dev_nvram_open(struct inode *inode, struct file * file)
9543 +{
9544 + MOD_INC_USE_COUNT;
9545 + return 0;
9546 +}
9547 +
9548 +static int
9549 +dev_nvram_release(struct inode *inode, struct file * file)
9550 +{
9551 + MOD_DEC_USE_COUNT;
9552 + return 0;
9553 +}
9554 +
9555 +static struct file_operations dev_nvram_fops = {
9556 + owner: THIS_MODULE,
9557 + open: dev_nvram_open,
9558 + release: dev_nvram_release,
9559 + read: dev_nvram_read,
9560 + write: dev_nvram_write,
9561 + ioctl: dev_nvram_ioctl,
9562 + mmap: dev_nvram_mmap,
9563 +};
9564 +
9565 +static void
9566 +dev_nvram_exit(void)
9567 +{
9568 + int order = 0;
9569 + struct page *page, *end;
9570 +
9571 + if (nvram_handle)
9572 + devfs_unregister(nvram_handle);
9573 +
9574 + if (nvram_major >= 0)
9575 + devfs_unregister_chrdev(nvram_major, "nvram");
9576 +
9577 + if (nvram_mtd)
9578 + put_mtd_device(nvram_mtd);
9579 +
9580 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
9581 + order++;
9582 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
9583 + for (page = virt_to_page(nvram_buf); page <= end; page++)
9584 + mem_map_unreserve(page);
9585 +
9586 + _nvram_exit();
9587 +}
9588 +
9589 +static int __init
9590 +dev_nvram_init(void)
9591 +{
9592 + int order = 0, ret = 0;
9593 + struct page *page, *end;
9594 + unsigned int i;
9595 +
9596 + /* Allocate and reserve memory to mmap() */
9597 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
9598 + order++;
9599 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
9600 + for (page = virt_to_page(nvram_buf); page <= end; page++)
9601 + mem_map_reserve(page);
9602 +
9603 +#ifdef CONFIG_MTD
9604 + /* Find associated MTD device */
9605 + for (i = 0; i < MAX_MTD_DEVICES; i++) {
9606 + nvram_mtd = get_mtd_device(NULL, i);
9607 + if (nvram_mtd) {
9608 + if (!strcmp(nvram_mtd->name, "nvram") &&
9609 + nvram_mtd->size >= NVRAM_SPACE)
9610 + break;
9611 + put_mtd_device(nvram_mtd);
9612 + }
9613 + }
9614 + if (i >= MAX_MTD_DEVICES)
9615 + nvram_mtd = NULL;
9616 +#endif
9617 +
9618 + /* Initialize hash table lock */
9619 + spin_lock_init(&nvram_lock);
9620 +
9621 + /* Initialize commit semaphore */
9622 + init_MUTEX(&nvram_sem);
9623 +
9624 + /* Register char device */
9625 + if ((nvram_major = devfs_register_chrdev(0, "nvram", &dev_nvram_fops)) < 0) {
9626 + ret = nvram_major;
9627 + goto err;
9628 + }
9629 +
9630 + /* Initialize hash table */
9631 + _nvram_init(sbh);
9632 +
9633 + /* Create /dev/nvram handle */
9634 + nvram_handle = devfs_register(NULL, "nvram", DEVFS_FL_NONE, nvram_major, 0,
9635 + S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, &dev_nvram_fops, NULL);
9636 +
9637 + /* Set the SDRAM NCDL value into NVRAM if not already done */
9638 + if (getintvar(NULL, "sdram_ncdl") == 0) {
9639 + unsigned int ncdl;
9640 + char buf[] = "0x00000000";
9641 +
9642 + if ((ncdl = sb_memc_get_ncdl(sbh))) {
9643 + sprintf(buf, "0x%08x", ncdl);
9644 + nvram_set("sdram_ncdl", buf);
9645 + nvram_commit();
9646 + }
9647 + }
9648 +
9649 + return 0;
9650 +
9651 + err:
9652 + dev_nvram_exit();
9653 + return ret;
9654 +}
9655 +
9656 +module_init(dev_nvram_init);
9657 +module_exit(dev_nvram_exit);
9658 diff -urN linux.old/arch/mips/bcm947xx/pcibios.c linux.dev/arch/mips/bcm947xx/pcibios.c
9659 --- linux.old/arch/mips/bcm947xx/pcibios.c 1970-01-01 01:00:00.000000000 +0100
9660 +++ linux.dev/arch/mips/bcm947xx/pcibios.c 2006-04-27 23:42:50.000000000 +0200
9661 @@ -0,0 +1,380 @@
9662 +/*
9663 + * Low-Level PCI and SB support for BCM47xx (Linux support code)
9664 + *
9665 + * Copyright 2006, Broadcom Corporation
9666 + * All Rights Reserved.
9667 + *
9668 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9669 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9670 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9671 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9672 + *
9673 + * $Id: pcibios.c,v 1.1.1.9 2006/02/27 03:42:55 honor Exp $
9674 + */
9675 +
9676 +#include <linux/config.h>
9677 +#include <linux/types.h>
9678 +#include <linux/kernel.h>
9679 +#include <linux/sched.h>
9680 +#include <linux/pci.h>
9681 +#include <linux/init.h>
9682 +#include <linux/delay.h>
9683 +#include <asm/io.h>
9684 +#include <asm/irq.h>
9685 +#include <asm/paccess.h>
9686 +
9687 +#include <typedefs.h>
9688 +#include <osl.h>
9689 +#include <bcmutils.h>
9690 +#include <sbconfig.h>
9691 +#include <sbutils.h>
9692 +#include <hndpci.h>
9693 +#include <pcicfg.h>
9694 +#include <bcmdevs.h>
9695 +#include <bcmnvram.h>
9696 +
9697 +/* Global SB handle */
9698 +extern sb_t *bcm947xx_sbh;
9699 +extern spinlock_t bcm947xx_sbh_lock;
9700 +
9701 +/* Convenience */
9702 +#define sbh bcm947xx_sbh
9703 +#define sbh_lock bcm947xx_sbh_lock
9704 +
9705 +static int
9706 +sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
9707 +{
9708 + unsigned long flags;
9709 + int ret;
9710 +
9711 + spin_lock_irqsave(&sbh_lock, flags);
9712 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9713 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9714 + spin_unlock_irqrestore(&sbh_lock, flags);
9715 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9716 +}
9717 +
9718 +static int
9719 +sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
9720 +{
9721 + unsigned long flags;
9722 + int ret;
9723 +
9724 + spin_lock_irqsave(&sbh_lock, flags);
9725 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9726 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9727 + spin_unlock_irqrestore(&sbh_lock, flags);
9728 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9729 +}
9730 +
9731 +static int
9732 +sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
9733 +{
9734 + unsigned long flags;
9735 + int ret;
9736 +
9737 + spin_lock_irqsave(&sbh_lock, flags);
9738 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9739 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9740 + spin_unlock_irqrestore(&sbh_lock, flags);
9741 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9742 +}
9743 +
9744 +static int
9745 +sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
9746 +{
9747 + unsigned long flags;
9748 + int ret;
9749 +
9750 + spin_lock_irqsave(&sbh_lock, flags);
9751 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9752 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9753 + spin_unlock_irqrestore(&sbh_lock, flags);
9754 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9755 +}
9756 +
9757 +static int
9758 +sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
9759 +{
9760 + unsigned long flags;
9761 + int ret;
9762 +
9763 + spin_lock_irqsave(&sbh_lock, flags);
9764 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9765 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9766 + spin_unlock_irqrestore(&sbh_lock, flags);
9767 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9768 +}
9769 +
9770 +static int
9771 +sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
9772 +{
9773 + unsigned long flags;
9774 + int ret;
9775 +
9776 + spin_lock_irqsave(&sbh_lock, flags);
9777 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9778 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9779 + spin_unlock_irqrestore(&sbh_lock, flags);
9780 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9781 +}
9782 +
9783 +static struct pci_ops pcibios_ops = {
9784 + sbpci_read_config_byte,
9785 + sbpci_read_config_word,
9786 + sbpci_read_config_dword,
9787 + sbpci_write_config_byte,
9788 + sbpci_write_config_word,
9789 + sbpci_write_config_dword
9790 +};
9791 +
9792 +
9793 +void __init
9794 +pcibios_init(void)
9795 +{
9796 + ulong flags;
9797 +
9798 + if (!(sbh = sb_kattach()))
9799 + panic("sb_kattach failed");
9800 + spin_lock_init(&sbh_lock);
9801 +
9802 + spin_lock_irqsave(&sbh_lock, flags);
9803 + sbpci_init(sbh);
9804 + spin_unlock_irqrestore(&sbh_lock, flags);
9805 +
9806 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
9807 +
9808 + /* Scan the SB bus */
9809 + pci_scan_bus(0, &pcibios_ops, NULL);
9810 +
9811 +}
9812 +
9813 +char * __init
9814 +pcibios_setup(char *str)
9815 +{
9816 + if (!strncmp(str, "ban=", 4)) {
9817 + sbpci_ban(simple_strtoul(str + 4, NULL, 0));
9818 + return NULL;
9819 + }
9820 +
9821 + return (str);
9822 +}
9823 +
9824 +static u32 pci_iobase = 0x100;
9825 +static u32 pci_membase = SB_PCI_DMA;
9826 +
9827 +void __init
9828 +pcibios_fixup_bus(struct pci_bus *b)
9829 +{
9830 + struct list_head *ln;
9831 + struct pci_dev *d;
9832 + struct resource *res;
9833 + int pos, size;
9834 + u32 *base;
9835 + u8 irq;
9836 +
9837 + printk("PCI: Fixing up bus %d\n", b->number);
9838 +
9839 + /* Fix up SB */
9840 + if (b->number == 0) {
9841 + for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
9842 + d = pci_dev_b(ln);
9843 + /* Fix up interrupt lines */
9844 + pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
9845 + d->irq = irq + 2;
9846 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
9847 + }
9848 + }
9849 +
9850 + /* Fix up external PCI */
9851 + else {
9852 + for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
9853 + d = pci_dev_b(ln);
9854 + /* Fix up resource bases */
9855 + for (pos = 0; pos < 6; pos++) {
9856 + res = &d->resource[pos];
9857 + base = (res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase;
9858 + if (res->end) {
9859 + size = res->end - res->start + 1;
9860 + if (*base & (size - 1))
9861 + *base = (*base + size) & ~(size - 1);
9862 + res->start = *base;
9863 + res->end = res->start + size - 1;
9864 + *base += size;
9865 + pci_write_config_dword(d,
9866 + PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
9867 + }
9868 + /* Fix up PCI bridge BAR0 only */
9869 + if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
9870 + break;
9871 + }
9872 + /* Fix up interrupt lines */
9873 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
9874 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
9875 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
9876 + }
9877 + }
9878 +}
9879 +
9880 +unsigned int
9881 +pcibios_assign_all_busses(void)
9882 +{
9883 + return 1;
9884 +}
9885 +
9886 +void
9887 +pcibios_align_resource(void *data, struct resource *res,
9888 + unsigned long size, unsigned long align)
9889 +{
9890 +}
9891 +
9892 +int
9893 +pcibios_enable_resources(struct pci_dev *dev)
9894 +{
9895 + u16 cmd, old_cmd;
9896 + int idx;
9897 + struct resource *r;
9898 +
9899 + /* External PCI only */
9900 + if (dev->bus->number == 0)
9901 + return 0;
9902 +
9903 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
9904 + old_cmd = cmd;
9905 + for (idx = 0; idx < 6; idx++) {
9906 + r = &dev->resource[idx];
9907 + if (r->flags & IORESOURCE_IO)
9908 + cmd |= PCI_COMMAND_IO;
9909 + if (r->flags & IORESOURCE_MEM)
9910 + cmd |= PCI_COMMAND_MEMORY;
9911 + }
9912 + if (dev->resource[PCI_ROM_RESOURCE].start)
9913 + cmd |= PCI_COMMAND_MEMORY;
9914 + if (cmd != old_cmd) {
9915 + printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
9916 + pci_write_config_word(dev, PCI_COMMAND, cmd);
9917 + }
9918 + return 0;
9919 +}
9920 +
9921 +int
9922 +pcibios_enable_device(struct pci_dev *dev, int mask)
9923 +{
9924 + ulong flags;
9925 + uint coreidx;
9926 + void *regs;
9927 +
9928 + /* External PCI device enable */
9929 + if (dev->bus->number != 0)
9930 + return pcibios_enable_resources(dev);
9931 +
9932 + /* These cores come out of reset enabled */
9933 + if (dev->device == SB_MIPS ||
9934 + dev->device == SB_MIPS33 ||
9935 + dev->device == SB_EXTIF ||
9936 + dev->device == SB_CC)
9937 + return 0;
9938 +
9939 + spin_lock_irqsave(&sbh_lock, flags);
9940 + coreidx = sb_coreidx(sbh);
9941 + regs = sb_setcoreidx(sbh, PCI_SLOT(dev->devfn));
9942 + if (!regs)
9943 + return PCIBIOS_DEVICE_NOT_FOUND;
9944 +
9945 + /*
9946 + * The USB core requires a special bit to be set during core
9947 + * reset to enable host (OHCI) mode. Resetting the SB core in
9948 + * pcibios_enable_device() is a hack for compatibility with
9949 + * vanilla usb-ohci so that it does not have to know about
9950 + * SB. A driver that wants to use the USB core in device mode
9951 + * should know about SB and should reset the bit back to 0
9952 + * after calling pcibios_enable_device().
9953 + */
9954 + if (sb_coreid(sbh) == SB_USB) {
9955 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
9956 + sb_core_reset(sbh, 1 << 29, 0);
9957 + }
9958 + /*
9959 + * USB 2.0 special considerations:
9960 + *
9961 + * 1. Since the core supports both OHCI and EHCI functions, it must
9962 + * only be reset once.
9963 + *
9964 + * 2. In addition to the standard SB reset sequence, the Host Control
9965 + * Register must be programmed to bring the USB core and various
9966 + * phy components out of reset.
9967 + */
9968 + else if (sb_coreid(sbh) == SB_USB20H) {
9969 + if (!sb_iscoreup(sbh)) {
9970 + sb_core_reset(sbh, 0, 0);
9971 + writel(0x7FF, (ulong)regs + 0x200);
9972 + udelay(1);
9973 + }
9974 + } else
9975 + sb_core_reset(sbh, 0, 0);
9976 +
9977 + sb_setcoreidx(sbh, coreidx);
9978 + spin_unlock_irqrestore(&sbh_lock, flags);
9979 +
9980 + return 0;
9981 +}
9982 +
9983 +void
9984 +pcibios_update_resource(struct pci_dev *dev, struct resource *root,
9985 + struct resource *res, int resource)
9986 +{
9987 + unsigned long where, size;
9988 + u32 reg;
9989 +
9990 + /* External PCI only */
9991 + if (dev->bus->number == 0)
9992 + return;
9993 +
9994 + where = PCI_BASE_ADDRESS_0 + (resource * 4);
9995 + size = res->end - res->start;
9996 + pci_read_config_dword(dev, where, &reg);
9997 + reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
9998 + pci_write_config_dword(dev, where, reg);
9999 +}
10000 +
10001 +static void __init
10002 +quirk_sbpci_bridge(struct pci_dev *dev)
10003 +{
10004 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
10005 + return;
10006 +
10007 + printk("PCI: Fixing up bridge\n");
10008 +
10009 + /* Enable PCI bridge bus mastering and memory space */
10010 + pci_set_master(dev);
10011 + pcibios_enable_resources(dev);
10012 +
10013 + /* Enable PCI bridge BAR1 prefetch and burst */
10014 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
10015 +}
10016 +
10017 +struct pci_fixup pcibios_fixups[] = {
10018 + { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
10019 + { 0 }
10020 +};
10021 +
10022 +/*
10023 + * If we set up a device for bus mastering, we need to check the latency
10024 + * timer as certain crappy BIOSes forget to set it properly.
10025 + */
10026 +unsigned int pcibios_max_latency = 255;
10027 +
10028 +void pcibios_set_master(struct pci_dev *dev)
10029 +{
10030 + u8 lat;
10031 + pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
10032 + if (lat < 16)
10033 + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
10034 + else if (lat > pcibios_max_latency)
10035 + lat = pcibios_max_latency;
10036 + else
10037 + return;
10038 + printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
10039 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
10040 +}
10041 +
10042 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
10043 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
10044 +++ linux.dev/arch/mips/bcm947xx/prom.c 2006-04-27 19:24:19.000000000 +0200
10045 @@ -0,0 +1,41 @@
10046 +/*
10047 + * Early initialization code for BCM94710 boards
10048 + *
10049 + * Copyright 2004, Broadcom Corporation
10050 + * All Rights Reserved.
10051 + *
10052 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10053 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10054 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10055 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10056 + *
10057 + * $Id: prom.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
10058 + */
10059 +
10060 +#include <linux/config.h>
10061 +#include <linux/init.h>
10062 +#include <linux/kernel.h>
10063 +#include <linux/types.h>
10064 +#include <asm/bootinfo.h>
10065 +
10066 +void __init
10067 +prom_init(int argc, const char **argv)
10068 +{
10069 + unsigned long mem;
10070 +
10071 + mips_machgroup = MACH_GROUP_BRCM;
10072 + mips_machtype = MACH_BCM947XX;
10073 +
10074 + /* Figure out memory size by finding aliases */
10075 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
10076 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
10077 + *(unsigned long *)(prom_init))
10078 + break;
10079 + }
10080 + add_memory_region(0, mem, BOOT_MEM_RAM);
10081 +}
10082 +
10083 +void __init
10084 +prom_free_prom_memory(void)
10085 +{
10086 +}
10087 diff -urN linux.old/arch/mips/bcm947xx/sbmips.c linux.dev/arch/mips/bcm947xx/sbmips.c
10088 --- linux.old/arch/mips/bcm947xx/sbmips.c 1970-01-01 01:00:00.000000000 +0100
10089 +++ linux.dev/arch/mips/bcm947xx/sbmips.c 2006-05-02 04:43:13.000000000 +0200
10090 @@ -0,0 +1,1132 @@
10091 +/*
10092 + * BCM47XX Sonics SiliconBackplane MIPS core routines
10093 + *
10094 + * Copyright 2006, Broadcom Corporation
10095 + * All Rights Reserved.
10096 + *
10097 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10098 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10099 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10100 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10101 + *
10102 + * $Id: hndmips.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
10103 + */
10104 +
10105 +#include <typedefs.h>
10106 +#include <bcmdefs.h>
10107 +#include <osl.h>
10108 +#include <bcmutils.h>
10109 +#include <sbutils.h>
10110 +#include <bcmdevs.h>
10111 +#include <bcmnvram.h>
10112 +#include <sbconfig.h>
10113 +#include <sbextif.h>
10114 +#include <sbchipc.h>
10115 +#include <sbmemc.h>
10116 +#include <mipsinc.h>
10117 +#include <sbhndmips.h>
10118 +#include <hndcpu.h>
10119 +
10120 +/* sbipsflag register format, indexed by irq. */
10121 +static const uint32 sbips_int_mask[] = {
10122 + 0, /* placeholder */
10123 + SBIPS_INT1_MASK,
10124 + SBIPS_INT2_MASK,
10125 + SBIPS_INT3_MASK,
10126 + SBIPS_INT4_MASK
10127 +};
10128 +
10129 +static const uint32 sbips_int_shift[] = {
10130 + 0, /* placeholder */
10131 + SBIPS_INT1_SHIFT,
10132 + SBIPS_INT2_SHIFT,
10133 + SBIPS_INT3_SHIFT,
10134 + SBIPS_INT4_SHIFT
10135 +};
10136 +
10137 +/*
10138 + * Map SB cores sharing the MIPS hardware IRQ0 to virtual dedicated OS IRQs.
10139 + * Per-port BSP code is required to provide necessary translations between
10140 + * the shared MIPS IRQ and the virtual OS IRQs based on SB core flag.
10141 + *
10142 + * See sb_irq() for the mapping.
10143 + */
10144 +static uint shirq_map_base = 0;
10145 +
10146 +/* Returns the SB interrupt flag of the current core. */
10147 +static uint32
10148 +sb_getflag(sb_t *sbh)
10149 +{
10150 + osl_t *osh;
10151 + void *regs;
10152 + sbconfig_t *sb;
10153 +
10154 + osh = sb_osh(sbh);
10155 + regs = sb_coreregs(sbh);
10156 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10157 +
10158 + return (R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK);
10159 +}
10160 +
10161 +/*
10162 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
10163 + * 0 is returned.
10164 + */
10165 +uint
10166 +sb_irq(sb_t *sbh)
10167 +{
10168 + osl_t *osh;
10169 + uint idx;
10170 + void *regs;
10171 + sbconfig_t *sb;
10172 + uint32 flag, sbipsflag;
10173 + uint irq = 0;
10174 +
10175 + osh = sb_osh(sbh);
10176 + flag = sb_getflag(sbh);
10177 +
10178 + idx = sb_coreidx(sbh);
10179 +
10180 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
10181 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
10182 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10183 +
10184 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
10185 + sbipsflag = R_REG(osh, &sb->sbipsflag);
10186 + for (irq = 1; irq <= 4; irq++) {
10187 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
10188 + break;
10189 + }
10190 + if (irq == 5)
10191 + irq = 0;
10192 + }
10193 +
10194 + sb_setcoreidx(sbh, idx);
10195 +
10196 + return irq;
10197 +}
10198 +
10199 +/* Clears the specified MIPS IRQ. */
10200 +static void
10201 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
10202 +{
10203 + osl_t *osh;
10204 + void *regs;
10205 + sbconfig_t *sb;
10206 +
10207 + osh = sb_osh(sbh);
10208 +
10209 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
10210 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
10211 + ASSERT(regs);
10212 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10213 +
10214 + if (irq == 0)
10215 + W_REG(osh, &sb->sbintvec, 0);
10216 + else
10217 + OR_REG(osh, &sb->sbipsflag, sbips_int_mask[irq]);
10218 +}
10219 +
10220 +/*
10221 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
10222 + * IRQ 0 may be assigned more than once.
10223 + *
10224 + * The old assignment to the specified core is removed first.
10225 + */
10226 +static void
10227 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
10228 +{
10229 + osl_t *osh;
10230 + void *regs;
10231 + sbconfig_t *sb;
10232 + uint32 flag;
10233 + uint oldirq;
10234 +
10235 + osh = sb_osh(sbh);
10236 +
10237 + regs = sb_setcore(sbh, coreid, coreunit);
10238 + ASSERT(regs);
10239 + flag = sb_getflag(sbh);
10240 + oldirq = sb_irq(sbh);
10241 + if (oldirq)
10242 + sb_clearirq(sbh, oldirq);
10243 +
10244 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
10245 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
10246 + ASSERT(regs);
10247 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10248 +
10249 + if (!oldirq)
10250 + AND_REG(osh, &sb->sbintvec, ~(1 << flag));
10251 +
10252 + if (irq == 0)
10253 + OR_REG(osh, &sb->sbintvec, 1 << flag);
10254 + else {
10255 + flag <<= sbips_int_shift[irq];
10256 + ASSERT(!(flag & ~sbips_int_mask[irq]));
10257 + flag |= R_REG(osh, &sb->sbipsflag) & ~sbips_int_mask[irq];
10258 + W_REG(osh, &sb->sbipsflag, flag);
10259 + }
10260 +}
10261 +
10262 +/*
10263 + * Initializes clocks and interrupts. SB and NVRAM access must be
10264 + * initialized prior to calling.
10265 + *
10266 + * 'shirqmap' enables virtual dedicated OS IRQ mapping if non-zero.
10267 + */
10268 +void
10269 +BCMINITFN(sb_mips_init)(sb_t *sbh, uint shirqmap)
10270 +{
10271 + osl_t *osh;
10272 + ulong hz, ns, tmp;
10273 + extifregs_t *eir;
10274 + chipcregs_t *cc;
10275 + char *value;
10276 + uint irq;
10277 +
10278 + osh = sb_osh(sbh);
10279 +
10280 + /* Figure out current SB clock speed */
10281 + if ((hz = sb_clock(sbh)) == 0)
10282 + hz = 100000000;
10283 + ns = 1000000000 / hz;
10284 +
10285 + /* Setup external interface timing */
10286 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
10287 + /* Initialize extif so we can get to the LEDs and external UART */
10288 + W_REG(osh, &eir->prog_config, CF_EN);
10289 +
10290 + /* Set timing for the flash */
10291 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10292 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
10293 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10294 + W_REG(osh, &eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10295 +
10296 + /* Set programmable interface timing for external uart */
10297 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10298 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
10299 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
10300 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10301 + W_REG(osh, &eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10302 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
10303 + /* Set timing for the flash */
10304 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10305 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
10306 + tmp |= CEIL(120, ns); /* W0 = 120nS */
10307 + if ((sb_corerev(sbh) < 9) ||
10308 + (BCMINIT(sb_chip)(sbh) == 0x5365))
10309 + W_REG(osh, &cc->flash_waitcount, tmp);
10310 +
10311 + if ((sb_corerev(sbh) < 9) ||
10312 + ((sb_chip(sbh) == BCM5350_CHIP_ID) && sb_chiprev(sbh) == 0) ||
10313 + (BCMINIT(sb_chip)(sbh) == 0x5365)) {
10314 + W_REG(osh, &cc->pcmcia_memwait, tmp);
10315 + }
10316 +
10317 + /* Save shared IRQ mapping base */
10318 + shirq_map_base = shirqmap;
10319 + }
10320 +
10321 + /* Chip specific initialization */
10322 + switch (sb_chip(sbh)) {
10323 + case BCM4710_CHIP_ID:
10324 + /* Clear interrupt map */
10325 + for (irq = 0; irq <= 4; irq++)
10326 + sb_clearirq(sbh, irq);
10327 + sb_setirq(sbh, 0, SB_CODEC, 0);
10328 + sb_setirq(sbh, 0, SB_EXTIF, 0);
10329 + sb_setirq(sbh, 2, SB_ENET, 1);
10330 + sb_setirq(sbh, 3, SB_ILINE20, 0);
10331 + sb_setirq(sbh, 4, SB_PCI, 0);
10332 + ASSERT(eir);
10333 + value = nvram_get("et0phyaddr");
10334 + if (value && !strcmp(value, "31")) {
10335 + /* Enable internal UART */
10336 + W_REG(osh, &eir->corecontrol, CC_UE);
10337 + /* Give USB its own interrupt */
10338 + sb_setirq(sbh, 1, SB_USB, 0);
10339 + } else {
10340 + /* Disable internal UART */
10341 + W_REG(osh, &eir->corecontrol, 0);
10342 + /* Give Ethernet its own interrupt */
10343 + sb_setirq(sbh, 1, SB_ENET, 0);
10344 + sb_setirq(sbh, 0, SB_USB, 0);
10345 + }
10346 + break;
10347 + case BCM5350_CHIP_ID:
10348 + /* Clear interrupt map */
10349 + for (irq = 0; irq <= 4; irq++)
10350 + sb_clearirq(sbh, irq);
10351 + sb_setirq(sbh, 0, SB_CC, 0);
10352 + sb_setirq(sbh, 0, SB_MIPS33, 0);
10353 + sb_setirq(sbh, 1, SB_D11, 0);
10354 + sb_setirq(sbh, 2, SB_ENET, 0);
10355 + sb_setirq(sbh, 3, SB_PCI, 0);
10356 + sb_setirq(sbh, 4, SB_USB, 0);
10357 + break;
10358 + case BCM4785_CHIP_ID:
10359 + /* Reassign PCI to irq 4 */
10360 + sb_setirq(sbh, 4, SB_PCI, 0);
10361 + break;
10362 + }
10363 +}
10364 +
10365 +uint32
10366 +BCMINITFN(sb_cpu_clock)(sb_t *sbh)
10367 +{
10368 + extifregs_t *eir;
10369 + chipcregs_t *cc;
10370 + uint32 n, m;
10371 + uint idx;
10372 + uint32 pll_type, rate = 0;
10373 +
10374 + /* get index of the current core */
10375 + idx = sb_coreidx(sbh);
10376 + pll_type = PLL_TYPE1;
10377 +
10378 + /* switch to extif or chipc core */
10379 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
10380 + n = R_REG(osh, &eir->clockcontrol_n);
10381 + m = R_REG(osh, &eir->clockcontrol_sb);
10382 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
10383 + pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
10384 + n = R_REG(osh, &cc->clockcontrol_n);
10385 + if ((pll_type == PLL_TYPE2) ||
10386 + (pll_type == PLL_TYPE4) ||
10387 + (pll_type == PLL_TYPE6) ||
10388 + (pll_type == PLL_TYPE7))
10389 + m = R_REG(osh, &cc->clockcontrol_m3);
10390 + else if (pll_type == PLL_TYPE5) {
10391 + rate = 200000000;
10392 + goto out;
10393 + }
10394 + else if (pll_type == PLL_TYPE3) {
10395 + if (sb_chip(sbh) == BCM5365_CHIP_ID) {
10396 + rate = 200000000;
10397 + goto out;
10398 + }
10399 + /* 5350 uses m2 to control mips */
10400 + else
10401 + m = R_REG(osh, &cc->clockcontrol_m2);
10402 + } else
10403 + m = R_REG(osh, &cc->clockcontrol_sb);
10404 + } else
10405 + goto out;
10406 +
10407 +
10408 + /* calculate rate */
10409 + if (BCMINIT(sb_chip)(sbh) == 0x5365)
10410 + rate = 100000000;
10411 + else
10412 + rate = sb_clock_rate(pll_type, n, m);
10413 +
10414 + if (pll_type == PLL_TYPE6)
10415 + rate = SB2MIPS_T6(rate);
10416 +
10417 +out:
10418 + /* switch back to previous core */
10419 + sb_setcoreidx(sbh, idx);
10420 +
10421 + return rate;
10422 +}
10423 +
10424 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
10425 +
10426 +static void
10427 +BCMINITFN(handler)(void)
10428 +{
10429 + __asm__(
10430 + ".set\tmips32\n\t"
10431 + "ssnop\n\t"
10432 + "ssnop\n\t"
10433 + /* Disable interrupts */
10434 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
10435 + "mfc0 $15, $12\n\t"
10436 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
10437 + "li $14, -31746\n\t"
10438 + "and $15, $15, $14\n\t"
10439 + "mtc0 $15, $12\n\t"
10440 + "eret\n\t"
10441 + "nop\n\t"
10442 + "nop\n\t"
10443 + ".set\tmips0");
10444 +}
10445 +
10446 +/* The following MUST come right after handler() */
10447 +static void
10448 +BCMINITFN(afterhandler)(void)
10449 +{
10450 +}
10451 +
10452 +/*
10453 + * Set the MIPS, backplane and PCI clocks as closely as possible.
10454 + *
10455 + * MIPS clocks synchronization function has been moved from PLL in chipcommon
10456 + * core rev. 15 to a DLL inside the MIPS core in 4785.
10457 + */
10458 +bool
10459 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
10460 +{
10461 + extifregs_t *eir = NULL;
10462 + chipcregs_t *cc = NULL;
10463 + mipsregs_t *mipsr = NULL;
10464 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
10465 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
10466 + uint32 pll_type, sync_mode;
10467 + uint ic_size, ic_lsize;
10468 + uint idx, i;
10469 +
10470 + /* PLL configuration: type 1 */
10471 + typedef struct {
10472 + uint32 mipsclock;
10473 + uint16 n;
10474 + uint32 sb;
10475 + uint32 pci33;
10476 + uint32 pci25;
10477 + } n3m_table_t;
10478 + static n3m_table_t BCMINITDATA(type1_table)[] = {
10479 + /* 96.000 32.000 24.000 */
10480 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 },
10481 + /* 100.000 33.333 25.000 */
10482 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 },
10483 + /* 104.000 31.200 24.960 */
10484 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 },
10485 + /* 108.000 32.400 24.923 */
10486 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 },
10487 + /* 112.000 32.000 24.889 */
10488 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 },
10489 + /* 115.200 32.000 24.000 */
10490 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 },
10491 + /* 120.000 30.000 24.000 */
10492 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 },
10493 + /* 124.800 31.200 24.960 */
10494 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 },
10495 + /* 128.000 32.000 24.000 */
10496 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 },
10497 + /* 132.000 33.000 24.750 */
10498 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 },
10499 + /* 136.000 32.640 24.727 */
10500 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 },
10501 + /* 140.000 30.000 24.706 */
10502 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 },
10503 + /* 144.000 30.857 24.686 */
10504 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 },
10505 + /* 150.857 33.000 24.000 */
10506 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 },
10507 + /* 152.000 32.571 24.000 */
10508 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 },
10509 + /* 156.000 31.200 24.960 */
10510 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 },
10511 + /* 160.000 32.000 24.000 */
10512 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 },
10513 + /* 163.200 32.640 24.727 */
10514 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 },
10515 + /* 168.000 32.000 24.889 */
10516 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 },
10517 + /* 176.000 33.000 24.000 */
10518 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 },
10519 + };
10520 +
10521 + /* PLL configuration: type 3 */
10522 + typedef struct {
10523 + uint32 mipsclock;
10524 + uint16 n;
10525 + uint32 m2; /* that is the clockcontrol_m2 */
10526 + } type3_table_t;
10527 + static type3_table_t type3_table[] = {
10528 + /* for 5350, mips clock is always double sb clock */
10529 + { 150000000, 0x311, 0x4020005 },
10530 + { 200000000, 0x311, 0x4020003 },
10531 + };
10532 +
10533 + /* PLL configuration: type 2, 4, 7 */
10534 + typedef struct {
10535 + uint32 mipsclock;
10536 + uint32 sbclock;
10537 + uint16 n;
10538 + uint32 sb;
10539 + uint32 pci33;
10540 + uint32 m2;
10541 + uint32 m3;
10542 + uint32 ratio_cfg;
10543 + uint32 ratio_parm;
10544 + uint32 d11_r1;
10545 + uint32 d11_r2;
10546 + } n4m_table_t;
10547 + static n4m_table_t BCMINITDATA(type2_table)[] = {
10548 + { 120000000, 60000000, 0x0303, 0x01000200, 0x01000600, 0x01000200, 0x05000200, 11,
10549 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10550 + { 150000000, 75000000, 0x0303, 0x01000100, 0x01000600, 0x01000100, 0x05000100, 11,
10551 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10552 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8,
10553 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10554 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11,
10555 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10556 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11,
10557 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10558 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11,
10559 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10560 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11,
10561 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10562 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11,
10563 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10564 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8,
10565 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10566 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11,
10567 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10568 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11,
10569 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10570 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11,
10571 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10572 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10573 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10574 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10575 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10576 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11,
10577 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10578 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10579 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10580 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11,
10581 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10582 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01010100, 0x05000100, 8,
10583 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10584 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01010100, 0x05000100, 11,
10585 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10586 + { 330000000, 132000000, 0x0903, 0x01000200, 0x00020200, 0x01010100, 0x05000100, 0,
10587 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10588 + { 330000000, 146666666, 0x0903, 0x01010000, 0x00020200, 0x01010100, 0x05000100, 0,
10589 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10590 + { 330000000, 165000000, 0x0903, 0x01000100, 0x00020200, 0x01010100, 0x05000100, 0,
10591 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10592 + { 360000000, 120000000, 0x0a03, 0x01000300, 0x00010201, 0x01010200, 0x05000100, 0,
10593 + 0, 12 /* ratio 4/12 */, 0x04920492 },
10594 + { 360000000, 144000000, 0x0a03, 0x01000200, 0x00010201, 0x01010200, 0x05000100, 0,
10595 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10596 + { 360000000, 160000000, 0x0a03, 0x01010000, 0x00010201, 0x01010200, 0x05000100, 0,
10597 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10598 + { 360000000, 180000000, 0x0a03, 0x01000100, 0x00010201, 0x01010200, 0x05000100, 0,
10599 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10600 + { 390000000, 130000000, 0x0b03, 0x01010100, 0x00020101, 0x01020100, 0x05000100, 0,
10601 + 0, 12 /* ratio 4/12 */, 0x04920492 },
10602 + { 390000000, 156000000, 0x0b03, 0x01000200, 0x00020101, 0x01020100, 0x05000100, 0,
10603 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10604 + { 390000000, 173000000, 0x0b03, 0x01010000, 0x00020101, 0x01020100, 0x05000100, 0,
10605 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10606 + { 390000000, 195000000, 0x0b03, 0x01000100, 0x00020101, 0x01020100, 0x05000100, 0,
10607 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10608 + };
10609 + static n4m_table_t BCMINITDATA(type4_table)[] = {
10610 + { 120000000, 60000000, 0x0009, 0x11020009, 0x01030203, 0x11020009, 0x04000009, 11,
10611 + 0x0aaa0555 },
10612 + { 150000000, 75000000, 0x0009, 0x11050002, 0x01030203, 0x11050002, 0x04000005, 11,
10613 + 0x0aaa0555 },
10614 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10615 + 0x0aaa0555 },
10616 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11,
10617 + 0x0aaa0555 },
10618 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11,
10619 + 0x0aaa0555 },
10620 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10621 + 0x0aaa0555 },
10622 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11,
10623 + 0x0aaa0555 },
10624 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10625 + 0x0aaa0555 },
10626 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10627 + 0x0aaa0555 },
10628 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11,
10629 + 0x0aaa0555 },
10630 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8,
10631 + 0x012a00a9 },
10632 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11,
10633 + 0x0aaa0555 },
10634 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13,
10635 + 0x254a14a9 },
10636 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11,
10637 + 0x0aaa0555 },
10638 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9,
10639 + 0x02520129 },
10640 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11,
10641 + 0x0aaa0555 },
10642 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11,
10643 + 0x0aaa0555 },
10644 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13,
10645 + 0x254a14a9 },
10646 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13,
10647 + 0x254a14a9 },
10648 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13,
10649 + 0x254a14a9 },
10650 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9,
10651 + 0x02520129 },
10652 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11,
10653 + 0x0aaa0555 }
10654 + };
10655 + static n4m_table_t BCMINITDATA(type7_table)[] = {
10656 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10657 + 0x0aaa0555 },
10658 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10659 + 0x0aaa0555 },
10660 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11,
10661 + 0x0aaa0555 },
10662 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11,
10663 + 0x0aaa0555 },
10664 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11,
10665 + 0x0aaa0555 },
10666 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11,
10667 + 0x0aaa0555 },
10668 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10669 + 0x0aaa0555 },
10670 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11,
10671 + 0x0aaa0555 },
10672 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10673 + 0x0aaa0555 },
10674 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10675 + 0x0aaa0555 },
10676 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10677 + 0x0aaa0555 },
10678 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11,
10679 + 0x0aaa0555 },
10680 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11,
10681 + 0x0aaa0555 },
10682 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11,
10683 + 0x0aaa0555 }
10684 + };
10685 +
10686 + ulong start, end, dst;
10687 + bool ret = FALSE;
10688 +
10689 + volatile uint32 *dll_ctrl = (volatile uint32 *)0xff400008;
10690 + volatile uint32 *dll_r1 = (volatile uint32 *)0xff400010;
10691 + volatile uint32 *dll_r2 = (volatile uint32 *)0xff400018;
10692 +
10693 + /* get index of the current core */
10694 + idx = sb_coreidx(sbh);
10695 + clockcontrol_m2 = NULL;
10696 +
10697 + /* switch to extif or chipc core */
10698 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
10699 + pll_type = PLL_TYPE1;
10700 + clockcontrol_n = &eir->clockcontrol_n;
10701 + clockcontrol_sb = &eir->clockcontrol_sb;
10702 + clockcontrol_pci = &eir->clockcontrol_pci;
10703 + clockcontrol_m2 = &cc->clockcontrol_m2;
10704 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
10705 + pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
10706 + if (pll_type == PLL_TYPE6) {
10707 + clockcontrol_n = NULL;
10708 + clockcontrol_sb = NULL;
10709 + clockcontrol_pci = NULL;
10710 + } else {
10711 + clockcontrol_n = &cc->clockcontrol_n;
10712 + clockcontrol_sb = &cc->clockcontrol_sb;
10713 + clockcontrol_pci = &cc->clockcontrol_pci;
10714 + clockcontrol_m2 = &cc->clockcontrol_m2;
10715 + }
10716 + } else
10717 + goto done;
10718 +
10719 + if (pll_type == PLL_TYPE6) {
10720 + /* Silence compilers */
10721 + orig_n = orig_sb = orig_pci = 0;
10722 + } else {
10723 + /* Store the current clock register values */
10724 + orig_n = R_REG(osh, clockcontrol_n);
10725 + orig_sb = R_REG(osh, clockcontrol_sb);
10726 + orig_pci = R_REG(osh, clockcontrol_pci);
10727 + }
10728 +
10729 + if (pll_type == PLL_TYPE1) {
10730 + /* Keep the current PCI clock if not specified */
10731 + if (pciclock == 0) {
10732 + pciclock = sb_clock_rate(pll_type, R_REG(osh, clockcontrol_n),
10733 + R_REG(osh, clockcontrol_pci));
10734 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
10735 + }
10736 +
10737 + /* Search for the closest MIPS clock less than or equal to a preferred value */
10738 + for (i = 0; i < ARRAYSIZE(type1_table); i++) {
10739 + ASSERT(type1_table[i].mipsclock ==
10740 + sb_clock_rate(pll_type, type1_table[i].n,
10741 + type1_table[i].sb));
10742 + if (type1_table[i].mipsclock > mipsclock)
10743 + break;
10744 + }
10745 + if (i == 0) {
10746 + ret = FALSE;
10747 + goto done;
10748 + } else {
10749 + ret = TRUE;
10750 + i--;
10751 + }
10752 + ASSERT(type1_table[i].mipsclock <= mipsclock);
10753 +
10754 + /* No PLL change */
10755 + if ((orig_n == type1_table[i].n) &&
10756 + (orig_sb == type1_table[i].sb) &&
10757 + (orig_pci == type1_table[i].pci33))
10758 + goto done;
10759 +
10760 + /* Set the PLL controls */
10761 + W_REG(osh, clockcontrol_n, type1_table[i].n);
10762 + W_REG(osh, clockcontrol_sb, type1_table[i].sb);
10763 + if (pciclock == 25000000)
10764 + W_REG(osh, clockcontrol_pci, type1_table[i].pci25);
10765 + else
10766 + W_REG(osh, clockcontrol_pci, type1_table[i].pci33);
10767 +
10768 + /* Reset */
10769 + sb_watchdog(sbh, 1);
10770 + while (1);
10771 + } else if (pll_type == PLL_TYPE3) {
10772 + /* 5350 */
10773 + if (sb_chip(sbh) != BCM5365_CHIP_ID) {
10774 + /*
10775 + * Search for the closest MIPS clock less than or equal to
10776 + * a preferred value.
10777 + */
10778 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
10779 + if (type3_table[i].mipsclock > mipsclock)
10780 + break;
10781 + }
10782 + if (i == 0) {
10783 + ret = FALSE;
10784 + goto done;
10785 + } else {
10786 + ret = TRUE;
10787 + i--;
10788 + }
10789 + ASSERT(type3_table[i].mipsclock <= mipsclock);
10790 +
10791 + /* No PLL change */
10792 + orig_m2 = R_REG(osh, &cc->clockcontrol_m2);
10793 + if ((orig_n == type3_table[i].n) &&
10794 + (orig_m2 == type3_table[i].m2)) {
10795 + goto done;
10796 + }
10797 +
10798 + /* Set the PLL controls */
10799 + W_REG(osh, clockcontrol_n, type3_table[i].n);
10800 + W_REG(osh, clockcontrol_m2, type3_table[i].m2);
10801 +
10802 + /* Reset */
10803 + sb_watchdog(sbh, 1);
10804 + while (1);
10805 + }
10806 + } else if ((pll_type == PLL_TYPE2) ||
10807 + (pll_type == PLL_TYPE4) ||
10808 + (pll_type == PLL_TYPE6) ||
10809 + (pll_type == PLL_TYPE7)) {
10810 + n4m_table_t *table = NULL, *te;
10811 + uint tabsz = 0;
10812 +
10813 + ASSERT(cc);
10814 +
10815 + orig_mips = R_REG(osh, &cc->clockcontrol_m3);
10816 +
10817 + switch (pll_type) {
10818 + case PLL_TYPE6: {
10819 + uint32 new_mips = 0;
10820 +
10821 + ret = TRUE;
10822 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
10823 + new_mips = CC_T6_MMASK;
10824 +
10825 + if (orig_mips == new_mips)
10826 + goto done;
10827 +
10828 + W_REG(osh, &cc->clockcontrol_m3, new_mips);
10829 + goto end_fill;
10830 + }
10831 + case PLL_TYPE2:
10832 + table = type2_table;
10833 + tabsz = ARRAYSIZE(type2_table);
10834 + break;
10835 + case PLL_TYPE4:
10836 + table = type4_table;
10837 + tabsz = ARRAYSIZE(type4_table);
10838 + break;
10839 + case PLL_TYPE7:
10840 + table = type7_table;
10841 + tabsz = ARRAYSIZE(type7_table);
10842 + break;
10843 + default:
10844 + ASSERT("No table for plltype" == NULL);
10845 + break;
10846 + }
10847 +
10848 + /* Store the current clock register values */
10849 + orig_m2 = R_REG(osh, &cc->clockcontrol_m2);
10850 + orig_ratio_parm = 0;
10851 + orig_ratio_cfg = 0;
10852 +
10853 + /* Look up current ratio */
10854 + for (i = 0; i < tabsz; i++) {
10855 + if ((orig_n == table[i].n) &&
10856 + (orig_sb == table[i].sb) &&
10857 + (orig_pci == table[i].pci33) &&
10858 + (orig_m2 == table[i].m2) &&
10859 + (orig_mips == table[i].m3)) {
10860 + orig_ratio_parm = table[i].ratio_parm;
10861 + orig_ratio_cfg = table[i].ratio_cfg;
10862 + break;
10863 + }
10864 + }
10865 +
10866 + /* Search for the closest MIPS clock greater or equal to a preferred value */
10867 + for (i = 0; i < tabsz; i++) {
10868 + ASSERT(table[i].mipsclock ==
10869 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
10870 + if ((mipsclock <= table[i].mipsclock) &&
10871 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
10872 + break;
10873 + }
10874 + if (i == tabsz) {
10875 + ret = FALSE;
10876 + goto done;
10877 + } else {
10878 + te = &table[i];
10879 + ret = TRUE;
10880 + }
10881 +
10882 + /* No PLL change */
10883 + if ((orig_n == te->n) &&
10884 + (orig_sb == te->sb) &&
10885 + (orig_pci == te->pci33) &&
10886 + (orig_m2 == te->m2) &&
10887 + (orig_mips == te->m3))
10888 + goto done;
10889 +
10890 + /* Set the PLL controls */
10891 + W_REG(osh, clockcontrol_n, te->n);
10892 + W_REG(osh, clockcontrol_sb, te->sb);
10893 + W_REG(osh, clockcontrol_pci, te->pci33);
10894 + W_REG(osh, &cc->clockcontrol_m2, te->m2);
10895 + W_REG(osh, &cc->clockcontrol_m3, te->m3);
10896 +
10897 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
10898 + if ((pll_type == PLL_TYPE7) && (te->sb != te->m2) &&
10899 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
10900 + W_REG(osh, &cc->chipcontrol,
10901 + R_REG(osh, &cc->chipcontrol) | 0x100);
10902 +
10903 + /* No ratio change */
10904 + if (sb_chip(sbh) != BCM4785_CHIP_ID) {
10905 + if (orig_ratio_parm == te->ratio_parm)
10906 + goto end_fill;
10907 + }
10908 +
10909 + /* Preload the code into the cache */
10910 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
10911 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
10912 + start = ((ulong) &&start_fill_4785) & ~(ic_lsize - 1);
10913 + end = ((ulong) &&end_fill_4785 + (ic_lsize - 1)) & ~(ic_lsize - 1);
10914 + }
10915 + else {
10916 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
10917 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
10918 + }
10919 + while (start < end) {
10920 + cache_op(start, Fill_I);
10921 + start += ic_lsize;
10922 + }
10923 +
10924 + /* Copy the handler */
10925 + start = (ulong) &handler;
10926 + end = (ulong) &afterhandler;
10927 + dst = KSEG1ADDR(0x180);
10928 + for (i = 0; i < (end - start); i += 4)
10929 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
10930 +
10931 + /* Preload the handler into the cache one line at a time */
10932 + for (i = 0; i < (end - start); i += ic_lsize)
10933 + cache_op(dst + i, Fill_I);
10934 +
10935 + /* Clear BEV bit */
10936 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
10937 +
10938 + /* Enable interrupts */
10939 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
10940 +
10941 + /* 4785 clock freq change procedures */
10942 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
10943 + start_fill_4785:
10944 + /* Switch to async */
10945 + MTC0(C0_BROADCOM, 4, (1 << 22));
10946 +
10947 + /* Set clock ratio in MIPS */
10948 + *dll_r1 = (*dll_r1 & 0xfffffff0) | (te->d11_r1 - 1);
10949 + *dll_r2 = te->d11_r2;
10950 +
10951 + /* Enable new settings in MIPS */
10952 + *dll_r1 = *dll_r1 | 0xc0000000;
10953 +
10954 + /* Set active cfg */
10955 + MTC0(C0_BROADCOM, 2, MFC0(C0_BROADCOM, 2) | (1 << 3) | 1);
10956 +
10957 + /* Fake soft reset (clock cfg registers not reset) */
10958 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | (1 << 2));
10959 +
10960 + /* Clear active cfg */
10961 + MTC0(C0_BROADCOM, 2, MFC0(C0_BROADCOM, 2) & ~(1 << 3));
10962 +
10963 + /* set watchdog timer */
10964 + W_REG(osh, &cc->watchdog, 20);
10965 + (void) R_REG(osh, &cc->chipid);
10966 +
10967 + /* wait for timer interrupt */
10968 + __asm__ __volatile__(
10969 + ".set\tmips3\n\t"
10970 + "sync\n\t"
10971 + "wait\n\t"
10972 + ".set\tmips0");
10973 + end_fill_4785:
10974 + while (1);
10975 + }
10976 + /* Generic clock freq change procedures */
10977 + else {
10978 + /* Enable MIPS timer interrupt */
10979 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
10980 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
10981 + ASSERT(mipsr);
10982 + W_REG(osh, &mipsr->intmask, 1);
10983 +
10984 + start_fill:
10985 + /* step 1, set clock ratios */
10986 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
10987 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
10988 +
10989 + /* step 2: program timer intr */
10990 + W_REG(osh, &mipsr->timer, 100);
10991 + (void) R_REG(osh, &mipsr->timer);
10992 +
10993 + /* step 3, switch to async */
10994 + sync_mode = MFC0(C0_BROADCOM, 4);
10995 + MTC0(C0_BROADCOM, 4, 1 << 22);
10996 +
10997 + /* step 4, set cfg active */
10998 + MTC0(C0_BROADCOM, 2, (1 << 3) | 1);
10999 +
11000 + /* steps 5 & 6 */
11001 + __asm__ __volatile__(
11002 + ".set\tmips3\n\t"
11003 + "wait\n\t"
11004 + ".set\tmips0");
11005 +
11006 + /* step 7, clear cfg active */
11007 + MTC0(C0_BROADCOM, 2, 0);
11008 +
11009 + /* Additional Step: set back to orig sync mode */
11010 + MTC0(C0_BROADCOM, 4, sync_mode);
11011 +
11012 + /* step 8, fake soft reset */
11013 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | (1 << 2));
11014 +
11015 + end_fill:
11016 + /* set watchdog timer */
11017 + W_REG(osh, &cc->watchdog, 20);
11018 + (void) R_REG(osh, &cc->chipid);
11019 +
11020 + /* wait for timer interrupt */
11021 + __asm__ __volatile__(
11022 + ".set\tmips3\n\t"
11023 + "sync\n\t"
11024 + "wait\n\t"
11025 + ".set\tmips0");
11026 + while (1);
11027 + }
11028 + }
11029 +
11030 +done:
11031 + /* Enable 4785 DLL */
11032 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
11033 + uint32 tmp;
11034 +
11035 + /* set mask to 1e, enable DLL (bit 0) */
11036 + *dll_ctrl |= 0x0041e021;
11037 +
11038 + /* enable aggressive hardware mode */
11039 + *dll_ctrl |= 0x00000080;
11040 +
11041 + /* wait for lock flag to clear */
11042 + while ((*dll_ctrl & 0x2) == 0);
11043 +
11044 + /* clear sticky flags (clear on write 1) */
11045 + tmp = *dll_ctrl;
11046 + *dll_ctrl = tmp;
11047 +
11048 + /* set mask to 5b'10001 */
11049 + *dll_ctrl = (*dll_ctrl & 0xfffc1fff) | 0x00022000;
11050 +
11051 + /* enable sync mode */
11052 + MTC0(C0_BROADCOM, 4, MFC0(C0_BROADCOM, 4) & 0xfe3fffff);
11053 + (void)MFC0(C0_BROADCOM, 4);
11054 + }
11055 +
11056 + /* switch back to previous core */
11057 + sb_setcoreidx(sbh, idx);
11058 +
11059 + return ret;
11060 +}
11061 +
11062 +void
11063 +BCMINITFN(enable_pfc)(uint32 mode)
11064 +{
11065 + ulong start, end;
11066 + uint ic_size, ic_lsize;
11067 +
11068 + /* If auto then choose the correct mode for this
11069 + * platform, currently we only ever select one mode
11070 + */
11071 + if (mode == PFC_AUTO)
11072 + mode = PFC_INST;
11073 +
11074 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
11075 +
11076 + /* enable prefetch cache if available */
11077 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
11078 + start = ((ulong) &&setpfc_start) & ~(ic_lsize - 1);
11079 + end = ((ulong) &&setpfc_end + (ic_lsize - 1)) & ~(ic_lsize - 1);
11080 +
11081 + /* Preload setpfc code into the cache one line at a time */
11082 + while (start < end) {
11083 + cache_op(start, Fill_I);
11084 + start += ic_lsize;
11085 + }
11086 +
11087 + /* Now set the pfc */
11088 + setpfc_start:
11089 + /* write range */
11090 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
11091 +
11092 + /* enable */
11093 + *(volatile uint32 *)PFC_CR0 = mode;
11094 + setpfc_end:
11095 + /* Compiler foder */
11096 + ic_size = 0;
11097 + }
11098 +}
11099 +
11100 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
11101 +uint32
11102 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
11103 +{
11104 + osl_t *osh;
11105 + sbmemcregs_t *memc;
11106 + uint32 ret = 0;
11107 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
11108 + uint idx, rev;
11109 +
11110 + osh = sb_osh(sbh);
11111 +
11112 + idx = sb_coreidx(sbh);
11113 +
11114 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
11115 + if (memc == 0)
11116 + goto out;
11117 +
11118 + rev = sb_corerev(sbh);
11119 +
11120 + config = R_REG(osh, &memc->config);
11121 + wr = R_REG(osh, &memc->wrncdlcor);
11122 + rd = R_REG(osh, &memc->rdncdlcor);
11123 + misc = R_REG(osh, &memc->miscdlyctl);
11124 + dqsg = R_REG(osh, &memc->dqsgatencdl);
11125 +
11126 + rd &= MEMC_RDNCDLCOR_RD_MASK;
11127 + wr &= MEMC_WRNCDLCOR_WR_MASK;
11128 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
11129 +
11130 + if (config & MEMC_CONFIG_DDR) {
11131 + ret = (wr << 16) | (rd << 8) | dqsg;
11132 + } else {
11133 + if (rev > 0)
11134 + cd = rd;
11135 + else
11136 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
11137 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
11138 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
11139 + ret = (sm << 16) | (sd << 8) | cd;
11140 + }
11141 +
11142 +out:
11143 + /* switch back to previous core */
11144 + sb_setcoreidx(sbh, idx);
11145 +
11146 + return ret;
11147 +}
11148 +
11149 +#if defined(BCMPERFSTATS)
11150 +/*
11151 + * CP0 Register 25 supports 4 semi-independent 32bit performance counters.
11152 + * $25 select 0, 1, 2, and 3 are the counters. The counters *decrement* (who thought this one up?)
11153 + * $25 select 4 and 5 each contain 2-16bit control fields, one for each of the 4 counters
11154 + * $25 select 6 is the global perf control register.
11155 + */
11156 +/* enable and start instruction counting */
11157 +
11158 +void
11159 +hndmips_perf_instrcount_enable()
11160 +{
11161 + MTC0(C0_PERFORMANCE, 6, 0x80000200); /* global enable perf counters */
11162 + MTC0(C0_PERFORMANCE, 4,
11163 + 0x8044 | MFC0(C0_PERFORMANCE, 4)); /* enable instruction counting for counter 0 */
11164 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter zero */
11165 +}
11166 +
11167 +/* enable and start I$ hit and I$ miss counting */
11168 +void
11169 +hndmips_perf_icachecount_enable(void)
11170 +{
11171 + MTC0(C0_PERFORMANCE, 6, 0x80000218); /* enable I$ counting */
11172 + MTC0(C0_PERFORMANCE, 4, 0x80148018); /* count I$ hits in cntr 0 and misses in cntr 1 */
11173 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter 0 - # I$ hits */
11174 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter 1 - # I$ misses */
11175 +}
11176 +
11177 +/* enable and start D$ hit and I$ miss counting */
11178 +void
11179 +hndmips_perf_dcachecount_enable(void)
11180 +{
11181 + MTC0(C0_PERFORMANCE, 6, 0x80000211); /* enable D$ counting */
11182 + MTC0(C0_PERFORMANCE, 4, 0x80248028); /* count D$ hits in cntr 0 and misses in cntr 1 */
11183 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter 0 - # D$ hits */
11184 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter 1 - # D$ misses */
11185 +}
11186 +
11187 +void
11188 +hndmips_perf_icache_miss_enable()
11189 +{
11190 + MTC0(C0_PERFORMANCE, 4,
11191 + 0x80140000 | MFC0(C0_PERFORMANCE, 4)); /* enable cache misses counting for counter 1 */
11192 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter one */
11193 +}
11194 +
11195 +
11196 +void
11197 +hndmips_perf_icache_hit_enable()
11198 +{
11199 + MTC0(C0_PERFORMANCE, 5, 0x8018 | MFC0(C0_PERFORMANCE, 5));
11200 + /* enable cache hits counting for counter 2 */
11201 + MTC0(C0_PERFORMANCE, 2, 0); /* zero counter 2 */
11202 +}
11203 +
11204 +uint32
11205 +hndmips_perf_read_instrcount()
11206 +{
11207 + return -(long)(MFC0(C0_PERFORMANCE, 0));
11208 +}
11209 +
11210 +uint32
11211 +hndmips_perf_read_cache_miss()
11212 +{
11213 + return -(long)(MFC0(C0_PERFORMANCE, 1));
11214 +}
11215 +
11216 +uint32
11217 +hndmips_perf_read_cache_hit()
11218 +{
11219 + return -(long)(MFC0(C0_PERFORMANCE, 2));
11220 +}
11221 +
11222 +#endif /* BCMINTERNAL | BCMPERFSTATS */
11223 diff -urN linux.old/arch/mips/bcm947xx/sbpci.c linux.dev/arch/mips/bcm947xx/sbpci.c
11224 --- linux.old/arch/mips/bcm947xx/sbpci.c 1970-01-01 01:00:00.000000000 +0100
11225 +++ linux.dev/arch/mips/bcm947xx/sbpci.c 2006-05-02 17:37:13.000000000 +0200
11226 @@ -0,0 +1,768 @@
11227 +/*
11228 + * Low-Level PCI and SB support for BCM47xx
11229 + *
11230 + * Copyright 2006, Broadcom Corporation
11231 + * All Rights Reserved.
11232 + *
11233 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11234 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11235 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11236 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11237 + *
11238 + * $Id: hndpci.c,v 1.1.1.3 2006/04/08 06:13:39 honor Exp $
11239 + */
11240 +
11241 +#include <typedefs.h>
11242 +#include <osl.h>
11243 +#include <pcicfg.h>
11244 +#include <bcmdevs.h>
11245 +#include <sbconfig.h>
11246 +#include <bcmutils.h>
11247 +#include <sbutils.h>
11248 +#include <sbpci.h>
11249 +#include <bcmendian.h>
11250 +#include <bcmnvram.h>
11251 +#include <hndcpu.h>
11252 +#include <hndmips.h>
11253 +#include <hndpci.h>
11254 +
11255 +/* debug/trace */
11256 +#ifdef BCMDBG_PCI
11257 +#define PCI_MSG(args) printf args
11258 +#else
11259 +#define PCI_MSG(args)
11260 +#endif /* BCMDBG_PCI */
11261 +
11262 +/* Can free sbpci_init() memory after boot */
11263 +#ifndef linux
11264 +#define __init
11265 +#endif /* linux */
11266 +
11267 +/* Emulated configuration space */
11268 +typedef struct {
11269 + int n;
11270 + uint size0;
11271 + uint size1;
11272 + uint size2;
11273 + uint size3;
11274 +} sb_bar_cfg_t;
11275 +static pci_config_regs sb_config_regs[SB_MAXCORES];
11276 +static sb_bar_cfg_t sb_bar_cfg[SB_MAXCORES];
11277 +
11278 +/* Links to emulated and real PCI configuration spaces */
11279 +#define MAXFUNCS 2
11280 +typedef struct {
11281 + pci_config_regs *emu; /* emulated PCI config */
11282 + pci_config_regs *pci; /* real PCI config */
11283 + sb_bar_cfg_t *bar; /* region sizes */
11284 +} sb_pci_cfg_t;
11285 +static sb_pci_cfg_t sb_pci_cfg[SB_MAXCORES][MAXFUNCS];
11286 +
11287 +/* Special emulated config space for non-existing device */
11288 +static pci_config_regs sb_pci_null = { 0xffff, 0xffff };
11289 +
11290 +/* Banned cores */
11291 +static uint16 pci_ban[SB_MAXCORES] = { 0 };
11292 +static uint pci_banned = 0;
11293 +
11294 +/* CardBus mode */
11295 +static bool cardbus = FALSE;
11296 +
11297 +/* Disable PCI host core */
11298 +static bool pci_disabled = FALSE;
11299 +
11300 +/* Host bridge slot #, default to 0 */
11301 +static uint8 pci_hbslot = 0;
11302 +
11303 +/* Internal macros */
11304 +#define PCI_SLOTAD_MAP 16 /* SLOT<n> mapps to AD<n+16> */
11305 +#define PCI_HBSBCFG_REV 8 /* MIN. core rev. required to
11306 + * access host bridge PCI cfg space
11307 + * from SB
11308 + */
11309 +
11310 +/*
11311 + * Functions for accessing external PCI configuration space
11312 + */
11313 +
11314 +/* Assume one-hot slot wiring */
11315 +#define PCI_SLOT_MAX 16 /* Max. PCI Slots */
11316 +
11317 +static uint32
11318 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
11319 +{
11320 + uint coreidx;
11321 + sbpciregs_t *regs;
11322 + uint32 addr = 0;
11323 + osl_t *osh;
11324 +
11325 + /* CardBusMode supports only one device */
11326 + if (cardbus && dev > 1)
11327 + return 0;
11328 +
11329 + osh = sb_osh(sbh);
11330 +
11331 + coreidx = sb_coreidx(sbh);
11332 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
11333 +
11334 + /* Type 0 transaction */
11335 + if (bus == 1) {
11336 + /* Skip unwired slots */
11337 + if (dev < PCI_SLOT_MAX) {
11338 + uint32 win;
11339 +
11340 + /* Slide the PCI window to the appropriate slot */
11341 + win = (SBTOPCI_CFG0 | ((1 << (dev + PCI_SLOTAD_MAP)) & SBTOPCI1_MASK));
11342 + W_REG(osh, &regs->sbtopci1, win);
11343 + addr = SB_PCI_CFG |
11344 + ((1 << (dev + PCI_SLOTAD_MAP)) & ~SBTOPCI1_MASK) |
11345 + (func << PCICFG_FUN_SHIFT) |
11346 + (off & ~3);
11347 + }
11348 + } else {
11349 + /* Type 1 transaction */
11350 + W_REG(osh, &regs->sbtopci1, SBTOPCI_CFG1);
11351 + addr = SB_PCI_CFG |
11352 + (bus << PCICFG_BUS_SHIFT) |
11353 + (dev << PCICFG_SLOT_SHIFT) |
11354 + (func << PCICFG_FUN_SHIFT) |
11355 + (off & ~3);
11356 + }
11357 +
11358 + sb_setcoreidx(sbh, coreidx);
11359 +
11360 + return addr;
11361 +}
11362 +
11363 +/*
11364 + * Read host bridge PCI config registers from Silicon Backplane (>=rev8).
11365 + *
11366 + * It returns TRUE to indicate that access to the host bridge's pci config
11367 + * from SB is ok, and values in 'addr' and 'val' are valid.
11368 + *
11369 + * It can only read registers at multiple of 4-bytes. Callers must pick up
11370 + * needed bytes from 'val' based on 'off' value. Value in 'addr' reflects
11371 + * the register address where value in 'val' is read.
11372 + */
11373 +static bool
11374 +sb_pcihb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off,
11375 + uint32 **addr, uint32 *val)
11376 +{
11377 + sbpciregs_t *regs;
11378 + osl_t *osh;
11379 + uint coreidx;
11380 + bool ret = FALSE;
11381 +
11382 + /* sanity check */
11383 + ASSERT(bus == 1);
11384 + ASSERT(dev == pci_hbslot);
11385 + ASSERT(func == 0);
11386 +
11387 + osh = sb_osh(sbh);
11388 +
11389 + /* read pci config when core rev >= 8 */
11390 + coreidx = sb_coreidx(sbh);
11391 + regs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
11392 + if (regs && sb_corerev(sbh) >= PCI_HBSBCFG_REV) {
11393 + *addr = (uint32 *)&regs->pcicfg[func][off >> 2];
11394 + *val = R_REG(osh, *addr);
11395 + ret = TRUE;
11396 + }
11397 + sb_setcoreidx(sbh, coreidx);
11398 +
11399 + return ret;
11400 +}
11401 +
11402 +int
11403 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11404 +{
11405 + uint32 addr = 0, *reg = NULL, val;
11406 + int ret = 0;
11407 +
11408 + /*
11409 + * Set value to -1 when:
11410 + * flag 'pci_disabled' is true;
11411 + * value of 'addr' is zero;
11412 + * REG_MAP() fails;
11413 + * BUSPROBE() fails;
11414 + */
11415 + if (pci_disabled)
11416 + val = 0xffffffff;
11417 + else if (bus == 1 && dev == pci_hbslot && func == 0 &&
11418 + sb_pcihb_read_config(sbh, bus, dev, func, off, &reg, &val))
11419 + ;
11420 + else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
11421 + ((reg = (uint32 *)REG_MAP(addr, len)) == 0) ||
11422 + (BUSPROBE(val, reg) != 0))
11423 + val = 0xffffffff;
11424 +
11425 + PCI_MSG(("%s: 0x%x <= 0x%p(0x%x), len %d, off 0x%x, buf 0x%p\n",
11426 + __FUNCTION__, val, reg, addr, len, off, buf));
11427 +
11428 + val >>= 8 * (off & 3);
11429 + if (len == 4)
11430 + *((uint32 *) buf) = val;
11431 + else if (len == 2)
11432 + *((uint16 *) buf) = (uint16) val;
11433 + else if (len == 1)
11434 + *((uint8 *) buf) = (uint8) val;
11435 + else
11436 + ret = -1;
11437 +
11438 + if (reg && addr)
11439 + REG_UNMAP(reg);
11440 +
11441 + return ret;
11442 +}
11443 +
11444 +int
11445 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11446 +{
11447 + osl_t *osh;
11448 + uint32 addr = 0, *reg = NULL, val;
11449 + int ret = 0;
11450 +
11451 + osh = sb_osh(sbh);
11452 +
11453 + /*
11454 + * Ignore write attempt when:
11455 + * flag 'pci_disabled' is true;
11456 + * value of 'addr' is zero;
11457 + * REG_MAP() fails;
11458 + * BUSPROBE() fails;
11459 + */
11460 + if (pci_disabled)
11461 + return 0;
11462 + else if (bus == 1 && dev == pci_hbslot && func == 0 &&
11463 + sb_pcihb_read_config(sbh, bus, dev, func, off, &reg, &val))
11464 + ;
11465 + else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
11466 + ((reg = (uint32 *) REG_MAP(addr, len)) == 0) ||
11467 + (BUSPROBE(val, reg) != 0))
11468 + goto done;
11469 +
11470 + if (len == 4)
11471 + val = *((uint32 *) buf);
11472 + else if (len == 2) {
11473 + val &= ~(0xffff << (8 * (off & 3)));
11474 + val |= *((uint16 *) buf) << (8 * (off & 3));
11475 + } else if (len == 1) {
11476 + val &= ~(0xff << (8 * (off & 3)));
11477 + val |= *((uint8 *) buf) << (8 * (off & 3));
11478 + } else {
11479 + ret = -1;
11480 + goto done;
11481 + }
11482 +
11483 + PCI_MSG(("%s: 0x%x => 0x%p\n", __FUNCTION__, val, reg));
11484 +
11485 + W_REG(osh, reg, val);
11486 +
11487 +done:
11488 + if (reg && addr)
11489 + REG_UNMAP(reg);
11490 +
11491 + return ret;
11492 +}
11493 +
11494 +/*
11495 + * Must access emulated PCI configuration at these locations even when
11496 + * the real PCI config space exists and is accessible.
11497 + *
11498 + * PCI_CFG_VID (0x00)
11499 + * PCI_CFG_DID (0x02)
11500 + * PCI_CFG_PROGIF (0x09)
11501 + * PCI_CFG_SUBCL (0x0a)
11502 + * PCI_CFG_BASECL (0x0b)
11503 + * PCI_CFG_HDR (0x0e)
11504 + * PCI_CFG_INT (0x3c)
11505 + * PCI_CFG_PIN (0x3d)
11506 + */
11507 +#define FORCE_EMUCFG(off, len) \
11508 + ((off == PCI_CFG_VID) || (off == PCI_CFG_DID) || \
11509 + (off == PCI_CFG_PROGIF) || \
11510 + (off == PCI_CFG_SUBCL) || (off == PCI_CFG_BASECL) || \
11511 + (off == PCI_CFG_HDR) || \
11512 + (off == PCI_CFG_INT) || (off == PCI_CFG_PIN))
11513 +
11514 +/* Sync the emulation registers and the real PCI config registers. */
11515 +static void
11516 +sb_pcid_read_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
11517 + uint off, uint len)
11518 +{
11519 + osl_t *osh;
11520 + uint oldidx;
11521 +
11522 + ASSERT(cfg);
11523 + ASSERT(cfg->emu);
11524 + ASSERT(cfg->pci);
11525 +
11526 + /* decide if real PCI config register access is necessary */
11527 + if (FORCE_EMUCFG(off, len))
11528 + return;
11529 +
11530 + osh = sb_osh(sbh);
11531 +
11532 + /* access to the real pci config space only when the core is up */
11533 + oldidx = sb_coreidx(sbh);
11534 + sb_setcoreidx(sbh, coreidx);
11535 + if (sb_iscoreup(sbh)) {
11536 + if (len == 4)
11537 + *(uint32 *)((ulong)cfg->emu + off) =
11538 + htol32(R_REG(osh, (uint32 *)((ulong)cfg->pci + off)));
11539 + else if (len == 2)
11540 + *(uint16 *)((ulong)cfg->emu + off) =
11541 + htol16(R_REG(osh, (uint16 *)((ulong)cfg->pci + off)));
11542 + else if (len == 1)
11543 + *(uint8 *)((ulong)cfg->emu + off) =
11544 + R_REG(osh, (uint8 *)((ulong)cfg->pci + off));
11545 + }
11546 + sb_setcoreidx(sbh, oldidx);
11547 +}
11548 +
11549 +static void
11550 +sb_pcid_write_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
11551 + uint off, uint len)
11552 +{
11553 + osl_t *osh;
11554 + uint oldidx;
11555 +
11556 + ASSERT(cfg);
11557 + ASSERT(cfg->emu);
11558 + ASSERT(cfg->pci);
11559 +
11560 + osh = sb_osh(sbh);
11561 +
11562 + /* decide if real PCI config register access is necessary */
11563 + if (FORCE_EMUCFG(off, len))
11564 + return;
11565 +
11566 + /* access to the real pci config space only when the core is up */
11567 + oldidx = sb_coreidx(sbh);
11568 + sb_setcoreidx(sbh, coreidx);
11569 + if (sb_iscoreup(sbh)) {
11570 + if (len == 4)
11571 + W_REG(osh, (uint32 *)((ulong)cfg->pci + off),
11572 + ltoh32(*(uint32 *)((ulong)cfg->emu + off)));
11573 + else if (len == 2)
11574 + W_REG(osh, (uint16 *)((ulong)cfg->pci + off),
11575 + ltoh16(*(uint16 *)((ulong)cfg->emu + off)));
11576 + else if (len == 1)
11577 + W_REG(osh, (uint8 *)((ulong)cfg->pci + off),
11578 + *(uint8 *)((ulong)cfg->emu + off));
11579 + }
11580 + sb_setcoreidx(sbh, oldidx);
11581 +}
11582 +
11583 +/*
11584 + * Functions for accessing translated SB configuration space
11585 + */
11586 +static int
11587 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11588 +{
11589 + pci_config_regs *cfg;
11590 +
11591 + if (dev >= SB_MAXCORES || func >= MAXFUNCS || (off + len) > sizeof(pci_config_regs))
11592 + return -1;
11593 + cfg = sb_pci_cfg[dev][func].emu;
11594 +
11595 + ASSERT(ISALIGNED(off, len));
11596 + ASSERT(ISALIGNED((uintptr)buf, len));
11597 +
11598 + /* use special config space if the device does not exist */
11599 + if (!cfg)
11600 + cfg = &sb_pci_null;
11601 + /* sync emulation with real PCI config if necessary */
11602 + else if (sb_pci_cfg[dev][func].pci)
11603 + sb_pcid_read_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
11604 +
11605 + if (len == 4)
11606 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
11607 + else if (len == 2)
11608 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
11609 + else if (len == 1)
11610 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
11611 + else
11612 + return -1;
11613 +
11614 + return 0;
11615 +}
11616 +
11617 +static int
11618 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11619 +{
11620 + uint coreidx;
11621 + void *regs;
11622 + pci_config_regs *cfg;
11623 + osl_t *osh;
11624 + sb_bar_cfg_t *bar;
11625 +
11626 + if (dev >= SB_MAXCORES || func >= MAXFUNCS || (off + len) > sizeof(pci_config_regs))
11627 + return -1;
11628 + cfg = sb_pci_cfg[dev][func].emu;
11629 + if (!cfg)
11630 + return -1;
11631 +
11632 + ASSERT(ISALIGNED(off, len));
11633 + ASSERT(ISALIGNED((uintptr)buf, len));
11634 +
11635 + osh = sb_osh(sbh);
11636 +
11637 + /* Emulate BAR sizing */
11638 + if (off >= OFFSETOF(pci_config_regs, base[0]) &&
11639 + off <= OFFSETOF(pci_config_regs, base[3]) &&
11640 + len == 4 && *((uint32 *) buf) == ~0) {
11641 + coreidx = sb_coreidx(sbh);
11642 + if ((regs = sb_setcoreidx(sbh, dev))) {
11643 + bar = sb_pci_cfg[dev][func].bar;
11644 + /* Highest numbered address match register */
11645 + if (off == OFFSETOF(pci_config_regs, base[0]))
11646 + cfg->base[0] = ~(bar->size0 - 1);
11647 + else if (off == OFFSETOF(pci_config_regs, base[1]) && bar->n >= 1)
11648 + cfg->base[1] = ~(bar->size1 - 1);
11649 + else if (off == OFFSETOF(pci_config_regs, base[2]) && bar->n >= 2)
11650 + cfg->base[2] = ~(bar->size2 - 1);
11651 + else if (off == OFFSETOF(pci_config_regs, base[3]) && bar->n >= 3)
11652 + cfg->base[3] = ~(bar->size3 - 1);
11653 + }
11654 + sb_setcoreidx(sbh, coreidx);
11655 + }
11656 + else if (len == 4)
11657 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
11658 + else if (len == 2)
11659 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
11660 + else if (len == 1)
11661 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
11662 + else
11663 + return -1;
11664 +
11665 + /* sync emulation with real PCI config if necessary */
11666 + if (sb_pci_cfg[dev][func].pci)
11667 + sb_pcid_write_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
11668 +
11669 + return 0;
11670 +}
11671 +
11672 +int
11673 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11674 +{
11675 + if (bus == 0)
11676 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
11677 + else
11678 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
11679 +}
11680 +
11681 +int
11682 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11683 +{
11684 + if (bus == 0)
11685 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
11686 + else
11687 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
11688 +}
11689 +
11690 +void
11691 +sbpci_ban(uint16 core)
11692 +{
11693 + if (pci_banned < ARRAYSIZE(pci_ban))
11694 + pci_ban[pci_banned++] = core;
11695 +}
11696 +
11697 +/*
11698 + * Initiliaze PCI core. Return 0 after a successful initialization.
11699 + * Otherwise return -1 to indicate there is no PCI core and return 1
11700 + * to indicate PCI core is disabled.
11701 + */
11702 +int __init
11703 +sbpci_init_pci(sb_t *sbh)
11704 +{
11705 + uint chip, chiprev, chippkg, host;
11706 + uint32 boardflags;
11707 + sbpciregs_t *pci;
11708 + sbconfig_t *sb;
11709 + uint32 val;
11710 + int ret = 0;
11711 + char *hbslot;
11712 + osl_t *osh;
11713 +
11714 + chip = sb_chip(sbh);
11715 + chiprev = sb_chiprev(sbh);
11716 + chippkg = sb_chippkg(sbh);
11717 +
11718 + osh = sb_osh(sbh);
11719 +
11720 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
11721 + printk("PCI: no core\n");
11722 + pci_disabled = TRUE;
11723 + return -1;
11724 + }
11725 +
11726 + if ((chip == 0x4310) && (chiprev == 0))
11727 + pci_disabled = TRUE;
11728 +
11729 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
11730 +
11731 + boardflags = (uint32) getintvar(NULL, "boardflags");
11732 +
11733 + /*
11734 + * The 200-pin BCM4712 package does not bond out PCI. Even when
11735 + * PCI is bonded out, some boards may leave the pins
11736 + * floating.
11737 + */
11738 + if (((chip == BCM4712_CHIP_ID) &&
11739 + ((chippkg == BCM4712SMALL_PKG_ID) ||
11740 + (chippkg == BCM4712MID_PKG_ID))) ||
11741 + (boardflags & BFL_NOPCI))
11742 + pci_disabled = TRUE;
11743 +
11744 + /* Enable the core */
11745 + sb_core_reset(sbh, 0, 0);
11746 +
11747 + /*
11748 + * If the PCI core should not be touched (disabled, not bonded
11749 + * out, or pins floating), do not even attempt to access core
11750 + * registers. Otherwise, try to determine if it is in host
11751 + * mode.
11752 + */
11753 + if (pci_disabled)
11754 + host = 0;
11755 + else
11756 + host = !BUSPROBE(val, &pci->control);
11757 +
11758 + if (!host) {
11759 + ret = 1;
11760 +
11761 + /* Disable PCI interrupts in client mode */
11762 + W_REG(osh, &sb->sbintvec, 0);
11763 +
11764 + /* Disable the PCI bridge in client mode */
11765 + sbpci_ban(SB_PCI);
11766 + sb_core_disable(sbh, 0);
11767 +
11768 + printk("PCI: Disabled\n");
11769 + } else {
11770 + printk("PCI: Initializing host\n");
11771 +
11772 + /* Disable PCI SBReqeustTimeout for BCM4785 */
11773 + if (chip == BCM4785_CHIP_ID) {
11774 + AND_REG(osh, &sb->sbimconfiglow, ~0x00000070);
11775 + sb_commit(sbh);
11776 + }
11777 +
11778 + /* Reset the external PCI bus and enable the clock */
11779 + W_REG(osh, &pci->control, 0x5); /* enable the tristate drivers */
11780 + W_REG(osh, &pci->control, 0xd); /* enable the PCI clock */
11781 + OSL_DELAY(150); /* delay > 100 us */
11782 + W_REG(osh, &pci->control, 0xf); /* deassert PCI reset */
11783 + /* Use internal arbiter and park REQ/GRNT at external master 0 */
11784 + W_REG(osh, &pci->arbcontrol, PCI_INT_ARB);
11785 + OSL_DELAY(1); /* delay 1 us */
11786 + if (sb_corerev(sbh) >= 8) {
11787 + val = getintvar(NULL, "parkid");
11788 + ASSERT(val <= PCI_PARKID_LAST);
11789 + OR_REG(osh, &pci->arbcontrol, val << PCI_PARKID_SHIFT);
11790 + OSL_DELAY(1);
11791 + }
11792 +
11793 + /* Enable CardBusMode */
11794 + cardbus = getintvar(NULL, "cardbus") == 1;
11795 + if (cardbus) {
11796 + printk("PCI: Enabling CardBus\n");
11797 + /* GPIO 1 resets the CardBus device on bcm94710ap */
11798 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
11799 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
11800 + W_REG(osh, &pci->sprom[0], R_REG(osh, &pci->sprom[0]) | 0x400);
11801 + }
11802 +
11803 + /* 64 MB I/O access window */
11804 + W_REG(osh, &pci->sbtopci0, SBTOPCI_IO);
11805 + /* 64 MB configuration access window */
11806 + W_REG(osh, &pci->sbtopci1, SBTOPCI_CFG0);
11807 + /* 1 GB memory access window */
11808 + W_REG(osh, &pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
11809 +
11810 + /* Host bridge slot # nvram overwrite */
11811 + if ((hbslot = nvram_get("pcihbslot"))) {
11812 + pci_hbslot = bcm_strtoul(hbslot, NULL, 0);
11813 + ASSERT(pci_hbslot < PCI_MAX_DEVICES);
11814 + }
11815 +
11816 + /* Enable PCI bridge BAR0 prefetch and burst */
11817 + val = 6;
11818 + sbpci_write_config(sbh, 1, pci_hbslot, 0, PCI_CFG_CMD, &val, sizeof(val));
11819 +
11820 + /* Enable PCI interrupts */
11821 + W_REG(osh, &pci->intmask, PCI_INTA);
11822 + }
11823 +
11824 + return ret;
11825 +}
11826 +
11827 +/*
11828 + * Get the PCI region address and size information.
11829 + */
11830 +static void __init
11831 +sbpci_init_regions(sb_t *sbh, uint func, pci_config_regs *cfg, sb_bar_cfg_t *bar)
11832 +{
11833 + osl_t *osh;
11834 + uint16 coreid;
11835 + void *regs;
11836 + sbconfig_t *sb;
11837 + uint32 base;
11838 +
11839 + osh = sb_osh(sbh);
11840 + coreid = sb_coreid(sbh);
11841 + regs = sb_coreregs(sbh);
11842 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11843 +
11844 + switch (coreid) {
11845 + case SB_USB20H:
11846 + base = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
11847 +
11848 + cfg->base[0] = func == 0 ? base : base + 0x800; /* OHCI/EHCI */
11849 + cfg->base[1] = 0;
11850 + cfg->base[2] = 0;
11851 + cfg->base[3] = 0;
11852 + cfg->base[4] = 0;
11853 + cfg->base[5] = 0;
11854 + bar->n = 1;
11855 + bar->size0 = func == 0 ? 0x200 : 0x100; /* OHCI/EHCI */
11856 + bar->size1 = 0;
11857 + bar->size2 = 0;
11858 + bar->size3 = 0;
11859 + break;
11860 + default:
11861 + cfg->base[0] = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
11862 + cfg->base[1] = htol32(sb_base(R_REG(osh, &sb->sbadmatch1)));
11863 + cfg->base[2] = htol32(sb_base(R_REG(osh, &sb->sbadmatch2)));
11864 + cfg->base[3] = htol32(sb_base(R_REG(osh, &sb->sbadmatch3)));
11865 + cfg->base[4] = 0;
11866 + cfg->base[5] = 0;
11867 + bar->n = (R_REG(osh, &sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
11868 + bar->size0 = sb_size(R_REG(osh, &sb->sbadmatch0));
11869 + bar->size1 = sb_size(R_REG(osh, &sb->sbadmatch1));
11870 + bar->size2 = sb_size(R_REG(osh, &sb->sbadmatch2));
11871 + bar->size3 = sb_size(R_REG(osh, &sb->sbadmatch3));
11872 + break;
11873 + }
11874 +}
11875 +
11876 +/*
11877 + * Construct PCI config spaces for SB cores so that they
11878 + * can be accessed as if they were PCI devices.
11879 + */
11880 +static void __init
11881 +sbpci_init_cores(sb_t *sbh)
11882 +{
11883 + uint chiprev, coreidx, i;
11884 + sbconfig_t *sb;
11885 + pci_config_regs *cfg, *pci;
11886 + sb_bar_cfg_t *bar;
11887 + void *regs;
11888 + osl_t *osh;
11889 + uint16 vendor, device;
11890 + uint16 coreid;
11891 + uint8 class, subclass, progif;
11892 + uint dev;
11893 + uint8 header;
11894 + uint func;
11895 +
11896 + chiprev = sb_chiprev(sbh);
11897 + coreidx = sb_coreidx(sbh);
11898 +
11899 + osh = sb_osh(sbh);
11900 +
11901 + /* Scan the SB bus */
11902 + bzero(sb_config_regs, sizeof(sb_config_regs));
11903 + bzero(sb_bar_cfg, sizeof(sb_bar_cfg));
11904 + bzero(sb_pci_cfg, sizeof(sb_pci_cfg));
11905 + memset(&sb_pci_null, -1, sizeof(sb_pci_null));
11906 + cfg = sb_config_regs;
11907 + bar = sb_bar_cfg;
11908 + for (dev = 0; dev < SB_MAXCORES; dev ++) {
11909 + /* Check if the core exists */
11910 + if (!(regs = sb_setcoreidx(sbh, dev)))
11911 + continue;
11912 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11913 +
11914 + /* Check if this core is banned */
11915 + coreid = sb_coreid(sbh);
11916 + for (i = 0; i < pci_banned; i++)
11917 + if (coreid == pci_ban[i])
11918 + break;
11919 + if (i < pci_banned)
11920 + continue;
11921 +
11922 + for (func = 0; func < MAXFUNCS; ++func) {
11923 + /* Make sure we won't go beyond the limit */
11924 + if (cfg >= &sb_config_regs[SB_MAXCORES]) {
11925 + printk("PCI: too many emulated devices\n");
11926 + goto done;
11927 + }
11928 +
11929 + /* Convert core id to pci id */
11930 + if (sb_corepciid(sbh, func, &vendor, &device, &class, &subclass,
11931 + &progif, &header))
11932 + continue;
11933 +
11934 + /*
11935 + * Differentiate real PCI config from emulated.
11936 + * non zero 'pci' indicate there is a real PCI config space
11937 + * for this device.
11938 + */
11939 + switch (device) {
11940 + case BCM47XX_GIGETH_ID:
11941 + pci = (pci_config_regs *)((uint32)regs + 0x800);
11942 + break;
11943 + case BCM47XX_SATAXOR_ID:
11944 + pci = (pci_config_regs *)((uint32)regs + 0x400);
11945 + break;
11946 + case BCM47XX_ATA100_ID:
11947 + pci = (pci_config_regs *)((uint32)regs + 0x800);
11948 + break;
11949 + default:
11950 + pci = NULL;
11951 + break;
11952 + }
11953 + /* Supported translations */
11954 + cfg->vendor = htol16(vendor);
11955 + cfg->device = htol16(device);
11956 + cfg->rev_id = chiprev;
11957 + cfg->prog_if = progif;
11958 + cfg->sub_class = subclass;
11959 + cfg->base_class = class;
11960 + cfg->header_type = header;
11961 + sbpci_init_regions(sbh, func, cfg, bar);
11962 + /* Save core interrupt flag */
11963 + cfg->int_pin = R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
11964 + /* Save core interrupt assignment */
11965 + cfg->int_line = sb_irq(sbh);
11966 + /* Indicate there is no SROM */
11967 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
11968 +
11969 + /* Point to the PCI config spaces */
11970 + sb_pci_cfg[dev][func].emu = cfg;
11971 + sb_pci_cfg[dev][func].pci = pci;
11972 + sb_pci_cfg[dev][func].bar = bar;
11973 + cfg ++;
11974 + bar ++;
11975 + }
11976 + }
11977 +
11978 +done:
11979 + sb_setcoreidx(sbh, coreidx);
11980 +}
11981 +
11982 +/*
11983 + * Initialize PCI core and construct PCI config spaces for SB cores.
11984 + * Must propagate sbpci_init_pci() return value to the caller to let
11985 + * them know the PCI core initialization status.
11986 + */
11987 +int __init
11988 +sbpci_init(sb_t *sbh)
11989 +{
11990 + int status = sbpci_init_pci(sbh);
11991 + sbpci_init_cores(sbh);
11992 + return status;
11993 +}
11994 +
11995 diff -urN linux.old/arch/mips/bcm947xx/sbutils.c linux.dev/arch/mips/bcm947xx/sbutils.c
11996 --- linux.old/arch/mips/bcm947xx/sbutils.c 1970-01-01 01:00:00.000000000 +0100
11997 +++ linux.dev/arch/mips/bcm947xx/sbutils.c 2006-05-02 04:33:16.000000000 +0200
11998 @@ -0,0 +1,3081 @@
11999 +/*
12000 + * Misc utility routines for accessing chip-specific features
12001 + * of the SiliconBackplane-based Broadcom chips.
12002 + *
12003 + * Copyright 2006, Broadcom Corporation
12004 + * All Rights Reserved.
12005 + *
12006 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12007 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
12008 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
12009 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12010 + * $Id: sbutils.c,v 1.10 2006/04/08 07:12:42 honor Exp $
12011 + */
12012 +
12013 +#include <typedefs.h>
12014 +#include <bcmdefs.h>
12015 +#include <osl.h>
12016 +#include <bcmutils.h>
12017 +#include <sbutils.h>
12018 +#include <bcmdevs.h>
12019 +#include <sbconfig.h>
12020 +#include <sbchipc.h>
12021 +#include <sbpci.h>
12022 +#include <sbpcie.h>
12023 +#include <pcicfg.h>
12024 +#include <sbpcmcia.h>
12025 +#include <sbextif.h>
12026 +#include <sbsocram.h>
12027 +#include <bcmsrom.h>
12028 +#ifdef __mips__
12029 +#include <mipsinc.h>
12030 +#endif /* __mips__ */
12031 +
12032 +/* debug/trace */
12033 +#define SB_ERROR(args)
12034 +
12035 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
12036 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
12037 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
12038 +
12039 +/* misc sb info needed by some of the routines */
12040 +typedef struct sb_info {
12041 +
12042 + struct sb_pub sb; /* back plane public state (must be first field) */
12043 +
12044 + void *osh; /* osl os handle */
12045 + void *sdh; /* bcmsdh handle */
12046 +
12047 + void *curmap; /* current regs va */
12048 + void *regs[SB_MAXCORES]; /* other regs va */
12049 +
12050 + uint curidx; /* current core index */
12051 + uint dev_coreid; /* the core provides driver functions */
12052 +
12053 + bool memseg; /* flag to toggle MEM_SEG register */
12054 +
12055 + uint gpioidx; /* gpio control core index */
12056 + uint gpioid; /* gpio control coretype */
12057 +
12058 + uint numcores; /* # discovered cores */
12059 + uint coreid[SB_MAXCORES]; /* id of each core */
12060 +
12061 + void *intr_arg; /* interrupt callback function arg */
12062 + sb_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
12063 + sb_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
12064 + sb_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
12065 +
12066 +} sb_info_t;
12067 +
12068 +/* local prototypes */
12069 +static sb_info_t * sb_doattach(sb_info_t *si, uint devid, osl_t *osh, void *regs,
12070 + uint bustype, void *sdh, char **vars, uint *varsz);
12071 +static void sb_scan(sb_info_t *si);
12072 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
12073 +static uint _sb_coreidx(sb_info_t *si);
12074 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
12075 +static uint sb_pcidev2chip(uint pcidev);
12076 +static uint sb_chip2numcores(uint chip);
12077 +static bool sb_ispcie(sb_info_t *si);
12078 +static bool sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen);
12079 +static int sb_pci_fixcfg(sb_info_t *si);
12080 +
12081 +/* routines to access mdio slave device registers */
12082 +static int sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint readdr, uint val);
12083 +static void sb_war30841(sb_info_t *si);
12084 +
12085 +/* delay needed between the mdio control/ mdiodata register data access */
12086 +#define PR28829_DELAY() OSL_DELAY(10)
12087 +
12088 +/* size that can take bitfielddump */
12089 +#define BITFIELD_DUMP_SIZE 32
12090 +
12091 +/* global variable to indicate reservation/release of gpio's */
12092 +static uint32 sb_gpioreservation = 0;
12093 +
12094 +#define SB_INFO(sbh) (sb_info_t*)sbh
12095 +#define SET_SBREG(si, r, mask, val) \
12096 + W_SBREG((si), (r), ((R_SBREG((si), (r)) & ~(mask)) | (val)))
12097 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && \
12098 + ISALIGNED((x), SB_CORE_SIZE))
12099 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
12100 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
12101 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
12102 +#define BADIDX (SB_MAXCORES+1)
12103 +#define NOREV -1 /* Invalid rev */
12104 +
12105 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
12106 +#define PCIE(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCIE))
12107 +
12108 +/* sonicsrev */
12109 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
12110 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
12111 +
12112 +#define R_SBREG(si, sbr) sb_read_sbreg((si), (sbr))
12113 +#define W_SBREG(si, sbr, v) sb_write_sbreg((si), (sbr), (v))
12114 +#define AND_SBREG(si, sbr, v) W_SBREG((si), (sbr), (R_SBREG((si), (sbr)) & (v)))
12115 +#define OR_SBREG(si, sbr, v) W_SBREG((si), (sbr), (R_SBREG((si), (sbr)) | (v)))
12116 +
12117 +/*
12118 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
12119 + * after core switching to avoid invalid register accesss inside ISR.
12120 + */
12121 +#define INTR_OFF(si, intr_val) \
12122 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
12123 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
12124 +#define INTR_RESTORE(si, intr_val) \
12125 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
12126 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
12127 +
12128 +/* dynamic clock control defines */
12129 +#define LPOMINFREQ 25000 /* low power oscillator min */
12130 +#define LPOMAXFREQ 43000 /* low power oscillator max */
12131 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
12132 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
12133 +#define PCIMINFREQ 25000000 /* 25 MHz */
12134 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
12135 +
12136 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
12137 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
12138 +
12139 +/* different register spaces to access thr'u pcie indirect access */
12140 +#define PCIE_CONFIGREGS 1 /* Access to config space */
12141 +#define PCIE_PCIEREGS 2 /* Access to pcie registers */
12142 +
12143 +/* GPIO Based LED powersave defines */
12144 +#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
12145 +#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
12146 +
12147 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
12148 +
12149 +static uint32
12150 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
12151 +{
12152 + uint8 tmp;
12153 + uint32 val, intr_val = 0;
12154 +
12155 +
12156 + /*
12157 + * compact flash only has 11 bits address, while we needs 12 bits address.
12158 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
12159 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
12160 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
12161 + */
12162 + if (si->memseg) {
12163 + INTR_OFF(si, intr_val);
12164 + tmp = 1;
12165 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12166 + sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
12167 + }
12168 +
12169 + val = R_REG(si->osh, sbr);
12170 +
12171 + if (si->memseg) {
12172 + tmp = 0;
12173 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12174 + INTR_RESTORE(si, intr_val);
12175 + }
12176 +
12177 + return (val);
12178 +}
12179 +
12180 +static void
12181 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
12182 +{
12183 + uint8 tmp;
12184 + volatile uint32 dummy;
12185 + uint32 intr_val = 0;
12186 +
12187 +
12188 + /*
12189 + * compact flash only has 11 bits address, while we needs 12 bits address.
12190 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
12191 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
12192 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
12193 + */
12194 + if (si->memseg) {
12195 + INTR_OFF(si, intr_val);
12196 + tmp = 1;
12197 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12198 + sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
12199 + }
12200 +
12201 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12202 +#ifdef IL_BIGENDIAN
12203 + dummy = R_REG(si->osh, sbr);
12204 + W_REG(si->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
12205 + dummy = R_REG(si->osh, sbr);
12206 + W_REG(si->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
12207 +#else
12208 + dummy = R_REG(si->osh, sbr);
12209 + W_REG(si->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
12210 + dummy = R_REG(si->osh, sbr);
12211 + W_REG(si->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
12212 +#endif /* IL_BIGENDIAN */
12213 + } else
12214 + W_REG(si->osh, sbr, v);
12215 +
12216 + if (si->memseg) {
12217 + tmp = 0;
12218 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12219 + INTR_RESTORE(si, intr_val);
12220 + }
12221 +}
12222 +
12223 +/*
12224 + * Allocate a sb handle.
12225 + * devid - pci device id (used to determine chip#)
12226 + * osh - opaque OS handle
12227 + * regs - virtual address of initial core registers
12228 + * bustype - pci/pcmcia/sb/sdio/etc
12229 + * vars - pointer to a pointer area for "environment" variables
12230 + * varsz - pointer to int to return the size of the vars
12231 + */
12232 +sb_t *
12233 +BCMINITFN(sb_attach)(uint devid, osl_t *osh, void *regs,
12234 + uint bustype, void *sdh, char **vars, uint *varsz)
12235 +{
12236 + sb_info_t *si;
12237 +
12238 + /* alloc sb_info_t */
12239 + if ((si = MALLOC(osh, sizeof (sb_info_t))) == NULL) {
12240 + SB_ERROR(("sb_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
12241 + return (NULL);
12242 + }
12243 +
12244 + if (sb_doattach(si, devid, osh, regs, bustype, sdh, vars, (uint*)varsz) == NULL) {
12245 + MFREE(osh, si, sizeof(sb_info_t));
12246 + return (NULL);
12247 + }
12248 +
12249 + return (sb_t *)si;
12250 +}
12251 +
12252 +/* Using sb_kattach depends on SB_BUS support, either implicit */
12253 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
12254 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
12255 +
12256 +/* global kernel resource */
12257 +static sb_info_t ksi;
12258 +static bool ksi_attached = FALSE;
12259 +
12260 +/* generic kernel variant of sb_attach() */
12261 +sb_t *
12262 +BCMINITFN(sb_kattach)(void)
12263 +{
12264 + osl_t *osh = NULL;
12265 + uint32 *regs;
12266 +
12267 + if (!ksi_attached) {
12268 + uint32 cid;
12269 +
12270 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
12271 + cid = R_REG(osh, (uint32 *)regs);
12272 + if (((cid & CID_ID_MASK) == BCM4712_CHIP_ID) &&
12273 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
12274 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
12275 + uint32 *scc, val;
12276 +
12277 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
12278 + val = R_REG(osh, scc);
12279 + SB_ERROR((" initial scc = 0x%x\n", val));
12280 + val |= SCC_SS_XTAL;
12281 + W_REG(osh, scc, val);
12282 + }
12283 +
12284 + if (sb_doattach(&ksi, BCM4710_DEVICE_ID, osh, (void*)regs,
12285 + SB_BUS, NULL, NULL, NULL) == NULL) {
12286 + return NULL;
12287 + }
12288 + else
12289 + ksi_attached = TRUE;
12290 + }
12291 +
12292 + return (sb_t *)&ksi;
12293 +}
12294 +#endif /* !BCMBUSTYPE || (BCMBUSTYPE == SB_BUS) */
12295 +
12296 +static sb_info_t *
12297 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
12298 + uint bustype, void *sdh, char **vars, uint *varsz)
12299 +{
12300 + uint origidx;
12301 + chipcregs_t *cc;
12302 + sbconfig_t *sb;
12303 + uint32 w;
12304 +
12305 + ASSERT(GOODREGS(regs));
12306 +
12307 + bzero((uchar*)si, sizeof(sb_info_t));
12308 +
12309 + si->sb.buscoreidx = si->gpioidx = BADIDX;
12310 +
12311 + si->curmap = regs;
12312 + si->sdh = sdh;
12313 + si->osh = osh;
12314 +
12315 + /* check to see if we are a sb core mimic'ing a pci core */
12316 + if (bustype == PCI_BUS) {
12317 + if (OSL_PCI_READ_CONFIG(si->osh, PCI_SPROM_CONTROL, sizeof(uint32)) == 0xffffffff) {
12318 + SB_ERROR(("%s: incoming bus is PCI but it's a lie, switching to SB "
12319 + "devid:0x%x\n", __FUNCTION__, devid));
12320 + bustype = SB_BUS;
12321 + }
12322 + }
12323 +
12324 + si->sb.bustype = bustype;
12325 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
12326 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
12327 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
12328 + return NULL;
12329 + }
12330 +
12331 + /* need to set memseg flag for CF card first before any sb registers access */
12332 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
12333 + si->memseg = TRUE;
12334 +
12335 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
12336 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
12337 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
12338 +
12339 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12340 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32));
12341 + if (!GOODCOREADDR(w))
12342 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32), SB_ENUM_BASE);
12343 + }
12344 +
12345 + /* initialize current core index value */
12346 + si->curidx = _sb_coreidx(si);
12347 +
12348 + if (si->curidx == BADIDX) {
12349 + SB_ERROR(("sb_doattach: bad core index\n"));
12350 + return NULL;
12351 + }
12352 +
12353 + /* get sonics backplane revision */
12354 + sb = REGS2SB(si->curmap);
12355 + si->sb.sonicsrev = (R_SBREG(si, &sb->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
12356 +
12357 + /* keep and reuse the initial register mapping */
12358 + origidx = si->curidx;
12359 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
12360 + si->regs[origidx] = regs;
12361 +
12362 + /* is core-0 a chipcommon core? */
12363 + si->numcores = 1;
12364 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
12365 + if (sb_coreid(&si->sb) != SB_CC)
12366 + cc = NULL;
12367 +
12368 + /* determine chip id and rev */
12369 + if (cc) {
12370 + /* chip common core found! */
12371 + si->sb.chip = R_REG(si->osh, &cc->chipid) & CID_ID_MASK;
12372 + si->sb.chiprev = (R_REG(si->osh, &cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
12373 + si->sb.chippkg = (R_REG(si->osh, &cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
12374 + } else {
12375 + /* no chip common core -- must convert device id to chip id */
12376 + if ((si->sb.chip = sb_pcidev2chip(devid)) == 0) {
12377 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
12378 + sb_setcoreidx(&si->sb, origidx);
12379 + return NULL;
12380 + }
12381 + }
12382 +
12383 + /* get chipcommon rev */
12384 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
12385 +
12386 + /* determine numcores */
12387 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
12388 + si->numcores = (R_REG(si->osh, &cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
12389 + else
12390 + si->numcores = sb_chip2numcores(si->sb.chip);
12391 +
12392 + /* return to original core */
12393 + sb_setcoreidx(&si->sb, origidx);
12394 +
12395 + /* sanity checks */
12396 + ASSERT(si->sb.chip);
12397 +
12398 + /* scan for cores */
12399 + sb_scan(si);
12400 +
12401 + /* fixup necessary chip/core configurations */
12402 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12403 + if (sb_pci_fixcfg(si)) {
12404 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
12405 + return NULL;
12406 + }
12407 + }
12408 +
12409 + /* srom_var_init() depends on sb_scan() info */
12410 + if (srom_var_init(si, si->sb.bustype, si->curmap, si->osh, vars, varsz)) {
12411 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
12412 + return (NULL);
12413 + }
12414 +
12415 + if (cc == NULL) {
12416 + /*
12417 + * The chip revision number is hardwired into all
12418 + * of the pci function config rev fields and is
12419 + * independent from the individual core revision numbers.
12420 + * For example, the "A0" silicon of each chip is chip rev 0.
12421 + * For PCMCIA we get it from the CIS instead.
12422 + */
12423 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12424 + ASSERT(vars);
12425 + si->sb.chiprev = getintvar(*vars, "chiprev");
12426 + } else if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12427 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_REV, sizeof(uint32));
12428 + si->sb.chiprev = w & 0xff;
12429 + } else
12430 + si->sb.chiprev = 0;
12431 + }
12432 +
12433 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12434 + w = getintvar(*vars, "regwindowsz");
12435 + si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
12436 + }
12437 +
12438 + /* gpio control core is required */
12439 + if (!GOODIDX(si->gpioidx)) {
12440 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
12441 + return NULL;
12442 + }
12443 +
12444 + /* get boardtype and boardrev */
12445 + switch (BUSTYPE(si->sb.bustype)) {
12446 + case PCI_BUS:
12447 + /* do a pci config read to get subsystem id and subvendor id */
12448 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_SVID, sizeof(uint32));
12449 + si->sb.boardvendor = w & 0xffff;
12450 + si->sb.boardtype = (w >> 16) & 0xffff;
12451 + break;
12452 +
12453 + case PCMCIA_BUS:
12454 + case SDIO_BUS:
12455 + si->sb.boardvendor = getintvar(*vars, "manfid");
12456 + si->sb.boardtype = getintvar(*vars, "prodid");
12457 + break;
12458 +
12459 + case SB_BUS:
12460 + case JTAG_BUS:
12461 + si->sb.boardvendor = VENDOR_BROADCOM;
12462 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
12463 + si->sb.boardtype = 0xffff;
12464 + break;
12465 + }
12466 +
12467 + if (si->sb.boardtype == 0) {
12468 + SB_ERROR(("sb_doattach: unknown board type\n"));
12469 + ASSERT(si->sb.boardtype);
12470 + }
12471 +
12472 + /* setup the GPIO based LED powersave register */
12473 + if (si->sb.ccrev >= 16) {
12474 + if ((vars == NULL) || ((w = getintvar(*vars, "leddc")) == 0))
12475 + w = DEFAULT_GPIOTIMERVAL;
12476 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
12477 + }
12478 + if ((si->sb.chip == BCM4311_CHIP_ID) && (si->sb.chiprev <= 1)) {
12479 + /* set proper clk setup delays before forcing HT */
12480 + sb_clkctl_init((void *)si);
12481 + sb_corereg((void*)si, SB_CC_IDX, OFFSETOF(chipcregs_t, system_clk_ctl),
12482 + SYCC_HR, SYCC_HR);
12483 + }
12484 +
12485 +
12486 + return (si);
12487 +}
12488 +
12489 +uint
12490 +sb_coreid(sb_t *sbh)
12491 +{
12492 + sb_info_t *si;
12493 + sbconfig_t *sb;
12494 +
12495 + si = SB_INFO(sbh);
12496 + sb = REGS2SB(si->curmap);
12497 +
12498 + return ((R_SBREG(si, &sb->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
12499 +}
12500 +
12501 +uint
12502 +sb_coreidx(sb_t *sbh)
12503 +{
12504 + sb_info_t *si;
12505 +
12506 + si = SB_INFO(sbh);
12507 + return (si->curidx);
12508 +}
12509 +
12510 +/* return current index of core */
12511 +static uint
12512 +_sb_coreidx(sb_info_t *si)
12513 +{
12514 + sbconfig_t *sb;
12515 + uint32 sbaddr = 0;
12516 +
12517 + ASSERT(si);
12518 +
12519 + switch (BUSTYPE(si->sb.bustype)) {
12520 + case SB_BUS:
12521 + sb = REGS2SB(si->curmap);
12522 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
12523 + break;
12524 +
12525 + case PCI_BUS:
12526 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32));
12527 + break;
12528 +
12529 + case PCMCIA_BUS: {
12530 + uint8 tmp = 0;
12531 +
12532 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
12533 + sbaddr = (uint)tmp << 12;
12534 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
12535 + sbaddr |= (uint)tmp << 16;
12536 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
12537 + sbaddr |= (uint)tmp << 24;
12538 + break;
12539 + }
12540 +
12541 +#ifdef BCMJTAG
12542 + case JTAG_BUS:
12543 + sbaddr = (uint32)si->curmap;
12544 + break;
12545 +#endif /* BCMJTAG */
12546 +
12547 + default:
12548 + ASSERT(0);
12549 + }
12550 +
12551 + if (!GOODCOREADDR(sbaddr))
12552 + return BADIDX;
12553 +
12554 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
12555 +}
12556 +
12557 +uint
12558 +sb_corevendor(sb_t *sbh)
12559 +{
12560 + sb_info_t *si;
12561 + sbconfig_t *sb;
12562 +
12563 + si = SB_INFO(sbh);
12564 + sb = REGS2SB(si->curmap);
12565 +
12566 + return ((R_SBREG(si, &sb->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
12567 +}
12568 +
12569 +uint
12570 +sb_corerev(sb_t *sbh)
12571 +{
12572 + sb_info_t *si;
12573 + sbconfig_t *sb;
12574 + uint sbidh;
12575 +
12576 + si = SB_INFO(sbh);
12577 + sb = REGS2SB(si->curmap);
12578 + sbidh = R_SBREG(si, &sb->sbidhigh);
12579 +
12580 + return (SBCOREREV(sbidh));
12581 +}
12582 +
12583 +void *
12584 +sb_osh(sb_t *sbh)
12585 +{
12586 + sb_info_t *si;
12587 +
12588 + si = SB_INFO(sbh);
12589 + return si->osh;
12590 +}
12591 +
12592 +void
12593 +sb_setosh(sb_t *sbh, osl_t *osh)
12594 +{
12595 + sb_info_t *si;
12596 +
12597 + si = SB_INFO(sbh);
12598 + if (si->osh != NULL) {
12599 + SB_ERROR(("osh is already set....\n"));
12600 + ASSERT(!si->osh);
12601 + }
12602 + si->osh = osh;
12603 +}
12604 +
12605 +/* set/clear sbtmstatelow core-specific flags */
12606 +uint32
12607 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
12608 +{
12609 + sb_info_t *si;
12610 + sbconfig_t *sb;
12611 + uint32 w;
12612 +
12613 + si = SB_INFO(sbh);
12614 + sb = REGS2SB(si->curmap);
12615 +
12616 + ASSERT((val & ~mask) == 0);
12617 +
12618 + /* mask and set */
12619 + if (mask || val) {
12620 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
12621 + W_SBREG(si, &sb->sbtmstatelow, w);
12622 + }
12623 +
12624 + /* return the new value */
12625 + return (R_SBREG(si, &sb->sbtmstatelow));
12626 +}
12627 +
12628 +/* set/clear sbtmstatehigh core-specific flags */
12629 +uint32
12630 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
12631 +{
12632 + sb_info_t *si;
12633 + sbconfig_t *sb;
12634 + uint32 w;
12635 +
12636 + si = SB_INFO(sbh);
12637 + sb = REGS2SB(si->curmap);
12638 +
12639 + ASSERT((val & ~mask) == 0);
12640 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
12641 +
12642 + /* mask and set */
12643 + if (mask || val) {
12644 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
12645 + W_SBREG(si, &sb->sbtmstatehigh, w);
12646 + }
12647 +
12648 + /* return the new value */
12649 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
12650 +}
12651 +
12652 +/* Run bist on current core. Caller needs to take care of core-specific bist hazards */
12653 +int
12654 +sb_corebist(sb_t *sbh)
12655 +{
12656 + uint32 sblo;
12657 + sb_info_t *si;
12658 + sbconfig_t *sb;
12659 + int result = 0;
12660 +
12661 + si = SB_INFO(sbh);
12662 + sb = REGS2SB(si->curmap);
12663 +
12664 + sblo = R_SBREG(si, &sb->sbtmstatelow);
12665 + W_SBREG(si, &sb->sbtmstatelow, (sblo | SBTML_FGC | SBTML_BE));
12666 +
12667 + SPINWAIT(((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BISTD) == 0), 100000);
12668 +
12669 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BISTF)
12670 + result = BCME_ERROR;
12671 +
12672 + W_SBREG(si, &sb->sbtmstatelow, sblo);
12673 +
12674 + return result;
12675 +}
12676 +
12677 +bool
12678 +sb_iscoreup(sb_t *sbh)
12679 +{
12680 + sb_info_t *si;
12681 + sbconfig_t *sb;
12682 +
12683 + si = SB_INFO(sbh);
12684 + sb = REGS2SB(si->curmap);
12685 +
12686 + return ((R_SBREG(si, &sb->sbtmstatelow) &
12687 + (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
12688 +}
12689 +
12690 +/*
12691 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
12692 + * switch back to the original core, and return the new value.
12693 + *
12694 + * When using the silicon backplane, no fidleing with interrupts or core switches are needed.
12695 + *
12696 + * Also, when using pci/pcie, we can optimize away the core switching for pci registers
12697 + * and (on newer pci cores) chipcommon registers.
12698 + */
12699 +static uint
12700 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
12701 +{
12702 + uint origidx = 0;
12703 + uint32 *r = NULL;
12704 + uint w;
12705 + uint intr_val = 0;
12706 + bool fast = FALSE;
12707 +
12708 + ASSERT(GOODIDX(coreidx));
12709 + ASSERT(regoff < SB_CORE_SIZE);
12710 + ASSERT((val & ~mask) == 0);
12711 +
12712 +#ifdef notyet
12713 + if (si->sb.bustype == SB_BUS) {
12714 + /* If internal bus, we can always get at everything */
12715 + fast = TRUE;
12716 + r = (uint32 *)((uchar *)si->regs[coreidx] + regoff);
12717 + } else if (si->sb.bustype == PCI_BUS) {
12718 + /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
12719 +
12720 + if ((si->coreid[coreidx] == SB_CC) &&
12721 + ((si->sb.buscoretype == SB_PCIE) ||
12722 + (si->sb.buscorerev >= 13))) {
12723 + /* Chipc registers are mapped at 12KB */
12724 +
12725 + fast = TRUE;
12726 + r = (uint32 *)((char *)si->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
12727 + } else if (si->sb.buscoreidx == coreidx) {
12728 + /* pci registers are at either in the last 2KB of an 8KB window
12729 + * or, in pcie and pci rev 13 at 8KB
12730 + */
12731 + fast = TRUE;
12732 + if ((si->sb.buscoretype == SB_PCIE) ||
12733 + (si->sb.buscorerev >= 13))
12734 + r = (uint32 *)((char *)si->curmap +
12735 + PCI_16KB0_PCIREGS_OFFSET + regoff);
12736 + else
12737 + r = (uint32 *)((char *)si->curmap +
12738 + ((regoff >= SBCONFIGOFF) ?
12739 + PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
12740 + regoff);
12741 + }
12742 + }
12743 +#endif /* notyet */
12744 +
12745 + if (!fast) {
12746 + INTR_OFF(si, intr_val);
12747 +
12748 + /* save current core index */
12749 + origidx = sb_coreidx(&si->sb);
12750 +
12751 + /* switch core */
12752 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
12753 + }
12754 + ASSERT(r);
12755 +
12756 + /* mask and set */
12757 + if (mask || val) {
12758 + if (regoff >= SBCONFIGOFF) {
12759 + w = (R_SBREG(si, r) & ~mask) | val;
12760 + W_SBREG(si, r, w);
12761 + } else {
12762 + w = (R_REG(si->osh, r) & ~mask) | val;
12763 + W_REG(si->osh, r, w);
12764 + }
12765 + }
12766 +
12767 + /* readback */
12768 + if (regoff >= SBCONFIGOFF)
12769 + w = R_SBREG(si, r);
12770 + else
12771 + w = R_REG(si->osh, r);
12772 +
12773 + if (!fast) {
12774 + /* restore core index */
12775 + if (origidx != coreidx)
12776 + sb_setcoreidx(&si->sb, origidx);
12777 +
12778 + INTR_RESTORE(si, intr_val);
12779 + }
12780 +
12781 + return (w);
12782 +}
12783 +
12784 +#define DWORD_ALIGN(x) (x & ~(0x03))
12785 +#define BYTE_POS(x) (x & 0x3)
12786 +#define WORD_POS(x) (x & 0x1)
12787 +
12788 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
12789 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
12790 +
12791 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
12792 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
12793 +
12794 +#define read_pci_cfg_byte(a) \
12795 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
12796 +
12797 +#define read_pci_cfg_write(a) \
12798 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
12799 +
12800 +
12801 +/* return TRUE if requested capability exists in the PCI config space */
12802 +static bool
12803 +sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen)
12804 +{
12805 + uint8 cap_id;
12806 + uint8 cap_ptr;
12807 + uint32 bufsize;
12808 + uint8 byte_val;
12809 +
12810 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
12811 + return FALSE;
12812 +
12813 + /* check for Header type 0 */
12814 + byte_val = read_pci_cfg_byte(PCI_CFG_HDR);
12815 + if ((byte_val & 0x7f) != PCI_HEADER_NORMAL)
12816 + return FALSE;
12817 +
12818 + /* check if the capability pointer field exists */
12819 + byte_val = read_pci_cfg_byte(PCI_CFG_STAT);
12820 + if (!(byte_val & PCI_CAPPTR_PRESENT))
12821 + return FALSE;
12822 +
12823 + cap_ptr = read_pci_cfg_byte(PCI_CFG_CAPPTR);
12824 + /* check if the capability pointer is 0x00 */
12825 + if (cap_ptr == 0x00)
12826 + return FALSE;
12827 +
12828 +
12829 + /* loop thr'u the capability list and see if the pcie capabilty exists */
12830 +
12831 + cap_id = read_pci_cfg_byte(cap_ptr);
12832 +
12833 + while (cap_id != req_cap_id) {
12834 + cap_ptr = read_pci_cfg_byte((cap_ptr+1));
12835 + if (cap_ptr == 0x00) break;
12836 + cap_id = read_pci_cfg_byte(cap_ptr);
12837 + }
12838 + if (cap_id != req_cap_id) {
12839 + return FALSE;
12840 + }
12841 + /* found the caller requested capability */
12842 + if ((buf != NULL) && (buflen != NULL)) {
12843 + bufsize = *buflen;
12844 + if (!bufsize) goto end;
12845 + *buflen = 0;
12846 + /* copy the cpability data excluding cap ID and next ptr */
12847 + cap_ptr += 2;
12848 + if ((bufsize + cap_ptr) > SZPCR)
12849 + bufsize = SZPCR - cap_ptr;
12850 + *buflen = bufsize;
12851 + while (bufsize--) {
12852 + *buf = read_pci_cfg_byte(cap_ptr);
12853 + cap_ptr++;
12854 + buf++;
12855 + }
12856 + }
12857 +end:
12858 + return TRUE;
12859 +}
12860 +
12861 +/* return TRUE if PCIE capability exists the pci config space */
12862 +static inline bool
12863 +sb_ispcie(sb_info_t *si)
12864 +{
12865 + return (sb_find_pci_capability(si, PCI_CAP_PCIECAP_ID, NULL, NULL));
12866 +}
12867 +
12868 +/* scan the sb enumerated space to identify all cores */
12869 +static void
12870 +BCMINITFN(sb_scan)(sb_info_t *si)
12871 +{
12872 + uint origidx;
12873 + uint i;
12874 + bool pci;
12875 + bool pcie;
12876 + uint pciidx;
12877 + uint pcieidx;
12878 + uint pcirev;
12879 + uint pcierev;
12880 +
12881 +
12882 + /* numcores should already be set */
12883 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
12884 +
12885 + /* save current core index */
12886 + origidx = sb_coreidx(&si->sb);
12887 +
12888 + si->sb.buscorerev = NOREV;
12889 + si->sb.buscoreidx = BADIDX;
12890 +
12891 + si->gpioidx = BADIDX;
12892 +
12893 + pci = pcie = FALSE;
12894 + pcirev = pcierev = NOREV;
12895 + pciidx = pcieidx = BADIDX;
12896 +
12897 + for (i = 0; i < si->numcores; i++) {
12898 + sb_setcoreidx(&si->sb, i);
12899 + si->coreid[i] = sb_coreid(&si->sb);
12900 +
12901 + if (si->coreid[i] == SB_PCI) {
12902 + pciidx = i;
12903 + pcirev = sb_corerev(&si->sb);
12904 + pci = TRUE;
12905 + } else if (si->coreid[i] == SB_PCIE) {
12906 + pcieidx = i;
12907 + pcierev = sb_corerev(&si->sb);
12908 + pcie = TRUE;
12909 + } else if (si->coreid[i] == SB_PCMCIA) {
12910 + si->sb.buscorerev = sb_corerev(&si->sb);
12911 + si->sb.buscoretype = si->coreid[i];
12912 + si->sb.buscoreidx = i;
12913 + }
12914 + }
12915 + if (pci && pcie) {
12916 + if (sb_ispcie(si))
12917 + pci = FALSE;
12918 + else
12919 + pcie = FALSE;
12920 + }
12921 + if (pci) {
12922 + si->sb.buscoretype = SB_PCI;
12923 + si->sb.buscorerev = pcirev;
12924 + si->sb.buscoreidx = pciidx;
12925 + } else if (pcie) {
12926 + si->sb.buscoretype = SB_PCIE;
12927 + si->sb.buscorerev = pcierev;
12928 + si->sb.buscoreidx = pcieidx;
12929 + }
12930 +
12931 + /*
12932 + * Find the gpio "controlling core" type and index.
12933 + * Precedence:
12934 + * - if there's a chip common core - use that
12935 + * - else if there's a pci core (rev >= 2) - use that
12936 + * - else there had better be an extif core (4710 only)
12937 + */
12938 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
12939 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
12940 + si->gpioid = SB_CC;
12941 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
12942 + si->gpioidx = si->sb.buscoreidx;
12943 + si->gpioid = SB_PCI;
12944 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
12945 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
12946 + si->gpioid = SB_EXTIF;
12947 + } else
12948 + ASSERT(si->gpioidx != BADIDX);
12949 +
12950 + /* return to original core index */
12951 + sb_setcoreidx(&si->sb, origidx);
12952 +}
12953 +
12954 +/* may be called with core in reset */
12955 +void
12956 +sb_detach(sb_t *sbh)
12957 +{
12958 + sb_info_t *si;
12959 + uint idx;
12960 +
12961 + si = SB_INFO(sbh);
12962 +
12963 + if (si == NULL)
12964 + return;
12965 +
12966 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
12967 + for (idx = 0; idx < SB_MAXCORES; idx++)
12968 + if (si->regs[idx]) {
12969 + REG_UNMAP(si->regs[idx]);
12970 + si->regs[idx] = NULL;
12971 + }
12972 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
12973 + if (si != &ksi)
12974 +#endif /* !BCMBUSTYPE || (BCMBUSTYPE == SB_BUS) */
12975 + MFREE(si->osh, si, sizeof(sb_info_t));
12976 +
12977 +}
12978 +
12979 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
12980 +static uint
12981 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
12982 +{
12983 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
12984 + return (BCM4710_CHIP_ID);
12985 + if ((pcidev >= BCM4402_ENET_ID) && (pcidev <= BCM4402_V90_ID))
12986 + return (BCM4402_CHIP_ID);
12987 + if (pcidev == BCM4401_ENET_ID)
12988 + return (BCM4402_CHIP_ID);
12989 +
12990 + return (0);
12991 +}
12992 +
12993 +/* convert chip number to number of i/o cores */
12994 +static uint
12995 +BCMINITFN(sb_chip2numcores)(uint chip)
12996 +{
12997 + if (chip == BCM4710_CHIP_ID)
12998 + return (9);
12999 + if (chip == BCM4402_CHIP_ID)
13000 + return (3);
13001 + if (chip == BCM4306_CHIP_ID) /* < 4306c0 */
13002 + return (6);
13003 + if (chip == BCM4704_CHIP_ID)
13004 + return (9);
13005 + if (chip == BCM5365_CHIP_ID)
13006 + return (7);
13007 +
13008 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
13009 + ASSERT(0);
13010 + return (1);
13011 +}
13012 +
13013 +/* return index of coreid or BADIDX if not found */
13014 +static uint
13015 +sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit)
13016 +{
13017 + uint found;
13018 + uint i;
13019 +
13020 + found = 0;
13021 +
13022 + for (i = 0; i < si->numcores; i++)
13023 + if (si->coreid[i] == coreid) {
13024 + if (found == coreunit)
13025 + return (i);
13026 + found++;
13027 + }
13028 +
13029 + return (BADIDX);
13030 +}
13031 +
13032 +/*
13033 + * this function changes logical "focus" to the indiciated core,
13034 + * must be called with interrupt off.
13035 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
13036 + */
13037 +void*
13038 +sb_setcoreidx(sb_t *sbh, uint coreidx)
13039 +{
13040 + sb_info_t *si;
13041 + uint32 sbaddr;
13042 + uint8 tmp;
13043 +
13044 + si = SB_INFO(sbh);
13045 +
13046 + if (coreidx >= si->numcores)
13047 + return (NULL);
13048 +
13049 + /*
13050 + * If the user has provided an interrupt mask enabled function,
13051 + * then assert interrupts are disabled before switching the core.
13052 + */
13053 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
13054 +
13055 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
13056 +
13057 + switch (BUSTYPE(si->sb.bustype)) {
13058 + case SB_BUS:
13059 + /* map new one */
13060 + if (!si->regs[coreidx]) {
13061 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
13062 + ASSERT(GOODREGS(si->regs[coreidx]));
13063 + }
13064 + si->curmap = si->regs[coreidx];
13065 + break;
13066 +
13067 + case PCI_BUS:
13068 + /* point bar0 window */
13069 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
13070 + break;
13071 +
13072 + case PCMCIA_BUS:
13073 + tmp = (sbaddr >> 12) & 0x0f;
13074 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
13075 + tmp = (sbaddr >> 16) & 0xff;
13076 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
13077 + tmp = (sbaddr >> 24) & 0xff;
13078 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
13079 + break;
13080 +#ifdef BCMJTAG
13081 + case JTAG_BUS:
13082 + /* map new one */
13083 + if (!si->regs[coreidx]) {
13084 + si->regs[coreidx] = (void *)sbaddr;
13085 + ASSERT(GOODREGS(si->regs[coreidx]));
13086 + }
13087 + si->curmap = si->regs[coreidx];
13088 + break;
13089 +#endif /* BCMJTAG */
13090 + }
13091 +
13092 + si->curidx = coreidx;
13093 +
13094 + return (si->curmap);
13095 +}
13096 +
13097 +/*
13098 + * this function changes logical "focus" to the indiciated core,
13099 + * must be called with interrupt off.
13100 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
13101 + */
13102 +void*
13103 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
13104 +{
13105 + sb_info_t *si;
13106 + uint idx;
13107 +
13108 + si = SB_INFO(sbh);
13109 + idx = sb_findcoreidx(si, coreid, coreunit);
13110 + if (!GOODIDX(idx))
13111 + return (NULL);
13112 +
13113 + return (sb_setcoreidx(sbh, idx));
13114 +}
13115 +
13116 +/* return chip number */
13117 +uint
13118 +sb_chip(sb_t *sbh)
13119 +{
13120 + sb_info_t *si;
13121 +
13122 + si = SB_INFO(sbh);
13123 + return (si->sb.chip);
13124 +}
13125 +
13126 +/* return chip revision number */
13127 +uint
13128 +sb_chiprev(sb_t *sbh)
13129 +{
13130 + sb_info_t *si;
13131 +
13132 + si = SB_INFO(sbh);
13133 + return (si->sb.chiprev);
13134 +}
13135 +
13136 +/* return chip common revision number */
13137 +uint
13138 +sb_chipcrev(sb_t *sbh)
13139 +{
13140 + sb_info_t *si;
13141 +
13142 + si = SB_INFO(sbh);
13143 + return (si->sb.ccrev);
13144 +}
13145 +
13146 +/* return chip package option */
13147 +uint
13148 +sb_chippkg(sb_t *sbh)
13149 +{
13150 + sb_info_t *si;
13151 +
13152 + si = SB_INFO(sbh);
13153 + return (si->sb.chippkg);
13154 +}
13155 +
13156 +/* return PCI core rev. */
13157 +uint
13158 +sb_pcirev(sb_t *sbh)
13159 +{
13160 + sb_info_t *si;
13161 +
13162 + si = SB_INFO(sbh);
13163 + return (si->sb.buscorerev);
13164 +}
13165 +
13166 +bool
13167 +BCMINITFN(sb_war16165)(sb_t *sbh)
13168 +{
13169 + sb_info_t *si;
13170 +
13171 + si = SB_INFO(sbh);
13172 +
13173 + return (PCI(si) && (si->sb.buscorerev <= 10));
13174 +}
13175 +
13176 +static void
13177 +BCMINITFN(sb_war30841)(sb_info_t *si)
13178 +{
13179 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
13180 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
13181 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
13182 +}
13183 +
13184 +/* return PCMCIA core rev. */
13185 +uint
13186 +BCMINITFN(sb_pcmciarev)(sb_t *sbh)
13187 +{
13188 + sb_info_t *si;
13189 +
13190 + si = SB_INFO(sbh);
13191 + return (si->sb.buscorerev);
13192 +}
13193 +
13194 +/* return board vendor id */
13195 +uint
13196 +sb_boardvendor(sb_t *sbh)
13197 +{
13198 + sb_info_t *si;
13199 +
13200 + si = SB_INFO(sbh);
13201 + return (si->sb.boardvendor);
13202 +}
13203 +
13204 +/* return boardtype */
13205 +uint
13206 +sb_boardtype(sb_t *sbh)
13207 +{
13208 + sb_info_t *si;
13209 + char *var;
13210 +
13211 + si = SB_INFO(sbh);
13212 +
13213 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
13214 + /* boardtype format is a hex string */
13215 + si->sb.boardtype = getintvar(NULL, "boardtype");
13216 +
13217 + /* backward compatibility for older boardtype string format */
13218 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
13219 + if (!strcmp(var, "bcm94710dev"))
13220 + si->sb.boardtype = BCM94710D_BOARD;
13221 + else if (!strcmp(var, "bcm94710ap"))
13222 + si->sb.boardtype = BCM94710AP_BOARD;
13223 + else if (!strcmp(var, "bu4710"))
13224 + si->sb.boardtype = BU4710_BOARD;
13225 + else if (!strcmp(var, "bcm94702mn"))
13226 + si->sb.boardtype = BCM94702MN_BOARD;
13227 + else if (!strcmp(var, "bcm94710r1"))
13228 + si->sb.boardtype = BCM94710R1_BOARD;
13229 + else if (!strcmp(var, "bcm94710r4"))
13230 + si->sb.boardtype = BCM94710R4_BOARD;
13231 + else if (!strcmp(var, "bcm94702cpci"))
13232 + si->sb.boardtype = BCM94702CPCI_BOARD;
13233 + else if (!strcmp(var, "bcm95380_rr"))
13234 + si->sb.boardtype = BCM95380RR_BOARD;
13235 + }
13236 + }
13237 +
13238 + return (si->sb.boardtype);
13239 +}
13240 +
13241 +/* return bus type of sbh device */
13242 +uint
13243 +sb_bus(sb_t *sbh)
13244 +{
13245 + sb_info_t *si;
13246 +
13247 + si = SB_INFO(sbh);
13248 + return (si->sb.bustype);
13249 +}
13250 +
13251 +/* return bus core type */
13252 +uint
13253 +sb_buscoretype(sb_t *sbh)
13254 +{
13255 + sb_info_t *si;
13256 +
13257 + si = SB_INFO(sbh);
13258 +
13259 + return (si->sb.buscoretype);
13260 +}
13261 +
13262 +/* return bus core revision */
13263 +uint
13264 +sb_buscorerev(sb_t *sbh)
13265 +{
13266 + sb_info_t *si;
13267 + si = SB_INFO(sbh);
13268 +
13269 + return (si->sb.buscorerev);
13270 +}
13271 +
13272 +/* return list of found cores */
13273 +uint
13274 +sb_corelist(sb_t *sbh, uint coreid[])
13275 +{
13276 + sb_info_t *si;
13277 +
13278 + si = SB_INFO(sbh);
13279 +
13280 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof(uint)));
13281 + return (si->numcores);
13282 +}
13283 +
13284 +/* return current register mapping */
13285 +void *
13286 +sb_coreregs(sb_t *sbh)
13287 +{
13288 + sb_info_t *si;
13289 +
13290 + si = SB_INFO(sbh);
13291 + ASSERT(GOODREGS(si->curmap));
13292 +
13293 + return (si->curmap);
13294 +}
13295 +
13296 +
13297 +/* do buffered registers update */
13298 +void
13299 +sb_commit(sb_t *sbh)
13300 +{
13301 + sb_info_t *si;
13302 + uint origidx;
13303 + uint intr_val = 0;
13304 +
13305 + si = SB_INFO(sbh);
13306 +
13307 + origidx = si->curidx;
13308 + ASSERT(GOODIDX(origidx));
13309 +
13310 + INTR_OFF(si, intr_val);
13311 +
13312 + /* switch over to chipcommon core if there is one, else use pci */
13313 + if (si->sb.ccrev != NOREV) {
13314 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
13315 +
13316 + /* do the buffer registers update */
13317 + W_REG(si->osh, &ccregs->broadcastaddress, SB_COMMIT);
13318 + W_REG(si->osh, &ccregs->broadcastdata, 0x0);
13319 + } else if (PCI(si)) {
13320 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
13321 +
13322 + /* do the buffer registers update */
13323 + W_REG(si->osh, &pciregs->bcastaddr, SB_COMMIT);
13324 + W_REG(si->osh, &pciregs->bcastdata, 0x0);
13325 + } else
13326 + ASSERT(0);
13327 +
13328 + /* restore core index */
13329 + sb_setcoreidx(sbh, origidx);
13330 + INTR_RESTORE(si, intr_val);
13331 +}
13332 +
13333 +/* reset and re-enable a core
13334 + * inputs:
13335 + * bits - core specific bits that are set during and after reset sequence
13336 + * resetbits - core specific bits that are set only during reset sequence
13337 + */
13338 +void
13339 +sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits)
13340 +{
13341 + sb_info_t *si;
13342 + sbconfig_t *sb;
13343 + volatile uint32 dummy;
13344 +
13345 + si = SB_INFO(sbh);
13346 + ASSERT(GOODREGS(si->curmap));
13347 + sb = REGS2SB(si->curmap);
13348 +
13349 + /*
13350 + * Must do the disable sequence first to work for arbitrary current core state.
13351 + */
13352 + sb_core_disable(sbh, (bits | resetbits));
13353 +
13354 + /*
13355 + * Now do the initialization sequence.
13356 + */
13357 +
13358 + /* set reset while enabling the clock and forcing them on throughout the core */
13359 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits | resetbits));
13360 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13361 + OSL_DELAY(1);
13362 +
13363 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
13364 + W_SBREG(si, &sb->sbtmstatehigh, 0);
13365 + }
13366 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
13367 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
13368 + }
13369 +
13370 + /* clear reset and allow it to propagate throughout the core */
13371 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
13372 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13373 + OSL_DELAY(1);
13374 +
13375 + /* leave clock enabled */
13376 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
13377 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13378 + OSL_DELAY(1);
13379 +}
13380 +
13381 +void
13382 +sb_core_tofixup(sb_t *sbh)
13383 +{
13384 + sb_info_t *si;
13385 + sbconfig_t *sb;
13386 +
13387 + si = SB_INFO(sbh);
13388 +
13389 + if ((BUSTYPE(si->sb.bustype) != PCI_BUS) || PCIE(si) ||
13390 + (PCI(si) && (si->sb.buscorerev >= 5)))
13391 + return;
13392 +
13393 + ASSERT(GOODREGS(si->curmap));
13394 + sb = REGS2SB(si->curmap);
13395 +
13396 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
13397 + SET_SBREG(si, &sb->sbimconfiglow,
13398 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13399 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
13400 + } else {
13401 + if (sb_coreid(sbh) == SB_PCI) {
13402 + SET_SBREG(si, &sb->sbimconfiglow,
13403 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13404 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
13405 + } else {
13406 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
13407 + }
13408 + }
13409 +
13410 + sb_commit(sbh);
13411 +}
13412 +
13413 +/*
13414 + * Set the initiator timeout for the "master core".
13415 + * The master core is defined to be the core in control
13416 + * of the chip and so it issues accesses to non-memory
13417 + * locations (Because of dma *any* core can access memeory).
13418 + *
13419 + * The routine uses the bus to decide who is the master:
13420 + * SB_BUS => mips
13421 + * JTAG_BUS => chipc
13422 + * PCI_BUS => pci or pcie
13423 + * PCMCIA_BUS => pcmcia
13424 + * SDIO_BUS => pcmcia
13425 + *
13426 + * This routine exists so callers can disable initiator
13427 + * timeouts so accesses to very slow devices like otp
13428 + * won't cause an abort. The routine allows arbitrary
13429 + * settings of the service and request timeouts, though.
13430 + *
13431 + * Returns the timeout state before changing it or -1
13432 + * on error.
13433 + */
13434 +
13435 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
13436 +
13437 +uint32
13438 +sb_set_initiator_to(sb_t *sbh, uint32 to)
13439 +{
13440 + sb_info_t *si;
13441 + uint origidx, idx;
13442 + uint intr_val = 0;
13443 + uint32 tmp, ret = 0xffffffff;
13444 + sbconfig_t *sb;
13445 +
13446 + si = SB_INFO(sbh);
13447 +
13448 + if ((to & ~TO_MASK) != 0)
13449 + return ret;
13450 +
13451 + /* Figure out the master core */
13452 + idx = BADIDX;
13453 + switch (BUSTYPE(si->sb.bustype)) {
13454 + case PCI_BUS:
13455 + idx = si->sb.buscoreidx;
13456 + break;
13457 + case JTAG_BUS:
13458 + idx = SB_CC_IDX;
13459 + break;
13460 + case PCMCIA_BUS:
13461 + case SDIO_BUS:
13462 + idx = sb_findcoreidx(si, SB_PCMCIA, 0);
13463 + break;
13464 + case SB_BUS:
13465 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
13466 + idx = sb_findcoreidx(si, SB_MIPS, 0);
13467 + break;
13468 + default:
13469 + ASSERT(0);
13470 + }
13471 + if (idx == BADIDX)
13472 + return ret;
13473 +
13474 + INTR_OFF(si, intr_val);
13475 + origidx = sb_coreidx(sbh);
13476 +
13477 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
13478 +
13479 + tmp = R_SBREG(si, &sb->sbimconfiglow);
13480 + ret = tmp & TO_MASK;
13481 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
13482 +
13483 + sb_commit(sbh);
13484 + sb_setcoreidx(sbh, origidx);
13485 + INTR_RESTORE(si, intr_val);
13486 + return ret;
13487 +}
13488 +
13489 +void
13490 +sb_core_disable(sb_t *sbh, uint32 bits)
13491 +{
13492 + sb_info_t *si;
13493 + volatile uint32 dummy;
13494 + uint32 rej;
13495 + sbconfig_t *sb;
13496 +
13497 + si = SB_INFO(sbh);
13498 +
13499 + ASSERT(GOODREGS(si->curmap));
13500 + sb = REGS2SB(si->curmap);
13501 +
13502 + /* if core is already in reset, just return */
13503 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
13504 + return;
13505 +
13506 + /* reject value changed between sonics 2.2 and 2.3 */
13507 + if (si->sb.sonicsrev == SONICS_2_2)
13508 + rej = (1 << SBTML_REJ_SHIFT);
13509 + else
13510 + rej = (2 << SBTML_REJ_SHIFT);
13511 +
13512 + /* if clocks are not enabled, put into reset and return */
13513 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
13514 + goto disable;
13515 +
13516 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
13517 + OR_SBREG(si, &sb->sbtmstatelow, rej);
13518 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13519 + OSL_DELAY(1);
13520 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
13521 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY)
13522 + SB_ERROR(("%s: target state still busy\n", __FUNCTION__));
13523 +
13524 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
13525 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
13526 + dummy = R_SBREG(si, &sb->sbimstate);
13527 + OSL_DELAY(1);
13528 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
13529 + }
13530 +
13531 + /* set reset and reject while enabling the clocks */
13532 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
13533 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13534 + OSL_DELAY(10);
13535 +
13536 + /* don't forget to clear the initiator reject bit */
13537 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
13538 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
13539 +
13540 +disable:
13541 + /* leave reset and reject asserted */
13542 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
13543 + OSL_DELAY(1);
13544 +}
13545 +
13546 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
13547 +void
13548 +sb_watchdog(sb_t *sbh, uint ticks)
13549 +{
13550 + sb_info_t *si = SB_INFO(sbh);
13551 +
13552 + /* make sure we come up in fast clock mode */
13553 + sb_clkctl_clk(sbh, CLK_FAST);
13554 +
13555 + /* instant NMI */
13556 + switch (si->gpioid) {
13557 + case SB_CC:
13558 +#ifdef __mips__
13559 + if (sb_chip(sbh) == BCM4785_CHIP_ID && ticks <= 1)
13560 + MTC0(C0_BROADCOM, 4, (1 << 22));
13561 +#endif /* __mips__ */
13562 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
13563 +#ifdef __mips__
13564 + if (sb_chip(sbh) == BCM4785_CHIP_ID && ticks <= 1) {
13565 + __asm__ __volatile__ (
13566 + ".set\tmips3\n\t"
13567 + "sync\n\t"
13568 + "wait\n\t"
13569 + ".set\tmips0"
13570 + );
13571 + while (1);
13572 + }
13573 +#endif /* __mips__ */
13574 + break;
13575 + case SB_EXTIF:
13576 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
13577 + break;
13578 + }
13579 +}
13580 +
13581 +/* initialize the pcmcia core */
13582 +void
13583 +sb_pcmcia_init(sb_t *sbh)
13584 +{
13585 + sb_info_t *si;
13586 + uint8 cor = 0;
13587 +
13588 + si = SB_INFO(sbh);
13589 +
13590 + /* enable d11 mac interrupts */
13591 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
13592 + cor |= COR_IRQEN | COR_FUNEN;
13593 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
13594 +
13595 +}
13596 +
13597 +
13598 +/*
13599 + * Configure the pci core for pci client (NIC) action
13600 + * coremask is the bitvec of cores by index to be enabled.
13601 + */
13602 +void
13603 +BCMINITFN(sb_pci_setup)(sb_t *sbh, uint coremask)
13604 +{
13605 + sb_info_t *si;
13606 + sbconfig_t *sb;
13607 + sbpciregs_t *pciregs;
13608 + uint32 sbflag;
13609 + uint32 w;
13610 + uint idx;
13611 + int reg_val;
13612 +
13613 + si = SB_INFO(sbh);
13614 +
13615 + /* if not pci bus, we're done */
13616 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
13617 + return;
13618 +
13619 + ASSERT(PCI(si) || PCIE(si));
13620 + ASSERT(si->sb.buscoreidx != BADIDX);
13621 +
13622 + /* get current core index */
13623 + idx = si->curidx;
13624 +
13625 + /* we interrupt on this backplane flag number */
13626 + ASSERT(GOODREGS(si->curmap));
13627 + sb = REGS2SB(si->curmap);
13628 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
13629 +
13630 + /* switch over to pci core */
13631 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
13632 + sb = REGS2SB(pciregs);
13633 +
13634 + /*
13635 + * Enable sb->pci interrupts. Assume
13636 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
13637 + */
13638 + if (PCIE(si) || (PCI(si) && ((si->sb.buscorerev) >= 6))) {
13639 + /* pci config write to set this core bit in PCIIntMask */
13640 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
13641 + w |= (coremask << PCI_SBIM_SHIFT);
13642 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
13643 + } else {
13644 + /* set sbintvec bit for our flag number */
13645 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
13646 + }
13647 +
13648 + if (PCI(si)) {
13649 + OR_REG(si->osh, &pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
13650 + if (si->sb.buscorerev >= 11)
13651 + OR_REG(si->osh, &pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
13652 + if (si->sb.buscorerev < 5) {
13653 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13654 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
13655 + sb_commit(sbh);
13656 + }
13657 + }
13658 +
13659 +#ifdef PCIE_SUPPOER
13660 + /* PCIE workarounds */
13661 + if (PCIE(si)) {
13662 + if ((si->sb.buscorerev == 0) || (si->sb.buscorerev == 1)) {
13663 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS,
13664 + PCIE_TLP_WORKAROUNDSREG);
13665 + reg_val |= 0x8;
13666 + sb_pcie_writereg((void *)sbh, (void *)PCIE_PCIEREGS,
13667 + PCIE_TLP_WORKAROUNDSREG, reg_val);
13668 + }
13669 +
13670 + if (si->sb.buscorerev == 1) {
13671 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS,
13672 + PCIE_DLLP_LCREG);
13673 + reg_val |= (0x40);
13674 + sb_pcie_writereg(sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG, reg_val);
13675 + }
13676 +
13677 + if (si->sb.buscorerev == 0)
13678 + sb_war30841(si);
13679 + }
13680 +#endif
13681 +
13682 + /* switch back to previous core */
13683 + sb_setcoreidx(sbh, idx);
13684 +}
13685 +
13686 +uint32
13687 +sb_base(uint32 admatch)
13688 +{
13689 + uint32 base;
13690 + uint type;
13691 +
13692 + type = admatch & SBAM_TYPE_MASK;
13693 + ASSERT(type < 3);
13694 +
13695 + base = 0;
13696 +
13697 + if (type == 0) {
13698 + base = admatch & SBAM_BASE0_MASK;
13699 + } else if (type == 1) {
13700 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13701 + base = admatch & SBAM_BASE1_MASK;
13702 + } else if (type == 2) {
13703 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13704 + base = admatch & SBAM_BASE2_MASK;
13705 + }
13706 +
13707 + return (base);
13708 +}
13709 +
13710 +uint32
13711 +sb_size(uint32 admatch)
13712 +{
13713 + uint32 size;
13714 + uint type;
13715 +
13716 + type = admatch & SBAM_TYPE_MASK;
13717 + ASSERT(type < 3);
13718 +
13719 + size = 0;
13720 +
13721 + if (type == 0) {
13722 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
13723 + } else if (type == 1) {
13724 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13725 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
13726 + } else if (type == 2) {
13727 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13728 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
13729 + }
13730 +
13731 + return (size);
13732 +}
13733 +
13734 +/* return the core-type instantiation # of the current core */
13735 +uint
13736 +sb_coreunit(sb_t *sbh)
13737 +{
13738 + sb_info_t *si;
13739 + uint idx;
13740 + uint coreid;
13741 + uint coreunit;
13742 + uint i;
13743 +
13744 + si = SB_INFO(sbh);
13745 + coreunit = 0;
13746 +
13747 + idx = si->curidx;
13748 +
13749 + ASSERT(GOODREGS(si->curmap));
13750 + coreid = sb_coreid(sbh);
13751 +
13752 + /* count the cores of our type */
13753 + for (i = 0; i < idx; i++)
13754 + if (si->coreid[i] == coreid)
13755 + coreunit++;
13756 +
13757 + return (coreunit);
13758 +}
13759 +
13760 +static INLINE uint32
13761 +factor6(uint32 x)
13762 +{
13763 + switch (x) {
13764 + case CC_F6_2: return 2;
13765 + case CC_F6_3: return 3;
13766 + case CC_F6_4: return 4;
13767 + case CC_F6_5: return 5;
13768 + case CC_F6_6: return 6;
13769 + case CC_F6_7: return 7;
13770 + default: return 0;
13771 + }
13772 +}
13773 +
13774 +/* calculate the speed the SB would run at given a set of clockcontrol values */
13775 +uint32
13776 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
13777 +{
13778 + uint32 n1, n2, clock, m1, m2, m3, mc;
13779 +
13780 + n1 = n & CN_N1_MASK;
13781 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
13782 +
13783 + if (pll_type == PLL_TYPE6) {
13784 + if (m & CC_T6_MMASK)
13785 + return CC_T6_M1;
13786 + else
13787 + return CC_T6_M0;
13788 + } else if ((pll_type == PLL_TYPE1) ||
13789 + (pll_type == PLL_TYPE3) ||
13790 + (pll_type == PLL_TYPE4) ||
13791 + (pll_type == PLL_TYPE7)) {
13792 + n1 = factor6(n1);
13793 + n2 += CC_F5_BIAS;
13794 + } else if (pll_type == PLL_TYPE2) {
13795 + n1 += CC_T2_BIAS;
13796 + n2 += CC_T2_BIAS;
13797 + ASSERT((n1 >= 2) && (n1 <= 7));
13798 + ASSERT((n2 >= 5) && (n2 <= 23));
13799 + } else if (pll_type == PLL_TYPE5) {
13800 + return (100000000);
13801 + } else
13802 + ASSERT(0);
13803 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
13804 + if ((pll_type == PLL_TYPE3) ||
13805 + (pll_type == PLL_TYPE7)) {
13806 + clock = CC_CLOCK_BASE2 * n1 * n2;
13807 + } else
13808 + clock = CC_CLOCK_BASE1 * n1 * n2;
13809 +
13810 + if (clock == 0)
13811 + return 0;
13812 +
13813 + m1 = m & CC_M1_MASK;
13814 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
13815 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
13816 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
13817 +
13818 + if ((pll_type == PLL_TYPE1) ||
13819 + (pll_type == PLL_TYPE3) ||
13820 + (pll_type == PLL_TYPE4) ||
13821 + (pll_type == PLL_TYPE7)) {
13822 + m1 = factor6(m1);
13823 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
13824 + m2 += CC_F5_BIAS;
13825 + else
13826 + m2 = factor6(m2);
13827 + m3 = factor6(m3);
13828 +
13829 + switch (mc) {
13830 + case CC_MC_BYPASS: return (clock);
13831 + case CC_MC_M1: return (clock / m1);
13832 + case CC_MC_M1M2: return (clock / (m1 * m2));
13833 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
13834 + case CC_MC_M1M3: return (clock / (m1 * m3));
13835 + default: return (0);
13836 + }
13837 + } else {
13838 + ASSERT(pll_type == PLL_TYPE2);
13839 +
13840 + m1 += CC_T2_BIAS;
13841 + m2 += CC_T2M2_BIAS;
13842 + m3 += CC_T2_BIAS;
13843 + ASSERT((m1 >= 2) && (m1 <= 7));
13844 + ASSERT((m2 >= 3) && (m2 <= 10));
13845 + ASSERT((m3 >= 2) && (m3 <= 7));
13846 +
13847 + if ((mc & CC_T2MC_M1BYP) == 0)
13848 + clock /= m1;
13849 + if ((mc & CC_T2MC_M2BYP) == 0)
13850 + clock /= m2;
13851 + if ((mc & CC_T2MC_M3BYP) == 0)
13852 + clock /= m3;
13853 +
13854 + return (clock);
13855 + }
13856 +}
13857 +
13858 +/* returns the current speed the SB is running at */
13859 +uint32
13860 +sb_clock(sb_t *sbh)
13861 +{
13862 + sb_info_t *si;
13863 + extifregs_t *eir;
13864 + chipcregs_t *cc;
13865 + uint32 n, m;
13866 + uint idx;
13867 + uint32 pll_type, rate;
13868 + uint intr_val = 0;
13869 +
13870 + si = SB_INFO(sbh);
13871 + idx = si->curidx;
13872 + pll_type = PLL_TYPE1;
13873 +
13874 + INTR_OFF(si, intr_val);
13875 +
13876 + /* switch to extif or chipc core */
13877 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
13878 + n = R_REG(si->osh, &eir->clockcontrol_n);
13879 + m = R_REG(si->osh, &eir->clockcontrol_sb);
13880 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
13881 + pll_type = R_REG(si->osh, &cc->capabilities) & CAP_PLL_MASK;
13882 + if (pll_type == PLL_NONE) {
13883 + INTR_RESTORE(si, intr_val);
13884 + return 80000000;
13885 + }
13886 + n = R_REG(si->osh, &cc->clockcontrol_n);
13887 + if (pll_type == PLL_TYPE6)
13888 + m = R_REG(si->osh, &cc->clockcontrol_m3);
13889 + else if ((pll_type == PLL_TYPE3) && !(BCMINIT(sb_chip)(sbh) == 0x5365))
13890 + m = R_REG(si->osh, &cc->clockcontrol_m2);
13891 + else
13892 + m = R_REG(si->osh, &cc->clockcontrol_sb);
13893 + } else {
13894 + INTR_RESTORE(si, intr_val);
13895 + return 0;
13896 + }
13897 +
13898 + /* calculate rate */
13899 + if (BCMINIT(sb_chip)(sbh) == 0x5365)
13900 + rate = 100000000;
13901 + else {
13902 + rate = sb_clock_rate(pll_type, n, m);
13903 +
13904 + if (pll_type == PLL_TYPE3)
13905 + rate = rate / 2;
13906 + }
13907 +
13908 + /* switch back to previous core */
13909 + sb_setcoreidx(sbh, idx);
13910 +
13911 + INTR_RESTORE(si, intr_val);
13912 +
13913 + return rate;
13914 +}
13915 +
13916 +/* change logical "focus" to the gpio core for optimized access */
13917 +void*
13918 +sb_gpiosetcore(sb_t *sbh)
13919 +{
13920 + sb_info_t *si;
13921 +
13922 + si = SB_INFO(sbh);
13923 +
13924 + return (sb_setcoreidx(sbh, si->gpioidx));
13925 +}
13926 +
13927 +/* mask&set gpiocontrol bits */
13928 +uint32
13929 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
13930 +{
13931 + sb_info_t *si;
13932 + uint regoff;
13933 +
13934 + si = SB_INFO(sbh);
13935 + regoff = 0;
13936 +
13937 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
13938 +
13939 + /* gpios could be shared on router platforms */
13940 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
13941 + mask = priority ? (sb_gpioreservation & mask) :
13942 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
13943 + val &= mask;
13944 + }
13945 +
13946 + switch (si->gpioid) {
13947 + case SB_CC:
13948 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
13949 + break;
13950 +
13951 + case SB_PCI:
13952 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
13953 + break;
13954 +
13955 + case SB_EXTIF:
13956 + return (0);
13957 + }
13958 +
13959 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
13960 +}
13961 +
13962 +/* mask&set gpio output enable bits */
13963 +uint32
13964 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
13965 +{
13966 + sb_info_t *si;
13967 + uint regoff;
13968 +
13969 + si = SB_INFO(sbh);
13970 + regoff = 0;
13971 +
13972 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
13973 +
13974 + /* gpios could be shared on router platforms */
13975 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
13976 + mask = priority ? (sb_gpioreservation & mask) :
13977 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
13978 + val &= mask;
13979 + }
13980 +
13981 + switch (si->gpioid) {
13982 + case SB_CC:
13983 + regoff = OFFSETOF(chipcregs_t, gpioouten);
13984 + break;
13985 +
13986 + case SB_PCI:
13987 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
13988 + break;
13989 +
13990 + case SB_EXTIF:
13991 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
13992 + break;
13993 + }
13994 +
13995 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
13996 +}
13997 +
13998 +/* mask&set gpio output bits */
13999 +uint32
14000 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14001 +{
14002 + sb_info_t *si;
14003 + uint regoff;
14004 +
14005 + si = SB_INFO(sbh);
14006 + regoff = 0;
14007 +
14008 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14009 +
14010 + /* gpios could be shared on router platforms */
14011 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14012 + mask = priority ? (sb_gpioreservation & mask) :
14013 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14014 + val &= mask;
14015 + }
14016 +
14017 + switch (si->gpioid) {
14018 + case SB_CC:
14019 + regoff = OFFSETOF(chipcregs_t, gpioout);
14020 + break;
14021 +
14022 + case SB_PCI:
14023 + regoff = OFFSETOF(sbpciregs_t, gpioout);
14024 + break;
14025 +
14026 + case SB_EXTIF:
14027 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
14028 + break;
14029 + }
14030 +
14031 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14032 +}
14033 +
14034 +/* reserve one gpio */
14035 +uint32
14036 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
14037 +{
14038 + sb_info_t *si;
14039 +
14040 + si = SB_INFO(sbh);
14041 +
14042 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14043 +
14044 + /* only cores on SB_BUS share GPIO's and only applcation users need to
14045 + * reserve/release GPIO
14046 + */
14047 + if ((BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
14048 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
14049 + return -1;
14050 + }
14051 + /* make sure only one bit is set */
14052 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
14053 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
14054 + return -1;
14055 + }
14056 +
14057 + /* already reserved */
14058 + if (sb_gpioreservation & gpio_bitmask)
14059 + return -1;
14060 + /* set reservation */
14061 + sb_gpioreservation |= gpio_bitmask;
14062 +
14063 + return sb_gpioreservation;
14064 +}
14065 +
14066 +/* release one gpio */
14067 +/*
14068 + * releasing the gpio doesn't change the current value on the GPIO last write value
14069 + * persists till some one overwrites it
14070 +*/
14071 +
14072 +uint32
14073 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
14074 +{
14075 + sb_info_t *si;
14076 +
14077 + si = SB_INFO(sbh);
14078 +
14079 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14080 +
14081 + /* only cores on SB_BUS share GPIO's and only applcation users need to
14082 + * reserve/release GPIO
14083 + */
14084 + if ((BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
14085 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
14086 + return -1;
14087 + }
14088 + /* make sure only one bit is set */
14089 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
14090 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
14091 + return -1;
14092 + }
14093 +
14094 + /* already released */
14095 + if (!(sb_gpioreservation & gpio_bitmask))
14096 + return -1;
14097 +
14098 + /* clear reservation */
14099 + sb_gpioreservation &= ~gpio_bitmask;
14100 +
14101 + return sb_gpioreservation;
14102 +}
14103 +
14104 +/* return the current gpioin register value */
14105 +uint32
14106 +sb_gpioin(sb_t *sbh)
14107 +{
14108 + sb_info_t *si;
14109 + uint regoff;
14110 +
14111 + si = SB_INFO(sbh);
14112 + regoff = 0;
14113 +
14114 + switch (si->gpioid) {
14115 + case SB_CC:
14116 + regoff = OFFSETOF(chipcregs_t, gpioin);
14117 + break;
14118 +
14119 + case SB_PCI:
14120 + regoff = OFFSETOF(sbpciregs_t, gpioin);
14121 + break;
14122 +
14123 + case SB_EXTIF:
14124 + regoff = OFFSETOF(extifregs_t, gpioin);
14125 + break;
14126 + }
14127 +
14128 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
14129 +}
14130 +
14131 +/* mask&set gpio interrupt polarity bits */
14132 +uint32
14133 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14134 +{
14135 + sb_info_t *si;
14136 + uint regoff;
14137 +
14138 + si = SB_INFO(sbh);
14139 + regoff = 0;
14140 +
14141 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14142 +
14143 + /* gpios could be shared on router platforms */
14144 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14145 + mask = priority ? (sb_gpioreservation & mask) :
14146 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14147 + val &= mask;
14148 + }
14149 +
14150 + switch (si->gpioid) {
14151 + case SB_CC:
14152 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
14153 + break;
14154 +
14155 + case SB_PCI:
14156 + /* pci gpio implementation does not support interrupt polarity */
14157 + ASSERT(0);
14158 + break;
14159 +
14160 + case SB_EXTIF:
14161 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
14162 + break;
14163 + }
14164 +
14165 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14166 +}
14167 +
14168 +/* mask&set gpio interrupt mask bits */
14169 +uint32
14170 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14171 +{
14172 + sb_info_t *si;
14173 + uint regoff;
14174 +
14175 + si = SB_INFO(sbh);
14176 + regoff = 0;
14177 +
14178 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14179 +
14180 + /* gpios could be shared on router platforms */
14181 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14182 + mask = priority ? (sb_gpioreservation & mask) :
14183 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14184 + val &= mask;
14185 + }
14186 +
14187 + switch (si->gpioid) {
14188 + case SB_CC:
14189 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
14190 + break;
14191 +
14192 + case SB_PCI:
14193 + /* pci gpio implementation does not support interrupt mask */
14194 + ASSERT(0);
14195 + break;
14196 +
14197 + case SB_EXTIF:
14198 + regoff = OFFSETOF(extifregs_t, gpiointmask);
14199 + break;
14200 + }
14201 +
14202 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14203 +}
14204 +
14205 +/* assign the gpio to an led */
14206 +uint32
14207 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
14208 +{
14209 + sb_info_t *si;
14210 +
14211 + si = SB_INFO(sbh);
14212 + if (si->sb.ccrev < 16)
14213 + return -1;
14214 +
14215 + /* gpio led powersave reg */
14216 + return (sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
14217 +}
14218 +
14219 +/* mask & set gpio timer val */
14220 +uint32
14221 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
14222 +{
14223 + sb_info_t *si;
14224 + si = SB_INFO(sbh);
14225 +
14226 + if (si->sb.ccrev < 16)
14227 + return -1;
14228 +
14229 + return (sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
14230 +}
14231 +
14232 +
14233 +/* return the slow clock source - LPO, XTAL, or PCI */
14234 +static uint
14235 +sb_slowclk_src(sb_info_t *si)
14236 +{
14237 + chipcregs_t *cc;
14238 +
14239 +
14240 + ASSERT(sb_coreid(&si->sb) == SB_CC);
14241 +
14242 + if (si->sb.ccrev < 6) {
14243 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS) &&
14244 + (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32)) &
14245 + PCI_CFG_GPIO_SCS))
14246 + return (SCC_SS_PCI);
14247 + else
14248 + return (SCC_SS_XTAL);
14249 + } else if (si->sb.ccrev < 10) {
14250 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
14251 + return (R_REG(si->osh, &cc->slow_clk_ctl) & SCC_SS_MASK);
14252 + } else /* Insta-clock */
14253 + return (SCC_SS_XTAL);
14254 +}
14255 +
14256 +/* return the ILP (slowclock) min or max frequency */
14257 +static uint
14258 +sb_slowclk_freq(sb_info_t *si, bool max)
14259 +{
14260 + chipcregs_t *cc;
14261 + uint32 slowclk;
14262 + uint div;
14263 +
14264 +
14265 + ASSERT(sb_coreid(&si->sb) == SB_CC);
14266 +
14267 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
14268 +
14269 + /* shouldn't be here unless we've established the chip has dynamic clk control */
14270 + ASSERT(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL);
14271 +
14272 + slowclk = sb_slowclk_src(si);
14273 + if (si->sb.ccrev < 6) {
14274 + if (slowclk == SCC_SS_PCI)
14275 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
14276 + else
14277 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
14278 + } else if (si->sb.ccrev < 10) {
14279 + div = 4 * (((R_REG(si->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
14280 + if (slowclk == SCC_SS_LPO)
14281 + return (max? LPOMAXFREQ : LPOMINFREQ);
14282 + else if (slowclk == SCC_SS_XTAL)
14283 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
14284 + else if (slowclk == SCC_SS_PCI)
14285 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
14286 + else
14287 + ASSERT(0);
14288 + } else {
14289 + /* Chipc rev 10 is InstaClock */
14290 + div = R_REG(si->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT;
14291 + div = 4 * (div + 1);
14292 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
14293 + }
14294 + return (0);
14295 +}
14296 +
14297 +static void
14298 +BCMINITFN(sb_clkctl_setdelay)(sb_info_t *si, void *chipcregs)
14299 +{
14300 + chipcregs_t * cc;
14301 + uint slowmaxfreq, pll_delay, slowclk;
14302 + uint pll_on_delay, fref_sel_delay;
14303 +
14304 + pll_delay = PLL_DELAY;
14305 +
14306 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
14307 + * since the xtal will also be powered down by dynamic clk control logic.
14308 + */
14309 +
14310 + slowclk = sb_slowclk_src(si);
14311 + if (slowclk != SCC_SS_XTAL)
14312 + pll_delay += XTAL_ON_DELAY;
14313 +
14314 + /* Starting with 4318 it is ILP that is used for the delays */
14315 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
14316 +
14317 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
14318 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
14319 +
14320 + cc = (chipcregs_t *)chipcregs;
14321 + W_REG(si->osh, &cc->pll_on_delay, pll_on_delay);
14322 + W_REG(si->osh, &cc->fref_sel_delay, fref_sel_delay);
14323 +}
14324 +
14325 +/* initialize power control delay registers */
14326 +void
14327 +BCMINITFN(sb_clkctl_init)(sb_t *sbh)
14328 +{
14329 + sb_info_t *si;
14330 + uint origidx;
14331 + chipcregs_t *cc;
14332 +
14333 + si = SB_INFO(sbh);
14334 +
14335 + origidx = si->curidx;
14336 +
14337 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
14338 + return;
14339 +
14340 + if ((si->sb.chip == BCM4321_CHIP_ID) && (si->sb.chiprev < 2))
14341 + W_REG(si->osh, &cc->chipcontrol,
14342 + (si->sb.chiprev == 0) ? CHIPCTRL_4321A0_DEFAULT : CHIPCTRL_4321A1_DEFAULT);
14343 +
14344 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14345 + goto done;
14346 +
14347 + /* set all Instaclk chip ILP to 1 MHz */
14348 + else if (si->sb.ccrev >= 10)
14349 + SET_REG(si->osh, &cc->system_clk_ctl, SYCC_CD_MASK,
14350 + (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
14351 +
14352 + sb_clkctl_setdelay(si, (void *)cc);
14353 +
14354 +done:
14355 + sb_setcoreidx(sbh, origidx);
14356 +}
14357 +
14358 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
14359 +uint16
14360 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
14361 +{
14362 + sb_info_t *si;
14363 + uint origidx;
14364 + chipcregs_t *cc;
14365 + uint slowminfreq;
14366 + uint16 fpdelay;
14367 + uint intr_val = 0;
14368 +
14369 + si = SB_INFO(sbh);
14370 + fpdelay = 0;
14371 + origidx = si->curidx;
14372 +
14373 + INTR_OFF(si, intr_val);
14374 +
14375 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
14376 + goto done;
14377 +
14378 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14379 + goto done;
14380 +
14381 + slowminfreq = sb_slowclk_freq(si, FALSE);
14382 + fpdelay = (((R_REG(si->osh, &cc->pll_on_delay) + 2) * 1000000) +
14383 + (slowminfreq - 1)) / slowminfreq;
14384 +
14385 +done:
14386 + sb_setcoreidx(sbh, origidx);
14387 + INTR_RESTORE(si, intr_val);
14388 + return (fpdelay);
14389 +}
14390 +
14391 +/* turn primary xtal and/or pll off/on */
14392 +int
14393 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
14394 +{
14395 + sb_info_t *si;
14396 + uint32 in, out, outen;
14397 +
14398 + si = SB_INFO(sbh);
14399 +
14400 + switch (BUSTYPE(si->sb.bustype)) {
14401 +
14402 +
14403 + case PCMCIA_BUS:
14404 + return (0);
14405 +
14406 +
14407 + case PCI_BUS:
14408 +
14409 + /* pcie core doesn't have any mapping to control the xtal pu */
14410 + if (PCIE(si))
14411 + return -1;
14412 +
14413 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof(uint32));
14414 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32));
14415 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof(uint32));
14416 +
14417 + /*
14418 + * Avoid glitching the clock if GPRS is already using it.
14419 + * We can't actually read the state of the PLLPD so we infer it
14420 + * by the value of XTAL_PU which *is* readable via gpioin.
14421 + */
14422 + if (on && (in & PCI_CFG_GPIO_XTAL))
14423 + return (0);
14424 +
14425 + if (what & XTAL)
14426 + outen |= PCI_CFG_GPIO_XTAL;
14427 + if (what & PLL)
14428 + outen |= PCI_CFG_GPIO_PLL;
14429 +
14430 + if (on) {
14431 + /* turn primary xtal on */
14432 + if (what & XTAL) {
14433 + out |= PCI_CFG_GPIO_XTAL;
14434 + if (what & PLL)
14435 + out |= PCI_CFG_GPIO_PLL;
14436 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT,
14437 + sizeof(uint32), out);
14438 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN,
14439 + sizeof(uint32), outen);
14440 + OSL_DELAY(XTAL_ON_DELAY);
14441 + }
14442 +
14443 + /* turn pll on */
14444 + if (what & PLL) {
14445 + out &= ~PCI_CFG_GPIO_PLL;
14446 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT,
14447 + sizeof(uint32), out);
14448 + OSL_DELAY(2000);
14449 + }
14450 + } else {
14451 + if (what & XTAL)
14452 + out &= ~PCI_CFG_GPIO_XTAL;
14453 + if (what & PLL)
14454 + out |= PCI_CFG_GPIO_PLL;
14455 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32), out);
14456 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof(uint32),
14457 + outen);
14458 + }
14459 +
14460 + default:
14461 + return (-1);
14462 + }
14463 +
14464 + return (0);
14465 +}
14466 +
14467 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
14468 +/* returns true if we are forcing fast clock */
14469 +bool
14470 +sb_clkctl_clk(sb_t *sbh, uint mode)
14471 +{
14472 + sb_info_t *si;
14473 + uint origidx;
14474 + chipcregs_t *cc;
14475 + uint32 scc;
14476 + uint intr_val = 0;
14477 +
14478 + si = SB_INFO(sbh);
14479 +
14480 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
14481 + if (si->sb.ccrev < 6)
14482 + return (FALSE);
14483 +
14484 +
14485 + /* Chips with ccrev 10 are EOL and they don't have SYCC_HR which we use below */
14486 + ASSERT(si->sb.ccrev != 10);
14487 +
14488 + INTR_OFF(si, intr_val);
14489 +
14490 + origidx = si->curidx;
14491 +
14492 + if (sb_setcore(sbh, SB_MIPS33, 0) && (sb_corerev(&si->sb) <= 7) &&
14493 + (BUSTYPE(si->sb.bustype) == SB_BUS) && (si->sb.ccrev >= 10))
14494 + goto done;
14495 +
14496 + /* PR32414WAR "Force HT clock on" all the time, no dynamic clk ctl */
14497 + if ((si->sb.chip == BCM4311_CHIP_ID) && (si->sb.chiprev <= 1))
14498 + goto done;
14499 +
14500 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
14501 + ASSERT(cc != NULL);
14502 +
14503 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14504 + goto done;
14505 +
14506 + switch (mode) {
14507 + case CLK_FAST: /* force fast (pll) clock */
14508 + if (si->sb.ccrev < 10) {
14509 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
14510 + sb_clkctl_xtal(&si->sb, XTAL, ON);
14511 +
14512 + SET_REG(si->osh, &cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
14513 + } else
14514 + OR_REG(si->osh, &cc->system_clk_ctl, SYCC_HR);
14515 + /* wait for the PLL */
14516 + OSL_DELAY(PLL_DELAY);
14517 + break;
14518 +
14519 + case CLK_DYNAMIC: /* enable dynamic clock control */
14520 +
14521 + if (si->sb.ccrev < 10) {
14522 + scc = R_REG(si->osh, &cc->slow_clk_ctl);
14523 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
14524 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
14525 + scc |= SCC_XC;
14526 + W_REG(si->osh, &cc->slow_clk_ctl, scc);
14527 +
14528 + /* for dynamic control, we have to release our xtal_pu "force on" */
14529 + if (scc & SCC_XC)
14530 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
14531 + } else {
14532 + /* Instaclock */
14533 + AND_REG(si->osh, &cc->system_clk_ctl, ~SYCC_HR);
14534 + }
14535 + break;
14536 +
14537 + default:
14538 + ASSERT(0);
14539 + }
14540 +
14541 +done:
14542 + sb_setcoreidx(sbh, origidx);
14543 + INTR_RESTORE(si, intr_val);
14544 + return (mode == CLK_FAST);
14545 +}
14546 +
14547 +/* register driver interrupt disabling and restoring callback functions */
14548 +void
14549 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
14550 + void *intrsenabled_fn, void *intr_arg)
14551 +{
14552 + sb_info_t *si;
14553 +
14554 + si = SB_INFO(sbh);
14555 + si->intr_arg = intr_arg;
14556 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
14557 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
14558 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
14559 + /* save current core id. when this function called, the current core
14560 + * must be the core which provides driver functions(il, et, wl, etc.)
14561 + */
14562 + si->dev_coreid = si->coreid[si->curidx];
14563 +}
14564 +
14565 +
14566 +int
14567 +sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
14568 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
14569 + uint8 *pciheader)
14570 +{
14571 + uint16 vendor = 0xffff, device = 0xffff;
14572 + uint core, unit;
14573 + uint chip, chippkg;
14574 + uint nfunc;
14575 + char varname[SB_DEVPATH_BUFSZ + 8];
14576 + uint8 class, subclass, progif;
14577 + char devpath[SB_DEVPATH_BUFSZ];
14578 + uint8 header;
14579 +
14580 + core = sb_coreid(sbh);
14581 + unit = sb_coreunit(sbh);
14582 +
14583 + chip = sb_chip(sbh);
14584 + chippkg = sb_chippkg(sbh);
14585 +
14586 + progif = 0;
14587 + header = PCI_HEADER_NORMAL;
14588 +
14589 + /* Verify whether the function exists for the core */
14590 + nfunc = (core == SB_USB20H) ? 2 : 1;
14591 + if (func >= nfunc)
14592 + return BCME_ERROR;
14593 +
14594 + /* Known vendor translations */
14595 + switch (sb_corevendor(sbh)) {
14596 + case SB_VEND_BCM:
14597 + vendor = VENDOR_BROADCOM;
14598 + break;
14599 + default:
14600 + return BCME_ERROR;
14601 + }
14602 +
14603 + /* Determine class based on known core codes */
14604 + switch (core) {
14605 + case SB_ILINE20:
14606 + class = PCI_CLASS_NET;
14607 + subclass = PCI_NET_ETHER;
14608 + device = BCM47XX_ILINE_ID;
14609 + break;
14610 + case SB_ENET:
14611 + class = PCI_CLASS_NET;
14612 + subclass = PCI_NET_ETHER;
14613 + device = BCM47XX_ENET_ID;
14614 + break;
14615 + case SB_GIGETH:
14616 + class = PCI_CLASS_NET;
14617 + subclass = PCI_NET_ETHER;
14618 + device = BCM47XX_GIGETH_ID;
14619 + break;
14620 + case SB_SDRAM:
14621 + case SB_MEMC:
14622 + class = PCI_CLASS_MEMORY;
14623 + subclass = PCI_MEMORY_RAM;
14624 + device = (uint16)core;
14625 + break;
14626 + case SB_PCI:
14627 + case SB_PCIE:
14628 + class = PCI_CLASS_BRIDGE;
14629 + subclass = PCI_BRIDGE_PCI;
14630 + device = (uint16)core;
14631 + header = PCI_HEADER_BRIDGE;
14632 + break;
14633 + case SB_MIPS:
14634 + case SB_MIPS33:
14635 + class = PCI_CLASS_CPU;
14636 + subclass = PCI_CPU_MIPS;
14637 + device = (uint16)core;
14638 + break;
14639 + case SB_CODEC:
14640 + class = PCI_CLASS_COMM;
14641 + subclass = PCI_COMM_MODEM;
14642 + device = BCM47XX_V90_ID;
14643 + break;
14644 + case SB_USB:
14645 + class = PCI_CLASS_SERIAL;
14646 + subclass = PCI_SERIAL_USB;
14647 + progif = 0x10; /* OHCI */
14648 + device = BCM47XX_USB_ID;
14649 + break;
14650 + case SB_USB11H:
14651 + class = PCI_CLASS_SERIAL;
14652 + subclass = PCI_SERIAL_USB;
14653 + progif = 0x10; /* OHCI */
14654 + device = BCM47XX_USBH_ID;
14655 + break;
14656 + case SB_USB20H:
14657 + class = PCI_CLASS_SERIAL;
14658 + subclass = PCI_SERIAL_USB;
14659 + progif = func == 0 ? 0x10 : 0x20; /* OHCI/EHCI */
14660 + device = BCM47XX_USB20H_ID;
14661 + header = 0x80; /* multifunction */
14662 + break;
14663 + case SB_USB11D:
14664 + class = PCI_CLASS_SERIAL;
14665 + subclass = PCI_SERIAL_USB;
14666 + device = BCM47XX_USBD_ID;
14667 + break;
14668 + case SB_USB20D:
14669 + class = PCI_CLASS_SERIAL;
14670 + subclass = PCI_SERIAL_USB;
14671 + device = BCM47XX_USB20D_ID;
14672 + break;
14673 + case SB_IPSEC:
14674 + class = PCI_CLASS_CRYPT;
14675 + subclass = PCI_CRYPT_NETWORK;
14676 + device = BCM47XX_IPSEC_ID;
14677 + break;
14678 + case SB_ROBO:
14679 + class = PCI_CLASS_NET;
14680 + subclass = PCI_NET_OTHER;
14681 + device = BCM47XX_ROBO_ID;
14682 + break;
14683 + case SB_EXTIF:
14684 + case SB_CC:
14685 + class = PCI_CLASS_MEMORY;
14686 + subclass = PCI_MEMORY_FLASH;
14687 + device = (uint16)core;
14688 + break;
14689 + case SB_D11:
14690 + class = PCI_CLASS_NET;
14691 + subclass = PCI_NET_OTHER;
14692 + /* Let nvram variable override core ID */
14693 + sb_devpath(sbh, devpath, sizeof(devpath));
14694 + sprintf(varname, "%sdevid", devpath);
14695 + if ((device = (uint16)getintvar(NULL, varname)))
14696 + break;
14697 + /*
14698 + * no longer support wl%did, but keep the code
14699 + * here for backward compatibility.
14700 + */
14701 + sprintf(varname, "wl%did", unit);
14702 + if ((device = (uint16)getintvar(NULL, varname)))
14703 + break;
14704 + /* Chip specific conversion */
14705 + if (chip == BCM4712_CHIP_ID) {
14706 + if (chippkg == BCM4712SMALL_PKG_ID)
14707 + device = BCM4306_D11G_ID;
14708 + else
14709 + device = BCM4306_D11DUAL_ID;
14710 + break;
14711 + }
14712 + /* ignore it */
14713 + device = 0xffff;
14714 + break;
14715 + case SB_SATAXOR:
14716 + class = PCI_CLASS_XOR;
14717 + subclass = PCI_XOR_QDMA;
14718 + device = BCM47XX_SATAXOR_ID;
14719 + break;
14720 + case SB_ATA100:
14721 + class = PCI_CLASS_DASDI;
14722 + subclass = PCI_DASDI_IDE;
14723 + device = BCM47XX_ATA100_ID;
14724 + break;
14725 +
14726 + default:
14727 + class = subclass = progif = 0xff;
14728 + device = (uint16)core;
14729 + break;
14730 + }
14731 +
14732 + *pcivendor = vendor;
14733 + *pcidevice = device;
14734 + *pciclass = class;
14735 + *pcisubclass = subclass;
14736 + *pciprogif = progif;
14737 + *pciheader = header;
14738 +
14739 + return 0;
14740 +}
14741 +
14742 +
14743 +
14744 +/* use the mdio interface to write to mdio slaves */
14745 +static int
14746 +sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint regaddr, uint val)
14747 +{
14748 + uint mdiodata;
14749 + uint i = 0;
14750 + sbpcieregs_t *pcieregs;
14751 +
14752 + pcieregs = (sbpcieregs_t*) sb_setcoreidx(&si->sb, si->sb.buscoreidx);
14753 + ASSERT(pcieregs);
14754 +
14755 + /* enable mdio access to SERDES */
14756 + W_REG(si->osh, (&pcieregs->mdiocontrol), MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
14757 +
14758 + mdiodata = MDIODATA_START | MDIODATA_WRITE |
14759 + (physmedia << MDIODATA_DEVADDR_SHF) |
14760 + (regaddr << MDIODATA_REGADDR_SHF) | MDIODATA_TA | val;
14761 +
14762 + W_REG(si->osh, (&pcieregs->mdiodata), mdiodata);
14763 +
14764 + PR28829_DELAY();
14765 +
14766 + /* retry till the transaction is complete */
14767 + while (i < 10) {
14768 + if (R_REG(si->osh, &(pcieregs->mdiocontrol)) & MDIOCTL_ACCESS_DONE) {
14769 + /* Disable mdio access to SERDES */
14770 + W_REG(si->osh, (&pcieregs->mdiocontrol), 0);
14771 + return 0;
14772 + }
14773 + OSL_DELAY(1000);
14774 + i++;
14775 + }
14776 +
14777 + SB_ERROR(("sb_pcie_mdiowrite: timed out\n"));
14778 + /* Disable mdio access to SERDES */
14779 + W_REG(si->osh, (&pcieregs->mdiocontrol), 0);
14780 + ASSERT(0);
14781 + return 1;
14782 +
14783 +}
14784 +
14785 +/* indirect way to read pcie config regs */
14786 +uint
14787 +sb_pcie_readreg(void *sb, void* arg1, uint offset)
14788 +{
14789 + sb_info_t *si;
14790 + sb_t *sbh;
14791 + uint retval = 0xFFFFFFFF;
14792 + sbpcieregs_t *pcieregs;
14793 + uint addrtype;
14794 +
14795 + sbh = (sb_t *)sb;
14796 + si = SB_INFO(sbh);
14797 + ASSERT(PCIE(si));
14798 +
14799 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
14800 + ASSERT(pcieregs);
14801 +
14802 + addrtype = (uint)((uintptr)arg1);
14803 + switch (addrtype) {
14804 + case PCIE_CONFIGREGS:
14805 + W_REG(si->osh, (&pcieregs->configaddr), offset);
14806 + retval = R_REG(si->osh, &(pcieregs->configdata));
14807 + break;
14808 + case PCIE_PCIEREGS:
14809 + W_REG(si->osh, &(pcieregs->pcieaddr), offset);
14810 + retval = R_REG(si->osh, &(pcieregs->pciedata));
14811 + break;
14812 + default:
14813 + ASSERT(0);
14814 + break;
14815 + }
14816 + return retval;
14817 +}
14818 +
14819 +/* indirect way to write pcie config/mdio/pciecore regs */
14820 +uint
14821 +sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val)
14822 +{
14823 + sb_info_t *si;
14824 + sbpcieregs_t *pcieregs;
14825 + uint addrtype;
14826 +
14827 + si = SB_INFO(sbh);
14828 + ASSERT(PCIE(si));
14829 +
14830 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
14831 + ASSERT(pcieregs);
14832 +
14833 + addrtype = (uint)((uintptr)arg1);
14834 +
14835 + switch (addrtype) {
14836 + case PCIE_CONFIGREGS:
14837 + W_REG(si->osh, (&pcieregs->configaddr), offset);
14838 + W_REG(si->osh, (&pcieregs->configdata), val);
14839 + break;
14840 + case PCIE_PCIEREGS:
14841 + W_REG(si->osh, (&pcieregs->pcieaddr), offset);
14842 + W_REG(si->osh, (&pcieregs->pciedata), val);
14843 + break;
14844 + default:
14845 + ASSERT(0);
14846 + break;
14847 + }
14848 + return 0;
14849 +}
14850 +
14851 +/* Build device path. Support SB, PCI, and JTAG for now. */
14852 +int
14853 +sb_devpath(sb_t *sbh, char *path, int size)
14854 +{
14855 + ASSERT(path);
14856 + ASSERT(size >= SB_DEVPATH_BUFSZ);
14857 +
14858 + switch (BUSTYPE((SB_INFO(sbh))->sb.bustype)) {
14859 + case SB_BUS:
14860 + case JTAG_BUS:
14861 + sprintf(path, "sb/%u/", sb_coreidx(sbh));
14862 + break;
14863 + case PCI_BUS:
14864 + ASSERT((SB_INFO(sbh))->osh);
14865 + sprintf(path, "pci/%u/%u/", OSL_PCI_BUS((SB_INFO(sbh))->osh),
14866 + OSL_PCI_SLOT((SB_INFO(sbh))->osh));
14867 + break;
14868 + case PCMCIA_BUS:
14869 + SB_ERROR(("sb_devpath: OSL_PCMCIA_BUS() not implemented, bus 1 assumed\n"));
14870 + SB_ERROR(("sb_devpath: OSL_PCMCIA_SLOT() not implemented, slot 1 assumed\n"));
14871 + sprintf(path, "pc/%u/%u/", 1, 1);
14872 + break;
14873 + case SDIO_BUS:
14874 + SB_ERROR(("sb_devpath: device 0 assumed\n"));
14875 + sprintf(path, "sd/%u/", sb_coreidx(sbh));
14876 + break;
14877 + default:
14878 + ASSERT(0);
14879 + break;
14880 + }
14881 +
14882 + return 0;
14883 +}
14884 +
14885 +/*
14886 + * Fixup SROMless PCI device's configuration.
14887 + * The current core may be changed upon return.
14888 + */
14889 +static int
14890 +sb_pci_fixcfg(sb_info_t *si)
14891 +{
14892 + uint origidx, pciidx;
14893 + sbpciregs_t *pciregs;
14894 + sbpcieregs_t *pcieregs;
14895 + uint16 val16, *reg16;
14896 + char name[SB_DEVPATH_BUFSZ+16], *value;
14897 + char devpath[SB_DEVPATH_BUFSZ];
14898 +
14899 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
14900 +
14901 + /* Fixup PI in SROM shadow area to enable the correct PCI core access */
14902 + /* save the current index */
14903 + origidx = sb_coreidx(&si->sb);
14904 +
14905 + /* check 'pi' is correct and fix it if not */
14906 + if (si->sb.buscoretype == SB_PCIE) {
14907 + pcieregs = (sbpcieregs_t *)sb_setcore(&si->sb, SB_PCIE, 0);
14908 + ASSERT(pcieregs);
14909 + reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
14910 + } else if (si->sb.buscoretype == SB_PCI) {
14911 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
14912 + ASSERT(pciregs);
14913 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
14914 + } else {
14915 + ASSERT(0);
14916 + return -1;
14917 + }
14918 + pciidx = sb_coreidx(&si->sb);
14919 + val16 = R_REG(si->osh, reg16);
14920 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
14921 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
14922 + W_REG(si->osh, reg16, val16);
14923 + }
14924 +
14925 + /* restore the original index */
14926 + sb_setcoreidx(&si->sb, origidx);
14927 +
14928 + /*
14929 + * Fixup bar0window in PCI config space to make the core indicated
14930 + * by the nvram variable the current core.
14931 + * !Do it last, it may change the current core!
14932 + */
14933 + if (sb_devpath(&si->sb, devpath, sizeof(devpath)))
14934 + return -1;
14935 + sprintf(name, "%sb0w", devpath);
14936 + if ((value = getvar(NULL, name))) {
14937 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32),
14938 + bcm_strtoul(value, NULL, 16));
14939 + /* update curidx since the current core is changed */
14940 + si->curidx = _sb_coreidx(si);
14941 + if (si->curidx == BADIDX) {
14942 + SB_ERROR(("sb_pci_fixcfg: bad core index\n"));
14943 + return -1;
14944 + }
14945 + }
14946 +
14947 + return 0;
14948 +}
14949 +
14950 +static uint
14951 +sb_chipc_capability(sb_t *sbh)
14952 +{
14953 + sb_info_t *si;
14954 +
14955 + si = SB_INFO(sbh);
14956 +
14957 + /* Make sure that there is ChipCommon core present */
14958 + if (si->coreid[SB_CC_IDX] == SB_CC)
14959 + return (sb_corereg(si, SB_CC_IDX, OFFSETOF(chipcregs_t, capabilities),
14960 + 0, 0));
14961 + return 0;
14962 +}
14963 +
14964 +/* Return ADDR64 capability of the backplane */
14965 +bool
14966 +sb_backplane64(sb_t *sbh)
14967 +{
14968 + return ((sb_chipc_capability(sbh) & CAP_BKPLN64) != 0);
14969 +}
14970 +
14971 +void
14972 +sb_btcgpiowar(sb_t *sbh)
14973 +{
14974 + sb_info_t *si;
14975 + uint origidx;
14976 + uint intr_val = 0;
14977 + chipcregs_t *cc;
14978 + si = SB_INFO(sbh);
14979 +
14980 + /* Make sure that there is ChipCommon core present &&
14981 + * UART_TX is strapped to 1
14982 + */
14983 + if (!(sb_chipc_capability(sbh) & CAP_UARTGPIO))
14984 + return;
14985 +
14986 + /* sb_corereg cannot be used as we have to guarantee 8-bit read/writes */
14987 + INTR_OFF(si, intr_val);
14988 +
14989 + origidx = sb_coreidx(sbh);
14990 +
14991 + cc = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
14992 + if (cc == NULL)
14993 + goto end;
14994 +
14995 + W_REG(si->osh, &cc->uart0mcr, R_REG(si->osh, &cc->uart0mcr) | 0x04);
14996 +
14997 +end:
14998 + /* restore the original index */
14999 + sb_setcoreidx(sbh, origidx);
15000 +
15001 + INTR_RESTORE(si, intr_val);
15002 +}
15003 +
15004 +/* check if the device is removed */
15005 +bool
15006 +sb_deviceremoved(sb_t *sbh)
15007 +{
15008 + uint32 w;
15009 + sb_info_t *si;
15010 +
15011 + si = SB_INFO(sbh);
15012 +
15013 + switch (BUSTYPE(si->sb.bustype)) {
15014 + case PCI_BUS:
15015 + ASSERT(si->osh);
15016 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_VID, sizeof(uint32));
15017 + if ((w & 0xFFFF) != VENDOR_BROADCOM)
15018 + return TRUE;
15019 + else
15020 + return FALSE;
15021 + default:
15022 + return FALSE;
15023 + }
15024 + return FALSE;
15025 +}
15026 +
15027 +/* Return the RAM size of the SOCRAM core */
15028 +uint32
15029 +sb_socram_size(sb_t *sbh)
15030 +{
15031 + sb_info_t *si;
15032 + uint origidx;
15033 + uint intr_val = 0;
15034 +
15035 + sbsocramregs_t *regs;
15036 + bool wasup;
15037 + uint corerev;
15038 + uint32 coreinfo;
15039 + uint memsize = 0;
15040 +
15041 + si = SB_INFO(sbh);
15042 + ASSERT(si);
15043 +
15044 + /* Block ints and save current core */
15045 + INTR_OFF(si, intr_val);
15046 + origidx = sb_coreidx(sbh);
15047 +
15048 + /* Switch to SOCRAM core */
15049 + if (!(regs = sb_setcore(sbh, SB_SOCRAM, 0)))
15050 + goto done;
15051 +
15052 + /* Get info for determining size */
15053 + if (!(wasup = sb_iscoreup(sbh)))
15054 + sb_core_reset(sbh, 0, 0);
15055 + corerev = sb_corerev(sbh);
15056 + coreinfo = R_REG(si->osh, &regs->coreinfo);
15057 +
15058 + /* Calculate size from coreinfo based on rev */
15059 + switch (corerev) {
15060 + case 0:
15061 + memsize = 1 << (16 + (coreinfo & SRCI_MS0_MASK));
15062 + break;
15063 + default: /* rev >= 1 */
15064 + memsize = 1 << (SR_BSZ_BASE + (coreinfo & SRCI_SRBSZ_MASK));
15065 + memsize *= (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
15066 + break;
15067 + }
15068 +
15069 + /* Return to previous state and core */
15070 + if (!wasup)
15071 + sb_core_disable(sbh, 0);
15072 + sb_setcoreidx(sbh, origidx);
15073 +
15074 +done:
15075 + INTR_RESTORE(si, intr_val);
15076 + return memsize;
15077 +}
15078 +
15079 +
15080 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
15081 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
15082 +++ linux.dev/arch/mips/bcm947xx/setup.c 2006-04-27 23:22:53.000000000 +0200
15083 @@ -0,0 +1,241 @@
15084 +/*
15085 + * Generic setup routines for Broadcom MIPS boards
15086 + *
15087 + * Copyright (C) 2005 Felix Fietkau <nbd@openwrt.org>
15088 + *
15089 + * This program is free software; you can redistribute it and/or modify it
15090 + * under the terms of the GNU General Public License as published by the
15091 + * Free Software Foundation; either version 2 of the License, or (at your
15092 + * option) any later version.
15093 + *
15094 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15095 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15096 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15097 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15098 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15099 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15100 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
15101 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15102 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
15103 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15104 + *
15105 + * You should have received a copy of the GNU General Public License along
15106 + * with this program; if not, write to the Free Software Foundation, Inc.,
15107 + * 675 Mass Ave, Cambridge, MA 02139, USA.
15108 + *
15109 + *
15110 + * Copyright 2005, Broadcom Corporation
15111 + * All Rights Reserved.
15112 + *
15113 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15114 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15115 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15116 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15117 + *
15118 + */
15119 +
15120 +#include <linux/config.h>
15121 +#include <linux/init.h>
15122 +#include <linux/kernel.h>
15123 +#include <linux/module.h>
15124 +#include <linux/serialP.h>
15125 +#include <linux/ide.h>
15126 +#include <asm/bootinfo.h>
15127 +#include <asm/cpu.h>
15128 +#include <asm/time.h>
15129 +#include <asm/reboot.h>
15130 +
15131 +#include <typedefs.h>
15132 +#include <osl.h>
15133 +#include <sbutils.h>
15134 +#include <bcmutils.h>
15135 +#include <bcmnvram.h>
15136 +#include <sbhndmips.h>
15137 +#include <hndmips.h>
15138 +#include <trxhdr.h>
15139 +
15140 +/* Virtual IRQ base, after last hw IRQ */
15141 +#define SBMIPS_VIRTIRQ_BASE 6
15142 +
15143 +/* # IRQs, hw and sw IRQs */
15144 +#define SBMIPS_NUMIRQS 8
15145 +
15146 +/* Global SB handle */
15147 +sb_t *bcm947xx_sbh = NULL;
15148 +spinlock_t bcm947xx_sbh_lock = SPIN_LOCK_UNLOCKED;
15149 +
15150 +/* Convenience */
15151 +#define sbh bcm947xx_sbh
15152 +#define sbh_lock bcm947xx_sbh_lock
15153 +
15154 +extern void bcm947xx_time_init(void);
15155 +extern void bcm947xx_timer_setup(struct irqaction *irq);
15156 +
15157 +#ifdef CONFIG_REMOTE_DEBUG
15158 +extern void set_debug_traps(void);
15159 +extern void rs_kgdb_hook(struct serial_state *);
15160 +extern void breakpoint(void);
15161 +#endif
15162 +
15163 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
15164 +extern struct ide_ops std_ide_ops;
15165 +#endif
15166 +
15167 +/* Kernel command line */
15168 +char arcs_cmdline[CL_SIZE] __initdata = CONFIG_CMDLINE;
15169 +extern void sb_serial_init(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
15170 +
15171 +void
15172 +bcm947xx_machine_restart(char *command)
15173 +{
15174 + printk("Please stand by while rebooting the system...\n");
15175 +
15176 + /* Set the watchdog timer to reset immediately */
15177 + __cli();
15178 + sb_watchdog(sbh, 1);
15179 + while (1);
15180 +}
15181 +
15182 +void
15183 +bcm947xx_machine_halt(void)
15184 +{
15185 + printk("System halted\n");
15186 +
15187 + /* Disable interrupts and watchdog and spin forever */
15188 + __cli();
15189 + sb_watchdog(sbh, 0);
15190 + while (1);
15191 +}
15192 +
15193 +#ifdef CONFIG_SERIAL
15194 +
15195 +static int ser_line = 0;
15196 +
15197 +typedef struct {
15198 + void *regs;
15199 + uint irq;
15200 + uint baud_base;
15201 + uint reg_shift;
15202 +} serial_port;
15203 +
15204 +static serial_port ports[4];
15205 +static int num_ports = 0;
15206 +
15207 +static void
15208 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
15209 +{
15210 + ports[num_ports].regs = regs;
15211 + ports[num_ports].irq = irq;
15212 + ports[num_ports].baud_base = baud_base;
15213 + ports[num_ports].reg_shift = reg_shift;
15214 + num_ports++;
15215 +}
15216 +
15217 +static void
15218 +do_serial_add(serial_port *port)
15219 +{
15220 + void *regs;
15221 + uint irq;
15222 + uint baud_base;
15223 + uint reg_shift;
15224 + struct serial_struct s;
15225 +
15226 + regs = port->regs;
15227 + irq = port->irq;
15228 + baud_base = port->baud_base;
15229 + reg_shift = port->reg_shift;
15230 +
15231 + memset(&s, 0, sizeof(s));
15232 +
15233 + s.line = ser_line++;
15234 + s.iomem_base = regs;
15235 + s.irq = irq + 2;
15236 + s.baud_base = baud_base / 16;
15237 + s.flags = ASYNC_BOOT_AUTOCONF;
15238 + s.io_type = SERIAL_IO_MEM;
15239 + s.iomem_reg_shift = reg_shift;
15240 +
15241 + if (early_serial_setup(&s) != 0) {
15242 + printk(KERN_ERR "Serial setup failed!\n");
15243 + }
15244 +}
15245 +
15246 +#endif /* CONFIG_SERIAL */
15247 +
15248 +void __init
15249 +brcm_setup(void)
15250 +{
15251 + char *s;
15252 + int i;
15253 + char *value;
15254 +
15255 + /* Get global SB handle */
15256 + sbh = sb_kattach();
15257 +
15258 + /* Initialize clocks and interrupts */
15259 + sb_mips_init(sbh, SBMIPS_VIRTIRQ_BASE);
15260 +
15261 + if (BCM330X(current_cpu_data.processor_id) &&
15262 + (read_c0_diag() & BRCM_PFC_AVAIL)) {
15263 + /*
15264 + * Now that the sbh is inited set the proper PFC value
15265 + */
15266 + printk("Setting the PFC to its default value\n");
15267 + enable_pfc(PFC_AUTO);
15268 + }
15269 +
15270 +
15271 +#ifdef CONFIG_SERIAL
15272 + sb_serial_init(sbh, serial_add);
15273 +
15274 + /* reverse serial ports if nvram variable starts with console=ttyS1 */
15275 + /* Initialize UARTs */
15276 + s = nvram_get("kernel_args");
15277 + if (!s) s = "";
15278 + if (!strncmp(s, "console=ttyS1", 13)) {
15279 + for (i = num_ports; i; i--)
15280 + do_serial_add(&ports[i - 1]);
15281 + } else {
15282 + for (i = 0; i < num_ports; i++)
15283 + do_serial_add(&ports[i]);
15284 + }
15285 +#endif
15286 +
15287 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
15288 + ide_ops = &std_ide_ops;
15289 +#endif
15290 +
15291 + /* Override default command line arguments */
15292 + value = nvram_get("kernel_cmdline");
15293 + if (value && strlen(value) && strncmp(value, "empty", 5))
15294 + strncpy(arcs_cmdline, value, sizeof(arcs_cmdline));
15295 +
15296 +
15297 + /* Generic setup */
15298 + _machine_restart = bcm947xx_machine_restart;
15299 + _machine_halt = bcm947xx_machine_halt;
15300 + _machine_power_off = bcm947xx_machine_halt;
15301 +
15302 + board_time_init = bcm947xx_time_init;
15303 + board_timer_setup = bcm947xx_timer_setup;
15304 +}
15305 +
15306 +const char *
15307 +get_system_type(void)
15308 +{
15309 + static char s[32];
15310 +
15311 + if (bcm947xx_sbh) {
15312 + sprintf(s, "Broadcom BCM%X chip rev %d", sb_chip(bcm947xx_sbh),
15313 + sb_chiprev(bcm947xx_sbh));
15314 + return s;
15315 + }
15316 + else
15317 + return "Broadcom BCM947XX";
15318 +}
15319 +
15320 +void __init
15321 +bus_error_init(void)
15322 +{
15323 +}
15324 +
15325 diff -urN linux.old/arch/mips/bcm947xx/sflash.c linux.dev/arch/mips/bcm947xx/sflash.c
15326 --- linux.old/arch/mips/bcm947xx/sflash.c 1970-01-01 01:00:00.000000000 +0100
15327 +++ linux.dev/arch/mips/bcm947xx/sflash.c 2006-04-27 22:11:27.000000000 +0200
15328 @@ -0,0 +1,422 @@
15329 +/*
15330 + * Broadcom SiliconBackplane chipcommon serial flash interface
15331 + *
15332 + * Copyright 2006, Broadcom Corporation
15333 + * All Rights Reserved.
15334 + *
15335 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15336 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15337 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15338 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15339 + *
15340 + * $Id: sflash.c,v 1.1.1.13 2006/02/27 03:43:16 honor Exp $
15341 + */
15342 +
15343 +#include <osl.h>
15344 +#include <typedefs.h>
15345 +#include <sbconfig.h>
15346 +#include <sbchipc.h>
15347 +#include <mipsinc.h>
15348 +#include <bcmutils.h>
15349 +#include <bcmdevs.h>
15350 +#include <sflash.h>
15351 +
15352 +/* Private global state */
15353 +static struct sflash sflash;
15354 +
15355 +/* Issue a serial flash command */
15356 +static INLINE void
15357 +sflash_cmd(chipcregs_t *cc, uint opcode)
15358 +{
15359 + W_REG(NULL, &cc->flashcontrol, SFLASH_START | opcode);
15360 + while (R_REG(NULL, &cc->flashcontrol) & SFLASH_BUSY);
15361 +}
15362 +
15363 +/* Initialize serial flash access */
15364 +struct sflash *
15365 +sflash_init(chipcregs_t *cc)
15366 +{
15367 + uint32 id, id2;
15368 +
15369 + bzero(&sflash, sizeof(sflash));
15370 +
15371 + sflash.type = R_REG(NULL, &cc->capabilities) & CAP_FLASH_MASK;
15372 +
15373 + switch (sflash.type) {
15374 + case SFLASH_ST:
15375 + /* Probe for ST chips */
15376 + sflash_cmd(cc, SFLASH_ST_DP);
15377 + sflash_cmd(cc, SFLASH_ST_RES);
15378 + id = R_REG(NULL, &cc->flashdata);
15379 + switch (id) {
15380 + case 0x11:
15381 + /* ST M25P20 2 Mbit Serial Flash */
15382 + sflash.blocksize = 64 * 1024;
15383 + sflash.numblocks = 4;
15384 + break;
15385 + case 0x12:
15386 + /* ST M25P40 4 Mbit Serial Flash */
15387 + sflash.blocksize = 64 * 1024;
15388 + sflash.numblocks = 8;
15389 + break;
15390 + case 0x13:
15391 + /* ST M25P80 8 Mbit Serial Flash */
15392 + sflash.blocksize = 64 * 1024;
15393 + sflash.numblocks = 16;
15394 + break;
15395 + case 0x14:
15396 + /* ST M25P16 16 Mbit Serial Flash */
15397 + sflash.blocksize = 64 * 1024;
15398 + sflash.numblocks = 32;
15399 + break;
15400 + case 0x15:
15401 + /* ST M25P32 32 Mbit Serial Flash */
15402 + sflash.blocksize = 64 * 1024;
15403 + sflash.numblocks = 64;
15404 + break;
15405 + case 0x16:
15406 + /* ST M25P64 64 Mbit Serial Flash */
15407 + sflash.blocksize = 64 * 1024;
15408 + sflash.numblocks = 128;
15409 + break;
15410 + case 0xbf:
15411 + W_REG(NULL, &cc->flashaddress, 1);
15412 + sflash_cmd(cc, SFLASH_ST_RES);
15413 + id2 = R_REG(NULL, &cc->flashdata);
15414 + if (id2 == 0x44) {
15415 + /* SST M25VF80 4 Mbit Serial Flash */
15416 + sflash.blocksize = 64 * 1024;
15417 + sflash.numblocks = 8;
15418 + }
15419 + break;
15420 + }
15421 + break;
15422 +
15423 + case SFLASH_AT:
15424 + /* Probe for Atmel chips */
15425 + sflash_cmd(cc, SFLASH_AT_STATUS);
15426 + id = R_REG(NULL, &cc->flashdata) & 0x3c;
15427 + switch (id) {
15428 + case 0xc:
15429 + /* Atmel AT45DB011 1Mbit Serial Flash */
15430 + sflash.blocksize = 256;
15431 + sflash.numblocks = 512;
15432 + break;
15433 + case 0x14:
15434 + /* Atmel AT45DB021 2Mbit Serial Flash */
15435 + sflash.blocksize = 256;
15436 + sflash.numblocks = 1024;
15437 + break;
15438 + case 0x1c:
15439 + /* Atmel AT45DB041 4Mbit Serial Flash */
15440 + sflash.blocksize = 256;
15441 + sflash.numblocks = 2048;
15442 + break;
15443 + case 0x24:
15444 + /* Atmel AT45DB081 8Mbit Serial Flash */
15445 + sflash.blocksize = 256;
15446 + sflash.numblocks = 4096;
15447 + break;
15448 + case 0x2c:
15449 + /* Atmel AT45DB161 16Mbit Serial Flash */
15450 + sflash.blocksize = 512;
15451 + sflash.numblocks = 4096;
15452 + break;
15453 + case 0x34:
15454 + /* Atmel AT45DB321 32Mbit Serial Flash */
15455 + sflash.blocksize = 512;
15456 + sflash.numblocks = 8192;
15457 + break;
15458 + case 0x3c:
15459 + /* Atmel AT45DB642 64Mbit Serial Flash */
15460 + sflash.blocksize = 1024;
15461 + sflash.numblocks = 8192;
15462 + break;
15463 + }
15464 + break;
15465 + }
15466 +
15467 + sflash.size = sflash.blocksize * sflash.numblocks;
15468 + return sflash.size ? &sflash : NULL;
15469 +}
15470 +
15471 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
15472 +int
15473 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
15474 +{
15475 + int cnt;
15476 + uint32 *from, *to;
15477 +
15478 + if (!len)
15479 + return 0;
15480 +
15481 + if ((offset + len) > sflash.size)
15482 + return -22;
15483 +
15484 + if ((len >= 4) && (offset & 3))
15485 + cnt = 4 - (offset & 3);
15486 + else if ((len >= 4) && ((uint32)buf & 3))
15487 + cnt = 4 - ((uint32)buf & 3);
15488 + else
15489 + cnt = len;
15490 +
15491 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
15492 + to = (uint32 *)buf;
15493 +
15494 + if (cnt < 4) {
15495 + bcopy(from, to, cnt);
15496 + return cnt;
15497 + }
15498 +
15499 + while (cnt >= 4) {
15500 + *to++ = *from++;
15501 + cnt -= 4;
15502 + }
15503 +
15504 + return (len - cnt);
15505 +}
15506 +
15507 +/* Poll for command completion. Returns zero when complete. */
15508 +int
15509 +sflash_poll(chipcregs_t *cc, uint offset)
15510 +{
15511 + if (offset >= sflash.size)
15512 + return -22;
15513 +
15514 + switch (sflash.type) {
15515 + case SFLASH_ST:
15516 + /* Check for ST Write In Progress bit */
15517 + sflash_cmd(cc, SFLASH_ST_RDSR);
15518 + return R_REG(NULL, &cc->flashdata) & SFLASH_ST_WIP;
15519 + case SFLASH_AT:
15520 + /* Check for Atmel Ready bit */
15521 + sflash_cmd(cc, SFLASH_AT_STATUS);
15522 + return !(R_REG(NULL, &cc->flashdata) & SFLASH_AT_READY);
15523 + }
15524 +
15525 + return 0;
15526 +}
15527 +
15528 +/* Write len bytes starting at offset into buf. Returns number of bytes
15529 + * written. Caller should poll for completion.
15530 + */
15531 +int
15532 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
15533 +{
15534 + struct sflash *sfl;
15535 + int ret = 0;
15536 + bool is4712b0;
15537 + uint32 page, byte, mask;
15538 +
15539 + if (!len)
15540 + return 0;
15541 +
15542 + if ((offset + len) > sflash.size)
15543 + return -22;
15544 +
15545 + sfl = &sflash;
15546 + switch (sfl->type) {
15547 + case SFLASH_ST:
15548 + mask = R_REG(NULL, &cc->chipid);
15549 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_CHIP_ID) &&
15550 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
15551 + /* Enable writes */
15552 + sflash_cmd(cc, SFLASH_ST_WREN);
15553 + if (is4712b0) {
15554 + mask = 1 << 14;
15555 + W_REG(NULL, &cc->flashaddress, offset);
15556 + W_REG(NULL, &cc->flashdata, *buf++);
15557 + /* Set chip select */
15558 + OR_REG(NULL, &cc->gpioout, mask);
15559 + /* Issue a page program with the first byte */
15560 + sflash_cmd(cc, SFLASH_ST_PP);
15561 + ret = 1;
15562 + offset++;
15563 + len--;
15564 + while (len > 0) {
15565 + if ((offset & 255) == 0) {
15566 + /* Page boundary, drop cs and return */
15567 + AND_REG(NULL, &cc->gpioout, ~mask);
15568 + if (!sflash_poll(cc, offset)) {
15569 + /* Flash rejected command */
15570 + return -11;
15571 + }
15572 + return ret;
15573 + } else {
15574 + /* Write single byte */
15575 + sflash_cmd(cc, *buf++);
15576 + }
15577 + ret++;
15578 + offset++;
15579 + len--;
15580 + }
15581 + /* All done, drop cs if needed */
15582 + if ((offset & 255) != 1) {
15583 + /* Drop cs */
15584 + AND_REG(NULL, &cc->gpioout, ~mask);
15585 + if (!sflash_poll(cc, offset)) {
15586 + /* Flash rejected command */
15587 + return -12;
15588 + }
15589 + }
15590 + } else {
15591 + ret = 1;
15592 + W_REG(NULL, &cc->flashaddress, offset);
15593 + W_REG(NULL, &cc->flashdata, *buf);
15594 + /* Page program */
15595 + sflash_cmd(cc, SFLASH_ST_PP);
15596 + }
15597 + break;
15598 + case SFLASH_AT:
15599 + mask = sfl->blocksize - 1;
15600 + page = (offset & ~mask) << 1;
15601 + byte = offset & mask;
15602 + /* Read main memory page into buffer 1 */
15603 + if (byte || (len < sfl->blocksize)) {
15604 + W_REG(NULL, &cc->flashaddress, page);
15605 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
15606 + /* 250 us for AT45DB321B */
15607 + SPINWAIT(sflash_poll(cc, offset), 1000);
15608 + ASSERT(!sflash_poll(cc, offset));
15609 + }
15610 + /* Write into buffer 1 */
15611 + for (ret = 0; (ret < (int)len) && (byte < sfl->blocksize); ret++) {
15612 + W_REG(NULL, &cc->flashaddress, byte++);
15613 + W_REG(NULL, &cc->flashdata, *buf++);
15614 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
15615 + }
15616 + /* Write buffer 1 into main memory page */
15617 + W_REG(NULL, &cc->flashaddress, page);
15618 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
15619 + break;
15620 + }
15621 +
15622 + return ret;
15623 +}
15624 +
15625 +/* Erase a region. Returns number of bytes scheduled for erasure.
15626 + * Caller should poll for completion.
15627 + */
15628 +int
15629 +sflash_erase(chipcregs_t *cc, uint offset)
15630 +{
15631 + struct sflash *sfl;
15632 +
15633 + if (offset >= sflash.size)
15634 + return -22;
15635 +
15636 + sfl = &sflash;
15637 + switch (sfl->type) {
15638 + case SFLASH_ST:
15639 + sflash_cmd(cc, SFLASH_ST_WREN);
15640 + W_REG(NULL, &cc->flashaddress, offset);
15641 + sflash_cmd(cc, SFLASH_ST_SE);
15642 + return sfl->blocksize;
15643 + case SFLASH_AT:
15644 + W_REG(NULL, &cc->flashaddress, offset << 1);
15645 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
15646 + return sfl->blocksize;
15647 + }
15648 +
15649 + return 0;
15650 +}
15651 +
15652 +/*
15653 + * writes the appropriate range of flash, a NULL buf simply erases
15654 + * the region of flash
15655 + */
15656 +int
15657 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
15658 +{
15659 + struct sflash *sfl;
15660 + uchar *block = NULL, *cur_ptr, *blk_ptr;
15661 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
15662 + uint blk_offset, blk_len, copied;
15663 + int bytes, ret = 0;
15664 +
15665 + /* Check address range */
15666 + if (len <= 0)
15667 + return 0;
15668 +
15669 + sfl = &sflash;
15670 + if ((offset + len) > sfl->size)
15671 + return -1;
15672 +
15673 + blocksize = sfl->blocksize;
15674 + mask = blocksize - 1;
15675 +
15676 + /* Allocate a block of mem */
15677 + if (!(block = MALLOC(NULL, blocksize)))
15678 + return -1;
15679 +
15680 + while (len) {
15681 + /* Align offset */
15682 + cur_offset = offset & ~mask;
15683 + cur_length = blocksize;
15684 + cur_ptr = block;
15685 +
15686 + remainder = blocksize - (offset & mask);
15687 + if (len < remainder)
15688 + cur_retlen = len;
15689 + else
15690 + cur_retlen = remainder;
15691 +
15692 + /* buf == NULL means erase only */
15693 + if (buf) {
15694 + /* Copy existing data into holding block if necessary */
15695 + if ((offset & mask) || (len < blocksize)) {
15696 + blk_offset = cur_offset;
15697 + blk_len = cur_length;
15698 + blk_ptr = cur_ptr;
15699 +
15700 + /* Copy entire block */
15701 + while (blk_len) {
15702 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
15703 + blk_offset += copied;
15704 + blk_len -= copied;
15705 + blk_ptr += copied;
15706 + }
15707 + }
15708 +
15709 + /* Copy input data into holding block */
15710 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
15711 + }
15712 +
15713 + /* Erase block */
15714 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
15715 + goto done;
15716 + while (sflash_poll(cc, (uint) cur_offset));
15717 +
15718 + /* buf == NULL means erase only */
15719 + if (!buf) {
15720 + offset += cur_retlen;
15721 + len -= cur_retlen;
15722 + continue;
15723 + }
15724 +
15725 + /* Write holding block */
15726 + while (cur_length > 0) {
15727 + if ((bytes = sflash_write(cc,
15728 + (uint) cur_offset,
15729 + (uint) cur_length,
15730 + (uchar *) cur_ptr)) < 0) {
15731 + ret = bytes;
15732 + goto done;
15733 + }
15734 + while (sflash_poll(cc, (uint) cur_offset));
15735 + cur_offset += bytes;
15736 + cur_length -= bytes;
15737 + cur_ptr += bytes;
15738 + }
15739 +
15740 + offset += cur_retlen;
15741 + len -= cur_retlen;
15742 + buf += cur_retlen;
15743 + }
15744 +
15745 + ret = len;
15746 +done:
15747 + if (block)
15748 + MFREE(NULL, block, blocksize);
15749 + return ret;
15750 +}
15751 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
15752 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
15753 +++ linux.dev/arch/mips/bcm947xx/time.c 2006-04-28 00:45:40.000000000 +0200
15754 @@ -0,0 +1,104 @@
15755 +/*
15756 + * Copyright 2006, Broadcom Corporation
15757 + * All Rights Reserved.
15758 + *
15759 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15760 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15761 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15762 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15763 + *
15764 + * $Id: time.c,v 1.1.1.10 2006/02/27 03:42:55 honor Exp $
15765 + */
15766 +#include <linux/config.h>
15767 +#include <linux/init.h>
15768 +#include <linux/kernel.h>
15769 +#include <linux/sched.h>
15770 +#include <linux/serial_reg.h>
15771 +#include <linux/interrupt.h>
15772 +#include <asm/addrspace.h>
15773 +#include <asm/io.h>
15774 +#include <asm/time.h>
15775 +
15776 +#include <typedefs.h>
15777 +#include <osl.h>
15778 +#include <bcmnvram.h>
15779 +#include <sbconfig.h>
15780 +#include <sbextif.h>
15781 +#include <sbutils.h>
15782 +#include <hndmips.h>
15783 +#include <mipsinc.h>
15784 +#include <hndcpu.h>
15785 +
15786 +/* Global SB handle */
15787 +extern void *bcm947xx_sbh;
15788 +extern spinlock_t bcm947xx_sbh_lock;
15789 +
15790 +/* Convenience */
15791 +#define sbh bcm947xx_sbh
15792 +#define sbh_lock bcm947xx_sbh_lock
15793 +
15794 +extern int panic_timeout;
15795 +static int watchdog = 0;
15796 +static u8 *mcr = NULL;
15797 +
15798 +void __init
15799 +bcm947xx_time_init(void)
15800 +{
15801 + unsigned int hz;
15802 + extifregs_t *eir;
15803 +
15804 + /*
15805 + * Use deterministic values for initial counter interrupt
15806 + * so that calibrate delay avoids encountering a counter wrap.
15807 + */
15808 + write_c0_count(0);
15809 + write_c0_compare(0xffff);
15810 +
15811 + if (!(hz = sb_cpu_clock(sbh)))
15812 + hz = 100000000;
15813 +
15814 + printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
15815 + (hz + 500000) / 1000000);
15816 +
15817 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
15818 + mips_hpt_frequency = hz / 2;
15819 +
15820 + /* Set watchdog interval in ms */
15821 + watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
15822 +
15823 + /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
15824 + if (watchdog > 0) {
15825 + if (watchdog < 3000)
15826 + watchdog = 3000;
15827 + }
15828 +
15829 + /* Set panic timeout in seconds */
15830 + panic_timeout = watchdog / 1000;
15831 +}
15832 +
15833 +static void
15834 +bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
15835 +{
15836 + /* Generic MIPS timer code */
15837 + timer_interrupt(irq, dev_id, regs);
15838 +
15839 + /* Set the watchdog timer to reset after the specified number of ms */
15840 + if (watchdog > 0)
15841 + sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
15842 +}
15843 +
15844 +static struct irqaction bcm947xx_timer_irqaction = {
15845 + bcm947xx_timer_interrupt,
15846 + SA_INTERRUPT,
15847 + 0,
15848 + "timer",
15849 + NULL,
15850 + NULL
15851 +};
15852 +
15853 +void __init
15854 +bcm947xx_timer_setup(struct irqaction *irq)
15855 +{
15856 + /* Enable the timer interrupt */
15857 + setup_irq(7, &bcm947xx_timer_irqaction);
15858 +}
15859 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
15860 --- linux.old/arch/mips/config-shared.in 2006-04-27 18:04:37.000000000 +0200
15861 +++ linux.dev/arch/mips/config-shared.in 2006-04-27 19:24:19.000000000 +0200
15862 @@ -208,6 +208,14 @@
15863 fi
15864 define_bool CONFIG_MIPS_RTC y
15865 fi
15866 +dep_bool 'Support for Broadcom MIPS-based boards' CONFIG_MIPS_BRCM $CONFIG_EXPERIMENTAL
15867 +dep_bool 'Support for Broadcom BCM947XX' CONFIG_BCM947XX $CONFIG_MIPS_BRCM
15868 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15869 + bool ' Support for Broadcom BCM4710' CONFIG_BCM4710
15870 + bool ' Support for Broadcom BCM4310' CONFIG_BCM4310
15871 + bool ' Support for Broadcom BCM4704' CONFIG_BCM4704
15872 + bool ' Support for Broadcom BCM5365' CONFIG_BCM5365
15873 +fi
15874 bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
15875 bool 'Support for TANBAC TB0226 (Mbase)' CONFIG_TANBAC_TB0226
15876 bool 'Support for TANBAC TB0229 (VR4131DIMM)' CONFIG_TANBAC_TB0229
15877 @@ -229,6 +237,11 @@
15878 define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
15879
15880 #
15881 +# Provide an option for a default kernel command line
15882 +#
15883 +string 'Default kernel command string' CONFIG_CMDLINE ""
15884 +
15885 +#
15886 # Select some configuration options automatically based on user selections.
15887 #
15888 if [ "$CONFIG_ACER_PICA_61" = "y" ]; then
15889 @@ -554,6 +567,12 @@
15890 define_bool CONFIG_SWAP_IO_SPACE_L y
15891 define_bool CONFIG_BOOT_ELF32 y
15892 fi
15893 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15894 + define_bool CONFIG_PCI y
15895 + define_bool CONFIG_NONCOHERENT_IO y
15896 + define_bool CONFIG_NEW_TIME_C y
15897 + define_bool CONFIG_NEW_IRQ y
15898 +fi
15899 if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
15900 define_bool CONFIG_ARC32 y
15901 define_bool CONFIG_ARC_MEMORY y
15902 @@ -1042,7 +1062,11 @@
15903
15904 bool 'Are you using a crosscompiler' CONFIG_CROSSCOMPILE
15905 bool 'Enable run-time debugging' CONFIG_RUNTIME_DEBUG
15906 -bool 'Remote GDB kernel debugging' CONFIG_KGDB
15907 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15908 + bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG
15909 +else
15910 + bool 'Remote GDB kernel debugging' CONFIG_KGDB
15911 +fi
15912 dep_bool ' Console output to GDB' CONFIG_GDB_CONSOLE $CONFIG_KGDB
15913 if [ "$CONFIG_KGDB" = "y" ]; then
15914 define_bool CONFIG_DEBUG_INFO y
15915 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
15916 --- linux.old/arch/mips/kernel/cpu-probe.c 2006-04-27 18:04:37.000000000 +0200
15917 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2006-04-27 19:24:19.000000000 +0200
15918 @@ -162,7 +162,7 @@
15919
15920 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
15921 {
15922 - switch (c->processor_id & 0xff00) {
15923 + switch (c->processor_id & PRID_IMP_MASK) {
15924 case PRID_IMP_R2000:
15925 c->cputype = CPU_R2000;
15926 c->isa_level = MIPS_CPU_ISA_I;
15927 @@ -172,7 +172,7 @@
15928 c->tlbsize = 64;
15929 break;
15930 case PRID_IMP_R3000:
15931 - if ((c->processor_id & 0xff) == PRID_REV_R3000A)
15932 + if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A)
15933 if (cpu_has_confreg())
15934 c->cputype = CPU_R3081E;
15935 else
15936 @@ -187,12 +187,12 @@
15937 break;
15938 case PRID_IMP_R4000:
15939 if (read_c0_config() & CONF_SC) {
15940 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
15941 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
15942 c->cputype = CPU_R4400PC;
15943 else
15944 c->cputype = CPU_R4000PC;
15945 } else {
15946 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
15947 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
15948 c->cputype = CPU_R4400SC;
15949 else
15950 c->cputype = CPU_R4000SC;
15951 @@ -438,7 +438,7 @@
15952 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
15953 {
15954 decode_config1(c);
15955 - switch (c->processor_id & 0xff00) {
15956 + switch (c->processor_id & PRID_IMP_MASK) {
15957 case PRID_IMP_4KC:
15958 c->cputype = CPU_4KC;
15959 c->isa_level = MIPS_CPU_ISA_M32;
15960 @@ -479,10 +479,10 @@
15961 {
15962 decode_config1(c);
15963 c->options |= MIPS_CPU_PREFETCH;
15964 - switch (c->processor_id & 0xff00) {
15965 + switch (c->processor_id & PRID_IMP_MASK) {
15966 case PRID_IMP_AU1_REV1:
15967 case PRID_IMP_AU1_REV2:
15968 - switch ((c->processor_id >> 24) & 0xff) {
15969 + switch ((c->processor_id >> 24) & PRID_REV_MASK) {
15970 case 0:
15971 c->cputype = CPU_AU1000;
15972 break;
15973 @@ -510,10 +510,34 @@
15974 }
15975 }
15976
15977 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
15978 +{
15979 + decode_config1(c);
15980 + c->options |= MIPS_CPU_PREFETCH;
15981 + switch (c->processor_id & PRID_IMP_MASK) {
15982 + case PRID_IMP_BCM4710:
15983 + c->cputype = CPU_BCM4710;
15984 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
15985 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
15986 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
15987 + break;
15988 + case PRID_IMP_4KC:
15989 + case PRID_IMP_BCM3302:
15990 + c->cputype = CPU_BCM3302;
15991 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
15992 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
15993 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
15994 + break;
15995 + default:
15996 + c->cputype = CPU_UNKNOWN;
15997 + break;
15998 + }
15999 +}
16000 +
16001 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
16002 {
16003 decode_config1(c);
16004 - switch (c->processor_id & 0xff00) {
16005 + switch (c->processor_id & PRID_IMP_MASK) {
16006 case PRID_IMP_SB1:
16007 c->cputype = CPU_SB1;
16008 c->isa_level = MIPS_CPU_ISA_M64;
16009 @@ -535,7 +559,7 @@
16010 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
16011 {
16012 decode_config1(c);
16013 - switch (c->processor_id & 0xff00) {
16014 + switch (c->processor_id & PRID_IMP_MASK) {
16015 case PRID_IMP_SR71000:
16016 c->cputype = CPU_SR71000;
16017 c->isa_level = MIPS_CPU_ISA_M64;
16018 @@ -560,7 +584,7 @@
16019 c->cputype = CPU_UNKNOWN;
16020
16021 c->processor_id = read_c0_prid();
16022 - switch (c->processor_id & 0xff0000) {
16023 + switch (c->processor_id & PRID_COMP_MASK) {
16024
16025 case PRID_COMP_LEGACY:
16026 cpu_probe_legacy(c);
16027 @@ -571,6 +595,9 @@
16028 case PRID_COMP_ALCHEMY:
16029 cpu_probe_alchemy(c);
16030 break;
16031 + case PRID_COMP_BROADCOM:
16032 + cpu_probe_broadcom(c);
16033 + break;
16034 case PRID_COMP_SIBYTE:
16035 cpu_probe_sibyte(c);
16036 break;
16037 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
16038 --- linux.old/arch/mips/kernel/head.S 2006-04-27 18:04:37.000000000 +0200
16039 +++ linux.dev/arch/mips/kernel/head.S 2006-04-27 19:24:19.000000000 +0200
16040 @@ -28,12 +28,20 @@
16041 #include <asm/mipsregs.h>
16042 #include <asm/stackframe.h>
16043
16044 +#ifdef CONFIG_BCM4710
16045 +#undef eret
16046 +#define eret nop; nop; eret
16047 +#endif
16048 +
16049 .text
16050 + j kernel_entry
16051 + nop
16052 +
16053 /*
16054 * Reserved space for exception handlers.
16055 * Necessary for machines which link their kernels at KSEG0.
16056 */
16057 - .fill 0x400
16058 + .fill 0x3f4
16059
16060 /* The following two symbols are used for kernel profiling. */
16061 EXPORT(stext)
16062 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
16063 --- linux.old/arch/mips/kernel/proc.c 2006-04-27 18:04:37.000000000 +0200
16064 +++ linux.dev/arch/mips/kernel/proc.c 2006-04-27 19:24:19.000000000 +0200
16065 @@ -78,9 +78,10 @@
16066 [CPU_AU1550] "Au1550",
16067 [CPU_24K] "MIPS 24K",
16068 [CPU_AU1200] "Au1200",
16069 + [CPU_BCM4710] "BCM4710",
16070 + [CPU_BCM3302] "BCM3302",
16071 };
16072
16073 -
16074 static int show_cpuinfo(struct seq_file *m, void *v)
16075 {
16076 unsigned int version = current_cpu_data.processor_id;
16077 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
16078 --- linux.old/arch/mips/kernel/setup.c 2006-04-27 18:04:37.000000000 +0200
16079 +++ linux.dev/arch/mips/kernel/setup.c 2006-04-27 19:24:19.000000000 +0200
16080 @@ -493,6 +493,7 @@
16081 void swarm_setup(void);
16082 void hp_setup(void);
16083 void au1x00_setup(void);
16084 + void brcm_setup(void);
16085 void frame_info_init(void);
16086
16087 frame_info_init();
16088 @@ -691,6 +692,11 @@
16089 pmc_yosemite_setup();
16090 break;
16091 #endif
16092 +#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4310)
16093 + case MACH_GROUP_BRCM:
16094 + brcm_setup();
16095 + break;
16096 +#endif
16097 default:
16098 panic("Unsupported architecture");
16099 }
16100 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
16101 --- linux.old/arch/mips/kernel/traps.c 2006-04-27 18:04:37.000000000 +0200
16102 +++ linux.dev/arch/mips/kernel/traps.c 2006-04-27 19:24:19.000000000 +0200
16103 @@ -920,6 +920,7 @@
16104 void __init trap_init(void)
16105 {
16106 extern char except_vec1_generic;
16107 + extern char except_vec2_generic;
16108 extern char except_vec3_generic, except_vec3_r4000;
16109 extern char except_vec_ejtag_debug;
16110 extern char except_vec4;
16111 @@ -927,6 +928,7 @@
16112
16113 /* Copy the generic exception handler code to it's final destination. */
16114 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
16115 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
16116
16117 /*
16118 * Setup default vectors
16119 @@ -985,6 +987,12 @@
16120 set_except_vector(13, handle_tr);
16121 set_except_vector(22, handle_mdmx);
16122
16123 + if (current_cpu_data.cputype == CPU_SB1) {
16124 + /* Enable timer interrupt and scd mapped interrupt */
16125 + clear_c0_status(0xf000);
16126 + set_c0_status(0xc00);
16127 + }
16128 +
16129 if (cpu_has_fpu && !cpu_has_nofpuex)
16130 set_except_vector(15, handle_fpe);
16131
16132 diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
16133 --- linux.old/arch/mips/mm/c-r4k.c 2006-04-27 18:04:37.000000000 +0200
16134 +++ linux.dev/arch/mips/mm/c-r4k.c 2006-04-27 19:24:19.000000000 +0200
16135 @@ -1166,3 +1166,47 @@
16136 build_clear_page();
16137 build_copy_page();
16138 }
16139 +
16140 +#ifdef CONFIG_BCM4704
16141 +static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
16142 +{
16143 + unsigned long ic_lsize = current_cpu_data.icache.linesz;
16144 + int i;
16145 + for (i = 0; i < nbytes; i += ic_lsize)
16146 + fill_icache_line((addr + i));
16147 +}
16148 +
16149 +/*
16150 + * This must be run from the cache on 4704A0
16151 + * so there are no mips core BIU ops in progress
16152 + * when the PFC is enabled.
16153 + */
16154 +#define PFC_CR0 0xff400000 /* control reg 0 */
16155 +#define PFC_CR1 0xff400004 /* control reg 1 */
16156 +static void __init enable_pfc(u32 mode)
16157 +{
16158 + /* write range */
16159 + *(volatile u32 *)PFC_CR1 = 0xffff0000;
16160 +
16161 + /* enable */
16162 + *(volatile u32 *)PFC_CR0 = mode;
16163 +}
16164 +#endif
16165 +
16166 +
16167 +void check_enable_mips_pfc(int val)
16168 +{
16169 +
16170 +#ifdef CONFIG_BCM4704
16171 + struct cpuinfo_mips *c = &current_cpu_data;
16172 +
16173 + /* enable prefetch cache */
16174 + if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
16175 + && (read_c0_diag() & (1 << 29))) {
16176 + mips32_icache_fill((unsigned long) &enable_pfc, 64);
16177 + enable_pfc(val);
16178 + }
16179 +#endif
16180 +}
16181 +
16182 +
16183 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
16184 --- linux.old/arch/mips/pci/Makefile 2006-04-27 18:04:37.000000000 +0200
16185 +++ linux.dev/arch/mips/pci/Makefile 2006-04-27 19:24:19.000000000 +0200
16186 @@ -13,7 +13,9 @@
16187 obj-$(CONFIG_MIPS_MSC) += ops-msc.o
16188 obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
16189 obj-$(CONFIG_SNI_RM200_PCI) += ops-sni.o
16190 +ifndef CONFIG_BCM947XX
16191 obj-y += pci.o
16192 +endif
16193 obj-$(CONFIG_PCI_AUTO) += pci_auto.o
16194
16195 include $(TOPDIR)/Rules.make
16196 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
16197 --- linux.old/drivers/char/serial.c 2006-04-27 18:04:37.000000000 +0200
16198 +++ linux.dev/drivers/char/serial.c 2006-04-27 19:24:19.000000000 +0200
16199 @@ -444,6 +444,10 @@
16200 return inb(info->port+1);
16201 #endif
16202 case SERIAL_IO_MEM:
16203 +#ifdef CONFIG_BCM4310
16204 + readb((unsigned long) info->iomem_base +
16205 + (UART_SCR<<info->iomem_reg_shift));
16206 +#endif
16207 return readb((unsigned long) info->iomem_base +
16208 (offset<<info->iomem_reg_shift));
16209 default:
16210 @@ -464,6 +468,9 @@
16211 case SERIAL_IO_MEM:
16212 writeb(value, (unsigned long) info->iomem_base +
16213 (offset<<info->iomem_reg_shift));
16214 +#ifdef CONFIG_BCM4704
16215 + *((volatile unsigned int *) KSEG1ADDR(0x18000000));
16216 +#endif
16217 break;
16218 default:
16219 outb(value, info->port+offset);
16220 @@ -1728,7 +1735,7 @@
16221 /* Special case since 134 is really 134.5 */
16222 quot = (2*baud_base / 269);
16223 else if (baud)
16224 - quot = baud_base / baud;
16225 + quot = (baud_base + (baud / 2)) / baud;
16226 }
16227 /* If the quotient is zero refuse the change */
16228 if (!quot && old_termios) {
16229 @@ -1745,12 +1752,12 @@
16230 /* Special case since 134 is really 134.5 */
16231 quot = (2*baud_base / 269);
16232 else if (baud)
16233 - quot = baud_base / baud;
16234 + quot = (baud_base + (baud / 2)) / baud;
16235 }
16236 }
16237 /* As a last resort, if the quotient is zero, default to 9600 bps */
16238 if (!quot)
16239 - quot = baud_base / 9600;
16240 + quot = (baud_base + 4800) / 9600;
16241 /*
16242 * Work around a bug in the Oxford Semiconductor 952 rev B
16243 * chip which causes it to seriously miscalculate baud rates
16244 @@ -5994,6 +6001,13 @@
16245 * Divisor, bytesize and parity
16246 */
16247 state = rs_table + co->index;
16248 + /*
16249 + * Safe guard: state structure must have been initialized
16250 + */
16251 + if (state->iomem_base == NULL) {
16252 + printk("!unable to setup serial console!\n");
16253 + return -1;
16254 + }
16255 if (doflow)
16256 state->flags |= ASYNC_CONS_FLOW;
16257 info = &async_sercons;
16258 @@ -6007,7 +6021,7 @@
16259 info->io_type = state->io_type;
16260 info->iomem_base = state->iomem_base;
16261 info->iomem_reg_shift = state->iomem_reg_shift;
16262 - quot = state->baud_base / baud;
16263 + quot = (state->baud_base + (baud / 2)) / baud;
16264 cval = cflag & (CSIZE | CSTOPB);
16265 #if defined(__powerpc__) || defined(__alpha__)
16266 cval >>= 8;
16267 diff -urN linux.old/drivers/net/Makefile linux.dev/drivers/net/Makefile
16268 --- linux.old/drivers/net/Makefile 2006-04-27 18:04:38.000000000 +0200
16269 +++ linux.dev/drivers/net/Makefile 2006-05-04 01:41:03.000000000 +0200
16270 @@ -3,6 +3,8 @@
16271 # Makefile for the Linux network (ethercard) device drivers.
16272 #
16273
16274 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
16275 +
16276 obj-y :=
16277 obj-m :=
16278 obj-n :=
16279 diff -urN linux.old/drivers/parport/Config.in linux.dev/drivers/parport/Config.in
16280 --- linux.old/drivers/parport/Config.in 2006-04-27 18:04:38.000000000 +0200
16281 +++ linux.dev/drivers/parport/Config.in 2006-04-27 19:24:19.000000000 +0200
16282 @@ -11,6 +11,7 @@
16283 tristate 'Parallel port support' CONFIG_PARPORT
16284 if [ "$CONFIG_PARPORT" != "n" ]; then
16285 dep_tristate ' PC-style hardware' CONFIG_PARPORT_PC $CONFIG_PARPORT
16286 + dep_tristate ' Asus WL500g parallel port' CONFIG_PARPORT_SPLINK $CONFIG_PARPORT
16287 if [ "$CONFIG_PARPORT_PC" != "n" -a "$CONFIG_SERIAL" != "n" ]; then
16288 if [ "$CONFIG_SERIAL" = "m" ]; then
16289 define_tristate CONFIG_PARPORT_PC_CML1 m
16290 diff -urN linux.old/drivers/parport/Makefile linux.dev/drivers/parport/Makefile
16291 --- linux.old/drivers/parport/Makefile 2006-04-27 18:04:38.000000000 +0200
16292 +++ linux.dev/drivers/parport/Makefile 2006-04-27 19:24:19.000000000 +0200
16293 @@ -22,6 +22,7 @@
16294
16295 obj-$(CONFIG_PARPORT) += parport.o
16296 obj-$(CONFIG_PARPORT_PC) += parport_pc.o
16297 +obj-$(CONFIG_PARPORT_SPLINK) += parport_splink.o
16298 obj-$(CONFIG_PARPORT_PC_PCMCIA) += parport_cs.o
16299 obj-$(CONFIG_PARPORT_AMIGA) += parport_amiga.o
16300 obj-$(CONFIG_PARPORT_MFC3) += parport_mfc3.o
16301 diff -urN linux.old/drivers/parport/parport_splink.c linux.dev/drivers/parport/parport_splink.c
16302 --- linux.old/drivers/parport/parport_splink.c 1970-01-01 01:00:00.000000000 +0100
16303 +++ linux.dev/drivers/parport/parport_splink.c 2006-04-27 19:24:19.000000000 +0200
16304 @@ -0,0 +1,345 @@
16305 +/* Low-level parallel port routines for the ASUS WL-500g built-in port
16306 + *
16307 + * Author: Nuno Grilo <nuno.grilo@netcabo.pt>
16308 + * Based on parport_pc source
16309 + */
16310 +
16311 +#include <linux/config.h>
16312 +#include <linux/module.h>
16313 +#include <linux/init.h>
16314 +#include <linux/ioport.h>
16315 +#include <linux/kernel.h>
16316 +#include <linux/slab.h>
16317 +#include <linux/parport.h>
16318 +#include <linux/parport_pc.h>
16319 +
16320 +#define SPLINK_ADDRESS 0xBF800010
16321 +
16322 +#undef DEBUG
16323 +
16324 +#ifdef DEBUG
16325 +#define DPRINTK printk
16326 +#else
16327 +#define DPRINTK(stuff...)
16328 +#endif
16329 +
16330 +
16331 +/* __parport_splink_frob_control differs from parport_splink_frob_control in that
16332 + * it doesn't do any extra masking. */
16333 +static __inline__ unsigned char __parport_splink_frob_control (struct parport *p,
16334 + unsigned char mask,
16335 + unsigned char val)
16336 +{
16337 + struct parport_pc_private *priv = p->physport->private_data;
16338 + unsigned char *io = (unsigned char *) p->base;
16339 + unsigned char ctr = priv->ctr;
16340 +#ifdef DEBUG_PARPORT
16341 + printk (KERN_DEBUG
16342 + "__parport_splink_frob_control(%02x,%02x): %02x -> %02x\n",
16343 + mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable);
16344 +#endif
16345 + ctr = (ctr & ~mask) ^ val;
16346 + ctr &= priv->ctr_writable; /* only write writable bits. */
16347 + *(io+2) = ctr;
16348 + priv->ctr = ctr; /* Update soft copy */
16349 + return ctr;
16350 +}
16351 +
16352 +
16353 +
16354 +static void parport_splink_data_forward (struct parport *p)
16355 +{
16356 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
16357 + __parport_splink_frob_control (p, 0x20, 0);
16358 +}
16359 +
16360 +static void parport_splink_data_reverse (struct parport *p)
16361 +{
16362 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
16363 + __parport_splink_frob_control (p, 0x20, 0x20);
16364 +}
16365 +
16366 +/*
16367 +static void parport_splink_interrupt(int irq, void *dev_id, struct pt_regs *regs)
16368 +{
16369 + DPRINTK(KERN_DEBUG "parport_splink: IRQ handler called\n");
16370 + parport_generic_irq(irq, (struct parport *) dev_id, regs);
16371 +}
16372 +*/
16373 +
16374 +static void parport_splink_enable_irq(struct parport *p)
16375 +{
16376 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_enable_irq called\n");
16377 + __parport_splink_frob_control (p, 0x10, 0x10);
16378 +}
16379 +
16380 +static void parport_splink_disable_irq(struct parport *p)
16381 +{
16382 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_disable_irq called\n");
16383 + __parport_splink_frob_control (p, 0x10, 0);
16384 +}
16385 +
16386 +static void parport_splink_init_state(struct pardevice *dev, struct parport_state *s)
16387 +{
16388 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_init_state called\n");
16389 + s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0);
16390 + if (dev->irq_func &&
16391 + dev->port->irq != PARPORT_IRQ_NONE)
16392 + /* Set ackIntEn */
16393 + s->u.pc.ctr |= 0x10;
16394 +}
16395 +
16396 +static void parport_splink_save_state(struct parport *p, struct parport_state *s)
16397 +{
16398 + const struct parport_pc_private *priv = p->physport->private_data;
16399 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_save_state called\n");
16400 + s->u.pc.ctr = priv->ctr;
16401 +}
16402 +
16403 +static void parport_splink_restore_state(struct parport *p, struct parport_state *s)
16404 +{
16405 + struct parport_pc_private *priv = p->physport->private_data;
16406 + unsigned char *io = (unsigned char *) p->base;
16407 + unsigned char ctr = s->u.pc.ctr;
16408 +
16409 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_restore_state called\n");
16410 + *(io+2) = ctr;
16411 + priv->ctr = ctr;
16412 +}
16413 +
16414 +static void parport_splink_setup_interrupt(void) {
16415 + return;
16416 +}
16417 +
16418 +static void parport_splink_write_data(struct parport *p, unsigned char d) {
16419 + DPRINTK(KERN_DEBUG "parport_splink: write data called\n");
16420 + unsigned char *io = (unsigned char *) p->base;
16421 + *io = d;
16422 +}
16423 +
16424 +static unsigned char parport_splink_read_data(struct parport *p) {
16425 + DPRINTK(KERN_DEBUG "parport_splink: read data called\n");
16426 + unsigned char *io = (unsigned char *) p->base;
16427 + return *io;
16428 +}
16429 +
16430 +static void parport_splink_write_control(struct parport *p, unsigned char d)
16431 +{
16432 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16433 + PARPORT_CONTROL_AUTOFD |
16434 + PARPORT_CONTROL_INIT |
16435 + PARPORT_CONTROL_SELECT);
16436 +
16437 + DPRINTK(KERN_DEBUG "parport_splink: write control called\n");
16438 + /* Take this out when drivers have adapted to the newer interface. */
16439 + if (d & 0x20) {
16440 + printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n",
16441 + p->name, p->cad->name);
16442 + parport_splink_data_reverse (p);
16443 + }
16444 +
16445 + __parport_splink_frob_control (p, wm, d & wm);
16446 +}
16447 +
16448 +static unsigned char parport_splink_read_control(struct parport *p)
16449 +{
16450 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16451 + PARPORT_CONTROL_AUTOFD |
16452 + PARPORT_CONTROL_INIT |
16453 + PARPORT_CONTROL_SELECT);
16454 + DPRINTK(KERN_DEBUG "parport_splink: read control called\n");
16455 + const struct parport_pc_private *priv = p->physport->private_data;
16456 + return priv->ctr & wm; /* Use soft copy */
16457 +}
16458 +
16459 +static unsigned char parport_splink_frob_control (struct parport *p, unsigned char mask,
16460 + unsigned char val)
16461 +{
16462 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16463 + PARPORT_CONTROL_AUTOFD |
16464 + PARPORT_CONTROL_INIT |
16465 + PARPORT_CONTROL_SELECT);
16466 +
16467 + DPRINTK(KERN_DEBUG "parport_splink: frob control called\n");
16468 + /* Take this out when drivers have adapted to the newer interface. */
16469 + if (mask & 0x20) {
16470 + printk (KERN_DEBUG "%s (%s): use data_%s for this!\n",
16471 + p->name, p->cad->name,
16472 + (val & 0x20) ? "reverse" : "forward");
16473 + if (val & 0x20)
16474 + parport_splink_data_reverse (p);
16475 + else
16476 + parport_splink_data_forward (p);
16477 + }
16478 +
16479 + /* Restrict mask and val to control lines. */
16480 + mask &= wm;
16481 + val &= wm;
16482 +
16483 + return __parport_splink_frob_control (p, mask, val);
16484 +}
16485 +
16486 +static unsigned char parport_splink_read_status(struct parport *p)
16487 +{
16488 + DPRINTK(KERN_DEBUG "parport_splink: read status called\n");
16489 + unsigned char *io = (unsigned char *) p->base;
16490 + return *(io+1);
16491 +}
16492 +
16493 +static void parport_splink_inc_use_count(void)
16494 +{
16495 +#ifdef MODULE
16496 + MOD_INC_USE_COUNT;
16497 +#endif
16498 +}
16499 +
16500 +static void parport_splink_dec_use_count(void)
16501 +{
16502 +#ifdef MODULE
16503 + MOD_DEC_USE_COUNT;
16504 +#endif
16505 +}
16506 +
16507 +static struct parport_operations parport_splink_ops =
16508 +{
16509 + parport_splink_write_data,
16510 + parport_splink_read_data,
16511 +
16512 + parport_splink_write_control,
16513 + parport_splink_read_control,
16514 + parport_splink_frob_control,
16515 +
16516 + parport_splink_read_status,
16517 +
16518 + parport_splink_enable_irq,
16519 + parport_splink_disable_irq,
16520 +
16521 + parport_splink_data_forward,
16522 + parport_splink_data_reverse,
16523 +
16524 + parport_splink_init_state,
16525 + parport_splink_save_state,
16526 + parport_splink_restore_state,
16527 +
16528 + parport_splink_inc_use_count,
16529 + parport_splink_dec_use_count,
16530 +
16531 + parport_ieee1284_epp_write_data,
16532 + parport_ieee1284_epp_read_data,
16533 + parport_ieee1284_epp_write_addr,
16534 + parport_ieee1284_epp_read_addr,
16535 +
16536 + parport_ieee1284_ecp_write_data,
16537 + parport_ieee1284_ecp_read_data,
16538 + parport_ieee1284_ecp_write_addr,
16539 +
16540 + parport_ieee1284_write_compat,
16541 + parport_ieee1284_read_nibble,
16542 + parport_ieee1284_read_byte,
16543 +};
16544 +
16545 +/* --- Initialisation code -------------------------------- */
16546 +
16547 +static struct parport *parport_splink_probe_port (unsigned long int base)
16548 +{
16549 + struct parport_pc_private *priv;
16550 + struct parport_operations *ops;
16551 + struct parport *p;
16552 +
16553 + if (check_mem_region(base, 3)) {
16554 + printk (KERN_DEBUG "parport (0x%lx): iomem region not available\n", base);
16555 + return NULL;
16556 + }
16557 + priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
16558 + if (!priv) {
16559 + printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base);
16560 + return NULL;
16561 + }
16562 + ops = kmalloc (sizeof (struct parport_operations), GFP_KERNEL);
16563 + if (!ops) {
16564 + printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n",
16565 + base);
16566 + kfree (priv);
16567 + return NULL;
16568 + }
16569 + memcpy (ops, &parport_splink_ops, sizeof (struct parport_operations));
16570 + priv->ctr = 0xc;
16571 + priv->ctr_writable = 0xff;
16572 +
16573 + if (!(p = parport_register_port(base, PARPORT_IRQ_NONE,
16574 + PARPORT_DMA_NONE, ops))) {
16575 + printk (KERN_DEBUG "parport (0x%lx): registration failed!\n",
16576 + base);
16577 + kfree (priv);
16578 + kfree (ops);
16579 + return NULL;
16580 + }
16581 +
16582 + p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
16583 + p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
16584 + p->private_data = priv;
16585 +
16586 + parport_proc_register(p);
16587 + request_mem_region (p->base, 3, p->name);
16588 +
16589 + /* Done probing. Now put the port into a sensible start-up state. */
16590 + parport_splink_write_data(p, 0);
16591 + parport_splink_data_forward (p);
16592 +
16593 + /* Now that we've told the sharing engine about the port, and
16594 + found out its characteristics, let the high-level drivers
16595 + know about it. */
16596 + parport_announce_port (p);
16597 +
16598 + DPRINTK(KERN_DEBUG "parport (0x%lx): init ok!\n",
16599 + base);
16600 + return p;
16601 +}
16602 +
16603 +static void parport_splink_unregister_port(struct parport *p) {
16604 + struct parport_pc_private *priv = p->private_data;
16605 + struct parport_operations *ops = p->ops;
16606 +
16607 + if (p->irq != PARPORT_IRQ_NONE)
16608 + free_irq(p->irq, p);
16609 + release_mem_region(p->base, 3);
16610 + parport_proc_unregister(p);
16611 + kfree (priv);
16612 + parport_unregister_port(p);
16613 + kfree (ops);
16614 +}
16615 +
16616 +
16617 +int parport_splink_init(void)
16618 +{
16619 + int ret;
16620 +
16621 + DPRINTK(KERN_DEBUG "parport_splink init called\n");
16622 + parport_splink_setup_interrupt();
16623 + ret = !parport_splink_probe_port(SPLINK_ADDRESS);
16624 +
16625 + return ret;
16626 +}
16627 +
16628 +void parport_splink_cleanup(void) {
16629 + struct parport *p = parport_enumerate(), *tmp;
16630 + DPRINTK(KERN_DEBUG "parport_splink cleanup called\n");
16631 + if (p->size) {
16632 + if (p->modes & PARPORT_MODE_PCSPP) {
16633 + while(p) {
16634 + tmp = p->next;
16635 + parport_splink_unregister_port(p);
16636 + p = tmp;
16637 + }
16638 + }
16639 + }
16640 +}
16641 +
16642 +MODULE_AUTHOR("Nuno Grilo <nuno.grilo@netcabo.pt>");
16643 +MODULE_DESCRIPTION("Parport Driver for ASUS WL-500g router builtin Port");
16644 +MODULE_SUPPORTED_DEVICE("ASUS WL-500g builtin Parallel Port");
16645 +MODULE_LICENSE("GPL");
16646 +
16647 +module_init(parport_splink_init)
16648 +module_exit(parport_splink_cleanup)
16649 +
16650 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
16651 --- linux.old/include/asm-mips/bootinfo.h 2006-04-27 18:04:38.000000000 +0200
16652 +++ linux.dev/include/asm-mips/bootinfo.h 2006-04-27 19:24:19.000000000 +0200
16653 @@ -37,6 +37,7 @@
16654 #define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */
16655 #define MACH_GROUP_LASAT 21
16656 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
16657 +#define MACH_GROUP_BRCM 23 /* Broadcom */
16658
16659 /*
16660 * Valid machtype values for group unknown (low order halfword of mips_machtype)
16661 @@ -197,6 +198,15 @@
16662 #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
16663
16664 /*
16665 + * Valid machtypes for group Broadcom
16666 + */
16667 +#define MACH_BCM93725 0
16668 +#define MACH_BCM93725_VJ 1
16669 +#define MACH_BCM93730 2
16670 +#define MACH_BCM947XX 3
16671 +#define MACH_BCM933XX 4
16672 +
16673 +/*
16674 * Valid machtype for group TITAN
16675 */
16676 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
16677 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
16678 --- linux.old/include/asm-mips/cpu.h 2006-04-27 18:04:38.000000000 +0200
16679 +++ linux.dev/include/asm-mips/cpu.h 2006-04-27 19:24:19.000000000 +0200
16680 @@ -22,6 +22,11 @@
16681 spec.
16682 */
16683
16684 +#define PRID_COPT_MASK 0xff000000
16685 +#define PRID_COMP_MASK 0x00ff0000
16686 +#define PRID_IMP_MASK 0x0000ff00
16687 +#define PRID_REV_MASK 0x000000ff
16688 +
16689 #define PRID_COMP_LEGACY 0x000000
16690 #define PRID_COMP_MIPS 0x010000
16691 #define PRID_COMP_BROADCOM 0x020000
16692 @@ -58,6 +63,7 @@
16693 #define PRID_IMP_RM7000 0x2700
16694 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
16695 #define PRID_IMP_RM9000 0x3400
16696 +#define PRID_IMP_BCM4710 0x4000
16697 #define PRID_IMP_R5432 0x5400
16698 #define PRID_IMP_R5500 0x5500
16699 #define PRID_IMP_4KC 0x8000
16700 @@ -66,10 +72,16 @@
16701 #define PRID_IMP_4KEC 0x8400
16702 #define PRID_IMP_4KSC 0x8600
16703 #define PRID_IMP_25KF 0x8800
16704 +#define PRID_IMP_BCM3302 0x9000
16705 +#define PRID_IMP_BCM3303 0x9100
16706 #define PRID_IMP_24K 0x9300
16707
16708 #define PRID_IMP_UNKNOWN 0xff00
16709
16710 +#define BCM330X(id) \
16711 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
16712 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
16713 +
16714 /*
16715 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
16716 */
16717 @@ -174,7 +186,9 @@
16718 #define CPU_AU1550 57
16719 #define CPU_24K 58
16720 #define CPU_AU1200 59
16721 -#define CPU_LAST 59
16722 +#define CPU_BCM4710 60
16723 +#define CPU_BCM3302 61
16724 +#define CPU_LAST 61
16725
16726 /*
16727 * ISA Level encodings
16728 diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
16729 --- linux.old/include/asm-mips/r4kcache.h 2006-04-27 18:04:38.000000000 +0200
16730 +++ linux.dev/include/asm-mips/r4kcache.h 2006-04-27 19:24:19.000000000 +0200
16731 @@ -658,4 +658,17 @@
16732 cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
16733 }
16734
16735 +extern inline void fill_icache_line(unsigned long addr)
16736 +{
16737 + __asm__ __volatile__(
16738 + ".set noreorder\n\t"
16739 + ".set mips3\n\t"
16740 + "cache %1, (%0)\n\t"
16741 + ".set mips0\n\t"
16742 + ".set reorder"
16743 + :
16744 + : "r" (addr),
16745 + "i" (Fill));
16746 +}
16747 +
16748 #endif /* __ASM_R4KCACHE_H */
16749 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
16750 --- linux.old/include/asm-mips/serial.h 2006-04-27 18:04:38.000000000 +0200
16751 +++ linux.dev/include/asm-mips/serial.h 2006-04-27 19:24:19.000000000 +0200
16752 @@ -223,6 +223,13 @@
16753 #define TXX927_SERIAL_PORT_DEFNS
16754 #endif
16755
16756 +#ifdef CONFIG_BCM947XX
16757 +/* reserve 4 ports to be configured at runtime */
16758 +#define BCM947XX_SERIAL_PORT_DEFNS { 0, }, { 0, }, { 0, }, { 0, },
16759 +#else
16760 +#define BCM947XX_SERIAL_PORT_DEFNS
16761 +#endif
16762 +
16763 #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
16764 #define STD_SERIAL_PORT_DEFNS \
16765 /* UART CLK PORT IRQ FLAGS */ \
16766 @@ -470,6 +477,7 @@
16767 #define SERIAL_PORT_DFNS \
16768 ATLAS_SERIAL_PORT_DEFNS \
16769 AU1000_SERIAL_PORT_DEFNS \
16770 + BCM947XX_SERIAL_PORT_DEFNS \
16771 COBALT_SERIAL_PORT_DEFNS \
16772 DDB5477_SERIAL_PORT_DEFNS \
16773 EV96100_SERIAL_PORT_DEFNS \
16774 diff -urN linux.old/init/do_mounts.c linux.dev/init/do_mounts.c
16775 --- linux.old/init/do_mounts.c 2006-04-27 18:04:38.000000000 +0200
16776 +++ linux.dev/init/do_mounts.c 2006-04-27 19:24:19.000000000 +0200
16777 @@ -254,7 +254,13 @@
16778 { "ftlb", 0x2c08 },
16779 { "ftlc", 0x2c10 },
16780 { "ftld", 0x2c18 },
16781 +#if defined(CONFIG_MTD_BLOCK) || defined(CONFIG_MTD_BLOCK_RO)
16782 { "mtdblock", 0x1f00 },
16783 + { "mtdblock0",0x1f00 },
16784 + { "mtdblock1",0x1f01 },
16785 + { "mtdblock2",0x1f02 },
16786 + { "mtdblock3",0x1f03 },
16787 +#endif
16788 { "nb", 0x2b00 },
16789 { NULL, 0 }
16790 };
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