1 /* Smedia Glamo 336x/337x driver
3 * (C) 2007 by Openmoko, Inc.
4 * Author: Harald Welte <laforge@openmoko.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/string.h>
28 #include <linux/tty.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/irq.h>
34 #include <linux/interrupt.h>
35 #include <linux/workqueue.h>
36 #include <linux/wait.h>
37 #include <linux/platform_device.h>
38 #include <linux/kernel_stat.h>
39 #include <linux/spinlock.h>
40 #include <linux/glamofb.h>
41 #include <linux/mmc/mmc.h>
42 #include <linux/mmc/host.h>
45 #include <asm/uaccess.h>
46 #include <asm/div64.h>
52 #include "glamo-regs.h"
53 #include "glamo-core.h"
55 #define GLAMO_MEM_REFRESH_COUNT 0x100
58 * Glamo internal settings
60 * We run the memory interface from the faster PLLB on 2.6.28 kernels and
61 * above. Couple of GTA02 users report trouble with memory bus when they
62 * upgraded from 2.6.24. So this parameter allows reversion to 2.6.24
63 * scheme if their Glamo chip needs it.
65 * you can override the faster default on kernel commandline using
67 * glamo3362.slow_memory=1
72 static int slow_memory
= 0;
73 module_param(slow_memory
, int, 0644);
81 struct reg_range reg_range
[] = {
82 { 0x0000, 0x76, "General", 1 },
83 { 0x0200, 0x16, "Host Bus", 1 },
84 { 0x0300, 0x38, "Memory", 1 },
85 /* { 0x0400, 0x100, "Sensor", 0 }, */
86 /* { 0x0500, 0x300, "ISP", 0 }, */
87 /* { 0x0800, 0x400, "JPEG", 0 }, */
88 /* { 0x0c00, 0xcc, "MPEG", 0 }, */
89 { 0x1100, 0xb2, "LCD 1", 1 },
90 { 0x1200, 0x64, "LCD 2", 1 },
91 { 0x1400, 0x40, "MMC", 1 },
92 /* { 0x1500, 0x080, "MPU 0", 0 },
93 { 0x1580, 0x080, "MPU 1", 0 },
94 { 0x1600, 0x080, "Cmd Queue", 0 },
95 { 0x1680, 0x080, "RISC CPU", 0 },
96 { 0x1700, 0x400, "2D Unit", 0 },
97 { 0x1b00, 0x900, "3D Unit", 0 }, */
100 static struct glamo_core
*glamo_handle
;
102 static inline void __reg_write(struct glamo_core
*glamo
,
103 u_int16_t reg
, u_int16_t val
)
105 writew(val
, glamo
->base
+ reg
);
108 static inline u_int16_t
__reg_read(struct glamo_core
*glamo
,
111 return readw(glamo
->base
+ reg
);
114 static void __reg_set_bit_mask(struct glamo_core
*glamo
,
115 u_int16_t reg
, u_int16_t mask
,
122 tmp
= __reg_read(glamo
, reg
);
125 __reg_write(glamo
, reg
, tmp
);
128 static void reg_set_bit_mask(struct glamo_core
*glamo
,
129 u_int16_t reg
, u_int16_t mask
,
132 spin_lock(&glamo
->lock
);
133 __reg_set_bit_mask(glamo
, reg
, mask
, val
);
134 spin_unlock(&glamo
->lock
);
137 static inline void __reg_set_bit(struct glamo_core
*glamo
,
138 u_int16_t reg
, u_int16_t bit
)
140 __reg_set_bit_mask(glamo
, reg
, bit
, 0xffff);
143 static inline void __reg_clear_bit(struct glamo_core
*glamo
,
144 u_int16_t reg
, u_int16_t bit
)
146 __reg_set_bit_mask(glamo
, reg
, bit
, 0);
149 /***********************************************************************
150 * resources of sibling devices
151 ***********************************************************************/
154 static struct resource glamo_core_resources
[] = {
156 .start
= GLAMO_REGOFS_GENERIC
,
157 .end
= GLAMO_REGOFS_GENERIC
+ 0x400,
158 .flags
= IORESOURCE_MEM
,
162 .flags
= IORESOURCE_IRQ
,
166 static struct platform_device glamo_core_dev
= {
167 .name
= "glamo-core",
168 .resource
= &glamo_core_resources
,
169 .num_resources
= ARRAY_SIZE(glamo_core_resources
),
173 static struct resource glamo_jpeg_resources
[] = {
175 .start
= GLAMO_REGOFS_JPEG
,
176 .end
= GLAMO_REGOFS_MPEG
- 1,
177 .flags
= IORESOURCE_MEM
,
179 .start
= IRQ_GLAMO_JPEG
,
180 .end
= IRQ_GLAMO_JPEG
,
181 .flags
= IORESOURCE_IRQ
,
185 static struct platform_device glamo_jpeg_dev
= {
186 .name
= "glamo-jpeg",
187 .resource
= glamo_jpeg_resources
,
188 .num_resources
= ARRAY_SIZE(glamo_jpeg_resources
),
191 static struct resource glamo_mpeg_resources
[] = {
193 .start
= GLAMO_REGOFS_MPEG
,
194 .end
= GLAMO_REGOFS_LCD
- 1,
195 .flags
= IORESOURCE_MEM
,
197 .start
= IRQ_GLAMO_MPEG
,
198 .end
= IRQ_GLAMO_MPEG
,
199 .flags
= IORESOURCE_IRQ
,
203 static struct platform_device glamo_mpeg_dev
= {
204 .name
= "glamo-mpeg",
205 .resource
= glamo_mpeg_resources
,
206 .num_resources
= ARRAY_SIZE(glamo_mpeg_resources
),
209 static struct resource glamo_2d_resources
[] = {
211 .start
= GLAMO_REGOFS_2D
,
212 .end
= GLAMO_REGOFS_3D
- 1,
213 .flags
= IORESOURCE_MEM
,
215 .start
= IRQ_GLAMO_2D
,
217 .flags
= IORESOURCE_IRQ
,
221 static struct platform_device glamo_2d_dev
= {
223 .resource
= glamo_2d_resources
,
224 .num_resources
= ARRAY_SIZE(glamo_2d_resources
),
227 static struct resource glamo_3d_resources
[] = {
229 .start
= GLAMO_REGOFS_3D
,
230 .end
= GLAMO_REGOFS_END
- 1,
231 .flags
= IORESOURCE_MEM
,
235 static struct platform_device glamo_3d_dev
= {
237 .resource
= glamo_3d_resources
,
238 .num_resources
= ARRAY_SIZE(glamo_3d_resources
),
241 static struct platform_device glamo_spigpio_dev
= {
242 .name
= "glamo-spi-gpio",
245 static struct resource glamo_fb_resources
[] = {
246 /* FIXME: those need to be incremented by parent base */
248 .name
= "glamo-fb-regs",
249 .start
= GLAMO_REGOFS_LCD
,
250 .end
= GLAMO_REGOFS_MMC
- 1,
251 .flags
= IORESOURCE_MEM
,
253 .name
= "glamo-fb-mem",
254 .start
= GLAMO_OFFSET_FB
,
255 .end
= GLAMO_OFFSET_FB
+ GLAMO_FB_SIZE
- 1,
256 .flags
= IORESOURCE_MEM
,
260 static struct platform_device glamo_fb_dev
= {
262 .resource
= glamo_fb_resources
,
263 .num_resources
= ARRAY_SIZE(glamo_fb_resources
),
266 static struct resource glamo_mmc_resources
[] = {
268 /* FIXME: those need to be incremented by parent base */
269 .start
= GLAMO_REGOFS_MMC
,
270 .end
= GLAMO_REGOFS_MPROC0
- 1,
271 .flags
= IORESOURCE_MEM
273 .start
= IRQ_GLAMO_MMC
,
274 .end
= IRQ_GLAMO_MMC
,
275 .flags
= IORESOURCE_IRQ
,
276 }, { /* our data buffer for MMC transfers */
277 .start
= GLAMO_OFFSET_FB
+ GLAMO_FB_SIZE
,
278 .end
= GLAMO_OFFSET_FB
+ GLAMO_FB_SIZE
+
279 GLAMO_MMC_BUFFER_SIZE
- 1,
280 .flags
= IORESOURCE_MEM
284 static struct glamo_mci_pdata glamo_mci_def_pdata
= {
286 .glamo_can_set_mci_power
= NULL
, /* filled in from MFD platform data */
287 /* .ocr_avail = MMC_VDD_20_21 |
299 .glamo_irq_is_wired
= NULL
, /* filled in from MFD platform data */
300 .mci_suspending
= NULL
, /* filled in from MFD platform data */
301 .mci_all_dependencies_resumed
= NULL
, /* filled in from MFD platform data */
304 static void mangle_mem_resources(struct resource
*res
, int num_res
,
305 struct resource
*parent
)
309 for (i
= 0; i
< num_res
; i
++) {
310 if (res
[i
].flags
!= IORESOURCE_MEM
)
312 res
[i
].start
+= parent
->start
;
313 res
[i
].end
+= parent
->start
;
314 res
[i
].parent
= parent
;
318 /***********************************************************************
320 ***********************************************************************/
321 #define irq2glamo(x) (x - IRQ_GLAMO(0))
323 static void glamo_ack_irq(unsigned int irq
)
325 /* clear interrupt source */
326 __reg_write(glamo_handle
, GLAMO_REG_IRQ_CLEAR
,
327 1 << irq2glamo(irq
));
330 static void glamo_mask_irq(unsigned int irq
)
334 /* clear bit in enable register */
335 tmp
= __reg_read(glamo_handle
, GLAMO_REG_IRQ_ENABLE
);
336 tmp
&= ~(1 << irq2glamo(irq
));
337 __reg_write(glamo_handle
, GLAMO_REG_IRQ_ENABLE
, tmp
);
340 static void glamo_unmask_irq(unsigned int irq
)
344 /* set bit in enable register */
345 tmp
= __reg_read(glamo_handle
, GLAMO_REG_IRQ_ENABLE
);
346 tmp
|= (1 << irq2glamo(irq
));
347 __reg_write(glamo_handle
, GLAMO_REG_IRQ_ENABLE
, tmp
);
350 static struct irq_chip glamo_irq_chip
= {
351 .ack
= glamo_ack_irq
,
352 .mask
= glamo_mask_irq
,
353 .unmask
= glamo_unmask_irq
,
356 static void glamo_irq_demux_handler(unsigned int irq
, struct irq_desc
*desc
)
358 desc
->status
&= ~(IRQ_REPLAY
| IRQ_WAITING
);
360 if (unlikely(desc
->status
& IRQ_INPROGRESS
)) {
361 desc
->status
|= (IRQ_PENDING
| IRQ_MASKED
);
362 desc
->chip
->mask(irq
);
363 desc
->chip
->ack(irq
);
366 kstat_incr_irqs_this_cpu(irq
, desc
);
368 desc
->chip
->ack(irq
);
369 desc
->status
|= IRQ_INPROGRESS
;
375 if (unlikely((desc
->status
&
376 (IRQ_PENDING
| IRQ_MASKED
| IRQ_DISABLED
)) ==
377 (IRQ_PENDING
| IRQ_MASKED
))) {
378 /* dealing with pending IRQ, unmasking */
379 desc
->chip
->unmask(irq
);
380 desc
->status
&= ~IRQ_MASKED
;
383 desc
->status
&= ~IRQ_PENDING
;
385 /* read IRQ status register */
386 irqstatus
= __reg_read(glamo_handle
, GLAMO_REG_IRQ_STATUS
);
387 for (i
= 0; i
< 9; i
++)
388 if (irqstatus
& (1 << i
))
389 desc_handle_irq(IRQ_GLAMO(i
),
390 irq_desc
+IRQ_GLAMO(i
));
392 } while ((desc
->status
& (IRQ_PENDING
| IRQ_DISABLED
)) == IRQ_PENDING
);
394 desc
->status
&= ~IRQ_INPROGRESS
;
398 static ssize_t
regs_write(struct device
*dev
, struct device_attribute
*attr
,
399 const char *buf
, size_t count
)
401 unsigned long reg
= simple_strtoul(buf
, NULL
, 10);
402 struct glamo_core
*glamo
= dev_get_drvdata(dev
);
404 while (*buf
&& (*buf
!= ' '))
408 while (*buf
&& (*buf
== ' '))
413 printk(KERN_INFO
"reg 0x%02lX <-- 0x%04lX\n",
414 reg
, simple_strtoul(buf
, NULL
, 10));
416 __reg_write(glamo
, reg
, simple_strtoul(buf
, NULL
, 10));
421 static ssize_t
regs_read(struct device
*dev
, struct device_attribute
*attr
,
424 struct glamo_core
*glamo
= dev_get_drvdata(dev
);
428 spin_lock(&glamo
->lock
);
430 for (r
= 0; r
< ARRAY_SIZE(reg_range
); r
++) {
431 if (!reg_range
[r
].dump
)
434 end
+= sprintf(end
, "\n%s\n", reg_range
[r
].name
);
435 for (n
= reg_range
[r
].start
;
436 n
< reg_range
[r
].start
+ reg_range
[r
].count
; n
+= 2) {
437 if (((n1
++) & 7) == 0)
438 end
+= sprintf(end
, "\n%04X: ", n
);
439 end
+= sprintf(end
, "%04x ", __reg_read(glamo
, n
));
441 end
+= sprintf(end
, "\n");
447 spin_unlock(&glamo
->lock
);
452 static DEVICE_ATTR(regs
, 0644, regs_read
, regs_write
);
453 static struct attribute
*glamo_sysfs_entries
[] = {
457 static struct attribute_group glamo_attr_group
= {
459 .attrs
= glamo_sysfs_entries
,
464 /***********************************************************************
466 ***********************************************************************/
468 int __glamo_engine_enable(struct glamo_core
*glamo
, enum glamo_engine engine
)
471 case GLAMO_ENGINE_LCD
:
472 __reg_set_bit_mask(glamo
, GLAMO_REG_HOSTBUS(2),
473 GLAMO_HOSTBUS2_MMIO_EN_LCD
,
474 GLAMO_HOSTBUS2_MMIO_EN_LCD
);
475 __reg_write(glamo
, GLAMO_REG_CLOCK_LCD
,
476 GLAMO_CLOCK_LCD_EN_M5CLK
|
477 GLAMO_CLOCK_LCD_EN_DHCLK
|
478 GLAMO_CLOCK_LCD_EN_DMCLK
|
479 GLAMO_CLOCK_LCD_EN_DCLK
|
480 GLAMO_CLOCK_LCD_DG_M5CLK
|
481 GLAMO_CLOCK_LCD_DG_DMCLK
);
482 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
483 GLAMO_CLOCK_GEN51_EN_DIV_DHCLK
|
484 GLAMO_CLOCK_GEN51_EN_DIV_DMCLK
|
485 GLAMO_CLOCK_GEN51_EN_DIV_DCLK
, 0xffff);
487 case GLAMO_ENGINE_MMC
:
488 __reg_set_bit_mask(glamo
, GLAMO_REG_HOSTBUS(2),
489 GLAMO_HOSTBUS2_MMIO_EN_MMC
,
490 GLAMO_HOSTBUS2_MMIO_EN_MMC
);
491 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_MMC
,
492 GLAMO_CLOCK_MMC_EN_M9CLK
|
493 GLAMO_CLOCK_MMC_EN_TCLK
|
494 GLAMO_CLOCK_MMC_DG_M9CLK
|
495 GLAMO_CLOCK_MMC_DG_TCLK
, 0xffff);
496 /* enable the TCLK divider clk input */
497 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
498 GLAMO_CLOCK_GEN51_EN_DIV_TCLK
,
499 GLAMO_CLOCK_GEN51_EN_DIV_TCLK
);
501 case GLAMO_ENGINE_2D
:
502 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_2D
,
503 GLAMO_CLOCK_2D_EN_M7CLK
|
504 GLAMO_CLOCK_2D_EN_GCLK
|
505 GLAMO_CLOCK_2D_DG_M7CLK
|
506 GLAMO_CLOCK_2D_DG_GCLK
, 0xffff);
507 __reg_set_bit_mask(glamo
, GLAMO_REG_HOSTBUS(2),
508 GLAMO_HOSTBUS2_MMIO_EN_2D
,
509 GLAMO_HOSTBUS2_MMIO_EN_2D
);
510 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
511 GLAMO_CLOCK_GEN51_EN_DIV_GCLK
,
514 case GLAMO_ENGINE_CMDQ
:
515 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_2D
,
516 GLAMO_CLOCK_2D_EN_M6CLK
, 0xffff);
517 __reg_set_bit_mask(glamo
, GLAMO_REG_HOSTBUS(2),
518 GLAMO_HOSTBUS2_MMIO_EN_CQ
,
519 GLAMO_HOSTBUS2_MMIO_EN_CQ
);
520 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
521 GLAMO_CLOCK_GEN51_EN_DIV_MCLK
,
524 /* FIXME: Implementation */
529 glamo
->engine_enabled_bitfield
|= 1 << engine
;
534 int glamo_engine_enable(struct glamo_core
*glamo
, enum glamo_engine engine
)
538 spin_lock(&glamo
->lock
);
540 ret
= __glamo_engine_enable(glamo
, engine
);
542 spin_unlock(&glamo
->lock
);
546 EXPORT_SYMBOL_GPL(glamo_engine_enable
);
548 int __glamo_engine_disable(struct glamo_core
*glamo
, enum glamo_engine engine
)
551 case GLAMO_ENGINE_LCD
:
552 /* remove pixel clock to LCM */
553 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_LCD
,
554 GLAMO_CLOCK_LCD_EN_DCLK
, 0);
555 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_LCD
,
556 GLAMO_CLOCK_LCD_EN_DHCLK
|
557 GLAMO_CLOCK_LCD_EN_DMCLK
, 0);
558 /* kill memory clock */
559 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_LCD
,
560 GLAMO_CLOCK_LCD_EN_M5CLK
, 0);
561 /* stop dividing the clocks */
562 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
563 GLAMO_CLOCK_GEN51_EN_DIV_DHCLK
|
564 GLAMO_CLOCK_GEN51_EN_DIV_DMCLK
|
565 GLAMO_CLOCK_GEN51_EN_DIV_DCLK
, 0);
568 case GLAMO_ENGINE_MMC
:
569 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_MMC
,
570 GLAMO_CLOCK_MMC_EN_M9CLK
|
571 GLAMO_CLOCK_MMC_EN_TCLK
|
572 GLAMO_CLOCK_MMC_DG_M9CLK
|
573 GLAMO_CLOCK_MMC_DG_TCLK
, 0);
574 /* disable the TCLK divider clk input */
575 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
576 GLAMO_CLOCK_GEN51_EN_DIV_TCLK
, 0);
578 case GLAMO_ENGINE_CMDQ
:
579 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_2D
,
580 GLAMO_CLOCK_2D_EN_M6CLK
,
582 __reg_set_bit_mask(glamo
, GLAMO_REG_HOSTBUS(2),
583 GLAMO_HOSTBUS2_MMIO_EN_CQ
,
584 GLAMO_HOSTBUS2_MMIO_EN_CQ
);
585 /* __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
586 GLAMO_CLOCK_GEN51_EN_DIV_MCLK,
589 case GLAMO_ENGINE_2D
:
590 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_2D
,
591 GLAMO_CLOCK_2D_EN_M7CLK
|
592 GLAMO_CLOCK_2D_EN_GCLK
|
593 GLAMO_CLOCK_2D_DG_M7CLK
|
594 GLAMO_CLOCK_2D_DG_GCLK
,
596 __reg_set_bit_mask(glamo
, GLAMO_REG_HOSTBUS(2),
597 GLAMO_HOSTBUS2_MMIO_EN_2D
,
598 GLAMO_HOSTBUS2_MMIO_EN_2D
);
599 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
600 GLAMO_CLOCK_GEN51_EN_DIV_GCLK
,
607 glamo
->engine_enabled_bitfield
&= ~(1 << engine
);
611 int glamo_engine_disable(struct glamo_core
*glamo
, enum glamo_engine engine
)
615 spin_lock(&glamo
->lock
);
617 ret
= __glamo_engine_disable(glamo
, engine
);
619 spin_unlock(&glamo
->lock
);
623 EXPORT_SYMBOL_GPL(glamo_engine_disable
);
625 static const u_int16_t engine_clock_regs
[__NUM_GLAMO_ENGINES
] = {
626 [GLAMO_ENGINE_LCD
] = GLAMO_REG_CLOCK_LCD
,
627 [GLAMO_ENGINE_MMC
] = GLAMO_REG_CLOCK_MMC
,
628 [GLAMO_ENGINE_ISP
] = GLAMO_REG_CLOCK_ISP
,
629 [GLAMO_ENGINE_JPEG
] = GLAMO_REG_CLOCK_JPEG
,
630 [GLAMO_ENGINE_3D
] = GLAMO_REG_CLOCK_3D
,
631 [GLAMO_ENGINE_2D
] = GLAMO_REG_CLOCK_2D
,
632 [GLAMO_ENGINE_MPEG_ENC
] = GLAMO_REG_CLOCK_MPEG
,
633 [GLAMO_ENGINE_MPEG_DEC
] = GLAMO_REG_CLOCK_MPEG
,
636 void glamo_engine_clkreg_set(struct glamo_core
*glamo
,
637 enum glamo_engine engine
,
638 u_int16_t mask
, u_int16_t val
)
640 reg_set_bit_mask(glamo
, engine_clock_regs
[engine
], mask
, val
);
642 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_set
);
644 u_int16_t
glamo_engine_clkreg_get(struct glamo_core
*glamo
,
645 enum glamo_engine engine
)
649 spin_lock(&glamo
->lock
);
650 val
= __reg_read(glamo
, engine_clock_regs
[engine
]);
651 spin_unlock(&glamo
->lock
);
655 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_get
);
657 struct glamo_script reset_regs
[] = {
658 [GLAMO_ENGINE_LCD
] = {
659 GLAMO_REG_CLOCK_LCD
, GLAMO_CLOCK_LCD_RESET
662 [GLAMO_ENGINE_HOST
] = {
663 GLAMO_REG_CLOCK_HOST
, GLAMO_CLOCK_HOST_RESET
665 [GLAMO_ENGINE_MEM
] = {
666 GLAMO_REG_CLOCK_MEM
, GLAMO_CLOCK_MEM_RESET
669 [GLAMO_ENGINE_MMC
] = {
670 GLAMO_REG_CLOCK_MMC
, GLAMO_CLOCK_MMC_RESET
672 [GLAMO_ENGINE_CMDQ
] = {
673 GLAMO_REG_CLOCK_2D
, GLAMO_CLOCK_2D_CQ_RESET
675 [GLAMO_ENGINE_2D
] = {
676 GLAMO_REG_CLOCK_2D
, GLAMO_CLOCK_2D_RESET
678 [GLAMO_ENGINE_JPEG
] = {
679 GLAMO_REG_CLOCK_JPEG
, GLAMO_CLOCK_JPEG_RESET
683 void glamo_engine_reset(struct glamo_core
*glamo
, enum glamo_engine engine
)
685 struct glamo_script
*rst
;
687 if (engine
>= ARRAY_SIZE(reset_regs
)) {
688 dev_warn(&glamo
->pdev
->dev
, "unknown engine %u ", engine
);
692 rst
= &reset_regs
[engine
];
694 spin_lock(&glamo
->lock
);
695 __reg_set_bit(glamo
, rst
->reg
, rst
->val
);
696 __reg_clear_bit(glamo
, rst
->reg
, rst
->val
);
697 spin_unlock(&glamo
->lock
);
699 EXPORT_SYMBOL_GPL(glamo_engine_reset
);
701 void glamo_lcm_reset(int level
)
706 glamo_gpio_setpin(glamo_handle
, GLAMO_GPIO4
, level
);
707 glamo_gpio_cfgpin(glamo_handle
, GLAMO_GPIO4_OUTPUT
);
710 EXPORT_SYMBOL_GPL(glamo_lcm_reset
);
717 static int glamo_pll_rate(struct glamo_core
*glamo
,
721 unsigned int div
= 512;
722 /* FIXME: move osci into platform_data */
723 unsigned int osci
= 32768;
730 reg
= __reg_read(glamo
, GLAMO_REG_PLL_GEN1
);
733 reg
= __reg_read(glamo
, GLAMO_REG_PLL_GEN3
);
738 return (osci
/div
)*reg
;
741 int glamo_engine_reclock(struct glamo_core
*glamo
,
742 enum glamo_engine engine
,
746 u_int16_t reg
, mask
, val
= 0;
752 case GLAMO_ENGINE_LCD
:
754 reg
= GLAMO_REG_CLOCK_GEN7
;
758 dev_warn(&glamo
->pdev
->dev
,
759 "reclock of engine 0x%x not supported\n", engine
);
764 pll
= glamo_pll_rate(glamo
, pll
);
765 khz
= 1000000000UL / ps
;
768 val
= (pll
/ khz
) / 1000;
770 dev_dbg(&glamo
->pdev
->dev
,
771 "PLL %d, kHZ %d, div %d\n", pll
, khz
, val
);
775 reg_set_bit_mask(glamo
, reg
, mask
, val
);
776 mdelay(5); /* wait some time to stabilize */
783 EXPORT_SYMBOL_GPL(glamo_engine_reclock
);
785 /***********************************************************************
787 ***********************************************************************/
789 int glamo_run_script(struct glamo_core
*glamo
, struct glamo_script
*script
,
790 int len
, int may_sleep
)
794 for (i
= 0; i
< len
; i
++) {
795 struct glamo_script
*line
= &script
[i
];
804 mdelay(line
->val
* 4);
807 /* spin until PLLs lock */
808 while ((__reg_read(glamo
, GLAMO_REG_PLL_GEN5
) & 3) != 3)
813 * couple of people reported artefacts with 2.6.28 changes, this
814 * allows reversion to 2.6.24 settings
818 switch (slow_memory
) {
819 /* choice 1 is the most conservative */
820 case 1: /* 3 waits on Async BB R & W, Use PLL 1 for mem bus */
821 __reg_write(glamo
, script
[i
].reg
, 0xef0);
823 case 2: /* 2 waits on Async BB R & W, Use PLL 1 for mem bus */
824 __reg_write(glamo
, script
[i
].reg
, 0xea0);
826 case 3: /* 1 waits on Async BB R & W, Use PLL 1 for mem bus */
827 __reg_write(glamo
, script
[i
].reg
, 0xe50);
829 case 4: /* 0 waits on Async BB R & W, Use PLL 1 for mem bus */
830 __reg_write(glamo
, script
[i
].reg
, 0xe00);
833 /* using PLL2 for memory bus increases CPU bandwidth significantly */
834 case 5: /* 3 waits on Async BB R & W, Use PLL 2 for mem bus */
835 __reg_write(glamo
, script
[i
].reg
, 0xef3);
837 case 6: /* 2 waits on Async BB R & W, Use PLL 2 for mem bus */
838 __reg_write(glamo
, script
[i
].reg
, 0xea3);
840 case 7: /* 1 waits on Async BB R & W, Use PLL 2 for mem bus */
841 __reg_write(glamo
, script
[i
].reg
, 0xe53);
843 /* default of 0 or >7 is fastest */
844 default: /* 0 waits on Async BB R & W, Use PLL 2 for mem bus */
845 __reg_write(glamo
, script
[i
].reg
, 0xe03);
851 __reg_write(glamo
, script
[i
].reg
, script
[i
].val
);
858 EXPORT_SYMBOL(glamo_run_script
);
860 static struct glamo_script glamo_init_script
[] = {
861 { GLAMO_REG_CLOCK_HOST
, 0x1000 },
863 { GLAMO_REG_CLOCK_MEMORY
, 0x1000 },
864 { GLAMO_REG_CLOCK_MEMORY
, 0x2000 },
865 { GLAMO_REG_CLOCK_LCD
, 0x1000 },
866 { GLAMO_REG_CLOCK_MMC
, 0x1000 },
867 { GLAMO_REG_CLOCK_ISP
, 0x1000 },
868 { GLAMO_REG_CLOCK_ISP
, 0x3000 },
869 { GLAMO_REG_CLOCK_JPEG
, 0x1000 },
870 { GLAMO_REG_CLOCK_3D
, 0x1000 },
871 { GLAMO_REG_CLOCK_3D
, 0x3000 },
872 { GLAMO_REG_CLOCK_2D
, 0x1000 },
873 { GLAMO_REG_CLOCK_2D
, 0x3000 },
874 { GLAMO_REG_CLOCK_RISC1
, 0x1000 },
875 { GLAMO_REG_CLOCK_MPEG
, 0x3000 },
876 { GLAMO_REG_CLOCK_MPEG
, 0x3000 },
877 { GLAMO_REG_CLOCK_MPROC
, 0x1000 /*0x100f*/ },
879 { GLAMO_REG_CLOCK_HOST
, 0x0000 },
880 { GLAMO_REG_CLOCK_MEMORY
, 0x0000 },
881 { GLAMO_REG_CLOCK_LCD
, 0x0000 },
882 { GLAMO_REG_CLOCK_MMC
, 0x0000 },
884 /* unused engines must be left in reset to stop MMC block read "blackouts" */
885 { GLAMO_REG_CLOCK_ISP
, 0x0000 },
886 { GLAMO_REG_CLOCK_ISP
, 0x0000 },
887 { GLAMO_REG_CLOCK_JPEG
, 0x0000 },
888 { GLAMO_REG_CLOCK_3D
, 0x0000 },
889 { GLAMO_REG_CLOCK_3D
, 0x0000 },
890 { GLAMO_REG_CLOCK_2D
, 0x0000 },
891 { GLAMO_REG_CLOCK_2D
, 0x0000 },
892 { GLAMO_REG_CLOCK_RISC1
, 0x0000 },
893 { GLAMO_REG_CLOCK_MPEG
, 0x0000 },
894 { GLAMO_REG_CLOCK_MPEG
, 0x0000 },
896 { GLAMO_REG_PLL_GEN1
, 0x05db }, /* 48MHz */
897 { GLAMO_REG_PLL_GEN3
, 0x0aba }, /* 90MHz */
900 * b9 of this register MUST be zero to get any interrupts on INT#
901 * the other set bits enable all the engine interrupt sources
903 { GLAMO_REG_IRQ_ENABLE
, 0x01ff },
904 { GLAMO_REG_CLOCK_GEN6
, 0x2000 },
905 { GLAMO_REG_CLOCK_GEN7
, 0x0101 },
906 { GLAMO_REG_CLOCK_GEN8
, 0x0100 },
907 { GLAMO_REG_CLOCK_HOST
, 0x000d },
909 * b7..b4 = 0 = no wait states on read or write
910 * b0 = 1 select PLL2 for Host interface, b1 = enable it
912 { 0x200, 0x0e03 /* this is replaced by script parser */ },
918 /* S-Media recommended "set tiling mode to 512 mode for memory access
919 * more efficiency when 640x480" */
920 { GLAMO_REG_MEM_TYPE
, 0x0c74 }, /* 8MB, 16 word pg wr+rd */
921 { GLAMO_REG_MEM_GEN
, 0xafaf }, /* 63 grants min + max */
923 { GLAMO_REGOFS_HOSTBUS
+ 2, 0xffff }, /* enable on MMIO*/
925 { GLAMO_REG_MEM_TIMING1
, 0x0108 },
926 { GLAMO_REG_MEM_TIMING2
, 0x0010 }, /* Taa = 3 MCLK */
927 { GLAMO_REG_MEM_TIMING3
, 0x0000 },
928 { GLAMO_REG_MEM_TIMING4
, 0x0000 }, /* CE1# delay fall/rise */
929 { GLAMO_REG_MEM_TIMING5
, 0x0000 }, /* UB# LB# */
930 { GLAMO_REG_MEM_TIMING6
, 0x0000 }, /* OE# */
931 { GLAMO_REG_MEM_TIMING7
, 0x0000 }, /* WE# */
932 { GLAMO_REG_MEM_TIMING8
, 0x1002 }, /* MCLK delay, was 0x1000 */
933 { GLAMO_REG_MEM_TIMING9
, 0x6006 },
934 { GLAMO_REG_MEM_TIMING10
, 0x00ff },
935 { GLAMO_REG_MEM_TIMING11
, 0x0001 },
936 { GLAMO_REG_MEM_POWER1
, 0x0020 },
937 { GLAMO_REG_MEM_POWER2
, 0x0000 },
938 { GLAMO_REG_MEM_DRAM1
, 0x0000 },
940 { GLAMO_REG_MEM_DRAM1
, 0xc100 },
942 { GLAMO_REG_MEM_DRAM1
, 0xe100 },
943 { GLAMO_REG_MEM_DRAM2
, 0x01d6 },
944 { GLAMO_REG_CLOCK_MEMORY
, 0x000b },
945 { GLAMO_REG_GPIO_GEN1
, 0x000f },
946 { GLAMO_REG_GPIO_GEN2
, 0x111e },
947 { GLAMO_REG_GPIO_GEN3
, 0xccc3 },
948 { GLAMO_REG_GPIO_GEN4
, 0x111e },
949 { GLAMO_REG_GPIO_GEN5
, 0x000f },
952 static struct glamo_script glamo_resume_script
[] = {
954 { GLAMO_REG_PLL_GEN1
, 0x05db }, /* 48MHz */
955 { GLAMO_REG_PLL_GEN3
, 0x0aba }, /* 90MHz */
956 { GLAMO_REG_DFT_GEN6
, 1 },
962 * b9 of this register MUST be zero to get any interrupts on INT#
963 * the other set bits enable all the engine interrupt sources
965 { GLAMO_REG_IRQ_ENABLE
, 0x01ff },
966 { GLAMO_REG_CLOCK_HOST
, 0x0018 },
967 { GLAMO_REG_CLOCK_GEN5_1
, 0x18b1 },
969 { GLAMO_REG_MEM_DRAM1
, 0x0000 },
971 { GLAMO_REG_MEM_DRAM1
, 0xc100 },
973 { GLAMO_REG_MEM_DRAM1
, 0xe100 },
974 { GLAMO_REG_MEM_DRAM2
, 0x01d6 },
975 { GLAMO_REG_CLOCK_MEMORY
, 0x000b },
984 static void glamo_power(struct glamo_core
*glamo
,
985 enum glamo_power new_state
)
990 spin_lock_irqsave(&glamo
->lock
, flags
);
992 dev_info(&glamo
->pdev
->dev
, "***** glamo_power -> %d\n", new_state
);
996 static const REG_VALUE_MASK_TYPE reg_powerOn[] =
998 { REG_GEN_DFT6, REG_BIT_ALL, REG_DATA(1u << 0) },
999 { REG_GEN_PLL3, 0u, REG_DATA(1u << 13) },
1000 { REG_GEN_MEM_CLK, REG_BIT_ALL, REG_BIT_EN_MOCACLK },
1001 { REG_MEM_DRAM2, 0u, REG_BIT_EN_DEEP_POWER_DOWN },
1002 { REG_MEM_DRAM1, 0u, REG_BIT_SELF_REFRESH }
1005 static const REG_VALUE_MASK_TYPE reg_powerStandby[] =
1007 { REG_MEM_DRAM1, REG_BIT_ALL, REG_BIT_SELF_REFRESH },
1008 { REG_GEN_MEM_CLK, 0u, REG_BIT_EN_MOCACLK },
1009 { REG_GEN_PLL3, REG_BIT_ALL, REG_DATA(1u << 13) },
1010 { REG_GEN_DFT5, REG_BIT_ALL, REG_DATA(1u << 0) }
1013 static const REG_VALUE_MASK_TYPE reg_powerSuspend[] =
1015 { REG_MEM_DRAM2, REG_BIT_ALL, REG_BIT_EN_DEEP_POWER_DOWN },
1016 { REG_GEN_MEM_CLK, 0u, REG_BIT_EN_MOCACLK },
1017 { REG_GEN_PLL3, REG_BIT_ALL, REG_DATA(1u << 13) },
1018 { REG_GEN_DFT5, REG_BIT_ALL, REG_DATA(1u << 0) }
1022 switch (new_state
) {
1023 case GLAMO_POWER_ON
:
1026 * glamo state on resume is nondeterministic in some
1027 * fundamental way, it has also been observed that the
1028 * Glamo reset pin can get asserted by, eg, touching it with
1029 * a scope probe. So the only answer is to roll with it and
1030 * force an external reset on the Glamo during resume.
1033 (glamo
->pdata
->glamo_external_reset
)(0);
1035 (glamo
->pdata
->glamo_external_reset
)(1);
1038 glamo_run_script(glamo
, glamo_init_script
,
1039 ARRAY_SIZE(glamo_init_script
), 0);
1043 case GLAMO_POWER_SUSPEND
:
1045 /* nuke interrupts */
1046 __reg_write(glamo
, GLAMO_REG_IRQ_ENABLE
, 0x200);
1048 /* stash a copy of which engines were running */
1049 glamo
->engine_enabled_bitfield_suspend
=
1050 glamo
->engine_enabled_bitfield
;
1052 /* take down each engine before we kill mem and pll */
1053 for (n
= 0; n
< __NUM_GLAMO_ENGINES
; n
++)
1054 if (glamo
->engine_enabled_bitfield
& (1 << n
))
1055 __glamo_engine_disable(glamo
, n
);
1057 /* enable self-refresh */
1059 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
,
1060 GLAMO_MEM_DRAM1_EN_DRAM_REFRESH
|
1061 GLAMO_MEM_DRAM1_EN_GATE_CKE
|
1062 GLAMO_MEM_DRAM1_SELF_REFRESH
|
1063 GLAMO_MEM_REFRESH_COUNT
);
1064 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
,
1065 GLAMO_MEM_DRAM1_EN_MODEREG_SET
|
1066 GLAMO_MEM_DRAM1_EN_DRAM_REFRESH
|
1067 GLAMO_MEM_DRAM1_EN_GATE_CKE
|
1068 GLAMO_MEM_DRAM1_SELF_REFRESH
|
1069 GLAMO_MEM_REFRESH_COUNT
);
1071 /* force RAM into deep powerdown */
1073 __reg_write(glamo
, GLAMO_REG_MEM_DRAM2
,
1074 GLAMO_MEM_DRAM2_DEEP_PWRDOWN
|
1075 (7 << 6) | /* tRC */
1076 (1 << 4) | /* tRP */
1077 (1 << 2) | /* tRCD */
1078 2); /* CAS latency */
1080 /* disable clocks to memory */
1081 __reg_write(glamo
, GLAMO_REG_CLOCK_MEMORY
, 0);
1083 /* all dividers from OSCI */
1084 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
, 0x400, 0x400);
1086 /* PLL2 into bypass */
1087 __reg_set_bit_mask(glamo
, GLAMO_REG_PLL_GEN3
, 1 << 12, 1 << 12);
1089 __reg_write(glamo
, 0x200, 0x0e00);
1092 /* kill PLLS 1 then 2 */
1093 __reg_write(glamo
, GLAMO_REG_DFT_GEN5
, 0x0001);
1094 __reg_set_bit_mask(glamo
, GLAMO_REG_PLL_GEN3
, 1 << 13, 1 << 13);
1099 spin_unlock_irqrestore(&glamo
->lock
, flags
);
1103 #define MEMDETECT_RETRY 6
1104 static unsigned int detect_memsize(struct glamo_core
*glamo
)
1108 /*static const u_int16_t pattern[] = {
1109 0x1111, 0x8a8a, 0x2222, 0x7a7a,
1110 0x3333, 0x6a6a, 0x4444, 0x5a5a,
1111 0x5555, 0x4a4a, 0x6666, 0x3a3a,
1112 0x7777, 0x2a2a, 0x8888, 0x1a1a
1115 for (i
= 0; i
< MEMDETECT_RETRY
; i
++) {
1116 switch (glamo
->type
) {
1118 __reg_write(glamo
, GLAMO_REG_MEM_TYPE
, 0x0072);
1119 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
, 0xc100);
1122 switch (glamo
->revision
) {
1123 case GLAMO_CORE_REV_A0
:
1125 __reg_write(glamo
, GLAMO_REG_MEM_TYPE
,
1128 __reg_write(glamo
, GLAMO_REG_MEM_TYPE
,
1131 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
, 0x0000);
1133 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
, 0xc100);
1137 __reg_write(glamo
, GLAMO_REG_MEM_TYPE
,
1140 __reg_write(glamo
, GLAMO_REG_MEM_TYPE
,
1143 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
, 0x0000);
1145 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
, 0xe100);
1156 /* FIXME: finish implementation */
1157 for (j
= 0; j
< 8; j
++) {
1166 /* Find out if we can support this version of the Glamo chip */
1167 static int glamo_supported(struct glamo_core
*glamo
)
1169 u_int16_t dev_id
, rev_id
; /*, memsize; */
1171 dev_id
= __reg_read(glamo
, GLAMO_REG_DEVICE_ID
);
1172 rev_id
= __reg_read(glamo
, GLAMO_REG_REVISION_ID
);
1177 case GLAMO_CORE_REV_A2
:
1179 case GLAMO_CORE_REV_A0
:
1180 case GLAMO_CORE_REV_A1
:
1181 case GLAMO_CORE_REV_A3
:
1182 dev_warn(&glamo
->pdev
->dev
, "untested core revision "
1183 "%04x, your mileage may vary\n", rev_id
);
1186 dev_warn(&glamo
->pdev
->dev
, "unknown glamo revision "
1187 "%04x, your mileage may vary\n", rev_id
);
1188 /* maybe should abort ? */
1194 dev_err(&glamo
->pdev
->dev
, "unsupported Glamo device %04x\n",
1199 dev_dbg(&glamo
->pdev
->dev
, "Detected Glamo core %04x Revision %04x "
1200 "(%uHz CPU / %uHz Memory)\n", dev_id
, rev_id
,
1201 glamo_pll_rate(glamo
, GLAMO_PLL1
),
1202 glamo_pll_rate(glamo
, GLAMO_PLL2
));
1207 static int __init
glamo_probe(struct platform_device
*pdev
)
1210 struct glamo_core
*glamo
;
1211 struct platform_device
*glamo_mmc_dev
;
1215 "This driver supports only one instance\n");
1219 glamo
= kmalloc(GFP_KERNEL
, sizeof(*glamo
));
1223 spin_lock_init(&glamo
->lock
);
1224 glamo_handle
= glamo
;
1226 glamo
->mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1227 glamo
->irq
= platform_get_irq(pdev
, 0);
1228 glamo
->pdata
= pdev
->dev
.platform_data
;
1229 if (!glamo
->mem
|| !glamo
->pdata
) {
1230 dev_err(&pdev
->dev
, "platform device with no MEM/PDATA ?\n");
1235 /* register a number of sibling devices whoise IOMEM resources
1236 * are siblings of pdev's IOMEM resource */
1238 glamo_core_dev
.dev
.parent
= &pdev
.dev
;
1239 mangle_mem_resources(glamo_core_dev
.resources
,
1240 glamo_core_dev
.num_resources
, glamo
->mem
);
1241 glamo_core_dev
.resources
[1].start
= glamo
->irq
;
1242 glamo_core_dev
.resources
[1].end
= glamo
->irq
;
1243 platform_device_register(&glamo_core_dev
);
1245 /* only remap the generic, hostbus and memory controller registers */
1246 glamo
->base
= ioremap(glamo
->mem
->start
, 0x4000 /*GLAMO_REGOFS_VIDCAP*/);
1248 dev_err(&pdev
->dev
, "failed to ioremap() memory region\n");
1252 platform_set_drvdata(pdev
, glamo
);
1254 (glamo
->pdata
->glamo_external_reset
)(0);
1256 (glamo
->pdata
->glamo_external_reset
)(1);
1260 * finally set the mfd interrupts up
1261 * can't do them earlier or sibling probes blow up
1264 for (irq
= IRQ_GLAMO(0); irq
<= IRQ_GLAMO(8); irq
++) {
1265 set_irq_chip(irq
, &glamo_irq_chip
);
1266 set_irq_handler(irq
, handle_level_irq
);
1267 set_irq_flags(irq
, IRQF_VALID
);
1270 if (glamo
->pdata
->glamo_irq_is_wired
&&
1271 !glamo
->pdata
->glamo_irq_is_wired()) {
1272 set_irq_chained_handler(glamo
->irq
, glamo_irq_demux_handler
);
1273 set_irq_type(glamo
->irq
, IRQ_TYPE_EDGE_FALLING
);
1274 dev_info(&pdev
->dev
, "Glamo interrupt registered\n");
1275 glamo
->irq_works
= 1;
1277 dev_err(&pdev
->dev
, "Glamo interrupt not used\n");
1278 glamo
->irq_works
= 0;
1282 /* confirm it isn't insane version */
1283 if (!glamo_supported(glamo
)) {
1284 dev_err(&pdev
->dev
, "This Glamo is not supported\n");
1289 rc
= sysfs_create_group(&pdev
->dev
.kobj
, &glamo_attr_group
);
1291 dev_err(&pdev
->dev
, "cannot create sysfs group\n");
1295 /* init the chip with canned register set */
1297 dev_dbg(&glamo
->pdev
->dev
, "running init script\n");
1298 glamo_run_script(glamo
, glamo_init_script
,
1299 ARRAY_SIZE(glamo_init_script
), 1);
1301 dev_info(&glamo
->pdev
->dev
, "Glamo core PLL1: %uHz, PLL2: %uHz\n",
1302 glamo_pll_rate(glamo
, GLAMO_PLL1
),
1303 glamo_pll_rate(glamo
, GLAMO_PLL2
));
1305 /* bring MCI specific stuff over from our MFD platform data */
1306 glamo_mci_def_pdata
.glamo_can_set_mci_power
=
1307 glamo
->pdata
->glamo_can_set_mci_power
;
1308 glamo_mci_def_pdata
.glamo_mci_use_slow
=
1309 glamo
->pdata
->glamo_mci_use_slow
;
1310 glamo_mci_def_pdata
.glamo_irq_is_wired
=
1311 glamo
->pdata
->glamo_irq_is_wired
;
1313 /* start creating the siblings */
1315 glamo_2d_dev
.dev
.parent
= &pdev
->dev
;
1316 mangle_mem_resources(glamo_2d_dev
.resource
,
1317 glamo_2d_dev
.num_resources
, glamo
->mem
);
1318 platform_device_register(&glamo_2d_dev
);
1320 glamo_3d_dev
.dev
.parent
= &pdev
->dev
;
1321 mangle_mem_resources(glamo_3d_dev
.resource
,
1322 glamo_3d_dev
.num_resources
, glamo
->mem
);
1323 platform_device_register(&glamo_3d_dev
);
1325 glamo_jpeg_dev
.dev
.parent
= &pdev
->dev
;
1326 mangle_mem_resources(glamo_jpeg_dev
.resource
,
1327 glamo_jpeg_dev
.num_resources
, glamo
->mem
);
1328 platform_device_register(&glamo_jpeg_dev
);
1330 glamo_mpeg_dev
.dev
.parent
= &pdev
->dev
;
1331 mangle_mem_resources(glamo_mpeg_dev
.resource
,
1332 glamo_mpeg_dev
.num_resources
, glamo
->mem
);
1333 platform_device_register(&glamo_mpeg_dev
);
1335 glamo
->pdata
->glamo
= glamo
;
1336 glamo_fb_dev
.dev
.parent
= &pdev
->dev
;
1337 glamo_fb_dev
.dev
.platform_data
= glamo
->pdata
;
1338 mangle_mem_resources(glamo_fb_dev
.resource
,
1339 glamo_fb_dev
.num_resources
, glamo
->mem
);
1340 platform_device_register(&glamo_fb_dev
);
1342 glamo
->pdata
->spigpio_info
->glamo
= glamo
;
1343 glamo_spigpio_dev
.dev
.parent
= &pdev
->dev
;
1344 glamo_spigpio_dev
.dev
.platform_data
= glamo
->pdata
->spigpio_info
;
1345 platform_device_register(&glamo_spigpio_dev
);
1347 glamo_mmc_dev
= glamo
->pdata
->mmc_dev
;
1348 glamo_mmc_dev
->name
= "glamo-mci";
1349 glamo_mmc_dev
->dev
.parent
= &pdev
->dev
;
1350 glamo_mmc_dev
->resource
= glamo_mmc_resources
;
1351 glamo_mmc_dev
->num_resources
= ARRAY_SIZE(glamo_mmc_resources
);
1352 glamo_mmc_dev
->dev
.platform_data
= &glamo_mci_def_pdata
;
1354 /* we need it later to give to the engine enable and disable */
1355 glamo_mci_def_pdata
.pglamo
= glamo
;
1356 mangle_mem_resources(glamo_mmc_dev
->resource
,
1357 glamo_mmc_dev
->num_resources
, glamo
->mem
);
1358 platform_device_register(glamo_mmc_dev
);
1360 /* only request the generic, hostbus and memory controller MMIO */
1361 glamo
->mem
= request_mem_region(glamo
->mem
->start
,
1362 GLAMO_REGOFS_VIDCAP
, "glamo-core");
1364 dev_err(&pdev
->dev
, "failed to request memory region\n");
1371 disable_irq(glamo
->irq
);
1372 set_irq_chained_handler(glamo
->irq
, NULL
);
1374 for (irq
= IRQ_GLAMO(0); irq
<= IRQ_GLAMO(8); irq
++) {
1375 set_irq_flags(irq
, 0);
1376 set_irq_chip(irq
, NULL
);
1379 iounmap(glamo
->base
);
1381 platform_set_drvdata(pdev
, NULL
);
1382 glamo_handle
= NULL
;
1388 static int glamo_remove(struct platform_device
*pdev
)
1390 struct glamo_core
*glamo
= platform_get_drvdata(pdev
);
1393 disable_irq(glamo
->irq
);
1394 set_irq_chained_handler(glamo
->irq
, NULL
);
1396 for (irq
= IRQ_GLAMO(0); irq
<= IRQ_GLAMO(8); irq
++) {
1397 set_irq_flags(irq
, 0);
1398 set_irq_chip(irq
, NULL
);
1401 platform_set_drvdata(pdev
, NULL
);
1402 platform_device_unregister(&glamo_fb_dev
);
1403 platform_device_unregister(glamo
->pdata
->mmc_dev
);
1404 iounmap(glamo
->base
);
1405 release_mem_region(glamo
->mem
->start
, GLAMO_REGOFS_VIDCAP
);
1406 glamo_handle
= NULL
;
1414 static int glamo_suspend(struct platform_device
*pdev
, pm_message_t state
)
1416 glamo_handle
->suspending
= 1;
1417 glamo_power(glamo_handle
, GLAMO_POWER_SUSPEND
);
1422 static int glamo_resume(struct platform_device
*pdev
)
1424 glamo_power(glamo_handle
, GLAMO_POWER_ON
);
1425 glamo_handle
->suspending
= 0;
1431 #define glamo_suspend NULL
1432 #define glamo_resume NULL
1435 static struct platform_driver glamo_driver
= {
1436 .probe
= glamo_probe
,
1437 .remove
= glamo_remove
,
1438 .suspend
= glamo_suspend
,
1439 .resume
= glamo_resume
,
1441 .name
= "glamo3362",
1442 .owner
= THIS_MODULE
,
1446 static int __devinit
glamo_init(void)
1448 return platform_driver_register(&glamo_driver
);
1451 static void __exit
glamo_cleanup(void)
1453 platform_driver_unregister(&glamo_driver
);
1456 module_init(glamo_init
);
1457 module_exit(glamo_cleanup
);
1459 MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
1460 MODULE_DESCRIPTION("Smedia Glamo 336x/337x core/resource driver");
1461 MODULE_LICENSE("GPL");