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ar71xx: sync kernel configs
[openwrt.git] / target / linux / atheros / patches-2.6.31 / 110-ar2313_ethernet.patch
1 --- a/drivers/net/Kconfig
2 +++ b/drivers/net/Kconfig
3 @@ -359,6 +359,12 @@ config AX88796_93CX6
4 help
5 Select this if your platform comes with an external 93CX6 eeprom.
6
7 +config AR231X_ETHERNET
8 + tristate "AR231x Ethernet support"
9 + depends on ATHEROS_AR231X
10 + help
11 + Support for the AR231x/531x ethernet controller
12 +
13 config MACE
14 tristate "MACE (Power Mac ethernet) support"
15 depends on PPC_PMAC && PPC32
16 --- a/drivers/net/Makefile
17 +++ b/drivers/net/Makefile
18 @@ -211,6 +211,7 @@ obj-$(CONFIG_EQUALIZER) += eql.o
19 obj-$(CONFIG_KORINA) += korina.o
20 obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o
21 obj-$(CONFIG_MIPS_AU1X00_ENET) += au1000_eth.o
22 +obj-$(CONFIG_AR231X_ETHERNET) += ar231x.o
23 obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o
24 obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o
25 obj-$(CONFIG_DECLANCE) += declance.o
26 --- /dev/null
27 +++ b/drivers/net/ar231x.c
28 @@ -0,0 +1,1263 @@
29 +/*
30 + * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
31 + *
32 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
33 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
34 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
35 + *
36 + * Thanks to Atheros for providing hardware and documentation
37 + * enabling me to write this driver.
38 + *
39 + * This program is free software; you can redistribute it and/or modify
40 + * it under the terms of the GNU General Public License as published by
41 + * the Free Software Foundation; either version 2 of the License, or
42 + * (at your option) any later version.
43 + *
44 + * Additional credits:
45 + * This code is taken from John Taylor's Sibyte driver and then
46 + * modified for the AR2313.
47 + */
48 +
49 +#include <linux/module.h>
50 +#include <linux/version.h>
51 +#include <linux/types.h>
52 +#include <linux/errno.h>
53 +#include <linux/ioport.h>
54 +#include <linux/pci.h>
55 +#include <linux/netdevice.h>
56 +#include <linux/etherdevice.h>
57 +#include <linux/skbuff.h>
58 +#include <linux/init.h>
59 +#include <linux/delay.h>
60 +#include <linux/mm.h>
61 +#include <linux/highmem.h>
62 +#include <linux/sockios.h>
63 +#include <linux/pkt_sched.h>
64 +#include <linux/mii.h>
65 +#include <linux/phy.h>
66 +#include <linux/ethtool.h>
67 +#include <linux/ctype.h>
68 +#include <linux/platform_device.h>
69 +
70 +#include <net/sock.h>
71 +#include <net/ip.h>
72 +
73 +#include <asm/system.h>
74 +#include <asm/io.h>
75 +#include <asm/irq.h>
76 +#include <asm/byteorder.h>
77 +#include <asm/uaccess.h>
78 +#include <asm/bootinfo.h>
79 +
80 +#define AR2313_MTU 1692
81 +#define AR2313_PRIOS 1
82 +#define AR2313_QUEUES (2*AR2313_PRIOS)
83 +#define AR2313_DESCR_ENTRIES 64
84 +
85 +
86 +#ifndef min
87 +#define min(a,b) (((a)<(b))?(a):(b))
88 +#endif
89 +
90 +#ifndef SMP_CACHE_BYTES
91 +#define SMP_CACHE_BYTES L1_CACHE_BYTES
92 +#endif
93 +
94 +#define AR2313_MBOX_SET_BIT 0x8
95 +
96 +#include "ar231x.h"
97 +
98 +/*
99 + * New interrupt handler strategy:
100 + *
101 + * An old interrupt handler worked using the traditional method of
102 + * replacing an skbuff with a new one when a packet arrives. However
103 + * the rx rings do not need to contain a static number of buffer
104 + * descriptors, thus it makes sense to move the memory allocation out
105 + * of the main interrupt handler and do it in a bottom half handler
106 + * and only allocate new buffers when the number of buffers in the
107 + * ring is below a certain threshold. In order to avoid starving the
108 + * NIC under heavy load it is however necessary to force allocation
109 + * when hitting a minimum threshold. The strategy for alloction is as
110 + * follows:
111 + *
112 + * RX_LOW_BUF_THRES - allocate buffers in the bottom half
113 + * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
114 + * the buffers in the interrupt handler
115 + * RX_RING_THRES - maximum number of buffers in the rx ring
116 + *
117 + * One advantagous side effect of this allocation approach is that the
118 + * entire rx processing can be done without holding any spin lock
119 + * since the rx rings and registers are totally independent of the tx
120 + * ring and its registers. This of course includes the kmalloc's of
121 + * new skb's. Thus start_xmit can run in parallel with rx processing
122 + * and the memory allocation on SMP systems.
123 + *
124 + * Note that running the skb reallocation in a bottom half opens up
125 + * another can of races which needs to be handled properly. In
126 + * particular it can happen that the interrupt handler tries to run
127 + * the reallocation while the bottom half is either running on another
128 + * CPU or was interrupted on the same CPU. To get around this the
129 + * driver uses bitops to prevent the reallocation routines from being
130 + * reentered.
131 + *
132 + * TX handling can also be done without holding any spin lock, wheee
133 + * this is fun! since tx_csm is only written to by the interrupt
134 + * handler.
135 + */
136 +
137 +/*
138 + * Threshold values for RX buffer allocation - the low water marks for
139 + * when to start refilling the rings are set to 75% of the ring
140 + * sizes. It seems to make sense to refill the rings entirely from the
141 + * intrrupt handler once it gets below the panic threshold, that way
142 + * we don't risk that the refilling is moved to another CPU when the
143 + * one running the interrupt handler just got the slab code hot in its
144 + * cache.
145 + */
146 +#define RX_RING_SIZE AR2313_DESCR_ENTRIES
147 +#define RX_PANIC_THRES (RX_RING_SIZE/4)
148 +#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
149 +#define CRC_LEN 4
150 +#define RX_OFFSET 2
151 +
152 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
153 +#define VLAN_HDR 4
154 +#else
155 +#define VLAN_HDR 0
156 +#endif
157 +
158 +#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + RX_OFFSET)
159 +
160 +#ifdef MODULE
161 +MODULE_LICENSE("GPL");
162 +MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@openwrt.org>");
163 +MODULE_DESCRIPTION("AR231x Ethernet driver");
164 +#endif
165 +
166 +#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
167 +
168 +// prototypes
169 +static void ar231x_halt(struct net_device *dev);
170 +static void rx_tasklet_func(unsigned long data);
171 +static void rx_tasklet_cleanup(struct net_device *dev);
172 +static void ar231x_multicast_list(struct net_device *dev);
173 +
174 +static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
175 +static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value);
176 +static int ar231x_mdiobus_reset(struct mii_bus *bus);
177 +static int ar231x_mdiobus_probe (struct net_device *dev);
178 +static void ar231x_adjust_link(struct net_device *dev);
179 +
180 +#ifndef ERR
181 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
182 +#endif
183 +
184 +static const struct net_device_ops ar231x_ops = {
185 + .ndo_open = ar231x_open,
186 + .ndo_stop = ar231x_close,
187 + .ndo_start_xmit = ar231x_start_xmit,
188 + .ndo_set_multicast_list = ar231x_multicast_list,
189 + .ndo_do_ioctl = ar231x_ioctl,
190 +};
191 +
192 +int __init ar231x_probe(struct platform_device *pdev)
193 +{
194 + struct net_device *dev;
195 + struct ar231x_private *sp;
196 + struct resource *res;
197 + unsigned long ar_eth_base;
198 + char buf[64];
199 +
200 + dev = alloc_etherdev(sizeof(struct ar231x_private));
201 +
202 + if (dev == NULL) {
203 + printk(KERN_ERR
204 + "ar231x: Unable to allocate net_device structure!\n");
205 + return -ENOMEM;
206 + }
207 +
208 + platform_set_drvdata(pdev, dev);
209 +
210 + sp = netdev_priv(dev);
211 + sp->dev = dev;
212 + sp->cfg = pdev->dev.platform_data;
213 +
214 + sprintf(buf, "eth%d_membase", pdev->id);
215 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
216 + if (!res)
217 + return -ENODEV;
218 +
219 + sp->link = 0;
220 + ar_eth_base = res->start;
221 +
222 + sprintf(buf, "eth%d_irq", pdev->id);
223 + dev->irq = platform_get_irq_byname(pdev, buf);
224 +
225 + spin_lock_init(&sp->lock);
226 +
227 + dev->features |= NETIF_F_HIGHDMA;
228 + dev->netdev_ops = &ar231x_ops;
229 +
230 + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev);
231 + tasklet_disable(&sp->rx_tasklet);
232 +
233 + sp->eth_regs =
234 + ioremap_nocache(virt_to_phys(ar_eth_base), sizeof(*sp->eth_regs));
235 + if (!sp->eth_regs) {
236 + printk("Can't remap eth registers\n");
237 + return (-ENXIO);
238 + }
239 +
240 + /*
241 + * When there's only one MAC, PHY regs are typically on ENET0,
242 + * even though the MAC might be on ENET1.
243 + * Needto remap PHY regs separately in this case
244 + */
245 + if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs))
246 + sp->phy_regs = sp->eth_regs;
247 + else {
248 + sp->phy_regs =
249 + ioremap_nocache(virt_to_phys(sp->cfg->phy_base),
250 + sizeof(*sp->phy_regs));
251 + if (!sp->phy_regs) {
252 + printk("Can't remap phy registers\n");
253 + return (-ENXIO);
254 + }
255 + }
256 +
257 + sp->dma_regs =
258 + ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000),
259 + sizeof(*sp->dma_regs));
260 + dev->base_addr = (unsigned int) sp->dma_regs;
261 + if (!sp->dma_regs) {
262 + printk("Can't remap DMA registers\n");
263 + return (-ENXIO);
264 + }
265 +
266 + sp->int_regs = ioremap_nocache(virt_to_phys(sp->cfg->reset_base), 4);
267 + if (!sp->int_regs) {
268 + printk("Can't remap INTERRUPT registers\n");
269 + return (-ENXIO);
270 + }
271 +
272 + strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
273 + sp->name[sizeof(sp->name) - 1] = '\0';
274 + memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
275 +
276 + if (ar231x_init(dev)) {
277 + /*
278 + * ar231x_init() calls ar231x_init_cleanup() on error.
279 + */
280 + kfree(dev);
281 + return -ENODEV;
282 + }
283 +
284 + if (register_netdev(dev)) {
285 + printk("%s: register_netdev failed\n", __func__);
286 + return -1;
287 + }
288 +
289 + printk("%s: %s: %02x:%02x:%02x:%02x:%02x:%02x, irq %d\n",
290 + dev->name, sp->name,
291 + dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
292 + dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], dev->irq);
293 +
294 + sp->mii_bus = mdiobus_alloc();
295 + if (sp->mii_bus == NULL)
296 + return -1;
297 +
298 + sp->mii_bus->priv = dev;
299 + sp->mii_bus->read = ar231x_mdiobus_read;
300 + sp->mii_bus->write = ar231x_mdiobus_write;
301 + sp->mii_bus->reset = ar231x_mdiobus_reset;
302 + sp->mii_bus->name = "ar231x_eth_mii";
303 + snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
304 + sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL);
305 + *sp->mii_bus->irq = PHY_POLL;
306 +
307 + mdiobus_register(sp->mii_bus);
308 +
309 + if (ar231x_mdiobus_probe(dev) != 0) {
310 + printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
311 + rx_tasklet_cleanup(dev);
312 + ar231x_init_cleanup(dev);
313 + unregister_netdev(dev);
314 + kfree(dev);
315 + return -ENODEV;
316 + }
317 +
318 + /* start link poll timer */
319 + ar231x_setup_timer(dev);
320 +
321 + return 0;
322 +}
323 +
324 +
325 +static void ar231x_multicast_list(struct net_device *dev)
326 +{
327 + struct ar231x_private *sp = netdev_priv(dev);
328 + unsigned int filter;
329 +
330 + filter = sp->eth_regs->mac_control;
331 +
332 + if (dev->flags & IFF_PROMISC)
333 + filter |= MAC_CONTROL_PR;
334 + else
335 + filter &= ~MAC_CONTROL_PR;
336 + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
337 + filter |= MAC_CONTROL_PM;
338 + else
339 + filter &= ~MAC_CONTROL_PM;
340 +
341 + sp->eth_regs->mac_control = filter;
342 +}
343 +
344 +static void rx_tasklet_cleanup(struct net_device *dev)
345 +{
346 + struct ar231x_private *sp = netdev_priv(dev);
347 +
348 + /*
349 + * Tasklet may be scheduled. Need to get it removed from the list
350 + * since we're about to free the struct.
351 + */
352 +
353 + sp->unloading = 1;
354 + tasklet_enable(&sp->rx_tasklet);
355 + tasklet_kill(&sp->rx_tasklet);
356 +}
357 +
358 +static int __exit ar231x_remove(struct platform_device *pdev)
359 +{
360 + struct net_device *dev = platform_get_drvdata(pdev);
361 + struct ar231x_private *sp = netdev_priv(dev);
362 + rx_tasklet_cleanup(dev);
363 + ar231x_init_cleanup(dev);
364 + unregister_netdev(dev);
365 + mdiobus_unregister(sp->mii_bus);
366 + mdiobus_free(sp->mii_bus);
367 + kfree(dev);
368 + return 0;
369 +}
370 +
371 +
372 +/*
373 + * Restart the AR2313 ethernet controller.
374 + */
375 +static int ar231x_restart(struct net_device *dev)
376 +{
377 + /* disable interrupts */
378 + disable_irq(dev->irq);
379 +
380 + /* stop mac */
381 + ar231x_halt(dev);
382 +
383 + /* initialize */
384 + ar231x_init(dev);
385 +
386 + /* enable interrupts */
387 + enable_irq(dev->irq);
388 +
389 + return 0;
390 +}
391 +
392 +static struct platform_driver ar231x_driver = {
393 + .driver.name = "ar231x-eth",
394 + .probe = ar231x_probe,
395 + .remove = ar231x_remove,
396 +};
397 +
398 +int __init ar231x_module_init(void)
399 +{
400 + return platform_driver_register(&ar231x_driver);
401 +}
402 +
403 +void __exit ar231x_module_cleanup(void)
404 +{
405 + platform_driver_unregister(&ar231x_driver);
406 +}
407 +
408 +module_init(ar231x_module_init);
409 +module_exit(ar231x_module_cleanup);
410 +
411 +
412 +static void ar231x_free_descriptors(struct net_device *dev)
413 +{
414 + struct ar231x_private *sp = netdev_priv(dev);
415 + if (sp->rx_ring != NULL) {
416 + kfree((void *) KSEG0ADDR(sp->rx_ring));
417 + sp->rx_ring = NULL;
418 + sp->tx_ring = NULL;
419 + }
420 +}
421 +
422 +
423 +static int ar231x_allocate_descriptors(struct net_device *dev)
424 +{
425 + struct ar231x_private *sp = netdev_priv(dev);
426 + int size;
427 + int j;
428 + ar231x_descr_t *space;
429 +
430 + if (sp->rx_ring != NULL) {
431 + printk("%s: already done.\n", __FUNCTION__);
432 + return 0;
433 + }
434 +
435 + size =
436 + (sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES));
437 + space = kmalloc(size, GFP_KERNEL);
438 + if (space == NULL)
439 + return 1;
440 +
441 + /* invalidate caches */
442 + dma_cache_inv((unsigned int) space, size);
443 +
444 + /* now convert pointer to KSEG1 */
445 + space = (ar231x_descr_t *) KSEG1ADDR(space);
446 +
447 + memset((void *) space, 0, size);
448 +
449 + sp->rx_ring = space;
450 + space += AR2313_DESCR_ENTRIES;
451 +
452 + sp->tx_ring = space;
453 + space += AR2313_DESCR_ENTRIES;
454 +
455 + /* Initialize the transmit Descriptors */
456 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
457 + ar231x_descr_t *td = &sp->tx_ring[j];
458 + td->status = 0;
459 + td->devcs = DMA_TX1_CHAINED;
460 + td->addr = 0;
461 + td->descr =
462 + virt_to_phys(&sp->
463 + tx_ring[(j + 1) & (AR2313_DESCR_ENTRIES - 1)]);
464 + }
465 +
466 + return 0;
467 +}
468 +
469 +
470 +/*
471 + * Generic cleanup handling data allocated during init. Used when the
472 + * module is unloaded or if an error occurs during initialization
473 + */
474 +static void ar231x_init_cleanup(struct net_device *dev)
475 +{
476 + struct ar231x_private *sp = netdev_priv(dev);
477 + struct sk_buff *skb;
478 + int j;
479 +
480 + ar231x_free_descriptors(dev);
481 +
482 + if (sp->eth_regs)
483 + iounmap((void *) sp->eth_regs);
484 + if (sp->dma_regs)
485 + iounmap((void *) sp->dma_regs);
486 +
487 + if (sp->rx_skb) {
488 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
489 + skb = sp->rx_skb[j];
490 + if (skb) {
491 + sp->rx_skb[j] = NULL;
492 + dev_kfree_skb(skb);
493 + }
494 + }
495 + kfree(sp->rx_skb);
496 + sp->rx_skb = NULL;
497 + }
498 +
499 + if (sp->tx_skb) {
500 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
501 + skb = sp->tx_skb[j];
502 + if (skb) {
503 + sp->tx_skb[j] = NULL;
504 + dev_kfree_skb(skb);
505 + }
506 + }
507 + kfree(sp->tx_skb);
508 + sp->tx_skb = NULL;
509 + }
510 +}
511 +
512 +static int ar231x_setup_timer(struct net_device *dev)
513 +{
514 + struct ar231x_private *sp = netdev_priv(dev);
515 +
516 + init_timer(&sp->link_timer);
517 +
518 + sp->link_timer.function = ar231x_link_timer_fn;
519 + sp->link_timer.data = (int) dev;
520 + sp->link_timer.expires = jiffies + HZ;
521 +
522 + add_timer(&sp->link_timer);
523 + return 0;
524 +
525 +}
526 +
527 +static void ar231x_link_timer_fn(unsigned long data)
528 +{
529 + struct net_device *dev = (struct net_device *) data;
530 + struct ar231x_private *sp = netdev_priv(dev);
531 +
532 + // see if the link status changed
533 + // This was needed to make sure we set the PHY to the
534 + // autonegotiated value of half or full duplex.
535 + ar231x_check_link(dev);
536 +
537 + // Loop faster when we don't have link.
538 + // This was needed to speed up the AP bootstrap time.
539 + if (sp->link == 0) {
540 + mod_timer(&sp->link_timer, jiffies + HZ / 2);
541 + } else {
542 + mod_timer(&sp->link_timer, jiffies + LINK_TIMER);
543 + }
544 +}
545 +
546 +static void ar231x_check_link(struct net_device *dev)
547 +{
548 + struct ar231x_private *sp = netdev_priv(dev);
549 + u16 phyData;
550 +
551 + phyData = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR);
552 + if (sp->phyData != phyData) {
553 + if (phyData & BMSR_LSTATUS) {
554 + /* link is present, ready link partner ability to deterine
555 + duplexity */
556 + int duplex = 0;
557 + u16 reg;
558 +
559 + sp->link = 1;
560 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMCR);
561 + if (reg & BMCR_ANENABLE) {
562 + /* auto neg enabled */
563 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_LPA);
564 + duplex = (reg & (LPA_100FULL | LPA_10FULL)) ? 1 : 0;
565 + } else {
566 + /* no auto neg, just read duplex config */
567 + duplex = (reg & BMCR_FULLDPLX) ? 1 : 0;
568 + }
569 +
570 + printk(KERN_INFO "%s: Configuring MAC for %s duplex\n",
571 + dev->name, (duplex) ? "full" : "half");
572 +
573 + if (duplex) {
574 + /* full duplex */
575 + sp->eth_regs->mac_control =
576 + ((sp->eth_regs->
577 + mac_control | MAC_CONTROL_F) & ~MAC_CONTROL_DRO);
578 + } else {
579 + /* half duplex */
580 + sp->eth_regs->mac_control =
581 + ((sp->eth_regs->
582 + mac_control | MAC_CONTROL_DRO) & ~MAC_CONTROL_F);
583 + }
584 + } else {
585 + /* no link */
586 + sp->link = 0;
587 + }
588 + sp->phyData = phyData;
589 + }
590 +}
591 +
592 +static int ar231x_reset_reg(struct net_device *dev)
593 +{
594 + struct ar231x_private *sp = netdev_priv(dev);
595 + unsigned int ethsal, ethsah;
596 + unsigned int flags;
597 +
598 + *sp->int_regs |= sp->cfg->reset_mac;
599 + mdelay(10);
600 + *sp->int_regs &= ~sp->cfg->reset_mac;
601 + mdelay(10);
602 + *sp->int_regs |= sp->cfg->reset_phy;
603 + mdelay(10);
604 + *sp->int_regs &= ~sp->cfg->reset_phy;
605 + mdelay(10);
606 +
607 + sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
608 + mdelay(10);
609 + sp->dma_regs->bus_mode =
610 + ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
611 +
612 + /* enable interrupts */
613 + sp->dma_regs->intr_ena = (DMA_STATUS_AIS |
614 + DMA_STATUS_NIS |
615 + DMA_STATUS_RI |
616 + DMA_STATUS_TI | DMA_STATUS_FBE);
617 + sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
618 + sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
619 + sp->dma_regs->control =
620 + (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
621 +
622 + sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
623 + sp->eth_regs->vlan_tag = (0x8100);
624 +
625 + /* Enable Ethernet Interface */
626 + flags = (MAC_CONTROL_TE | /* transmit enable */
627 + MAC_CONTROL_PM | /* pass mcast */
628 + MAC_CONTROL_F | /* full duplex */
629 + MAC_CONTROL_HBD); /* heart beat disabled */
630 +
631 + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
632 + flags |= MAC_CONTROL_PR;
633 + }
634 + sp->eth_regs->mac_control = flags;
635 +
636 + /* Set all Ethernet station address registers to their initial values */
637 + ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
638 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF));
639 +
640 + ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
641 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
642 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
643 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF));
644 +
645 + sp->eth_regs->mac_addr[0] = ethsah;
646 + sp->eth_regs->mac_addr[1] = ethsal;
647 +
648 + mdelay(10);
649 +
650 + return (0);
651 +}
652 +
653 +
654 +static int ar231x_init(struct net_device *dev)
655 +{
656 + struct ar231x_private *sp = netdev_priv(dev);
657 + int ecode = 0;
658 +
659 + /*
660 + * Allocate descriptors
661 + */
662 + if (ar231x_allocate_descriptors(dev)) {
663 + printk("%s: %s: ar231x_allocate_descriptors failed\n",
664 + dev->name, __FUNCTION__);
665 + ecode = -EAGAIN;
666 + goto init_error;
667 + }
668 +
669 + /*
670 + * Get the memory for the skb rings.
671 + */
672 + if (sp->rx_skb == NULL) {
673 + sp->rx_skb =
674 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
675 + GFP_KERNEL);
676 + if (!(sp->rx_skb)) {
677 + printk("%s: %s: rx_skb kmalloc failed\n",
678 + dev->name, __FUNCTION__);
679 + ecode = -EAGAIN;
680 + goto init_error;
681 + }
682 + }
683 + memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
684 +
685 + if (sp->tx_skb == NULL) {
686 + sp->tx_skb =
687 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
688 + GFP_KERNEL);
689 + if (!(sp->tx_skb)) {
690 + printk("%s: %s: tx_skb kmalloc failed\n",
691 + dev->name, __FUNCTION__);
692 + ecode = -EAGAIN;
693 + goto init_error;
694 + }
695 + }
696 + memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
697 +
698 + /*
699 + * Set tx_csm before we start receiving interrupts, otherwise
700 + * the interrupt handler might think it is supposed to process
701 + * tx ints before we are up and running, which may cause a null
702 + * pointer access in the int handler.
703 + */
704 + sp->rx_skbprd = 0;
705 + sp->cur_rx = 0;
706 + sp->tx_prd = 0;
707 + sp->tx_csm = 0;
708 +
709 + /*
710 + * Zero the stats before starting the interface
711 + */
712 + memset(&dev->stats, 0, sizeof(dev->stats));
713 +
714 + /*
715 + * We load the ring here as there seem to be no way to tell the
716 + * firmware to wipe the ring without re-initializing it.
717 + */
718 + ar231x_load_rx_ring(dev, RX_RING_SIZE);
719 +
720 + /*
721 + * Init hardware
722 + */
723 + ar231x_reset_reg(dev);
724 +
725 + /*
726 + * Get the IRQ
727 + */
728 + ecode =
729 + request_irq(dev->irq, &ar231x_interrupt,
730 + IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
731 + dev->name, dev);
732 + if (ecode) {
733 + printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
734 + dev->name, __FUNCTION__, dev->irq);
735 + goto init_error;
736 + }
737 +
738 +
739 + tasklet_enable(&sp->rx_tasklet);
740 +
741 + return 0;
742 +
743 + init_error:
744 + ar231x_init_cleanup(dev);
745 + return ecode;
746 +}
747 +
748 +/*
749 + * Load the rx ring.
750 + *
751 + * Loading rings is safe without holding the spin lock since this is
752 + * done only before the device is enabled, thus no interrupts are
753 + * generated and by the interrupt handler/tasklet handler.
754 + */
755 +static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
756 +{
757 +
758 + struct ar231x_private *sp = netdev_priv(dev);
759 + short i, idx;
760 +
761 + idx = sp->rx_skbprd;
762 +
763 + for (i = 0; i < nr_bufs; i++) {
764 + struct sk_buff *skb;
765 + ar231x_descr_t *rd;
766 +
767 + if (sp->rx_skb[idx])
768 + break;
769 +
770 + skb = netdev_alloc_skb(dev, AR2313_BUFSIZE);
771 + if (!skb) {
772 + printk("\n\n\n\n %s: No memory in system\n\n\n\n",
773 + __FUNCTION__);
774 + break;
775 + }
776 +
777 + /*
778 + * Make sure IP header starts on a fresh cache line.
779 + */
780 + skb->dev = dev;
781 + skb_reserve(skb, RX_OFFSET);
782 + sp->rx_skb[idx] = skb;
783 +
784 + rd = (ar231x_descr_t *) & sp->rx_ring[idx];
785 +
786 + /* initialize dma descriptor */
787 + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
788 + DMA_RX1_CHAINED);
789 + rd->addr = virt_to_phys(skb->data);
790 + rd->descr =
791 + virt_to_phys(&sp->
792 + rx_ring[(idx + 1) & (AR2313_DESCR_ENTRIES - 1)]);
793 + rd->status = DMA_RX_OWN;
794 +
795 + idx = DSC_NEXT(idx);
796 + }
797 +
798 + if (i)
799 + sp->rx_skbprd = idx;
800 +
801 + return;
802 +}
803 +
804 +#define AR2313_MAX_PKTS_PER_CALL 64
805 +
806 +static int ar231x_rx_int(struct net_device *dev)
807 +{
808 + struct ar231x_private *sp = netdev_priv(dev);
809 + struct sk_buff *skb, *skb_new;
810 + ar231x_descr_t *rxdesc;
811 + unsigned int status;
812 + u32 idx;
813 + int pkts = 0;
814 + int rval;
815 +
816 + idx = sp->cur_rx;
817 +
818 + /* process at most the entire ring and then wait for another interrupt
819 + */
820 + while (1) {
821 +
822 + rxdesc = &sp->rx_ring[idx];
823 + status = rxdesc->status;
824 + if (status & DMA_RX_OWN) {
825 + /* SiByte owns descriptor or descr not yet filled in */
826 + rval = 0;
827 + break;
828 + }
829 +
830 + if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
831 + rval = 1;
832 + break;
833 + }
834 +
835 + if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
836 + dev->stats.rx_errors++;
837 + dev->stats.rx_dropped++;
838 +
839 + /* add statistics counters */
840 + if (status & DMA_RX_ERR_CRC)
841 + dev->stats.rx_crc_errors++;
842 + if (status & DMA_RX_ERR_COL)
843 + dev->stats.rx_over_errors++;
844 + if (status & DMA_RX_ERR_LENGTH)
845 + dev->stats.rx_length_errors++;
846 + if (status & DMA_RX_ERR_RUNT)
847 + dev->stats.rx_over_errors++;
848 + if (status & DMA_RX_ERR_DESC)
849 + dev->stats.rx_over_errors++;
850 +
851 + } else {
852 + /* alloc new buffer. */
853 + skb_new = netdev_alloc_skb(dev, AR2313_BUFSIZE + RX_OFFSET);
854 + if (skb_new != NULL) {
855 +
856 + skb = sp->rx_skb[idx];
857 + /* set skb */
858 + skb_put(skb,
859 + ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN);
860 +
861 + dev->stats.rx_bytes += skb->len;
862 + skb->protocol = eth_type_trans(skb, dev);
863 + /* pass the packet to upper layers */
864 + netif_rx(skb);
865 +
866 + skb_new->dev = dev;
867 + /* 16 bit align */
868 + skb_reserve(skb_new, RX_OFFSET);
869 + /* reset descriptor's curr_addr */
870 + rxdesc->addr = virt_to_phys(skb_new->data);
871 +
872 + dev->stats.rx_packets++;
873 + sp->rx_skb[idx] = skb_new;
874 + } else {
875 + dev->stats.rx_dropped++;
876 + }
877 + }
878 +
879 + rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
880 + DMA_RX1_CHAINED);
881 + rxdesc->status = DMA_RX_OWN;
882 +
883 + idx = DSC_NEXT(idx);
884 + }
885 +
886 + sp->cur_rx = idx;
887 +
888 + return rval;
889 +}
890 +
891 +
892 +static void ar231x_tx_int(struct net_device *dev)
893 +{
894 + struct ar231x_private *sp = netdev_priv(dev);
895 + u32 idx;
896 + struct sk_buff *skb;
897 + ar231x_descr_t *txdesc;
898 + unsigned int status = 0;
899 +
900 + idx = sp->tx_csm;
901 +
902 + while (idx != sp->tx_prd) {
903 + txdesc = &sp->tx_ring[idx];
904 +
905 + if ((status = txdesc->status) & DMA_TX_OWN) {
906 + /* ar231x dma still owns descr */
907 + break;
908 + }
909 + /* done with this descriptor */
910 + dma_unmap_single(NULL, txdesc->addr,
911 + txdesc->devcs & DMA_TX1_BSIZE_MASK,
912 + DMA_TO_DEVICE);
913 + txdesc->status = 0;
914 +
915 + if (status & DMA_TX_ERROR) {
916 + dev->stats.tx_errors++;
917 + dev->stats.tx_dropped++;
918 + if (status & DMA_TX_ERR_UNDER)
919 + dev->stats.tx_fifo_errors++;
920 + if (status & DMA_TX_ERR_HB)
921 + dev->stats.tx_heartbeat_errors++;
922 + if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
923 + dev->stats.tx_carrier_errors++;
924 + if (status & (DMA_TX_ERR_LATE |
925 + DMA_TX_ERR_COL |
926 + DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
927 + dev->stats.tx_aborted_errors++;
928 + } else {
929 + /* transmit OK */
930 + dev->stats.tx_packets++;
931 + }
932 +
933 + skb = sp->tx_skb[idx];
934 + sp->tx_skb[idx] = NULL;
935 + idx = DSC_NEXT(idx);
936 + dev->stats.tx_bytes += skb->len;
937 + dev_kfree_skb_irq(skb);
938 + }
939 +
940 + sp->tx_csm = idx;
941 +
942 + return;
943 +}
944 +
945 +
946 +static void rx_tasklet_func(unsigned long data)
947 +{
948 + struct net_device *dev = (struct net_device *) data;
949 + struct ar231x_private *sp = netdev_priv(dev);
950 +
951 + if (sp->unloading) {
952 + return;
953 + }
954 +
955 + if (ar231x_rx_int(dev)) {
956 + tasklet_hi_schedule(&sp->rx_tasklet);
957 + } else {
958 + unsigned long flags;
959 + spin_lock_irqsave(&sp->lock, flags);
960 + sp->dma_regs->intr_ena |= DMA_STATUS_RI;
961 + spin_unlock_irqrestore(&sp->lock, flags);
962 + }
963 +}
964 +
965 +static void rx_schedule(struct net_device *dev)
966 +{
967 + struct ar231x_private *sp = netdev_priv(dev);
968 +
969 + sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
970 +
971 + tasklet_hi_schedule(&sp->rx_tasklet);
972 +}
973 +
974 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
975 +{
976 + struct net_device *dev = (struct net_device *) dev_id;
977 + struct ar231x_private *sp = netdev_priv(dev);
978 + unsigned int status, enabled;
979 +
980 + /* clear interrupt */
981 + /*
982 + * Don't clear RI bit if currently disabled.
983 + */
984 + status = sp->dma_regs->status;
985 + enabled = sp->dma_regs->intr_ena;
986 + sp->dma_regs->status = status & enabled;
987 +
988 + if (status & DMA_STATUS_NIS) {
989 + /* normal status */
990 + /*
991 + * Don't schedule rx processing if interrupt
992 + * is already disabled.
993 + */
994 + if (status & enabled & DMA_STATUS_RI) {
995 + /* receive interrupt */
996 + rx_schedule(dev);
997 + }
998 + if (status & DMA_STATUS_TI) {
999 + /* transmit interrupt */
1000 + ar231x_tx_int(dev);
1001 + }
1002 + }
1003 +
1004 + /* abnormal status */
1005 + if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS)) {
1006 + ar231x_restart(dev);
1007 + }
1008 + return IRQ_HANDLED;
1009 +}
1010 +
1011 +
1012 +static int ar231x_open(struct net_device *dev)
1013 +{
1014 + struct ar231x_private *sp = netdev_priv(dev);
1015 + unsigned int ethsal, ethsah;
1016 +
1017 + /* reset the hardware, in case the MAC address changed */
1018 + ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
1019 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF));
1020 +
1021 + ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
1022 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
1023 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
1024 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF));
1025 +
1026 + sp->eth_regs->mac_addr[0] = ethsah;
1027 + sp->eth_regs->mac_addr[1] = ethsal;
1028 +
1029 + mdelay(10);
1030 +
1031 + dev->mtu = 1500;
1032 + netif_start_queue(dev);
1033 +
1034 + sp->eth_regs->mac_control |= MAC_CONTROL_RE;
1035 +
1036 + return 0;
1037 +}
1038 +
1039 +static void ar231x_halt(struct net_device *dev)
1040 +{
1041 + struct ar231x_private *sp = netdev_priv(dev);
1042 + int j;
1043 +
1044 + tasklet_disable(&sp->rx_tasklet);
1045 +
1046 + /* kill the MAC */
1047 + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
1048 + MAC_CONTROL_TE); /* disable Transmits */
1049 + /* stop dma */
1050 + sp->dma_regs->control = 0;
1051 + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
1052 +
1053 + /* place phy and MAC in reset */
1054 + *sp->int_regs |= (sp->cfg->reset_mac | sp->cfg->reset_phy);
1055 +
1056 + /* free buffers on tx ring */
1057 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
1058 + struct sk_buff *skb;
1059 + ar231x_descr_t *txdesc;
1060 +
1061 + txdesc = &sp->tx_ring[j];
1062 + txdesc->descr = 0;
1063 +
1064 + skb = sp->tx_skb[j];
1065 + if (skb) {
1066 + dev_kfree_skb(skb);
1067 + sp->tx_skb[j] = NULL;
1068 + }
1069 + }
1070 +}
1071 +
1072 +/*
1073 + * close should do nothing. Here's why. It's called when
1074 + * 'ifconfig bond0 down' is run. If it calls free_irq then
1075 + * the irq is gone forever ! When bond0 is made 'up' again,
1076 + * the ar231x_open () does not call request_irq (). Worse,
1077 + * the call to ar231x_halt() generates a WDOG reset due to
1078 + * the write to 'sp->int_regs' and the box reboots.
1079 + * Commenting this out is good since it allows the
1080 + * system to resume when bond0 is made up again.
1081 + */
1082 +static int ar231x_close(struct net_device *dev)
1083 +{
1084 +#if 0
1085 + /*
1086 + * Disable interrupts
1087 + */
1088 + disable_irq(dev->irq);
1089 +
1090 + /*
1091 + * Without (or before) releasing irq and stopping hardware, this
1092 + * is an absolute non-sense, by the way. It will be reset instantly
1093 + * by the first irq.
1094 + */
1095 + netif_stop_queue(dev);
1096 +
1097 + /* stop the MAC and DMA engines */
1098 + ar231x_halt(dev);
1099 +
1100 + /* release the interrupt */
1101 + free_irq(dev->irq, dev);
1102 +
1103 +#endif
1104 + return 0;
1105 +}
1106 +
1107 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
1108 +{
1109 + struct ar231x_private *sp = netdev_priv(dev);
1110 + ar231x_descr_t *td;
1111 + u32 idx;
1112 +
1113 + idx = sp->tx_prd;
1114 + td = &sp->tx_ring[idx];
1115 +
1116 + if (td->status & DMA_TX_OWN) {
1117 + /* free skbuf and lie to the caller that we sent it out */
1118 + dev->stats.tx_dropped++;
1119 + dev_kfree_skb(skb);
1120 +
1121 + /* restart transmitter in case locked */
1122 + sp->dma_regs->xmt_poll = 0;
1123 + return 0;
1124 + }
1125 +
1126 + /* Setup the transmit descriptor. */
1127 + td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
1128 + (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
1129 + td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
1130 + td->status = DMA_TX_OWN;
1131 +
1132 + /* kick transmitter last */
1133 + sp->dma_regs->xmt_poll = 0;
1134 +
1135 + sp->tx_skb[idx] = skb;
1136 + idx = DSC_NEXT(idx);
1137 + sp->tx_prd = idx;
1138 +
1139 + return 0;
1140 +}
1141 +
1142 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1143 +{
1144 + struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
1145 + struct ar231x_private *sp = netdev_priv(dev);
1146 + int ret;
1147 +
1148 + switch (cmd) {
1149 +
1150 + case SIOCETHTOOL:
1151 + spin_lock_irq(&sp->lock);
1152 + ret = phy_ethtool_ioctl(sp->phy_dev, (void *) ifr->ifr_data);
1153 + spin_unlock_irq(&sp->lock);
1154 + return ret;
1155 +
1156 + case SIOCSIFHWADDR:
1157 + if (copy_from_user
1158 + (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
1159 + return -EFAULT;
1160 + return 0;
1161 +
1162 + case SIOCGIFHWADDR:
1163 + if (copy_to_user
1164 + (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
1165 + return -EFAULT;
1166 + return 0;
1167 +
1168 + case SIOCGMIIPHY:
1169 + case SIOCGMIIREG:
1170 + case SIOCSMIIREG:
1171 + return phy_mii_ioctl(sp->phy_dev, data, cmd);
1172 +
1173 + default:
1174 + break;
1175 + }
1176 +
1177 + return -EOPNOTSUPP;
1178 +}
1179 +
1180 +static void ar231x_adjust_link(struct net_device *dev)
1181 +{
1182 + struct ar231x_private *sp = netdev_priv(dev);
1183 + unsigned int mc;
1184 +
1185 + if (!sp->phy_dev->link)
1186 + return;
1187 +
1188 + if (sp->phy_dev->duplex != sp->oldduplex) {
1189 + mc = readl(&sp->eth_regs->mac_control);
1190 + mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO);
1191 + if (sp->phy_dev->duplex)
1192 + mc |= MAC_CONTROL_F;
1193 + else
1194 + mc |= MAC_CONTROL_DRO;
1195 + writel(mc, &sp->eth_regs->mac_control);
1196 + sp->oldduplex = sp->phy_dev->duplex;
1197 + }
1198 +}
1199 +
1200 +#define MII_ADDR(phy, reg) \
1201 + ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
1202 +
1203 +static int
1204 +ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1205 +{
1206 + struct net_device *const dev = bus->priv;
1207 + struct ar231x_private *sp = netdev_priv(dev);
1208 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1209 +
1210 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
1211 + while (ethernet->mii_addr & MII_ADDR_BUSY);
1212 + return (ethernet->mii_data >> MII_DATA_SHIFT);
1213 +}
1214 +
1215 +static int
1216 +ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
1217 + u16 value)
1218 +{
1219 + struct net_device *const dev = bus->priv;
1220 + struct ar231x_private *sp = netdev_priv(dev);
1221 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1222 +
1223 + while (ethernet->mii_addr & MII_ADDR_BUSY);
1224 + ethernet->mii_data = value << MII_DATA_SHIFT;
1225 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
1226 +
1227 + return 0;
1228 +}
1229 +
1230 +static int ar231x_mdiobus_reset(struct mii_bus *bus)
1231 +{
1232 + struct net_device *const dev = bus->priv;
1233 +
1234 + ar231x_reset_reg(dev);
1235 +
1236 + return 0;
1237 +}
1238 +
1239 +static int ar231x_mdiobus_probe (struct net_device *dev)
1240 +{
1241 + struct ar231x_private *const sp = netdev_priv(dev);
1242 + struct phy_device *phydev = NULL;
1243 + int phy_addr;
1244 +
1245 + /* find the first (lowest address) PHY on the current MAC's MII bus */
1246 + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
1247 + if (sp->mii_bus->phy_map[phy_addr]) {
1248 + phydev = sp->mii_bus->phy_map[phy_addr];
1249 + sp->phy = phy_addr;
1250 + break; /* break out with first one found */
1251 + }
1252 +
1253 + if (!phydev) {
1254 + printk (KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
1255 + return -1;
1256 + }
1257 +
1258 + /* now we are supposed to have a proper phydev, to attach to... */
1259 + BUG_ON(!phydev);
1260 + BUG_ON(phydev->attached_dev);
1261 +
1262 + phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, 0,
1263 + PHY_INTERFACE_MODE_MII);
1264 +
1265 + if (IS_ERR(phydev)) {
1266 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1267 + return PTR_ERR(phydev);
1268 + }
1269 +
1270 + /* mask with MAC supported features */
1271 + phydev->supported &= (SUPPORTED_10baseT_Half
1272 + | SUPPORTED_10baseT_Full
1273 + | SUPPORTED_100baseT_Half
1274 + | SUPPORTED_100baseT_Full
1275 + | SUPPORTED_Autoneg
1276 + /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
1277 + | SUPPORTED_MII
1278 + | SUPPORTED_TP);
1279 +
1280 + phydev->advertising = phydev->supported;
1281 +
1282 + sp->oldduplex = -1;
1283 + sp->phy_dev = phydev;
1284 +
1285 + printk(KERN_INFO "%s: attached PHY driver [%s] "
1286 + "(mii_bus:phy_addr=%s)\n",
1287 + dev->name, phydev->drv->name, dev_name(&phydev->dev));
1288 +
1289 + return 0;
1290 +}
1291 +
1292 --- /dev/null
1293 +++ b/drivers/net/ar231x.h
1294 @@ -0,0 +1,302 @@
1295 +/*
1296 + * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
1297 + *
1298 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
1299 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1300 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1301 + *
1302 + * Thanks to Atheros for providing hardware and documentation
1303 + * enabling me to write this driver.
1304 + *
1305 + * This program is free software; you can redistribute it and/or modify
1306 + * it under the terms of the GNU General Public License as published by
1307 + * the Free Software Foundation; either version 2 of the License, or
1308 + * (at your option) any later version.
1309 + */
1310 +
1311 +#ifndef _AR2313_H_
1312 +#define _AR2313_H_
1313 +
1314 +#include <linux/autoconf.h>
1315 +#include <linux/bitops.h>
1316 +#include <asm/bootinfo.h>
1317 +#include <ar231x_platform.h>
1318 +
1319 +/*
1320 + * probe link timer - 5 secs
1321 + */
1322 +#define LINK_TIMER (5*HZ)
1323 +
1324 +#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
1325 +#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
1326 +#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
1327 +
1328 +#define AR2313_TX_TIMEOUT (HZ/4)
1329 +
1330 +/*
1331 + * Rings
1332 + */
1333 +#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
1334 +#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
1335 +
1336 +#define AR2313_MBGET 2
1337 +#define AR2313_MBSET 3
1338 +#define AR2313_PCI_RECONFIG 4
1339 +#define AR2313_PCI_DUMP 5
1340 +#define AR2313_TEST_PANIC 6
1341 +#define AR2313_TEST_NULLPTR 7
1342 +#define AR2313_READ_DATA 8
1343 +#define AR2313_WRITE_DATA 9
1344 +#define AR2313_GET_VERSION 10
1345 +#define AR2313_TEST_HANG 11
1346 +#define AR2313_SYNC 12
1347 +
1348 +#define DMA_RX_ERR_CRC BIT(1)
1349 +#define DMA_RX_ERR_DRIB BIT(2)
1350 +#define DMA_RX_ERR_MII BIT(3)
1351 +#define DMA_RX_EV2 BIT(5)
1352 +#define DMA_RX_ERR_COL BIT(6)
1353 +#define DMA_RX_LONG BIT(7)
1354 +#define DMA_RX_LS BIT(8) /* last descriptor */
1355 +#define DMA_RX_FS BIT(9) /* first descriptor */
1356 +#define DMA_RX_MF BIT(10) /* multicast frame */
1357 +#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
1358 +#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
1359 +#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
1360 +#define DMA_RX_ERROR BIT(15) /* error summary */
1361 +#define DMA_RX_LEN_MASK 0x3fff0000
1362 +#define DMA_RX_LEN_SHIFT 16
1363 +#define DMA_RX_FILT BIT(30)
1364 +#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
1365 +
1366 +#define DMA_RX1_BSIZE_MASK 0x000007ff
1367 +#define DMA_RX1_BSIZE_SHIFT 0
1368 +#define DMA_RX1_CHAINED BIT(24)
1369 +#define DMA_RX1_RER BIT(25)
1370 +
1371 +#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
1372 +#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
1373 +#define DMA_TX_COL_MASK 0x78
1374 +#define DMA_TX_COL_SHIFT 3
1375 +#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
1376 +#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
1377 +#define DMA_TX_ERR_LATE BIT(9) /* late collision */
1378 +#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
1379 +#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
1380 +#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
1381 +#define DMA_TX_ERROR BIT(15) /* frame aborted */
1382 +#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
1383 +
1384 +#define DMA_TX1_BSIZE_MASK 0x000007ff
1385 +#define DMA_TX1_BSIZE_SHIFT 0
1386 +#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
1387 +#define DMA_TX1_TER BIT(25) /* transmit end of ring */
1388 +#define DMA_TX1_FS BIT(29) /* first segment */
1389 +#define DMA_TX1_LS BIT(30) /* last segment */
1390 +#define DMA_TX1_IC BIT(31) /* interrupt on completion */
1391 +
1392 +#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
1393 +
1394 +#define MAC_CONTROL_RE BIT(2) /* receive enable */
1395 +#define MAC_CONTROL_TE BIT(3) /* transmit enable */
1396 +#define MAC_CONTROL_DC BIT(5) /* Deferral check */
1397 +#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
1398 +#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
1399 +#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
1400 +#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
1401 +#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
1402 +#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
1403 +#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
1404 +#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
1405 +#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
1406 +#define MAC_CONTROL_PR BIT(18) /* promiscuous mode (valid frames only) */
1407 +#define MAC_CONTROL_PM BIT(19) /* pass multicast */
1408 +#define MAC_CONTROL_F BIT(20) /* full-duplex */
1409 +#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
1410 +#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
1411 +#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
1412 +#define MAC_CONTROL_RA BIT(31) /* receive all (valid and invalid frames) */
1413 +
1414 +#define MII_ADDR_BUSY BIT(0)
1415 +#define MII_ADDR_WRITE BIT(1)
1416 +#define MII_ADDR_REG_SHIFT 6
1417 +#define MII_ADDR_PHY_SHIFT 11
1418 +#define MII_DATA_SHIFT 0
1419 +
1420 +#define FLOW_CONTROL_FCE BIT(1)
1421 +
1422 +#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
1423 +#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
1424 +#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
1425 +#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
1426 +
1427 +#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
1428 +#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
1429 +#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
1430 +#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
1431 +#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
1432 +#define DMA_STATUS_RI BIT(6) /* receive interrupt */
1433 +#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
1434 +#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
1435 +#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
1436 +#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
1437 +#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
1438 +#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
1439 +#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
1440 +#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
1441 +#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
1442 +#define DMA_STATUS_EB_SHIFT 23 /* error bits */
1443 +
1444 +#define DMA_CONTROL_SR BIT(1) /* start receive */
1445 +#define DMA_CONTROL_ST BIT(13) /* start transmit */
1446 +#define DMA_CONTROL_SF BIT(21) /* store and forward */
1447 +
1448 +
1449 +typedef struct {
1450 + volatile unsigned int status; // OWN, Device control and status.
1451 + volatile unsigned int devcs; // pkt Control bits + Length
1452 + volatile unsigned int addr; // Current Address.
1453 + volatile unsigned int descr; // Next descriptor in chain.
1454 +} ar231x_descr_t;
1455 +
1456 +
1457 +
1458 +//
1459 +// New Combo structure for Both Eth0 AND eth1
1460 +//
1461 +typedef struct {
1462 + volatile unsigned int mac_control; /* 0x00 */
1463 + volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
1464 + volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
1465 + volatile unsigned int mii_addr; /* 0x14 */
1466 + volatile unsigned int mii_data; /* 0x18 */
1467 + volatile unsigned int flow_control; /* 0x1c */
1468 + volatile unsigned int vlan_tag; /* 0x20 */
1469 + volatile unsigned int pad[7]; /* 0x24 - 0x3c */
1470 + volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
1471 +
1472 +} ETHERNET_STRUCT;
1473 +
1474 +/********************************************************************
1475 + * Interrupt controller
1476 + ********************************************************************/
1477 +
1478 +typedef struct {
1479 + volatile unsigned int wdog_control; /* 0x08 */
1480 + volatile unsigned int wdog_timer; /* 0x0c */
1481 + volatile unsigned int misc_status; /* 0x10 */
1482 + volatile unsigned int misc_mask; /* 0x14 */
1483 + volatile unsigned int global_status; /* 0x18 */
1484 + volatile unsigned int reserved; /* 0x1c */
1485 + volatile unsigned int reset_control; /* 0x20 */
1486 +} INTERRUPT;
1487 +
1488 +/********************************************************************
1489 + * DMA controller
1490 + ********************************************************************/
1491 +typedef struct {
1492 + volatile unsigned int bus_mode; /* 0x00 (CSR0) */
1493 + volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
1494 + volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
1495 + volatile unsigned int rcv_base; /* 0x0c (CSR3) */
1496 + volatile unsigned int xmt_base; /* 0x10 (CSR4) */
1497 + volatile unsigned int status; /* 0x14 (CSR5) */
1498 + volatile unsigned int control; /* 0x18 (CSR6) */
1499 + volatile unsigned int intr_ena; /* 0x1c (CSR7) */
1500 + volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
1501 + volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
1502 + volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
1503 + volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
1504 +} DMA;
1505 +
1506 +/*
1507 + * Struct private for the Sibyte.
1508 + *
1509 + * Elements are grouped so variables used by the tx handling goes
1510 + * together, and will go into the same cache lines etc. in order to
1511 + * avoid cache line contention between the rx and tx handling on SMP.
1512 + *
1513 + * Frequently accessed variables are put at the beginning of the
1514 + * struct to help the compiler generate better/shorter code.
1515 + */
1516 +struct ar231x_private {
1517 + struct net_device *dev;
1518 + int version;
1519 + u32 mb[2];
1520 +
1521 + volatile ETHERNET_STRUCT *phy_regs;
1522 + volatile ETHERNET_STRUCT *eth_regs;
1523 + volatile DMA *dma_regs;
1524 + volatile u32 *int_regs;
1525 + struct ar231x_eth *cfg;
1526 +
1527 + spinlock_t lock; /* Serialise access to device */
1528 +
1529 + /*
1530 + * RX and TX descriptors, must be adjacent
1531 + */
1532 + ar231x_descr_t *rx_ring;
1533 + ar231x_descr_t *tx_ring;
1534 +
1535 +
1536 + struct sk_buff **rx_skb;
1537 + struct sk_buff **tx_skb;
1538 +
1539 + /*
1540 + * RX elements
1541 + */
1542 + u32 rx_skbprd;
1543 + u32 cur_rx;
1544 +
1545 + /*
1546 + * TX elements
1547 + */
1548 + u32 tx_prd;
1549 + u32 tx_csm;
1550 +
1551 + /*
1552 + * Misc elements
1553 + */
1554 + char name[48];
1555 + struct {
1556 + u32 address;
1557 + u32 length;
1558 + char *mapping;
1559 + } desc;
1560 +
1561 +
1562 + struct timer_list link_timer;
1563 + unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
1564 + unsigned short mac;
1565 + unsigned short link; /* 0 - link down, 1 - link up */
1566 + u16 phyData;
1567 +
1568 + struct tasklet_struct rx_tasklet;
1569 + int unloading;
1570 +
1571 + struct phy_device *phy_dev;
1572 + struct mii_bus *mii_bus;
1573 + int oldduplex;
1574 +};
1575 +
1576 +
1577 +/*
1578 + * Prototypes
1579 + */
1580 +static int ar231x_init(struct net_device *dev);
1581 +#ifdef TX_TIMEOUT
1582 +static void ar231x_tx_timeout(struct net_device *dev);
1583 +#endif
1584 +static int ar231x_restart(struct net_device *dev);
1585 +static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
1586 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
1587 +static int ar231x_open(struct net_device *dev);
1588 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
1589 +static int ar231x_close(struct net_device *dev);
1590 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr,
1591 + int cmd);
1592 +static void ar231x_init_cleanup(struct net_device *dev);
1593 +static int ar231x_setup_timer(struct net_device *dev);
1594 +static void ar231x_link_timer_fn(unsigned long data);
1595 +static void ar231x_check_link(struct net_device *dev);
1596 +#endif /* _AR2313_H_ */
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