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fix base-files-arch package
[openwrt.git] / openwrt / target / linux / linux-2.4 / patches / ar7 / 000-ar7_support.patch
1 diff -urN linux.old/arch/mips/ar7/ar7/jump.S linux.dev/arch/mips/ar7/ar7/jump.S
2 --- linux.old/arch/mips/ar7/ar7/jump.S 1970-01-01 01:00:00.000000000 +0100
3 +++ linux.dev/arch/mips/ar7/ar7/jump.S 2005-07-12 02:59:26.167672328 +0200
4 @@ -0,0 +1,89 @@
5 +/*
6 + * $Id$
7 + * Copyright (C) $Date$ $Author$
8 + *
9 + * This program is free software; you can redistribute it and/or modify
10 + * it under the terms of the GNU General Public License as published by
11 + * the Free Software Foundation; either version 2 of the License, or
12 + * (at your option) any later version.
13 + *
14 + * This program is distributed in the hope that it will be useful,
15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 + * GNU General Public License for more details.
18 + *
19 + * You should have received a copy of the GNU General Public License
20 + * along with this program; if not, write to the Free Software
21 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 + *
23 + */
24 +
25 +#include <linux/config.h>
26 +#include <linux/threads.h>
27 +
28 +#include <asm/asm.h>
29 +#include <asm/cacheops.h>
30 +#include <asm/current.h>
31 +#include <asm/offset.h>
32 +#include <asm/processor.h>
33 +#include <asm/regdef.h>
34 +#include <asm/cachectl.h>
35 +#include <asm/mipsregs.h>
36 +#include <asm/stackframe.h>
37 +
38 +.text
39 +
40 +.set noreorder
41 +.set noat
42 +
43 +/* TLB Miss Vector */
44 +
45 +LEAF(jump_tlb_miss)
46 + .set mips2
47 + lui k0,0x9400
48 + ori k0,0
49 + jr k0
50 + nop
51 +END(jump_tlb_miss)
52 +
53 + /* Unused TLB Miss Vector */
54 +
55 +LEAF(jump_tlb_miss_unused)
56 + .set mips2
57 + lui k0,0x9400
58 + ori k0,0x80
59 + jr k0
60 + nop
61 +END(jump_tlb_miss_unused)
62 +
63 + /* Cache Error Vector */
64 +
65 +LEAF(jump_cache_error)
66 + .set mips2
67 + lui k0,0x9400
68 + ori k0,0x100
69 + jr k0
70 + nop
71 +END(jump_cache_error)
72 +
73 + /* General Exception */
74 +
75 +LEAF(jump_general_exception)
76 + .set mips2
77 + lui k0,0x9400
78 + ori k0,0x180
79 + jr k0
80 + nop
81 +END(jump_general_exception)
82 +
83 + /* Dedicated Interrupt */
84 +
85 +LEAF(jump_dedicated_interrupt)
86 + .set mips2
87 + lui k0,0x9400
88 + ori k0,0x200
89 + jr k0
90 + nop
91 +END(jump_dedicated_interrupt)
92 +
93 + .set at
94 diff -urN linux.old/arch/mips/ar7/ar7/Makefile linux.dev/arch/mips/ar7/ar7/Makefile
95 --- linux.old/arch/mips/ar7/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
96 +++ linux.dev/arch/mips/ar7/ar7/Makefile 2005-07-12 02:59:26.167672328 +0200
97 @@ -0,0 +1,31 @@
98 +# $Id$
99 +# Copyright (C) $Date$ $Author$
100 +#
101 +# This program is free software; you can redistribute it and/or modify
102 +# it under the terms of the GNU General Public License as published by
103 +# the Free Software Foundation; either version 2 of the License, or
104 +# (at your option) any later version.
105 +#
106 +# This program is distributed in the hope that it will be useful,
107 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
108 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
109 +# GNU General Public License for more details.
110 +#
111 +# You should have received a copy of the GNU General Public License
112 +# along with this program; if not, write to the Free Software
113 +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
114 +
115 +.S.s:
116 + $(CPP) $(AFLAGS) $< -o $*.s
117 +
118 +.S.o:
119 + $(CC) $(AFLAGS) -c $< -o $*.o
120 +
121 +EXTRA_CFLAGS := -DLITTLE_ENDIAN -D_LINK_KSEG0_
122 +
123 +O_TARGET := ar7.o
124 +
125 +export-objs := misc.o
126 +obj-y += paging.o jump.o misc.o
127 +
128 +include $(TOPDIR)/Rules.make
129 diff -urN linux.old/arch/mips/ar7/ar7/misc.c linux.dev/arch/mips/ar7/ar7/misc.c
130 --- linux.old/arch/mips/ar7/ar7/misc.c 1970-01-01 01:00:00.000000000 +0100
131 +++ linux.dev/arch/mips/ar7/ar7/misc.c 2005-07-12 02:59:26.168672176 +0200
132 @@ -0,0 +1,319 @@
133 +#include <asm/ar7/sangam.h>
134 +#include <asm/ar7/avalanche_misc.h>
135 +#include <linux/module.h>
136 +#include <linux/spinlock.h>
137 +
138 +#define TRUE 1
139 +
140 +static unsigned int avalanche_vbus_freq;
141 +
142 +REMOTE_VLYNQ_DEV_RESET_CTRL_FN p_remote_vlynq_dev_reset_ctrl = NULL;
143 +
144 +/*****************************************************************************
145 + * Reset Control Module.
146 + *****************************************************************************/
147 +void avalanche_reset_ctrl(unsigned int module_reset_bit,
148 + AVALANCHE_RESET_CTRL_T reset_ctrl)
149 +{
150 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
151 +
152 + if(module_reset_bit >= 32 && module_reset_bit < 64)
153 + return;
154 +
155 + if(module_reset_bit >= 64)
156 + {
157 + if(p_remote_vlynq_dev_reset_ctrl)
158 + return(p_remote_vlynq_dev_reset_ctrl(module_reset_bit - 64, reset_ctrl));
159 + else
160 + return;
161 + }
162 +
163 + if(reset_ctrl == OUT_OF_RESET)
164 + *reset_reg |= 1 << module_reset_bit;
165 + else
166 + *reset_reg &= ~(1 << module_reset_bit);
167 +}
168 +
169 +AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int module_reset_bit)
170 +{
171 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
172 +
173 + return (((*reset_reg) & (1 << module_reset_bit)) ? OUT_OF_RESET : IN_RESET );
174 +}
175 +
176 +void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode)
177 +{
178 + volatile unsigned int *sw_reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_SWRCR;
179 + *sw_reset_reg = mode;
180 +}
181 +
182 +#define AVALANCHE_RST_CTRL_RSR_MASK 0x3
183 +
184 +AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status()
185 +{
186 + volatile unsigned int *sys_reset_status = (unsigned int*) AVALANCHE_RST_CTRL_RSR;
187 +
188 + return ( (AVALANCHE_SYS_RESET_STATUS_T) (*sys_reset_status & AVALANCHE_RST_CTRL_RSR_MASK) );
189 +}
190 +
191 +
192 +/*****************************************************************************
193 + * Power Control Module
194 + *****************************************************************************/
195 +#define AVALANCHE_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
196 +#define AVALANCHE_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
197 +
198 +
199 +void avalanche_power_ctrl(unsigned int module_power_bit, AVALANCHE_POWER_CTRL_T power_ctrl)
200 +{
201 + volatile unsigned int *power_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
202 +
203 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
204 + /* power down the module */
205 + *power_reg |= (1 << module_power_bit);
206 + else
207 + /* power on the module */
208 + *power_reg &= (~(1 << module_power_bit));
209 +}
210 +
211 +AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int module_power_bit)
212 +{
213 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
214 +
215 + return (((*power_status_reg) & (1 << module_power_bit)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP);
216 +}
217 +
218 +void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode)
219 +{
220 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
221 +
222 + *power_status_reg &= AVALANCHE_GLOBAL_POWER_DOWN_MASK;
223 + *power_status_reg |= ( power_mode << AVALANCHE_GLOBAL_POWER_DOWN_BIT);
224 +}
225 +
226 +AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void)
227 +{
228 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
229 +
230 + return((AVALANCHE_SYS_POWER_MODE_T) (((*power_status_reg) & (~AVALANCHE_GLOBAL_POWER_DOWN_MASK))
231 + >> AVALANCHE_GLOBAL_POWER_DOWN_BIT));
232 +}
233 +
234 +/*****************************************************************************
235 + * GPIO Control
236 + *****************************************************************************/
237 +
238 +/****************************************************************************
239 + * FUNCTION: avalanche_gpio_init
240 + ***************************************************************************/
241 +void avalanche_gpio_init(void)
242 +{
243 + spinlock_t closeLock;
244 + unsigned int closeFlag;
245 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
246 + spin_lock_irqsave(&closeLock, closeFlag);
247 + *reset_reg |= (1 << AVALANCHE_GPIO_RESET_BIT);
248 + spin_unlock_irqrestore(&closeLock, closeFlag);
249 +}
250 +
251 +/****************************************************************************
252 + * FUNCTION: avalanche_gpio_ctrl
253 + ***************************************************************************/
254 +int avalanche_gpio_ctrl(unsigned int gpio_pin,
255 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
256 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction)
257 +{
258 + spinlock_t closeLock;
259 + unsigned int closeFlag;
260 + volatile unsigned int *gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_ENBL;
261 +
262 + if(gpio_pin >= 32)
263 + return(-1);
264 +
265 + spin_lock_irqsave(&closeLock, closeFlag);
266 +
267 + if(pin_mode == GPIO_PIN)
268 + {
269 + *gpio_ctrl |= (1 << gpio_pin);
270 +
271 + gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_DIR;
272 +
273 + if(pin_direction == GPIO_INPUT_PIN)
274 + *gpio_ctrl |= (1 << gpio_pin);
275 + else
276 + *gpio_ctrl &= ~(1 << gpio_pin);
277 + }
278 + else /* FUNCTIONAL PIN */
279 + {
280 + *gpio_ctrl &= ~(1 << gpio_pin);
281 + }
282 +
283 + spin_unlock_irqrestore(&closeLock, closeFlag);
284 +
285 + return (0);
286 +}
287 +
288 +/****************************************************************************
289 + * FUNCTION: avalanche_gpio_out
290 + ***************************************************************************/
291 +int avalanche_gpio_out_bit(unsigned int gpio_pin, int value)
292 +{
293 + spinlock_t closeLock;
294 + unsigned int closeFlag;
295 + volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
296 +
297 + if(gpio_pin >= 32)
298 + return(-1);
299 +
300 + spin_lock_irqsave(&closeLock, closeFlag);
301 + if(value == TRUE)
302 + *gpio_out |= 1 << gpio_pin;
303 + else
304 + *gpio_out &= ~(1 << gpio_pin);
305 + spin_unlock_irqrestore(&closeLock, closeFlag);
306 +
307 + return(0);
308 +}
309 +
310 +/****************************************************************************
311 + * FUNCTION: avalanche_gpio_in
312 + ***************************************************************************/
313 +int avalanche_gpio_in_bit(unsigned int gpio_pin)
314 +{
315 + spinlock_t closeLock;
316 + unsigned int closeFlag;
317 + volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
318 + int ret_val = 0;
319 +
320 + if(gpio_pin >= 32)
321 + return(-1);
322 +
323 + spin_lock_irqsave(&closeLock, closeFlag);
324 + ret_val = ((*gpio_in) & (1 << gpio_pin));
325 + spin_unlock_irqrestore(&closeLock, closeFlag);
326 +
327 + return (ret_val);
328 +}
329 +
330 +/****************************************************************************
331 + * FUNCTION: avalanche_gpio_out_val
332 + ***************************************************************************/
333 +int avalanche_gpio_out_value(unsigned int out_val, unsigned int out_mask,
334 + unsigned int reg_index)
335 +{
336 + spinlock_t closeLock;
337 + unsigned int closeFlag;
338 + volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
339 +
340 + if(reg_index > 0)
341 + return(-1);
342 +
343 + spin_lock_irqsave(&closeLock, closeFlag);
344 + *gpio_out &= ~out_mask;
345 + *gpio_out |= out_val;
346 + spin_unlock_irqrestore(&closeLock, closeFlag);
347 +
348 + return(0);
349 +}
350 +
351 +/****************************************************************************
352 + * FUNCTION: avalanche_gpio_in_value
353 + ***************************************************************************/
354 +int avalanche_gpio_in_value(unsigned int* in_val, unsigned int reg_index)
355 +{
356 + spinlock_t closeLock;
357 + unsigned int closeFlag;
358 + volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
359 +
360 + if(reg_index > 0)
361 + return(-1);
362 +
363 + spin_lock_irqsave(&closeLock, closeFlag);
364 + *in_val = *gpio_in;
365 + spin_unlock_irqrestore(&closeLock, closeFlag);
366 +
367 + return (0);
368 +}
369 +
370 +/***********************************************************************
371 + *
372 + * Wakeup Control Module for TNETV1050 Communication Processor
373 + *
374 + ***********************************************************************/
375 +
376 +#define AVALANCHE_WAKEUP_POLARITY_BIT 16
377 +
378 +void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
379 + AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
380 + AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity)
381 +{
382 + volatile unsigned int *wakeup_status_reg = (unsigned int*) AVALANCHE_WAKEUP_CTRL_WKCR;
383 +
384 + /* enable/disable */
385 + if (wakeup_ctrl == WAKEUP_ENABLED)
386 + /* enable wakeup */
387 + *wakeup_status_reg |= wakeup_int;
388 + else
389 + /* disable wakeup */
390 + *wakeup_status_reg &= (~wakeup_int);
391 +
392 + /* set polarity */
393 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
394 + *wakeup_status_reg |= (wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
395 + else
396 + *wakeup_status_reg &= ~(wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
397 +}
398 +
399 +void avalanche_set_vbus_freq(unsigned int new_vbus_freq)
400 +{
401 + avalanche_vbus_freq = new_vbus_freq;
402 +}
403 +
404 +unsigned int avalanche_get_vbus_freq()
405 +{
406 + return(avalanche_vbus_freq);
407 +}
408 +
409 +unsigned int avalanche_get_chip_version_info()
410 +{
411 + return(*(volatile unsigned int*)AVALANCHE_CVR);
412 +}
413 +
414 +SET_MDIX_ON_CHIP_FN_T p_set_mdix_on_chip_fn = NULL;
415 +
416 +int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation)
417 +{
418 + if(p_set_mdix_on_chip_fn)
419 + return (p_set_mdix_on_chip_fn(base_addr, operation));
420 + else
421 + return(-1);
422 +}
423 +
424 +unsigned int avalanche_is_mdix_on_chip(void)
425 +{
426 + return(p_set_mdix_on_chip_fn ? 1:0);
427 +}
428 +
429 +EXPORT_SYMBOL(avalanche_reset_ctrl);
430 +EXPORT_SYMBOL(avalanche_get_reset_status);
431 +EXPORT_SYMBOL(avalanche_sys_reset);
432 +EXPORT_SYMBOL(avalanche_get_sys_last_reset_status);
433 +EXPORT_SYMBOL(avalanche_power_ctrl);
434 +EXPORT_SYMBOL(avalanche_get_power_status);
435 +EXPORT_SYMBOL(avalanche_set_global_power_mode);
436 +EXPORT_SYMBOL(avalanche_get_global_power_mode);
437 +EXPORT_SYMBOL(avalanche_set_mdix_on_chip);
438 +EXPORT_SYMBOL(avalanche_is_mdix_on_chip);
439 +
440 +EXPORT_SYMBOL(avalanche_gpio_init);
441 +EXPORT_SYMBOL(avalanche_gpio_ctrl);
442 +EXPORT_SYMBOL(avalanche_gpio_out_bit);
443 +EXPORT_SYMBOL(avalanche_gpio_in_bit);
444 +EXPORT_SYMBOL(avalanche_gpio_out_value);
445 +EXPORT_SYMBOL(avalanche_gpio_in_value);
446 +
447 +EXPORT_SYMBOL(avalanche_set_vbus_freq);
448 +EXPORT_SYMBOL(avalanche_get_vbus_freq);
449 +
450 +EXPORT_SYMBOL(avalanche_get_chip_version_info);
451 +
452 diff -urN linux.old/arch/mips/ar7/ar7/paging.c linux.dev/arch/mips/ar7/ar7/paging.c
453 --- linux.old/arch/mips/ar7/ar7/paging.c 1970-01-01 01:00:00.000000000 +0100
454 +++ linux.dev/arch/mips/ar7/ar7/paging.c 2005-07-12 02:59:26.168672176 +0200
455 @@ -0,0 +1,314 @@
456 +/*
457 + * -*- linux-c -*-
458 + * This file is subject to the terms and conditions of the GNU General Public
459 + * License. See the file "COPYING" in the main directory of this archive
460 + * for more details.
461 + *
462 + * Copyright (C) 2002 by Jeff Harrell (jharrell@ti.com)
463 + * Copyright (C) 2002 Texas Instruments, Inc.
464 + *
465 + */
466 +
467 +/*
468 + * This file takes care of the "memory hole" issue that exists with the standard
469 + * linux kernel and the TI Avalanche ASIC. The Avalanche ASIC requires an offset
470 + * of 0x14000000 due to the ASIC's memory map constraints. This file corrects the
471 + * paging tables so that the only reflect valid memory (i.e. > 0x14000000)
472 + *
473 + * -JAH
474 + */
475 +#include <linux/config.h>
476 +#include <linux/signal.h>
477 +#include <linux/sched.h>
478 +#include <linux/kernel.h>
479 +#include <linux/errno.h>
480 +#include <linux/string.h>
481 +#include <linux/types.h>
482 +#include <linux/ptrace.h>
483 +#include <linux/mman.h>
484 +#include <linux/mm.h>
485 +#include <linux/swap.h>
486 +#include <linux/smp.h>
487 +#include <linux/init.h>
488 +#ifdef CONFIG_BLK_DEV_INITRD
489 +#include <linux/blk.h>
490 +#endif /* CONFIG_BLK_DEV_INITRD */
491 +#include <linux/highmem.h>
492 +#include <linux/bootmem.h>
493 +
494 +#include <asm/processor.h>
495 +#include <asm/system.h>
496 +#include <asm/uaccess.h>
497 +#include <asm/pgtable.h>
498 +#include <asm/pgalloc.h>
499 +#include <asm/mmu_context.h>
500 +#include <asm/io.h>
501 +#include <asm/tlb.h>
502 +#include <asm/cpu.h>
503 +
504 +#define __MEMORY_START CONFIG_AR7_MEMORY
505 +
506 +#ifdef CONFIG_DISCONTIGMEM
507 +pg_data_t discontig_page_data[NR_NODES];
508 +bootmem_data_t discontig_node_bdata[NR_NODES];
509 +#endif
510 +
511 +static unsigned long totalram_pages;
512 +/* static unsigned long totalhigh_pages; */
513 +
514 +#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
515 +#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
516 +
517 +#define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
518 +#define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
519 +#define PFN_PHYS(x) ((x) << PAGE_SHIFT)
520 +
521 +unsigned long bootmap_size;
522 +
523 +extern char *prom_getenv(char *envname);
524 +
525 +/*
526 + * We have upto 8 empty zeroed pages so we can map one of the right colour
527 + * when needed. This is necessary only on R4000 / R4400 SC and MC versions
528 + * where we have to avoid VCED / VECI exceptions for good performance at
529 + * any price. Since page is never written to after the initialization we
530 + * don't have to care about aliases on other CPUs.
531 + */
532 +
533 +static inline unsigned long setup_zero_pages(void)
534 +{
535 + unsigned long order, size;
536 + struct page *page;
537 + if(current_cpu_data.options & MIPS_CPU_VCE)
538 + order = 3;
539 + else
540 + order = 0;
541 +
542 + empty_zero_page = __get_free_pages(GFP_KERNEL, order);
543 +
544 + if (!empty_zero_page)
545 + panic("Oh boy, that early out of memory?");
546 +
547 + page = virt_to_page(empty_zero_page);
548 +
549 + while (page < virt_to_page(empty_zero_page + (PAGE_SIZE << order))) {
550 + set_bit(PG_reserved, &page->flags);
551 + set_page_count(page, 0);
552 + page++;
553 + }
554 +
555 + size = PAGE_SIZE << order;
556 + zero_page_mask = (size - 1) & PAGE_MASK;
557 + memset((void *)empty_zero_page, 0, size);
558 +
559 + return 1UL << order;
560 +}
561 +
562 +/*
563 + * paging_init() sets up the page tables
564 + *
565 + * This routines also unmaps the page at virtual kernel address 0, so
566 + * that we can trap those pesky NULL-reference errors in the kernel.
567 + */
568 +void __init paging_init(void)
569 +{
570 + unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
571 + unsigned long low, start_pfn;
572 +
573 + /* Initialize the entire pgd. */
574 + pgd_init((unsigned long)swapper_pg_dir);
575 + pgd_init((unsigned long)swapper_pg_dir + PAGE_SIZE / 2);
576 +
577 +
578 + start_pfn = START_PFN;
579 + // max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
580 + low = MAX_LOW_PFN;
581 +
582 + /* Avalanche DMA-able memory 0x14000000+memsize */
583 +
584 + zones_size[ZONE_DMA] = low - start_pfn;
585 +
586 + free_area_init_node(0, NODE_DATA(0), 0, zones_size, __MEMORY_START, 0);
587 +
588 +#ifdef CONFIG_DISCONTIGMEM
589 + zones_size[ZONE_DMA] = __MEMORY_SIZE_2ND >> PAGE_SHIFT;
590 + zones_size[ZONE_NORMAL] = 0;
591 + free_area_init_node(1, NODE_DATA(1), 0, zones_size, __MEMORY_START_2ND, 0);
592 +#endif /* CONFIG_DISCONTIGMEM */
593 +
594 +}
595 +
596 +extern char _ftext, _etext, _fdata, _edata, _end;
597 +extern char __init_begin, __init_end;
598 +
599 +void __init mem_init(void)
600 +{
601 + int codesize, reservedpages, datasize, initsize;
602 + int tmp;
603 +
604 + max_mapnr = num_physpages = MAX_LOW_PFN - START_PFN;
605 + high_memory = (void *)__va(MAX_LOW_PFN * PAGE_SIZE);
606 +
607 + /* free up the memory associated with Adam2 -
608 + * that is the, after the first page that is
609 + * reserved all the way up to the start of the kernel
610 + */
611 + free_bootmem_node(NODE_DATA(0), (__MEMORY_START+PAGE_SIZE),
612 + (__pa(&_ftext))-(__MEMORY_START+PAGE_SIZE) );
613 +
614 + /* this will put all low memory onto the freelists */
615 + totalram_pages += free_all_bootmem_node(NODE_DATA(0));
616 +
617 + /* Setup zeroed pages */
618 + totalram_pages -= setup_zero_pages();
619 +
620 +
621 +#ifdef CONFIG_DISCONTIGMEM
622 + totalram_pages += free_all_bootmem_node(NODE_DATA(1));
623 +#endif
624 + reservedpages = 0;
625 + for (tmp = 0; tmp < num_physpages; tmp++)
626 + /*
627 + * Only count reserved RAM pages
628 + */
629 + if (PageReserved(mem_map+tmp))
630 + reservedpages++;
631 +
632 + codesize = (unsigned long) &_etext - (unsigned long) &_ftext;
633 + datasize = (unsigned long) &_edata - (unsigned long) &_fdata;
634 + initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin;
635 +
636 + printk("Memory: %luk/%luk available (%dk kernel code, %dk reserved, %dk data, %dk init)\n",
637 + (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
638 + max_mapnr << (PAGE_SHIFT-10),
639 + codesize >> 10,
640 + reservedpages << (PAGE_SHIFT-10),
641 + datasize >> 10,
642 + initsize >> 10);
643 +
644 +}
645 +
646 +/* fixes paging routines for avalanche (utilized in /arch/mips/kernel/setup.c) */
647 +
648 +void avalanche_bootmem_init(void)
649 +{
650 + unsigned long start_pfn, max_pfn;
651 + unsigned long max_low_pfn;
652 + unsigned int memsize,memory_end,memory_start;
653 + char *memsize_str;
654 +
655 + memsize_str = prom_getenv("memsize");
656 + if (!memsize_str) {
657 + memsize = 0x02000000;
658 + } else {
659 + memsize = simple_strtol(memsize_str, NULL, 0);
660 + }
661 +
662 +
663 + memory_start = (unsigned long)PAGE_OFFSET+__MEMORY_START;
664 + memory_end = memory_start + memsize;
665 +
666 + /*
667 + * Find the highest memory page fram number we have available
668 + */
669 +
670 + max_pfn = PFN_DOWN(__pa(memory_end));
671 +
672 + /*
673 + * Determine the low and high memory ranges
674 + */
675 +
676 + max_low_pfn = max_pfn;
677 +
678 + /*
679 + * Partially used pages are not usable - thus we are
680 + * rounding upwards:
681 + */
682 +
683 + start_pfn = PFN_UP(__pa(&_end));
684 +
685 + /*
686 + * Find a proper area for the bootmem bitmap. After this
687 + * bootstrap step all allocations (until the page allocator is
688 + * intact) must be done via bootmem_alloc().
689 + */
690 +
691 + bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
692 + __MEMORY_START>>PAGE_SHIFT, max_low_pfn);
693 +
694 +
695 + /*
696 + * Register fully available low RAM pages with the bootmem allocator.
697 + */
698 +
699 + {
700 + unsigned long curr_pfn, last_pfn, pages;
701 +
702 + /*
703 + * We are rounding up the start address of usable memory:
704 + */
705 + curr_pfn = PFN_UP(__MEMORY_START);
706 +
707 + /*
708 + * ... and at the end of the usable range downwards:
709 + */
710 + last_pfn = PFN_DOWN(__pa(memory_end));
711 +
712 + if (last_pfn > max_low_pfn)
713 + last_pfn = max_low_pfn;
714 +
715 + pages = last_pfn - curr_pfn;
716 +
717 +
718 + free_bootmem_node(NODE_DATA(0), PFN_PHYS(curr_pfn),
719 + PFN_PHYS(pages));
720 + }
721 +
722 + /*
723 + * Reserve the kernel text and
724 + * Reserve the bootmem bitmap. We do this in two steps (first step
725 + * was init_bootmem()), because this catches the (definitely buggy)
726 + * case of us accidentally initializing the bootmem allocator with
727 + * an invalid RAM area.
728 + */
729 + reserve_bootmem_node(NODE_DATA(0), __MEMORY_START+PAGE_SIZE,
730 + (PFN_PHYS(start_pfn)+bootmap_size+PAGE_SIZE-1)-__MEMORY_START);
731 +
732 + /*
733 + * reserve physical page 0 - it's a special BIOS page on many boxes,
734 + * enabling clean reboots, SMP operation, laptop functions.
735 + */
736 + reserve_bootmem_node(NODE_DATA(0), __MEMORY_START, PAGE_SIZE);
737 +}
738 +
739 +extern char __init_begin, __init_end;
740 +
741 +void free_initmem(void)
742 +{
743 + unsigned long addr;
744 + // prom_free_prom_memory ();
745 +
746 + addr = (unsigned long) &__init_begin;
747 + while (addr < (unsigned long) &__init_end) {
748 + ClearPageReserved(virt_to_page(addr));
749 + set_page_count(virt_to_page(addr), 1);
750 + free_page(addr);
751 + totalram_pages++;
752 + addr += PAGE_SIZE;
753 + }
754 + printk("Freeing unused kernel memory: %dk freed\n",
755 + (&__init_end - &__init_begin) >> 10);
756 +}
757 +
758 +void si_meminfo(struct sysinfo *val)
759 +{
760 + val->totalram = totalram_pages;
761 + val->sharedram = 0;
762 + val->freeram = nr_free_pages();
763 + val->bufferram = atomic_read(&buffermem_pages);
764 + val->totalhigh = 0;
765 + val->freehigh = nr_free_highpages();
766 + val->mem_unit = PAGE_SIZE;
767 +
768 + return;
769 +}
770 diff -urN linux.old/arch/mips/ar7/cmdline.c linux.dev/arch/mips/ar7/cmdline.c
771 --- linux.old/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100
772 +++ linux.dev/arch/mips/ar7/cmdline.c 2005-07-12 02:59:26.169672024 +0200
773 @@ -0,0 +1,64 @@
774 +/*
775 + * Carsten Langgaard, carstenl@mips.com
776 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
777 + *
778 + * This program is free software; you can distribute it and/or modify it
779 + * under the terms of the GNU General Public License (Version 2) as
780 + * published by the Free Software Foundation.
781 + *
782 + * This program is distributed in the hope it will be useful, but WITHOUT
783 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
784 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
785 + * for more details.
786 + *
787 + * You should have received a copy of the GNU General Public License along
788 + * with this program; if not, write to the Free Software Foundation, Inc.,
789 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
790 + *
791 + * Kernel command line creation using the prom monitor (YAMON) argc/argv.
792 + */
793 +#include <linux/init.h>
794 +#include <linux/string.h>
795 +
796 +#include <asm/bootinfo.h>
797 +
798 +extern int prom_argc;
799 +extern int *_prom_argv;
800 +
801 +/*
802 + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
803 + * This macro take care of sign extension.
804 + */
805 +#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
806 +
807 +char arcs_cmdline[CL_SIZE];
808 +
809 +char * __init prom_getcmdline(void)
810 +{
811 + return &(arcs_cmdline[0]);
812 +}
813 +
814 +
815 +void __init prom_init_cmdline(void)
816 +{
817 + char *cp;
818 + int actr;
819 +
820 + actr = 1; /* Always ignore argv[0] */
821 +
822 + cp = &(arcs_cmdline[0]);
823 +#ifdef CONFIG_CMDLINE_BOOL
824 + strcpy(cp, CONFIG_CMDLINE);
825 + cp += strlen(CONFIG_CMDLINE);
826 + *cp++ = ' ';
827 +#endif
828 + while(actr < prom_argc) {
829 + strcpy(cp, prom_argv(actr));
830 + cp += strlen(prom_argv(actr));
831 + *cp++ = ' ';
832 + actr++;
833 + }
834 + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
835 + --cp;
836 + *cp = '\0';
837 +}
838 diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c
839 --- linux.old/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100
840 +++ linux.dev/arch/mips/ar7/init.c 2005-07-12 02:59:26.169672024 +0200
841 @@ -0,0 +1,144 @@
842 +/*
843 + * Carsten Langgaard, carstenl@mips.com
844 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
845 + *
846 + * This program is free software; you can distribute it and/or modify it
847 + * under the terms of the GNU General Public License (Version 2) as
848 + * published by the Free Software Foundation.
849 + *
850 + * This program is distributed in the hope it will be useful, but WITHOUT
851 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
852 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
853 + * for more details.
854 + *
855 + * You should have received a copy of the GNU General Public License along
856 + * with this program; if not, write to the Free Software Foundation, Inc.,
857 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
858 + *
859 + * PROM library initialisation code.
860 + */
861 +#include <linux/config.h>
862 +#include <linux/init.h>
863 +#include <linux/string.h>
864 +#include <linux/kernel.h>
865 +#include <linux/module.h>
866 +
867 +#include <asm/io.h>
868 +#include <asm/mips-boards/prom.h>
869 +#include <asm/mips-boards/generic.h>
870 +
871 +/* Environment variable */
872 +typedef struct {
873 + char *name;
874 + char *val;
875 +} t_env_var;
876 +
877 +int prom_argc;
878 +int *_prom_argv, *_prom_envp;
879 +
880 +/* max # of Adam2 environment variables */
881 +#define MAX_ENV_ENTRY 80
882 +
883 +static t_env_var local_envp[MAX_ENV_ENTRY];
884 +int init_debug = 0;
885 +
886 +char *prom_getenv(char *envname)
887 +{
888 + /*
889 + * Return a pointer to the given environment variable.
890 + * In 64-bit mode: we're using 64-bit pointers, but all pointers
891 + * in the PROM structures are only 32-bit, so we need some
892 + * workarounds, if we are running in 64-bit mode.
893 + */
894 + int i, index=0;
895 + t_env_var *env = (t_env_var *) local_envp;
896 +
897 + i = strlen(envname);
898 + while (env->name) {
899 + if(strncmp(envname, env->name, i) == 0) {
900 + return(env->val);
901 + }
902 + env++;
903 + }
904 +
905 + return NULL;
906 +}
907 +
908 +static inline unsigned char str2hexnum(unsigned char c)
909 +{
910 + if (c >= '0' && c <= '9')
911 + return c - '0';
912 + if (c >= 'a' && c <= 'f')
913 + return c - 'a' + 10;
914 + return 0; /* foo */
915 +}
916 +
917 +static inline void str2eaddr(unsigned char *ea, unsigned char *str)
918 +{
919 + int i;
920 +
921 + for (i = 0; i < 6; i++) {
922 + unsigned char num;
923 +
924 + if((*str == '.') || (*str == ':'))
925 + str++;
926 + num = str2hexnum(*str++) << 4;
927 + num |= (str2hexnum(*str++));
928 + ea[i] = num;
929 + }
930 +}
931 +
932 +int get_ethernet_addr(char *ethernet_addr)
933 +{
934 + char *ethaddr_str;
935 +
936 + ethaddr_str = prom_getenv("ethaddr");
937 + if (!ethaddr_str) {
938 + printk("ethaddr not set in boot prom\n");
939 + return -1;
940 + }
941 + str2eaddr(ethernet_addr, ethaddr_str);
942 +
943 + if (init_debug > 1) {
944 + int i;
945 + printk("get_ethernet_addr: ");
946 + for (i=0; i<5; i++)
947 + printk("%02x:", (unsigned char)*(ethernet_addr+i));
948 + printk("%02x\n", *(ethernet_addr+i));
949 + }
950 +
951 + return 0;
952 +}
953 +
954 +int __init prom_init(int argc, char **argv, char **envp)
955 +{
956 + int i;
957 + t_env_var *env = (t_env_var *) envp;
958 +
959 + prom_argc = argc;
960 + _prom_argv = (int *)argv;
961 + _prom_envp = (int *)envp;
962 +
963 + /* Copy what we need locally so we are not dependent on
964 + * bootloader RAM. In Adam2, the environment parameters
965 + * are in flash but the table that references them is in
966 + * RAM
967 + */
968 + for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
969 + if (env->name) {
970 + local_envp[i].name = env->name;
971 + local_envp[i].val = env->val;
972 + } else {
973 + local_envp[i].name = NULL;
974 + local_envp[i].val = NULL;
975 + }
976 + }
977 +
978 + set_io_port_base(0);
979 +
980 + prom_printf("\nLINUX started...\n");
981 + prom_init_cmdline();
982 + prom_meminit();
983 +
984 + return 0;
985 +}
986 diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c
987 --- linux.old/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100
988 +++ linux.dev/arch/mips/ar7/irq.c 2005-07-12 02:59:26.190668832 +0200
989 @@ -0,0 +1,705 @@
990 +/*
991 + * Nitin Dhingra, iamnd@ti.com
992 + * Copyright (C) 2002 Texas Instruments, Inc. All rights reserved.
993 + *
994 + * ########################################################################
995 + *
996 + * This program is free software; you can distribute it and/or modify it
997 + * under the terms of the GNU General Public License (Version 2) as
998 + * published by the Free Software Foundation.
999 + *
1000 + * This program is distributed in the hope it will be useful, but WITHOUT
1001 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1002 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1003 + * for more details.
1004 + *
1005 + * You should have received a copy of the GNU General Public License along
1006 + * with this program; if not, write to the Free Software Foundation, Inc.,
1007 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1008 + *
1009 + * ########################################################################
1010 + *
1011 + * Routines for generic manipulation of the interrupts found on the Texas
1012 + * Instruments avalanche board
1013 + *
1014 + */
1015 +
1016 +#include <linux/config.h>
1017 +#include <linux/init.h>
1018 +#include <linux/sched.h>
1019 +#include <linux/slab.h>
1020 +#include <linux/interrupt.h>
1021 +#include <linux/kernel_stat.h>
1022 +#include <linux/proc_fs.h>
1023 +#include <asm/irq.h>
1024 +#include <asm/mips-boards/prom.h>
1025 +#include <asm/ar7/ar7.h>
1026 +#include <asm/ar7/avalanche_intc.h>
1027 +#include <asm/gdb-stub.h>
1028 +
1029 +
1030 +#define shutdown_avalanche_irq disable_avalanche_irq
1031 +#define mask_and_ack_avalanche_irq disable_avalanche_irq
1032 +
1033 +static unsigned int startup_avalanche_irq(unsigned int irq);
1034 +static void end_avalanche_irq(unsigned int irq);
1035 +void enable_avalanche_irq(unsigned int irq_nr);
1036 +void disable_avalanche_irq(unsigned int irq_nr);
1037 +
1038 +static struct hw_interrupt_type avalanche_irq_type = {
1039 + "TI AVALANCHE",
1040 + startup_avalanche_irq,
1041 + shutdown_avalanche_irq,
1042 + enable_avalanche_irq,
1043 + disable_avalanche_irq,
1044 + mask_and_ack_avalanche_irq,
1045 + end_avalanche_irq,
1046 + NULL
1047 +};
1048 +
1049 +irq_desc_t irq_desc_ti[AVALANCHE_INT_END+1] __cacheline_aligned =
1050 +{ [0 ... AVALANCHE_INT_END] = { 0, &avalanche_irq_type, NULL, 0, SPIN_LOCK_UNLOCKED}};
1051 +
1052 +
1053 +unsigned long spurious_count = 0;
1054 +
1055 +struct avalanche_ictrl_regs *avalanche_hw0_icregs; /* Interrupt control regs (primary) */
1056 +struct avalanche_exctrl_regs *avalanche_hw0_ecregs; /* Exception control regs (secondary) */
1057 +struct avalanche_ipace_regs *avalanche_hw0_ipaceregs;
1058 +struct avalanche_channel_int_number *avalanche_hw0_chregs; /* Channel control registers */
1059 +
1060 +extern asmlinkage void mipsIRQ(void);
1061 +
1062 +
1063 +/*
1064 + * The avalanche/MIPS interrupt line numbers are used to represent the
1065 + * interrupts within the irqaction arrays. The index notation is
1066 + * is as follows:
1067 + *
1068 + * 0-7 MIPS CPU Exceptions (HW/SW)
1069 + * 8-47 Primary Interrupts (Avalanche)
1070 + * 48-79 Secondary Interrupts (Avalanche)
1071 + *
1072 + */
1073 +
1074 +
1075 +static struct irqaction *hw0_irq_action_primary[AVINTNUM(AVALANCHE_INT_END_PRIMARY)] =
1076 +{
1077 + NULL, NULL, NULL, NULL,
1078 + NULL, NULL, NULL, NULL,
1079 + NULL, NULL, NULL, NULL,
1080 + NULL, NULL, NULL, NULL,
1081 + NULL, NULL, NULL, NULL,
1082 + NULL, NULL, NULL, NULL,
1083 + NULL, NULL, NULL, NULL,
1084 + NULL, NULL, NULL, NULL,
1085 + NULL, NULL, NULL, NULL,
1086 + NULL, NULL, NULL, NULL
1087 +};
1088 +
1089 +static struct irqaction *hw0_irq_action_secondary[AVINTNUM(AVALANCHE_INT_END_SECONDARY)] =
1090 +{
1091 + NULL, NULL, NULL, NULL,
1092 + NULL, NULL, NULL, NULL,
1093 + NULL, NULL, NULL, NULL,
1094 + NULL, NULL, NULL, NULL,
1095 + NULL, NULL, NULL, NULL,
1096 + NULL, NULL, NULL, NULL,
1097 + NULL, NULL, NULL, NULL,
1098 + NULL, NULL, NULL, NULL
1099 +};
1100 +
1101 +/*
1102 + This remaps interrupts to exist on other channels than the default
1103 + channels. essentially we can use the line # as the index for this
1104 + array
1105 + */
1106 +
1107 +
1108 +static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
1109 +unsigned long uni_secondary_interrupt = 0;
1110 +
1111 +static struct irqaction r4ktimer_action = {
1112 + NULL, 0, 0, "R4000 timer/counter", NULL, NULL,
1113 +};
1114 +
1115 +static struct irqaction *irq_action[8] = {
1116 + NULL, /* SW int 0 */
1117 + NULL, /* SW int 1 */
1118 + NULL, /* HW int 0 */
1119 + NULL,
1120 + NULL,
1121 + NULL, /* HW int 3 */
1122 + NULL, /* HW int 4 */
1123 + &r4ktimer_action /* HW int 5 */
1124 +};
1125 +
1126 +static void end_avalanche_irq(unsigned int irq)
1127 +{
1128 + if (!(irq_desc_ti[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
1129 + enable_avalanche_irq(irq);
1130 +}
1131 +
1132 +void disable_avalanche_irq(unsigned int irq_nr)
1133 +{
1134 + unsigned long flags;
1135 + unsigned long chan_nr=0;
1136 + unsigned long int_bit=0;
1137 +
1138 + if(irq_nr >= AVALANCHE_INT_END)
1139 + {
1140 + printk("whee, invalid irq_nr %d\n", irq_nr);
1141 + panic("IRQ, you lose...");
1142 + }
1143 +
1144 + save_and_cli(flags);
1145 +
1146 +
1147 + if(irq_nr < MIPS_EXCEPTION_OFFSET)
1148 + {
1149 + /* disable mips exception */
1150 +
1151 + int_bit = read_c0_status() & ~(1 << (8+irq_nr));
1152 + change_c0_status(ST0_IM,int_bit);
1153 + restore_flags(flags);
1154 + return;
1155 + }
1156 +
1157 + /* irq_nr represents the line number for the interrupt. We must
1158 + * disable the channel number associated with that line number.
1159 + */
1160 +
1161 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
1162 + chan_nr = AVINTNUM(irq_nr); /*CHECK THIS ALSO*/
1163 + else
1164 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
1165 +
1166 + /* disable the interrupt channel bit */
1167 +
1168 + /* primary interrupt #'s 0-31 */
1169 +
1170 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
1171 + avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
1172 +
1173 + /* primary interrupt #'s 32-39 */
1174 +
1175 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
1176 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
1177 + avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
1178 +
1179 + else /* secondary interrupt #'s 0-31 */
1180 + avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
1181 +
1182 + restore_flags(flags);
1183 +}
1184 +
1185 +void enable_avalanche_irq(unsigned int irq_nr)
1186 +{
1187 + unsigned long flags;
1188 + unsigned long chan_nr=0;
1189 + unsigned long int_bit=0;
1190 +
1191 + if(irq_nr > AVALANCHE_INT_END) {
1192 + printk("whee, invalid irq_nr %d\n", irq_nr);
1193 + panic("IRQ, you lose...");
1194 + }
1195 +
1196 + save_and_cli(flags);
1197 +
1198 +
1199 + if(irq_nr < MIPS_EXCEPTION_OFFSET)
1200 + {
1201 + /* Enable MIPS exceptions */
1202 + int_bit = read_c0_status();
1203 + change_c0_status(ST0_IM,int_bit | (1<<(8+irq_nr)));
1204 + restore_flags(flags);
1205 + return;
1206 + }
1207 +
1208 + /* irq_nr represents the line number for the interrupt. We must
1209 + * disable the channel number associated with that line number.
1210 + */
1211 +
1212 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
1213 + chan_nr = AVINTNUM(irq_nr);
1214 + else
1215 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];
1216 +
1217 + /* enable the interrupt channel bit */
1218 +
1219 + /* primary interrupt #'s 0-31 */
1220 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
1221 + avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
1222 +
1223 + /* primary interrupt #'s 32 throuth 39 */
1224 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
1225 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
1226 + avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
1227 +
1228 + else /* secondary interrupt #'s 0-31 */
1229 + avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
1230 +
1231 + restore_flags(flags);
1232 +}
1233 +
1234 +static unsigned int startup_avalanche_irq(unsigned int irq)
1235 +{
1236 + enable_avalanche_irq(irq);
1237 + return 0; /* never anything pending */
1238 +}
1239 +
1240 +
1241 +int get_irq_list(char *buf)
1242 +{
1243 + int i, len = 0;
1244 + int num = 0;
1245 + struct irqaction *action;
1246 +
1247 + for (i = 0; i < MIPS_EXCEPTION_OFFSET; i++, num++)
1248 + {
1249 + action = irq_action[i];
1250 + if (!action)
1251 + continue;
1252 + len += sprintf(buf+len, "%2d: %8d %c %s",
1253 + num, kstat.irqs[0][num],
1254 + (action->flags & SA_INTERRUPT) ? '+' : ' ',
1255 + action->name);
1256 + for (action=action->next; action; action = action->next) {
1257 + len += sprintf(buf+len, ",%s %s",
1258 + (action->flags & SA_INTERRUPT) ? " +" : "",
1259 + action->name);
1260 + }
1261 + len += sprintf(buf+len, " [MIPS interrupt]\n");
1262 + }
1263 +
1264 +
1265 + for (i = 0; i < AVINTNUM(AVALANCHE_INT_END); i++,num++)
1266 + {
1267 + if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
1268 + action = hw0_irq_action_primary[i];
1269 + else
1270 + action = hw0_irq_action_secondary[i-AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
1271 + if (!action)
1272 + continue;
1273 + len += sprintf(buf+len, "%2d: %8d %c %s",
1274 + num, kstat.irqs[0][ LNXINTNUM(i) ],
1275 + (action->flags & SA_INTERRUPT) ? '+' : ' ',
1276 + action->name);
1277 +
1278 + for (action=action->next; action; action = action->next)
1279 + {
1280 + len += sprintf(buf+len, ",%s %s",
1281 + (action->flags & SA_INTERRUPT) ? " +" : "",
1282 + action->name);
1283 + }
1284 +
1285 + if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
1286 + len += sprintf(buf+len, " [hw0 (Avalanche Primary)]\n");
1287 + else
1288 + len += sprintf(buf+len, " [hw0 (Avalanche Secondary)]\n");
1289 +
1290 + }
1291 +
1292 + return len;
1293 +}
1294 +
1295 +int request_irq(unsigned int irq,
1296 + void (*handler)(int, void *, struct pt_regs *),
1297 + unsigned long irqflags,
1298 + const char * devname,
1299 + void *dev_id)
1300 +{
1301 + struct irqaction *action;
1302 +
1303 + if (irq > AVALANCHE_INT_END)
1304 + return -EINVAL;
1305 + if (!handler)
1306 + return -EINVAL;
1307 +
1308 + action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
1309 + if(!action)
1310 + return -ENOMEM;
1311 +
1312 + action->handler = handler;
1313 + action->flags = irqflags;
1314 + action->mask = 0;
1315 + action->name = devname;
1316 + irq_desc_ti[irq].action = action;
1317 + action->dev_id = dev_id;
1318 +
1319 + action->next = 0;
1320 +
1321 + if(irq < MIPS_EXCEPTION_OFFSET)
1322 + {
1323 + irq_action[irq] = action;
1324 + enable_avalanche_irq(irq);
1325 + return 0;
1326 + }
1327 +
1328 + if(irq < AVALANCHE_INT_END_PRIMARY)
1329 + hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = action;
1330 + else
1331 + hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = action;
1332 +
1333 + enable_avalanche_irq(irq);
1334 +
1335 + return 0;
1336 +}
1337 +
1338 +void free_irq(unsigned int irq, void *dev_id)
1339 +{
1340 + struct irqaction *action;
1341 +
1342 + if (irq > AVALANCHE_INT_END) {
1343 + printk("Trying to free IRQ%d\n",irq);
1344 + return;
1345 + }
1346 +
1347 + if(irq < MIPS_EXCEPTION_OFFSET)
1348 + {
1349 + action = irq_action[irq];
1350 + irq_action[irq] = NULL;
1351 + irq_desc_ti[irq].action = NULL;
1352 + disable_avalanche_irq(irq);
1353 + kfree(action);
1354 + return;
1355 + }
1356 +
1357 + if(irq < AVALANCHE_INT_END_PRIMARY) {
1358 + action = hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]];
1359 + hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = NULL;
1360 + irq_desc_ti[irq].action = NULL;
1361 + }
1362 + else {
1363 + action = hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY];
1364 + hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = NULL;
1365 + irq_desc_ti[irq].action = NULL;
1366 + }
1367 +
1368 + disable_avalanche_irq(irq);
1369 + kfree(action);
1370 +}
1371 +
1372 +#ifdef CONFIG_KGDB
1373 +extern void breakpoint(void);
1374 +extern int remote_debug;
1375 +#endif
1376 +
1377 +//void init_IRQ(void) __init;
1378 +void __init init_IRQ(void)
1379 +{
1380 + int i;
1381 +
1382 + avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
1383 + avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
1384 + avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
1385 + avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
1386 +
1387 + /* Disable interrupts and clear pending
1388 + */
1389 +
1390 + avalanche_hw0_icregs->intecr1 = 0xffffffff; /* disable interrupts 0:31 */
1391 + avalanche_hw0_icregs->intcr1 = 0xffffffff; /* clear interrupts 0:31 */
1392 + avalanche_hw0_icregs->intecr2 = 0xff; /* disable interrupts 32:39 */
1393 + avalanche_hw0_icregs->intcr2 = 0xff; /* clear interrupts 32:39 */
1394 + avalanche_hw0_ecregs->exiecr = 0xffffffff; /* disable secondary interrupts 0:31 */
1395 + avalanche_hw0_ecregs->excr = 0xffffffff; /* clear secondary interrupts 0:31 */
1396 +
1397 +
1398 + /* Channel to line mapping, Line to Channel mapping */
1399 +
1400 + for(i = 0; i < 40; i++)
1401 + avalanche_int_set(i,i);
1402 +
1403 + /* Now safe to set the exception vector. */
1404 + set_except_vector(0, mipsIRQ);
1405 +
1406 + /* Setup the IRQ description array. These will be mapped
1407 + * as flat interrupts numbers. The mapping is as follows
1408 + *
1409 + * 0-7 MIPS CPU Exceptions (HW/SW)
1410 + * 8-46 Primary Interrupts (Avalanche)
1411 + * 47-78 Secondary Interrupts (Avalanche)
1412 + */
1413 +
1414 + for (i = 0; i <= AVALANCHE_INT_END; i++)
1415 + {
1416 + irq_desc_ti[i].status = IRQ_DISABLED;
1417 + irq_desc_ti[i].action = 0;
1418 + irq_desc_ti[i].depth = 1;
1419 + irq_desc_ti[i].handler = &avalanche_irq_type;
1420 + }
1421 +
1422 +#ifdef CONFIG_KGDB
1423 + if (remote_debug)
1424 + {
1425 + set_debug_traps();
1426 + breakpoint();
1427 + }
1428 +#endif
1429 +}
1430 +
1431 +
1432 +void avalanche_hw0_irqdispatch(struct pt_regs *regs)
1433 +{
1434 + struct irqaction *action;
1435 + int irq, cpu = smp_processor_id();
1436 + unsigned long int_line_number,status;
1437 + int i,secondary = 0;
1438 + int chan_nr=0;
1439 +
1440 + int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
1441 + chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
1442 +
1443 +
1444 + if(chan_nr < 32)
1445 + {
1446 + if( chan_nr != uni_secondary_interrupt)
1447 + avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
1448 +
1449 + }
1450 +
1451 + if((chan_nr < 40) && (chan_nr > 31))
1452 + {
1453 + avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
1454 + }
1455 +
1456 +
1457 + /* If the Priority Interrupt Index Register returns 40 then no
1458 + * interrupts are pending
1459 + */
1460 +
1461 + if(chan_nr == 40)
1462 + return;
1463 +
1464 + if(chan_nr == uni_secondary_interrupt)
1465 + {
1466 + status = avalanche_hw0_ecregs->exsr;
1467 + for(i=0; i < AVINTNUM(AVALANCHE_INT_END_SECONDARY); i++)
1468 + {
1469 + if (status & 1<<i)
1470 + {
1471 + /* clear secondary interrupt */
1472 + avalanche_hw0_ecregs->excr = 1 << i;
1473 + break;
1474 + }
1475 + }
1476 + irq = i;
1477 + secondary = 1;
1478 +
1479 + /* clear the universal secondary interrupt */
1480 + avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
1481 +
1482 + }
1483 + else
1484 + irq = chan_nr;
1485 +
1486 + /* Suraj Add code to clear secondary interrupt */
1487 +
1488 + if(secondary)
1489 + action = hw0_irq_action_secondary[irq];
1490 + else
1491 + action = hw0_irq_action_primary[irq];
1492 +
1493 + /* if action == NULL, then we don't have a handler for the irq */
1494 +
1495 + if ( action == NULL ) {
1496 + printk("No handler for hw0 irq: %i\n", irq);
1497 + return;
1498 + }
1499 +
1500 + irq_enter(cpu,irq);
1501 + if(secondary)
1502 + {
1503 + kstat.irqs[0][(irq + AVINTNUM(AVALANCHE_INT_END_PRIMARY)) + 8]++;
1504 + action->handler((irq + AVALANCHE_INT_END_PRIMARY), action->dev_id, regs);
1505 + }
1506 + else
1507 + {
1508 + kstat.irqs[0][irq + 8]++;
1509 + action->handler(LNXINTNUM(irq), action->dev_id, regs);
1510 + }
1511 +
1512 + irq_exit(cpu,irq);
1513 +
1514 + if(softirq_pending(cpu))
1515 + do_softirq();
1516 +
1517 + return;
1518 +}
1519 +
1520 +void avalanche_int_set(int channel, int line)
1521 +{
1522 + switch(channel)
1523 + {
1524 + case(0):
1525 + avalanche_hw0_chregs->cintnr0 = line;
1526 + break;
1527 + case(1):
1528 + avalanche_hw0_chregs->cintnr1 = line;
1529 + break;
1530 + case(2):
1531 + avalanche_hw0_chregs->cintnr2 = line;
1532 + break;
1533 + case(3):
1534 + avalanche_hw0_chregs->cintnr3 = line;
1535 + break;
1536 + case(4):
1537 + avalanche_hw0_chregs->cintnr4 = line;
1538 + break;
1539 + case(5):
1540 + avalanche_hw0_chregs->cintnr5 = line;
1541 + break;
1542 + case(6):
1543 + avalanche_hw0_chregs->cintnr6 = line;
1544 + break;
1545 + case(7):
1546 + avalanche_hw0_chregs->cintnr7 = line;
1547 + break;
1548 + case(8):
1549 + avalanche_hw0_chregs->cintnr8 = line;
1550 + break;
1551 + case(9):
1552 + avalanche_hw0_chregs->cintnr9 = line;
1553 + break;
1554 + case(10):
1555 + avalanche_hw0_chregs->cintnr10 = line;
1556 + break;
1557 + case(11):
1558 + avalanche_hw0_chregs->cintnr11 = line;
1559 + break;
1560 + case(12):
1561 + avalanche_hw0_chregs->cintnr12 = line;
1562 + break;
1563 + case(13):
1564 + avalanche_hw0_chregs->cintnr13 = line;
1565 + break;
1566 + case(14):
1567 + avalanche_hw0_chregs->cintnr14 = line;
1568 + break;
1569 + case(15):
1570 + avalanche_hw0_chregs->cintnr15 = line;
1571 + break;
1572 + case(16):
1573 + avalanche_hw0_chregs->cintnr16 = line;
1574 + break;
1575 + case(17):
1576 + avalanche_hw0_chregs->cintnr17 = line;
1577 + break;
1578 + case(18):
1579 + avalanche_hw0_chregs->cintnr18 = line;
1580 + break;
1581 + case(19):
1582 + avalanche_hw0_chregs->cintnr19 = line;
1583 + break;
1584 + case(20):
1585 + avalanche_hw0_chregs->cintnr20 = line;
1586 + break;
1587 + case(21):
1588 + avalanche_hw0_chregs->cintnr21 = line;
1589 + break;
1590 + case(22):
1591 + avalanche_hw0_chregs->cintnr22 = line;
1592 + break;
1593 + case(23):
1594 + avalanche_hw0_chregs->cintnr23 = line;
1595 + break;
1596 + case(24):
1597 + avalanche_hw0_chregs->cintnr24 = line;
1598 + break;
1599 + case(25):
1600 + avalanche_hw0_chregs->cintnr25 = line;
1601 + break;
1602 + case(26):
1603 + avalanche_hw0_chregs->cintnr26 = line;
1604 + break;
1605 + case(27):
1606 + avalanche_hw0_chregs->cintnr27 = line;
1607 + break;
1608 + case(28):
1609 + avalanche_hw0_chregs->cintnr28 = line;
1610 + break;
1611 + case(29):
1612 + avalanche_hw0_chregs->cintnr29 = line;
1613 + break;
1614 + case(30):
1615 + avalanche_hw0_chregs->cintnr30 = line;
1616 + break;
1617 + case(31):
1618 + avalanche_hw0_chregs->cintnr31 = line;
1619 + break;
1620 + case(32):
1621 + avalanche_hw0_chregs->cintnr32 = line;
1622 + break;
1623 + case(33):
1624 + avalanche_hw0_chregs->cintnr33 = line;
1625 + break;
1626 + case(34):
1627 + avalanche_hw0_chregs->cintnr34 = line;
1628 + break;
1629 + case(35):
1630 + avalanche_hw0_chregs->cintnr35 = line;
1631 + break;
1632 + case(36):
1633 + avalanche_hw0_chregs->cintnr36 = line;
1634 + break;
1635 + case(37):
1636 + avalanche_hw0_chregs->cintnr37 = line;
1637 + break;
1638 + case(38):
1639 + avalanche_hw0_chregs->cintnr38 = line;
1640 + break;
1641 + case(39):
1642 + avalanche_hw0_chregs->cintnr39 = line;
1643 + break;
1644 + default:
1645 + printk("Error: Unknown Avalanche interrupt channel\n");
1646 + }
1647 +
1648 + line_to_channel[line] = channel; /* Suraj check */
1649 +
1650 + if (channel == UNIFIED_SECONDARY_INTERRUPT)
1651 + uni_secondary_interrupt = line;
1652 +
1653 +}
1654 +
1655 +
1656 +#define AVALANCHE_MAX_PACING_BLK 3
1657 +#define AVALANCHE_PACING_LOW_VAL 2
1658 +#define AVALANCHE_PACING_HIGH_VAL 63
1659 +
1660 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num,
1661 + unsigned int pace_value)
1662 +{
1663 + unsigned int blk_offset;
1664 + unsigned long flags;
1665 +
1666 + if(irq_nr < MIPS_EXCEPTION_OFFSET &&
1667 + irq_nr >= AVALANCHE_INT_END_PRIMARY)
1668 + return (0);
1669 +
1670 + if(blk_num > AVALANCHE_MAX_PACING_BLK)
1671 + return(-1);
1672 +
1673 + if(pace_value > AVALANCHE_PACING_HIGH_VAL &&
1674 + pace_value < AVALANCHE_PACING_LOW_VAL)
1675 + return(-1);
1676 +
1677 + blk_offset = blk_num*8;
1678 +
1679 + save_and_cli(flags);
1680 +
1681 + /* disable the interrupt pacing, if enabled previously */
1682 + avalanche_hw0_ipaceregs->ipacemax &= ~(0xff << blk_offset);
1683 +
1684 + /* clear the pacing map */
1685 + avalanche_hw0_ipaceregs->ipacemap &= ~(0xff << blk_offset);
1686 +
1687 + /* setup the new values */
1688 + avalanche_hw0_ipaceregs->ipacemap |= ((AVINTNUM(irq_nr)) << blk_offset);
1689 + avalanche_hw0_ipaceregs->ipacemax |= ((0x80 | pace_value) << blk_offset);
1690 +
1691 + restore_flags(flags);
1692 +
1693 + return(0);
1694 +}
1695 diff -urN linux.old/arch/mips/ar7/Makefile linux.dev/arch/mips/ar7/Makefile
1696 --- linux.old/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
1697 +++ linux.dev/arch/mips/ar7/Makefile 2005-07-12 02:59:43.730002448 +0200
1698 @@ -0,0 +1,13 @@
1699 +.S.s:
1700 + $(CPP) $(AFLAGS) $< -o $*.s
1701 +
1702 +.S.o:
1703 + $(CC) $(AFLAGS) -c $< -o $*.o
1704 +
1705 +EXTRA_CFLAGS := -I$(TOPDIR)/include/asm/ar7 -DLITTLE_ENDIAN -D_LINK_KSEG0_
1706 +O_TARGET := ar7.o
1707 +
1708 +obj-y := tnetd73xx_misc.o
1709 +obj-y += setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o
1710 +
1711 +include $(TOPDIR)/Rules.make
1712 diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c
1713 --- linux.old/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100
1714 +++ linux.dev/arch/mips/ar7/memory.c 2005-07-12 02:59:26.190668832 +0200
1715 @@ -0,0 +1,130 @@
1716 +/*
1717 + * Carsten Langgaard, carstenl@mips.com
1718 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1719 + *
1720 + * ########################################################################
1721 + *
1722 + * This program is free software; you can distribute it and/or modify it
1723 + * under the terms of the GNU General Public License (Version 2) as
1724 + * published by the Free Software Foundation.
1725 + *
1726 + * This program is distributed in the hope it will be useful, but WITHOUT
1727 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1728 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1729 + * for more details.
1730 + *
1731 + * You should have received a copy of the GNU General Public License along
1732 + * with this program; if not, write to the Free Software Foundation, Inc.,
1733 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1734 + *
1735 + * ########################################################################
1736 + *
1737 + * PROM library functions for acquiring/using memory descriptors given to
1738 + * us from the YAMON.
1739 + *
1740 + */
1741 +#include <linux/config.h>
1742 +#include <linux/init.h>
1743 +#include <linux/mm.h>
1744 +#include <linux/bootmem.h>
1745 +
1746 +#include <asm/bootinfo.h>
1747 +#include <asm/page.h>
1748 +#include <asm/mips-boards/prom.h>
1749 +#include <asm/ar7/ar7.h>
1750 +
1751 +enum yamon_memtypes {
1752 + yamon_dontuse,
1753 + yamon_prom,
1754 + yamon_free,
1755 +};
1756 +struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
1757 +
1758 +/* References to section boundaries */
1759 +extern char _end;
1760 +
1761 +#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
1762 +
1763 +
1764 +struct prom_pmemblock * __init prom_getmdesc(void)
1765 +{
1766 + char *memsize_str;
1767 + unsigned int memsize;
1768 +
1769 + memsize_str = prom_getenv("memsize");
1770 + if (!memsize_str) {
1771 + memsize = 0x02000000;
1772 + } else {
1773 + memsize = simple_strtol(memsize_str, NULL, 0);
1774 + }
1775 +
1776 + memset(mdesc, 0, sizeof(mdesc));
1777 +
1778 + mdesc[0].type = yamon_dontuse;
1779 + mdesc[0].base = 0x00000000;
1780 + mdesc[0].size = CONFIG_AR7_MEMORY;
1781 +
1782 + mdesc[1].type = yamon_prom;
1783 + mdesc[1].base = CONFIG_AR7_MEMORY;
1784 + mdesc[1].size = 0x00020000;
1785 +
1786 + mdesc[2].type = yamon_free;
1787 + mdesc[2].base = CONFIG_AR7_MEMORY + 0x00020000;
1788 + mdesc[2].size = (memsize + CONFIG_AR7_MEMORY) - mdesc[2].base;
1789 +
1790 + return &mdesc[0];
1791 +}
1792 +
1793 +static int __init prom_memtype_classify (unsigned int type)
1794 +{
1795 + switch (type) {
1796 + case yamon_free:
1797 + return BOOT_MEM_RAM;
1798 + case yamon_prom:
1799 + return BOOT_MEM_ROM_DATA;
1800 + default:
1801 + return BOOT_MEM_RESERVED;
1802 + }
1803 +}
1804 +
1805 +void __init prom_meminit(void)
1806 +{
1807 + struct prom_pmemblock *p;
1808 +
1809 + p = prom_getmdesc();
1810 +
1811 + while (p->size) {
1812 + long type;
1813 + unsigned long base, size;
1814 +
1815 + type = prom_memtype_classify (p->type);
1816 + base = p->base;
1817 + size = p->size;
1818 +
1819 + add_memory_region(base, size, type);
1820 + p++;
1821 + }
1822 +}
1823 +
1824 +void __init prom_free_prom_memory (void)
1825 +{
1826 + int i;
1827 + unsigned long freed = 0;
1828 + unsigned long addr;
1829 +
1830 + for (i = 0; i < boot_mem_map.nr_map; i++) {
1831 + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
1832 + continue;
1833 +
1834 + addr = boot_mem_map.map[i].addr;
1835 + while (addr < boot_mem_map.map[i].addr
1836 + + boot_mem_map.map[i].size) {
1837 + ClearPageReserved(virt_to_page(__va(addr)));
1838 + set_page_count(virt_to_page(__va(addr)), 1);
1839 + free_page((unsigned long)__va(addr));
1840 + addr += PAGE_SIZE;
1841 + freed += PAGE_SIZE;
1842 + }
1843 + }
1844 + printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
1845 +}
1846 diff -urN linux.old/arch/mips/ar7/mipsIRQ.S linux.dev/arch/mips/ar7/mipsIRQ.S
1847 --- linux.old/arch/mips/ar7/mipsIRQ.S 1970-01-01 01:00:00.000000000 +0100
1848 +++ linux.dev/arch/mips/ar7/mipsIRQ.S 2005-07-12 02:59:26.191668680 +0200
1849 @@ -0,0 +1,120 @@
1850 +/*
1851 + * Carsten Langgaard, carstenl@mips.com
1852 + * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
1853 + *
1854 + * ########################################################################
1855 + *
1856 + * This program is free software; you can distribute it and/or modify it
1857 + * under the terms of the GNU General Public License (Version 2) as
1858 + * published by the Free Software Foundation.
1859 + *
1860 + * This program is distributed in the hope it will be useful, but WITHOUT
1861 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1862 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1863 + * for more details.
1864 + *
1865 + * You should have received a copy of the GNU General Public License along
1866 + * with this program; if not, write to the Free Software Foundation, Inc.,
1867 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1868 + *
1869 + * ########################################################################
1870 + *
1871 + * Interrupt exception dispatch code.
1872 + *
1873 + */
1874 +#include <linux/config.h>
1875 +
1876 +#include <asm/asm.h>
1877 +#include <asm/mipsregs.h>
1878 +#include <asm/regdef.h>
1879 +#include <asm/stackframe.h>
1880 +
1881 +/* A lot of complication here is taken away because:
1882 + *
1883 + * 1) We handle one interrupt and return, sitting in a loop and moving across
1884 + * all the pending IRQ bits in the cause register is _NOT_ the answer, the
1885 + * common case is one pending IRQ so optimize in that direction.
1886 + *
1887 + * 2) We need not check against bits in the status register IRQ mask, that
1888 + * would make this routine slow as hell.
1889 + *
1890 + * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
1891 + * between like BSD spl() brain-damage.
1892 + *
1893 + * Furthermore, the IRQs on the MIPS board look basically (barring software
1894 + * IRQs which we don't use at all and all external interrupt sources are
1895 + * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
1896 + *
1897 + * MIPS IRQ Source
1898 + * -------- ------
1899 + * 0 Software (ignored)
1900 + * 1 Software (ignored)
1901 + * 2 Combined hardware interrupt (hw0)
1902 + * 3 Hardware (ignored)
1903 + * 4 Hardware (ignored)
1904 + * 5 Hardware (ignored)
1905 + * 6 Hardware (ignored)
1906 + * 7 R4k timer (what we use)
1907 + *
1908 + * Note: On the SEAD board thing are a little bit different.
1909 + * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
1910 + * wired to UART1.
1911 + *
1912 + * We handle the IRQ according to _our_ priority which is:
1913 + *
1914 + * Highest ---- R4k Timer
1915 + * Lowest ---- Combined hardware interrupt
1916 + *
1917 + * then we just return, if multiple IRQs are pending then we will just take
1918 + * another exception, big deal.
1919 + */
1920 +
1921 +.text
1922 +.set noreorder
1923 +.set noat
1924 + .align 5
1925 +NESTED(mipsIRQ, PT_SIZE, sp)
1926 + SAVE_ALL
1927 + CLI
1928 + .set at
1929 +
1930 + mfc0 s0, CP0_CAUSE # get irq bits
1931 +
1932 + /* First we check for r4k counter/timer IRQ. */
1933 + andi a0, s0, CAUSEF_IP7
1934 + beq a0, zero, 1f
1935 + andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt
1936 +
1937 + /* Wheee, a timer interrupt. */
1938 + move a0, sp
1939 + jal ar7_timer_interrupt
1940 + nop
1941 +
1942 + j ret_from_irq
1943 + nop
1944 +
1945 + 1:
1946 + beq a0, zero, 1f # delay slot, check hw3 interrupt
1947 + nop
1948 +
1949 + /* Wheee, combined hardware level zero interrupt. */
1950 + jal avalanche_hw0_irqdispatch
1951 + move a0, sp # delay slot
1952 +
1953 + j ret_from_irq
1954 + nop # delay slot
1955 +
1956 + 1:
1957 + /*
1958 + * Here by mistake? This is possible, what can happen is that by the
1959 + * time we take the exception the IRQ pin goes low, so just leave if
1960 + * this is the case.
1961 + */
1962 + move a1,s0
1963 + PRINT("Got interrupt: c0_cause = %08x\n")
1964 + mfc0 a1, CP0_EPC
1965 + PRINT("c0_epc = %08x\n")
1966 +
1967 + j ret_from_irq
1968 + nop
1969 +END(mipsIRQ)
1970 diff -urN linux.old/arch/mips/ar7/printf.c linux.dev/arch/mips/ar7/printf.c
1971 --- linux.old/arch/mips/ar7/printf.c 1970-01-01 01:00:00.000000000 +0100
1972 +++ linux.dev/arch/mips/ar7/printf.c 2005-07-12 02:59:26.191668680 +0200
1973 @@ -0,0 +1,54 @@
1974 +/*
1975 + * Carsten Langgaard, carstenl@mips.com
1976 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1977 + *
1978 + * This program is free software; you can distribute it and/or modify it
1979 + * under the terms of the GNU General Public License (Version 2) as
1980 + * published by the Free Software Foundation.
1981 + *
1982 + * This program is distributed in the hope it will be useful, but WITHOUT
1983 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1984 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1985 + * for more details.
1986 + *
1987 + * You should have received a copy of the GNU General Public License along
1988 + * with this program; if not, write to the Free Software Foundation, Inc.,
1989 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1990 + *
1991 + * Putting things on the screen/serial line using Adam2 facilities.
1992 + */
1993 +
1994 +#include <linux/config.h>
1995 +#include <linux/init.h>
1996 +#include <linux/kernel.h>
1997 +#include <linux/serial_reg.h>
1998 +#include <linux/spinlock.h>
1999 +#include <asm/io.h>
2000 +#include <asm/serial.h>
2001 +#include <asm/addrspace.h>
2002 +#include <asm/ar7/ar7.h>
2003 +
2004 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
2005 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
2006 +
2007 +static char ppbuf[1024];
2008 +
2009 +void (*prom_print_str)(unsigned int out, char *s, int len);
2010 +
2011 +void prom_printf(char *fmt, ...) __init;
2012 +void prom_printf(char *fmt, ...)
2013 +{
2014 + va_list args;
2015 + int len;
2016 + prom_print_str = (void *)*(unsigned int *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR;
2017 +
2018 + va_start(args, fmt);
2019 + vsprintf(ppbuf, fmt, args);
2020 + len = strlen(ppbuf);
2021 +
2022 + prom_print_str(1, ppbuf, len);
2023 +
2024 + va_end(args);
2025 + return;
2026 +
2027 +}
2028 diff -urN linux.old/arch/mips/ar7/reset.c linux.dev/arch/mips/ar7/reset.c
2029 --- linux.old/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
2030 +++ linux.dev/arch/mips/ar7/reset.c 2005-07-12 02:59:26.191668680 +0200
2031 @@ -0,0 +1,54 @@
2032 +/*
2033 + * Carsten Langgaard, carstenl@mips.com
2034 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
2035 + *
2036 + * ########################################################################
2037 + *
2038 + * This program is free software; you can distribute it and/or modify it
2039 + * under the terms of the GNU General Public License (Version 2) as
2040 + * published by the Free Software Foundation.
2041 + *
2042 + * This program is distributed in the hope it will be useful, but WITHOUT
2043 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2044 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2045 + * for more details.
2046 + *
2047 + * You should have received a copy of the GNU General Public License along
2048 + * with this program; if not, write to the Free Software Foundation, Inc.,
2049 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2050 + *
2051 + * ########################################################################
2052 + *
2053 + * Reset the MIPS boards.
2054 + *
2055 + */
2056 +#include <linux/config.h>
2057 +
2058 +#include <asm/reboot.h>
2059 +#include <asm/mips-boards/generic.h>
2060 +
2061 +static void ar7_machine_restart(char *command);
2062 +static void ar7_machine_halt(void);
2063 +static void ar7_machine_power_off(void);
2064 +
2065 +static void ar7_machine_restart(char *command)
2066 +{
2067 +
2068 +}
2069 +
2070 +static void ar7_machine_halt(void)
2071 +{
2072 +
2073 +}
2074 +
2075 +static void ar7_machine_power_off(void)
2076 +{
2077 +
2078 +}
2079 +
2080 +void ar7_reboot_setup(void)
2081 +{
2082 + _machine_restart = ar7_machine_restart;
2083 + _machine_halt = ar7_machine_halt;
2084 + _machine_power_off = ar7_machine_power_off;
2085 +}
2086 diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c
2087 --- linux.old/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
2088 +++ linux.dev/arch/mips/ar7/setup.c 2005-07-12 02:59:26.191668680 +0200
2089 @@ -0,0 +1,120 @@
2090 +/*
2091 + * Carsten Langgaard, carstenl@mips.com
2092 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
2093 + *
2094 + * This program is free software; you can distribute it and/or modify it
2095 + * under the terms of the GNU General Public License (Version 2) as
2096 + * published by the Free Software Foundation.
2097 + *
2098 + * This program is distributed in the hope it will be useful, but WITHOUT
2099 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2100 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2101 + * for more details.
2102 + *
2103 + * You should have received a copy of the GNU General Public License along
2104 + * with this program; if not, write to the Free Software Foundation, Inc.,
2105 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2106 + */
2107 +#include <linux/config.h>
2108 +#include <linux/init.h>
2109 +#include <linux/sched.h>
2110 +#include <linux/mc146818rtc.h>
2111 +#include <linux/ioport.h>
2112 +
2113 +#include <asm/cpu.h>
2114 +#include <asm/bootinfo.h>
2115 +#include <asm/irq.h>
2116 +#include <asm/mips-boards/generic.h>
2117 +#include <asm/mips-boards/prom.h>
2118 +
2119 +#include <asm/dma.h>
2120 +#include <asm/time.h>
2121 +#include <asm/traps.h>
2122 +
2123 +#ifdef CONFIG_KGDB
2124 +extern void rs_kgdb_hook(int);
2125 +int remote_debug = 0;
2126 +#endif
2127 +
2128 +extern struct rtc_ops no_rtc_ops;
2129 +
2130 +extern void ar7_reboot_setup(void);
2131 +
2132 +extern void ar7_time_init(void);
2133 +extern void ar7_timer_setup(struct irqaction *irq);
2134 +
2135 +const char *get_system_type(void)
2136 +{
2137 + return "Texas Instruments AR7";
2138 +}
2139 +
2140 +void __init ar7_setup(void)
2141 +{
2142 +#ifdef CONFIG_KGDB
2143 + int rs_putDebugChar(char);
2144 + char rs_getDebugChar(void);
2145 + extern int (*generic_putDebugChar)(char);
2146 + extern char (*generic_getDebugChar)(void);
2147 +#endif
2148 + char *argptr;
2149 +#ifdef CONFIG_SERIAL_CONSOLE
2150 + argptr = prom_getcmdline();
2151 + if ((argptr = strstr(argptr, "console=")) == NULL) {
2152 + char console[20];
2153 + char *s;
2154 + int i = 0;
2155 +
2156 + s = prom_getenv("modetty0");
2157 + strcpy(console, "38400");
2158 +
2159 + if (s != NULL) {
2160 + while (s[i] >= '0' && s[i] <= '9')
2161 + i++;
2162 +
2163 + if (i > 0) {
2164 + strncpy(console, s, i);
2165 + console[i] = 0;
2166 + }
2167 + }
2168 +
2169 + argptr = prom_getcmdline();
2170 + strcat(argptr, " console=ttyS0,");
2171 + strcat(argptr, console);
2172 + }
2173 +#endif
2174 +
2175 +#ifdef CONFIG_KGDB
2176 + argptr = prom_getcmdline();
2177 + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
2178 + int line;
2179 + argptr += strlen("kgdb=ttyS");
2180 + if (*argptr != '0' && *argptr != '1')
2181 + printk("KGDB: Uknown serial line /dev/ttyS%c, "
2182 + "falling back to /dev/ttyS1\n", *argptr);
2183 + line = *argptr == '0' ? 0 : 1;
2184 + printk("KGDB: Using serial line /dev/ttyS%d for session\n",
2185 + line ? 1 : 0);
2186 +
2187 + rs_kgdb_hook(line);
2188 + generic_putDebugChar = rs_putDebugChar;
2189 + generic_getDebugChar = rs_getDebugChar;
2190 +
2191 + prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
2192 + "please connect your debugger\n", line ? 1 : 0);
2193 +
2194 + remote_debug = 1;
2195 + /* Breakpoints are in init_IRQ() */
2196 + }
2197 +#endif
2198 +
2199 + argptr = prom_getcmdline();
2200 + if ((argptr = strstr(argptr, "nofpu")) != NULL)
2201 + cpu_data[0].options &= ~MIPS_CPU_FPU;
2202 +
2203 + rtc_ops = &no_rtc_ops;
2204 +
2205 + ar7_reboot_setup();
2206 +
2207 + board_time_init = ar7_time_init;
2208 + board_timer_setup = ar7_timer_setup;
2209 +}
2210 diff -urN linux.old/arch/mips/ar7/time.c linux.dev/arch/mips/ar7/time.c
2211 --- linux.old/arch/mips/ar7/time.c 1970-01-01 01:00:00.000000000 +0100
2212 +++ linux.dev/arch/mips/ar7/time.c 2005-07-12 02:59:26.192668528 +0200
2213 @@ -0,0 +1,125 @@
2214 +/*
2215 + * Carsten Langgaard, carstenl@mips.com
2216 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
2217 + *
2218 + * ########################################################################
2219 + *
2220 + * This program is free software; you can distribute it and/or modify it
2221 + * under the terms of the GNU General Public License (Version 2) as
2222 + * published by the Free Software Foundation.
2223 + *
2224 + * This program is distributed in the hope it will be useful, but WITHOUT
2225 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2226 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2227 + * for more details.
2228 + *
2229 + * You should have received a copy of the GNU General Public License along
2230 + * with this program; if not, write to the Free Software Foundation, Inc.,
2231 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2232 + *
2233 + * ########################################################################
2234 + *
2235 + * Setting up the clock on the MIPS boards.
2236 + *
2237 + */
2238 +
2239 +#include <linux/types.h>
2240 +#include <linux/config.h>
2241 +#include <linux/init.h>
2242 +#include <linux/kernel_stat.h>
2243 +#include <linux/sched.h>
2244 +#include <linux/spinlock.h>
2245 +
2246 +#include <asm/mipsregs.h>
2247 +#include <asm/ptrace.h>
2248 +#include <asm/hardirq.h>
2249 +#include <asm/div64.h>
2250 +
2251 +#include <linux/interrupt.h>
2252 +#include <linux/mc146818rtc.h>
2253 +#include <linux/timex.h>
2254 +
2255 +#include <asm/mips-boards/generic.h>
2256 +#include <asm/mips-boards/prom.h>
2257 +#include <asm/ar7/ar7.h>
2258 +
2259 +extern asmlinkage void mipsIRQ(void);
2260 +
2261 +static unsigned long r4k_offset; /* Amount to increment compare reg each time */
2262 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
2263 +
2264 +#define MIPS_CPU_TIMER_IRQ 7
2265 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
2266 +
2267 +static inline void ack_r4ktimer(unsigned long newval)
2268 +{
2269 + write_c0_compare(newval);
2270 +}
2271 +
2272 +void ar7_timer_interrupt(struct pt_regs *regs)
2273 +{
2274 + int cpu = smp_processor_id();
2275 +
2276 + irq_enter(cpu, MIPS_CPU_TIMER_IRQ);
2277 +
2278 + if (r4k_offset == 0)
2279 + goto null;
2280 +
2281 + do {
2282 + kstat.irqs[cpu][MIPS_CPU_TIMER_IRQ]++;
2283 + do_timer(regs);
2284 + r4k_cur += r4k_offset;
2285 + ack_r4ktimer(r4k_cur);
2286 +
2287 + } while (((unsigned long)read_c0_count()
2288 + - r4k_cur) < 0x7fffffff);
2289 +
2290 + irq_exit(cpu, MIPS_CPU_TIMER_IRQ);
2291 +
2292 + if (softirq_pending(cpu))
2293 + do_softirq();
2294 +
2295 + return;
2296 +
2297 +null:
2298 + ack_r4ktimer(0);
2299 +}
2300 +
2301 +/*
2302 + * Figure out the r4k offset, the amount to increment the compare
2303 + * register for each time tick.
2304 + */
2305 +static unsigned long __init cal_r4koff(void)
2306 +{
2307 + return ((CONFIG_AR7_CPU_FREQUENCY*500000)/HZ);
2308 +}
2309 +
2310 +void __init ar7_time_init(void)
2311 +{
2312 + unsigned long flags;
2313 + unsigned int est_freq;
2314 +
2315 + set_except_vector(0, mipsIRQ);
2316 + write_c0_count(0);
2317 +
2318 + printk("calculating r4koff... ");
2319 + r4k_offset = cal_r4koff();
2320 + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
2321 +
2322 + est_freq = 2*r4k_offset*HZ;
2323 + est_freq += 5000; /* round */
2324 + est_freq -= est_freq%10000;
2325 + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
2326 + (est_freq%1000000)*100/1000000);
2327 +}
2328 +
2329 +void __init ar7_timer_setup(struct irqaction *irq)
2330 +{
2331 + /* we are using the cpu counter for timer interrupts */
2332 + irq->handler = no_action; /* we use our own handler */
2333 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
2334 +
2335 + r4k_cur = (read_c0_count() + r4k_offset);
2336 + write_c0_compare(r4k_cur);
2337 + set_c0_status(ALLINTS);
2338 +}
2339 diff -urN linux.old/arch/mips/ar7/tnetd73xx_misc.c linux.dev/arch/mips/ar7/tnetd73xx_misc.c
2340 --- linux.old/arch/mips/ar7/tnetd73xx_misc.c 1970-01-01 01:00:00.000000000 +0100
2341 +++ linux.dev/arch/mips/ar7/tnetd73xx_misc.c 2005-07-12 02:59:43.731002296 +0200
2342 @@ -0,0 +1,924 @@
2343 +/******************************************************************************
2344 + * FILE PURPOSE: TNETD73xx Misc modules API Source
2345 + ******************************************************************************
2346 + * FILE NAME: tnetd73xx_misc.c
2347 + *
2348 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
2349 + * FSER Modules API
2350 + * As per TNETD73xx specifications
2351 + *
2352 + * REVISION HISTORY:
2353 + * 27 Nov 02 - Sharath Kumar PSP TII
2354 + * 14 Feb 03 - Anant Gole PSP TII
2355 + *
2356 + * (C) Copyright 2002, Texas Instruments, Inc
2357 + *******************************************************************************/
2358 +
2359 +#define LITTLE_ENDIAN
2360 +#define _LINK_KSEG0_
2361 +
2362 +#include <linux/types.h>
2363 +#include <asm/ar7/tnetd73xx.h>
2364 +#include <asm/ar7/tnetd73xx_misc.h>
2365 +
2366 +/* TNETD73XX Revision */
2367 +u32 tnetd73xx_get_revision(void)
2368 +{
2369 + /* Read Chip revision register - This register is from GPIO module */
2370 + return ( (u32) REG32_DATA(TNETD73XX_CVR));
2371 +}
2372 +
2373 +/*****************************************************************************
2374 + * Reset Control Module
2375 + *****************************************************************************/
2376 +
2377 +
2378 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
2379 +{
2380 + u32 reset_status;
2381 +
2382 + /* read current reset register */
2383 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2384 +
2385 + if (reset_ctrl == OUT_OF_RESET)
2386 + {
2387 + /* bring module out of reset */
2388 + reset_status |= (1 << reset_module);
2389 + }
2390 + else
2391 + {
2392 + /* put module in reset */
2393 + reset_status &= (~(1 << reset_module));
2394 + }
2395 +
2396 + /* write to the reset register */
2397 + REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
2398 +}
2399 +
2400 +
2401 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
2402 +{
2403 + u32 reset_status;
2404 +
2405 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2406 + return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
2407 +}
2408 +
2409 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
2410 +{
2411 + REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
2412 +}
2413 +
2414 +#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
2415 +
2416 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
2417 +{
2418 + u32 sys_reset_status;
2419 +
2420 + REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
2421 +
2422 + return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
2423 +}
2424 +
2425 +
2426 +/*****************************************************************************
2427 + * Power Control Module
2428 + *****************************************************************************/
2429 +#define TNETD73XX_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
2430 +#define TNETD73XX_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
2431 +
2432 +
2433 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
2434 +{
2435 + u32 power_status;
2436 +
2437 + /* read current power down control register */
2438 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2439 +
2440 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
2441 + {
2442 + /* power down the module */
2443 + power_status |= (1 << power_module);
2444 + }
2445 + else
2446 + {
2447 + /* power on the module */
2448 + power_status &= (~(1 << power_module));
2449 + }
2450 +
2451 + /* write to the reset register */
2452 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2453 +}
2454 +
2455 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
2456 +{
2457 + u32 power_status;
2458 +
2459 + /* read current power down control register */
2460 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2461 +
2462 + return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
2463 +}
2464 +
2465 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
2466 +{
2467 + u32 power_status;
2468 +
2469 + /* read current power down control register */
2470 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2471 +
2472 + power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
2473 + power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2474 +
2475 + /* write to power down control register */
2476 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2477 +}
2478 +
2479 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
2480 +{
2481 + u32 power_status;
2482 +
2483 + /* read current power down control register */
2484 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2485 +
2486 + power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
2487 + power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2488 +
2489 + return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
2490 +}
2491 +
2492 +
2493 +/*****************************************************************************
2494 + * Wakeup Control
2495 + *****************************************************************************/
2496 +
2497 +#define TNETD73XX_WAKEUP_POLARITY_BIT 16
2498 +
2499 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
2500 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
2501 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
2502 +{
2503 + u32 wakeup_status;
2504 +
2505 + /* read the wakeup control register */
2506 + REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2507 +
2508 + /* enable/disable */
2509 + if (wakeup_ctrl == WAKEUP_ENABLED)
2510 + {
2511 + /* enable wakeup */
2512 + wakeup_status |= wakeup_int;
2513 + }
2514 + else
2515 + {
2516 + /* disable wakeup */
2517 + wakeup_status &= (~wakeup_int);
2518 + }
2519 +
2520 + /* set polarity */
2521 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
2522 + {
2523 + wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2524 + }
2525 + else
2526 + {
2527 + wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2528 + }
2529 +
2530 + /* write the wakeup control register */
2531 + REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2532 +}
2533 +
2534 +
2535 +/*****************************************************************************
2536 + * FSER Control
2537 + *****************************************************************************/
2538 +
2539 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
2540 +{
2541 + REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
2542 +}
2543 +
2544 +/*****************************************************************************
2545 + * Clock Control
2546 + *****************************************************************************/
2547 +
2548 +#define MIN(x,y) ( ((x) < (y)) ? (x) : (y) )
2549 +#define MAX(x,y) ( ((x) > (y)) ? (x) : (y) )
2550 +#define ABS(x) ( ((signed)(x) > 0) ? (x) : (-(x)) )
2551 +#define CEIL(x,y) ( ((x) + (y) / 2) / (y) )
2552 +
2553 +#define CLKC_CLKCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
2554 +#define CLKC_CLKPLLCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
2555 +
2556 +#define CLKC_PRE_DIVIDER 0x0000001F
2557 +#define CLKC_POST_DIVIDER 0x001F0000
2558 +
2559 +#define CLKC_PLL_STATUS 0x1
2560 +#define CLKC_PLL_FACTOR 0x0000F000
2561 +
2562 +#define BOOTCR_PLL_BYPASS (1 << 5)
2563 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
2564 +
2565 +#define MIPS_PLL_SELECT 0x00030000
2566 +#define SYSTEM_PLL_SELECT 0x0000C000
2567 +#define USB_PLL_SELECT 0x000C0000
2568 +#define ADSLSS_PLL_SELECT 0x00C00000
2569 +
2570 +#define MIPS_AFECLKI_SELECT 0x00000000
2571 +#define MIPS_REFCLKI_SELECT 0x00010000
2572 +#define MIPS_XTAL3IN_SELECT 0x00020000
2573 +
2574 +#define SYSTEM_AFECLKI_SELECT 0x00000000
2575 +#define SYSTEM_REFCLKI_SELECT 0x00004000
2576 +#define SYSTEM_XTAL3IN_SELECT 0x00008000
2577 +#define SYSTEM_MIPSPLL_SELECT 0x0000C000
2578 +
2579 +#define USB_SYSPLL_SELECT 0x00000000
2580 +#define USB_REFCLKI_SELECT 0x00040000
2581 +#define USB_XTAL3IN_SELECT 0x00080000
2582 +#define USB_MIPSPLL_SELECT 0x000C0000
2583 +
2584 +#define ADSLSS_AFECLKI_SELECT 0x00000000
2585 +#define ADSLSS_REFCLKI_SELECT 0x00400000
2586 +#define ADSLSS_XTAL3IN_SELECT 0x00800000
2587 +#define ADSLSS_MIPSPLL_SELECT 0x00C00000
2588 +
2589 +#define SYS_MAX CLK_MHZ(150)
2590 +#define SYS_MIN CLK_MHZ(1)
2591 +
2592 +#define MIPS_SYNC_MAX SYS_MAX
2593 +#define MIPS_ASYNC_MAX CLK_MHZ(160)
2594 +#define MIPS_MIN CLK_MHZ(1)
2595 +
2596 +#define USB_MAX CLK_MHZ(100)
2597 +#define USB_MIN CLK_MHZ(1)
2598 +
2599 +#define ADSL_MAX CLK_MHZ(180)
2600 +#define ADSL_MIN CLK_MHZ(1)
2601 +
2602 +#define PLL_MUL_MAXFACTOR 15
2603 +#define MAX_DIV_VALUE 32
2604 +#define MIN_DIV_VALUE 1
2605 +
2606 +#define MIN_PLL_INP_FREQ CLK_MHZ(8)
2607 +#define MAX_PLL_INP_FREQ CLK_MHZ(100)
2608 +
2609 +#define DIVIDER_LOCK_TIME 10100
2610 +#define PLL_LOCK_TIME 10100 * 75
2611 +
2612 +
2613 +
2614 + /****************************************************************************
2615 + * DATA PURPOSE: PRIVATE Variables
2616 + **************************************************************************/
2617 + static u32 *clk_src[4];
2618 + static u32 mips_pll_out;
2619 + static u32 sys_pll_out;
2620 + static u32 afeclk_inp;
2621 + static u32 refclk_inp;
2622 + static u32 xtal_inp;
2623 + static u32 present_min;
2624 + static u32 present_max;
2625 +
2626 + /* Forward References */
2627 + static u32 find_gcd(u32 min, u32 max);
2628 + static u32 compute_prediv( u32 divider, u32 min, u32 max);
2629 + static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
2630 + static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
2631 + static void find_approx(u32 *,u32 *,u32);
2632 +
2633 + /****************************************************************************
2634 + * FUNCTION: tnetd73xx_clkc_init
2635 + ****************************************************************************
2636 + * Description: The routine initializes the internal variables depending on
2637 + * on the sources selected for different clocks.
2638 + ***************************************************************************/
2639 +void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in)
2640 +{
2641 +
2642 + u32 choice;
2643 +
2644 + afeclk_inp = afeclk;
2645 + refclk_inp = refclk;
2646 + xtal_inp = xtal3in;
2647 +
2648 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
2649 + switch(choice)
2650 + {
2651 + case MIPS_AFECLKI_SELECT:
2652 + clk_src[CLKC_MIPS] = &afeclk_inp;
2653 + break;
2654 +
2655 + case MIPS_REFCLKI_SELECT:
2656 + clk_src[CLKC_MIPS] = &refclk_inp;
2657 + break;
2658 +
2659 + case MIPS_XTAL3IN_SELECT:
2660 + clk_src[CLKC_MIPS] = &xtal_inp;
2661 + break;
2662 +
2663 + default :
2664 + clk_src[CLKC_MIPS] = 0;
2665 +
2666 + }
2667 +
2668 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
2669 + switch(choice)
2670 + {
2671 + case SYSTEM_AFECLKI_SELECT:
2672 + clk_src[CLKC_SYS] = &afeclk_inp;
2673 + break;
2674 +
2675 + case SYSTEM_REFCLKI_SELECT:
2676 + clk_src[CLKC_SYS] = &refclk_inp;
2677 + break;
2678 +
2679 + case SYSTEM_XTAL3IN_SELECT:
2680 + clk_src[CLKC_SYS] = &xtal_inp;
2681 + break;
2682 +
2683 + case SYSTEM_MIPSPLL_SELECT:
2684 + clk_src[CLKC_SYS] = &mips_pll_out;
2685 + break;
2686 +
2687 + default :
2688 + clk_src[CLKC_SYS] = 0;
2689 +
2690 + }
2691 +
2692 +
2693 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
2694 + switch(choice)
2695 + {
2696 + case ADSLSS_AFECLKI_SELECT:
2697 + clk_src[CLKC_ADSLSS] = &afeclk_inp;
2698 + break;
2699 +
2700 + case ADSLSS_REFCLKI_SELECT:
2701 + clk_src[CLKC_ADSLSS] = &refclk_inp;
2702 + break;
2703 +
2704 + case ADSLSS_XTAL3IN_SELECT:
2705 + clk_src[CLKC_ADSLSS] = &xtal_inp;
2706 + break;
2707 +
2708 + case ADSLSS_MIPSPLL_SELECT:
2709 + clk_src[CLKC_ADSLSS] = &mips_pll_out;
2710 + break;
2711 +
2712 + default :
2713 + clk_src[CLKC_ADSLSS] = 0;
2714 +
2715 + }
2716 +
2717 +
2718 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
2719 + switch(choice)
2720 + {
2721 + case USB_SYSPLL_SELECT:
2722 + clk_src[CLKC_USB] = &sys_pll_out ;
2723 + break;
2724 +
2725 + case USB_REFCLKI_SELECT:
2726 + clk_src[CLKC_USB] = &refclk_inp;
2727 + break;
2728 +
2729 + case USB_XTAL3IN_SELECT:
2730 + clk_src[CLKC_USB] = &xtal_inp;
2731 + break;
2732 +
2733 + case USB_MIPSPLL_SELECT:
2734 + clk_src[CLKC_USB] = &mips_pll_out;
2735 + break;
2736 +
2737 + default :
2738 + clk_src[CLKC_USB] = 0;
2739 +
2740 + }
2741 +}
2742 +
2743 +
2744 +
2745 +/****************************************************************************
2746 + * FUNCTION: tnetd73xx_clkc_set_freq
2747 + ****************************************************************************
2748 + * Description: The above routine is called to set the output_frequency of the
2749 + * selected clock(using clk_id) to the required value given
2750 + * by the variable output_freq.
2751 + ***************************************************************************/
2752 +TNETD73XX_ERR tnetd73xx_clkc_set_freq
2753 +(
2754 + TNETD73XX_CLKC_ID_T clk_id,
2755 + u32 output_freq
2756 + )
2757 +{
2758 + u32 base_freq;
2759 + u32 multiplier;
2760 + u32 divider;
2761 + u32 min_prediv;
2762 + u32 max_prediv;
2763 + u32 prediv;
2764 + u32 postdiv;
2765 + u32 temp;
2766 +
2767 + /* check if PLLs are bypassed*/
2768 + if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
2769 + {
2770 + return TNETD73XX_ERR_ERROR;
2771 + }
2772 +
2773 + /*check if the requested output_frequency is in valid range*/
2774 + switch( clk_id )
2775 + {
2776 + case CLKC_SYS:
2777 + if( output_freq < SYS_MIN || output_freq > SYS_MAX)
2778 + {
2779 + return TNETD73XX_ERR_ERROR;
2780 + }
2781 + present_min = SYS_MIN;
2782 + present_max = SYS_MAX;
2783 + break;
2784 +
2785 + case CLKC_MIPS:
2786 + if((output_freq < MIPS_MIN) ||
2787 + (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
2788 + {
2789 + return TNETD73XX_ERR_ERROR;
2790 + }
2791 + present_min = MIPS_MIN;
2792 + present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
2793 + break;
2794 +
2795 + case CLKC_USB:
2796 + if( output_freq < USB_MIN || output_freq > USB_MAX)
2797 + {
2798 + return TNETD73XX_ERR_ERROR;
2799 + }
2800 + present_min = USB_MIN;
2801 + present_max = USB_MAX;
2802 + break;
2803 +
2804 + case CLKC_ADSLSS:
2805 + if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
2806 + {
2807 + return TNETD73XX_ERR_ERROR;
2808 + }
2809 + present_min = ADSL_MIN;
2810 + present_max = ADSL_MAX;
2811 + break;
2812 + }
2813 +
2814 +
2815 + base_freq = get_base_frequency(clk_id);
2816 +
2817 +
2818 + /* check for minimum base frequency value */
2819 + if( base_freq < MIN_PLL_INP_FREQ)
2820 + {
2821 + return TNETD73XX_ERR_ERROR;
2822 + }
2823 +
2824 + get_val(output_freq, base_freq, &multiplier, &divider);
2825 +
2826 + /* check multiplier range */
2827 + if( (multiplier > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
2828 + {
2829 + return TNETD73XX_ERR_ERROR;
2830 + }
2831 +
2832 + /* check divider value */
2833 + if( divider == 0 )
2834 + {
2835 + return TNETD73XX_ERR_ERROR;
2836 + }
2837 +
2838 + /*compute minimum and maximum predivider values */
2839 + min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
2840 + max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
2841 +
2842 + /*adjust the value of divider so that it not less than minimum predivider value*/
2843 + if (divider < min_prediv)
2844 + {
2845 + temp = CEIL(min_prediv, divider);
2846 + if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
2847 + {
2848 + return TNETD73XX_ERR_ERROR ;
2849 + }
2850 + else
2851 + {
2852 + multiplier = temp * multiplier;
2853 + divider = min_prediv;
2854 + }
2855 +
2856 + }
2857 +
2858 + /* compute predivider and postdivider values */
2859 + prediv = compute_prediv (divider, min_prediv, max_prediv);
2860 + postdiv = CEIL(divider,prediv);
2861 +
2862 + /*return fail if postdivider value falls out of range */
2863 + if(postdiv > MAX_DIV_VALUE)
2864 + {
2865 + return TNETD73XX_ERR_ERROR;
2866 + }
2867 +
2868 +
2869 + /*write predivider and postdivider values*/
2870 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2871 + REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
2872 +
2873 + /*wait for divider output to stabilise*/
2874 + for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
2875 +
2876 + /*write to PLL clock register*/
2877 +
2878 + if(clk_id == CLKC_SYS)
2879 + {
2880 + /* but before writing put DRAM to hold mode */
2881 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
2882 + }
2883 + /*Bring PLL into div mode */
2884 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
2885 +
2886 + /*compute the word to be written to PLLCR
2887 + *corresponding to multiplier value
2888 + */
2889 + multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
2890 +
2891 + /* wait till PLL enters div mode */
2892 + while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2893 + /*nothing*/;
2894 +
2895 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
2896 +
2897 + while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2898 + /*nothing*/;
2899 +
2900 +
2901 + /*wait for External pll to lock*/
2902 + for(temp =0; temp < PLL_LOCK_TIME; temp++);
2903 +
2904 + if(clk_id == CLKC_SYS)
2905 + {
2906 + /* Bring DRAM out of hold */
2907 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
2908 + }
2909 +
2910 + return TNETD73XX_ERR_OK ;
2911 +}
2912 +
2913 +/****************************************************************************
2914 + * FUNCTION: tnetd73xx_clkc_get_freq
2915 + ****************************************************************************
2916 + * Description: The above routine is called to get the output_frequency of the
2917 + * selected clock( clk_id)
2918 + ***************************************************************************/
2919 +u32 tnetd73xx_clkc_get_freq
2920 +(
2921 + TNETD73XX_CLKC_ID_T clk_id
2922 + )
2923 +{
2924 +
2925 + u32 clk_ctrl_register;
2926 + u32 clk_pll_setting;
2927 + u32 clk_predivider;
2928 + u32 clk_postdivider;
2929 + u16 pll_factor;
2930 + u32 base_freq;
2931 + u32 divider;
2932 +
2933 + base_freq = get_base_frequency(clk_id);
2934 +
2935 + clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
2936 +
2937 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2938 + clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
2939 + clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
2940 +
2941 + divider = clk_predivider * clk_postdivider;
2942 +
2943 +
2944 + if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
2945 + {
2946 + return (CEIL(base_freq, divider)); /* PLLs bypassed.*/
2947 + }
2948 +
2949 +
2950 + else
2951 + {
2952 + /* return the current clock speed based upon the PLL setting */
2953 + clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
2954 +
2955 + /* Get the PLL multiplication factor */
2956 + pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
2957 +
2958 + /* Check if we're in divide mode or multiply mode */
2959 + if((clk_pll_setting & 0x1) == 0)
2960 + {
2961 + /* We're in divide mode */
2962 + if(pll_factor < 0x10)
2963 + return (CEIL(base_freq >> 1, divider));
2964 + else
2965 + return (CEIL(base_freq >> 2, divider));
2966 + }
2967 +
2968 + else /* We're in PLL mode */
2969 + {
2970 + /* See if PLLNDIV & PLLDIV are set */
2971 + if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
2972 + {
2973 + if(clk_pll_setting & 0x1000)
2974 + {
2975 + /* clk = base_freq * k/2 */
2976 + return(CEIL((base_freq * pll_factor) >> 1, divider));
2977 + }
2978 + else
2979 + {
2980 + /* clk = base_freq * (k-1) / 4)*/
2981 + return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
2982 + }
2983 + }
2984 + else
2985 + {
2986 + if(pll_factor < 0x10)
2987 + {
2988 + /* clk = base_freq * k */
2989 + return(CEIL(base_freq * pll_factor, divider));
2990 + }
2991 +
2992 + else
2993 + {
2994 + /* clk = base_freq */
2995 + return(CEIL(base_freq, divider));
2996 + }
2997 + }
2998 + }
2999 + return(0); /* Should never reach here */
3000 +
3001 + }
3002 +
3003 +}
3004 +
3005 +
3006 +/* local helper functions */
3007 +
3008 +/****************************************************************************
3009 + * FUNCTION: get_base_frequency
3010 + ****************************************************************************
3011 + * Description: The above routine is called to get base frequency of the clocks.
3012 + ***************************************************************************/
3013 +
3014 +static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
3015 +{
3016 + /* update the current MIPs PLL output value, if the required
3017 + * source is MIPS PLL
3018 + */
3019 + if ( clk_src[clk_id] == &mips_pll_out)
3020 + {
3021 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
3022 + }
3023 +
3024 +
3025 + /* update the current System PLL output value, if the required
3026 + * source is system PLL
3027 + */
3028 + if ( clk_src[clk_id] == &sys_pll_out)
3029 + {
3030 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
3031 + }
3032 +
3033 + return (*clk_src[clk_id]);
3034 +
3035 +}
3036 +
3037 +
3038 +
3039 +/****************************************************************************
3040 + * FUNCTION: find_gcd
3041 + ****************************************************************************
3042 + * Description: The above routine is called to find gcd of 2 numbers.
3043 + ***************************************************************************/
3044 +static u32 find_gcd
3045 +(
3046 + u32 min,
3047 + u32 max
3048 + )
3049 +{
3050 + if (max % min == 0)
3051 + {
3052 + return min;
3053 + }
3054 + else
3055 + {
3056 + return find_gcd(max % min, min);
3057 + }
3058 +}
3059 +
3060 +/****************************************************************************
3061 + * FUNCTION: compute_prediv
3062 + ****************************************************************************
3063 + * Description: The above routine is called to compute predivider value
3064 + ***************************************************************************/
3065 +static u32 compute_prediv(u32 divider, u32 min, u32 max)
3066 +{
3067 + u16 prediv;
3068 +
3069 + /* return the divider itself it it falls within the range of predivider*/
3070 + if (min <= divider && divider <= max)
3071 + {
3072 + return divider;
3073 + }
3074 +
3075 + /* find a value for prediv such that it is a factor of divider */
3076 + for (prediv = max; prediv >= min ; prediv--)
3077 + {
3078 + if ( (divider % prediv) == 0 )
3079 + {
3080 + return prediv;
3081 + }
3082 + }
3083 +
3084 + /* No such factor exists, return min as prediv */
3085 + return min;
3086 +}
3087 +
3088 +/****************************************************************************
3089 + * FUNCTION: get_val
3090 + ****************************************************************************
3091 + * Description: This routine is called to get values of divider and multiplier.
3092 + ***************************************************************************/
3093 +
3094 +static void get_val(u32 output_freq, u32 base_freq,u32 *multiplier, u32 *divider)
3095 +{
3096 + u32 temp_mul;
3097 + u32 temp_div;
3098 + u32 gcd;
3099 + u32 min_freq;
3100 + u32 max_freq;
3101 +
3102 + /* find gcd of base_freq, output_freq */
3103 + min_freq = (base_freq < output_freq) ? base_freq : output_freq;
3104 + max_freq = (base_freq > output_freq) ? base_freq : output_freq;
3105 + gcd = find_gcd(min_freq , max_freq);
3106 +
3107 + if(gcd == 0)
3108 + return; /* ERROR */
3109 +
3110 + /* compute values of multiplier and divider */
3111 + temp_mul = output_freq / gcd;
3112 + temp_div = base_freq / gcd;
3113 +
3114 +
3115 + /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
3116 + if( temp_mul > PLL_MUL_MAXFACTOR )
3117 + {
3118 + if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
3119 + return;
3120 +
3121 + find_approx(&temp_mul,&temp_div,base_freq);
3122 + }
3123 +
3124 + *multiplier = temp_mul;
3125 + *divider = temp_div;
3126 +}
3127 +
3128 +/****************************************************************************
3129 + * FUNCTION: find_approx
3130 + ****************************************************************************
3131 + * Description: This function gets the approx value of num/denom.
3132 + ***************************************************************************/
3133 +
3134 +static void find_approx(u32 *num,u32 *denom,u32 base_freq)
3135 +{
3136 + u32 num1;
3137 + u32 denom1;
3138 + u32 num2;
3139 + u32 denom2;
3140 + int32_t closest;
3141 + int32_t prev_closest;
3142 + u32 temp_num;
3143 + u32 temp_denom;
3144 + u32 normalize;
3145 + u32 gcd;
3146 + u32 output_freq;
3147 +
3148 + num1 = *num;
3149 + denom1 = *denom;
3150 +
3151 + prev_closest = 0x7fffffff; /* maximum possible value */
3152 + num2 = num1;
3153 + denom2 = denom1;
3154 +
3155 + /* start with max */
3156 + for(temp_num = 15; temp_num >=1; temp_num--)
3157 + {
3158 +
3159 + temp_denom = CEIL(temp_num * denom1, num1);
3160 + output_freq = (temp_num * base_freq) / temp_denom;
3161 +
3162 + if(temp_denom < 1)
3163 + {
3164 + break;
3165 + }
3166 + else
3167 + {
3168 + normalize = CEIL(num1,temp_num);
3169 + closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1))) * normalize;
3170 + if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
3171 + {
3172 + prev_closest = closest;
3173 + num2 = temp_num;
3174 + denom2 = temp_denom;
3175 + }
3176 +
3177 + }
3178 +
3179 + }
3180 +
3181 + gcd = find_gcd(num2,denom2);
3182 + num2 = num2 / gcd;
3183 + denom2 = denom2 /gcd;
3184 +
3185 + *num = num2;
3186 + *denom = denom2;
3187 +}
3188 +
3189 +
3190 +/*****************************************************************************
3191 + * GPIO Control
3192 + *****************************************************************************/
3193 +
3194 +/****************************************************************************
3195 + * FUNCTION: tnetd73xx_gpio_init
3196 + ***************************************************************************/
3197 +void tnetd73xx_gpio_init()
3198 +{
3199 + /* Bring module out of reset */
3200 + tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
3201 + REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);
3202 +}
3203 +
3204 +/****************************************************************************
3205 + * FUNCTION: tnetd73xx_gpio_ctrl
3206 + ***************************************************************************/
3207 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
3208 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
3209 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
3210 +{
3211 + u32 pin_status;
3212 + REG32_READ(TNETD73XX_GPIOENR, pin_status);
3213 + if (pin_mode == GPIO_PIN)
3214 + {
3215 + pin_status |= (1 << gpio_pin);
3216 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
3217 +
3218 + /* Set pin direction */
3219 + REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
3220 + if (pin_direction == GPIO_INPUT_PIN)
3221 + {
3222 + pin_status |= (1 << gpio_pin);
3223 + }
3224 + else /* GPIO_OUTPUT_PIN */
3225 + {
3226 + pin_status &= (~(1 << gpio_pin));
3227 + }
3228 + REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
3229 + }
3230 + else /* FUNCTIONAL PIN */
3231 + {
3232 + pin_status &= (~(1 << gpio_pin));
3233 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
3234 + }
3235 +
3236 +}
3237 +
3238 +/****************************************************************************
3239 + * FUNCTION: tnetd73xx_gpio_out
3240 + ***************************************************************************/
3241 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
3242 +{
3243 + u32 pin_value;
3244 +
3245 + REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
3246 + if (value == 1)
3247 + {
3248 + pin_value |= (1 << gpio_pin);
3249 + }
3250 + else
3251 + {
3252 + pin_value &= (~(1 << gpio_pin));
3253 + }
3254 + REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
3255 +}
3256 +
3257 +/****************************************************************************
3258 + * FUNCTION: tnetd73xx_gpio_in
3259 + ***************************************************************************/
3260 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
3261 +{
3262 + u32 pin_value;
3263 + REG32_READ(TNETD73XX_GPIODINR, pin_value);
3264 + return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
3265 +}
3266 +
3267 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
3268 --- linux.old/arch/mips/config-shared.in 2005-07-10 03:00:44.784181376 +0200
3269 +++ linux.dev/arch/mips/config-shared.in 2005-07-12 02:59:26.192668528 +0200
3270 @@ -20,6 +20,16 @@
3271 mainmenu_option next_comment
3272 comment 'Machine selection'
3273 dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
3274 +dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
3275 +if [ "$CONFIG_AR7" = "y" ]; then
3276 + choice 'Texas Instruments Reference Platform' \
3277 + "AR7DB CONFIG_AR7DB \
3278 + AR7RD CONFIG_AR7RD \
3279 + AR7WRD CONFIG_AR7WRD" AR7DB
3280 + int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_CPU_FREQUENCY 150
3281 + int 'Texas Instruments AR7 System Frequency' CONFIG_AR7_SYS_FREQUENCY 125
3282 + hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
3283 +fi
3284 dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
3285 dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
3286 dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
3287 @@ -239,6 +249,11 @@
3288 define_bool CONFIG_NONCOHERENT_IO y
3289 define_bool CONFIG_PC_KEYB y
3290 fi
3291 +if [ "$CONFIG_AR7" = "y" ]; then
3292 + define_bool CONFIG_NONCOHERENT_IO y
3293 + define_bool CONFIG_SWAP_IO_SPACE y
3294 + define_bool CONFIG_AR7_PAGING y
3295 +fi
3296 if [ "$CONFIG_CASIO_E55" = "y" ]; then
3297 define_bool CONFIG_IRQ_CPU y
3298 define_bool CONFIG_NONCOHERENT_IO y
3299 @@ -736,6 +751,7 @@
3300 mainmenu_option next_comment
3301 comment 'General setup'
3302 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
3303 + "$CONFIG_AR7" = "y" -o \
3304 "$CONFIG_CASIO_E55" = "y" -o \
3305 "$CONFIG_DDB5074" = "y" -o \
3306 "$CONFIG_DDB5476" = "y" -o \
3307 @@ -797,6 +813,7 @@
3308 bool 'Networking support' CONFIG_NET
3309
3310 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
3311 + "$CONFIG_AR7" = "y" -o \
3312 "$CONFIG_CASIO_E55" = "y" -o \
3313 "$CONFIG_DECSTATION" = "y" -o \
3314 "$CONFIG_IBM_WORKPAD" = "y" -o \
3315 diff -urN linux.old/arch/mips/kernel/irq.c linux.dev/arch/mips/kernel/irq.c
3316 --- linux.old/arch/mips/kernel/irq.c 2005-07-10 03:00:44.784181376 +0200
3317 +++ linux.dev/arch/mips/kernel/irq.c 2005-07-12 02:59:26.193668376 +0200
3318 @@ -76,6 +76,7 @@
3319 * Generic, controller-independent functions:
3320 */
3321
3322 +#ifndef CONFIG_AR7
3323 int get_irq_list(char *buf)
3324 {
3325 int i, j;
3326 @@ -110,6 +111,7 @@
3327 p += sprintf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
3328 return p - buf;
3329 }
3330 +#endif
3331
3332 #ifdef CONFIG_SMP
3333 int global_irq_holder = NO_PROC_ID;
3334 @@ -525,6 +527,7 @@
3335 *
3336 */
3337
3338 +#ifndef CONFIG_AR7
3339 int request_irq(unsigned int irq,
3340 void (*handler)(int, void *, struct pt_regs *),
3341 unsigned long irqflags,
3342 @@ -569,6 +572,7 @@
3343 kfree(action);
3344 return retval;
3345 }
3346 +#endif
3347
3348 /**
3349 * free_irq - free an interrupt
3350 @@ -588,6 +592,7 @@
3351 * the machine.
3352 */
3353
3354 +#ifndef CONFIG_AR7
3355 void free_irq(unsigned int irq, void *dev_id)
3356 {
3357 irq_desc_t *desc;
3358 @@ -629,6 +634,7 @@
3359 return;
3360 }
3361 }
3362 +#endif
3363
3364 /*
3365 * IRQ autodetection code..
3366 diff -urN linux.old/arch/mips/kernel/mips_ksyms.c linux.dev/arch/mips/kernel/mips_ksyms.c
3367 --- linux.old/arch/mips/kernel/mips_ksyms.c 2004-02-18 14:36:30.000000000 +0100
3368 +++ linux.dev/arch/mips/kernel/mips_ksyms.c 2005-07-12 02:59:26.193668376 +0200
3369 @@ -40,6 +40,12 @@
3370 extern long __strnlen_user_nocheck_asm(const char *s);
3371 extern long __strnlen_user_asm(const char *s);
3372
3373 +#ifdef CONFIG_AR7
3374 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num, unsigned int pace_value);
3375 +char *prom_getenv(char *envname);
3376 +#endif
3377 +
3378 +
3379 EXPORT_SYMBOL(mips_machtype);
3380 #ifdef CONFIG_EISA
3381 EXPORT_SYMBOL(EISA_bus);
3382 @@ -103,3 +109,9 @@
3383 #endif
3384
3385 EXPORT_SYMBOL(get_wchan);
3386 +
3387 +#ifdef CONFIG_AR7
3388 +EXPORT_SYMBOL_NOVERS(avalanche_request_pacing);
3389 +EXPORT_SYMBOL_NOVERS(prom_getenv);
3390 +#endif
3391 +
3392 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
3393 --- linux.old/arch/mips/kernel/setup.c 2005-07-10 03:00:44.785181224 +0200
3394 +++ linux.dev/arch/mips/kernel/setup.c 2005-07-12 02:59:26.194668224 +0200
3395 @@ -109,6 +109,7 @@
3396 unsigned long isa_slot_offset;
3397 EXPORT_SYMBOL(isa_slot_offset);
3398
3399 +extern void avalanche_bootmem_init(void);
3400 extern void SetUpBootInfo(void);
3401 extern void load_mmu(void);
3402 extern asmlinkage void start_kernel(void);
3403 @@ -267,6 +268,9 @@
3404 #endif /* CONFIG_BLK_DEV_INITRD */
3405
3406 /* Find the highest page frame number we have available. */
3407 +#ifdef CONFIG_AR7_PAGING
3408 + avalanche_bootmem_init();
3409 +#else
3410 max_pfn = 0;
3411 first_usable_pfn = -1UL;
3412 for (i = 0; i < boot_mem_map.nr_map; i++) {
3413 @@ -377,6 +381,7 @@
3414 /* Reserve the bootmap memory. */
3415 reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size);
3416
3417 +#endif
3418 #ifdef CONFIG_BLK_DEV_INITRD
3419 /* Board specific code should have set up initrd_start and initrd_end */
3420 ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
3421 @@ -494,6 +499,7 @@
3422 void hp_setup(void);
3423 void au1x00_setup(void);
3424 void frame_info_init(void);
3425 + void ar7_setup(void);
3426
3427 frame_info_init();
3428 #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
3429 @@ -691,6 +697,11 @@
3430 pmc_yosemite_setup();
3431 break;
3432 #endif
3433 +#ifdef CONFIG_AR7
3434 + case MACH_GROUP_UNKNOWN:
3435 + ar7_setup();
3436 + break;
3437 +#endif
3438 default:
3439 panic("Unsupported architecture");
3440 }
3441 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
3442 --- linux.old/arch/mips/kernel/traps.c 2005-07-10 03:00:44.786181072 +0200
3443 +++ linux.dev/arch/mips/kernel/traps.c 2005-07-12 02:59:26.194668224 +0200
3444 @@ -40,6 +40,10 @@
3445 #include <asm/uaccess.h>
3446 #include <asm/mmu_context.h>
3447
3448 +#ifdef CONFIG_AR7
3449 +#include <asm/ar7/ar7.h>
3450 +#endif
3451 +
3452 extern asmlinkage void handle_mod(void);
3453 extern asmlinkage void handle_tlbl(void);
3454 extern asmlinkage void handle_tlbs(void);
3455 @@ -869,9 +873,15 @@
3456
3457 exception_handlers[n] = handler;
3458 if (n == 0 && cpu_has_divec) {
3459 +#ifdef CONFIG_AR7
3460 + *(volatile u32 *)(AVALANCHE_VECS_KSEG0+0x200) = 0x08000000 |
3461 + (0x03ffffff & (handler >> 2));
3462 + flush_icache_range(AVALANCHE_VECS_KSEG0+0x200, AVALANCHE_VECS_KSEG0 + 0x204);
3463 +#else
3464 *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
3465 (0x03ffffff & (handler >> 2));
3466 flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
3467 +#endif
3468 }
3469 return (void *)old_handler;
3470 }
3471 @@ -920,14 +930,46 @@
3472 void __init trap_init(void)
3473 {
3474 extern char except_vec1_generic;
3475 + extern char except_vec2_generic;
3476 extern char except_vec3_generic, except_vec3_r4000;
3477 extern char except_vec_ejtag_debug;
3478 extern char except_vec4;
3479 unsigned long i;
3480
3481 +#ifdef CONFIG_AR7
3482 + extern char jump_tlb_miss, jump_tlb_miss_unused;
3483 + extern char jump_cache_error,jump_general_exception;
3484 + extern char jump_dedicated_interrupt;
3485 + clear_c0_status(ST0_BEV);
3486 +#endif
3487 +
3488 /* Copy the generic exception handler code to it's final destination. */
3489 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
3490 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
3491 + memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
3492
3493 + memcpy((void *)(KSEG0 + 0x0), &jump_tlb_miss, 0x80);
3494 + memcpy((void *)(KSEG0 + 0x80), &jump_tlb_miss_unused, 0x80);
3495 + memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
3496 + memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
3497 + memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
3498 +
3499 +#ifdef CONFIG_AR7
3500 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x80), &except_vec1_generic, 0x80);
3501 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x100), &except_vec2_generic, 0x80);
3502 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
3503 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
3504 +
3505 + memcpy((void *)(KSEG0 + 0x0), &jump_tlb_miss, 0x80);
3506 + memcpy((void *)(KSEG0 + 0x80), &jump_tlb_miss_unused, 0x80);
3507 + memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
3508 + memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
3509 + memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
3510 +#else
3511 + memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
3512 +#endif
3513 + flush_icache_range(KSEG0 + 0x80, KSEG0 + 0x200);
3514 +
3515 /*
3516 * Setup default vectors
3517 */
3518 @@ -951,8 +993,12 @@
3519 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
3520 * interrupt processing overhead. Use it where available.
3521 */
3522 +#ifdef CONFIG_AR7
3523 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x200), &except_vec4, 8);
3524 +#else
3525 if (cpu_has_divec)
3526 memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8);
3527 +#endif
3528
3529 /*
3530 * Some CPUs can enable/disable for cache parity detection, but does
3531 @@ -991,12 +1037,17 @@
3532 if (cpu_has_mcheck)
3533 set_except_vector(24, handle_mcheck);
3534
3535 +memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
3536 +#ifdef CONFIG_AR7
3537 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
3538 +#else
3539 if (cpu_has_vce)
3540 memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x80);
3541 else if (cpu_has_4kex)
3542 memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
3543 else
3544 memcpy((void *)(KSEG0 + 0x080), &except_vec3_generic, 0x80);
3545 +#endif
3546
3547 if (current_cpu_data.cputype == CPU_R6000 ||
3548 current_cpu_data.cputype == CPU_R6000A) {
3549 @@ -1023,7 +1074,11 @@
3550 if (board_nmi_handler_setup)
3551 board_nmi_handler_setup();
3552
3553 +#ifdef CONFIG_AR7
3554 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
3555 +#else
3556 flush_icache_range(KSEG0, KSEG0 + 0x400);
3557 +#endif
3558
3559 per_cpu_trap_init();
3560 }
3561 diff -urN linux.old/arch/mips/lib/promlib.c linux.dev/arch/mips/lib/promlib.c
3562 --- linux.old/arch/mips/lib/promlib.c 2005-07-10 03:00:44.786181072 +0200
3563 +++ linux.dev/arch/mips/lib/promlib.c 2005-07-12 02:59:26.195668072 +0200
3564 @@ -1,3 +1,4 @@
3565 +#ifndef CONFIG_AR7
3566 #include <stdarg.h>
3567 #include <linux/kernel.h>
3568
3569 @@ -22,3 +23,4 @@
3570 }
3571 va_end(args);
3572 }
3573 +#endif
3574 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
3575 --- linux.old/arch/mips/Makefile 2005-07-10 03:00:44.786181072 +0200
3576 +++ linux.dev/arch/mips/Makefile 2005-07-12 02:59:26.195668072 +0200
3577 @@ -369,6 +369,16 @@
3578 endif
3579
3580 #
3581 +# Texas Instruments AR7
3582 +#
3583 +
3584 +ifdef CONFIG_AR7
3585 +LIBS += arch/mips/ar7/ar7.o arch/mips/ar7/ar7/ar7.o
3586 +SUBDIRS += arch/mips/ar7 arch/mips/ar7/ar7
3587 +LOADADDR += 0x94020000
3588 +endif
3589 +
3590 +#
3591 # DECstation family
3592 #
3593 ifdef CONFIG_DECSTATION
3594 diff -urN linux.old/arch/mips/mm/init.c linux.dev/arch/mips/mm/init.c
3595 --- linux.old/arch/mips/mm/init.c 2005-07-10 03:00:44.787180920 +0200
3596 +++ linux.dev/arch/mips/mm/init.c 2005-07-12 02:59:26.195668072 +0200
3597 @@ -40,8 +40,10 @@
3598
3599 mmu_gather_t mmu_gathers[NR_CPUS];
3600 unsigned long highstart_pfn, highend_pfn;
3601 +#ifndef CONFIG_AR7_PAGING
3602 static unsigned long totalram_pages;
3603 static unsigned long totalhigh_pages;
3604 +#endif
3605
3606 void pgd_init(unsigned long page)
3607 {
3608 @@ -235,6 +237,7 @@
3609 #endif
3610 }
3611
3612 +#ifndef CONFIG_AR7_PAGING
3613 void __init paging_init(void)
3614 {
3615 unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
3616 @@ -272,6 +275,7 @@
3617
3618 free_area_init(zones_size);
3619 }
3620 +#endif
3621
3622 #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
3623 #define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
3624 @@ -298,6 +302,7 @@
3625 return 0;
3626 }
3627
3628 +#ifndef CONFIG_AR7_PAGING
3629 void __init mem_init(void)
3630 {
3631 unsigned long codesize, reservedpages, datasize, initsize;
3632 @@ -359,6 +364,7 @@
3633 initsize >> 10,
3634 (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10)));
3635 }
3636 +#endif
3637
3638 #ifdef CONFIG_BLK_DEV_INITRD
3639 void free_initrd_mem(unsigned long start, unsigned long end)
3640 @@ -376,6 +382,7 @@
3641 }
3642 #endif
3643
3644 +#ifndef CONFIG_AR7_PAGING
3645 extern char __init_begin, __init_end;
3646 extern void prom_free_prom_memory(void) __init;
3647
3648 @@ -383,7 +390,9 @@
3649 {
3650 unsigned long addr;
3651
3652 +#ifndef CONFIG_AR7
3653 prom_free_prom_memory ();
3654 +#endif
3655
3656 addr = (unsigned long) &__init_begin;
3657 while (addr < (unsigned long) &__init_end) {
3658 @@ -409,3 +418,4 @@
3659
3660 return;
3661 }
3662 +#endif
3663 diff -urN linux.old/arch/mips/mm/tlb-r4k.c linux.dev/arch/mips/mm/tlb-r4k.c
3664 --- linux.old/arch/mips/mm/tlb-r4k.c 2005-07-10 03:00:44.787180920 +0200
3665 +++ linux.dev/arch/mips/mm/tlb-r4k.c 2005-07-12 02:59:26.196667920 +0200
3666 @@ -20,6 +20,10 @@
3667 #include <asm/pgtable.h>
3668 #include <asm/system.h>
3669
3670 +#ifdef CONFIG_AR7
3671 +#include <asm/ar7/ar7.h>
3672 +#endif
3673 +
3674 extern char except_vec0_nevada, except_vec0_r4000, except_vec0_r4600;
3675
3676 /* CP0 hazard avoidance. */
3677 @@ -375,7 +379,12 @@
3678 else if (current_cpu_data.cputype == CPU_R4600)
3679 memcpy((void *)KSEG0, &except_vec0_r4600, 0x80);
3680 else
3681 +#ifdef CONFIG_AR7
3682 + memcpy((void *)AVALANCHE_VECS_KSEG0, &except_vec0_r4000, 0x80);
3683 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x80);
3684 +#else
3685 memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
3686 flush_icache_range(KSEG0, KSEG0 + 0x80);
3687 +#endif
3688 }
3689 }
3690 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
3691 --- linux.old/drivers/char/serial.c 2005-07-10 03:00:44.789180616 +0200
3692 +++ linux.dev/drivers/char/serial.c 2005-07-12 02:59:26.198667616 +0200
3693 @@ -419,7 +419,40 @@
3694 return 0;
3695 }
3696
3697 -#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
3698 +#if defined(CONFIG_AR7)
3699 +
3700 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
3701 +{
3702 + return (inb(info->port + (offset * 4)) & 0xff);
3703 +}
3704 +
3705 +
3706 +static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset)
3707 +{
3708 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
3709 + return (inb(info->port + (offset * 4)) & 0xff);
3710 +#else
3711 + return (inb_p(info->port + (offset * 4)) & 0xff);
3712 +#endif
3713 +}
3714 +
3715 +static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
3716 +{
3717 + outb(value, info->port + (offset * 4));
3718 +}
3719 +
3720 +
3721 +static _INLINE_ void serial_outp(struct async_struct *info, int offset,
3722 + int value)
3723 +{
3724 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
3725 + outb(value, info->port + (offset * 4));
3726 +#else
3727 + outb_p(value, info->port + (offset * 4));
3728 +#endif
3729 +}
3730 +
3731 +#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
3732
3733 #include <asm/mips-boards/atlas.h>
3734
3735 @@ -478,8 +511,10 @@
3736 * needed for certain old 386 machines, I've left these #define's
3737 * in....
3738 */
3739 +#ifndef CONFIG_AR7
3740 #define serial_inp(info, offset) serial_in(info, offset)
3741 #define serial_outp(info, offset, value) serial_out(info, offset, value)
3742 +#endif
3743
3744
3745 /*
3746 @@ -1728,7 +1763,16 @@
3747 /* Special case since 134 is really 134.5 */
3748 quot = (2*baud_base / 269);
3749 else if (baud)
3750 +#ifdef CONFIG_AR7
3751 + quot = (CONFIG_AR7_SYS_FREQUENCY*500000) / baud;
3752 + //quot = get_avalanche_vbus_freq() / baud;
3753 +
3754 + if ((quot%16)>7)
3755 + quot += 8;
3756 + quot /=16;
3757 +#else
3758 quot = baud_base / baud;
3759 +#endif
3760 }
3761 /* If the quotient is zero refuse the change */
3762 if (!quot && old_termios) {
3763 @@ -5552,8 +5596,10 @@
3764 state->irq = irq_cannonicalize(state->irq);
3765 if (state->hub6)
3766 state->io_type = SERIAL_IO_HUB6;
3767 +#ifndef CONFIG_AR7
3768 if (state->port && check_region(state->port,8))
3769 continue;
3770 +#endif
3771 #ifdef CONFIG_MCA
3772 if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
3773 continue;
3774 @@ -6009,7 +6055,16 @@
3775 info->io_type = state->io_type;
3776 info->iomem_base = state->iomem_base;
3777 info->iomem_reg_shift = state->iomem_reg_shift;
3778 +#ifdef CONFIG_AR7
3779 + //quot = get_avalanche_vbus_freq() / baud;
3780 + quot = (CONFIG_AR7_SYS_FREQUENCY*500000) / baud;
3781 +
3782 + if ((quot%16)>7)
3783 + quot += 8;
3784 + quot /=16;
3785 +#else
3786 quot = state->baud_base / baud;
3787 +#endif
3788 cval = cflag & (CSIZE | CSTOPB);
3789 #if defined(__powerpc__) || defined(__alpha__)
3790 cval >>= 8;
3791 diff -urN linux.old/include/asm-mips/ar7/ar7.h linux.dev/include/asm-mips/ar7/ar7.h
3792 --- linux.old/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100
3793 +++ linux.dev/include/asm-mips/ar7/ar7.h 2005-07-12 02:59:26.199667464 +0200
3794 @@ -0,0 +1,33 @@
3795 +/*
3796 + * $Id$
3797 + * Copyright (C) $Date$ $Author$
3798 + *
3799 + * This program is free software; you can redistribute it and/or modify
3800 + * it under the terms of the GNU General Public License as published by
3801 + * the Free Software Foundation; either version 2 of the License, or
3802 + * (at your option) any later version.
3803 + *
3804 + * This program is distributed in the hope that it will be useful,
3805 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3806 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3807 + * GNU General Public License for more details.
3808 + *
3809 + * You should have received a copy of the GNU General Public License
3810 + * along with this program; if not, write to the Free Software
3811 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
3812 + *
3813 + */
3814 +
3815 +#ifndef _AR7_H
3816 +#define _AR7_H
3817 +
3818 +#include <asm/addrspace.h>
3819 +#include <linux/config.h>
3820 +
3821 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(CONFIG_AR7_MEMORY))
3822 +
3823 +#define AR7_UART0_REGS_BASE (KSEG1ADDR(0x08610E00))
3824 +#define AR7_UART1_REGS_BASE (KSEG1ADDR(0x08610E00))
3825 +#define AR7_BASE_BAUD ( 3686400 / 16 )
3826 +
3827 +#endif
3828 diff -urN linux.old/include/asm-mips/ar7/avalanche_intc.h linux.dev/include/asm-mips/ar7/avalanche_intc.h
3829 --- linux.old/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 01:00:00.000000000 +0100
3830 +++ linux.dev/include/asm-mips/ar7/avalanche_intc.h 2005-07-12 02:59:26.199667464 +0200
3831 @@ -0,0 +1,278 @@
3832 + /*
3833 + * Nitin Dhingra, iamnd@ti.com
3834 + * Copyright (C) 2000 Texas Instruments Inc.
3835 + *
3836 + *
3837 + * ########################################################################
3838 + *
3839 + * This program is free software; you can distribute it and/or modify it
3840 + * under the terms of the GNU General Public License (Version 2) as
3841 + * published by the Free Software Foundation.
3842 + *
3843 + * This program is distributed in the hope it will be useful, but WITHOUT
3844 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3845 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
3846 + * for more details.
3847 + *
3848 + * You should have received a copy of the GNU General Public License along
3849 + * with this program; if not, write to the Free Software Foundation, Inc.,
3850 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
3851 + *
3852 + * ########################################################################
3853 + *
3854 + * Defines of the Sead board specific address-MAP, registers, etc.
3855 + *
3856 + */
3857 +#ifndef _AVALANCHE_INTC_H
3858 +#define _AVALANCHE_INTC_H
3859 +
3860 +#define MIPS_EXCEPTION_OFFSET 8
3861 +
3862 +/******************************************************************************
3863 + Avalanche Interrupt number
3864 +******************************************************************************/
3865 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
3866 +
3867 +/*******************************************************************************
3868 +*Linux Interrupt number
3869 +*******************************************************************************/
3870 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
3871 +
3872 +
3873 +
3874 +#define AVALANCHE_INT_END_PRIMARY (40 + MIPS_EXCEPTION_OFFSET)
3875 +#define AVALANCHE_INT_END_SECONDARY (32 + MIPS_EXCEPTION_OFFSET)
3876 +
3877 +#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
3878 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
3879 +
3880 +
3881 +#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + \
3882 + AVINTNUM(AVALANCHE_INT_END_SECONDARY) \
3883 + + MIPS_EXCEPTION_OFFSET - 1) /* Suraj, check */
3884 +
3885 +
3886 +/*
3887 + * Avalanche interrupt controller register base (primary)
3888 + */
3889 +#define KSEG1_BASE 0xA0000000
3890 +#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
3891 +#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
3892 +#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
3893 +
3894 +#define AVALANCHE_ICTRL_REGS_BASE KSEG1ADDR(0x08612400)// AVALANCHE_INTC_BASE
3895 +
3896 +/******************************************************************************
3897 + * Avalanche exception controller register base (secondary)
3898 + ******************************************************************************/
3899 +#define AVALANCHE_ECTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x80)
3900 +
3901 +
3902 +/******************************************************************************
3903 + * Avalanche Interrupt pacing register base (secondary)
3904 + ******************************************************************************/
3905 +#define AVALANCHE_IPACE_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0xA0)
3906 +
3907 +
3908 +
3909 +/******************************************************************************
3910 + * Avalanche Interrupt Channel Control register base
3911 + *****************************************************************************/
3912 +#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
3913 +
3914 +
3915 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
3916 +{
3917 + volatile unsigned long intsr1; /* Interrupt Status/Set Register 1 0x00 */
3918 + volatile unsigned long intsr2; /* Interrupt Status/Set Register 2 0x04 */
3919 + volatile unsigned long unused1; /*0x08 */
3920 + volatile unsigned long unused2; /*0x0C */
3921 + volatile unsigned long intcr1; /* Interrupt Clear Register 1 0x10 */
3922 + volatile unsigned long intcr2; /* Interrupt Clear Register 2 0x14 */
3923 + volatile unsigned long unused3; /*0x18 */
3924 + volatile unsigned long unused4; /*0x1C */
3925 + volatile unsigned long intesr1; /* Interrupt Enable (Set) Register 1 0x20 */
3926 + volatile unsigned long intesr2; /* Interrupt Enable (Set) Register 2 0x24 */
3927 + volatile unsigned long unused5; /*0x28 */
3928 + volatile unsigned long unused6; /*0x2C */
3929 + volatile unsigned long intecr1; /* Interrupt Enable Clear Register 1 0x30 */
3930 + volatile unsigned long intecr2; /* Interrupt Enable Clear Register 2 0x34 */
3931 + volatile unsigned long unused7; /* 0x38 */
3932 + volatile unsigned long unused8; /* 0x3c */
3933 + volatile unsigned long pintir; /* Priority Interrupt Index Register 0x40 */
3934 + volatile unsigned long intmsr; /* Priority Interrupt Mask Index Reg 0x44 */
3935 + volatile unsigned long unused9; /* 0x48 */
3936 + volatile unsigned long unused10; /* 0x4C */
3937 + volatile unsigned long intpolr1; /* Interrupt Polarity Mask register 10x50 */
3938 + volatile unsigned long intpolr2; /* Interrupt Polarity Mask register 20x54 */
3939 + volatile unsigned long unused11; /* 0x58 */
3940 + volatile unsigned long unused12; /*0x5C */
3941 + volatile unsigned long inttypr1; /* Interrupt Type Mask register 10x60 */
3942 + volatile unsigned long inttypr2; /* Interrupt Type Mask register 20x64 */
3943 +};
3944 +
3945 +struct avalanche_exctrl_regs /* Avalanche Exception control registers */
3946 +{
3947 + volatile unsigned long exsr; /* Exceptions Status/Set register 0x80 */
3948 + volatile unsigned long reserved; /*0x84 */
3949 + volatile unsigned long excr; /* Exceptions Clear Register 0x88 */
3950 + volatile unsigned long reserved1; /*0x8c */
3951 + volatile unsigned long exiesr; /* Exceptions Interrupt Enable (set) 0x90 */
3952 + volatile unsigned long reserved2; /*0x94 */
3953 + volatile unsigned long exiecr; /* Exceptions Interrupt Enable(clear)0x98 */
3954 +};
3955 +struct avalanche_ipace_regs
3956 +{
3957 +
3958 + volatile unsigned long ipacep; /* Interrupt pacing register 0xa0 */
3959 + volatile unsigned long ipacemap; /*Interrupt Pacing Map Register 0xa4 */
3960 + volatile unsigned long ipacemax; /*Interrupt Pacing Max Register 0xa8 */
3961 +};
3962 +struct avalanche_channel_int_number
3963 +{
3964 + volatile unsigned long cintnr0; /* Channel Interrupt Number Register0x200 */
3965 + volatile unsigned long cintnr1; /* Channel Interrupt Number Register0x204 */
3966 + volatile unsigned long cintnr2; /* Channel Interrupt Number Register0x208 */
3967 + volatile unsigned long cintnr3; /* Channel Interrupt Number Register0x20C */
3968 + volatile unsigned long cintnr4; /* Channel Interrupt Number Register0x210 */
3969 + volatile unsigned long cintnr5; /* Channel Interrupt Number Register0x214 */
3970 + volatile unsigned long cintnr6; /* Channel Interrupt Number Register0x218 */
3971 + volatile unsigned long cintnr7; /* Channel Interrupt Number Register0x21C */
3972 + volatile unsigned long cintnr8; /* Channel Interrupt Number Register0x220 */
3973 + volatile unsigned long cintnr9; /* Channel Interrupt Number Register0x224 */
3974 + volatile unsigned long cintnr10; /* Channel Interrupt Number Register0x228 */
3975 + volatile unsigned long cintnr11; /* Channel Interrupt Number Register0x22C */
3976 + volatile unsigned long cintnr12; /* Channel Interrupt Number Register0x230 */
3977 + volatile unsigned long cintnr13; /* Channel Interrupt Number Register0x234 */
3978 + volatile unsigned long cintnr14; /* Channel Interrupt Number Register0x238 */
3979 + volatile unsigned long cintnr15; /* Channel Interrupt Number Register0x23C */
3980 + volatile unsigned long cintnr16; /* Channel Interrupt Number Register0x240 */
3981 + volatile unsigned long cintnr17; /* Channel Interrupt Number Register0x244 */
3982 + volatile unsigned long cintnr18; /* Channel Interrupt Number Register0x248 */
3983 + volatile unsigned long cintnr19; /* Channel Interrupt Number Register0x24C */
3984 + volatile unsigned long cintnr20; /* Channel Interrupt Number Register0x250 */
3985 + volatile unsigned long cintnr21; /* Channel Interrupt Number Register0x254 */
3986 + volatile unsigned long cintnr22; /* Channel Interrupt Number Register0x358 */
3987 + volatile unsigned long cintnr23; /* Channel Interrupt Number Register0x35C */
3988 + volatile unsigned long cintnr24; /* Channel Interrupt Number Register0x260 */
3989 + volatile unsigned long cintnr25; /* Channel Interrupt Number Register0x264 */
3990 + volatile unsigned long cintnr26; /* Channel Interrupt Number Register0x268 */
3991 + volatile unsigned long cintnr27; /* Channel Interrupt Number Register0x26C */
3992 + volatile unsigned long cintnr28; /* Channel Interrupt Number Register0x270 */
3993 + volatile unsigned long cintnr29; /* Channel Interrupt Number Register0x274 */
3994 + volatile unsigned long cintnr30; /* Channel Interrupt Number Register0x278 */
3995 + volatile unsigned long cintnr31; /* Channel Interrupt Number Register0x27C */
3996 + volatile unsigned long cintnr32; /* Channel Interrupt Number Register0x280 */
3997 + volatile unsigned long cintnr33; /* Channel Interrupt Number Register0x284 */
3998 + volatile unsigned long cintnr34; /* Channel Interrupt Number Register0x288 */
3999 + volatile unsigned long cintnr35; /* Channel Interrupt Number Register0x28C */
4000 + volatile unsigned long cintnr36; /* Channel Interrupt Number Register0x290 */
4001 + volatile unsigned long cintnr37; /* Channel Interrupt Number Register0x294 */
4002 + volatile unsigned long cintnr38; /* Channel Interrupt Number Register0x298 */
4003 + volatile unsigned long cintnr39; /* Channel Interrupt Number Register0x29C */
4004 +};
4005 +
4006 +struct avalanche_interrupt_line_to_channel
4007 +{
4008 + unsigned long int_line0; /* Start of primary interrupts */
4009 + unsigned long int_line1;
4010 + unsigned long int_line2;
4011 + unsigned long int_line3;
4012 + unsigned long int_line4;
4013 + unsigned long int_line5;
4014 + unsigned long int_line6;
4015 + unsigned long int_line7;
4016 + unsigned long int_line8;
4017 + unsigned long int_line9;
4018 + unsigned long int_line10;
4019 + unsigned long int_line11;
4020 + unsigned long int_line12;
4021 + unsigned long int_line13;
4022 + unsigned long int_line14;
4023 + unsigned long int_line15;
4024 + unsigned long int_line16;
4025 + unsigned long int_line17;
4026 + unsigned long int_line18;
4027 + unsigned long int_line19;
4028 + unsigned long int_line20;
4029 + unsigned long int_line21;
4030 + unsigned long int_line22;
4031 + unsigned long int_line23;
4032 + unsigned long int_line24;
4033 + unsigned long int_line25;
4034 + unsigned long int_line26;
4035 + unsigned long int_line27;
4036 + unsigned long int_line28;
4037 + unsigned long int_line29;
4038 + unsigned long int_line30;
4039 + unsigned long int_line31;
4040 + unsigned long int_line32;
4041 + unsigned long int_line33;
4042 + unsigned long int_line34;
4043 + unsigned long int_line35;
4044 + unsigned long int_line36;
4045 + unsigned long int_line37;
4046 + unsigned long int_line38;
4047 + unsigned long int_line39;
4048 +};
4049 +
4050 +
4051 +/* Interrupt Line #'s (Sangam peripherals) */
4052 +
4053 +/*------------------------------*/
4054 +/* Sangam primary interrupts */
4055 +/*------------------------------*/
4056 +
4057 +#define UNIFIED_SECONDARY_INTERRUPT 0
4058 +#define AVALANCHE_EXT_INT_0 1
4059 +#define AVALANCHE_EXT_INT_1 2
4060 +/* Line #3 Reserved */
4061 +/* Line #4 Reserved */
4062 +#define AVALANCHE_TIMER_0_INT 5
4063 +#define AVALANCHE_TIMER_1_INT 6
4064 +#define AVALANCHE_UART0_INT 7
4065 +#define AVALANCHE_UART1_INT 8
4066 +#define AVALANCHE_PDMA_INT0 9
4067 +#define AVALANCHE_PDMA_INT1 10
4068 +/* Line #11 Reserved */
4069 +/* Line #12 Reserved */
4070 +/* Line #13 Reserved */
4071 +/* Line #14 Reserved */
4072 +#define AVALANCHE_ATM_SAR_INT 15
4073 +/* Line #16 Reserved */
4074 +/* Line #17 Reserved */
4075 +/* Line #18 Reserved */
4076 +#define AVALANCHE_MAC0_INT 19
4077 +/* Line #20 Reserved */
4078 +#define AVALANCHE_VLYNQ0_INT 21
4079 +#define AVALANCHE_CODEC_WAKE_INT 22
4080 +/* Line #23 Reserved */
4081 +#define AVALANCHE_USB_INT 24
4082 +#define AVALANCHE_VLYNQ1_INT 25
4083 +/* Line #26 Reserved */
4084 +/* Line #27 Reserved */
4085 +#define AVALANCHE_MAC1_INT 28
4086 +#define AVALANCHE_I2CM_INT 29
4087 +#define AVALANCHE_PDMA_INT2 30
4088 +#define AVALANCHE_PDMA_INT3 31
4089 +/* Line #32 Reserved */
4090 +/* Line #33 Reserved */
4091 +/* Line #34 Reserved */
4092 +/* Line #35 Reserved */
4093 +/* Line #36 Reserved */
4094 +#define AVALANCHE_VDMA_VT_RX_INT 37
4095 +#define AVALANCHE_VDMA_VT_TX_INT 38
4096 +#define AVALANCHE_ADSLSS_INT 39
4097 +
4098 +/*-----------------------------------*/
4099 +/* Sangam Secondary Interrupts */
4100 +/*-----------------------------------*/
4101 +#define PRIMARY_INTS 40
4102 +
4103 +#define EMIF_INT (7 + PRIMARY_INTS)
4104 +
4105 +
4106 +extern void avalanche_int_set(int channel, int line);
4107 +
4108 +
4109 +#endif /* _AVALANCHE_INTC_H */
4110 diff -urN linux.old/include/asm-mips/ar7/avalanche_misc.h linux.dev/include/asm-mips/ar7/avalanche_misc.h
4111 --- linux.old/include/asm-mips/ar7/avalanche_misc.h 1970-01-01 01:00:00.000000000 +0100
4112 +++ linux.dev/include/asm-mips/ar7/avalanche_misc.h 2005-07-12 02:59:26.200667312 +0200
4113 @@ -0,0 +1,174 @@
4114 +#ifndef _AVALANCHE_MISC_H_
4115 +#define _AVALANCHE_MISC_H_
4116 +
4117 +typedef enum AVALANCHE_ERR_t
4118 +{
4119 + AVALANCHE_ERR_OK = 0, /* OK or SUCCESS */
4120 + AVALANCHE_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
4121 +
4122 + /* Pointers and args */
4123 + AVALANCHE_ERR_INVARG = -2, /* Invaild argument to the call */
4124 + AVALANCHE_ERR_NULLPTR = -3, /* NULL pointer */
4125 + AVALANCHE_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
4126 +
4127 + /* Memory issues */
4128 + AVALANCHE_ERR_ALLOC_FAIL = -10, /* allocation failed */
4129 + AVALANCHE_ERR_FREE_FAIL = -11, /* free failed */
4130 + AVALANCHE_ERR_MEM_CORRUPT = -12, /* corrupted memory */
4131 + AVALANCHE_ERR_BUF_LINK = -13, /* buffer linking failed */
4132 +
4133 + /* Device issues */
4134 + AVALANCHE_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
4135 + AVALANCHE_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
4136 +
4137 + AVALANCHE_ERR_INVID = -30 /* Invalid ID */
4138 +
4139 +} AVALANCHE_ERR;
4140 +
4141 +/*****************************************************************************
4142 + * Reset Control Module
4143 + *****************************************************************************/
4144 +
4145 +typedef enum AVALANCHE_RESET_MODULE_tag
4146 +{
4147 + RESET_MODULE_UART0 = 0,
4148 + RESET_MODULE_UART1 = 1,
4149 + RESET_MODULE_I2C = 2,
4150 + RESET_MODULE_TIMER0 = 3,
4151 + RESET_MODULE_TIMER1 = 4,
4152 + RESET_MODULE_GPIO = 6,
4153 + RESET_MODULE_ADSLSS = 7,
4154 + RESET_MODULE_USBS = 8,
4155 + RESET_MODULE_SAR = 9,
4156 + RESET_MODULE_VDMA_VT = 11,
4157 + RESET_MODULE_FSER = 12,
4158 + RESET_MODULE_VLYNQ1 = 16,
4159 + RESET_MODULE_EMAC0 = 17,
4160 + RESET_MODULE_DMA = 18,
4161 + RESET_MODULE_BIST = 19,
4162 + RESET_MODULE_VLYNQ0 = 20,
4163 + RESET_MODULE_EMAC1 = 21,
4164 + RESET_MODULE_MDIO = 22,
4165 + RESET_MODULE_ADSLSS_DSP = 23,
4166 + RESET_MODULE_EPHY = 26
4167 +} AVALANCHE_RESET_MODULE_T;
4168 +
4169 +typedef enum AVALANCHE_RESET_CTRL_tag
4170 +{
4171 + IN_RESET = 0,
4172 + OUT_OF_RESET
4173 +} AVALANCHE_RESET_CTRL_T;
4174 +
4175 +typedef enum AVALANCHE_SYS_RST_MODE_tag
4176 +{
4177 + RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
4178 + RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
4179 +} AVALANCHE_SYS_RST_MODE_T;
4180 +
4181 +typedef enum AVALANCHE_SYS_RESET_STATUS_tag
4182 +{
4183 + HARDWARE_RESET = 0,
4184 + SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
4185 + WATCHDOG_RESET,
4186 + SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
4187 +} AVALANCHE_SYS_RESET_STATUS_T;
4188 +
4189 +AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(AVALANCHE_RESET_MODULE_T reset_module);
4190 +void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode);
4191 +AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status(void);
4192 +
4193 +typedef int (*REMOTE_VLYNQ_DEV_RESET_CTRL_FN)(unsigned int reset_module, AVALANCHE_RESET_CTRL_T reset_ctrl);
4194 +
4195 +/*****************************************************************************
4196 + * Power Control Module
4197 + *****************************************************************************/
4198 +
4199 +typedef enum AVALANCHE_POWER_CTRL_tag
4200 +{
4201 + POWER_CTRL_POWER_UP = 0,
4202 + POWER_CTRL_POWER_DOWN
4203 +} AVALANCHE_POWER_CTRL_T;
4204 +
4205 +typedef enum AVALANCHE_SYS_POWER_MODE_tag
4206 +{
4207 + GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
4208 + GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
4209 + GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
4210 + GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
4211 +} AVALANCHE_SYS_POWER_MODE_T;
4212 +
4213 +void avalanche_power_ctrl(unsigned int power_module, AVALANCHE_POWER_CTRL_T power_ctrl);
4214 +AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int power_module);
4215 +void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode);
4216 +AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void);
4217 +
4218 +/*****************************************************************************
4219 + * Wakeup Control
4220 + *****************************************************************************/
4221 +
4222 +typedef enum AVALANCHE_WAKEUP_INTERRUPT_tag
4223 +{
4224 + WAKEUP_INT0 = 1,
4225 + WAKEUP_INT1 = 2,
4226 + WAKEUP_INT2 = 4,
4227 + WAKEUP_INT3 = 8
4228 +} AVALANCHE_WAKEUP_INTERRUPT_T;
4229 +
4230 +typedef enum TNETV1050_WAKEUP_CTRL_tag
4231 +{
4232 + WAKEUP_DISABLED = 0,
4233 + WAKEUP_ENABLED
4234 +} AVALANCHE_WAKEUP_CTRL_T;
4235 +
4236 +typedef enum TNETV1050_WAKEUP_POLARITY_tag
4237 +{
4238 + WAKEUP_ACTIVE_HIGH = 0,
4239 + WAKEUP_ACTIVE_LOW
4240 +} AVALANCHE_WAKEUP_POLARITY_T;
4241 +
4242 +void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
4243 + AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
4244 + AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity);
4245 +
4246 +/*****************************************************************************
4247 + * GPIO Control
4248 + *****************************************************************************/
4249 +
4250 +typedef enum AVALANCHE_GPIO_PIN_MODE_tag
4251 +{
4252 + FUNCTIONAL_PIN = 0,
4253 + GPIO_PIN = 1
4254 +} AVALANCHE_GPIO_PIN_MODE_T;
4255 +
4256 +typedef enum AVALANCHE_GPIO_PIN_DIRECTION_tag
4257 +{
4258 + GPIO_OUTPUT_PIN = 0,
4259 + GPIO_INPUT_PIN = 1
4260 +} AVALANCHE_GPIO_PIN_DIRECTION_T;
4261 +
4262 +typedef enum { GPIO_FALSE, GPIO_TRUE } AVALANCHE_GPIO_BOOL_T;
4263 +
4264 +void avalanche_gpio_init(void);
4265 +int avalanche_gpio_ctrl(unsigned int gpio_pin,
4266 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
4267 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
4268 +int avalanche_gpio_ctrl_with_link_count(unsigned int gpio_pin,
4269 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
4270 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
4271 +int avalanche_gpio_out_bit(unsigned int gpio_pin, int value);
4272 +int avalanche_gpio_in_bit(unsigned int gpio_pin);
4273 +int avalanche_gpio_out_value(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
4274 +int avalanche_gpio_out_value_with_link_count(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
4275 +int avalanche_gpio_in_value(unsigned int *in_val, unsigned int reg_index);
4276 +
4277 +unsigned int avalanche_get_chip_version_info(void);
4278 +
4279 +unsigned int avalanche_get_vbus_freq(void);
4280 +void avalanche_set_vbus_freq(unsigned int);
4281 +
4282 +
4283 +typedef int (*SET_MDIX_ON_CHIP_FN_T)(unsigned int base_addr, unsigned int operation);
4284 +int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation);
4285 +unsigned int avalanche_is_mdix_on_chip(void);
4286 +
4287 +#endif
4288 diff -urN linux.old/include/asm-mips/ar7/avalanche_regs.h linux.dev/include/asm-mips/ar7/avalanche_regs.h
4289 --- linux.old/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 01:00:00.000000000 +0100
4290 +++ linux.dev/include/asm-mips/ar7/avalanche_regs.h 2005-07-12 02:59:26.201667160 +0200
4291 @@ -0,0 +1,567 @@
4292 +/*
4293 + * $Id$
4294 + * Avalanche Register Descriptions
4295 + *
4296 + * Jeff Harrell, jharrell@ti.com
4297 + * 2000 (c) Texas Instruments Inc.
4298 + */
4299 +
4300 +#ifndef __AVALANCHE_REGS_H
4301 +#define __AVALANCHE_REGS_H
4302 +
4303 +#include <asm/addrspace.h>
4304 +#include <linux/config.h>
4305 +
4306 +/*----------------------------------------*/
4307 +/* Base offsets within the Avalanche ASIC */
4308 +/*----------------------------------------*/
4309 +
4310 +#define BBIF_SPACE0 (KSEG1ADDR(0x01000000))
4311 +#define BBIF_SPACE1 (KSEG1ADDR(0x01800000))
4312 +#define BBIF_CONTROL (KSEG1ADDR(0x02000000))
4313 +#define ATM_SAR_BASE (KSEG1ADDR(0x03000000))
4314 +#define USB_MCU_BASE (KSEG1ADDR(0x03400000))
4315 +#define DES_BASE (KSEG1ADDR(0x08600000))
4316 +#define ETH_MACA_BASE (KSEG1ADDR(0x08610000))
4317 +#define ETH_MACB_BASE (KSEG1ADDR(0x08612800))
4318 +#define MEM_CTRLR_BASE (KSEG1ADDR(0x08610800))
4319 +#define GPIO_BASE (KSEG1ADDR(0x08610900))
4320 +#define CLK_CTRL_BASE (KSEG1ADDR(0x08610A00))
4321 +#define WATCH_DOG_BASE (KSEG1ADDR(0x08610B00))
4322 +#define TMR1_BASE (KSEG1ADDR(0x08610C00))
4323 +#define TRM2_BASE (KSEG1ADDR(0x08610D00))
4324 +#define UARTA_BASE (KSEG1ADDR(0x08610E00))
4325 +#define UARTB_BASE (KSEG1ADDR(0x08610F00))
4326 +#define I2C_BASE (KSEG1ADDR(0x08611000))
4327 +#define DEV_ID_BASE (KSEG1ADDR(0x08611100))
4328 +#define USB_BASE (KSEG1ADDR(0x08611200))
4329 +#define PCI_CONFIG_BASE (KSEG1ADDR(0x08611300))
4330 +#define DMA_BASE (KSEG1ADDR(0x08611400))
4331 +#define RESET_CTRL_BASE (KSEG1ADDR(0x08611600))
4332 +#define DSL_IF_BASE (KSEG1ADDR(0x08611B00))
4333 +#define INT_CTL_BASE (KSEG1ADDR(0x08612400))
4334 +#define PHY_BASE (KSEG1ADDR(0x1E000000))
4335 +
4336 +/*---------------------------------*/
4337 +/* Device ID, chip version number */
4338 +/*---------------------------------*/
4339 +
4340 +#define AVALANCHE_CHVN (*(volatile unsigned int *)(DEV_ID_BASE+0x14))
4341 +#define AVALANCHE_DEVID1 (*(volatile unsigned int *)(DEV_ID_BASE+0x18))
4342 +#define AVALANCHE_DEVID2 (*(volatile unsigned int *)(DEV_ID_BASE+0x1C))
4343 +
4344 +/*----------------------------------*/
4345 +/* Reset Control VW changed to ptrs */
4346 +/*----------------------------------*/
4347 +
4348 +#define AVALANCHE_PRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x0)) /* Peripheral reset control */
4349 +#define AVALANCHE_SWRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x4)) /* Software reset control */
4350 +#define AVALANCHE_RSR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x8)) /* Reset status register */
4351 +
4352 +/* reset control bits */
4353 +
4354 +#define AV_RST_UART0 (1<<0) /* Brings UART0 out of reset */
4355 +#define AV_RST_UART1 (1<<1) /* Brings UART1 out of reset */
4356 +#define AV_RST_IICM (1<<2) /* Brings the I2CM out of reset */
4357 +#define AV_RST_TIMER0 (1<<3) /* Brings Timer 0 out of reset */
4358 +#define AV_RST_TIMER1 (1<<4) /* Brings Timer 1 out of reset */
4359 +#define AV_RST_DES (1<<5) /* Brings the DES module out of reset */
4360 +#define AV_RST_GPIO (1<<6) /* Brings the GPIO module out of reset (see note below) */
4361 +/*
4362 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4363 + If you reset the GPIO interface all of the directions (i/o) of the UART B
4364 + interface pins are inputs and must be reconfigured so as not to lose the
4365 + serial console interface
4366 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4367 +*/
4368 +#define AV_RST_BBIF (1<<7) /* Brings the Broadband interface out of reset */
4369 +#define AV_RST_USB (1<<8) /* Brings the USB module out of reset */
4370 +#define AV_RST_SAR (1<<9) /* Brings the SAR out of reset */
4371 +#define AV_RST_HDLC (1<<10) /* Brings the HDLC module out of reset */
4372 +#define AV_RST_PCI (1<<16) /* Brings the PCI module out of reset */
4373 +#define AV_RST_ETH_MAC0 (1<<17) /* Brings the Ethernet MAC0 out of reset */
4374 +#define AV_RST_PICO_DMA (1<<18) /* Brings the PICO DMA module out of reset */
4375 +#define AV_RST_BIST (1<<19) /* Brings the BIST module out of reset */
4376 +#define AV_RST_DSP (1<<20) /* Brings the DSP sub system out of reset */
4377 +#define AV_RST_ETH_MAC1 (1<<21) /* Brings the Ethernet MAC1 out of reset */
4378 +
4379 +/*----------------------*/
4380 +/* Physical interfaces */
4381 +/*----------------------*/
4382 +
4383 +/* Phy loopback */
4384 +#define PHY_LOOPBACK 1
4385 +
4386 +
4387 +/* Phy 0 */
4388 +#define PHY0BASE (PHY_BASE)
4389 +#define PHY0RST (*(volatile unsigned char *) (PHY0BASE)) /* reset */
4390 +#define PHY0CTRL (*(volatile unsigned char *) (PHY0BASE+0x5)) /* control */
4391 +#define PHY0RACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x50)) /* RACP control/status */
4392 +#define PHY0TACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x60)) /* TACP idle/unassigned cell hdr */
4393 +#define PHY0RACPINT (*(volatile unsigned char *) (PHY0BASE+0x51)) /* RACP interrupt enable/Status */
4394 +
4395 +
4396 +/* Phy 1 */
4397 +
4398 +#define PHY1BASE (PHY_BASE + 0x100000)
4399 +#define PHY1RST (*(volatile unsigned char *) (PHY1BASE)) /* reset */
4400 +#define PHY1CTRL (*(volatile unsigned char *) (PHY1BASE+0x5)) /* control */
4401 +#define PHY1RACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x50))
4402 +#define PHY1TACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x60))
4403 +#define PHY1RACPINT (*(volatile unsigned char *) (PHY1BASE+0x51))
4404 +
4405 +/* Phy 2 */
4406 +
4407 +#define PHY2BASE (PHY_BASE + 0x200000)
4408 +#define PHY2RST (*(volatile unsigned char *) (PHY2BASE)) /* reset */
4409 +#define PHY2CTRL (*(volatile unsigned char *) (PHY2BASE+0x5)) /* control */
4410 +#define PHY2RACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x50))
4411 +#define PHY2TACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x60))
4412 +#define PHY2RACPINT (*(volatile unsigned char *) (PHY2BASE+0x51))
4413 +
4414 +/*-------------------*/
4415 +/* Avalanche ATM SAR */
4416 +/*-------------------*/
4417 +
4418 +#define AVSAR_SYSCONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000000)) /* SAR system config register */
4419 +#define AVSAR_SYSSTATUS (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000004)) /* SAR system status register */
4420 +#define AVSAR_INT_ENABLE (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000008)) /* SAR interrupt enable register */
4421 +#define AVSAR_CONN_VPI_VCI (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000000c)) /* VPI/VCI connection config */
4422 +#define AVSAR_CONN_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000010)) /* Connection config register */
4423 +#define AVSAR_OAM_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018)) /* OAM configuration register */
4424 +
4425 +/* Transmit completion ring registers */
4426 +
4427 +#define AVSAR_TCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000100))
4428 +#define AVSAR_TCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000104))
4429 +#define AVSAR_TCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000108))
4430 +#define AVSAR_TCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000010c))
4431 +#define AVSAR_TCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000110))
4432 +#define AVSAR_TCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000114))
4433 +#define AVSAR_TCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000118))
4434 +#define AVSAR_TCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000011c))
4435 +#define AVSAR_TCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000120))
4436 +#define AVSAR_TCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000124))
4437 +#define AVSAR_TCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000128))
4438 +#define AVSAR_TCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000012c))
4439 +#define AVSAR_TCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000130))
4440 +#define AVSAR_TCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000134))
4441 +
4442 +/* Transmit Queue Packet registers */
4443 +#define AVSAR_TXQUEUE_PKT0 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000140))
4444 +#define AVSAR_TXQUEUE_PKT1 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000144))
4445 +#define AVSAR_TXQUEUE_PKT2 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000148))
4446 +#define AVSAR_TX_FLUSH (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000014C))
4447 +/* Receive completion ring registers */
4448 +
4449 +#define AVSAR_RCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000200))
4450 +#define AVSAR_RCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000204))
4451 +#define AVSAR_RCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000208))
4452 +#define AVSAR_RCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000020c))
4453 +#define AVSAR_RCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000210))
4454 +#define AVSAR_RCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000214))
4455 +#define AVSAR_RCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000218))
4456 +#define AVSAR_RCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000021c))
4457 +#define AVSAR_RCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000220))
4458 +#define AVSAR_RCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000224))
4459 +#define AVSAR_RCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000228))
4460 +#define AVSAR_RCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000022c))
4461 +#define AVSAR_RCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000230))
4462 +#define AVSAR_RCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000234))
4463 +
4464 +#define AVSAR_RXFBL_ADD0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000240)) /* Rx Free buffer list add 0 */
4465 +#define AVSAR_RXFBL_ADD1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000244)) /* Rx Free buffer list add 1 */
4466 +#define AVSAR_RXFBL_ADD2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000248)) /* Rx Free buffer list add 2 */
4467 +#define AVSAR_RXFBLSIZE_0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000028c)) /* Rx Free buffer list size 0 */
4468 +#define AVSAR_RXFBLSIZE_1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000029c)) /* Rx Free buffer list size 1 */
4469 +#define AVSAR_RXFBLSIZE_2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002ac)) /* Rx Free buffer list size 2 */
4470 +#define AVSAR_RXFBLSIZE_3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002bc)) /* Rx Free buffer list size 3 */
4471 +
4472 +
4473 +#if defined(CONFIG_MIPS_EVM3D) || defined(CONFIG_MIPS_AR5D01) || defined(CONFIG_MIPS_AR5W01)
4474 +
4475 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010480))
4476 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010484))
4477 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010488))
4478 +#define AVSAR_OAM_CPID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E0))
4479 +#define AVSAR_OAM_LLID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F0))
4480 +#define AVSAR_OAM_CPID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E4))
4481 +#define AVSAR_OAM_LLID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F4))
4482 +#define AVSAR_OAM_CPID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E8))
4483 +#define AVSAR_OAM_LLID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F8))
4484 +#define AVSAR_OAM_CPID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104EC))
4485 +#define AVSAR_OAM_LLID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104FC))
4486 +#define AVSAR_OAM_CORR_TAG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010500))
4487 +#define AVSAR_OAM_FAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010520))
4488 +#define AVSAR_OAM_NEAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010540))
4489 +#define AVSAR_OAM_CONFIG_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018))
4490 +#define AVSAR_FAIRNESS_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104B8))
4491 +#define AVSAR_UBR_PCR_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010490))
4492 +
4493 +
4494 +/*
4495 +
4496 +#define OAM_CPID_ADD 0xa30104e0
4497 +
4498 +#define OAM_LLID_ADD 0xa30104f0
4499 +
4500 +#define OAM_LLID_VAL 0xffffffff
4501 +
4502 +#define OAM_CORR_TAG 0xa3010500
4503 +
4504 +#define OAM_FAR_COUNT_ADD 0xa3010520
4505 +
4506 +#define OAM_NEAR_COUNT_ADD 0xa3010540
4507 +
4508 +#define OAM_CONFIG_REG_ADD 0xa3000018
4509 +*/
4510 +
4511 +
4512 +#else /* CONFIG_MIPS_EVM3 || CONFIG_MIPS_ACPEP */
4513 +
4514 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012000))
4515 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012004))
4516 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012008))
4517 +#define AVSAR_OAM_CPID (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012300))
4518 +
4519 +#endif /* CONFIG_MIPS_EVM3D || CONFIG_MIPS_AR5D01 || CONFIG_MIPS_AR5W01 */
4520 +
4521 +
4522 +#define AVSAR_STATE_RAM (ATM_SAR_BASE + 0x010000) /* SAR state RAM */
4523 +#define AVSAR_PDSP_BASE (ATM_SAR_BASE + 0x020000) /* SAR PDSP base address */
4524 +#define AVSAR_TXDMA_BASE (ATM_SAR_BASE + 0x030000) /* Transmit DMA state base */
4525 +#define AVSAR_TDMASTATE6 0x18 /* Transmit DMA state word 6 */
4526 +#define AVSAR_RXDMA_BASE (ATM_SAR_BASE + 0x040000) /* Receive DMA state base */
4527 +#define AVSAR_RDMASTATE0 0x0 /* Receive DMA state word 0 */
4528 +
4529 +/*------------------------------------------*/
4530 +/* DSL Interface */
4531 +/*------------------------------------------*/
4532 +
4533 +#define AVDSL_TX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000000))
4534 +#define AVDSL_RX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000004))
4535 +#define AVDSL_POLL (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000008))
4536 +
4537 +/* Fast */
4538 +
4539 +#define AVDSL_TX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000000C))
4540 +#define AVDSL_TX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000010))
4541 +#define AVDSL_TX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000014))
4542 +#define AVDSL_TX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000018))
4543 +#define AVDSL_RX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000001C))
4544 +#define AVDSL_RX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000020))
4545 +#define AVDSL_RX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000024))
4546 +#define AVDSL_RX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000028))
4547 +
4548 +/* Interleaved */
4549 +
4550 +#define AVDSL_TX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000002C))
4551 +#define AVDSL_TX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000030))
4552 +#define AVDSL_TX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000034))
4553 +#define AVDSL_TX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000038))
4554 +#define AVDSL_RX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000003C))
4555 +#define AVDSL_RX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000040))
4556 +#define AVDSL_RX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000044))
4557 +#define AVDSL_RX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000048))
4558 +
4559 +/*------------------------------------------*/
4560 +/* Broadband I/F */
4561 +/*------------------------------------------*/
4562 +
4563 +#define AVBBIF_BBIF_CNTRL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000000))
4564 +#define AVBBIF_ADDR_TRANS_0 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000004))
4565 +#define AVBBIF_ADDR_TRANS_1 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000008))
4566 +#define AVBBIF_ADDR_XB_MX_BL (*(volatile unsigned int *)(BBIF_CONTROL + 0x0000000C))
4567 +#define AVBBIF_INFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000010))
4568 +#define AVBBIF_OUTFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000014))
4569 +
4570 +#define AVBBIF_DISABLED 0x0
4571 +#define AVBBIF_LBT4040_INT 0x1
4572 +#define AVBBIF_XBUS 0x2
4573 +#define AVBBIF_LBT4040_EXT 0x4
4574 +
4575 +#define AVBBIF_ADDR_MASK0 0xff000000 /* handles upper bits of BBIF 0 address */
4576 +#define AVBBIF_ADDR_MASK1 0xff800000 /* handles upper bits of BBIF 1 address */
4577 +#define AVBBIF_TRANS_MASK 0xff000000
4578 +/*------------------------------------------*/
4579 +/* GPIO I/F */
4580 +/*------------------------------------------*/
4581 +
4582 +#define GPIO_DATA_INPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000000))
4583 +#define GPIO_DATA_OUTPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000004))
4584 +#define GPIO_DATA_DIR (*(volatile unsigned int *)(GPIO_BASE + 0x00000008)) /* 0=output 1=input */
4585 +#define GPIO_DATA_ENABLE (*(volatile unsigned int *)(GPIO_BASE + 0x0000000C)) /* 0=GPIO Mux 1=GPIO */
4586 +
4587 +#define GPIO_0 (1<<21)
4588 +#define GPIO_1 (1<<22)
4589 +#define GPIO_2 (1<<23)
4590 +#define GPIO_3 (1<<24)
4591 +#define EINT_1 (1<<18)
4592 +
4593 +/*
4594 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4595 + If you reset the GPIO interface all of the directions (i/o) of the UART B
4596 + interface pins are inputs and must be reconfigured so as not to lose the
4597 + serial console interface
4598 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4599 +*/
4600 +
4601 +/*------------------------------------------*/
4602 +/* CLK_CTRL */
4603 +/*------------------------------------------*/
4604 +#define PERIPH_CLK_CTL (*(volatile unsigned int *)(CLK_CTRL_BASE + 0x00000004))
4605 +
4606 +#define PCLK_0_HALF_VBUS (0<<16)
4607 +#define PCLK_EQ_INPUT (1<<16)
4608 +#define BBIF_CLK_HALF_VBUS (0<<17)
4609 +#define BBIF_CLK_EQ_VBUS (1<<17)
4610 +#define BBIF_CLK_EQ_BBCLK (3<<17)
4611 +#define DSP_MODCLK_DSPCLKI (0<<20)
4612 +#define DSP_MODCLK_REFCLKI (1<<20)
4613 +#define USB_CLK_EQ_USBCLKI (0<<21)
4614 +#define USB_CLK_EQ_REFCLKI (1<<21)
4615 +
4616 +/*------------------------------------------*/
4617 +/* PCI Control Registers */
4618 +/*------------------------------------------*/
4619 +#define PCIC_CONTROL (*(volatile unsigned int *)(PCI_CONFIG_BASE))
4620 +#define PCIC_CONTROL_CFG_DONE (1<<0)
4621 +#define PCIC_CONTROL_DIS_SLAVE_TO (1<<1)
4622 +#define PCIC_CONTROL_FORCE_DELAY_READ (1<<2)
4623 +#define PCIC_CONTROL_FORCE_DELAY_READ_LINE (1<<3)
4624 +#define PCIC_CONTROL_FORCE_DELAY_READ_MULT (1<<4)
4625 +#define PCIC_CONTROL_MEM_SPACE_EN (1<<5)
4626 +#define PCIC_CONTROL_MEM_MASK (1<<6)
4627 +#define PCIC_CONTROL_IO_SPACE_EN (1<<7)
4628 +#define PCIC_CONTROL_IO_MASK (1<<8)
4629 +/* PCIC_CONTROL_RESERVED (1<<9) */
4630 +#define PCIC_CONTROL_BASE0_EN (1<<10)
4631 +#define PCIC_CONTROL_BASE1_EN (1<<11)
4632 +#define PCIC_CONTROL_BASE2_EN (1<<12)
4633 +#define PCIC_CONTROL_HOLD_MASTER_WRITE (1<<13)
4634 +#define PCIC_CONTROL_ARBITER_EN (1<<14)
4635 +#define PCIC_INT_SOURCE (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000004))
4636 +#define PCIC_INT_SOURCE_PWR_MGMT (1<<0)
4637 +#define PCIC_INT_SOURCE_PCI_TARGET (1<<1)
4638 +#define PCIC_INT_SOURCE_PCI_MASTER (1<<2)
4639 +#define PCIC_INT_SOURCE_POWER_WAKEUP (1<<3)
4640 +#define PCIC_INT_SOURCE_PMEIN (1<<4)
4641 +/* PCIC_INT_SOURCE_RESERVED (1<<5) */
4642 +/* PCIC_INT_SOURCE_RESERVED (1<<6) */
4643 +#define PCIC_INT_SOURCE_PIC_INTA (1<<7)
4644 +#define PCIC_INT_SOURCE_PIC_INTB (1<<8)
4645 +#define PCIC_INT_SOURCE_PIC_INTC (1<<9)
4646 +#define PCIC_INT_SOURCE_PIC_INTD (1<<10)
4647 +#define PCIC_INT_SOURCE_SOFT_INT0 (1<<11)
4648 +#define PCIC_INT_SOURCE_SOFT_INT1 (1<<12)
4649 +#define PCIC_INT_SOURCE_SOFT_INT2 (1<<13)
4650 +#define PCIC_INT_SOURCE_SOFT_INT3 (1<<14)
4651 +#define PCIC_INT_CLEAR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000008))
4652 +#define PCIC_INT_CLEAR_PM (1<<0)
4653 +#define PCIC_INT_CLEAR_PCI_TARGET (1<<1)
4654 +#define PCIC_INT_CLEAR_PCI_MASTER (1<<2)
4655 +/* PCIC_INT_CLEAR_RESERVED (1<<3) */
4656 +#define PCIC_INT_CLEAR_PMEIN (1<<4)
4657 +/* PCIC_INT_CLEAR_RESERVED (1<<5) */
4658 +/* PCIC_INT_CLEAR_RESERVED (1<<6) */
4659 +#define PCIC_INT_CLEAR_PCI_INTA (1<<7)
4660 +#define PCIC_INT_CLEAR_PCI_INTB (1<<8)
4661 +#define PCIC_INT_CLEAR_PCI_INTC (1<<9)
4662 +#define PCIC_INT_CLEAR_PCI_INTD (1<<10)
4663 +#define PCIC_INT_CLEAR_SOFT_INT0 (1<<11)
4664 +#define PCIC_INT_CLEAR_SOFT_INT1 (1<<12)
4665 +#define PCIC_INT_CLEAR_SOFT_INT2 (1<<13)
4666 +#define PCIC_INT_CLEAR_SOFT_INT3 (1<<14)
4667 +#define PCIC_INT_EN_AVAL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000000c))
4668 +#define PCIC_INT_EN_AVAL_PM (1<<0)
4669 +#define PCIC_INT_EN_AVAL_PCI_TARGET (1<<1)
4670 +#define PCIC_INT_EN_AVAL_PCI_MASTER (1<<2)
4671 +/* PCIC_INT_EN_AVAL_RESERVED (1<<3) */
4672 +#define PCIC_INT_EN_AVAL_PMEIN (1<<4)
4673 +/* PCIC_INT_EN_AVAL_RESERVED (1<<5) */
4674 +/* PCIC_INT_EN_AVAL_RESERVED (1<<6) */
4675 +#define PCIC_INT_EN_AVAL_PCI_INTA (1<<7)
4676 +#define PCIC_INT_EN_AVAL_PCI_INTB (1<<8)
4677 +#define PCIC_INT_EN_AVAL_PCI_INTC (1<<9)
4678 +#define PCIC_INT_EN_AVAL_PCI_INTD (1<<10)
4679 +#define PCIC_INT_EN_AVAL_SOFT_INT0 (1<<11)
4680 +#define PCIC_INT_EN_AVAL_SOFT_INT1 (1<<12)
4681 +#define PCIC_INT_EN_AVAL_SOFT_INT2 (1<<13)
4682 +#define PCIC_INT_EN_AVAL_SOFT_INT3 (1<<14)
4683 +#define PCIC_INT_EN_PCI (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000010))
4684 +#define PCIC_INT_EN_PCI_PM (1<<0)
4685 +#define PCIC_INT_EN_PCI_PCI_TARGET (1<<1)
4686 +#define PCIC_INT_EN_PCI_PCI_MASTER (1<<2)
4687 +/* PCIC_INT_EN_PCI_RESERVED (1<<3) */
4688 +#define PCIC_INT_EN_PCI_PMEIN (1<<4)
4689 +/* PCIC_INT_EN_PCI_RESERVED (1<<5) */
4690 +/* PCIC_INT_EN_PCI_RESERVED (1<<6) */
4691 +#define PCIC_INT_EN_PCI_PCI_INTA (1<<7)
4692 +#define PCIC_INT_EN_PCI_PCI_INTB (1<<8)
4693 +#define PCIC_INT_EN_PCI_PCI_INTC (1<<9)
4694 +#define PCIC_INT_EN_PCI_PCI_INTD (1<<10)
4695 +#define PCIC_INT_EN_PCI_SOFT_INT0 (1<<11)
4696 +#define PCIC_INT_EN_PCI_SOFT_INT1 (1<<12)
4697 +#define PCIC_INT_EN_PCI_SOFT_INT2 (1<<13)
4698 +#define PCIC_INT_EN_PCI_SOFT_INT3 (1<<14)
4699 +#define PCIC_INT_SWSET (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000014))
4700 +#define PCIC_INT_SWSET_SOFT_INT0 (1<<0)
4701 +#define PCIC_INT_SWSET_SOFT_INT1 (1<<1)
4702 +#define PCIC_INT_SWSET_SOFT_INT2 (1<<2)
4703 +#define PCIC_INT_SWSET_SOFT_INT3 (1<<3)
4704 +#define PCIC_PM_CTL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000018))
4705 +#define PCIC_PM_CTL_PWR_STATE_MASK (0x02)
4706 +/* PCIC_PM_CTL_RESERVED (1<<2) */
4707 +/* PCIC_PM_CTL_RESERVED (1<<3) */
4708 +/* PCIC_PM_CTL_RESERVED (1<<4) */
4709 +/* PCIC_PM_CTL_RESERVED (1<<5) */
4710 +/* PCIC_PM_CTL_RESERVED (1<<6) */
4711 +/* PCIC_PM_CTL_RESERVED (1<<7) */
4712 +/* PCIC_PM_CTL_RESERVED (1<<8) */
4713 +/* PCIC_PM_CTL_RESERVED (1<<9) */
4714 +#define PCIC_PM_CTL_PWR_SUPPORT (1<<10)
4715 +#define PCIC_PM_CTL_PMEIN (1<<11)
4716 +#define PCIC_PM_CTL_CAP_MASK (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x0000001a))
4717 +#define PCIC_PM_CONSUME (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000001c))
4718 +#define PCIC_PM_CONSUME_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001c))
4719 +#define PCIC_PM_CONSUME_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001d))
4720 +#define PCIC_PM_CONSUME_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001e))
4721 +#define PCIC_PM_CONSUME_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001f))
4722 +#define PCIC_PM_DISSAPATED (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000020))
4723 +#define PCIC_PM_DISSAPATED_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000020))
4724 +#define PCIC_PM_DISSAPATED_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000021))
4725 +#define PCIC_PM_DISSAPATED_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000022))
4726 +#define PCIC_PM_DISSAPATED_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000023))
4727 +#define PCIC_PM_DATA_SCALE (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x00000024))
4728 +#define PCIC_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000028))
4729 +#define PCIC_SUB_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000002c))
4730 +#define PCIC_CLASS_REV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000030))
4731 +#define PCIC_MAX_MIN (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000034))
4732 +#define PCIC_MAST_MEM_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000003c))
4733 +#define PCIC_MAST_MEM_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000040))
4734 +#define PCIC_MAST_MEM_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000044))
4735 +#define PCIC_SLAVE_MASK0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000004c))
4736 +#define PCIC_SLAVE_MASK1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000050))
4737 +#define PCIC_SLAVE_MASK2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000054))
4738 +#define PCIC_SLAVE_BASE_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000058))
4739 +#define PCIC_SLAVE_BASE_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000005c))
4740 +#define PCIC_SLAVE_BASE_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000060))
4741 +#define PCIC_CONF_COMMAND (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000090))
4742 +#define PCIC_CONF_ADDR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000094))
4743 +#define PCIC_CONF_DATA (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000098))
4744 +
4745 +/*------------------------------------------*/
4746 +/* IIC_INTERFACE */
4747 +/*------------------------------------------*/
4748 +#define I2C_DATA_HI (*(volatile unsigned int *)(I2C_BASE + 0x0))
4749 +#define I2C_DATA_LOW (*(volatile unsigned int *)(I2C_BASE + 0x4))
4750 +#define I2C_CONFIG (*(volatile unsigned int *)(I2C_BASE + 0x8))
4751 +#define I2C_DATA_READ (*(volatile unsigned int *)(I2C_BASE + 0xC))
4752 +#define I2C_CLOCK_DIV (*(volatile unsigned int *)(I2C_BASE + 0x10))
4753 +
4754 +#define I2CWRITE 0x200
4755 +#define I2CREAD 0x300
4756 +#define I2C_END_BURST 0x400
4757 +
4758 +/* read bits */
4759 +#define I2C_READ_ERROR 0x8000
4760 +#define I2C_READ_COMPLETE 0x4000
4761 +#define I2C_READ_BUSY 0x2000
4762 +
4763 +/* device types */
4764 +#define I2C_IO_EXPANDER 0x2
4765 +#define I2C_RTC 0xd
4766 +
4767 +/* device Addresses on I2C bus (EVM3) */
4768 +#define SEVEN_SEGMENT_DISP 0x23 /* Device type = 0x2, Addr = 3 */
4769 +#define EVM3_RTC 0xd0 /* Device type = 0xd, Addr = 0 */
4770 +#define EVM3_RTC_I2C_ADDR 0x0
4771 +
4772 +/*------------------------------------------*/
4773 +/* Ethernet MAC register offset definitions */
4774 +/*------------------------------------------*/
4775 +#define VMAC_DMACONFIG(X) (*(volatile unsigned int *)(X + 0x00000000))
4776 +#define VMAC_INTSTS(X) (*(volatile unsigned int *)(X + 0x00000004))
4777 +#define VMAC_INTMASK(X) (*(volatile unsigned int *)(X + 0x00000008))
4778 +
4779 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
4780 +#define VMAC_STATSBASE(X) (*(volatile unsigned int *)(X + 0x00000400))
4781 +
4782 +#define VMAC_TCRPTR(X) (*(volatile unsigned int *)(X + 0x00000100))
4783 +#define VMAC_TCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000104))
4784 +#define VMAC_TCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000108))
4785 +#define VMAC_TCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000010C))
4786 +#define VMAC_TCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000110))
4787 +#define VMAC_TCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000114))
4788 +#define VMAC_TCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000118))
4789 +#define VMAC_TXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000011c))
4790 +
4791 +
4792 +#define VMAC_TDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000120))
4793 +#define VMAC_TDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000124))
4794 +#define VMAC_TDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000128))
4795 +#define VMAC_TDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000012C))
4796 +#define VMAC_TDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000130))
4797 +#define VMAC_TDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000134))
4798 +#define VMAC_TDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000138))
4799 +#define VMAC_TDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000013C))
4800 +#define VMAC_TXPADDCNT(X) (*(volatile unsigned int *)(X + 0x00000140))
4801 +#define VMAC_TXPADDSTART(X) (*(volatile unsigned int *)(X + 0x00000144))
4802 +#define VMAC_TXPADDEND(X) (*(volatile unsigned int *)(X + 0x00000148))
4803 +#define VMAC_TXQFLUSH(X) (*(volatile unsigned int *)(X + 0x0000014C))
4804 +
4805 +#define VMAC_RCRPTR(X) (*(volatile unsigned int *)(X + 0x00000200))
4806 +#define VMAC_RCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000204))
4807 +#define VMAC_RCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000208))
4808 +#define VMAC_RCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000020C))
4809 +#define VMAC_RCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000210))
4810 +#define VMAC_RCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000214))
4811 +#define VMAC_RCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000218))
4812 +#define VMAC_RXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000021c))
4813 +
4814 +#define VMAC_RDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000220))
4815 +#define VMAC_RDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000224))
4816 +#define VMAC_RDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000228))
4817 +#define VMAC_RDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000022C))
4818 +#define VMAC_RDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000230))
4819 +#define VMAC_RDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000234))
4820 +#define VMAC_RDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000238))
4821 +#define VMAC_RDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000023C))
4822 +#define VMAC_FBLADDCNT(X) (*(volatile unsigned int *)(X + 0x00000240))
4823 +#define VMAC_FBLADDSTART(X) (*(volatile unsigned int *)(X + 0x00000244))
4824 +#define VMAC_FBLADDEND(X) (*(volatile unsigned int *)(X + 0x00000248))
4825 +#define VMAC_RXONOFF(X) (*(volatile unsigned int *)(X + 0x0000024C))
4826 +
4827 +#define VMAC_FBL0NEXTD(X) (*(volatile unsigned int *)(X + 0x00000280))
4828 +#define VMAC_FBL0LASTD(X) (*(volatile unsigned int *)(X + 0x00000284))
4829 +#define VMAC_FBL0COUNTD(X) (*(volatile unsigned int *)(X + 0x00000288))
4830 +#define VMAC_FBL0BUFSIZE(X) (*(volatile unsigned int *)(X + 0x0000028C))
4831 +
4832 +#define VMAC_MACCONTROL(X) (*(volatile unsigned int *)(X + 0x00000300))
4833 +#define VMAC_MACSTATUS(X) (*(volatile unsigned int *)(X + 0x00000304))
4834 +#define VMAC_MACADDRHI(X) (*(volatile unsigned int *)(X + 0x00000308))
4835 +#define VMAC_MACADDRLO(X) (*(volatile unsigned int *)(X + 0x0000030C))
4836 +#define VMAC_MACHASH1(X) (*(volatile unsigned int *)(X + 0x00000310))
4837 +#define VMAC_MACHASH2(X) (*(volatile unsigned int *)(X + 0x00000314))
4838 +
4839 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
4840 +#define VMAC_BOFTEST(X) (*(volatile unsigned int *)(X + 0x00000344))
4841 +#define VMAC_PACTEST(X) (*(volatile unsigned int *)(X + 0x00000348))
4842 +#define VMAC_PAUSEOP(X) (*(volatile unsigned int *)(X + 0x0000034C))
4843 +
4844 +#define VMAC_MDIOCONTROL(X) (*(volatile unsigned int *)(X + 0x00000380))
4845 +#define VMAC_MDIOUSERACCESS(X) (*(volatile unsigned int *)(X +0x00000384))
4846 +#define VMAC_MDIOACK(X) (*(volatile unsigned int *)(X + 0x00000388))
4847 +#define VMAC_MDIOLINK(X) (*(volatile unsigned int *)(X + 0x0000038C))
4848 +#define VMAC_MDIOMACPHY(X) (*(volatile unsigned int *)(X + 0x00000390))
4849 +
4850 +#define VMAC_STATS_BASE(X) (X + 0x00000400)
4851 +
4852 +#endif __AVALANCHE_REGS_H
4853 +
4854 +
4855 +
4856 +
4857 +
4858 +
4859 diff -urN linux.old/include/asm-mips/ar7/if_port.h linux.dev/include/asm-mips/ar7/if_port.h
4860 --- linux.old/include/asm-mips/ar7/if_port.h 1970-01-01 01:00:00.000000000 +0100
4861 +++ linux.dev/include/asm-mips/ar7/if_port.h 2005-07-12 02:59:26.201667160 +0200
4862 @@ -0,0 +1,26 @@
4863 +/*******************************************************************************
4864 + * FILE PURPOSE: Interface port id Header file
4865 + *******************************************************************************
4866 + * FILE NAME: if_port.h
4867 + *
4868 + * DESCRIPTION: Header file carrying information about port ids of interfaces
4869 + *
4870 + *
4871 + * (C) Copyright 2003, Texas Instruments, Inc
4872 + ******************************************************************************/
4873 +#ifndef _IF_PORT_H_
4874 +#define _IF_PORT_H_
4875 +
4876 +#define AVALANCHE_CPMAC_LOW_PORT_ID 0
4877 +#define AVALANCHE_CPMAC_HIGH_PORT_ID 1
4878 +#define AVALANCHE_USB_PORT_ID 2
4879 +#define AVALANCHE_WLAN_PORT_ID 3
4880 +
4881 +
4882 +#define AVALANCHE_MARVELL_BASE_PORT_ID 4
4883 +
4884 +/* The marvell ports occupy port ids from 4 to 8 */
4885 +/* so the next port id number should start at 9 */
4886 +
4887 +
4888 +#endif /* _IF_PORT_H_ */
4889 diff -urN linux.old/include/asm-mips/ar7/sangam_boards.h linux.dev/include/asm-mips/ar7/sangam_boards.h
4890 --- linux.old/include/asm-mips/ar7/sangam_boards.h 1970-01-01 01:00:00.000000000 +0100
4891 +++ linux.dev/include/asm-mips/ar7/sangam_boards.h 2005-07-12 02:59:26.201667160 +0200
4892 @@ -0,0 +1,77 @@
4893 +#ifndef _SANGAM_BOARDS_H
4894 +#define _SANGAM_BOARDS_H
4895 +
4896 +// Let us define board specific information here.
4897 +
4898 +
4899 +#if defined(CONFIG_AR7DB)
4900 +
4901 +#define AFECLK_FREQ 35328000
4902 +#define REFCLK_FREQ 25000000
4903 +#define OSC3_FREQ 24000000
4904 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
4905 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555
4906 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
4907 +
4908 +#endif
4909 +
4910 +
4911 +#if defined(CONFIG_AR7RD)
4912 +#define AFECLK_FREQ 35328000
4913 +#define REFCLK_FREQ 25000000
4914 +#define OSC3_FREQ 24000000
4915 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
4916 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
4917 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
4918 +#endif
4919 +
4920 +
4921 +#if defined(CONFIG_AR7WI)
4922 +#define AFECLK_FREQ 35328000
4923 +#define REFCLK_FREQ 25000000
4924 +#define OSC3_FREQ 24000000
4925 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
4926 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
4927 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
4928 +#endif
4929 +
4930 +
4931 +#if defined(CONFIG_AR7V)
4932 +#define AFECLK_FREQ 35328000
4933 +#define REFCLK_FREQ 25000000
4934 +#define OSC3_FREQ 24000000
4935 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
4936 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
4937 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
4938 +#endif
4939 +
4940 +
4941 +#if defined(CONFIG_AR7WRD)
4942 +#define AFECLK_FREQ 35328000
4943 +#define REFCLK_FREQ 25000000
4944 +#define OSC3_FREQ 24000000
4945 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
4946 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000
4947 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
4948 +#endif
4949 +
4950 +
4951 +#if defined(CONFIG_AR7VWI)
4952 +#define AFECLK_FREQ 35328000
4953 +#define REFCLK_FREQ 25000000
4954 +#define OSC3_FREQ 24000000
4955 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
4956 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000
4957 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
4958 +#endif
4959 +
4960 +
4961 +#if defined CONFIG_SEAD2
4962 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0xAAAAAAAA
4963 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555
4964 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0
4965 +#include <asm/mips-boards/sead.h>
4966 +#endif
4967 +
4968 +
4969 +#endif
4970 diff -urN linux.old/include/asm-mips/ar7/sangam.h linux.dev/include/asm-mips/ar7/sangam.h
4971 --- linux.old/include/asm-mips/ar7/sangam.h 1970-01-01 01:00:00.000000000 +0100
4972 +++ linux.dev/include/asm-mips/ar7/sangam.h 2005-07-12 02:59:26.201667160 +0200
4973 @@ -0,0 +1,180 @@
4974 +#ifndef _SANGAM_H_
4975 +#define _SANGAM_H_
4976 +
4977 +#include <linux/config.h>
4978 +#include <asm/addrspace.h>
4979 +
4980 +/*----------------------------------------------------
4981 + * Sangam's Module Base Addresses
4982 + *--------------------------------------------------*/
4983 +#define AVALANCHE_ADSL_SUB_SYS_MEM_BASE (KSEG1ADDR(0x01000000)) /* AVALANCHE ADSL Mem Base */
4984 +#define AVALANCHE_BROADBAND_INTERFACE__BASE (KSEG1ADDR(0x02000000)) /* AVALANCHE BBIF */
4985 +#define AVALANCHE_ATM_SAR_BASE (KSEG1ADDR(0x03000000)) /* AVALANCHE ATM SAR */
4986 +#define AVALANCHE_USB_SLAVE_BASE (KSEG1ADDR(0x03400000)) /* AVALANCHE USB SLAVE */
4987 +#define AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x04000000)) /* AVALANCHE VLYNQ 0 Mem map */
4988 +#define AVALANCHE_LOW_CPMAC_BASE (KSEG1ADDR(0x08610000)) /* AVALANCHE CPMAC 0 */
4989 +#define AVALANCHE_EMIF_CONTROL_BASE (KSEG1ADDR(0x08610800)) /* AVALANCHE EMIF */
4990 +#define AVALANCHE_GPIO_BASE (KSEG1ADDR(0x08610900)) /* AVALANCHE GPIO */
4991 +#define AVALANCHE_CLOCK_CONTROL_BASE (KSEG1ADDR(0x08610A00)) /* AVALANCHE Clock Control */
4992 +#define AVALANCHE_WATCHDOG_TIMER_BASE (KSEG1ADDR(0x08610B00)) /* AVALANCHE Watch Dog Timer */
4993 +#define AVALANCHE_TIMER0_BASE (KSEG1ADDR(0x08610C00)) /* AVALANCHE Timer 1 */
4994 +#define AVALANCHE_TIMER1_BASE (KSEG1ADDR(0x08610D00)) /* AVALANCHE Timer 2 */
4995 +#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
4996 +#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 0 */
4997 +#define AVALANCHE_I2C_BASE (KSEG1ADDR(0x08611000)) /* AVALANCHE I2C */
4998 +#define AVALANCHE_USB_SLAVE_CONTROL_BASE (KSEG1ADDR(0x08611200)) /* AVALANCHE USB DMA */
4999 +#define AVALANCHE_MCDMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* AVALANCHE MC DMA 0 (channels 0-3) */
5000 +#define AVALANCHE_RESET_CONTROL_BASE (KSEG1ADDR(0x08611600)) /* AVALANCHE Reset Control */
5001 +#define AVALANCHE_BIST_CONTROL_BASE (KSEG1ADDR(0x08611700)) /* AVALANCHE BIST Control */
5002 +#define AVALANCHE_LOW_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611800)) /* AVALANCHE VLYNQ0 Control */
5003 +#define AVALANCHE_DEVICE_CONFIG_LATCH_BASE (KSEG1ADDR(0x08611A00)) /* AVALANCHE Device Config Latch */
5004 +#define AVALANCHE_HIGH_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611C00)) /* AVALANCHE VLYNQ1 Control */
5005 +#define AVALANCHE_MDIO_BASE (KSEG1ADDR(0x08611E00)) /* AVALANCHE MDIO */
5006 +#define AVALANCHE_FSER_BASE (KSEG1ADDR(0x08612000)) /* AVALANCHE FSER base */
5007 +#define AVALANCHE_INTC_BASE (KSEG1ADDR(0x08612400)) /* AVALANCHE INTC */
5008 +#define AVALANCHE_HIGH_CPMAC_BASE (KSEG1ADDR(0x08612800)) /* AVALANCHE CPMAC 1 */
5009 +#define AVALANCHE_HIGH_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x0C000000)) /* AVALANCHE VLYNQ 1 Mem map */
5010 +
5011 +#define AVALANCHE_SDRAM_BASE 0x14000000UL
5012 +
5013 +
5014 +/*----------------------------------------------------
5015 + * Sangam Interrupt Map (Primary Interrupts)
5016 + *--------------------------------------------------*/
5017 +
5018 +#define AVALANCHE_UNIFIED_SECONDARY_INT 0
5019 +#define AVALANCHE_EXT_INT_0 1
5020 +#define AVALANCHE_EXT_INT_1 2
5021 +/* Line# 3 to 4 are reserved */
5022 +#define AVALANCHE_TIMER_0_INT 5
5023 +#define AVALANCHE_TIMER_1_INT 6
5024 +#define AVALANCHE_UART0_INT 7
5025 +#define AVALANCHE_UART1_INT 8
5026 +#define AVALANCHE_DMA_INT0 9
5027 +#define AVALANCHE_DMA_INT1 10
5028 +/* Line# 11 to 14 are reserved */
5029 +#define AVALANCHE_ATM_SAR_INT 15
5030 +/* Line# 16 to 18 are reserved */
5031 +#define AVALANCHE_LOW_CPMAC_INT 19
5032 +/* Line# 20 is reserved */
5033 +#define AVALANCHE_LOW_VLYNQ_INT 21
5034 +#define AVALANCHE_CODEC_WAKEUP_INT 22
5035 +/* Line# 23 is reserved */
5036 +#define AVALANCHE_USB_SLAVE_INT 24
5037 +#define AVALANCHE_HIGH_VLYNQ_INT 25
5038 +/* Line# 26 to 27 are reserved */
5039 +#define AVALANCHE_UNIFIED_PHY_INT 28
5040 +#define AVALANCHE_I2C_INT 29
5041 +#define AVALANCHE_DMA_INT2 30
5042 +#define AVALANCHE_DMA_INT3 31
5043 +/* Line# 32 is reserved */
5044 +#define AVALANCHE_HIGH_CPMAC_INT 33
5045 +/* Line# 34 to 36 is reserved */
5046 +#define AVALANCHE_VDMA_VT_RX_INT 37
5047 +#define AVALANCHE_VDMA_VT_TX_INT 38
5048 +#define AVALANCHE_ADSL_SUB_SYSTEM_INT 39
5049 +
5050 +
5051 +#define AVALANCHE_EMIF_INT 47
5052 +
5053 +
5054 +
5055 +/*-----------------------------------------------------------
5056 + * Sangam's Reset Bits
5057 + *---------------------------------------------------------*/
5058 +
5059 +#define AVALANCHE_UART0_RESET_BIT 0
5060 +#define AVALANCHE_UART1_RESET_BIT 1
5061 +#define AVALANCHE_I2C_RESET_BIT 2
5062 +#define AVALANCHE_TIMER0_RESET_BIT 3
5063 +#define AVALANCHE_TIMER1_RESET_BIT 4
5064 +/* Reset bit 5 is reserved. */
5065 +#define AVALANCHE_GPIO_RESET_BIT 6
5066 +#define AVALANCHE_ADSL_SUB_SYS_RESET_BIT 7
5067 +#define AVALANCHE_USB_SLAVE_RESET_BIT 8
5068 +#define AVALANCHE_ATM_SAR_RESET_BIT 9
5069 +/* Reset bit 10 is reserved. */
5070 +#define AVALANCHE_VDMA_VT_RESET_BIT 11
5071 +#define AVALANCHE_FSER_RESET_BIT 12
5072 +/* Reset bit 13 to 15 are reserved */
5073 +#define AVALANCHE_HIGH_VLYNQ_RESET_BIT 16
5074 +#define AVALANCHE_LOW_CPMAC_RESET_BIT 17
5075 +#define AVALANCHE_MCDMA_RESET_BIT 18
5076 +#define AVALANCHE_BIST_RESET_BIT 19
5077 +#define AVALANCHE_LOW_VLYNQ_RESET_BIT 20
5078 +#define AVALANCHE_HIGH_CPMAC_RESET_BIT 21
5079 +#define AVALANCHE_MDIO_RESET_BIT 22
5080 +#define AVALANCHE_ADSL_SUB_SYS_DSP_RESET_BIT 23
5081 +/* Reset bit 24 to 25 are reserved */
5082 +#define AVALANCHE_LOW_EPHY_RESET_BIT 26
5083 +/* Reset bit 27 to 31 are reserved */
5084 +
5085 +
5086 +#define AVALANCHE_POWER_MODULE_USBSP 0
5087 +#define AVALANCHE_POWER_MODULE_WDTP 1
5088 +#define AVALANCHE_POWER_MODULE_UT0P 2
5089 +#define AVALANCHE_POWER_MODULE_UT1P 3
5090 +#define AVALANCHE_POWER_MODULE_IICP 4
5091 +#define AVALANCHE_POWER_MODULE_VDMAP 5
5092 +#define AVALANCHE_POWER_MODULE_GPIOP 6
5093 +#define AVALANCHE_POWER_MODULE_VLYNQ1P 7
5094 +#define AVALANCHE_POWER_MODULE_SARP 8
5095 +#define AVALANCHE_POWER_MODULE_ADSLP 9
5096 +#define AVALANCHE_POWER_MODULE_EMIFP 10
5097 +#define AVALANCHE_POWER_MODULE_ADSPP 12
5098 +#define AVALANCHE_POWER_MODULE_RAMP 13
5099 +#define AVALANCHE_POWER_MODULE_ROMP 14
5100 +#define AVALANCHE_POWER_MODULE_DMAP 15
5101 +#define AVALANCHE_POWER_MODULE_BISTP 16
5102 +#define AVALANCHE_POWER_MODULE_TIMER0P 18
5103 +#define AVALANCHE_POWER_MODULE_TIMER1P 19
5104 +#define AVALANCHE_POWER_MODULE_EMAC0P 20
5105 +#define AVALANCHE_POWER_MODULE_EMAC1P 22
5106 +#define AVALANCHE_POWER_MODULE_EPHYP 24
5107 +#define AVALANCHE_POWER_MODULE_VLYNQ0P 27
5108 +
5109 +
5110 +
5111 +
5112 +
5113 +/*
5114 + * Sangam board vectors
5115 + */
5116 +
5117 +#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
5118 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
5119 +
5120 +/*-----------------------------------------------------------------------------
5121 + * Sangam's system register.
5122 + *
5123 + *---------------------------------------------------------------------------*/
5124 +#define AVALANCHE_DCL_BOOTCR (KSEG1ADDR(0x08611A00))
5125 +#define AVALANCHE_EMIF_SDRAM_CFG (AVALANCHE_EMIF_CONTROL_BASE + 0x8)
5126 +#define AVALANCHE_RST_CTRL_PRCR (KSEG1ADDR(0x08611600))
5127 +#define AVALANCHE_RST_CTRL_SWRCR (KSEG1ADDR(0x08611604))
5128 +#define AVALANCHE_RST_CTRL_RSR (KSEG1ADDR(0x08611600))
5129 +
5130 +#define AVALANCHE_POWER_CTRL_PDCR (KSEG1ADDR(0x08610A00))
5131 +#define AVALANCHE_WAKEUP_CTRL_WKCR (KSEG1ADDR(0x08610A0C))
5132 +
5133 +#define AVALANCHE_GPIO_DATA_IN (AVALANCHE_GPIO_BASE + 0x0)
5134 +#define AVALANCHE_GPIO_DATA_OUT (AVALANCHE_GPIO_BASE + 0x4)
5135 +#define AVALANCHE_GPIO_DIR (AVALANCHE_GPIO_BASE + 0x8)
5136 +#define AVALANCHE_GPIO_ENBL (AVALANCHE_GPIO_BASE + 0xC)
5137 +#define AVALANCHE_CVR (AVALANCHE_GPIO_BASE + 0x14)
5138 +
5139 +/*
5140 + * Yamon Prom print address.
5141 + */
5142 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
5143 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
5144 +#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
5145 +
5146 +#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
5147 +
5148 +#define AVALANCHE_GPIO_PIN_COUNT 32
5149 +#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0}
5150 +
5151 +#include "sangam_boards.h"
5152 +
5153 +#endif /*_SANGAM_H_ */
5154 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_err.h linux.dev/include/asm-mips/ar7/tnetd73xx_err.h
5155 --- linux.old/include/asm-mips/ar7/tnetd73xx_err.h 1970-01-01 01:00:00.000000000 +0100
5156 +++ linux.dev/include/asm-mips/ar7/tnetd73xx_err.h 2005-07-12 03:01:26.109438408 +0200
5157 @@ -0,0 +1,42 @@
5158 +/******************************************************************************
5159 + * FILE PURPOSE: TNETD73xx Error Definations Header File
5160 + ******************************************************************************
5161 + * FILE NAME: tnetd73xx_err.h
5162 + *
5163 + * DESCRIPTION: Error definations for TNETD73XX
5164 + *
5165 + * REVISION HISTORY:
5166 + * 27 Nov 02 - PSP TII
5167 + *
5168 + * (C) Copyright 2002, Texas Instruments, Inc
5169 + *******************************************************************************/
5170 +
5171 +
5172 +#ifndef __TNETD73XX_ERR_H__
5173 +#define __TNETD73XX_ERR_H__
5174 +
5175 +typedef enum TNETD73XX_ERR_t
5176 +{
5177 + TNETD73XX_ERR_OK = 0, /* OK or SUCCESS */
5178 + TNETD73XX_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
5179 +
5180 + /* Pointers and args */
5181 + TNETD73XX_ERR_INVARG = -2, /* Invaild argument to the call */
5182 + TNETD73XX_ERR_NULLPTR = -3, /* NULL pointer */
5183 + TNETD73XX_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
5184 +
5185 + /* Memory issues */
5186 + TNETD73XX_ERR_ALLOC_FAIL = -10, /* allocation failed */
5187 + TNETD73XX_ERR_FREE_FAIL = -11, /* free failed */
5188 + TNETD73XX_ERR_MEM_CORRUPT = -12, /* corrupted memory */
5189 + TNETD73XX_ERR_BUF_LINK = -13, /* buffer linking failed */
5190 +
5191 + /* Device issues */
5192 + TNETD73XX_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
5193 + TNETD73XX_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
5194 +
5195 + TNETD73XX_ERR_INVID = -30 /* Invalid ID */
5196 +
5197 +} TNETD73XX_ERR;
5198 +
5199 +#endif /* __TNETD73XX_ERR_H__ */
5200 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx.h linux.dev/include/asm-mips/ar7/tnetd73xx.h
5201 --- linux.old/include/asm-mips/ar7/tnetd73xx.h 1970-01-01 01:00:00.000000000 +0100
5202 +++ linux.dev/include/asm-mips/ar7/tnetd73xx.h 2005-07-12 03:01:26.110438256 +0200
5203 @@ -0,0 +1,338 @@
5204 +/******************************************************************************
5205 + * FILE PURPOSE: TNETD73xx Common Header File
5206 + ******************************************************************************
5207 + * FILE NAME: tnetd73xx.h
5208 + *
5209 + * DESCRIPTION: shared typedef's, constants and API for TNETD73xx
5210 + *
5211 + * REVISION HISTORY:
5212 + * 27 Nov 02 - PSP TII
5213 + *
5214 + * (C) Copyright 2002, Texas Instruments, Inc
5215 + *******************************************************************************/
5216 +
5217 +/*
5218 + *
5219 + *
5220 + * These are const, typedef, and api definitions for tnetd73xx.
5221 + *
5222 + * NOTES:
5223 + * 1. This file may be included into both C and Assembly files.
5224 + * - for .s files, please do #define _ASMLANGUAGE in your ASM file to
5225 + * avoid C data types (typedefs) below;
5226 + * - for .c files, you don't have to do anything special.
5227 + *
5228 + * 2. This file has a number of sections for each SOC subsystem. When adding
5229 + * a new constant, find the subsystem you are working on and follow the
5230 + * name pattern. If you are adding another typedef for your interface, please,
5231 + * place it with other typedefs and function prototypes.
5232 + *
5233 + * 3. Please, DO NOT add any macros or types that are local to a subsystem to avoid
5234 + * cluttering. Include such items directly into the module's .c file or have a
5235 + * local .h file to pass data between smaller modules. This file defines only
5236 + * shared items.
5237 + */
5238 +
5239 +#ifndef __TNETD73XX_H__
5240 +#define __TNETD73XX_H__
5241 +
5242 +#ifndef _ASMLANGUAGE /* This part not for assembly language */
5243 +
5244 +extern unsigned int tnetd73xx_mips_freq;
5245 +extern unsigned int tnetd73xx_vbus_freq;
5246 +
5247 +#include "tnetd73xx_err.h"
5248 +
5249 +#endif /* _ASMLANGUAGE */
5250 +
5251 +
5252 +/*******************************************************************************************
5253 +* Emerald core specific
5254 +******************************************************************************************** */
5255 +
5256 +#ifdef BIG_ENDIAN
5257 +#elif defined(LITTLE_ENDIAN)
5258 +#else
5259 +#error Need to define endianism
5260 +#endif
5261 +
5262 +#ifndef KSEG_MSK
5263 +#define KSEG_MSK 0xE0000000 /* Most significant 3 bits denote kseg choice */
5264 +#endif
5265 +
5266 +#ifndef KSEG_INV_MASK
5267 +#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
5268 +#endif
5269 +
5270 +#ifndef KSEG0_BASE
5271 +#define KSEG0_BASE 0x80000000
5272 +#endif
5273 +
5274 +#ifndef KSEG1_BASE
5275 +#define KSEG1_BASE 0xA0000000
5276 +#endif
5277 +
5278 +#ifndef KSEG0
5279 +#define KSEG0(addr) (((__u32)(addr) & ~KSEG_MSK) | KSEG0_BASE)
5280 +#endif
5281 +
5282 +#ifndef KSEG1
5283 +#define KSEG1(addr) (((__u32)(addr) & ~KSEG_MSK) | KSEG1_BASE)
5284 +#endif
5285 +
5286 +#ifndef KUSEG
5287 +#define KUSEG(addr) ((__u32)(addr) & ~KSEG_MSK)
5288 +#endif
5289 +
5290 +#ifndef PHYS_ADDR
5291 +#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
5292 +#endif
5293 +
5294 +#ifndef PHYS_TO_K0
5295 +#define PHYS_TO_K0(addr) (PHYS_ADDR(addr)|KSEG0_BASE)
5296 +#endif
5297 +
5298 +#ifndef PHYS_TO_K1
5299 +#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
5300 +#endif
5301 +
5302 +#ifndef REG8_ADDR
5303 +#define REG8_ADDR(addr) (volatile __u8 *)(PHYS_TO_K1(addr))
5304 +#define REG8_DATA(addr) (*(volatile __u8 *)(PHYS_TO_K1(addr)))
5305 +#define REG8_WRITE(addr, data) REG8_DATA(addr) = data;
5306 +#define REG8_READ(addr, data) data = (__u8) REG8_DATA(addr);
5307 +#endif
5308 +
5309 +#ifndef REG16_ADDR
5310 +#define REG16_ADDR(addr) (volatile __u16 *)(PHYS_TO_K1(addr))
5311 +#define REG16_DATA(addr) (*(volatile __u16 *)(PHYS_TO_K1(addr)))
5312 +#define REG16_WRITE(addr, data) REG16_DATA(addr) = data;
5313 +#define REG16_READ(addr, data) data = (__u16) REG16_DATA(addr);
5314 +#endif
5315 +
5316 +#ifndef REG32_ADDR
5317 +#define REG32_ADDR(addr) (volatile __u32 *)(PHYS_TO_K1(addr))
5318 +#define REG32_DATA(addr) (*(volatile __u32 *)(PHYS_TO_K1(addr)))
5319 +#define REG32_WRITE(addr, data) REG32_DATA(addr) = data;
5320 +#define REG32_READ(addr, data) data = (__u32) REG32_DATA(addr);
5321 +#endif
5322 +
5323 +#ifdef _LINK_KSEG0_ /* Application is linked into KSEG0 space */
5324 +#define VIRT_ADDR(addr) PHYS_TO_K0(PHYS_ADDR(addr))
5325 +#endif
5326 +
5327 +#ifdef _LINK_KSEG1_ /* Application is linked into KSEG1 space */
5328 +#define VIRT_ADDR(addr) PHYS_TO_K1(PHYS_ADDR(addr))
5329 +#endif
5330 +
5331 +#if !defined(_LINK_KSEG0_) && !defined(_LINK_KSEG1_)
5332 +#error You must define _LINK_KSEG0_ or _LINK_KSEG1_ to compile the code.
5333 +#endif
5334 +
5335 +/* TNETD73XX chip definations */
5336 +
5337 +#define FREQ_1MHZ 1000000
5338 +#define TNETD73XX_MIPS_FREQ tnetd73xx_mips_freq /* CPU clock frequency */
5339 +#define TNETD73XX_VBUS_FREQ tnetd73xx_vbus_freq /* originally (TNETD73XX_MIPS_FREQ/2) */
5340 +
5341 +#ifdef AR7SEAD2
5342 +#define TNETD73XX_MIPS_FREQ_DEFAULT 25000000 /* 25 Mhz for sead2 board crystal */
5343 +#else
5344 +#define TNETD73XX_MIPS_FREQ_DEFAULT 125000000 /* 125 Mhz */
5345 +#endif
5346 +#define TNETD73XX_VBUS_FREQ_DEFAULT (TNETD73XX_MIPS_FREQ_DEFAULT / 2) /* Sync mode */
5347 +
5348 +
5349 +
5350 +/* Module base addresses */
5351 +#define TNETD73XX_ADSLSS_BASE PHYS_TO_K1(0x01000000) /* ADSLSS Module */
5352 +#define TNETD73XX_BBIF_CTRL_BASE PHYS_TO_K1(0x02000000) /* BBIF Control */
5353 +#define TNETD73XX_ATMSAR_BASE PHYS_TO_K1(0x03000000) /* ATM SAR */
5354 +#define TNETD73XX_USB_BASE PHYS_TO_K1(0x03400000) /* USB Module */
5355 +#define TNETD73XX_VLYNQ0_BASE PHYS_TO_K1(0x04000000) /* VLYNQ0 Module */
5356 +#define TNETD73xx_EMAC0_BASE PHYS_TO_K1(0x08610000) /* EMAC0 Module*/
5357 +#define TNETD73XX_EMIF_BASE PHYS_TO_K1(0x08610800) /* EMIF Module */
5358 +#define TNETD73XX_GPIO_BASE PHYS_TO_K1(0x08610900) /* GPIO control */
5359 +#define TNETD73XX_CLOCK_CTRL_BASE PHYS_TO_K1(0x08610A00) /* Clock Control */
5360 +#define TNETD73XX_WDTIMER_BASE PHYS_TO_K1(0x08610B00) /* WDTIMER Module */
5361 +#define TNETD73XX_TIMER0_BASE PHYS_TO_K1(0x08610C00) /* TIMER0 Module */
5362 +#define TNETD73XX_TIMER1_BASE PHYS_TO_K1(0x08610D00) /* TIMER1 Module */
5363 +#define TNETD73XX_UARTA_BASE PHYS_TO_K1(0x08610E00) /* UART A */
5364 +#define TNETD73XX_UARTB_BASE PHYS_TO_K1(0x08610F00) /* UART B */
5365 +#define TNETD73XX_I2C_BASE PHYS_TO_K1(0x08611000) /* I2C Module */
5366 +#define TNETD73XX_USB_DMA_BASE PHYS_TO_K1(0x08611200) /* USB Module */
5367 +#define TNETD73XX_MCDMA_BASE PHYS_TO_K1(0x08611400) /* MC-DMA */
5368 +#define TNETD73xx_VDMAVT_BASE PHYS_TO_K1(0x08611500) /* VDMAVT Control */
5369 +#define TNETD73XX_RST_CTRL_BASE PHYS_TO_K1(0x08611600) /* Reset Control */
5370 +#define TNETD73xx_BIST_CTRL_BASE PHYS_TO_K1(0x08611700) /* BIST Control */
5371 +#define TNETD73xx_VLYNQ0_CTRL_BASE PHYS_TO_K1(0x08611800) /* VLYNQ0 Control */
5372 +#define TNETD73XX_DCL_BASE PHYS_TO_K1(0x08611A00) /* Device Configuration Latch */
5373 +#define TNETD73xx_VLYNQ1_CTRL_BASE PHYS_TO_K1(0x08611C00) /* VLYNQ1 Control */
5374 +#define TNETD73xx_MDIO_BASE PHYS_TO_K1(0x08611E00) /* MDIO Control */
5375 +#define TNETD73XX_FSER_BASE PHYS_TO_K1(0x08612000) /* FSER Control */
5376 +#define TNETD73XX_INTC_BASE PHYS_TO_K1(0x08612400) /* Interrupt Controller */
5377 +#define TNETD73xx_EMAC1_BASE PHYS_TO_K1(0x08612800) /* EMAC1 Module*/
5378 +#define TNETD73XX_VLYNQ1_BASE PHYS_TO_K1(0x0C000000) /* VLYNQ1 Module */
5379 +
5380 +/* BBIF Registers */
5381 +#define TNETD73XX_BBIF_ADSLADR (TNETD73XX_BBIF_CTRL_BASE + 0x0)
5382 +
5383 +/* Device Configuration Latch Registers */
5384 +#define TNETD73XX_DCL_BOOTCR (TNETD73XX_DCL_BASE + 0x0)
5385 +#define TNETD73XX_DCL_DPLLSELR (TNETD73XX_DCL_BASE + 0x10)
5386 +#define TNETD73XX_DCL_SPEEDCTLR (TNETD73XX_DCL_BASE + 0x14)
5387 +#define TNETD73XX_DCL_SPEEDPWDR (TNETD73XX_DCL_BASE + 0x18)
5388 +#define TNETD73XX_DCL_SPEEDCAPR (TNETD73XX_DCL_BASE + 0x1C)
5389 +
5390 +/* GPIO Control */
5391 +#define TNETD73XX_GPIODINR (TNETD73XX_GPIO_BASE + 0x0)
5392 +#define TNETD73XX_GPIODOUTR (TNETD73XX_GPIO_BASE + 0x4)
5393 +#define TNETD73XX_GPIOPDIRR (TNETD73XX_GPIO_BASE + 0x8)
5394 +#define TNETD73XX_GPIOENR (TNETD73XX_GPIO_BASE + 0xC)
5395 +#define TNETD73XX_CVR (TNETD73XX_GPIO_BASE + 0x14)
5396 +#define TNETD73XX_DIDR1 (TNETD73XX_GPIO_BASE + 0x18)
5397 +#define TNETD73XX_DIDR2 (TNETD73XX_GPIO_BASE + 0x1C)
5398 +
5399 +/* Reset Control */
5400 +#define TNETD73XX_RST_CTRL_PRCR (TNETD73XX_RST_CTRL_BASE + 0x0)
5401 +#define TNETD73XX_RST_CTRL_SWRCR (TNETD73XX_RST_CTRL_BASE + 0x4)
5402 +#define TNETD73XX_RST_CTRL_RSR (TNETD73XX_RST_CTRL_BASE + 0x8)
5403 +
5404 +/* Power Control */
5405 +#define TNETD73XX_POWER_CTRL_PDCR (TNETD73XX_CLOCK_CTRL_BASE + 0x0)
5406 +#define TNETD73XX_POWER_CTRL_PCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x4)
5407 +#define TNETD73XX_POWER_CTRL_PDUCR (TNETD73XX_CLOCK_CTRL_BASE + 0x8)
5408 +#define TNETD73XX_POWER_CTRL_WKCR (TNETD73XX_CLOCK_CTRL_BASE + 0xC)
5409 +
5410 +/* Clock Control */
5411 +#define TNETD73XX_CLK_CTRL_SCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x20)
5412 +#define TNETD73XX_CLK_CTRL_SCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x30)
5413 +#define TNETD73XX_CLK_CTRL_MCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x40)
5414 +#define TNETD73XX_CLK_CTRL_MCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x50)
5415 +#define TNETD73XX_CLK_CTRL_UCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x60)
5416 +#define TNETD73XX_CLK_CTRL_UCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x70)
5417 +#define TNETD73XX_CLK_CTRL_ACLKCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x80)
5418 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x90)
5419 +#define TNETD73XX_CLK_CTRL_ACLKCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xA0)
5420 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xB0)
5421 +
5422 +/* EMIF control */
5423 +#define TNETD73XX_EMIF_SDRAM_CFG ( TNETD73XX_EMIF_BASE + 0x08 )
5424 +
5425 +/* UART */
5426 +#ifdef AR7SEAD2
5427 +#define TNETD73XX_UART_FREQ 3686400
5428 +#else
5429 +#define TNETD73XX_UART_FREQ TNETD73XX_VBUS_FREQ
5430 +#endif
5431 +
5432 +/* Interrupt Controller */
5433 +
5434 +/* Primary interrupts */
5435 +#define TNETD73XX_INTC_UNIFIED_SECONDARY 0 /* Unified secondary interrupt */
5436 +#define TNETD73XX_INTC_EXTERNAL0 1 /* External Interrupt Line 0 */
5437 +#define TNETD73XX_INTC_EXTERNAL1 2 /* External Interrupt Line 1 */
5438 +#define TNETD73XX_INTC_RESERVED3 3 /* Reserved */
5439 +#define TNETD73XX_INTC_RESERVED4 4 /* Reserved */
5440 +#define TNETD73XX_INTC_TIMER0 5 /* TIMER 0 int */
5441 +#define TNETD73XX_INTC_TIMER1 6 /* TIMER 1 int */
5442 +#define TNETD73XX_INTC_UART0 7 /* UART 0 int */
5443 +#define TNETD73XX_INTC_UART1 8 /* UART 1 int */
5444 +#define TNETD73XX_INTC_MCDMA0 9 /* MCDMA 0 int */
5445 +#define TNETD73XX_INTC_MCDMA1 10 /* MCDMA 1 int */
5446 +#define TNETD73XX_INTC_RESERVED11 11 /* Reserved */
5447 +#define TNETD73XX_INTC_RESERVED12 12 /* Reserved */
5448 +#define TNETD73XX_INTC_RESERVED13 13 /* Reserved */
5449 +#define TNETD73XX_INTC_RESERVED14 14 /* Reserved */
5450 +#define TNETD73XX_INTC_ATMSAR 15 /* ATM SAR int */
5451 +#define TNETD73XX_INTC_RESERVED16 16 /* Reserved */
5452 +#define TNETD73XX_INTC_RESERVED17 17 /* Reserved */
5453 +#define TNETD73XX_INTC_RESERVED18 18 /* Reserved */
5454 +#define TNETD73XX_INTC_EMAC0 19 /* EMAC 0 int */
5455 +#define TNETD73XX_INTC_RESERVED20 20 /* Reserved */
5456 +#define TNETD73XX_INTC_VLYNQ0 21 /* VLYNQ 0 int */
5457 +#define TNETD73XX_INTC_CODEC 22 /* CODEC int */
5458 +#define TNETD73XX_INTC_RESERVED23 23 /* Reserved */
5459 +#define TNETD73XX_INTC_USBSLAVE 24 /* USB Slave int */
5460 +#define TNETD73XX_INTC_VLYNQ1 25 /* VLYNQ 1 int */
5461 +#define TNETD73XX_INTC_RESERVED26 26 /* Reserved */
5462 +#define TNETD73XX_INTC_RESERVED27 27 /* Reserved */
5463 +#define TNETD73XX_INTC_ETH_PHY 28 /* Ethernet PHY */
5464 +#define TNETD73XX_INTC_I2C 29 /* I2C int */
5465 +#define TNETD73XX_INTC_MCDMA2 30 /* MCDMA 2 int */
5466 +#define TNETD73XX_INTC_MCDMA3 31 /* MCDMA 3 int */
5467 +#define TNETD73XX_INTC_RESERVED32 32 /* Reserved */
5468 +#define TNETD73XX_INTC_EMAC1 33 /* EMAC 1 int */
5469 +#define TNETD73XX_INTC_RESERVED34 34 /* Reserved */
5470 +#define TNETD73XX_INTC_RESERVED35 35 /* Reserved */
5471 +#define TNETD73XX_INTC_RESERVED36 36 /* Reserved */
5472 +#define TNETD73XX_INTC_VDMAVTRX 37 /* VDMAVTRX */
5473 +#define TNETD73XX_INTC_VDMAVTTX 38 /* VDMAVTTX */
5474 +#define TNETD73XX_INTC_ADSLSS 39 /* ADSLSS */
5475 +
5476 +/* Secondary interrupts */
5477 +#define TNETD73XX_INTC_SEC0 40 /* Secondary */
5478 +#define TNETD73XX_INTC_SEC1 41 /* Secondary */
5479 +#define TNETD73XX_INTC_SEC2 42 /* Secondary */
5480 +#define TNETD73XX_INTC_SEC3 43 /* Secondary */
5481 +#define TNETD73XX_INTC_SEC4 44 /* Secondary */
5482 +#define TNETD73XX_INTC_SEC5 45 /* Secondary */
5483 +#define TNETD73XX_INTC_SEC6 46 /* Secondary */
5484 +#define TNETD73XX_INTC_EMIF 47 /* EMIF */
5485 +#define TNETD73XX_INTC_SEC8 48 /* Secondary */
5486 +#define TNETD73XX_INTC_SEC9 49 /* Secondary */
5487 +#define TNETD73XX_INTC_SEC10 50 /* Secondary */
5488 +#define TNETD73XX_INTC_SEC11 51 /* Secondary */
5489 +#define TNETD73XX_INTC_SEC12 52 /* Secondary */
5490 +#define TNETD73XX_INTC_SEC13 53 /* Secondary */
5491 +#define TNETD73XX_INTC_SEC14 54 /* Secondary */
5492 +#define TNETD73XX_INTC_SEC15 55 /* Secondary */
5493 +#define TNETD73XX_INTC_SEC16 56 /* Secondary */
5494 +#define TNETD73XX_INTC_SEC17 57 /* Secondary */
5495 +#define TNETD73XX_INTC_SEC18 58 /* Secondary */
5496 +#define TNETD73XX_INTC_SEC19 59 /* Secondary */
5497 +#define TNETD73XX_INTC_SEC20 60 /* Secondary */
5498 +#define TNETD73XX_INTC_SEC21 61 /* Secondary */
5499 +#define TNETD73XX_INTC_SEC22 62 /* Secondary */
5500 +#define TNETD73XX_INTC_SEC23 63 /* Secondary */
5501 +#define TNETD73XX_INTC_SEC24 64 /* Secondary */
5502 +#define TNETD73XX_INTC_SEC25 65 /* Secondary */
5503 +#define TNETD73XX_INTC_SEC26 66 /* Secondary */
5504 +#define TNETD73XX_INTC_SEC27 67 /* Secondary */
5505 +#define TNETD73XX_INTC_SEC28 68 /* Secondary */
5506 +#define TNETD73XX_INTC_SEC29 69 /* Secondary */
5507 +#define TNETD73XX_INTC_SEC30 70 /* Secondary */
5508 +#define TNETD73XX_INTC_SEC31 71 /* Secondary */
5509 +
5510 +/* These ugly macros are to access the -1 registers, like config1 */
5511 +#define MFC0_SEL1_OPCODE(dst, src)\
5512 + .word (0x40000000 | ((dst)<<16) | ((src)<<11) | 1);\
5513 + nop; \
5514 + nop; \
5515 + nop
5516 +
5517 +#define MTC0_SEL1_OPCODE(dst, src)\
5518 + .word (0x40800000 | ((dst)<<16) | ((src)<<11) | 1);\
5519 + nop; \
5520 + nop; \
5521 + nop
5522 +
5523 +
5524 +/* Below are Jade core specific */
5525 +#define CFG0_4K_IL_MASK 0x00380000
5526 +#define CFG0_4K_IL_SHIFT 19
5527 +#define CFG0_4K_IA_MASK 0x00070000
5528 +#define CFG0_4K_IA_SHIFT 16
5529 +#define CFG0_4K_IS_MASK 0x01c00000
5530 +#define CFG0_4K_IS_SHIFT 22
5531 +
5532 +#define CFG0_4K_DL_MASK 0x00001c00
5533 +#define CFG0_4K_DL_SHIFT 10
5534 +#define CFG0_4K_DA_MASK 0x00000380
5535 +#define CFG0_4K_DA_SHIFT 7
5536 +#define CFG0_4K_DS_MASK 0x0000E000
5537 +#define CFG0_4K_DS_SHIFT 13
5538 +
5539 +
5540 +
5541 +#endif /* __TNETD73XX_H_ */
5542 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_misc.h linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h
5543 --- linux.old/include/asm-mips/ar7/tnetd73xx_misc.h 1970-01-01 01:00:00.000000000 +0100
5544 +++ linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h 2005-07-12 03:01:26.110438256 +0200
5545 @@ -0,0 +1,239 @@
5546 +/******************************************************************************
5547 + * FILE PURPOSE: TNETD73xx Misc modules API Header
5548 + ******************************************************************************
5549 + * FILE NAME: tnetd73xx_misc.h
5550 + *
5551 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
5552 + * FSER Modules API
5553 + * As per TNETD73xx specifications
5554 + *
5555 + * REVISION HISTORY:
5556 + * 27 Nov 02 - Sharath Kumar PSP TII
5557 + * 14 Feb 03 - Anant Gole PSP TII
5558 + *
5559 + * (C) Copyright 2002, Texas Instruments, Inc
5560 + *******************************************************************************/
5561 +
5562 +#ifndef __TNETD73XX_MISC_H__
5563 +#define __TNETD73XX_MISC_H__
5564 +
5565 +/*****************************************************************************
5566 + * Reset Control Module
5567 + *****************************************************************************/
5568 +
5569 +typedef enum TNETD73XX_RESET_MODULE_tag
5570 +{
5571 + RESET_MODULE_UART0 = 0,
5572 + RESET_MODULE_UART1 = 1,
5573 + RESET_MODULE_I2C = 2,
5574 + RESET_MODULE_TIMER0 = 3,
5575 + RESET_MODULE_TIMER1 = 4,
5576 + RESET_MODULE_GPIO = 6,
5577 + RESET_MODULE_ADSLSS = 7,
5578 + RESET_MODULE_USBS = 8,
5579 + RESET_MODULE_SAR = 9,
5580 + RESET_MODULE_VDMA_VT = 11,
5581 + RESET_MODULE_FSER = 12,
5582 + RESET_MODULE_VLYNQ1 = 16,
5583 + RESET_MODULE_EMAC0 = 17,
5584 + RESET_MODULE_DMA = 18,
5585 + RESET_MODULE_BIST = 19,
5586 + RESET_MODULE_VLYNQ0 = 20,
5587 + RESET_MODULE_EMAC1 = 21,
5588 + RESET_MODULE_MDIO = 22,
5589 + RESET_MODULE_ADSLSS_DSP = 23,
5590 + RESET_MODULE_EPHY = 26
5591 +} TNETD73XX_RESET_MODULE_T;
5592 +
5593 +typedef enum TNETD73XX_RESET_CTRL_tag
5594 +{
5595 + IN_RESET = 0,
5596 + OUT_OF_RESET
5597 +} TNETD73XX_RESET_CTRL_T;
5598 +
5599 +typedef enum TNETD73XX_SYS_RST_MODE_tag
5600 +{
5601 + RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
5602 + RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
5603 +} TNETD73XX_SYS_RST_MODE_T;
5604 +
5605 +typedef enum TNETD73XX_SYS_RESET_STATUS_tag
5606 +{
5607 + HARDWARE_RESET = 0,
5608 + SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
5609 + WATCHDOG_RESET,
5610 + SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
5611 +} TNETD73XX_SYS_RESET_STATUS_T;
5612 +
5613 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module,
5614 + TNETD73XX_RESET_CTRL_T reset_ctrl);
5615 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status(TNETD73XX_RESET_MODULE_T reset_module);
5616 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode);
5617 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status(void);
5618 +
5619 +/*****************************************************************************
5620 + * Power Control Module
5621 + *****************************************************************************/
5622 +
5623 +typedef enum TNETD73XX_POWER_MODULE_tag
5624 +{
5625 + POWER_MODULE_USBSP = 0,
5626 + POWER_MODULE_WDTP = 1,
5627 + POWER_MODULE_UT0P = 2,
5628 + POWER_MODULE_UT1P = 3,
5629 + POWER_MODULE_IICP = 4,
5630 + POWER_MODULE_VDMAP = 5,
5631 + POWER_MODULE_GPIOP = 6,
5632 + POWER_MODULE_VLYNQ1P = 7,
5633 + POWER_MODULE_SARP = 8,
5634 + POWER_MODULE_ADSLP = 9,
5635 + POWER_MODULE_EMIFP = 10,
5636 + POWER_MODULE_ADSPP = 12,
5637 + POWER_MODULE_RAMP = 13,
5638 + POWER_MODULE_ROMP = 14,
5639 + POWER_MODULE_DMAP = 15,
5640 + POWER_MODULE_BISTP = 16,
5641 + POWER_MODULE_TIMER0P = 18,
5642 + POWER_MODULE_TIMER1P = 19,
5643 + POWER_MODULE_EMAC0P = 20,
5644 + POWER_MODULE_EMAC1P = 22,
5645 + POWER_MODULE_EPHYP = 24,
5646 + POWER_MODULE_VLYNQ0P = 27,
5647 +} TNETD73XX_POWER_MODULE_T;
5648 +
5649 +typedef enum TNETD73XX_POWER_CTRL_tag
5650 +{
5651 + POWER_CTRL_POWER_UP = 0,
5652 + POWER_CTRL_POWER_DOWN
5653 +} TNETD73XX_POWER_CTRL_T;
5654 +
5655 +typedef enum TNETD73XX_SYS_POWER_MODE_tag
5656 +{
5657 + GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
5658 + GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
5659 + GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
5660 + GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
5661 +} TNETD73XX_SYS_POWER_MODE_T;
5662 +
5663 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl);
5664 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module);
5665 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode);
5666 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode(void);
5667 +
5668 +/*****************************************************************************
5669 + * Wakeup Control
5670 + *****************************************************************************/
5671 +
5672 +typedef enum TNETD73XX_WAKEUP_INTERRUPT_tag
5673 +{
5674 + WAKEUP_INT0 = 1,
5675 + WAKEUP_INT1 = 2,
5676 + WAKEUP_INT2 = 4,
5677 + WAKEUP_INT3 = 8
5678 +} TNETD73XX_WAKEUP_INTERRUPT_T;
5679 +
5680 +typedef enum TNETD73XX_WAKEUP_CTRL_tag
5681 +{
5682 + WAKEUP_DISABLED = 0,
5683 + WAKEUP_ENABLED
5684 +} TNETD73XX_WAKEUP_CTRL_T;
5685 +
5686 +typedef enum TNETD73XX_WAKEUP_POLARITY_tag
5687 +{
5688 + WAKEUP_ACTIVE_HIGH = 0,
5689 + WAKEUP_ACTIVE_LOW
5690 +} TNETD73XX_WAKEUP_POLARITY_T;
5691 +
5692 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
5693 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
5694 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity);
5695 +
5696 +/*****************************************************************************
5697 + * FSER Control
5698 + *****************************************************************************/
5699 +
5700 +typedef enum TNETD73XX_FSER_MODE_tag
5701 +{
5702 + FSER_I2C = 0,
5703 + FSER_UART = 1
5704 +} TNETD73XX_FSER_MODE_T;
5705 +
5706 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode);
5707 +
5708 +/*****************************************************************************
5709 + * Clock Control
5710 + *****************************************************************************/
5711 +
5712 +#define CLK_MHZ(x) ( (x) * 1000000 )
5713 +
5714 +typedef enum TNETD73XX_CLKC_ID_tag
5715 +{
5716 + CLKC_SYS = 0,
5717 + CLKC_MIPS,
5718 + CLKC_USB,
5719 + CLKC_ADSLSS
5720 +} TNETD73XX_CLKC_ID_T;
5721 +
5722 +void tnetd73xx_clkc_init(__u32 afeclk, __u32 refclk, __u32 xtal3in);
5723 +TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, __u32 output_freq);
5724 +__u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id);
5725 +
5726 +/*****************************************************************************
5727 + * GPIO Control
5728 + *****************************************************************************/
5729 +
5730 +typedef enum TNETD73XX_GPIO_PIN_tag
5731 +{
5732 + GPIO_UART0_RD = 0,
5733 + GPIO_UART0_TD = 1,
5734 + GPIO_UART0_RTS = 2,
5735 + GPIO_UART0_CTS = 3,
5736 + GPIO_FSER_CLK = 4,
5737 + GPIO_FSER_D = 5,
5738 + GPIO_EXT_AFE_SCLK = 6,
5739 + GPIO_EXT_AFE_TX_FS = 7,
5740 + GPIO_EXT_AFE_TXD = 8,
5741 + GPIO_EXT_AFE_RS_FS = 9,
5742 + GPIO_EXT_AFE_RXD1 = 10,
5743 + GPIO_EXT_AFE_RXD0 = 11,
5744 + GPIO_EXT_AFE_CDIN = 12,
5745 + GPIO_EXT_AFE_CDOUT = 13,
5746 + GPIO_EPHY_SPEED100 = 14,
5747 + GPIO_EPHY_LINKON = 15,
5748 + GPIO_EPHY_ACTIVITY = 16,
5749 + GPIO_EPHY_FDUPLEX = 17,
5750 + GPIO_EINT0 = 18,
5751 + GPIO_EINT1 = 19,
5752 + GPIO_MBSP0_TCLK = 20,
5753 + GPIO_MBSP0_RCLK = 21,
5754 + GPIO_MBSP0_RD = 22,
5755 + GPIO_MBSP0_TD = 23,
5756 + GPIO_MBSP0_RFS = 24,
5757 + GPIO_MBSP0_TFS = 25,
5758 + GPIO_MII_DIO = 26,
5759 + GPIO_MII_DCLK = 27,
5760 +} TNETD73XX_GPIO_PIN_T;
5761 +
5762 +typedef enum TNETD73XX_GPIO_PIN_MODE_tag
5763 +{
5764 + FUNCTIONAL_PIN = 0,
5765 + GPIO_PIN = 1
5766 +} TNETD73XX_GPIO_PIN_MODE_T;
5767 +
5768 +typedef enum TNETD73XX_GPIO_PIN_DIRECTION_tag
5769 +{
5770 + GPIO_OUTPUT_PIN = 0,
5771 + GPIO_INPUT_PIN = 1
5772 +} TNETD73XX_GPIO_PIN_DIRECTION_T;
5773 +
5774 +void tnetd73xx_gpio_init(void);
5775 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
5776 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
5777 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction);
5778 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value);
5779 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin);
5780 +
5781 +/* TNETD73XX Revision */
5782 +__u32 tnetd73xx_get_revision(void);
5783 +
5784 +#endif /* __TNETD73XX_MISC_H__ */
5785 diff -urN linux.old/include/asm-mips/io.h linux.dev/include/asm-mips/io.h
5786 --- linux.old/include/asm-mips/io.h 2005-07-10 03:00:44.797179400 +0200
5787 +++ linux.dev/include/asm-mips/io.h 2005-07-12 02:59:26.202667008 +0200
5788 @@ -63,8 +63,12 @@
5789 #ifdef CONFIG_64BIT_PHYS_ADDR
5790 #define page_to_phys(page) ((u64)(page - mem_map) << PAGE_SHIFT)
5791 #else
5792 +#ifdef CONFIG_AR7_PAGING
5793 +#define page_to_phys(page) (((page - mem_map) << PAGE_SHIFT) + CONFIG_AR7_MEMORY)
5794 +#else
5795 #define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
5796 #endif
5797 +#endif
5798
5799 #define IO_SPACE_LIMIT 0xffff
5800
5801 diff -urN linux.old/include/asm-mips/irq.h linux.dev/include/asm-mips/irq.h
5802 --- linux.old/include/asm-mips/irq.h 2005-07-10 03:00:44.798179248 +0200
5803 +++ linux.dev/include/asm-mips/irq.h 2005-07-12 02:59:26.202667008 +0200
5804 @@ -14,7 +14,12 @@
5805 #include <linux/config.h>
5806 #include <linux/linkage.h>
5807
5808 +#ifdef CONFIG_AR7
5809 +#include <asm/ar7/avalanche_intc.h>
5810 +#define NR_IRQS AVALANCHE_INT_END + 1
5811 +#else
5812 #define NR_IRQS 128 /* Largest number of ints of all machines. */
5813 +#endif
5814
5815 #ifdef CONFIG_I8259
5816 static inline int irq_cannonicalize(int irq)
5817 diff -urN linux.old/include/asm-mips/page.h linux.dev/include/asm-mips/page.h
5818 --- linux.old/include/asm-mips/page.h 2005-07-10 03:00:44.798179248 +0200
5819 +++ linux.dev/include/asm-mips/page.h 2005-07-12 02:59:26.202667008 +0200
5820 @@ -129,7 +129,11 @@
5821
5822 #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
5823 #define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
5824 +#ifdef CONFIG_AR7_PAGING
5825 +#define virt_to_page(kaddr) phys_to_page(__pa(kaddr))
5826 +#else
5827 #define virt_to_page(kaddr) (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
5828 +#endif
5829 #define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
5830
5831 #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
5832 diff -urN linux.old/include/asm-mips/pgtable-32.h linux.dev/include/asm-mips/pgtable-32.h
5833 --- linux.old/include/asm-mips/pgtable-32.h 2005-07-10 03:00:44.798179248 +0200
5834 +++ linux.dev/include/asm-mips/pgtable-32.h 2005-07-12 02:59:26.203666856 +0200
5835 @@ -108,7 +108,18 @@
5836 * and a page entry and page directory to the page they refer to.
5837 */
5838
5839 -#ifdef CONFIG_CPU_VR41XX
5840 +#if defined(CONFIG_AR7_PAGING)
5841 +#define mk_pte(page, pgprot) \
5842 +({ \
5843 + pte_t __pte; \
5844 + \
5845 + pte_val(__pte) = ((phys_t)(page - mem_map) << (PAGE_SHIFT) | \
5846 + CONFIG_AR7_MEMORY) | \
5847 + pgprot_val(pgprot); \
5848 + \
5849 + __pte; \
5850 +})
5851 +#elif defined(CONFIG_CPU_VR41XX)
5852 #define mk_pte(page, pgprot) \
5853 ({ \
5854 pte_t __pte; \
5855 @@ -130,6 +141,7 @@
5856 })
5857 #endif
5858
5859 +
5860 static inline pte_t mk_pte_phys(phys_t physpage, pgprot_t pgprot)
5861 {
5862 #ifdef CONFIG_CPU_VR41XX
5863 @@ -175,7 +187,10 @@
5864 set_pte(ptep, __pte(0));
5865 }
5866
5867 -#ifdef CONFIG_CPU_VR41XX
5868 +#if defined(CONFIG_AR7_PAGING)
5869 +#define phys_to_page(phys) (mem_map + (((phys)-CONFIG_AR7_MEMORY) >> PAGE_SHIFT))
5870 +#define pte_page(x) phys_to_page(pte_val(x))
5871 +#elif defined(CONFIG_CPU_VR41XX)
5872 #define pte_page(x) (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2)))))
5873 #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
5874 #else
5875 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
5876 --- linux.old/include/asm-mips/serial.h 2005-07-10 03:00:44.799179096 +0200
5877 +++ linux.dev/include/asm-mips/serial.h 2005-07-12 02:59:26.203666856 +0200
5878 @@ -65,6 +65,15 @@
5879
5880 #define C_P(card,port) (((card)<<6|(port)<<3) + 1)
5881
5882 +#ifdef CONFIG_AR7
5883 +#include <asm/ar7/ar7.h>
5884 +#define AR7_SERIAL_PORT_DEFNS \
5885 + { 0, AR7_BASE_BAUD, AR7_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
5886 + { 0, AR7_BASE_BAUD, AR7_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS },
5887 +#else
5888 +#define AR7_SERIAL_PORT_DEFNS
5889 +#endif
5890 +
5891 #ifdef CONFIG_MIPS_JAZZ
5892 #define _JAZZ_SERIAL_INIT(int, base) \
5893 { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
5894 @@ -468,6 +477,7 @@
5895 #endif
5896
5897 #define SERIAL_PORT_DFNS \
5898 + AR7_SERIAL_PORT_DEFNS \
5899 ATLAS_SERIAL_PORT_DEFNS \
5900 AU1000_SERIAL_PORT_DEFNS \
5901 COBALT_SERIAL_PORT_DEFNS \
5902 diff -urN linux.old/Makefile linux.dev/Makefile
5903 --- linux.old/Makefile 2005-07-10 03:00:44.799179096 +0200
5904 +++ linux.dev/Makefile 2005-07-12 02:59:26.204666704 +0200
5905 @@ -91,7 +91,7 @@
5906
5907 CPPFLAGS := -D__KERNEL__ -I$(HPATH)
5908
5909 -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
5910 +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
5911 -fno-strict-aliasing -fno-common
5912 ifndef CONFIG_FRAME_POINTER
5913 CFLAGS += -fomit-frame-pointer
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