target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_mdio.c

   1 /*
   2  *  Atheros AR71xx built-in ethernet mac driver
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Based on Atheros' AG7100 driver
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include "ag71xx.h"
  15
  16 #define AG71XX_MDIO_RETRY       1000
  17 #define AG71XX_MDIO_DELAY       5
  18
  19 struct ag71xx_mdio *ag71xx_mdio_bus;
  20
  21 static inline void ag71xx_mdio_wr(struct ag71xx_mdio *am, unsigned reg,
  22                                   u32 value)
  23 {
  24         void __iomem *r;
  25
  26         r = am->mdio_base + reg;
  27         __raw_writel(value, r);
  28
  29         /* flush write */
  30         (void) __raw_readl(r);
  31 }
  32
  33 static inline u32 ag71xx_mdio_rr(struct ag71xx_mdio *am, unsigned reg)
  34 {
  35         return __raw_readl(am->mdio_base + reg);
  36 }
  37
  38 static void ag71xx_mdio_dump_regs(struct ag71xx_mdio *am)
  39 {
  40         DBG("%s: mii_cfg=%08x, mii_cmd=%08x, mii_addr=%08x\n",
  41                 am->mii_bus->name,
  42                 ag71xx_mdio_rr(am, AG71XX_REG_MII_CFG),
  43                 ag71xx_mdio_rr(am, AG71XX_REG_MII_CMD),
  44                 ag71xx_mdio_rr(am, AG71XX_REG_MII_ADDR));
  45         DBG("%s: mii_ctrl=%08x, mii_status=%08x, mii_ind=%08x\n",
  46                 am->mii_bus->name,
  47                 ag71xx_mdio_rr(am, AG71XX_REG_MII_CTRL),
  48                 ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS),
  49                 ag71xx_mdio_rr(am, AG71XX_REG_MII_IND));
  50 }
  51
  52 static int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg)
  53 {
  54         int ret;
  55         int i;
  56
  57         ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
  58         ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR,
  59                         ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
  60         ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_READ);
  61
  62         i = AG71XX_MDIO_RETRY;
  63         while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) {
  64                 if (i-- == 0) {
  65                         printk(KERN_ERR "%s: mii_read timed out\n",
  66                                 am->mii_bus->name);
  67                         ret = 0xffff;
  68                         goto out;
  69                 }
  70                 udelay(AG71XX_MDIO_DELAY);
  71         }
  72
  73         ret = ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS) & 0xffff;
  74         ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
  75
  76         DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, ret);
  77
  78  out:
  79         return ret;
  80 }
  81
  82 static void ag71xx_mdio_mii_write(struct ag71xx_mdio *am,
  83                                   int addr, int reg, u16 val)
  84 {
  85         int i;
  86
  87         DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val);
  88
  89         ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR,
  90                         ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
  91         ag71xx_mdio_wr(am, AG71XX_REG_MII_CTRL, val);
  92
  93         i = AG71XX_MDIO_RETRY;
  94         while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) {
  95                 if (i-- == 0) {
  96                         printk(KERN_ERR "%s: mii_write timed out\n",
  97                                 am->mii_bus->name);
  98                         break;
  99                 }
 100                 udelay(AG71XX_MDIO_DELAY);
 101         }
 102 }
 103
 104 static int ag71xx_mdio_reset(struct mii_bus *bus)
 105 {
 106         struct ag71xx_mdio *am = bus->priv;
 107         u32 t;
 108
 109         t = MII_CFG_CLK_DIV_28;
 110
 111         ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t | MII_CFG_RESET);
 112         udelay(100);
 113
 114         ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t);
 115         udelay(100);
 116
 117         return 0;
 118 }
 119
 120 static int ag71xx_mdio_read(struct mii_bus *bus, int addr, int reg)
 121 {
 122         struct ag71xx_mdio *am = bus->priv;
 123
 124         return ag71xx_mdio_mii_read(am, addr, reg);
 125 }
 126
 127 static int ag71xx_mdio_write(struct mii_bus *bus, int addr, int reg, u16 val)
 128 {
 129         struct ag71xx_mdio *am = bus->priv;
 130
 131         ag71xx_mdio_mii_write(am, addr, reg, val);
 132         return 0;
 133 }
 134
 135 static int __init ag71xx_mdio_probe(struct platform_device *pdev)
 136 {
 137         struct ag71xx_mdio_platform_data *pdata;
 138         struct ag71xx_mdio *am;
 139         struct resource *res;
 140         int i;
 141         int err;
 142
 143         if (ag71xx_mdio_bus)
 144                 return -EBUSY;
 145
 146         am = kzalloc(sizeof(*am), GFP_KERNEL);
 147         if (!am) {
 148                 err = -ENOMEM;
 149                 goto err_out;
 150         }
 151
 152         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 153         if (!res) {
 154                 dev_err(&pdev->dev, "no iomem resource found\n");
 155                 err = -ENXIO;
 156                 goto err_out;
 157         }
 158
 159         am->mdio_base = ioremap_nocache(res->start, res->end - res->start + 1);
 160         if (!am->mdio_base) {
 161                 dev_err(&pdev->dev, "unable to ioremap registers\n");
 162                 err = -ENOMEM;
 163                 goto err_free_mdio;
 164         }
 165
 166         am->mii_bus = mdiobus_alloc();
 167         if (am->mii_bus == NULL) {
 168                 err = -ENOMEM;
 169                 goto err_iounmap;
 170         }
 171
 172         am->mii_bus->name = "ag71xx_mdio";
 173         am->mii_bus->read = ag71xx_mdio_read;
 174         am->mii_bus->write = ag71xx_mdio_write;
 175         am->mii_bus->reset = ag71xx_mdio_reset;
 176         am->mii_bus->irq = am->mii_irq;
 177         am->mii_bus->priv = am;
 178         am->mii_bus->parent = &pdev->dev;
 179         snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
 180
 181         pdata = pdev->dev.platform_data;
 182         if (pdata)
 183                 am->mii_bus->phy_mask = pdata->phy_mask;
 184
 185         for (i = 0; i < PHY_MAX_ADDR; i++)
 186                 am->mii_irq[i] = PHY_POLL;
 187
 188         ag71xx_mdio_wr(am, AG71XX_REG_MAC_CFG1, 0);
 189
 190         err = mdiobus_register(am->mii_bus);
 191         if (err)
 192                 goto err_free_bus;
 193
 194         ag71xx_mdio_dump_regs(am);
 195
 196         platform_set_drvdata(pdev, am);
 197         ag71xx_mdio_bus = am;
 198         return 0;
 199
 200  err_free_bus:
 201         mdiobus_free(am->mii_bus);
 202  err_iounmap:
 203         iounmap(am->mdio_base);
 204  err_free_mdio:
 205         kfree(am);
 206  err_out:
 207         return err;
 208 }
 209
 210 static int __exit ag71xx_mdio_remove(struct platform_device *pdev)
 211 {
 212         struct ag71xx_mdio *am = platform_get_drvdata(pdev);
 213
 214         if (am) {
 215                 ag71xx_mdio_bus = NULL;
 216                 mdiobus_unregister(am->mii_bus);
 217                 mdiobus_free(am->mii_bus);
 218                 iounmap(am->mdio_base);
 219                 kfree(am);
 220                 platform_set_drvdata(pdev, NULL);
 221         }
 222
 223         return 0;
 224 }
 225
 226 static struct platform_driver ag71xx_mdio_driver = {
 227         .probe          = ag71xx_mdio_probe,
 228         .remove         = __exit_p(ag71xx_mdio_remove),
 229         .driver = {
 230                 .name   = "ag71xx-mdio",
 231         }
 232 };
 233
 234 int ag71xx_mdio_driver_init(void)
 235 {
 236         return platform_driver_register(&ag71xx_mdio_driver);
 237 }
 238
 239 void ag71xx_mdio_driver_exit(void)
 240 {
 241         platform_driver_unregister(&ag71xx_mdio_driver);
 242 }