target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_nand.h

   1 /*
   2  *  ADM5120 NAND interface definitions
   3  *
   4  *  This header file defines the hardware registers of the ADM5120 SoC
   5  *  built-in NAND interface.
   6  *
   7  *  Copyright (C) 2007 OpenWrt.org
   8  *  Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
   9  *
  10  *  NAND interface routines was based on a driver for Linux 2.6.19+ which
  11  *  was derived from the driver for Linux 2.4.xx published by Mikrotik for
  12  *  their RouterBoard 1xx and 5xx series boards.
  13  *    Copyright (C) 2007 David Goodenough <david.goodenough@linkchoose.co.uk>
  14  *    Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
  15  *    The original Mikrotik code seems not to have a license.
  16  *
  17  *  This program is free software; you can redistribute it and/or modify it
  18  *  under the terms of the GNU General Public License version 2 as published
  19  *  by the Free Software Foundation.
  20  *
  21  */
  22
  23 #ifndef _ADM5120_NAND_H_
  24 #define _ADM5120_NAND_H_
  25
  26 #include <linux/types.h>
  27 #include <linux/io.h>
  28
  29 #include <adm5120_defs.h>
  30 #include <adm5120_switch.h>
  31
  32 /* NAND control registers */
  33 #define NAND_REG_DATA           0x0 /* data register */
  34 #define NAND_REG_SET_CEn        0x1 /* CE# low */
  35 #define NAND_REG_CLR_CEn        0x2 /* CE# high */
  36 #define NAND_REG_CLR_CLE        0x3 /* CLE low */
  37 #define NAND_REG_SET_CLE        0x4 /* CLE high */
  38 #define NAND_REG_CLR_ALE        0x5 /* ALE low */
  39 #define NAND_REG_SET_ALE        0x6 /* ALE high */
  40 #define NAND_REG_SET_SPn        0x7 /* SP# low (use spare area) */
  41 #define NAND_REG_CLR_SPn        0x8 /* SP# high (do not use spare area) */
  42 #define NAND_REG_SET_WPn        0x9 /* WP# low */
  43 #define NAND_REG_CLR_WPn        0xA /* WP# high */
  44 #define NAND_REG_STATUS         0xB /* Status register */
  45
  46 #define ADM5120_NAND_STATUS_READY       0x80
  47
  48 #define NAND_READ_REG(r) \
  49         readb((void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r))
  50 #define NAND_WRITE_REG(r, v) \
  51         writeb((v),(void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r))
  52
  53 /*-------------------------------------------------------------------------*/
  54
  55 static inline void adm5120_nand_enable(void)
  56 {
  57         SW_WRITE_REG(SWITCH_REG_BW_CNTL1, BW_CNTL1_NAND_ENABLE);
  58         SW_WRITE_REG(SWITCH_REG_BOOT_DONE, 1);
  59 }
  60
  61 static inline void adm5120_nand_set_wpn(unsigned int set)
  62 {
  63         NAND_WRITE_REG((set) ? NAND_REG_SET_WPn : NAND_REG_CLR_WPn, 1);
  64 }
  65
  66 static inline void adm5120_nand_set_spn(unsigned int set)
  67 {
  68         NAND_WRITE_REG((set) ? NAND_REG_SET_SPn : NAND_REG_CLR_SPn, 1);
  69 }
  70
  71 static inline void adm5120_nand_set_cle(unsigned int set)
  72 {
  73         NAND_WRITE_REG((set) ? NAND_REG_SET_CLE : NAND_REG_CLR_CLE, 1);
  74 }
  75
  76 static inline void adm5120_nand_set_ale(unsigned int set)
  77 {
  78         NAND_WRITE_REG((set) ? NAND_REG_SET_ALE : NAND_REG_CLR_ALE, 1);
  79 }
  80
  81 static inline void adm5120_nand_set_cen(unsigned int set)
  82 {
  83         NAND_WRITE_REG((set) ? NAND_REG_SET_CEn : NAND_REG_CLR_CEn, 1);
  84 }
  85
  86 static inline u8 adm5120_nand_get_status(void)
  87 {
  88         return NAND_READ_REG(NAND_REG_STATUS);
  89 }
  90
  91 #endif /* _ADM5120_NAND_H_ */