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atheros: fix ar5312 support
[openwrt.git] / target / linux / atheros / patches-2.6.28 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -60,6 +60,19 @@ config BCM47XX
4 help
5 Support for BCM47XX based boards
6
7 +config ATHEROS
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select GENERIC_GPIO
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config MIPS_COBALT
21 bool "Cobalt Server"
22 select CEVT_R4K
23 @@ -597,6 +610,7 @@ config WR_PPMC
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/basler/excite/Kconfig"
30 source "arch/mips/emma/Kconfig"
31 --- a/arch/mips/Makefile
32 +++ b/arch/mips/Makefile
33 @@ -278,6 +278,13 @@ libs-$(CONFIG_MIPS_XXS1500) += arch/mips
34 load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
35
36 #
37 +# Atheros AR5312/AR2312 WiSoC
38 +#
39 +core-$(CONFIG_ATHEROS) += arch/mips/ar231x/
40 +cflags-$(CONFIG_ATHEROS) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
41 +load-$(CONFIG_ATHEROS) += 0xffffffff80041000
42 +
43 +#
44 # Cobalt Server
45 #
46 core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/
47 --- /dev/null
48 +++ b/arch/mips/ar231x/Kconfig
49 @@ -0,0 +1,17 @@
50 +config ATHEROS_AR5312
51 + bool "Atheros 5312/2312+ support"
52 + depends on ATHEROS
53 + default y
54 +
55 +config ATHEROS_AR2315
56 + bool "Atheros 2315+ support"
57 + depends on ATHEROS
58 + select DMA_NONCOHERENT
59 + select CEVT_R4K
60 + select CSRC_R4K
61 + select IRQ_CPU
62 + select SYS_HAS_CPU_MIPS32_R1
63 + select SYS_SUPPORTS_32BIT_KERNEL
64 + select SYS_SUPPORTS_BIG_ENDIAN
65 + select GENERIC_GPIO
66 + default y
67 --- /dev/null
68 +++ b/arch/mips/ar231x/Makefile
69 @@ -0,0 +1,13 @@
70 +#
71 +# This file is subject to the terms and conditions of the GNU General Public
72 +# License. See the file "COPYING" in the main directory of this archive
73 +# for more details.
74 +#
75 +# Copyright (C) 2006 FON Technology, SL.
76 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
77 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
78 +#
79 +
80 +obj-y += board.o prom.o devices.o
81 +obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
82 +obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
83 --- /dev/null
84 +++ b/arch/mips/ar231x/board.c
85 @@ -0,0 +1,247 @@
86 +/*
87 + * This file is subject to the terms and conditions of the GNU General Public
88 + * License. See the file "COPYING" in the main directory of this archive
89 + * for more details.
90 + *
91 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
92 + * Copyright (C) 2006 FON Technology, SL.
93 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
94 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
95 + */
96 +
97 +#include <linux/autoconf.h>
98 +#include <linux/init.h>
99 +#include <linux/module.h>
100 +#include <linux/types.h>
101 +#include <linux/string.h>
102 +#include <linux/platform_device.h>
103 +#include <linux/kernel.h>
104 +#include <linux/random.h>
105 +#include <linux/etherdevice.h>
106 +#include <asm/irq_cpu.h>
107 +#include <asm/reboot.h>
108 +#include <asm/io.h>
109 +
110 +#include <ar231x_platform.h>
111 +#include "devices.h"
112 +#include "ar5312.h"
113 +#include "ar2315.h"
114 +
115 +void (*ar231x_irq_dispatch)(void);
116 +
117 +static inline bool
118 +check_radio_magic(u8 *addr)
119 +{
120 + addr += 0x7a; /* offset for flash magic */
121 + if ((addr[0] == 0x5a) && (addr[1] == 0xa5)) {
122 + return 1;
123 + }
124 + return 0;
125 +}
126 +
127 +static inline bool
128 +check_board_data(u8 *flash_limit, u8 *addr, bool broken)
129 +{
130 + /* config magic found */
131 + if (*((u32 *)addr) == AR531X_BD_MAGIC)
132 + return 1;
133 +
134 + if (!broken)
135 + return 0;
136 +
137 + if (check_radio_magic(addr + 0xf8))
138 + ar231x_board.radio = addr + 0xf8;
139 + if ((addr < flash_limit + 0x10000) &&
140 + check_radio_magic(addr + 0x10000))
141 + ar231x_board.radio = addr + 0x10000;
142 +
143 + if (ar231x_board.radio) {
144 + /* broken board data detected, use radio data to find the offset,
145 + * user will fix this */
146 + return 1;
147 + }
148 + return 0;
149 +}
150 +
151 +static u8 *
152 +find_board_config(u8 *flash_limit, bool broken)
153 +{
154 + u8 *addr;
155 + int found = 0;
156 +
157 + for (addr = flash_limit - 0x1000;
158 + addr >= flash_limit - 0x30000;
159 + addr -= 0x1000) {
160 +
161 + if (check_board_data(flash_limit, addr, broken)) {
162 + found = 1;
163 + break;
164 + }
165 + }
166 +
167 + if (!found)
168 + addr = NULL;
169 +
170 + return addr;
171 +}
172 +
173 +static u8 *
174 +find_radio_config(u8 *flash_limit, u8 *board_config)
175 +{
176 + int found;
177 + u8 *radio_config;
178 +
179 + /*
180 + * Now find the start of Radio Configuration data, using heuristics:
181 + * Search forward from Board Configuration data by 0x1000 bytes
182 + * at a time until we find non-0xffffffff.
183 + */
184 + found = 0;
185 + for (radio_config = board_config + 0x1000;
186 + (radio_config < flash_limit);
187 + radio_config += 0x1000) {
188 + if ((*(u32 *)radio_config != 0xffffffff) &&
189 + check_radio_magic(radio_config)) {
190 + found = 1;
191 + break;
192 + }
193 + }
194 +
195 + /* AR2316 relocates radio config to new location */
196 + if (!found) {
197 + for (radio_config = board_config + 0xf8;
198 + (radio_config < flash_limit - 0x1000 + 0xf8);
199 + radio_config += 0x1000) {
200 + if ((*(u32 *)radio_config != 0xffffffff) &&
201 + check_radio_magic(radio_config)) {
202 + found = 1;
203 + break;
204 + }
205 + }
206 + }
207 +
208 + if (!found) {
209 + printk("Could not find Radio Configuration data\n");
210 + radio_config = 0;
211 + }
212 +
213 + return (u8 *) radio_config;
214 +}
215 +
216 +int __init
217 +ar231x_find_config(u8 *flash_limit)
218 +{
219 + struct ar231x_boarddata *config;
220 + unsigned int rcfg_size;
221 + int broken_boarddata = 0;
222 + u8 *bcfg, *rcfg;
223 + u8 *board_data;
224 + u8 *radio_data;
225 + u32 offset;
226 +
227 + ar231x_board.config = NULL;
228 + ar231x_board.radio = NULL;
229 + /* Copy the board and radio data to RAM, because accessing the mapped
230 + * memory of the flash directly after booting is not safe */
231 +
232 + /* Try to find valid board and radio data */
233 + bcfg = find_board_config(flash_limit, false);
234 +
235 + /* If that fails, try to at least find valid radio data */
236 + if (!bcfg) {
237 + bcfg = find_board_config(flash_limit, true);
238 + broken_boarddata = 1;
239 + }
240 +
241 + if (!bcfg) {
242 + printk(KERN_WARNING "WARNING: No board configuration data found!\n");
243 + return -ENODEV;
244 + }
245 +
246 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
247 + ar231x_board.config = (struct ar231x_boarddata *) board_data;
248 + memcpy(board_data, bcfg, 0x100);
249 + if (broken_boarddata) {
250 + printk(KERN_WARNING "WARNING: broken board data detected\n");
251 + config = ar231x_board.config;
252 + if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) {
253 + printk(KERN_INFO "Fixing up empty mac addresses\n");
254 + random_ether_addr(config->enet0_mac);
255 + random_ether_addr(config->enet1_mac);
256 + }
257 + }
258 +
259 +
260 + /* Radio config starts 0x100 bytes after board config, regardless
261 + * of what the physical layout on the flash chip looks like */
262 +
263 + if (ar231x_board.radio)
264 + rcfg = (u8 *) ar231x_board.radio;
265 + else
266 + rcfg = find_radio_config(flash_limit, bcfg);
267 +
268 + if (!rcfg)
269 + return -ENODEV;
270 +
271 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
272 + ar231x_board.radio = radio_data;
273 + offset = radio_data - board_data;
274 + printk(KERN_INFO "Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, offset);
275 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
276 + memcpy(radio_data, rcfg, rcfg_size);
277 +
278 + return 0;
279 +}
280 +
281 +static void
282 +ar231x_halt(void)
283 +{
284 + local_irq_disable();
285 + while (1);
286 +}
287 +
288 +void __init
289 +plat_mem_setup(void)
290 +{
291 + _machine_halt = ar231x_halt;
292 + pm_power_off = ar231x_halt;
293 +
294 + ar5312_plat_setup();
295 + ar2315_plat_setup();
296 +
297 + /* Disable data watchpoints */
298 + write_c0_watchlo0(0);
299 +}
300 +
301 +
302 +asmlinkage void
303 +plat_irq_dispatch(void)
304 +{
305 + ar231x_irq_dispatch();
306 +}
307 +
308 +void __init
309 +plat_time_init(void)
310 +{
311 + ar5312_time_init();
312 + ar2315_time_init();
313 +}
314 +
315 +unsigned int __cpuinit
316 +get_c0_compare_irq(void)
317 +{
318 + return CP0_LEGACY_COMPARE_IRQ;
319 +}
320 +
321 +void __init
322 +arch_init_irq(void)
323 +{
324 + clear_c0_status(ST0_IM);
325 + mips_cpu_irq_init();
326 +
327 + /* Initialize interrupt controllers */
328 + ar5312_irq_init();
329 + ar2315_irq_init();
330 +}
331 +
332 +
333 --- /dev/null
334 +++ b/arch/mips/ar231x/prom.c
335 @@ -0,0 +1,37 @@
336 +/*
337 + * This file is subject to the terms and conditions of the GNU General Public
338 + * License. See the file "COPYING" in the main directory of this archive
339 + * for more details.
340 + *
341 + * Copyright MontaVista Software Inc
342 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
343 + * Copyright (C) 2006 FON Technology, SL.
344 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
345 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
346 + */
347 +
348 +/*
349 + * Prom setup file for ar531x
350 + */
351 +
352 +#include <linux/init.h>
353 +#include <linux/autoconf.h>
354 +#include <linux/kernel.h>
355 +#include <linux/string.h>
356 +#include <linux/mm.h>
357 +#include <linux/bootmem.h>
358 +
359 +#include <asm/bootinfo.h>
360 +#include <asm/addrspace.h>
361 +#include "ar5312.h"
362 +#include "ar2315.h"
363 +
364 +void __init prom_init(void)
365 +{
366 + ar5312_prom_init();
367 + ar2315_prom_init();
368 +}
369 +
370 +void __init prom_free_prom_memory(void)
371 +{
372 +}
373 --- /dev/null
374 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
375 @@ -0,0 +1,83 @@
376 +#ifndef __AR531X_PLATFORM_H
377 +#define __AR531X_PLATFORM_H
378 +
379 +/*
380 + * This is board-specific data that is stored in a "fixed" location in flash.
381 + * It is shared across operating systems, so it should not be changed lightly.
382 + * The main reason we need it is in order to extract the ethernet MAC
383 + * address(es).
384 + */
385 +struct ar231x_boarddata {
386 + u32 magic; /* board data is valid */
387 +#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */
388 + u16 cksum; /* checksum (starting with BD_REV 2) */
389 + u16 rev; /* revision of this struct */
390 +#define BD_REV 4
391 + char boardName[64]; /* Name of board */
392 + u16 major; /* Board major number */
393 + u16 minor; /* Board minor number */
394 + u32 flags; /* Board configuration */
395 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
396 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
397 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
398 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
399 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
400 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
401 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
402 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
403 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
404 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
405 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ memCap for testing */
406 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
407 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
408 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
409 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
410 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
411 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
412 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
413 + u16 resetConfigGpio; /* Reset factory GPIO pin */
414 + u16 sysLedGpio; /* System LED GPIO pin */
415 +
416 + u32 cpuFreq; /* CPU core frequency in Hz */
417 + u32 sysFreq; /* System frequency in Hz */
418 + u32 cntFreq; /* Calculated C0_COUNT frequency */
419 +
420 + u8 wlan0_mac[6];
421 + u8 enet0_mac[6];
422 + u8 enet1_mac[6];
423 +
424 + u16 pciId; /* Pseudo PCIID for common code */
425 + u16 memCap; /* cap bank1 in MB */
426 +
427 + /* version 3 */
428 + u8 wlan1_mac[6]; /* (ar5212) */
429 +};
430 +
431 +#define BOARD_CONFIG_BUFSZ 0x1000
432 +
433 +/*
434 + * Platform device information for the Wireless MAC
435 + */
436 +struct ar231x_board_config {
437 + u16 devid;
438 +
439 + /* board config data */
440 + struct ar231x_boarddata *config;
441 +
442 + /* radio calibration data */
443 + const char *radio;
444 +};
445 +
446 +/*
447 + * Platform device information for the Ethernet MAC
448 + */
449 +struct ar231x_eth {
450 + u32 reset_base;
451 + u32 reset_mac;
452 + u32 reset_phy;
453 + u32 phy_base;
454 + struct ar231x_board_config *config;
455 + char *macaddr;
456 +};
457 +
458 +#endif /* __AR531X_PLATFORM_H */
459 --- /dev/null
460 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
461 @@ -0,0 +1,84 @@
462 +/*
463 + * Atheros SoC specific CPU feature overrides
464 + *
465 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
466 + *
467 + * This file was derived from: include/asm-mips/cpu-features.h
468 + * Copyright (C) 2003, 2004 Ralf Baechle
469 + * Copyright (C) 2004 Maciej W. Rozycki
470 + *
471 + * This program is free software; you can redistribute it and/or modify it
472 + * under the terms of the GNU General Public License version 2 as published
473 + * by the Free Software Foundation.
474 + *
475 + */
476 +#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
477 +#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
478 +
479 +/*
480 + * The ATHEROS SoCs have MIPS 4Kc/4KEc core.
481 + */
482 +#define cpu_has_tlb 1
483 +#define cpu_has_4kex 1
484 +#define cpu_has_3k_cache 0
485 +#define cpu_has_4k_cache 1
486 +#define cpu_has_tx39_cache 0
487 +#define cpu_has_sb1_cache 0
488 +#define cpu_has_fpu 0
489 +#define cpu_has_32fpr 0
490 +#define cpu_has_counter 1
491 +/* #define cpu_has_watch ? */
492 +/* #define cpu_has_divec ? */
493 +/* #define cpu_has_vce ? */
494 +/* #define cpu_has_cache_cdex_p ? */
495 +/* #define cpu_has_cache_cdex_s ? */
496 +/* #define cpu_has_prefetch ? */
497 +/* #define cpu_has_mcheck ? */
498 +#define cpu_has_ejtag 1
499 +
500 +#if !defined(CONFIG_ATHEROS_AR5312)
501 +# define cpu_has_llsc 1
502 +#else
503 +/*
504 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
505 + * ll/sc instructions.
506 + */
507 +# define cpu_has_llsc 0
508 +#endif
509 +
510 +#define cpu_has_mips16 0
511 +#define cpu_has_mdmx 0
512 +#define cpu_has_mips3d 0
513 +#define cpu_has_smartmips 0
514 +
515 +/* #define cpu_has_vtag_icache ? */
516 +/* #define cpu_has_dc_aliases ? */
517 +/* #define cpu_has_ic_fills_f_dc ? */
518 +/* #define cpu_has_pindexed_dcache ? */
519 +
520 +/* #define cpu_icache_snoops_remote_store ? */
521 +
522 +#define cpu_has_mips32r1 1
523 +
524 +#if !defined(CONFIG_ATHEROS_AR5312)
525 +# define cpu_has_mips32r2 1
526 +#endif
527 +
528 +#define cpu_has_mips64r1 0
529 +#define cpu_has_mips64r2 0
530 +
531 +#define cpu_has_dsp 0
532 +#define cpu_has_mipsmt 0
533 +
534 +/* #define cpu_has_nofpuex ? */
535 +#define cpu_has_64bits 0
536 +#define cpu_has_64bit_zero_reg 0
537 +#define cpu_has_64bit_gp_regs 0
538 +#define cpu_has_64bit_addresses 0
539 +
540 +/* #define cpu_has_inclusive_pcaches ? */
541 +
542 +/* #define cpu_dcache_line_size() ? */
543 +/* #define cpu_icache_line_size() ? */
544 +
545 +#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */
546 --- /dev/null
547 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
548 @@ -0,0 +1,41 @@
549 +/*
550 + * This file is subject to the terms and conditions of the GNU General Public
551 + * License. See the file "COPYING" in the main directory of this archive
552 + * for more details.
553 + *
554 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
555 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
556 + *
557 + */
558 +#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H
559 +#define __ASM_MACH_GENERIC_DMA_COHERENCE_H
560 +
561 +#define PCI_DMA_OFFSET 0x20000000
562 +
563 +struct device;
564 +
565 +static dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
566 +{
567 + return virt_to_phys(addr) + (dev != NULL ? PCI_DMA_OFFSET : 0);
568 +}
569 +
570 +static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
571 +{
572 + return page_to_phys(page) + (dev != NULL ? PCI_DMA_OFFSET : 0);
573 +}
574 +
575 +static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
576 +{
577 + return (dma_addr > PCI_DMA_OFFSET ? dma_addr - PCI_DMA_OFFSET : dma_addr);
578 +}
579 +
580 +static void plat_unmap_dma_mem(dma_addr_t dma_addr)
581 +{
582 +}
583 +
584 +static inline int plat_device_is_coherent(struct device *dev)
585 +{
586 + return 0;
587 +}
588 +
589 +#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
590 --- /dev/null
591 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
592 @@ -0,0 +1,79 @@
593 +#ifndef _ATHEROS_GPIO_H_
594 +#define _ATHEROS_GPIO_H_
595 +
596 +#include <ar231x.h>
597 +
598 +struct ar231x_gpiodev {
599 + u32 valid_mask;
600 + u32 (*get_output)(void);
601 + u32 (*set_output)(u32 mask, u32 val);
602 + u32 (*get)(void);
603 + u32 (*set)(u32 mask, u32 val);
604 +};
605 +
606 +extern const struct ar231x_gpiodev *ar231x_gpiodev;
607 +
608 +/*
609 + * Wrappers for the generic GPIO layer
610 + */
611 +
612 +static inline int gpio_direction_input(unsigned gpio) {
613 + u32 mask = 1 << gpio;
614 +
615 + if (!(ar231x_gpiodev->valid_mask & mask))
616 + return -ENXIO;
617 +
618 + ar231x_gpiodev->set_output(mask, 0);
619 + return 0;
620 +}
621 +
622 +static inline void gpio_set_value(unsigned gpio, int value) {
623 + u32 mask = 1 << gpio;
624 +
625 + if (!(ar231x_gpiodev->valid_mask & mask))
626 + return;
627 +
628 + ar231x_gpiodev->set(mask, (!!value) * mask);
629 +}
630 +
631 +static inline int gpio_direction_output(unsigned gpio, int value) {
632 + u32 mask = 1 << gpio;
633 +
634 + if (!(ar231x_gpiodev->valid_mask & mask))
635 + return -ENXIO;
636 +
637 + ar231x_gpiodev->set_output(mask, mask);
638 + ar231x_gpiodev->set(mask, (!!value) * mask);
639 + return 0;
640 +}
641 +
642 +/* Reads the gpio pin. Unchecked function */
643 +static inline int gpio_get_value(unsigned gpio) {
644 + u32 mask = 1 << gpio;
645 +
646 + if (!(ar231x_gpiodev->valid_mask & mask))
647 + return 0;
648 +
649 + return !!(ar231x_gpiodev->get() & mask);
650 +}
651 +
652 +static inline int gpio_request(unsigned gpio, const char *label) {
653 + return 0;
654 +}
655 +
656 +static inline void gpio_free(unsigned gpio) {
657 +}
658 +
659 +/* Returns IRQ to attach for gpio. Unchecked function */
660 +static inline int gpio_to_irq(unsigned gpio) {
661 + return AR531X_GPIO_IRQ(gpio);
662 +}
663 +
664 +/* Returns gpio for IRQ attached. Unchecked function */
665 +static inline int irq_to_gpio(unsigned irq) {
666 + return (irq - (AR531X_GPIO_IRQ(0)));
667 +}
668 +
669 +#include <asm-generic/gpio.h> /* cansleep wrappers */
670 +
671 +#endif
672 --- /dev/null
673 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
674 @@ -0,0 +1,6 @@
675 +#ifndef __AR531X_RESET_H
676 +#define __AR531X_RESET_H
677 +
678 +void ar531x_disable_reset_button(void);
679 +
680 +#endif /* __AR531X_RESET_H */
681 --- /dev/null
682 +++ b/arch/mips/include/asm/mach-ar231x/war.h
683 @@ -0,0 +1,25 @@
684 +/*
685 + * This file is subject to the terms and conditions of the GNU General Public
686 + * License. See the file "COPYING" in the main directory of this archive
687 + * for more details.
688 + *
689 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
690 + */
691 +#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H
692 +#define __ASM_MIPS_MACH_ATHEROS_WAR_H
693 +
694 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
695 +#define R4600_V1_HIT_CACHEOP_WAR 0
696 +#define R4600_V2_HIT_CACHEOP_WAR 0
697 +#define R5432_CP0_INTERRUPT_WAR 0
698 +#define BCM1250_M3_WAR 0
699 +#define SIBYTE_1956_WAR 0
700 +#define MIPS4K_ICACHE_REFILL_WAR 0
701 +#define MIPS_CACHE_SYNC_WAR 0
702 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
703 +#define RM9000_CDEX_SMP_WAR 0
704 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
705 +#define R10000_LLSC_WAR 0
706 +#define MIPS34K_MISSED_ITLB_WAR 0
707 +
708 +#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */
709 --- /dev/null
710 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
711 @@ -0,0 +1,580 @@
712 +/*
713 + * Register definitions for AR2315+
714 + *
715 + * This file is subject to the terms and conditions of the GNU General Public
716 + * License. See the file "COPYING" in the main directory of this archive
717 + * for more details.
718 + *
719 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
720 + * Copyright (C) 2006 FON Technology, SL.
721 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
722 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
723 + */
724 +
725 +#ifndef __AR2315_REG_H
726 +#define __AR2315_REG_H
727 +
728 +/*
729 + * IRQs
730 + */
731 +#define AR2315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
732 +#define AR2315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
733 +#define AR2315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
734 +#define AR2315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
735 +#define AR2315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
736 +
737 +/*
738 + * Address map
739 + */
740 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
741 +#define AR2315_WLAN0 0xB0000000 /* Wireless MMR */
742 +#define AR2315_PCI 0xB0100000 /* PCI MMR */
743 +#define AR2315_SDRAMCTL 0xB0300000 /* SDRAM MMR */
744 +#define AR2315_LOCAL 0xB0400000 /* LOCAL BUS MMR */
745 +#define AR2315_ENET0 0xB0500000 /* ETHERNET MMR */
746 +#define AR2315_DSLBASE 0xB1000000 /* RESET CONTROL MMR */
747 +#define AR2315_UART0 0xB1100003 /* UART MMR */
748 +#define AR2315_SPI 0xB1300000 /* SPI FLASH MMR */
749 +#define AR2315_PCIEXT 0x80000000 /* pci external */
750 +
751 +/*
752 + * Reset Register
753 + */
754 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
755 +
756 +#define AR2315_RESET_COLD_AHB 0x00000001
757 +#define AR2315_RESET_COLD_APB 0x00000002
758 +#define AR2315_RESET_COLD_CPU 0x00000004
759 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
760 +#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */
761 +#define AR2317_RESET_SYSTEM 0x00000010
762 +
763 +
764 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
765 +
766 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */
767 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */
768 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
769 +#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
770 +#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */
771 +#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */
772 +#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */
773 +#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */
774 +#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */
775 +#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */
776 +#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */
777 +#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */
778 +
779 +/*
780 + * AHB master arbitration control
781 + */
782 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
783 +
784 +#define AR2315_ARB_CPU 0x00000001 /* CPU, default */
785 +#define AR2315_ARB_WLAN 0x00000002 /* WLAN */
786 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
787 +#define AR2315_ARB_LOCAL 0x00000008 /* LOCAL */
788 +#define AR2315_ARB_PCI 0x00000010 /* PCI */
789 +#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */
790 +#define AR2315_ARB_RETRY 0x00000100 /* retry policy, debug only */
791 +
792 +/*
793 + * Config Register
794 + */
795 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
796 +
797 +#define AR2315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */
798 +#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
799 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
800 +#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */
801 +#define AR2315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */
802 +#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
803 +#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */
804 +
805 +#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
806 +#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */
807 +#define AR2315_CONFIG_PCIAHB 0x00000800
808 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
809 +#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */
810 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
811 +#define AR2315_CONFIG_CPU_PCI 0x00020000
812 +#define AR2315_CONFIG_CPU_MMR 0x00040000
813 +#define AR2315_CONFIG_BIG 0x00000400
814 +
815 +
816 +/*
817 + * NMI control
818 + */
819 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
820 +
821 +#define AR2315_NMI_EN 1
822 +
823 +/*
824 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0).
825 + */
826 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
827 +
828 +#define AR2315_REV_MAJ 0x00f0
829 +#define AR2315_REV_MAJ_S 4
830 +#define AR2315_REV_MIN 0x000f
831 +#define AR2315_REV_MIN_S 0
832 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
833 +
834 +/*
835 + * Interface Enable
836 + */
837 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
838 +
839 +#define AR2315_IF_MASK 0x00000007
840 +#define AR2315_IF_DISABLED 0
841 +#define AR2315_IF_PCI 1
842 +#define AR2315_IF_TS_LOCAL 2
843 +#define AR2315_IF_ALL 3 /* only for emulation with separate pins */
844 +#define AR2315_IF_LOCAL_HOST 0x00000008
845 +#define AR2315_IF_PCI_HOST 0x00000010
846 +#define AR2315_IF_PCI_INTR 0x00000020
847 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
848 +#define AR2315_IF_PCI_CLK_INPUT 0
849 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
850 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
851 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
852 +#define AR2315_IF_PCI_CLK_SHIFT 16
853 +
854 +/*
855 + * APB Interrupt control
856 + */
857 +
858 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
859 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
860 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
861 +
862 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
863 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
864 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
865 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
866 +#define AR2315_ISR_APB 0x0010 /* APB error */
867 +#define AR2315_ISR_TIMER 0x0020 /* timer */
868 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
869 +#define AR2315_ISR_WD 0x0080 /* watchdog */
870 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
871 +
872 +#define AR2315_GISR_MISC 0x0001
873 +#define AR2315_GISR_WLAN0 0x0002
874 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
875 +#define AR2315_GISR_LOCALPCI 0x0008
876 +#define AR2315_GISR_WMACPOLL 0x0010
877 +#define AR2315_GISR_TIMER 0x0020
878 +#define AR2315_GISR_ETHERNET 0x0040
879 +
880 +/*
881 + * Interrupt routing from IO to the processor IP bits
882 + * Define our inter mask and level
883 + */
884 +#define AR2315_INTR_MISCIO SR_IBIT3
885 +#define AR2315_INTR_WLAN0 SR_IBIT4
886 +#define AR2315_INTR_ENET0 SR_IBIT5
887 +#define AR2315_INTR_LOCALPCI SR_IBIT6
888 +#define AR2315_INTR_WMACPOLL SR_IBIT7
889 +#define AR2315_INTR_COMPARE SR_IBIT8
890 +
891 +/*
892 + * Timers
893 + */
894 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
895 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
896 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
897 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
898 +
899 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
900 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
901 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
902 +
903 +/*
904 + * CPU Performance Counters
905 + */
906 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
907 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
908 +
909 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
910 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
911 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
912 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
913 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
914 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
915 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
916 +
917 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
918 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
919 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
920 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
921 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
922 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
923 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
924 +
925 +/*
926 + * AHB Error Reporting.
927 + */
928 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
929 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
930 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
931 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
932 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
933 +
934 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
935 + /* write 1 to clear all bits in ERR0 */
936 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
937 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
938 +
939 +#define AR2315_PROCERR_HMAST 0x0000000f
940 +#define AR2315_PROCERR_HMAST_DFLT 0
941 +#define AR2315_PROCERR_HMAST_WMAC 1
942 +#define AR2315_PROCERR_HMAST_ENET 2
943 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
944 +#define AR2315_PROCERR_HMAST_LOCAL 4
945 +#define AR2315_PROCERR_HMAST_CPU 5
946 +#define AR2315_PROCERR_HMAST_PCITGT 6
947 +
948 +#define AR2315_PROCERR_HMAST_S 0
949 +#define AR2315_PROCERR_HWRITE 0x00000010
950 +#define AR2315_PROCERR_HSIZE 0x00000060
951 +#define AR2315_PROCERR_HSIZE_S 5
952 +#define AR2315_PROCERR_HTRANS 0x00000180
953 +#define AR2315_PROCERR_HTRANS_S 7
954 +#define AR2315_PROCERR_HBURST 0x00000e00
955 +#define AR2315_PROCERR_HBURST_S 9
956 +
957 +/*
958 + * Clock Control
959 + */
960 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
961 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
962 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
963 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
964 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
965 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
966 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
967 +
968 +/* PLLc Control fields */
969 +#define PLLC_REF_DIV_M 0x00000003
970 +#define PLLC_REF_DIV_S 0
971 +#define PLLC_FDBACK_DIV_M 0x0000007C
972 +#define PLLC_FDBACK_DIV_S 2
973 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
974 +#define PLLC_ADD_FDBACK_DIV_S 7
975 +#define PLLC_CLKC_DIV_M 0x0001c000
976 +#define PLLC_CLKC_DIV_S 14
977 +#define PLLC_CLKM_DIV_M 0x00700000
978 +#define PLLC_CLKM_DIV_S 20
979 +
980 +/* CPU CLK Control fields */
981 +#define CPUCLK_CLK_SEL_M 0x00000003
982 +#define CPUCLK_CLK_SEL_S 0
983 +#define CPUCLK_CLK_DIV_M 0x0000000c
984 +#define CPUCLK_CLK_DIV_S 2
985 +
986 +/* AMBA CLK Control fields */
987 +#define AMBACLK_CLK_SEL_M 0x00000003
988 +#define AMBACLK_CLK_SEL_S 0
989 +#define AMBACLK_CLK_DIV_M 0x0000000c
990 +#define AMBACLK_CLK_DIV_S 2
991 +
992 +/*
993 + * GPIO
994 + */
995 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
996 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
997 +#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098)
998 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
999 +
1000 +#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1001 +#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */
1002 +#define AR2315_GPIO_CR_I(x) (0) /* input */
1003 +
1004 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1005 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1006 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1007 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1008 +
1009 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for AR5313_GPIO_INT_* macros */
1010 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1011 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1012 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1013 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1014 +
1015 +#define AR2315_RESET_GPIO 5
1016 +#define AR2315_NUM_GPIO 22
1017 +
1018 +/*
1019 + * PCI Clock Control
1020 + */
1021 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1022 +
1023 +#define AR2315_PCICLK_INPUT_M 0x3
1024 +#define AR2315_PCICLK_INPUT_S 0
1025 +
1026 +#define AR2315_PCICLK_PLLC_CLKM 0
1027 +#define AR2315_PCICLK_PLLC_CLKM1 1
1028 +#define AR2315_PCICLK_PLLC_CLKC 2
1029 +#define AR2315_PCICLK_REF_CLK 3
1030 +
1031 +#define AR2315_PCICLK_DIV_M 0xc
1032 +#define AR2315_PCICLK_DIV_S 2
1033 +
1034 +#define AR2315_PCICLK_IN_FREQ 0
1035 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1036 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1037 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1038 +
1039 +/*
1040 + * Observation Control Register
1041 + */
1042 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1043 +#define OCR_GPIO0_IRIN 0x0040
1044 +#define OCR_GPIO1_IROUT 0x0080
1045 +#define OCR_GPIO3_RXCLR 0x0200
1046 +
1047 +/*
1048 + * General Clock Control
1049 + */
1050 +
1051 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1052 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1053 +#define MISCCLK_PROCREFCLK 0x00000002
1054 +
1055 +/*
1056 + * SDRAM Controller
1057 + * - No read or write buffers are included.
1058 + */
1059 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1060 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1061 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1062 +
1063 +#define SDRAM_DATA_WIDTH_M 0x00006000
1064 +#define SDRAM_DATA_WIDTH_S 13
1065 +
1066 +#define SDRAM_COL_WIDTH_M 0x00001E00
1067 +#define SDRAM_COL_WIDTH_S 9
1068 +
1069 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1070 +#define SDRAM_ROW_WIDTH_S 5
1071 +
1072 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1073 +#define SDRAM_BANKADDR_BITS_S 3
1074 +
1075 +/*
1076 + * SPI Flash Interface Registers
1077 + */
1078 +
1079 +#define AR2315_SPI_CTL (AR2315_SPI + 0x00)
1080 +#define AR2315_SPI_OPCODE (AR2315_SPI + 0x04)
1081 +#define AR2315_SPI_DATA (AR2315_SPI + 0x08)
1082 +
1083 +#define SPI_CTL_START 0x00000100
1084 +#define SPI_CTL_BUSY 0x00010000
1085 +#define SPI_CTL_TXCNT_MASK 0x0000000f
1086 +#define SPI_CTL_RXCNT_MASK 0x000000f0
1087 +#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
1088 +#define SPI_CTL_SIZE_MASK 0x00060000
1089 +
1090 +#define SPI_CTL_CLK_SEL_MASK 0x03000000
1091 +#define SPI_OPCODE_MASK 0x000000ff
1092 +
1093 +/*
1094 + * PCI Bus Interface Registers
1095 + */
1096 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1097 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1098 +
1099 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1100 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1101 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1102 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1103 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1104 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1105 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1106 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1107 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1108 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1109 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1110 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1111 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */
1112 +
1113 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1114 +
1115 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1116 +
1117 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1118 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1119 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1120 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1121 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1122 +
1123 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1124 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1125 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1126 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1127 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1128 +
1129 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1130 +
1131 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1132 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1133 +
1134 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1135 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1136 +
1137 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1138 +
1139 +#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */
1140 +#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */
1141 +#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */
1142 +#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */
1143 +#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */
1144 +#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */
1145 +#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */
1146 +#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */
1147 +#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */
1148 +#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1149 +#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */
1150 +#define AR2315_PCI_EXT_INT 0x02000000
1151 +#define AR2315_PCI_ABORT_INT 0x04000000
1152 +
1153 +#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
1154 +
1155 +#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508)
1156 +#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
1157 +#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */
1158 +
1159 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1160 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1161 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1162 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1163 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1164 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1165 +
1166 +
1167 +/*
1168 + * Local Bus Interface Registers
1169 + */
1170 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1171 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1172 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1173 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1174 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1175 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1176 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1177 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1178 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1179 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1180 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1181 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1182 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1183 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1184 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1185 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1186 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1187 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1188 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1189 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1190 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1191 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1192 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1193 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1194 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1195 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1196 +
1197 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1198 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1199 +
1200 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1201 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1202 +
1203 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1204 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1205 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1206 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1207 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1208 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1209 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1210 +#define AR2315_LBM_TIMEOUT_SHFT 7
1211 +#define AR2315_LBM_PORTMUX 0x07000000
1212 +
1213 +
1214 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1215 +
1216 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1217 +#define AR2315_LB_TXEN_0 0x01
1218 +#define AR2315_LB_TXEN_1 0x02
1219 +#define AR2315_LB_TXEN_2 0x04
1220 +#define AR2315_LB_TXEN_3 0x08
1221 +
1222 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1223 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1224 +
1225 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1226 +#define AR2315_LB_RXEN 0x01
1227 +
1228 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1229 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1230 +
1231 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1232 +#define AR2315_INT_TX_DESC 0x0001
1233 +#define AR2315_INT_TX_OK 0x0002
1234 +#define AR2315_INT_TX_ERR 0x0004
1235 +#define AR2315_INT_TX_EOF 0x0008
1236 +#define AR2315_INT_RX_DESC 0x0010
1237 +#define AR2315_INT_RX_OK 0x0020
1238 +#define AR2315_INT_RX_ERR 0x0040
1239 +#define AR2315_INT_RX_EOF 0x0080
1240 +#define AR2315_INT_TX_TRUNC 0x0100
1241 +#define AR2315_INT_TX_STARVE 0x0200
1242 +#define AR2315_INT_LB_TIMEOUT 0x0400
1243 +#define AR2315_INT_LB_ERR 0x0800
1244 +#define AR2315_INT_MBOX_WR 0x1000
1245 +#define AR2315_INT_MBOX_RD 0x2000
1246 +
1247 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1248 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1249 +
1250 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1251 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1252 +
1253 +/*
1254 + * IR Interface Registers
1255 + */
1256 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1257 +
1258 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1259 +
1260 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1261 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1262 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1263 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */
1264 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1265 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */
1266 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1267 +
1268 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1269 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1270 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1271 +
1272 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1273 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert input polarity */
1274 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert output polarity */
1275 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1276 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 /* */
1277 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */
1278 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */
1279 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */
1280 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */
1281 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */
1282 +
1283 +#define HOST_PCI_DEV_ID 3
1284 +#define HOST_PCI_MBAR0 0x10000000
1285 +#define HOST_PCI_MBAR1 0x20000000
1286 +#define HOST_PCI_MBAR2 0x30000000
1287 +
1288 +#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1289 +#define PCI_DEVICE_MEM_SPACE 0x800000
1290 +
1291 +#endif /* __AR2315_REG_H */
1292 --- /dev/null
1293 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1294 @@ -0,0 +1,236 @@
1295 +/*
1296 + * This file is subject to the terms and conditions of the GNU General Public
1297 + * License. See the file "COPYING" in the main directory of this archive
1298 + * for more details.
1299 + *
1300 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1301 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1302 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1303 + */
1304 +
1305 +#ifndef AR5312_H
1306 +#define AR5312_H
1307 +
1308 +#include <asm/addrspace.h>
1309 +
1310 +/*
1311 + * IRQs
1312 + */
1313 +
1314 +#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
1315 +#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
1316 +#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
1317 +#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
1318 +#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
1319 +
1320 +
1321 +/* Address Map */
1322 +#define AR531X_WLAN0 0x18000000
1323 +#define AR531X_WLAN1 0x18500000
1324 +#define AR531X_ENET0 0x18100000
1325 +#define AR531X_ENET1 0x18200000
1326 +#define AR531X_SDRAMCTL 0x18300000
1327 +#define AR531X_FLASHCTL 0x18400000
1328 +#define AR531X_APBBASE 0x1c000000
1329 +#define AR531X_FLASH 0x1e000000
1330 +#define AR531X_UART0 0xbc000003 /* UART MMR */
1331 +
1332 +/*
1333 + * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that
1334 + * should be considered available. The AR5312 supports 2 enet MACS,
1335 + * even though many reference boards only actually use 1 of them
1336 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1337 + * The AR2312 supports 1 enet MAC.
1338 + */
1339 +#define AR531X_NUM_ENET_MAC 2
1340 +
1341 +/*
1342 + * Need these defines to determine true number of ethernet MACs
1343 + */
1344 +#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1345 +#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1346 +#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1347 +#define AR531X_RADIO_MASK_OFF 0xc8
1348 +#define AR531X_RADIO0_MASK 0x0003
1349 +#define AR531X_RADIO1_MASK 0x000c
1350 +#define AR531X_RADIO1_S 2
1351 +
1352 +/*
1353 + * AR531X_NUM_WMAC defines the number of Wireless MACs that\
1354 + * should be considered available.
1355 + */
1356 +#define AR531X_NUM_WMAC 2
1357 +
1358 +/* Reset/Timer Block Address Map */
1359 +#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000)
1360 +#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */
1361 +#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
1362 +#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */
1363 +#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */
1364 +#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */
1365 +#define AR531X_RESET (AR531X_RESETTMR + 0x0020)
1366 +#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064)
1367 +#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c)
1368 +#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070)
1369 +#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074)
1370 +#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078)
1371 +#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c)
1372 +#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */
1373 +#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */
1374 +
1375 +/* AR531X_WD_CTRL register bit field definitions */
1376 +#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000
1377 +#define AR531X_WD_CTRL_NMI 0x0001
1378 +#define AR531X_WD_CTRL_RESET 0x0002
1379 +
1380 +/* AR531X_ISR register bit field definitions */
1381 +#define AR531X_ISR_NONE 0x0000
1382 +#define AR531X_ISR_TIMER 0x0001
1383 +#define AR531X_ISR_AHBPROC 0x0002
1384 +#define AR531X_ISR_AHBDMA 0x0004
1385 +#define AR531X_ISR_GPIO 0x0008
1386 +#define AR531X_ISR_UART0 0x0010
1387 +#define AR531X_ISR_UART0DMA 0x0020
1388 +#define AR531X_ISR_WD 0x0040
1389 +#define AR531X_ISR_LOCAL 0x0080
1390 +
1391 +/* AR531X_RESET register bit field definitions */
1392 +#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */
1393 +#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */
1394 +#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1395 +#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1396 +#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1397 +#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1398 +#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1399 +#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1400 +#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1401 +#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1402 +#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1403 +#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1404 +#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1405 +#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */
1406 +#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1407 +#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1408 +#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1409 +#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1410 +
1411 +#define AR531X_RESET_WMAC0_BITS \
1412 + AR531X_RESET_WLAN0 |\
1413 + AR531X_RESET_WARM_WLAN0_MAC |\
1414 + AR531X_RESET_WARM_WLAN0_BB
1415 +
1416 +#define AR531X_RESERT_WMAC1_BITS \
1417 + AR531X_RESET_WLAN1 |\
1418 + AR531X_RESET_WARM_WLAN1_MAC |\
1419 + AR531X_RESET_WARM_WLAN1_BB
1420 +
1421 +/* AR5312_CLOCKCTL1 register bit field definitions */
1422 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1423 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1424 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1425 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1426 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1427 +
1428 +/* Valid for AR5312 and AR2312 */
1429 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1430 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1431 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1432 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1433 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1434 +
1435 +/* Valid for AR2313 */
1436 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1437 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1438 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1439 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1440 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1441 +
1442 +
1443 +/* AR531X_ENABLE register bit field definitions */
1444 +#define AR531X_ENABLE_WLAN0 0x0001
1445 +#define AR531X_ENABLE_ENET0 0x0002
1446 +#define AR531X_ENABLE_ENET1 0x0004
1447 +#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1448 +#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1449 +#define AR531X_ENABLE_WLAN1 \
1450 + (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA)
1451 +
1452 +/* AR531X_REV register bit field definitions */
1453 +#define AR531X_REV_WMAC_MAJ 0xf000
1454 +#define AR531X_REV_WMAC_MAJ_S 12
1455 +#define AR531X_REV_WMAC_MIN 0x0f00
1456 +#define AR531X_REV_WMAC_MIN_S 8
1457 +#define AR531X_REV_MAJ 0x00f0
1458 +#define AR531X_REV_MAJ_S 4
1459 +#define AR531X_REV_MIN 0x000f
1460 +#define AR531X_REV_MIN_S 0
1461 +#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN)
1462 +
1463 +/* Major revision numbers, bits 7..4 of Revision ID register */
1464 +#define AR531X_REV_MAJ_AR5312 0x4
1465 +#define AR531X_REV_MAJ_AR2313 0x5
1466 +
1467 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1468 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1469 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1470 +
1471 +/* AR531X_FLASHCTL register bit field definitions */
1472 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1473 +#define FLASHCTL_IDCY_S 0
1474 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1475 +#define FLASHCTL_WST1_S 5
1476 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1477 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1478 +#define FLASHCTL_WST2_S 11
1479 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1480 +#define FLASHCTL_AC_S 16
1481 +#define FLASHCTL_AC_128K 0x00000000
1482 +#define FLASHCTL_AC_256K 0x00010000
1483 +#define FLASHCTL_AC_512K 0x00020000
1484 +#define FLASHCTL_AC_1M 0x00030000
1485 +#define FLASHCTL_AC_2M 0x00040000
1486 +#define FLASHCTL_AC_4M 0x00050000
1487 +#define FLASHCTL_AC_8M 0x00060000
1488 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1489 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1490 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1491 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1492 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1493 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1494 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1495 +#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */
1496 +#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */
1497 +#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */
1498 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1499 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1500 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1501 +
1502 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1503 +#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00)
1504 +#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04)
1505 +#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08)
1506 +
1507 +/* ARM SDRAM Controller -- just enough to determine memory size */
1508 +#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04)
1509 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1510 +#define MEM_CFG1_AC0_S 8
1511 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1512 +#define MEM_CFG1_AC1_S 12
1513 +
1514 +/* GPIO Address Map */
1515 +#define AR531X_GPIO (AR531X_APBBASE + 0x2000)
1516 +#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */
1517 +#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */
1518 +#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */
1519 +
1520 +/* GPIO Control Register bit field definitions */
1521 +#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1522 +#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1523 +#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1524 +#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */
1525 +#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1526 +#define AR531X_NUM_GPIO 8
1527 +
1528 +
1529 +#endif
1530 +
1531 --- /dev/null
1532 +++ b/arch/mips/ar231x/ar5312.c
1533 @@ -0,0 +1,563 @@
1534 +/*
1535 + * This file is subject to the terms and conditions of the GNU General Public
1536 + * License. See the file "COPYING" in the main directory of this archive
1537 + * for more details.
1538 + *
1539 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1540 + * Copyright (C) 2006 FON Technology, SL.
1541 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1542 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1543 + */
1544 +
1545 +/*
1546 + * Platform devices for Atheros SoCs
1547 + */
1548 +
1549 +#include <linux/autoconf.h>
1550 +#include <linux/init.h>
1551 +#include <linux/module.h>
1552 +#include <linux/types.h>
1553 +#include <linux/string.h>
1554 +#include <linux/mtd/physmap.h>
1555 +#include <linux/platform_device.h>
1556 +#include <linux/kernel.h>
1557 +#include <linux/reboot.h>
1558 +#include <linux/leds.h>
1559 +#include <asm/bootinfo.h>
1560 +#include <asm/reboot.h>
1561 +#include <asm/time.h>
1562 +#include <asm/irq.h>
1563 +#include <asm/io.h>
1564 +#include <gpio.h>
1565 +
1566 +#include <ar231x_platform.h>
1567 +#include <ar5312_regs.h>
1568 +#include <ar231x.h>
1569 +#include "devices.h"
1570 +#include "ar5312.h"
1571 +
1572 +#define IS_5312() (current_cpu_data.cputype != CPU_4KEC)
1573 +
1574 +static void
1575 +ar5312_misc_irq_dispatch(void)
1576 +{
1577 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR);
1578 +
1579 + if (ar231x_misc_intrs & AR531X_ISR_TIMER) {
1580 + do_IRQ(AR531X_MISC_IRQ_TIMER);
1581 + (void)ar231x_read_reg(AR531X_TIMER);
1582 + } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC)
1583 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
1584 + else if ((ar231x_misc_intrs & AR531X_ISR_UART0))
1585 + do_IRQ(AR531X_MISC_IRQ_UART0);
1586 + else if (ar231x_misc_intrs & AR531X_ISR_WD)
1587 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
1588 + else
1589 + do_IRQ(AR531X_MISC_IRQ_NONE);
1590 +}
1591 +
1592 +void
1593 +ar5312_irq_dispatch(void)
1594 +{
1595 + int pending = read_c0_status() & read_c0_cause();
1596 +
1597 + if (pending & CAUSEF_IP2)
1598 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1599 + else if (pending & CAUSEF_IP3)
1600 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1601 + else if (pending & CAUSEF_IP4)
1602 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1603 + else if (pending & CAUSEF_IP5)
1604 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1605 + else if (pending & CAUSEF_IP6)
1606 + ar5312_misc_irq_dispatch();
1607 + else if (pending & CAUSEF_IP7)
1608 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
1609 +}
1610 +
1611 +
1612 +/* Enable the specified AR531X_MISC_IRQ interrupt */
1613 +static void
1614 +ar5312_misc_intr_enable(unsigned int irq)
1615 +{
1616 + unsigned int imr;
1617 +
1618 + imr = ar231x_read_reg(AR531X_IMR);
1619 + imr |= (1 << (irq - AR531X_MISC_IRQ_BASE - 1));
1620 + ar231x_write_reg(AR531X_IMR, imr);
1621 +}
1622 +
1623 +/* Disable the specified AR531X_MISC_IRQ interrupt */
1624 +static void
1625 +ar5312_misc_intr_disable(unsigned int irq)
1626 +{
1627 + unsigned int imr;
1628 +
1629 + imr = ar231x_read_reg(AR531X_IMR);
1630 + imr &= ~(1 << (irq - AR531X_MISC_IRQ_BASE - 1));
1631 + ar231x_write_reg(AR531X_IMR, imr);
1632 + ar231x_read_reg(AR531X_IMR); /* flush write buffer */
1633 +}
1634 +
1635 +static unsigned int
1636 +ar5312_misc_intr_startup(unsigned int irq)
1637 +{
1638 + ar5312_misc_intr_enable(irq);
1639 + return 0;
1640 +}
1641 +
1642 +static void
1643 +ar5312_misc_intr_end(unsigned int irq)
1644 +{
1645 + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
1646 + ar5312_misc_intr_enable(irq);
1647 +}
1648 +
1649 +static struct irq_chip ar5312_misc_intr_controller = {
1650 + .name = "AR5312-MISC",
1651 + .startup = ar5312_misc_intr_startup,
1652 + .shutdown = ar5312_misc_intr_disable,
1653 + .enable = ar5312_misc_intr_enable,
1654 + .disable = ar5312_misc_intr_disable,
1655 + .ack = ar5312_misc_intr_disable,
1656 + .end = ar5312_misc_intr_end,
1657 +};
1658 +
1659 +
1660 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1661 +{
1662 + u32 proc1 = ar231x_read_reg(AR531X_PROC1);
1663 + u32 procAddr = ar231x_read_reg(AR531X_PROCADDR); /* clears error state */
1664 + u32 dma1 = ar231x_read_reg(AR531X_DMA1);
1665 + u32 dmaAddr = ar231x_read_reg(AR531X_DMAADDR); /* clears error state */
1666 +
1667 + printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1668 + procAddr, proc1, dmaAddr, dma1);
1669 +
1670 + machine_restart("AHB error"); /* Catastrophic failure */
1671 + return IRQ_HANDLED;
1672 +}
1673 +
1674 +
1675 +static struct irqaction ar5312_ahb_proc_interrupt = {
1676 + .handler = ar5312_ahb_proc_handler,
1677 + .flags = IRQF_DISABLED,
1678 + .name = "ar5312_ahb_proc_interrupt",
1679 +};
1680 +
1681 +
1682 +static struct irqaction cascade = {
1683 + .handler = no_action,
1684 + .flags = IRQF_DISABLED,
1685 + .name = "cascade",
1686 +};
1687 +
1688 +void __init ar5312_irq_init(void)
1689 +{
1690 + int i;
1691 +
1692 + if (!IS_5312())
1693 + return;
1694 +
1695 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1696 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
1697 + int irq = AR531X_MISC_IRQ_BASE + i;
1698 + irq_desc[irq].status = IRQ_DISABLED;
1699 + irq_desc[irq].action = NULL;
1700 + irq_desc[irq].depth = 1;
1701 + irq_desc[irq].chip = &ar5312_misc_intr_controller;
1702 + }
1703 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1704 + setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
1705 +}
1706 +
1707 +const struct ar231x_gpiodev ar5312_gpiodev;
1708 +
1709 +static u32
1710 +ar5312_gpio_get_output(void)
1711 +{
1712 + u32 reg;
1713 + reg = ~(ar231x_read_reg(AR531X_GPIO_CR));
1714 + reg &= ar5312_gpiodev.valid_mask;
1715 + return reg;
1716 +}
1717 +
1718 +static u32
1719 +ar5312_gpio_set_output(u32 mask, u32 val)
1720 +{
1721 + u32 reg;
1722 +
1723 + reg = ar231x_read_reg(AR531X_GPIO_CR);
1724 + reg |= mask;
1725 + reg &= ~val;
1726 + ar231x_write_reg(AR531X_GPIO_CR, reg);
1727 + return reg;
1728 +}
1729 +
1730 +static u32
1731 +ar5312_gpio_get(void)
1732 +{
1733 + u32 reg;
1734 + reg = ar231x_read_reg(AR531X_GPIO_DI);
1735 + reg &= ar5312_gpiodev.valid_mask;
1736 + return reg;
1737 +}
1738 +
1739 +static u32
1740 +ar5312_gpio_set(u32 mask, u32 value)
1741 +{
1742 + u32 reg;
1743 + reg = ar231x_read_reg(AR531X_GPIO_DO);
1744 + reg &= ~mask;
1745 + reg |= value;
1746 + ar231x_write_reg(AR531X_GPIO_DO, reg);
1747 + return reg;
1748 +}
1749 +
1750 +const struct ar231x_gpiodev ar5312_gpiodev = {
1751 + .valid_mask = (1 << 8) - 1,
1752 + .get_output = ar5312_gpio_get_output,
1753 + .set_output = ar5312_gpio_set_output,
1754 + .get = ar5312_gpio_get,
1755 + .set = ar5312_gpio_set,
1756 +};
1757 +
1758 +static struct physmap_flash_data ar5312_flash_data = {
1759 + .width = 2,
1760 +};
1761 +
1762 +static struct resource ar5312_flash_resource = {
1763 + .start = AR531X_FLASH,
1764 + .end = AR531X_FLASH + 0x800000 - 1,
1765 + .flags = IORESOURCE_MEM,
1766 +};
1767 +
1768 +static struct ar231x_eth ar5312_eth0_data = {
1769 + .reset_base = AR531X_RESET,
1770 + .reset_mac = AR531X_RESET_ENET0,
1771 + .reset_phy = AR531X_RESET_EPHY0,
1772 + .phy_base = KSEG1ADDR(AR531X_ENET0),
1773 + .config = &ar231x_board,
1774 +};
1775 +
1776 +static struct ar231x_eth ar5312_eth1_data = {
1777 + .reset_base = AR531X_RESET,
1778 + .reset_mac = AR531X_RESET_ENET1,
1779 + .reset_phy = AR531X_RESET_EPHY1,
1780 + .phy_base = KSEG1ADDR(AR531X_ENET1),
1781 + .config = &ar231x_board,
1782 +};
1783 +
1784 +static struct platform_device ar5312_physmap_flash = {
1785 + .name = "physmap-flash",
1786 + .id = 0,
1787 + .dev.platform_data = &ar5312_flash_data,
1788 + .resource = &ar5312_flash_resource,
1789 + .num_resources = 1,
1790 +};
1791 +
1792 +#ifdef CONFIG_LEDS_GPIO
1793 +static struct gpio_led ar5312_leds[] = {
1794 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1795 +};
1796 +
1797 +static const struct gpio_led_platform_data ar5312_led_data = {
1798 + .num_leds = ARRAY_SIZE(ar5312_leds),
1799 + .leds = (void *) ar5312_leds,
1800 +};
1801 +
1802 +static struct platform_device ar5312_gpio_leds = {
1803 + .name = "leds-gpio",
1804 + .id = -1,
1805 + .dev.platform_data = (void *) &ar5312_led_data,
1806 +};
1807 +#endif
1808 +
1809 +/*
1810 + * NB: This mapping size is larger than the actual flash size,
1811 + * but this shouldn't be a problem here, because the flash
1812 + * will simply be mapped multiple times.
1813 + */
1814 +static char __init *ar5312_flash_limit(void)
1815 +{
1816 + u32 ctl;
1817 + /*
1818 + * Configure flash bank 0.
1819 + * Assume 8M window size. Flash will be aliased if it's smaller
1820 + */
1821 + ctl = FLASHCTL_E |
1822 + FLASHCTL_AC_8M |
1823 + FLASHCTL_RBLE |
1824 + (0x01 << FLASHCTL_IDCY_S) |
1825 + (0x07 << FLASHCTL_WST1_S) |
1826 + (0x07 << FLASHCTL_WST2_S) |
1827 + (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW);
1828 +
1829 + ar231x_write_reg(AR531X_FLASHCTL0, ctl);
1830 +
1831 + /* Disable other flash banks */
1832 + ar231x_write_reg(AR531X_FLASHCTL1,
1833 + ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC));
1834 +
1835 + ar231x_write_reg(AR531X_FLASHCTL2,
1836 + ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC));
1837 +
1838 + return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000);
1839 +}
1840 +
1841 +int __init ar5312_init_devices(void)
1842 +{
1843 + struct ar231x_boarddata *config;
1844 + u32 fctl = 0;
1845 + const u8 *radio;
1846 + u8 *c;
1847 +
1848 + if (!IS_5312())
1849 + return 0;
1850 +
1851 + /* Locate board/radio config data */
1852 + ar231x_find_config(ar5312_flash_limit());
1853 + config = ar231x_board.config;
1854 +
1855 +
1856 + /*
1857 + * Chip IDs and hardware detection for some Atheros
1858 + * models are really broken!
1859 + *
1860 + * Atheros uses a disabled WMAC0 and Silicon ID of AR5312
1861 + * as indication for AR2312, which is otherwise
1862 + * indistinguishable from the real AR5312.
1863 + */
1864 + if (ar231x_board.radio) {
1865 + radio = ar231x_board.radio + AR531X_RADIO_MASK_OFF;
1866 + if ((*((const u32 *) radio) & AR531X_RADIO0_MASK) == 0)
1867 + config->flags |= BD_ISCASPER;
1868 + } else
1869 + radio = NULL;
1870 +
1871 + /* AR2313 has CPU minor rev. 10 */
1872 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1873 + ar231x_devtype = DEV_TYPE_AR2313;
1874 +
1875 + /* AR2312 shares the same Silicon ID as AR5312 */
1876 + else if (config->flags & BD_ISCASPER)
1877 + ar231x_devtype = DEV_TYPE_AR2312;
1878 +
1879 + /* Everything else is probably AR5312 or compatible */
1880 + else
1881 + ar231x_devtype = DEV_TYPE_AR5312;
1882 +
1883 + /* fixup flash width */
1884 + fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW;
1885 + switch (fctl) {
1886 + case FLASHCTL_MWx16:
1887 + ar5312_flash_data.width = 2;
1888 + break;
1889 + case FLASHCTL_MWx8:
1890 + default:
1891 + ar5312_flash_data.width = 1;
1892 + break;
1893 + }
1894 +
1895 + platform_device_register(&ar5312_physmap_flash);
1896 +
1897 +#ifdef CONFIG_LEDS_GPIO
1898 + ar5312_leds[0].gpio = config->sysLedGpio;
1899 + platform_device_register(&ar5312_gpio_leds);
1900 +#endif
1901 +
1902 + /* Fix up MAC addresses if necessary */
1903 + if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6))
1904 + memcpy(config->enet0_mac, config->enet1_mac, 6);
1905 +
1906 + /* If ENET0 and ENET1 have the same mac address,
1907 + * increment the one from ENET1 */
1908 + if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) {
1909 + c = config->enet1_mac + 5;
1910 + while ((c >= config->enet1_mac) && !(++(*c)))
1911 + c--;
1912 + }
1913 +
1914 + switch(ar231x_devtype) {
1915 + case DEV_TYPE_AR5312:
1916 + ar5312_eth0_data.macaddr = config->enet0_mac;
1917 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0),
1918 + AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data);
1919 +
1920 + ar5312_eth1_data.macaddr = config->enet1_mac;
1921 + ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1),
1922 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1923 +
1924 + if (!ar231x_board.radio)
1925 + return 0;
1926 +
1927 + if (*((u32 *) ar231x_board.radio) & AR531X_RADIO0_MASK)
1928 + ar231x_add_wmac(0, AR531X_WLAN0,
1929 + AR5312_IRQ_WLAN0_INTRS);
1930 +
1931 + break;
1932 + /*
1933 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1934 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1935 + */
1936 + case DEV_TYPE_AR2312:
1937 + case DEV_TYPE_AR2313:
1938 + ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base;
1939 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1940 + ar5312_eth1_data.macaddr = config->enet0_mac;
1941 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1),
1942 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1943 +
1944 + if (!ar231x_board.radio)
1945 + return 0;
1946 + break;
1947 + default:
1948 + break;
1949 + }
1950 +
1951 + if (*((u32 *) ar231x_board.radio) & AR531X_RADIO1_MASK)
1952 + ar231x_add_wmac(1, AR531X_WLAN1,
1953 + AR5312_IRQ_WLAN1_INTRS);
1954 +
1955 + return 0;
1956 +}
1957 +
1958 +
1959 +static void ar5312_restart(char *command)
1960 +{
1961 + /* reset the system */
1962 + local_irq_disable();
1963 + while(1) {
1964 + ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM);
1965 + }
1966 +}
1967 +
1968 +
1969 +/*
1970 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1971 + * to determine the predevisor value.
1972 + */
1973 +static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = {
1974 + 1,
1975 + 2,
1976 + 4,
1977 + 5
1978 +};
1979 +
1980 +
1981 +static int __init
1982 +ar5312_cpu_frequency(void)
1983 +{
1984 + unsigned int result;
1985 + unsigned int predivide_mask, predivide_shift;
1986 + unsigned int multiplier_mask, multiplier_shift;
1987 + unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier;
1988 + unsigned int doubler_mask;
1989 + u16 devid;
1990 +
1991 + /* Trust the bootrom's idea of cpu frequency. */
1992 + if ((result = ar231x_read_reg(AR5312_SCRATCH)))
1993 + return result;
1994 +
1995 + devid = ar231x_read_reg(AR531X_REV);
1996 + devid &= AR531X_REV_MAJ;
1997 + devid >>= AR531X_REV_MAJ_S;
1998 + if (devid == AR531X_REV_MAJ_AR2313) {
1999 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
2000 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
2001 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
2002 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
2003 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
2004 + } else { /* AR5312 and AR2312 */
2005 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
2006 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
2007 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
2008 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
2009 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
2010 + }
2011 +
2012 + /*
2013 + * Clocking is derived from a fixed 40MHz input clock.
2014 + *
2015 + * cpuFreq = InputClock * MULT (where MULT is PLL multiplier)
2016 + * sysFreq = cpuFreq / 4 (used for APB clock, serial,
2017 + * flash, Timer, Watchdog Timer)
2018 + *
2019 + * cntFreq = cpuFreq / 2 (use for CPU count/compare)
2020 + *
2021 + * So, for example, with a PLL multiplier of 5, we have
2022 + *
2023 + * cpuFreq = 200MHz
2024 + * sysFreq = 50MHz
2025 + * cntFreq = 100MHz
2026 + *
2027 + * We compute the CPU frequency, based on PLL settings.
2028 + */
2029 +
2030 + clockCtl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2031 + preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift;
2032 + preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect];
2033 + multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift;
2034 +
2035 + if (clockCtl1 & doubler_mask) {
2036 + multiplier = multiplier << 1;
2037 + }
2038 + return (40000000 / preDivisor) * multiplier;
2039 +}
2040 +
2041 +static inline int
2042 +ar5312_sys_frequency(void)
2043 +{
2044 + return ar5312_cpu_frequency() / 4;
2045 +}
2046 +
2047 +void __init
2048 +ar5312_time_init(void)
2049 +{
2050 + if (!IS_5312())
2051 + return;
2052 +
2053 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2054 +}
2055 +
2056 +
2057 +void __init
2058 +ar5312_prom_init(void)
2059 +{
2060 + u32 memsize, memcfg, bank0AC, bank1AC;
2061 + u32 devid;
2062 +
2063 + if (!IS_5312())
2064 + return;
2065 +
2066 + /* Detect memory size */
2067 + memcfg = ar231x_read_reg(AR531X_MEM_CFG1);
2068 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2069 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2070 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0)
2071 + + (bank1AC ? (1 << (bank1AC+1)) : 0);
2072 + memsize <<= 20;
2073 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2074 +
2075 + devid = ar231x_read_reg(AR531X_REV);
2076 + devid >>= AR531X_REV_WMAC_MIN_S;
2077 + devid &= AR531X_REV_CHIP;
2078 + ar231x_board.devid = (u16) devid;
2079 + ar231x_gpiodev = &ar5312_gpiodev;
2080 +}
2081 +
2082 +void __init
2083 +ar5312_plat_setup(void)
2084 +{
2085 + if (!IS_5312())
2086 + return;
2087 +
2088 + /* Clear any lingering AHB errors */
2089 + ar231x_read_reg(AR531X_PROCADDR);
2090 + ar231x_read_reg(AR531X_DMAADDR);
2091 + ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
2092 +
2093 + _machine_restart = ar5312_restart;
2094 + ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency());
2095 +}
2096 +
2097 --- /dev/null
2098 +++ b/arch/mips/ar231x/ar2315.c
2099 @@ -0,0 +1,679 @@
2100 +/*
2101 + * This file is subject to the terms and conditions of the GNU General Public
2102 + * License. See the file "COPYING" in the main directory of this archive
2103 + * for more details.
2104 + *
2105 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2106 + * Copyright (C) 2006 FON Technology, SL.
2107 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2108 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2109 + */
2110 +
2111 +/*
2112 + * Platform devices for Atheros SoCs
2113 + */
2114 +
2115 +#include <linux/autoconf.h>
2116 +#include <linux/init.h>
2117 +#include <linux/module.h>
2118 +#include <linux/types.h>
2119 +#include <linux/string.h>
2120 +#include <linux/platform_device.h>
2121 +#include <linux/kernel.h>
2122 +#include <linux/reboot.h>
2123 +#include <linux/delay.h>
2124 +#include <linux/leds.h>
2125 +#include <asm/bootinfo.h>
2126 +#include <asm/reboot.h>
2127 +#include <asm/time.h>
2128 +#include <asm/irq.h>
2129 +#include <asm/io.h>
2130 +#include <asm/gpio.h>
2131 +
2132 +#include <ar231x_platform.h>
2133 +#include <ar2315_regs.h>
2134 +#include <ar231x.h>
2135 +#include "devices.h"
2136 +#include "ar2315.h"
2137 +
2138 +#define IS_2315() (current_cpu_data.cputype == CPU_4KEC)
2139 +
2140 +static u32 gpiointmask = 0, gpiointval = 0;
2141 +
2142 +static inline void ar2315_gpio_irq(void)
2143 +{
2144 + u32 pend;
2145 + int bit = -1;
2146 +
2147 + /* only do one gpio interrupt at a time */
2148 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2149 +
2150 + if (pend) {
2151 + bit = fls(pend) - 1;
2152 + printk("GPIO IRQ: pend=0x%08x, val=%08x, bit=%d\n", pend, gpiointval, bit);
2153 + pend &= ~(1 << bit);
2154 + gpiointval ^= (1 << bit);
2155 + printk("AFTER IRQ: pend=0x%08x, val=%08x, bit=%d\n", pend, gpiointval, bit);
2156 + }
2157 +
2158 + if (!pend)
2159 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2160 +
2161 + if (bit >= 0)
2162 + do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
2163 +}
2164 +
2165 +
2166 +/*
2167 + * Called when an interrupt is received, this function
2168 + * determines exactly which interrupt it was, and it
2169 + * invokes the appropriate handler.
2170 + *
2171 + * Implicitly, we also define interrupt priority by
2172 + * choosing which to dispatch first.
2173 + */
2174 +static void
2175 +ar2315_irq_dispatch(void)
2176 +{
2177 + int pending = read_c0_status() & read_c0_cause();
2178 +
2179 + if (pending & CAUSEF_IP3)
2180 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2181 + else if (pending & CAUSEF_IP4)
2182 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2183 + else if (pending & CAUSEF_IP2) {
2184 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR);
2185 +
2186 + if (misc_intr & AR2315_ISR_SPI)
2187 + do_IRQ(AR531X_MISC_IRQ_SPI);
2188 + else if (misc_intr & AR2315_ISR_TIMER)
2189 + do_IRQ(AR531X_MISC_IRQ_TIMER);
2190 + else if (misc_intr & AR2315_ISR_AHB)
2191 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
2192 + else if (misc_intr & AR2315_ISR_GPIO)
2193 + ar2315_gpio_irq();
2194 + else if (misc_intr & AR2315_ISR_UART0)
2195 + do_IRQ(AR531X_MISC_IRQ_UART0);
2196 + else if (misc_intr & AR2315_ISR_WD)
2197 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
2198 + else
2199 + do_IRQ(AR531X_MISC_IRQ_NONE);
2200 + } else if (pending & CAUSEF_IP7)
2201 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
2202 +}
2203 +
2204 +static void ar2315_set_gpiointmask(int gpio, int level)
2205 +{
2206 + u32 reg;
2207 +
2208 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2209 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2210 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2211 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2212 +}
2213 +
2214 +static void ar2315_gpio_intr_enable(unsigned int irq)
2215 +{
2216 + unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
2217 +
2218 + /* reconfigure GPIO line as input */
2219 + ar231x_mask_reg(AR2315_GPIO_CR, AR2315_GPIO_CR_M(gpio), AR2315_GPIO_CR_I(gpio));
2220 +
2221 + /* Enable interrupt with edge detection */
2222 + gpiointmask |= (1 << gpio);
2223 + ar2315_set_gpiointmask(gpio, 3);
2224 +}
2225 +
2226 +static void ar2315_gpio_intr_disable(unsigned int irq)
2227 +{
2228 + unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
2229 +
2230 + /* Disable interrupt */
2231 + gpiointmask &= ~(1 << gpio);
2232 + ar2315_set_gpiointmask(gpio, 0);
2233 +}
2234 +
2235 +static unsigned int
2236 +ar2315_gpio_intr_startup(unsigned int irq)
2237 +{
2238 + ar2315_gpio_intr_enable(irq);
2239 + return 0;
2240 +}
2241 +
2242 +static void
2243 +ar2315_gpio_intr_end(unsigned int irq)
2244 +{
2245 + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
2246 + ar2315_gpio_intr_enable(irq);
2247 +}
2248 +
2249 +static struct irq_chip ar2315_gpio_intr_controller = {
2250 + .typename = "AR2315-GPIO",
2251 + .startup = ar2315_gpio_intr_startup,
2252 + .shutdown = ar2315_gpio_intr_disable,
2253 + .enable = ar2315_gpio_intr_enable,
2254 + .disable = ar2315_gpio_intr_disable,
2255 + .ack = ar2315_gpio_intr_disable,
2256 + .end = ar2315_gpio_intr_end,
2257 +};
2258 +
2259 +static void
2260 +ar2315_misc_intr_enable(unsigned int irq)
2261 +{
2262 + unsigned int imr;
2263 +
2264 + imr = ar231x_read_reg(AR2315_IMR);
2265 + switch(irq) {
2266 + case AR531X_MISC_IRQ_SPI:
2267 + imr |= AR2315_ISR_SPI;
2268 + break;
2269 + case AR531X_MISC_IRQ_TIMER:
2270 + imr |= AR2315_ISR_TIMER;
2271 + break;
2272 + case AR531X_MISC_IRQ_AHB_PROC:
2273 + imr |= AR2315_ISR_AHB;
2274 + break;
2275 + case AR531X_MISC_IRQ_GPIO:
2276 + imr |= AR2315_ISR_GPIO;
2277 + break;
2278 + case AR531X_MISC_IRQ_UART0:
2279 + imr |= AR2315_ISR_UART0;
2280 + break;
2281 + case AR531X_MISC_IRQ_WATCHDOG:
2282 + imr |= AR2315_ISR_WD;
2283 + break;
2284 + default:
2285 + break;
2286 + }
2287 + ar231x_write_reg(AR2315_IMR, imr);
2288 +}
2289 +
2290 +static void
2291 +ar2315_misc_intr_disable(unsigned int irq)
2292 +{
2293 + unsigned int imr;
2294 +
2295 + imr = ar231x_read_reg(AR2315_IMR);
2296 + switch(irq) {
2297 + case AR531X_MISC_IRQ_SPI:
2298 + imr &= ~AR2315_ISR_SPI;
2299 + break;
2300 + case AR531X_MISC_IRQ_TIMER:
2301 + imr &= ~AR2315_ISR_TIMER;
2302 + break;
2303 + case AR531X_MISC_IRQ_AHB_PROC:
2304 + imr &= ~AR2315_ISR_AHB;
2305 + break;
2306 + case AR531X_MISC_IRQ_GPIO:
2307 + imr &= ~AR2315_ISR_GPIO;
2308 + break;
2309 + case AR531X_MISC_IRQ_UART0:
2310 + imr &= ~AR2315_ISR_UART0;
2311 + break;
2312 + case AR531X_MISC_IRQ_WATCHDOG:
2313 + imr &= ~AR2315_ISR_WD;
2314 + break;
2315 + default:
2316 + break;
2317 + }
2318 + ar231x_write_reg(AR2315_IMR, imr);
2319 +}
2320 +
2321 +static unsigned int
2322 +ar2315_misc_intr_startup(unsigned int irq)
2323 +{
2324 + ar2315_misc_intr_enable(irq);
2325 + return 0;
2326 +}
2327 +
2328 +static void
2329 +ar2315_misc_intr_end(unsigned int irq)
2330 +{
2331 + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
2332 + ar2315_misc_intr_enable(irq);
2333 +}
2334 +
2335 +
2336 +static struct irq_chip ar2315_misc_intr_controller = {
2337 + .typename = "AR2315-MISC",
2338 + .startup = ar2315_misc_intr_startup,
2339 + .shutdown = ar2315_misc_intr_disable,
2340 + .enable = ar2315_misc_intr_enable,
2341 + .disable = ar2315_misc_intr_disable,
2342 + .ack = ar2315_misc_intr_disable,
2343 + .end = ar2315_misc_intr_end,
2344 +};
2345 +
2346 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2347 +{
2348 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2349 + ar231x_read_reg(AR2315_AHB_ERR1);
2350 +
2351 + printk(KERN_ERR "AHB fatal error\n");
2352 + machine_restart("AHB error"); /* Catastrophic failure */
2353 +
2354 + return IRQ_HANDLED;
2355 +}
2356 +
2357 +static struct irqaction ar2315_ahb_proc_interrupt = {
2358 + .handler = ar2315_ahb_proc_handler,
2359 + .flags = IRQF_DISABLED,
2360 + .name = "ar2315_ahb_proc_interrupt",
2361 +};
2362 +
2363 +static struct irqaction cascade = {
2364 + .handler = no_action,
2365 + .flags = IRQF_DISABLED,
2366 + .name = "cascade",
2367 +};
2368 +
2369 +void
2370 +ar2315_irq_init(void)
2371 +{
2372 + int i;
2373 +
2374 + if (!IS_2315())
2375 + return;
2376 +
2377 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2378 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2379 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
2380 + int irq = AR531X_MISC_IRQ_BASE + i;
2381 + irq_desc[irq].status = IRQ_DISABLED;
2382 + irq_desc[irq].action = NULL;
2383 + irq_desc[irq].depth = 1;
2384 + irq_desc[irq].chip = &ar2315_misc_intr_controller;
2385 + }
2386 + for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) {
2387 + int irq = AR531X_GPIO_IRQ_BASE + i;
2388 + irq_desc[irq].status = IRQ_DISABLED;
2389 + irq_desc[irq].action = NULL;
2390 + irq_desc[irq].depth = 1;
2391 + irq_desc[irq].chip = &ar2315_gpio_intr_controller;
2392 + }
2393 + setup_irq(AR531X_MISC_IRQ_GPIO, &cascade);
2394 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt);
2395 + setup_irq(AR2315_IRQ_MISC_INTRS, &cascade);
2396 +}
2397 +
2398 +const struct ar231x_gpiodev ar2315_gpiodev;
2399 +
2400 +static u32
2401 +ar2315_gpio_get_output(void)
2402 +{
2403 + u32 reg;
2404 + reg = ar231x_read_reg(AR2315_GPIO_CR);
2405 + reg &= ar2315_gpiodev.valid_mask;
2406 + return reg;
2407 +}
2408 +
2409 +static u32
2410 +ar2315_gpio_set_output(u32 mask, u32 val)
2411 +{
2412 + u32 reg;
2413 +
2414 + reg = ar231x_read_reg(AR2315_GPIO_CR);
2415 + reg &= ~mask;
2416 + reg |= val;
2417 + ar231x_write_reg(AR2315_GPIO_CR, reg);
2418 + return reg;
2419 +}
2420 +
2421 +static u32
2422 +ar2315_gpio_get(void)
2423 +{
2424 + u32 reg;
2425 + reg = ar231x_read_reg(AR2315_GPIO_DI);
2426 + reg &= ar2315_gpiodev.valid_mask;
2427 + return reg;
2428 +}
2429 +
2430 +static u32
2431 +ar2315_gpio_set(u32 mask, u32 value)
2432 +{
2433 + u32 reg;
2434 + reg = ar231x_read_reg(AR2315_GPIO_DO);
2435 + reg &= ~mask;
2436 + reg |= value;
2437 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2438 + return reg;
2439 +}
2440 +
2441 +const struct ar231x_gpiodev ar2315_gpiodev = {
2442 + .valid_mask = (1 << 22) - 1,
2443 + .get_output = ar2315_gpio_get_output,
2444 + .set_output = ar2315_gpio_set_output,
2445 + .get = ar2315_gpio_get,
2446 + .set = ar2315_gpio_set,
2447 +};
2448 +
2449 +static struct ar231x_eth ar2315_eth_data = {
2450 + .reset_base = AR2315_RESET,
2451 + .reset_mac = AR2315_RESET_ENET0,
2452 + .reset_phy = AR2315_RESET_EPHY0,
2453 + .phy_base = AR2315_ENET0,
2454 + .config = &ar231x_board,
2455 +};
2456 +
2457 +static struct resource ar2315_spiflash_res[] = {
2458 + {
2459 + .name = "flash_base",
2460 + .flags = IORESOURCE_MEM,
2461 + .start = KSEG1ADDR(AR2315_SPI_READ),
2462 + .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1,
2463 + },
2464 + {
2465 + .name = "flash_regs",
2466 + .flags = IORESOURCE_MEM,
2467 + .start = 0x11300000,
2468 + .end = 0x11300012,
2469 + },
2470 +};
2471 +
2472 +static struct platform_device ar2315_spiflash = {
2473 + .id = 0,
2474 + .name = "spiflash",
2475 + .resource = ar2315_spiflash_res,
2476 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2477 +};
2478 +
2479 +static struct platform_device ar2315_wdt = {
2480 + .id = 0,
2481 + .name = "ar2315_wdt",
2482 +};
2483 +
2484 +#define SPI_FLASH_CTL 0x00
2485 +#define SPI_FLASH_OPCODE 0x04
2486 +#define SPI_FLASH_DATA 0x08
2487 +
2488 +static inline u32
2489 +spiflash_read_reg(int reg)
2490 +{
2491 + return ar231x_read_reg(KSEG1ADDR(AR2315_SPI) + reg);
2492 +}
2493 +
2494 +static inline void
2495 +spiflash_write_reg(int reg, u32 data)
2496 +{
2497 + ar231x_write_reg(KSEG1ADDR(AR2315_SPI) + reg, data);
2498 +}
2499 +
2500 +static u32
2501 +spiflash_wait_status(void)
2502 +{
2503 + u32 reg;
2504 +
2505 + do {
2506 + reg = spiflash_read_reg(SPI_FLASH_CTL);
2507 + } while (reg & SPI_CTL_BUSY);
2508 +
2509 + return reg;
2510 +}
2511 +
2512 +static u8
2513 +spiflash_probe(void)
2514 +{
2515 + u32 reg;
2516 +
2517 + reg = spiflash_wait_status();
2518 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
2519 + reg |= (1 << 4) | 4 | SPI_CTL_START;
2520 +
2521 + spiflash_write_reg(SPI_FLASH_OPCODE, 0xab);
2522 + spiflash_write_reg(SPI_FLASH_CTL, reg);
2523 +
2524 + reg = spiflash_wait_status();
2525 + reg = spiflash_read_reg(SPI_FLASH_DATA);
2526 + reg &= 0xff;
2527 +
2528 + return (u8) reg;
2529 +}
2530 +
2531 +
2532 +#define STM_8MBIT_SIGNATURE 0x13
2533 +#define STM_16MBIT_SIGNATURE 0x14
2534 +#define STM_32MBIT_SIGNATURE 0x15
2535 +#define STM_64MBIT_SIGNATURE 0x16
2536 +#define STM_128MBIT_SIGNATURE 0x17
2537 +
2538 +static u8 __init *
2539 +ar2315_flash_limit(void)
2540 +{
2541 + u32 flash_size = 0;
2542 +
2543 + /* probe the flash chip size */
2544 + switch(spiflash_probe()) {
2545 + case STM_8MBIT_SIGNATURE:
2546 + flash_size = 0x00100000;
2547 + break;
2548 + case STM_16MBIT_SIGNATURE:
2549 + flash_size = 0x00200000;
2550 + break;
2551 + case STM_32MBIT_SIGNATURE:
2552 + flash_size = 0x00400000;
2553 + break;
2554 + case STM_64MBIT_SIGNATURE:
2555 + flash_size = 0x00800000;
2556 + break;
2557 + case STM_128MBIT_SIGNATURE:
2558 + flash_size = 0x01000000;
2559 + break;
2560 + }
2561 +
2562 + ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start +
2563 + flash_size - 1;
2564 + return (u8 *) ar2315_spiflash_res[0].end + 1;
2565 +}
2566 +
2567 +#ifdef CONFIG_LEDS_GPIO
2568 +static struct gpio_led ar2315_leds[6];
2569 +static struct gpio_led_platform_data ar2315_led_data = {
2570 + .leds = (void *) ar2315_leds,
2571 +};
2572 +
2573 +static struct platform_device ar2315_gpio_leds = {
2574 + .name = "leds-gpio",
2575 + .id = -1,
2576 + .dev = {
2577 + .platform_data = (void *) &ar2315_led_data,
2578 + }
2579 +};
2580 +
2581 +static void __init
2582 +ar2315_init_gpio(void)
2583 +{
2584 + static char led_names[6][6];
2585 + int i, led = 0;
2586 +
2587 + ar2315_led_data.num_leds = 0;
2588 + for(i = 1; i < 8; i++)
2589 + {
2590 + if((i == AR2315_RESET_GPIO) ||
2591 + (i == ar231x_board.config->resetConfigGpio))
2592 + continue;
2593 +
2594 + if(i == ar231x_board.config->sysLedGpio)
2595 + strcpy(led_names[led], "wlan");
2596 + else
2597 + sprintf(led_names[led], "gpio%d", i);
2598 +
2599 + ar2315_leds[led].name = led_names[led];
2600 + ar2315_leds[led].gpio = i;
2601 + ar2315_leds[led].active_low = 0;
2602 + led++;
2603 + }
2604 + ar2315_led_data.num_leds = led;
2605 + platform_device_register(&ar2315_gpio_leds);
2606 +}
2607 +#else
2608 +static inline void ar2315_init_gpio(void)
2609 +{
2610 +}
2611 +#endif
2612 +
2613 +int __init
2614 +ar2315_init_devices(void)
2615 +{
2616 + if (!IS_2315())
2617 + return 0;
2618 +
2619 + /* Find board configuration */
2620 + ar231x_find_config(ar2315_flash_limit());
2621 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2622 +
2623 + ar2315_init_gpio();
2624 + platform_device_register(&ar2315_wdt);
2625 + platform_device_register(&ar2315_spiflash);
2626 + ar231x_add_ethernet(0, AR2315_ENET0, AR2315_IRQ_ENET0_INTRS,
2627 + &ar2315_eth_data);
2628 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2629 +
2630 + return 0;
2631 +}
2632 +
2633 +static void
2634 +ar2315_restart(char *command)
2635 +{
2636 + void (*mips_reset_vec)(void) = (void *) 0xbfc00000;
2637 +
2638 + local_irq_disable();
2639 +
2640 + /* try reset the system via reset control */
2641 + ar231x_write_reg(AR2315_COLD_RESET,AR2317_RESET_SYSTEM);
2642 +
2643 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
2644 + * give it some time to attempt a gpio based hardware reset
2645 + * (atheros reference design workaround) */
2646 + gpio_direction_output(AR2315_RESET_GPIO, 0);
2647 + mdelay(100);
2648 +
2649 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2650 + * workaround. Attempt to jump to the mips reset location -
2651 + * the boot loader itself might be able to recover the system */
2652 + mips_reset_vec();
2653 +}
2654 +
2655 +
2656 +/*
2657 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2658 + * to determine the predevisor value.
2659 + */
2660 +static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = {
2661 + 1,
2662 + 2,
2663 + 4,
2664 + 5
2665 +};
2666 +
2667 +static int __initdata PLLC_DIVIDE_TABLE[5] = {
2668 + 2,
2669 + 3,
2670 + 4,
2671 + 6,
2672 + 3
2673 +};
2674 +
2675 +static unsigned int __init
2676 +ar2315_sys_clk(unsigned int clockCtl)
2677 +{
2678 + unsigned int pllcCtrl,cpuDiv;
2679 + unsigned int pllcOut,refdiv,fdiv,divby2;
2680 + unsigned int clkDiv;
2681 +
2682 + pllcCtrl = ar231x_read_reg(AR2315_PLLC_CTL);
2683 + refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2684 + refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv];
2685 + fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2686 + divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2687 + divby2 += 1;
2688 + pllcOut = (40000000/refdiv)*(2*divby2)*fdiv;
2689 +
2690 +
2691 + /* clkm input selected */
2692 + switch(clockCtl & CPUCLK_CLK_SEL_M) {
2693 + case 0:
2694 + case 1:
2695 + clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
2696 + break;
2697 + case 2:
2698 + clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
2699 + break;
2700 + default:
2701 + pllcOut = 40000000;
2702 + clkDiv = 1;
2703 + break;
2704 + }
2705 + cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2706 + cpuDiv = cpuDiv * 2 ?: 1;
2707 + return (pllcOut/(clkDiv * cpuDiv));
2708 +}
2709 +
2710 +static inline unsigned int
2711 +ar2315_cpu_frequency(void)
2712 +{
2713 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2714 +}
2715 +
2716 +static inline unsigned int
2717 +ar2315_apb_frequency(void)
2718 +{
2719 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2720 +}
2721 +
2722 +void __init
2723 +ar2315_time_init(void)
2724 +{
2725 + if (!IS_2315())
2726 + return;
2727 +
2728 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2729 +}
2730 +
2731 +void __init
2732 +ar2315_prom_init(void)
2733 +{
2734 + u32 memsize, memcfg, devid;
2735 +
2736 + if (!IS_2315())
2737 + return;
2738 +
2739 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2740 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2741 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2742 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2743 + memsize <<= 3;
2744 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2745 +
2746 + /* Detect the hardware based on the device ID */
2747 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2748 + switch(devid) {
2749 + case 0x90:
2750 + case 0x91:
2751 + ar231x_devtype = DEV_TYPE_AR2317;
2752 + break;
2753 + default:
2754 + ar231x_devtype = DEV_TYPE_AR2315;
2755 + break;
2756 + }
2757 + ar231x_gpiodev = &ar2315_gpiodev;
2758 + ar231x_board.devid = devid;
2759 +}
2760 +
2761 +void __init
2762 +ar2315_plat_setup(void)
2763 +{
2764 + u32 config;
2765 +
2766 + if (!IS_2315())
2767 + return;
2768 +
2769 + /* Clear any lingering AHB errors */
2770 + config = read_c0_config();
2771 + write_c0_config(config & ~0x3);
2772 + ar231x_write_reg(AR2315_AHB_ERR0,AHB_ERROR_DET);
2773 + ar231x_read_reg(AR2315_AHB_ERR1);
2774 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2775 +
2776 + _machine_restart = ar2315_restart;
2777 + ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency());
2778 +}
2779 --- /dev/null
2780 +++ b/arch/mips/ar231x/ar2315.h
2781 @@ -0,0 +1,37 @@
2782 +#ifndef __AR2315_H
2783 +#define __AR2315_H
2784 +
2785 +#ifdef CONFIG_ATHEROS_AR2315
2786 +
2787 +extern void ar2315_irq_init(void);
2788 +extern int ar2315_init_devices(void);
2789 +extern void ar2315_prom_init(void);
2790 +extern void ar2315_plat_setup(void);
2791 +extern void ar2315_time_init(void);
2792 +
2793 +#else
2794 +
2795 +static inline void ar2315_irq_init(void)
2796 +{
2797 +}
2798 +
2799 +static inline int ar2315_init_devices(void)
2800 +{
2801 + return 0;
2802 +}
2803 +
2804 +static inline void ar2315_prom_init(void)
2805 +{
2806 +}
2807 +
2808 +static inline void ar2315_plat_setup(void)
2809 +{
2810 +}
2811 +
2812 +static inline void ar2315_time_init(void)
2813 +{
2814 +}
2815 +
2816 +#endif
2817 +
2818 +#endif
2819 --- /dev/null
2820 +++ b/arch/mips/ar231x/ar5312.h
2821 @@ -0,0 +1,38 @@
2822 +#ifndef __AR5312_H
2823 +#define __AR5312_H
2824 +
2825 +#ifdef CONFIG_ATHEROS_AR5312
2826 +
2827 +extern void ar5312_irq_init(void);
2828 +extern int ar5312_init_devices(void);
2829 +extern void ar5312_prom_init(void);
2830 +extern void ar5312_plat_setup(void);
2831 +extern void ar5312_time_init(void);
2832 +extern void ar5312_time_init(void);
2833 +
2834 +#else
2835 +
2836 +static inline void ar5312_irq_init(void)
2837 +{
2838 +}
2839 +
2840 +static inline int ar5312_init_devices(void)
2841 +{
2842 + return 0;
2843 +}
2844 +
2845 +static inline void ar5312_prom_init(void)
2846 +{
2847 +}
2848 +
2849 +static inline void ar5312_plat_setup(void)
2850 +{
2851 +}
2852 +
2853 +static inline void ar5312_time_init(void)
2854 +{
2855 +}
2856 +
2857 +#endif
2858 +
2859 +#endif
2860 --- /dev/null
2861 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2862 @@ -0,0 +1,54 @@
2863 +#ifndef __AR531X_H
2864 +#define __AR531X_H
2865 +
2866 +#define AR531X_MISC_IRQ_BASE 0x20
2867 +#define AR531X_GPIO_IRQ_BASE 0x30
2868 +
2869 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2870 +#define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0
2871 +#define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */
2872 +
2873 +/* Miscellaneous interrupts, which share IP6 */
2874 +#define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0
2875 +#define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1
2876 +#define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2
2877 +#define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3
2878 +#define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4
2879 +#define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5
2880 +#define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6
2881 +#define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7
2882 +#define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8
2883 +#define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9
2884 +#define AR531X_MISC_IRQ_COUNT 10
2885 +
2886 +/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
2887 +#define AR531X_GPIO_IRQ_NONE AR531X_GPIO_IRQ_BASE+0
2888 +#define AR531X_GPIO_IRQ(n) AR531X_GPIO_IRQ_BASE+n
2889 +#define AR531X_GPIO_IRQ_COUNT 22
2890 +
2891 +static inline u32
2892 +ar231x_read_reg(u32 reg)
2893 +{
2894 + return __raw_readl((u32 *) KSEG1ADDR(reg));
2895 +}
2896 +
2897 +static inline void
2898 +ar231x_write_reg(u32 reg, u32 val)
2899 +{
2900 + __raw_writel(val, (u32 *) KSEG1ADDR(reg));
2901 +}
2902 +
2903 +static inline u32
2904 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2905 +{
2906 + u32 ret;
2907 +
2908 + ret = ar231x_read_reg(reg);
2909 + ret &= ~mask;
2910 + ret |= val;
2911 + ar231x_write_reg(reg, ret);
2912 +
2913 + return ret;
2914 +}
2915 +
2916 +#endif
2917 --- /dev/null
2918 +++ b/arch/mips/ar231x/devices.h
2919 @@ -0,0 +1,27 @@
2920 +#ifndef __AR231X_DEVICES_H
2921 +#define __AR231X_DEVICES_H
2922 +
2923 +enum {
2924 + /* handled by ar5312.c */
2925 + DEV_TYPE_AR2312,
2926 + DEV_TYPE_AR2313,
2927 + DEV_TYPE_AR5312,
2928 +
2929 + /* handled by ar2315.c */
2930 + DEV_TYPE_AR2315,
2931 + DEV_TYPE_AR2316,
2932 + DEV_TYPE_AR2317,
2933 +
2934 + DEV_TYPE_UNKNOWN
2935 +};
2936 +
2937 +extern int ar231x_devtype;
2938 +extern struct ar231x_board_config ar231x_board;
2939 +extern void (*ar231x_irq_dispatch)(void);
2940 +
2941 +extern int ar231x_find_config(u8 *flash_limit);
2942 +extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk);
2943 +extern int ar231x_add_wmac(int nr, u32 base, int irq);
2944 +extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata);
2945 +
2946 +#endif
2947 --- /dev/null
2948 +++ b/arch/mips/ar231x/devices.c
2949 @@ -0,0 +1,174 @@
2950 +#include <linux/kernel.h>
2951 +#include <linux/init.h>
2952 +#include <linux/serial.h>
2953 +#include <linux/serial_core.h>
2954 +#include <linux/serial_8250.h>
2955 +#include <linux/platform_device.h>
2956 +#include <ar231x_platform.h>
2957 +#include <ar231x.h>
2958 +#include "devices.h"
2959 +#include "ar5312.h"
2960 +#include "ar2315.h"
2961 +
2962 +struct ar231x_board_config ar231x_board;
2963 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
2964 +const struct ar231x_gpiodev *ar231x_gpiodev;
2965 +
2966 +static struct resource ar231x_eth0_res[] = {
2967 + {
2968 + .name = "eth0_membase",
2969 + .flags = IORESOURCE_MEM,
2970 + },
2971 + {
2972 + .name = "eth0_irq",
2973 + .flags = IORESOURCE_IRQ,
2974 + }
2975 +};
2976 +
2977 +static struct resource ar231x_eth1_res[] = {
2978 + {
2979 + .name = "eth1_membase",
2980 + .flags = IORESOURCE_MEM,
2981 + },
2982 + {
2983 + .name = "eth1_irq",
2984 + .flags = IORESOURCE_IRQ,
2985 + }
2986 +};
2987 +
2988 +static struct platform_device ar231x_eth[] = {
2989 + {
2990 + .id = 0,
2991 + .name = "ar231x-eth",
2992 + .resource = ar231x_eth0_res,
2993 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
2994 + },
2995 + {
2996 + .id = 1,
2997 + .name = "ar231x-eth",
2998 + .resource = ar231x_eth1_res,
2999 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
3000 + }
3001 +};
3002 +
3003 +static struct resource ar231x_wmac0_res[] = {
3004 + {
3005 + .name = "wmac0_membase",
3006 + .flags = IORESOURCE_MEM,
3007 + },
3008 + {
3009 + .name = "wmac0_irq",
3010 + .flags = IORESOURCE_IRQ,
3011 + }
3012 +};
3013 +
3014 +static struct resource ar231x_wmac1_res[] = {
3015 + {
3016 + .name = "wmac1_membase",
3017 + .flags = IORESOURCE_MEM,
3018 + },
3019 + {
3020 + .name = "wmac1_irq",
3021 + .flags = IORESOURCE_IRQ,
3022 + }
3023 +};
3024 +
3025 +
3026 +static struct platform_device ar231x_wmac[] = {
3027 + {
3028 + .id = 0,
3029 + .name = "ar231x-wmac",
3030 + .resource = ar231x_wmac0_res,
3031 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
3032 + .dev.platform_data = &ar231x_board,
3033 + },
3034 + {
3035 + .id = 1,
3036 + .name = "ar231x-wmac",
3037 + .resource = ar231x_wmac1_res,
3038 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
3039 + .dev.platform_data = &ar231x_board,
3040 + },
3041 +};
3042 +
3043 +static const char *devtype_strings[] = {
3044 + [DEV_TYPE_AR5312] = "Atheros AR5312",
3045 + [DEV_TYPE_AR2312] = "Atheros AR2312",
3046 + [DEV_TYPE_AR2313] = "Atheros AR2313",
3047 + [DEV_TYPE_AR2315] = "Atheros AR2315",
3048 + [DEV_TYPE_AR2316] = "Atheros AR2316",
3049 + [DEV_TYPE_AR2317] = "Atheros AR2317",
3050 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
3051 +};
3052 +
3053 +const char *get_system_type(void)
3054 +{
3055 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
3056 + !devtype_strings[ar231x_devtype])
3057 + return devtype_strings[DEV_TYPE_UNKNOWN];
3058 + return devtype_strings[ar231x_devtype];
3059 +}
3060 +
3061 +
3062 +int __init
3063 +ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata)
3064 +{
3065 + struct resource *res;
3066 +
3067 + ar231x_eth[nr].dev.platform_data = pdata;
3068 + res = &ar231x_eth[nr].resource[0];
3069 + res->start = base;
3070 + res->end = base + 0x2000 - 1;
3071 + res++;
3072 + res->start = irq;
3073 + res->end = irq;
3074 + return platform_device_register(&ar231x_eth[nr]);
3075 +}
3076 +
3077 +void __init
3078 +ar231x_serial_setup(u32 mapbase, unsigned int uartclk)
3079 +{
3080 + struct uart_port s;
3081 +
3082 + memset(&s, 0, sizeof(s));
3083 +
3084 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
3085 + s.iotype = UPIO_MEM;
3086 + s.irq = AR531X_MISC_IRQ_UART0;
3087 + s.regshift = 2;
3088 + s.mapbase = mapbase;
3089 + s.uartclk = uartclk;
3090 + s.membase = (void __iomem *)s.mapbase;
3091 +
3092 + early_serial_setup(&s);
3093 +}
3094 +
3095 +int __init
3096 +ar231x_add_wmac(int nr, u32 base, int irq)
3097 +{
3098 + struct resource *res;
3099 +
3100 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
3101 + res = &ar231x_wmac[nr].resource[0];
3102 + res->start = base;
3103 + res->end = base + 0x10000 - 1;
3104 + res++;
3105 + res->start = irq;
3106 + res->end = irq;
3107 + return platform_device_register(&ar231x_wmac[nr]);
3108 +}
3109 +
3110 +static int __init ar231x_register_devices(void)
3111 +{
3112 + static struct resource res = {
3113 + .start = 0xFFFFFFFF,
3114 + };
3115 +
3116 + platform_device_register_simple("GPIODEV", 0, &res, 1);
3117 + ar5312_init_devices();
3118 + ar2315_init_devices();
3119 +
3120 + return 0;
3121 +}
3122 +
3123 +device_initcall(ar231x_register_devices);
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