target/linux/adm8668/files/arch/mips/include/asm/mach-adm8668/adm8668.h

   1 /************************************************************************
   2  *
   3  *    Copyright (c) 2005
   4  *    Infineon Technologies AG
   5  *    St. Martin Strasse 53; 81669 Muenchen; Germany
   6  *
   7  ************************************************************************/
   8
   9 #ifndef  __ADM8668_H__
  10 #define  __ADM8668_H__
  11
  12 #include <asm/addrspace.h>
  13 #include "bsp_sup.h"
  14
  15 #define MEM_KSEG0_BASE          0x80000000
  16 #define MEM_KSEG1_BASE          0xA0000000
  17 #define MEM_SEG_MASK            0xE0000000
  18 #define KVA2PA(_addr)           ((unsigned long)(_addr) & ~MEM_SEG_MASK)
  19
  20 #define MIPS_KSEG0A(_addr)      (KVA2PA(_addr) | MEM_KSEG0_BASE)
  21 #define MIPS_KSEG1A(_addr)      (KVA2PA(_addr) | MEM_KSEG1_BASE)
  22
  23 #define PA2VA(_addr)            (KVA2PA(_addr) | MEM_KSEG1_BASE)
  24 #define PA2CACHEVA(_addr)       (KVA2PA(_addr) | MEM_KSEG0_BASE)
  25
  26
  27 /*=======================  Physical Memory Map  ============================*/
  28 #define ADM8668_SDRAM_BASE      0
  29 #define ADM8668_SMEM1_BASE      0x10000000
  30 #define ADM8668_MPMC_BASE       0x11000000
  31 #define ADM8668_USB_BASE        0x11200000
  32 #define ADM8668_CONFIG_BASE     0x11400000
  33 #define ADM8668_WAN_BASE        0x11600000
  34 #define ADM8668_WLAN_BASE       0x11800000
  35 #define ADM8668_LAN_BASE        0x11A00000
  36 #define ADM8668_INTC_BASE       0x1E000000
  37 #define ADM8668_TMR_BASE        0x1E200000
  38 #define ADM8668_UART0_BASE      0x1E400000
  39 #define ADM8668_SMEM0_BASE      0x1FC00000
  40 #define ADM8668_NAND_BASE       0x1fffff00
  41
  42 #define PCICFG_BASE             0x12200000
  43 #define PCIDAT_BASE             0x12400000
  44
  45 /* for PCI bridge fixup ! */
  46 #define PCI_BRIDGE_MASK         0x40
  47
  48 /* WLAN registers */
  49 #define WCSR0                   0x00
  50 #define WCSR11A                 0x5c
  51
  52 #define GPIO_REG                WCSR11A
  53
  54 #define ADM8668_WLAN_REG(_reg)          \
  55         (*((volatile unsigned int *)(PA2VA(ADM8668_WLAN_BASE + (_reg)))))
  56
  57 /* configuration registers */
  58 #define ADM8668_CR0             0x00
  59 #define ADM8668_CR1             0x04
  60 #define ADM8668_CR2             0x08
  61 #define ADM8668_CR3             0x0C
  62 #define ADM8668_CR8             0x20
  63 #define ADM8668_CR10            0x28
  64 #define ADM8668_CR11            0x2C
  65 #define ADM8668_CR12            0x30
  66 #define ADM8668_CR13            0x34
  67 #define ADM8668_CR14            0x38
  68 #define ADM8668_CR15            0x3C
  69 #define ADM8668_CR16            0x40
  70 #define ADM8668_CR17            0x44
  71 #define ADM8668_CR18            0x48
  72 #define ADM8668_CR19            0x4C
  73 #define ADM8668_CR20            0x50
  74 #define ADM8668_CR21            0x54
  75 #define ADM8668_CR22            0x58
  76 #define ADM8668_CR23            0x5C
  77 #define ADM8668_CR24            0x60
  78 #define ADM8668_CR25            0x64
  79 #define ADM8668_CR26            0x68
  80 #define ADM8668_CR27            0x6C
  81 #define ADM8668_CR28            0x70
  82 #define ADM8668_CR29            0x74
  83 #define ADM8668_CR30            0x78
  84 #define ADM8668_CR31            0x7C
  85 #define ADM8668_CR32            0x80
  86 #define ADM8668_CR33            0x84
  87 #define ADM8668_CR34            0x88
  88 #define ADM8668_CR35            0x8C
  89 #define ADM8668_CR36            0x90
  90 #define ADM8668_CR37            0x94
  91 #define ADM8668_CR38            0x98
  92 #define ADM8668_CR39            0x9C
  93 #define ADM8668_CR40            0xA0
  94 #define ADM8668_CR41            0xA4
  95 #define ADM8668_CR42            0xA8
  96 #define ADM8668_CR43            0xAC
  97 #define ADM8668_CR44            0xB0
  98 #define ADM8668_CR45            0xB4
  99 #define ADM8668_CR46            0xB8
 100 #define ADM8668_CR47            0xBC
 101 #define ADM8668_CR48            0xC0
 102 #define ADM8668_CR49            0xC4
 103 #define ADM8668_CR50            0xC8
 104 #define ADM8668_CR51            0xCC
 105 #define ADM8668_CR52            0xD0
 106 #define ADM8668_CR53            0xD4
 107 #define ADM8668_CR54            0xD8
 108 #define ADM8668_CR55            0xDC
 109 #define ADM8668_CR56            0xE0
 110 #define ADM8668_CR57            0xE4
 111 #define ADM8668_CR58            0xE8
 112 #define ADM8668_CR59            0xEC
 113 #define ADM8668_CR60            0xF0
 114 #define ADM8668_CR61            0xF4
 115 #define ADM8668_CR62            0xF8
 116 #define ADM8668_CR63            0xFC
 117 #define ADM8668_CR64            0x100
 118 #define ADM8668_CR65            0x104
 119 #define ADM8668_CR66            0x108
 120 #define ADM8668_CR67            0x10C
 121 #define ADM8668_CR68            0x110
 122
 123 #define CRGPIO_REG              ADM8668_CR8
 124
 125 #define ADM8668_CONFIG_REG(_reg)                \
 126         (*((volatile unsigned int *)(PA2VA(ADM8668_CONFIG_BASE + (_reg)))))
 127 #define ADM8668_MPMC_REG(_reg)          \
 128         (*((volatile unsigned int *)(PA2VA(ADM8668_MPMC_BASE + (_reg)))))
 129
 130
 131 /*==========================  Interrupt Controller ==========================*/
 132 /* registers offset */
 133 #define IRQ_STATUS_REG          0x00    /* Read */
 134 #define IRQ_RAW_STATUS_REG      0x04    /* Read */
 135 #define IRQ_ENABLE_REG          0x08    /* Read/Write */
 136 #define IRQ_DISABLE_REG         0x0C    /* Write */
 137 #define IRQ_SOFT_REG            0x10    /* Write */
 138
 139 #define FIQ_STATUS_REG          0x100   /* Read */
 140 #define FIQ_RAW_STATUS_REG      0x104
 141 #define FIQ_ENABLE_REG          0x108
 142 #define FIQ_DISABLE_REG         0x10c
 143
 144
 145 /*  Macro for accessing Interrupt controller register  */
 146 #define ADM8668_INTC_REG(_reg)          \
 147         (*((volatile unsigned long *)(PA2VA(ADM8668_INTC_BASE + (_reg)))))
 148
 149
 150 /* interrupt levels */
 151 #define INT_LVL_SWI             1
 152 #define INT_LVL_COMMS_RX        2
 153 #define INT_LVL_COMMS_TX        3
 154 #define INT_LVL_TIMERINT0       4
 155 #define INT_LVL_TIMERINT1       5
 156 #define INT_LVL_UART0           6
 157 #define INT_LVL_LAN             7
 158 #define INT_LVL_WAN             8
 159 #define INT_LVL_WLAN            9
 160 #define INT_LVL_GPIO            10
 161 #define INT_LVL_IDE             11
 162 #define INT_LVL_PCI2            12
 163 #define INT_LVL_PCI1            13
 164 #define INT_LVL_PCI0            14
 165 #define INT_LVL_USB             15
 166 #define INT_LVL_MAX             INT_LVL_USB
 167
 168 #define IRQ_MASK                0xffff
 169
 170 #define IRQ_SWI                 (0x1<<INT_LVL_SWI)
 171 #define IRQ_TIMERINT0           (0x1<<INT_LVL_TIMERINT0)
 172 #define IRQ_TIMERINT1           (0x1<<INT_LVL_TIMERINT1)
 173 #define IRQ_UART0               (0x1<<INT_LVL_UART0)
 174 #define IRQ_LAN                 (0x1<<INT_LVL_LAN)
 175 #define IRQ_WAN                 (0x1<<INT_LVL_WAN)
 176 #define IRQ_WLAN                (0x1<<INT_LVL_WLAN)
 177 #define IRQ_GPIO                (0x1<<INT_LVL_GPIO)
 178 #define IRQ_IDEINT              (0x1<<INT_LVL_IDE)
 179 #define IRQ_PCI2                (0x1<<INT_LVL_PCI2)
 180 #define IRQ_PCI1                (0x1<<INT_LVL_PCI1)
 181 #define IRQ_PCI0                (0x1<<INT_LVL_PCI0)
 182 #define IRQ_USB                 (0x1<<INT_LVL_USB)
 183
 184
 185 /*===========================  UART Control Register ========================*/
 186 #define UART_DR_REG             0x00
 187 #define UART_RSR_REG            0x04
 188 #define UART_ECR_REG            0x04
 189 #define UART_LCR_H_REG          0x08
 190 #define UART_LCR_M_REG          0x0c
 191 #define UART_LCR_L_REG          0x10
 192 #define UART_CR_REG             0x14
 193 #define UART_FR_REG             0x18
 194 #define UART_IIR_REG            0x1c
 195 #define UART_ICR_REG            0x1C
 196 #define UART_ILPR_REG           0x20
 197
 198 /*  rsr/ecr reg  */
 199 #define UART_OVERRUN_ERR        0x08
 200 #define UART_BREAK_ERR          0x04
 201 #define UART_PARITY_ERR         0x02
 202 #define UART_FRAMING_ERR        0x01
 203 #define UART_RX_STATUS_MASK     0x0f
 204 #define UART_RX_ERROR           ( UART_BREAK_ERR        \
 205                                 | UART_PARITY_ERR       \
 206                                 | UART_FRAMING_ERR)
 207
 208 /*  lcr_h reg  */
 209 #define UART_SEND_BREAK         0x01
 210 #define UART_PARITY_EN          0x02
 211 #define UART_EVEN_PARITY        0x04
 212 #define UART_TWO_STOP_BITS      0x08
 213 #define UART_ENABLE_FIFO        0x10
 214
 215 #define UART_WLEN_5BITS         0x00
 216 #define UART_WLEN_6BITS         0x20
 217 #define UART_WLEN_7BITS         0x40
 218 #define UART_WLEN_8BITS         0x60
 219 #define UART_WLEN_MASK          0x60
 220
 221 /*  cr reg  */
 222 #define UART_PORT_EN                    0x01
 223 #define UART_SIREN                      0x02
 224 #define UART_SIRLP                      0x04
 225 #define UART_MODEM_STATUS_INT_EN        0x08
 226 #define UART_RX_INT_EN                  0x10
 227 #define UART_TX_INT_EN                  0x20
 228 #define UART_RX_TIMEOUT_INT_EN          0x40
 229 #define UART_LOOPBACK_EN                0x80
 230
 231 /*  fr reg  */
 232 #define UART_CTS                0x01
 233 #define UART_DSR                0x02
 234 #define UART_DCD                0x04
 235 #define UART_BUSY               0x08
 236 #define UART_RX_FIFO_EMPTY      0x10
 237 #define UART_TX_FIFO_FULL       0x20
 238 #define UART_RX_FIFO_FULL       0x40
 239 #define UART_TX_FIFO_EMPTY      0x80
 240
 241 /*  iir/icr reg  */
 242 #define UART_MODEM_STATUS_INT   0x01
 243 #define UART_RX_INT             0x02
 244 #define UART_TX_INT             0x04
 245 #define UART_RX_TIMEOUT_INT     0x08
 246
 247 #define UART_INT_MASK           0x0f
 248
 249 #ifdef _FPGA_
 250 #define ADM8668_UARTCLK_FREQ    3686400
 251 #else
 252 #define ADM8668_UARTCLK_FREQ    62500000
 253 #endif
 254
 255 #define UART_BAUDDIV(_rate)                             \
 256         ((unsigned long)(ADM8668_UARTCLK_FREQ/(16*(_rate)) - 1))
 257
 258 /*  uart_baudrate  */
 259 #define UART_230400bps_DIVISOR  UART_BAUDDIV(230400)
 260 #define UART_115200bps_DIVISOR  UART_BAUDDIV(115200)
 261 #define UART_76800bps_DIVISOR   UART_BAUDDIV(76800)
 262 #define UART_57600bps_DIVISOR   UART_BAUDDIV(57600)
 263 #define UART_38400bps_DIVISOR   UART_BAUDDIV(38400)
 264 #define UART_19200bps_DIVISOR   UART_BAUDDIV(19200)
 265 #define UART_14400bps_DIVISOR   UART_BAUDDIV(14400)
 266 #define UART_9600bps_DIVISOR    UART_BAUDDIV(9600)
 267 #define UART_2400bps_DIVISOR    UART_BAUDDIV(2400)
 268 #define UART_1200bps_DIVISOR    UART_BAUDDIV(1200)
 269
 270
 271 /*===========================  Counter Timer ==============================*/
 272 #define TIMER0_REG_BASE         ADM8668_TMR_BASE
 273 #define TIMER1_REG_BASE         ADM8668_TMR_BASE+0x20
 274
 275 #define TIMER_LOAD_REG          0x00
 276 #define TIMER_VALUE_REG         0x04
 277 #define TIMER_CTRL_REG          0x08
 278 #define TIMER_CLR_REG           0x0c
 279
 280 /* TIMER_LOAD_REG */
 281 #ifdef _FPGA_
 282 #define SYS_CLOCK               56000000
 283 #else
 284 #define SYS_CLOCK               175000000
 285 #endif
 286
 287 #define SYS_PRESCALE            256
 288
 289 #define TMR_10MS_TICKS          (SYS_CLOCK/SYS_PRESCALE/100)
 290
 291 /* TIMER_CTRL_REG */
 292 #define TMR_PRESCALE_1          0x00
 293 #define TMR_PRESCALE_16         0x04
 294 #define TMR_PRESCALE_256        0x08
 295 #define TMR_MODE_PERIODIC       0x40
 296 #define TMR_ENABLE              0x80
 297
 298 /* TIMER_CLR_REG */
 299 #define TMR_CLEAR_BIT           1
 300
 301
 302 /* Macro for access MPMC register */
 303 #define ADM8668_TMR_REG(base, _offset)                          \
 304                 (*((volatile unsigned long *)(PA2VA(base + (_offset)))))
 305
 306
 307 /* For GPIO control */
 308 #define GPIO0_OUTPUT_ENABLE     0x1000
 309 #define GPIO1_OUTPUT_ENABLE     0x2000
 310 #define GPIO2_OUTPUT_ENABLE     0x4000
 311 #define GPIO_OUTPUT_ENABLE_ALL  0x7000
 312 #define GPIO0_OUTPUT_1          0x40
 313 #define GPIO1_OUTPUT_1          0x80
 314 #define GPIO2_OUTPUT_1          0x100
 315 #define GPIO0_INPUT_1           0x1
 316 #define GPIO1_INPUT_1           0x2
 317 #define GPIO2_INPUT_1           0x4
 318
 319 #define GPIO_SET_HI(num)        \
 320         ADM8668_WLAN_REG(GPIO_REG) |= (1 << (6 + num))
 321
 322 #define GPIO_SET_LOW(num)       \
 323         ADM8668_WLAN_REG(GPIO_REG) &= ~(1 << (6 + num))
 324
 325 #define GPIO_TOGGLE(num)        \
 326         ADM8668_WLAN_REG(GPIO_REG) ^= (1 << (6 + num))
 327
 328 #define CRGPIO_SET_HI(num)      \
 329         ADM8668_CONFIG_REG(CRGPIO_REG) |= (1 << (6 + num))
 330
 331 #define CRGPIO_SET_LOW(num)     \
 332         ADM8668_CONFIG_REG(CRGPIO_REG) &= ~(1 << (6 + num))
 333
 334 #define CRGPIO_TOGGLE(num)      \
 335         ADM8668_CONFIG_REG(CRGPIO_REG) ^= (1 << (6 + num))
 336
 337
 338 /*==========================================================================*/
 339 /* Cache Controller */
 340 #define ADM8668_CACHE_LINE_SIZE         16
 341
 342 #define BIT_0                   0x00000001
 343 #define BIT_1                   0x00000002
 344 #define BIT_2                   0x00000004
 345 #define BIT_3                   0x00000008
 346 #define BIT_4                   0x00000010
 347 #define BIT_5                   0x00000020
 348 #define BIT_6                   0x00000040
 349 #define BIT_7                   0x00000080
 350 #define BIT_8                   0x00000100
 351 #define BIT_9                   0x00000200
 352 #define BIT_10                  0x00000400
 353 #define BIT_11                  0x00000800
 354 #define BIT_12                  0x00001000
 355 #define BIT_13                  0x00002000
 356 #define BIT_14                  0x00004000
 357 #define BIT_15                  0x00008000
 358 #define BIT_16                  0x00010000
 359 #define BIT_17                  0x00020000
 360 #define BIT_18                  0x00040000
 361 #define BIT_19                  0x00080000
 362 #define BIT_20                  0x00100000
 363 #define BIT_21                  0x00200000
 364 #define BIT_22                  0x00400000
 365 #define BIT_23                  0x00800000
 366 #define BIT_24                  0x01000000
 367 #define BIT_25                  0x02000000
 368 #define BIT_26                  0x04000000
 369 #define BIT_27                  0x08000000
 370 #define BIT_28                  0x10000000
 371 #define BIT_29                  0x20000000
 372 #define BIT_30                  0x40000000
 373 #define BIT_31                  0x80000000
 374
 375 /* network regs */
 376 #define NETCSR0                 0x0
 377 #define NETCSR1                 0x08
 378 #define NETCSR2                 0x10
 379 #define NETCSR3                 0x18
 380 #define NETCSR4                 0x20
 381 #define NETCSR5                 0x28
 382 #define NETCSR6                 0x30
 383 #define NETCSR7                 0x38
 384 #define NETCSR8                 0x40
 385 #define NETCSR9                 0x48
 386 #define NETCSR10                0x50
 387 #define NETCSR11                0x58
 388 #define NETCSR12                0x60
 389 #define NETCSR13                0x68
 390 #define NETCSR14                0x70
 391 #define NETCSR15                0x78
 392 #define NETCSR36                0xD0
 393 #define NETCSR36A               0xD4
 394 #define NETCSR36B               0xD8
 395 #define NETCSR36C               0xDC    // dummy
 396 #define NETCSR36D               0xE0
 397 #define NETCSR36E               0xE4
 398 #define NETCSR36F               0xE8
 399 #define NETCSR36G               0xEC
 400 #define NETCSR36H               0xF0
 401 #define NETCSR36I               0xF4
 402 #define NETCSR37                0xF8
 403
 404 /* for descriptor skip DWs */
 405 #define NETDESCSKIP_1DW         BIT_2
 406 #define NETDESCSKIP_2DW         BIT_3
 407 #define NETDESCSKIP_3DW         (BIT_3|BIT_2)
 408 #define NETDESCSKIP_4DW         BIT_4
 409
 410
 411 #define ADM8668_LAN_REG(_reg)           \
 412         (*((volatile unsigned int *)(PA2VA(ADM8668_LAN_BASE + (_reg)))))
 413 #define ADM8668_WAN_REG(_reg)           \
 414         (*((volatile unsigned int *)(PA2VA(ADM8668_WAN_BASE + (_reg)))))
 415
 416 #endif /* __ADM8668_H__ */