target/linux/brcm47xx/patches-2.6.28/130-remove_scache.patch

   1 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
   2 --- a/arch/mips/Kconfig
   3 +++ b/arch/mips/Kconfig
   4 @@ -198,7 +198,6 @@ config MIPS_MALTA
   5         select I8259
   6         select MIPS_BOARDS_GEN
   7         select MIPS_BONITO64
   8 -       select MIPS_CPU_SCACHE
   9         select PCI_GT64XXX_PCI0
  10         select MIPS_MSC
  11         select SWAP_IO_SPACE
  12 @@ -1383,13 +1382,6 @@ config IP22_CPU_SCACHE
  13         bool
  14         select BOARD_SCACHE
  15
  16 -#
  17 -# Support for a MIPS32 / MIPS64 style S-caches
  18 -#
  19 -config MIPS_CPU_SCACHE
  20 -       bool
  21 -       select BOARD_SCACHE
  22 -
  23  config R5000_CPU_SCACHE
  24         bool
  25         select BOARD_SCACHE
  26 diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
  27 --- a/arch/mips/kernel/cpu-probe.c
  28 +++ b/arch/mips/kernel/cpu-probe.c
  29 @@ -755,6 +755,8 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
  30         case PRID_IMP_25KF:
  31                 c->cputype = CPU_25KF;
  32                 __cpu_name[cpu] = "MIPS 25Kc";
  33 +               /* Probe for L2 cache */
  34 +               c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
  35                 break;
  36         case PRID_IMP_34K:
  37                 c->cputype = CPU_34K;
  38 diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
  39 --- a/arch/mips/mm/Makefile
  40 +++ b/arch/mips/mm/Makefile
  41 @@ -31,6 +31,5 @@ obj-$(CONFIG_CPU_VR41XX)      += c-r4k.o cex-gen.o tlb-r4k.o
  42  obj-$(CONFIG_IP22_CPU_SCACHE)  += sc-ip22.o
  43  obj-$(CONFIG_R5000_CPU_SCACHE)  += sc-r5k.o
  44  obj-$(CONFIG_RM7000_CPU_SCACHE)        += sc-rm7k.o
  45 -obj-$(CONFIG_MIPS_CPU_SCACHE)  += sc-mips.o
  46
  47  EXTRA_CFLAGS += -Werror
  48 diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
  49 --- a/arch/mips/mm/c-r4k.c
  50 +++ b/arch/mips/mm/c-r4k.c
  51 @@ -1121,7 +1121,6 @@ static void __init loongson2_sc_init(void)
  52
  53  extern int r5k_sc_init(void);
  54  extern int rm7k_sc_init(void);
  55 -extern int mips_sc_init(void);
  56
  57  static void __cpuinit setup_scache(void)
  58  {
  59 @@ -1175,29 +1174,17 @@ static void __cpuinit setup_scache(void)
  60  #endif
  61
  62         default:
  63 -               if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
  64 -                   c->isa_level == MIPS_CPU_ISA_M32R2 ||
  65 -                   c->isa_level == MIPS_CPU_ISA_M64R1 ||
  66 -                   c->isa_level == MIPS_CPU_ISA_M64R2) {
  67 -#ifdef CONFIG_MIPS_CPU_SCACHE
  68 -                       if (mips_sc_init ()) {
  69 -                               scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
  70 -                               printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
  71 -                                      scache_size >> 10,
  72 -                                      way_string[c->scache.ways], c->scache.linesz);
  73 -                       }
  74 -#else
  75 -                       if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
  76 -                               panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
  77 -#endif
  78 -                       return;
  79 -               }
  80                 sc_present = 0;
  81         }
  82
  83         if (!sc_present)
  84                 return;
  85
  86 +       if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
  87 +            c->isa_level == MIPS_CPU_ISA_M64R1) &&
  88 +           !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
  89 +               panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
  90 +
  91         /* compute a couple of other cache variables */
  92         c->scache.waysize = scache_size / c->scache.ways;
  93