2 +++ b/arch/powerpc/boot/dts/rb333.dts
6 + * RouterBOARD 333 series Device Tree Source
8 + * Copyright 2010 Alexandros C. Couloumbis <alex@ozo.com>
9 + * Copyright 2009 Michael Guntsche <mike@it-loops.com>
11 + * This program is free software; you can redistribute it and/or modify it
12 + * under the terms of the GNU General Public License as published by the
13 + * Free Software Foundation; either version 2 of the License, or (at your
14 + * option) any later version.
16 + * Warning (reg_format): "reg" property in /qe@e0100000/muram@10000/data-only@0 has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1)
17 + * Warning (ranges_format): "ranges" property in /qe@e0100000/muram@10000 has invalid length (12 bytes) (parent #address-cells == 1, child #address-cells == 2, #size-cells == 1)
18 + * Warning (avoid_default_addr_size): Relying on default #address-cells value for /qe@e0100000/muram@10000/data-only@0
19 + * Warning (avoid_default_addr_size): Relying on default #size-cells value for /qe@e0100000/muram@10000/data-only@0
20 + * Warning (obsolete_chosen_interrupt_controller): /chosen has obsolete "interrupt-controller" property
29 + compatible = "MPC83xx";
31 + #address-cells = <1>;
43 + bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1";
44 + // linux,platform = <0x8062>;
45 + // linux,initrd = <0x488000 0x0>;
46 + linux,stdout-path = "/soc8323@e0000000/serial@4500";
47 + // interrupt-controller = <&ipic>;
53 + #address-cells = <1>;
56 + device_type = "cpu";
58 + i-cache-size = <0x4000>;
59 + d-cache-size = <0x4000>;
60 + i-cache-line-size = <0x20>;
61 + d-cache-line-size = <0x20>;
62 + // clock-frequency = <0x13de3650>;
63 + // timebase-frequency = <0x1fc9f08>;
64 + timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob
65 + clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob
71 + device_type = "memory";
72 + reg = <0x0 0x4000000>;
73 + // reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob
77 + reg = <0xfe000000 0x20000>;
85 + reg = <0xf8000000 0x1000>;
86 + device_type = "rb,nand";
90 + reg = <0xf0000000 0x1000>;
94 + voltage_gpio = <&gpio3 0x11>;
98 + interrupt-parent = <&ipic>;
99 + interrupts = <0x14 0x8>;
100 + fan_on = <&gpio0 0x10>;
103 + pci0: pci@e0008500 {
104 + device_type = "pci";
105 + // compatible = "83xx";
106 + compatible = "fsl,mpc8349-pci";
107 + reg = <0xe0008500 0x100 0xe0008300 0x8>;
108 + #address-cells = <3>;
110 + #interrupt-cells = <1>;
111 + // clock-frequency = <0>;
112 + ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>;
113 + bus-range = <0x0 0x0>;
115 + /* IDSEL 0x10 AD16 miniPCI slot 0 */
116 + 0x8000 0x0 0x0 0x1 &ipic 0x11 0x8
117 + 0x8000 0x0 0x0 0x2 &ipic 0x12 0x8
119 + /* IDSEL 0x11 AD17 miniPCI slot 1 */
120 + 0x8800 0x0 0x0 0x1 &ipic 0x12 0x8
121 + 0x8800 0x0 0x0 0x2 &ipic 0x13 0x8
123 + /* IDSEL 0x12 AD18 miniPCI slot 2 */
124 + 0x9000 0x0 0x0 0x1 &ipic 0x13 0x8
125 + 0x9000 0x0 0x0 0x2 &ipic 0x11 0x8>;
127 + interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
128 + interrupt-parent = <&ipic>;
129 + // interrupts = <66 0x8>;
134 + reg = <0xe0100000 0x480>;
135 + ranges = <0x0 0xe0100000 0x100000>;
137 + device_type = "qe";
138 + compatible = "fsl,qe";
140 + #address-cells = <1>;
141 + brg-frequency = <0>;
142 + bus-frequency = <0>;
143 + // bus-frequency = <198000000>;
144 + fsl,qe-num-riscs = <1>;
145 + fsl,qe-num-snums = <28>;
148 + interrupt-controller;
149 + compatible = "fsl,qe-ic";
153 + #interrupt-cells = <1>;
154 + #address-cells = <0>;
155 + device_type = "qeic";
156 + interrupts = <0x20 0x8 0x21 0x8>;
157 + interrupt-parent = <&ipic>;
161 + compatible = "ucc_geth_phy";
162 + device_type = "mdio";
163 + reg = <0x3120 0x18>;
165 + #address-cells = <1>;
167 + phy3: ethernet-phy@03 {
168 + // interface = <0x3>;
169 + device_type = "ethernet-phy";
173 + phy2: ethernet-phy@02 {
174 + // interface = <0x3>;
175 + device_type = "ethernet-phy";
179 + phy1: ethernet-phy@01 {
180 + // interface = <0x3>;
181 + device_type = "ethernet-phy";
189 + mac-address = [00 0c 42 1c 29 d2];
190 + interrupt-parent = <&qeic>;
191 + interrupts = <0x22>;
192 + reg = <0x2200 0x200>;
195 + compatible = "ucc_geth";
196 + device_type = "network";
197 + phy-handle = <&phy2>;
198 + pio-handle = <&pio3>;
204 + mac-address = [00 0c 42 1c 29 d1];
205 + interrupt-parent = <&qeic>;
206 + interrupts = <0x23>;
207 + reg = <0x3200 0x200>;
210 + compatible = "ucc_geth";
211 + device_type = "network";
212 + phy-handle = <&phy3>;
213 + pio-handle = <&pio4>;
219 + mac-address = [00 0c 42 1c 29 d0];
220 + interrupt-parent = <&qeic>;
221 + interrupts = <0x21>;
222 + reg = <0x3000 0x200>;
225 + compatible = "ucc_geth";
226 + device_type = "network";
227 + phy-handle = <&phy1>;
228 + pio-handle = <&pio2>;
233 + interrupt-parent = <&qeic>;
234 + interrupts = <0x1>;
235 + reg = <0x500 0x40>;
236 + compatible = "fsl,spi";
237 + device_type = "spi";
242 + interrupt-parent = <&qeic>;
243 + interrupts = <0x2>;
244 + reg = <0x4c0 0x40>;
245 + compatible = "fsl,spi";
246 + device_type = "spi";
250 + #address-cells = <1>;
252 + compatible = "fsl,qe-muram", "fsl,cpm-muram";
253 + ranges = <0x0 0x10000 0x4000>;
254 + device_type = "muram";
257 + compatible = "fsl,qe-muram-data",
258 + "fsl,cpm-muram-data";
259 + reg = <0x0 0x4000>;
266 + bus-frequency = <0x1>;
267 + reg = <0xe0000000 0x200>;
268 + ranges = <0x0 0xe0000000 0x100000>;
269 + device_type = "soc";
270 + compatible = "simple-bus";
271 + #interrupt-cells = <0x2>;
273 + #address-cells = <1>;
276 + gpio = <&gpio3 0x12>;
277 + reg = <0x500 0x100>;
278 + interrupt-parent = <&ipic>;
279 + interrupts = <0x48 0x8>;
283 + reg = <0x144c 0x4>;
285 + compatible = "qe_gpio";
286 + device_type = "gpio";
290 + reg = <0x1434 0x4>;
292 + compatible = "qe_gpio";
293 + device_type = "gpio";
297 + reg = <0x1404 0x4>;
299 + compatible = "qe_gpio";
300 + device_type = "gpio";
305 + device_type = "par_io";
306 + reg = <0x1400 0x100>;
310 + /* port pin dir open_drain assignment has_irq */
330 + /* port pin dir open_drain assignment has_irq */
350 + /* port pin dir open_drain assignment has_irq */
372 + device_type = "ipic";
374 + reg = <0x700 0x100>;
375 + #interrupt-cells = <0x2>;
376 + #address-cells = <0x0>;
377 + interrupt-controller;
382 + interrupt-parent = <&ipic>;
383 + interrupts = <0x9 0x8>;
384 + clock-frequency = <0x7f27c20>;
385 + reg = <0x4500 0x100>;
386 + compatible = "ns16550";
387 + device_type = "serial";
391 + #address-cells = <1>;
393 + compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
395 + ranges = <0 0x8100 0x1a8>;
396 + interrupt-parent = <&ipic>;
397 + interrupts = <71 8>;
400 + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
403 + interrupt-parent = <&ipic>;
404 + interrupts = <71 8>;
407 + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
410 + interrupt-parent = <&ipic>;
411 + interrupts = <71 8>;
414 + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
415 + reg = <0x100 0x80>;
417 + interrupt-parent = <&ipic>;
418 + interrupts = <71 8>;
421 + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
422 + reg = <0x180 0x28>;
424 + interrupt-parent = <&ipic>;
425 + interrupts = <71 8>;
430 + reg = <0x200 0x100>;
431 + compatible = "mpc83xx_wdt";
432 + device_type = "watchdog";