target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_mdio.c

   1 /*
   2  *  Atheros AR71xx built-in ethernet mac driver
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Based on Atheros' AG7100 driver
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include "ag71xx.h"
  15
  16 #define AG71XX_MDIO_RETRY       1000
  17 #define AG71XX_MDIO_DELAY       5
  18
  19 static inline void ag71xx_mdio_wr(struct ag71xx_mdio *am, unsigned reg,
  20                                   u32 value)
  21 {
  22         void __iomem *r;
  23
  24         r = am->mdio_base + reg;
  25         __raw_writel(value, r);
  26
  27         /* flush write */
  28         (void) __raw_readl(r);
  29 }
  30
  31 static inline u32 ag71xx_mdio_rr(struct ag71xx_mdio *am, unsigned reg)
  32 {
  33         return __raw_readl(am->mdio_base + reg);
  34 }
  35
  36 static void ag71xx_mdio_dump_regs(struct ag71xx_mdio *am)
  37 {
  38         DBG("%s: mii_cfg=%08x, mii_cmd=%08x, mii_addr=%08x\n",
  39                 am->mii_bus->name,
  40                 ag71xx_mdio_rr(am, AG71XX_REG_MII_CFG),
  41                 ag71xx_mdio_rr(am, AG71XX_REG_MII_CMD),
  42                 ag71xx_mdio_rr(am, AG71XX_REG_MII_ADDR));
  43         DBG("%s: mii_ctrl=%08x, mii_status=%08x, mii_ind=%08x\n",
  44                 am->mii_bus->name,
  45                 ag71xx_mdio_rr(am, AG71XX_REG_MII_CTRL),
  46                 ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS),
  47                 ag71xx_mdio_rr(am, AG71XX_REG_MII_IND));
  48 }
  49
  50 static int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg)
  51 {
  52         int ret;
  53         int i;
  54
  55         ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
  56         ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR,
  57                         ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
  58         ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_READ);
  59
  60         i = AG71XX_MDIO_RETRY;
  61         while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) {
  62                 if (i-- == 0) {
  63                         printk(KERN_ERR "%s: mii_read timed out\n",
  64                                 am->mii_bus->name);
  65                         ret = 0xffff;
  66                         goto out;
  67                 }
  68                 udelay(AG71XX_MDIO_DELAY);
  69         }
  70
  71         ret = ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS) & 0xffff;
  72         ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
  73
  74         DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, ret);
  75
  76  out:
  77         return ret;
  78 }
  79
  80 static void ag71xx_mdio_mii_write(struct ag71xx_mdio *am,
  81                                   int addr, int reg, u16 val)
  82 {
  83         int i;
  84
  85         DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val);
  86
  87         ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR,
  88                         ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
  89         ag71xx_mdio_wr(am, AG71XX_REG_MII_CTRL, val);
  90
  91         i = AG71XX_MDIO_RETRY;
  92         while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) {
  93                 if (i-- == 0) {
  94                         printk(KERN_ERR "%s: mii_write timed out\n",
  95                                 am->mii_bus->name);
  96                         break;
  97                 }
  98                 udelay(AG71XX_MDIO_DELAY);
  99         }
 100 }
 101
 102 static int ag71xx_mdio_reset(struct mii_bus *bus)
 103 {
 104         struct ag71xx_mdio *am = bus->priv;
 105         u32 t;
 106
 107         if (am->pdata->is_ar7240)
 108                 t = MII_CFG_CLK_DIV_6;
 109         else
 110                 t = MII_CFG_CLK_DIV_28;
 111
 112         ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t | MII_CFG_RESET);
 113         udelay(100);
 114
 115         ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t);
 116         udelay(100);
 117
 118         return 0;
 119 }
 120
 121 static int ag71xx_mdio_read(struct mii_bus *bus, int addr, int reg)
 122 {
 123         struct ag71xx_mdio *am = bus->priv;
 124
 125         return ag71xx_mdio_mii_read(am, addr, reg);
 126 }
 127
 128 static int ag71xx_mdio_write(struct mii_bus *bus, int addr, int reg, u16 val)
 129 {
 130         struct ag71xx_mdio *am = bus->priv;
 131
 132         ag71xx_mdio_mii_write(am, addr, reg, val);
 133         return 0;
 134 }
 135
 136 static int __init ag71xx_mdio_probe(struct platform_device *pdev)
 137 {
 138         struct ag71xx_mdio_platform_data *pdata;
 139         struct ag71xx_mdio *am;
 140         struct resource *res;
 141         int i;
 142         int err;
 143
 144         pdata = pdev->dev.platform_data;
 145         if (!pdata) {
 146                 dev_err(&pdev->dev, "no platform data specified\n");
 147                 return -EINVAL;
 148         }
 149
 150         am = kzalloc(sizeof(*am), GFP_KERNEL);
 151         if (!am) {
 152                 err = -ENOMEM;
 153                 goto err_out;
 154         }
 155
 156         am->pdata = pdata;
 157
 158         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 159         if (!res) {
 160                 dev_err(&pdev->dev, "no iomem resource found\n");
 161                 err = -ENXIO;
 162                 goto err_out;
 163         }
 164
 165         am->mdio_base = ioremap_nocache(res->start, res->end - res->start + 1);
 166         if (!am->mdio_base) {
 167                 dev_err(&pdev->dev, "unable to ioremap registers\n");
 168                 err = -ENOMEM;
 169                 goto err_free_mdio;
 170         }
 171
 172         am->mii_bus = mdiobus_alloc();
 173         if (am->mii_bus == NULL) {
 174                 err = -ENOMEM;
 175                 goto err_iounmap;
 176         }
 177
 178         am->mii_bus->name = "ag71xx_mdio";
 179         am->mii_bus->read = ag71xx_mdio_read;
 180         am->mii_bus->write = ag71xx_mdio_write;
 181         am->mii_bus->reset = ag71xx_mdio_reset;
 182         am->mii_bus->irq = am->mii_irq;
 183         am->mii_bus->priv = am;
 184         am->mii_bus->parent = &pdev->dev;
 185         snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev));
 186         am->mii_bus->phy_mask = pdata->phy_mask;
 187
 188         for (i = 0; i < PHY_MAX_ADDR; i++)
 189                 am->mii_irq[i] = PHY_POLL;
 190
 191         ag71xx_mdio_wr(am, AG71XX_REG_MAC_CFG1, 0);
 192
 193         err = mdiobus_register(am->mii_bus);
 194         if (err)
 195                 goto err_free_bus;
 196
 197         ag71xx_mdio_dump_regs(am);
 198
 199         platform_set_drvdata(pdev, am);
 200         return 0;
 201
 202  err_free_bus:
 203         mdiobus_free(am->mii_bus);
 204  err_iounmap:
 205         iounmap(am->mdio_base);
 206  err_free_mdio:
 207         kfree(am);
 208  err_out:
 209         return err;
 210 }
 211
 212 static int __exit ag71xx_mdio_remove(struct platform_device *pdev)
 213 {
 214         struct ag71xx_mdio *am = platform_get_drvdata(pdev);
 215
 216         if (am) {
 217                 mdiobus_unregister(am->mii_bus);
 218                 mdiobus_free(am->mii_bus);
 219                 iounmap(am->mdio_base);
 220                 kfree(am);
 221                 platform_set_drvdata(pdev, NULL);
 222         }
 223
 224         return 0;
 225 }
 226
 227 static struct platform_driver ag71xx_mdio_driver = {
 228         .probe          = ag71xx_mdio_probe,
 229         .remove         = __exit_p(ag71xx_mdio_remove),
 230         .driver = {
 231                 .name   = "ag71xx-mdio",
 232         }
 233 };
 234
 235 int ag71xx_mdio_driver_init(void)
 236 {
 237         return platform_driver_register(&ag71xx_mdio_driver);
 238 }
 239
 240 void ag71xx_mdio_driver_exit(void)
 241 {
 242         platform_driver_unregister(&ag71xx_mdio_driver);
 243 }