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kernel: add a recent upstream commit (post-3.3) to the ssb update patch, required...
[openwrt.git] / target / linux / generic / patches-2.6.37 / 020-ssb_update.patch
1 --- a/drivers/ssb/main.c
2 +++ b/drivers/ssb/main.c
3 @@ -3,7 +3,7 @@
4 * Subsystem core
5 *
6 * Copyright 2005, Broadcom Corporation
7 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
9 *
10 * Licensed under the GNU/GPL. See COPYING for details.
11 */
12 @@ -12,6 +12,7 @@
13
14 #include <linux/delay.h>
15 #include <linux/io.h>
16 +#include <linux/module.h>
17 #include <linux/ssb/ssb.h>
18 #include <linux/ssb/ssb_regs.h>
19 #include <linux/ssb/ssb_driver_gige.h>
20 @@ -383,6 +384,35 @@ static int ssb_device_uevent(struct devi
21 ssb_dev->id.revision);
22 }
23
24 +#define ssb_config_attr(attrib, field, format_string) \
25 +static ssize_t \
26 +attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
27 +{ \
28 + return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
29 +}
30 +
31 +ssb_config_attr(core_num, core_index, "%u\n")
32 +ssb_config_attr(coreid, id.coreid, "0x%04x\n")
33 +ssb_config_attr(vendor, id.vendor, "0x%04x\n")
34 +ssb_config_attr(revision, id.revision, "%u\n")
35 +ssb_config_attr(irq, irq, "%u\n")
36 +static ssize_t
37 +name_show(struct device *dev, struct device_attribute *attr, char *buf)
38 +{
39 + return sprintf(buf, "%s\n",
40 + ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
41 +}
42 +
43 +static struct device_attribute ssb_device_attrs[] = {
44 + __ATTR_RO(name),
45 + __ATTR_RO(core_num),
46 + __ATTR_RO(coreid),
47 + __ATTR_RO(vendor),
48 + __ATTR_RO(revision),
49 + __ATTR_RO(irq),
50 + __ATTR_NULL,
51 +};
52 +
53 static struct bus_type ssb_bustype = {
54 .name = "ssb",
55 .match = ssb_bus_match,
56 @@ -392,6 +422,7 @@ static struct bus_type ssb_bustype = {
57 .suspend = ssb_device_suspend,
58 .resume = ssb_device_resume,
59 .uevent = ssb_device_uevent,
60 + .dev_attrs = ssb_device_attrs,
61 };
62
63 static void ssb_buses_lock(void)
64 @@ -527,7 +558,7 @@ error:
65 }
66
67 /* Needs ssb_buses_lock() */
68 -static int ssb_attach_queued_buses(void)
69 +static int __devinit ssb_attach_queued_buses(void)
70 {
71 struct ssb_bus *bus, *n;
72 int err = 0;
73 @@ -738,9 +769,9 @@ out:
74 return err;
75 }
76
77 -static int ssb_bus_register(struct ssb_bus *bus,
78 - ssb_invariants_func_t get_invariants,
79 - unsigned long baseaddr)
80 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
81 + ssb_invariants_func_t get_invariants,
82 + unsigned long baseaddr)
83 {
84 int err;
85
86 @@ -821,8 +852,8 @@ err_disable_xtal:
87 }
88
89 #ifdef CONFIG_SSB_PCIHOST
90 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
91 - struct pci_dev *host_pci)
92 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
93 + struct pci_dev *host_pci)
94 {
95 int err;
96
97 @@ -845,9 +876,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
98 #endif /* CONFIG_SSB_PCIHOST */
99
100 #ifdef CONFIG_SSB_PCMCIAHOST
101 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
102 - struct pcmcia_device *pcmcia_dev,
103 - unsigned long baseaddr)
104 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
105 + struct pcmcia_device *pcmcia_dev,
106 + unsigned long baseaddr)
107 {
108 int err;
109
110 @@ -867,8 +898,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register
111 #endif /* CONFIG_SSB_PCMCIAHOST */
112
113 #ifdef CONFIG_SSB_SDIOHOST
114 -int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
115 - unsigned int quirks)
116 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
117 + struct sdio_func *func,
118 + unsigned int quirks)
119 {
120 int err;
121
122 @@ -888,9 +920,9 @@ int ssb_bus_sdiobus_register(struct ssb_
123 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
124 #endif /* CONFIG_SSB_PCMCIAHOST */
125
126 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
127 - unsigned long baseaddr,
128 - ssb_invariants_func_t get_invariants)
129 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
130 + unsigned long baseaddr,
131 + ssb_invariants_func_t get_invariants)
132 {
133 int err;
134
135 @@ -971,8 +1003,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
136 switch (plltype) {
137 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
138 if (m & SSB_CHIPCO_CLK_T6_MMASK)
139 - return SSB_CHIPCO_CLK_T6_M0;
140 - return SSB_CHIPCO_CLK_T6_M1;
141 + return SSB_CHIPCO_CLK_T6_M1;
142 + return SSB_CHIPCO_CLK_T6_M0;
143 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
144 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
145 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
146 @@ -1087,23 +1119,22 @@ static u32 ssb_tmslow_reject_bitmask(str
147 {
148 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
149
150 - /* The REJECT bit changed position in TMSLOW between
151 - * Backplane revisions. */
152 + /* The REJECT bit seems to be different for Backplane rev 2.3 */
153 switch (rev) {
154 case SSB_IDLOW_SSBREV_22:
155 - return SSB_TMSLOW_REJECT_22;
156 + case SSB_IDLOW_SSBREV_24:
157 + case SSB_IDLOW_SSBREV_26:
158 + return SSB_TMSLOW_REJECT;
159 case SSB_IDLOW_SSBREV_23:
160 return SSB_TMSLOW_REJECT_23;
161 - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
162 - case SSB_IDLOW_SSBREV_25: /* same here */
163 - case SSB_IDLOW_SSBREV_26: /* same here */
164 + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
165 case SSB_IDLOW_SSBREV_27: /* same here */
166 - return SSB_TMSLOW_REJECT_23; /* this is a guess */
167 + return SSB_TMSLOW_REJECT; /* this is a guess */
168 default:
169 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
170 WARN_ON(1);
171 }
172 - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
173 + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
174 }
175
176 int ssb_device_is_enabled(struct ssb_device *dev)
177 @@ -1162,10 +1193,10 @@ void ssb_device_enable(struct ssb_device
178 }
179 EXPORT_SYMBOL(ssb_device_enable);
180
181 -/* Wait for a bit in a register to get set or unset.
182 +/* Wait for bitmask in a register to get set or cleared.
183 * timeout is in units of ten-microseconds */
184 -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
185 - int timeout, int set)
186 +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
187 + int timeout, int set)
188 {
189 int i;
190 u32 val;
191 @@ -1173,7 +1204,7 @@ static int ssb_wait_bit(struct ssb_devic
192 for (i = 0; i < timeout; i++) {
193 val = ssb_read32(dev, reg);
194 if (set) {
195 - if (val & bitmask)
196 + if ((val & bitmask) == bitmask)
197 return 0;
198 } else {
199 if (!(val & bitmask))
200 @@ -1190,20 +1221,38 @@ static int ssb_wait_bit(struct ssb_devic
201
202 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
203 {
204 - u32 reject;
205 + u32 reject, val;
206
207 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
208 return;
209
210 reject = ssb_tmslow_reject_bitmask(dev);
211 - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
212 - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
213 - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
214 - ssb_write32(dev, SSB_TMSLOW,
215 - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
216 - reject | SSB_TMSLOW_RESET |
217 - core_specific_flags);
218 - ssb_flush_tmslow(dev);
219 +
220 + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
221 + ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
222 + ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
223 + ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
224 +
225 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
226 + val = ssb_read32(dev, SSB_IMSTATE);
227 + val |= SSB_IMSTATE_REJECT;
228 + ssb_write32(dev, SSB_IMSTATE, val);
229 + ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
230 + 0);
231 + }
232 +
233 + ssb_write32(dev, SSB_TMSLOW,
234 + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
235 + reject | SSB_TMSLOW_RESET |
236 + core_specific_flags);
237 + ssb_flush_tmslow(dev);
238 +
239 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
240 + val = ssb_read32(dev, SSB_IMSTATE);
241 + val &= ~SSB_IMSTATE_REJECT;
242 + ssb_write32(dev, SSB_IMSTATE, val);
243 + }
244 + }
245
246 ssb_write32(dev, SSB_TMSLOW,
247 reject | SSB_TMSLOW_RESET |
248 @@ -1212,13 +1261,34 @@ void ssb_device_disable(struct ssb_devic
249 }
250 EXPORT_SYMBOL(ssb_device_disable);
251
252 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
253 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
254 +{
255 + u16 chip_id = dev->bus->chip_id;
256 +
257 + if (dev->id.coreid == SSB_DEV_80211) {
258 + return (chip_id == 0x4322 || chip_id == 43221 ||
259 + chip_id == 43231 || chip_id == 43222);
260 + }
261 +
262 + return 0;
263 +}
264 +
265 u32 ssb_dma_translation(struct ssb_device *dev)
266 {
267 switch (dev->bus->bustype) {
268 case SSB_BUSTYPE_SSB:
269 return 0;
270 case SSB_BUSTYPE_PCI:
271 - return SSB_PCI_DMA;
272 + if (pci_is_pcie(dev->bus->host_pci) &&
273 + ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
274 + return SSB_PCIE_DMA_H32;
275 + } else {
276 + if (ssb_dma_translation_special_bit(dev))
277 + return SSB_PCIE_DMA_H32;
278 + else
279 + return SSB_PCI_DMA;
280 + }
281 default:
282 __ssb_dma_not_implemented(dev);
283 }
284 @@ -1261,20 +1331,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
285
286 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
287 {
288 - struct ssb_chipcommon *cc;
289 int err;
290 enum ssb_clkmode mode;
291
292 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
293 if (err)
294 goto error;
295 - cc = &bus->chipco;
296 - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
297 - ssb_chipco_set_clockmode(cc, mode);
298
299 #ifdef CONFIG_SSB_DEBUG
300 bus->powered_up = 1;
301 #endif
302 +
303 + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
304 + ssb_chipco_set_clockmode(&bus->chipco, mode);
305 +
306 return 0;
307 error:
308 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
309 @@ -1282,6 +1352,37 @@ error:
310 }
311 EXPORT_SYMBOL(ssb_bus_powerup);
312
313 +static void ssb_broadcast_value(struct ssb_device *dev,
314 + u32 address, u32 data)
315 +{
316 +#ifdef CONFIG_SSB_DRIVER_PCICORE
317 + /* This is used for both, PCI and ChipCommon core, so be careful. */
318 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
319 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
320 +#endif
321 +
322 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
323 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
324 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
325 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
326 +}
327 +
328 +void ssb_commit_settings(struct ssb_bus *bus)
329 +{
330 + struct ssb_device *dev;
331 +
332 +#ifdef CONFIG_SSB_DRIVER_PCICORE
333 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
334 +#else
335 + dev = bus->chipco.dev;
336 +#endif
337 + if (WARN_ON(!dev))
338 + return;
339 + /* This forces an update of the cached registers. */
340 + ssb_broadcast_value(dev, 0xFD8, 0);
341 +}
342 +EXPORT_SYMBOL(ssb_commit_settings);
343 +
344 u32 ssb_admatch_base(u32 adm)
345 {
346 u32 base = 0;
347 --- a/drivers/ssb/pci.c
348 +++ b/drivers/ssb/pci.c
349 @@ -1,7 +1,7 @@
350 /*
351 * Sonics Silicon Backplane PCI-Hostbus related functions.
352 *
353 - * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
354 + * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
355 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
356 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
357 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
358 @@ -406,6 +406,46 @@ static void sprom_extract_r123(struct ss
359 out->antenna_gain.ghz5.a3 = gain;
360 }
361
362 +/* Revs 4 5 and 8 have partially shared layout */
363 +static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
364 +{
365 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
366 + SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
367 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
368 + SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
369 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
370 + SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
371 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
372 + SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
373 +
374 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
375 + SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
376 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
377 + SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
378 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
379 + SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
380 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
381 + SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
382 +
383 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
384 + SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
385 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
386 + SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
387 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
388 + SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
389 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
390 + SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
391 +
392 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
393 + SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
394 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
395 + SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
396 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
397 + SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
398 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
399 + SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
400 +}
401 +
402 static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
403 {
404 int i;
405 @@ -428,10 +468,14 @@ static void sprom_extract_r45(struct ssb
406 SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
407 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
408 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
409 + SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
410 + SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
411 } else {
412 SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
413 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
414 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
415 + SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
416 + SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
417 }
418 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
419 SSB_SPROM4_ANTAVAIL_A_SHIFT);
420 @@ -471,13 +515,21 @@ static void sprom_extract_r45(struct ssb
421 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
422 sizeof(out->antenna_gain.ghz5));
423
424 + sprom_extract_r458(out, in);
425 +
426 /* TODO - get remaining rev 4 stuff needed */
427 }
428
429 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
430 {
431 int i;
432 - u16 v;
433 + u16 v, o;
434 + u16 pwr_info_offset[] = {
435 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
436 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
437 + };
438 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
439 + ARRAY_SIZE(out->core_pwr_info));
440
441 /* extract the MAC address */
442 for (i = 0; i < 3; i++) {
443 @@ -561,6 +613,63 @@ static void sprom_extract_r8(struct ssb_
444 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
445 sizeof(out->antenna_gain.ghz5));
446
447 + /* Extract cores power info info */
448 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
449 + o = pwr_info_offset[i];
450 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
451 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
452 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
453 + SSB_SPROM8_2G_MAXP, 0);
454 +
455 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
456 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
457 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
458 +
459 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
460 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
461 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
462 + SSB_SPROM8_5G_MAXP, 0);
463 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
464 + SSB_SPROM8_5GH_MAXP, 0);
465 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
466 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
467 +
468 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
469 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
470 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
471 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
472 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
473 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
474 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
475 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
476 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
477 + }
478 +
479 + /* Extract FEM info */
480 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
481 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
482 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
483 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
484 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
485 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
486 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
487 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
488 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
489 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
490 +
491 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
492 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
493 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
494 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
495 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
496 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
497 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
498 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
499 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
500 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
501 +
502 + sprom_extract_r458(out, in);
503 +
504 /* TODO - get remaining rev 8 stuff needed */
505 }
506
507 @@ -573,37 +682,34 @@ static int sprom_extract(struct ssb_bus
508 ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
509 memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
510 memset(out->et1mac, 0xFF, 6);
511 +
512 if ((bus->chip_id & 0xFF00) == 0x4400) {
513 /* Workaround: The BCM44XX chip has a stupid revision
514 * number stored in the SPROM.
515 * Always extract r1. */
516 out->revision = 1;
517 + ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
518 + }
519 +
520 + switch (out->revision) {
521 + case 1:
522 + case 2:
523 + case 3:
524 sprom_extract_r123(out, in);
525 - } else if (bus->chip_id == 0x4321) {
526 - /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
527 - out->revision = 4;
528 + break;
529 + case 4:
530 + case 5:
531 sprom_extract_r45(out, in);
532 - } else {
533 - switch (out->revision) {
534 - case 1:
535 - case 2:
536 - case 3:
537 - sprom_extract_r123(out, in);
538 - break;
539 - case 4:
540 - case 5:
541 - sprom_extract_r45(out, in);
542 - break;
543 - case 8:
544 - sprom_extract_r8(out, in);
545 - break;
546 - default:
547 - ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
548 - " revision %d detected. Will extract"
549 - " v1\n", out->revision);
550 - out->revision = 1;
551 - sprom_extract_r123(out, in);
552 - }
553 + break;
554 + case 8:
555 + sprom_extract_r8(out, in);
556 + break;
557 + default:
558 + ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
559 + " revision %d detected. Will extract"
560 + " v1\n", out->revision);
561 + out->revision = 1;
562 + sprom_extract_r123(out, in);
563 }
564
565 if (out->boardflags_lo == 0xFFFF)
566 @@ -617,15 +723,14 @@ static int sprom_extract(struct ssb_bus
567 static int ssb_pci_sprom_get(struct ssb_bus *bus,
568 struct ssb_sprom *sprom)
569 {
570 - const struct ssb_sprom *fallback;
571 - int err = -ENOMEM;
572 + int err;
573 u16 *buf;
574
575 if (!ssb_is_sprom_available(bus)) {
576 ssb_printk(KERN_ERR PFX "No SPROM available!\n");
577 return -ENODEV;
578 }
579 - if (bus->chipco.dev) { /* can be unavailible! */
580 + if (bus->chipco.dev) { /* can be unavailable! */
581 /*
582 * get SPROM offset: SSB_SPROM_BASE1 except for
583 * chipcommon rev >= 31 or chip ID is 0x4312 and
584 @@ -645,7 +750,7 @@ static int ssb_pci_sprom_get(struct ssb_
585
586 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
587 if (!buf)
588 - goto out;
589 + return -ENOMEM;
590 bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
591 sprom_do_read(bus, buf);
592 err = sprom_check_crc(buf, bus->sprom_size);
593 @@ -655,17 +760,24 @@ static int ssb_pci_sprom_get(struct ssb_
594 buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
595 GFP_KERNEL);
596 if (!buf)
597 - goto out;
598 + return -ENOMEM;
599 bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
600 sprom_do_read(bus, buf);
601 err = sprom_check_crc(buf, bus->sprom_size);
602 if (err) {
603 /* All CRC attempts failed.
604 * Maybe there is no SPROM on the device?
605 - * If we have a fallback, use that. */
606 - fallback = ssb_get_fallback_sprom();
607 - if (fallback) {
608 - memcpy(sprom, fallback, sizeof(*sprom));
609 + * Now we ask the arch code if there is some sprom
610 + * available for this device in some other storage */
611 + err = ssb_fill_sprom_with_fallback(bus, sprom);
612 + if (err) {
613 + ssb_printk(KERN_WARNING PFX "WARNING: Using"
614 + " fallback SPROM failed (err %d)\n",
615 + err);
616 + } else {
617 + ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
618 + " revision %d provided by"
619 + " platform.\n", sprom->revision);
620 err = 0;
621 goto out_free;
622 }
623 @@ -677,19 +789,15 @@ static int ssb_pci_sprom_get(struct ssb_
624
625 out_free:
626 kfree(buf);
627 -out:
628 return err;
629 }
630
631 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
632 struct ssb_boardinfo *bi)
633 {
634 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
635 - &bi->vendor);
636 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
637 - &bi->type);
638 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
639 - &bi->rev);
640 + bi->vendor = bus->host_pci->subsystem_vendor;
641 + bi->type = bus->host_pci->subsystem_device;
642 + bi->rev = bus->host_pci->revision;
643 }
644
645 int ssb_pci_get_invariants(struct ssb_bus *bus,
646 --- a/drivers/ssb/pcihost_wrapper.c
647 +++ b/drivers/ssb/pcihost_wrapper.c
648 @@ -6,7 +6,7 @@
649 * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
650 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
651 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
652 - * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
653 + * Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
654 *
655 * Licensed under the GNU/GPL. See COPYING for details.
656 */
657 @@ -53,12 +53,13 @@ static int ssb_pcihost_resume(struct pci
658 # define ssb_pcihost_resume NULL
659 #endif /* CONFIG_PM */
660
661 -static int ssb_pcihost_probe(struct pci_dev *dev,
662 - const struct pci_device_id *id)
663 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
664 + const struct pci_device_id *id)
665 {
666 struct ssb_bus *ssb;
667 int err = -ENOMEM;
668 const char *name;
669 + u32 val;
670
671 ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
672 if (!ssb)
673 @@ -74,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_
674 goto err_pci_disable;
675 pci_set_master(dev);
676
677 + /* Disable the RETRY_TIMEOUT register (0x41) to keep
678 + * PCI Tx retries from interfering with C3 CPU state */
679 + pci_read_config_dword(dev, 0x40, &val);
680 + if ((val & 0x0000ff00) != 0)
681 + pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
682 +
683 err = ssb_bus_pcibus_register(ssb, dev);
684 if (err)
685 goto err_pci_release_regions;
686 @@ -103,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
687 pci_set_drvdata(dev, NULL);
688 }
689
690 -int ssb_pcihost_register(struct pci_driver *driver)
691 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
692 {
693 driver->probe = ssb_pcihost_probe;
694 driver->remove = ssb_pcihost_remove;
695 --- a/drivers/ssb/scan.c
696 +++ b/drivers/ssb/scan.c
697 @@ -2,7 +2,7 @@
698 * Sonics Silicon Backplane
699 * Bus scanning
700 *
701 - * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
702 + * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
703 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
704 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
705 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
706 @@ -258,7 +258,10 @@ static int we_support_multiple_80211_cor
707 #ifdef CONFIG_SSB_PCIHOST
708 if (bus->bustype == SSB_BUSTYPE_PCI) {
709 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
710 - bus->host_pci->device == 0x4324)
711 + ((bus->host_pci->device == 0x4313) ||
712 + (bus->host_pci->device == 0x431A) ||
713 + (bus->host_pci->device == 0x4321) ||
714 + (bus->host_pci->device == 0x4324)))
715 return 1;
716 }
717 #endif /* CONFIG_SSB_PCIHOST */
718 @@ -307,8 +310,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
719 } else {
720 if (bus->bustype == SSB_BUSTYPE_PCI) {
721 bus->chip_id = pcidev_to_chipid(bus->host_pci);
722 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
723 - &bus->chip_rev);
724 + bus->chip_rev = bus->host_pci->revision;
725 bus->chip_package = 0;
726 } else {
727 bus->chip_id = 0x4710;
728 @@ -405,10 +407,10 @@ int ssb_bus_scan(struct ssb_bus *bus,
729 /* Ignore PCI cores on PCI-E cards.
730 * Ignore PCI-E cores on PCI cards. */
731 if (dev->id.coreid == SSB_DEV_PCI) {
732 - if (bus->host_pci->is_pcie)
733 + if (pci_is_pcie(bus->host_pci))
734 continue;
735 } else {
736 - if (!bus->host_pci->is_pcie)
737 + if (!pci_is_pcie(bus->host_pci))
738 continue;
739 }
740 }
741 @@ -420,6 +422,16 @@ int ssb_bus_scan(struct ssb_bus *bus,
742 bus->pcicore.dev = dev;
743 #endif /* CONFIG_SSB_DRIVER_PCICORE */
744 break;
745 + case SSB_DEV_ETHERNET:
746 + if (bus->bustype == SSB_BUSTYPE_PCI) {
747 + if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
748 + (bus->host_pci->device & 0xFF00) == 0x4300) {
749 + /* This is a dangling ethernet core on a
750 + * wireless device. Ignore it. */
751 + continue;
752 + }
753 + }
754 + break;
755 default:
756 break;
757 }
758 --- a/include/linux/ssb/ssb.h
759 +++ b/include/linux/ssb/ssb.h
760 @@ -16,6 +16,12 @@ struct pcmcia_device;
761 struct ssb_bus;
762 struct ssb_driver;
763
764 +struct ssb_sprom_core_pwr_info {
765 + u8 itssi_2g, itssi_5g;
766 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
767 + u16 pa_2g[3], pa_5gl[3], pa_5g[3], pa_5gh[3];
768 +};
769 +
770 struct ssb_sprom {
771 u8 revision;
772 u8 il0mac[6]; /* MAC address for 802.11b/g */
773 @@ -25,8 +31,10 @@ struct ssb_sprom {
774 u8 et1phyaddr; /* MII address for enet1 */
775 u8 et0mdcport; /* MDIO for enet0 */
776 u8 et1mdcport; /* MDIO for enet1 */
777 - u8 board_rev; /* Board revision number from SPROM. */
778 + u16 board_rev; /* Board revision number from SPROM. */
779 u8 country_code; /* Country Code */
780 + u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
781 + u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
782 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
783 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
784 u16 pa0b0;
785 @@ -55,6 +63,10 @@ struct ssb_sprom {
786 u8 tri5gl; /* 5.2GHz TX isolation */
787 u8 tri5g; /* 5.3GHz TX isolation */
788 u8 tri5gh; /* 5.8GHz TX isolation */
789 + u8 txpid2g[4]; /* 2GHz TX power index */
790 + u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
791 + u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
792 + u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
793 u8 rxpo2g; /* 2GHz RX power offset */
794 u8 rxpo5g; /* 5GHz RX power offset */
795 u8 rssisav2g; /* 2GHz RSSI params */
796 @@ -76,6 +88,8 @@ struct ssb_sprom {
797 u16 boardflags2_hi; /* Board flags (bits 48-63) */
798 /* TODO store board flags in a single u64 */
799
800 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
801 +
802 /* Antenna gain values for up to 4 antennas
803 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
804 * loss in the connectors is bigger than the gain. */
805 @@ -88,6 +102,15 @@ struct ssb_sprom {
806 } ghz5; /* 5GHz band */
807 } antenna_gain;
808
809 + struct {
810 + struct {
811 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
812 + } ghz2;
813 + struct {
814 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
815 + } ghz5;
816 + } fem;
817 +
818 /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
819 };
820
821 @@ -95,7 +118,7 @@ struct ssb_sprom {
822 struct ssb_boardinfo {
823 u16 vendor;
824 u16 type;
825 - u16 rev;
826 + u8 rev;
827 };
828
829
830 @@ -225,10 +248,9 @@ struct ssb_driver {
831 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
832
833 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
834 -static inline int ssb_driver_register(struct ssb_driver *drv)
835 -{
836 - return __ssb_driver_register(drv, THIS_MODULE);
837 -}
838 +#define ssb_driver_register(drv) \
839 + __ssb_driver_register(drv, THIS_MODULE)
840 +
841 extern void ssb_driver_unregister(struct ssb_driver *drv);
842
843
844 @@ -304,7 +326,7 @@ struct ssb_bus {
845
846 /* ID information about the Chip. */
847 u16 chip_id;
848 - u16 chip_rev;
849 + u8 chip_rev;
850 u16 sprom_offset;
851 u16 sprom_size; /* number of words in sprom */
852 u8 chip_package;
853 @@ -400,7 +422,9 @@ extern bool ssb_is_sprom_available(struc
854
855 /* Set a fallback SPROM.
856 * See kdoc at the function definition for complete documentation. */
857 -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
858 +extern int ssb_arch_register_fallback_sprom(
859 + int (*sprom_callback)(struct ssb_bus *bus,
860 + struct ssb_sprom *out));
861
862 /* Suspend a SSB bus.
863 * Call this from the parent bus suspend routine. */
864 @@ -514,6 +538,7 @@ extern int ssb_bus_may_powerdown(struct
865 * Otherwise static always-on powercontrol will be used. */
866 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
867
868 +extern void ssb_commit_settings(struct ssb_bus *bus);
869
870 /* Various helper functions */
871 extern u32 ssb_admatch_base(u32 adm);
872 --- a/include/linux/ssb/ssb_regs.h
873 +++ b/include/linux/ssb/ssb_regs.h
874 @@ -85,6 +85,8 @@
875 #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
876 #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
877 #define SSB_IMSTATE_TO 0x00040000 /* Timeout */
878 +#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
879 +#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
880 #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
881 #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
882 #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
883 @@ -95,9 +97,8 @@
884 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
885 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
886 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
887 -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
888 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
889 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
890 -#define SSB_TMSLOW_PHYCLK 0x00000010 /* MAC PHY Clock Control Enable */
891 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
892 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
893 #define SSB_TMSLOW_PE 0x40000000 /* Power Management Enable */
894 @@ -268,6 +269,8 @@
895 /* SPROM Revision 4 */
896 #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
897 #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
898 +#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
899 +#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
900 #define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
901 #define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
902 #define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
903 @@ -299,6 +302,46 @@
904 #define SSB_SPROM4_AGAIN2_SHIFT 0
905 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
906 #define SSB_SPROM4_AGAIN3_SHIFT 8
907 +#define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */
908 +#define SSB_SPROM4_TXPID2G0 0x00FF
909 +#define SSB_SPROM4_TXPID2G0_SHIFT 0
910 +#define SSB_SPROM4_TXPID2G1 0xFF00
911 +#define SSB_SPROM4_TXPID2G1_SHIFT 8
912 +#define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */
913 +#define SSB_SPROM4_TXPID2G2 0x00FF
914 +#define SSB_SPROM4_TXPID2G2_SHIFT 0
915 +#define SSB_SPROM4_TXPID2G3 0xFF00
916 +#define SSB_SPROM4_TXPID2G3_SHIFT 8
917 +#define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */
918 +#define SSB_SPROM4_TXPID5G0 0x00FF
919 +#define SSB_SPROM4_TXPID5G0_SHIFT 0
920 +#define SSB_SPROM4_TXPID5G1 0xFF00
921 +#define SSB_SPROM4_TXPID5G1_SHIFT 8
922 +#define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */
923 +#define SSB_SPROM4_TXPID5G2 0x00FF
924 +#define SSB_SPROM4_TXPID5G2_SHIFT 0
925 +#define SSB_SPROM4_TXPID5G3 0xFF00
926 +#define SSB_SPROM4_TXPID5G3_SHIFT 8
927 +#define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */
928 +#define SSB_SPROM4_TXPID5GL0 0x00FF
929 +#define SSB_SPROM4_TXPID5GL0_SHIFT 0
930 +#define SSB_SPROM4_TXPID5GL1 0xFF00
931 +#define SSB_SPROM4_TXPID5GL1_SHIFT 8
932 +#define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */
933 +#define SSB_SPROM4_TXPID5GL2 0x00FF
934 +#define SSB_SPROM4_TXPID5GL2_SHIFT 0
935 +#define SSB_SPROM4_TXPID5GL3 0xFF00
936 +#define SSB_SPROM4_TXPID5GL3_SHIFT 8
937 +#define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */
938 +#define SSB_SPROM4_TXPID5GH0 0x00FF
939 +#define SSB_SPROM4_TXPID5GH0_SHIFT 0
940 +#define SSB_SPROM4_TXPID5GH1 0xFF00
941 +#define SSB_SPROM4_TXPID5GH1_SHIFT 8
942 +#define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */
943 +#define SSB_SPROM4_TXPID5GH2 0x00FF
944 +#define SSB_SPROM4_TXPID5GH2_SHIFT 0
945 +#define SSB_SPROM4_TXPID5GH3 0xFF00
946 +#define SSB_SPROM4_TXPID5GH3_SHIFT 8
947 #define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
948 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
949 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
950 @@ -318,6 +361,8 @@
951 #define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
952 #define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
953 #define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
954 +#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
955 +#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
956 #define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
957 #define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
958 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
959 @@ -387,6 +432,56 @@
960 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
961 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
962 #define SSB_SPROM8_RXPO5G_SHIFT 8
963 +#define SSB_SPROM8_FEM2G 0x00AE
964 +#define SSB_SPROM8_FEM5G 0x00B0
965 +#define SSB_SROM8_FEM_TSSIPOS 0x0001
966 +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
967 +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
968 +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
969 +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
970 +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
971 +#define SSB_SROM8_FEM_TR_ISO 0x0700
972 +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
973 +#define SSB_SROM8_FEM_ANTSWLUT 0xF800
974 +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
975 +#define SSB_SPROM8_THERMAL 0x00B2
976 +#define SSB_SPROM8_MPWR_RAWTS 0x00B4
977 +#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
978 +#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
979 +#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
980 +
981 +/* There are 4 blocks with power info sharing the same layout */
982 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
983 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
984 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
985 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
986 +
987 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
988 +#define SSB_SPROM8_2G_MAXP 0x00FF
989 +#define SSB_SPROM8_2G_ITSSI 0xFF00
990 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
991 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
992 +#define SSB_SROM8_2G_PA_1 0x04
993 +#define SSB_SROM8_2G_PA_2 0x06
994 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
995 +#define SSB_SPROM8_5G_MAXP 0x00FF
996 +#define SSB_SPROM8_5G_ITSSI 0xFF00
997 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
998 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
999 +#define SSB_SPROM8_5GH_MAXP 0x00FF
1000 +#define SSB_SPROM8_5GL_MAXP 0xFF00
1001 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
1002 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
1003 +#define SSB_SROM8_5G_PA_1 0x0E
1004 +#define SSB_SROM8_5G_PA_2 0x10
1005 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
1006 +#define SSB_SROM8_5GL_PA_1 0x14
1007 +#define SSB_SROM8_5GL_PA_2 0x16
1008 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
1009 +#define SSB_SROM8_5GH_PA_1 0x1A
1010 +#define SSB_SROM8_5GH_PA_2 0x1C
1011 +
1012 +/* TODO: Make it deprecated */
1013 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
1014 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
1015 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1016 @@ -411,12 +506,53 @@
1017 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
1018 #define SSB_SPROM8_PA1HIB1 0x00DA
1019 #define SSB_SPROM8_PA1HIB2 0x00DC
1020 +
1021 #define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
1022 #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
1023 #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
1024 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
1025 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
1026
1027 +/* Values for boardflags_lo read from SPROM */
1028 +#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
1029 +#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
1030 +#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
1031 +#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
1032 +#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
1033 +#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
1034 +#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
1035 +#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
1036 +#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
1037 +#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
1038 +#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
1039 +#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
1040 +#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
1041 +#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
1042 +#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
1043 +#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
1044 +
1045 +/* Values for boardflags_hi read from SPROM */
1046 +#define SSB_BFH_NOPA 0x0001 /* has no PA */
1047 +#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
1048 +#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
1049 +#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
1050 +#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
1051 +#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
1052 +#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
1053 +
1054 +/* Values for boardflags2_lo read from SPROM */
1055 +#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
1056 +#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
1057 +#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
1058 +#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
1059 +#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
1060 +#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
1061 +#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
1062 +#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
1063 +#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
1064 +#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
1065 +#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
1066 +
1067 /* Values for SSB_SPROM1_BINF_CCODE */
1068 enum {
1069 SSB_SPROM1CCODE_WORLD = 0,
1070 --- a/drivers/ssb/driver_chipcommon.c
1071 +++ b/drivers/ssb/driver_chipcommon.c
1072 @@ -3,7 +3,7 @@
1073 * Broadcom ChipCommon core driver
1074 *
1075 * Copyright 2005, Broadcom Corporation
1076 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1077 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1078 *
1079 * Licensed under the GNU/GPL. See COPYING for details.
1080 */
1081 @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb
1082 if (!ccdev)
1083 return;
1084 bus = ccdev->bus;
1085 +
1086 + /* We support SLOW only on 6..9 */
1087 + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
1088 + mode = SSB_CLKMODE_DYNAMIC;
1089 +
1090 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
1091 + return; /* PMU controls clockmode, separated function needed */
1092 + SSB_WARN_ON(ccdev->id.revision >= 20);
1093 +
1094 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1095 if (ccdev->id.revision < 6)
1096 return;
1097 - /* chipcommon cores rev10 are a whole new ball game */
1098 +
1099 + /* ChipCommon cores rev10+ need testing */
1100 if (ccdev->id.revision >= 10)
1101 return;
1102 +
1103 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
1104 return;
1105
1106 switch (mode) {
1107 - case SSB_CLKMODE_SLOW:
1108 + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
1109 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
1110 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
1111 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
1112 break;
1113 case SSB_CLKMODE_FAST:
1114 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
1115 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
1116 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
1117 - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
1118 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
1119 + if (ccdev->id.revision < 10) {
1120 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
1121 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
1122 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
1123 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
1124 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
1125 + } else {
1126 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
1127 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
1128 + SSB_CHIPCO_SYSCLKCTL_FORCEHT));
1129 + /* udelay(150); TODO: not available in early init */
1130 + }
1131 break;
1132 case SSB_CLKMODE_DYNAMIC:
1133 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
1134 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
1135 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
1136 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
1137 - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
1138 - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
1139 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
1140 -
1141 - /* for dynamic control, we have to release our xtal_pu "force on" */
1142 - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
1143 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
1144 + if (ccdev->id.revision < 10) {
1145 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
1146 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
1147 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
1148 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
1149 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
1150 + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
1151 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
1152 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
1153 +
1154 + /* For dynamic control, we have to release our xtal_pu
1155 + * "force on" */
1156 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
1157 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
1158 + } else {
1159 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
1160 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
1161 + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
1162 + }
1163 break;
1164 default:
1165 SSB_WARN_ON(1);
1166 @@ -260,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chip
1167 if (cc->dev->id.revision >= 11)
1168 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
1169 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
1170 +
1171 + if (cc->dev->id.revision >= 20) {
1172 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
1173 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
1174 + }
1175 +
1176 ssb_pmu_init(cc);
1177 chipco_powercontrol_init(cc);
1178 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
1179 --- a/drivers/ssb/driver_chipcommon_pmu.c
1180 +++ b/drivers/ssb/driver_chipcommon_pmu.c
1181 @@ -2,7 +2,7 @@
1182 * Sonics Silicon Backplane
1183 * Broadcom ChipCommon Power Management Unit driver
1184 *
1185 - * Copyright 2009, Michael Buesch <mb@bu3sch.de>
1186 + * Copyright 2009, Michael Buesch <m@bues.ch>
1187 * Copyright 2007, Broadcom Corporation
1188 *
1189 * Licensed under the GNU/GPL. See COPYING for details.
1190 @@ -417,12 +417,14 @@ static void ssb_pmu_resources_init(struc
1191 u32 min_msk = 0, max_msk = 0;
1192 unsigned int i;
1193 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
1194 - unsigned int updown_tab_size;
1195 + unsigned int updown_tab_size = 0;
1196 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
1197 - unsigned int depend_tab_size;
1198 + unsigned int depend_tab_size = 0;
1199
1200 switch (bus->chip_id) {
1201 case 0x4312:
1202 + min_msk = 0xCBB;
1203 + break;
1204 case 0x4322:
1205 /* We keep the default settings:
1206 * min_msk = 0xCBB
1207 --- a/drivers/ssb/driver_gige.c
1208 +++ b/drivers/ssb/driver_gige.c
1209 @@ -3,7 +3,7 @@
1210 * Broadcom Gigabit Ethernet core driver
1211 *
1212 * Copyright 2008, Broadcom Corporation
1213 - * Copyright 2008, Michael Buesch <mb@bu3sch.de>
1214 + * Copyright 2008, Michael Buesch <m@bues.ch>
1215 *
1216 * Licensed under the GNU/GPL. See COPYING for details.
1217 */
1218 @@ -106,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
1219 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
1220 }
1221
1222 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
1223 - int reg, int size, u32 *val)
1224 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
1225 + unsigned int devfn, int reg,
1226 + int size, u32 *val)
1227 {
1228 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
1229 unsigned long flags;
1230 @@ -136,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
1231 return PCIBIOS_SUCCESSFUL;
1232 }
1233
1234 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
1235 - int reg, int size, u32 val)
1236 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
1237 + unsigned int devfn, int reg,
1238 + int size, u32 val)
1239 {
1240 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
1241 unsigned long flags;
1242 @@ -166,7 +168,8 @@ static int ssb_gige_pci_write_config(str
1243 return PCIBIOS_SUCCESSFUL;
1244 }
1245
1246 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
1247 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
1248 + const struct ssb_device_id *id)
1249 {
1250 struct ssb_gige *dev;
1251 u32 base, tmslow, tmshigh;
1252 --- a/drivers/ssb/driver_pcicore.c
1253 +++ b/drivers/ssb/driver_pcicore.c
1254 @@ -3,7 +3,7 @@
1255 * Broadcom PCI-core driver
1256 *
1257 * Copyright 2005, Broadcom Corporation
1258 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1259 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1260 *
1261 * Licensed under the GNU/GPL. See COPYING for details.
1262 */
1263 @@ -15,6 +15,11 @@
1264
1265 #include "ssb_private.h"
1266
1267 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
1268 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
1269 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
1270 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1271 + u8 address, u16 data);
1272
1273 static inline
1274 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
1275 @@ -309,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
1276 return ssb_mips_irq(extpci_core->dev) + 2;
1277 }
1278
1279 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
1280 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
1281 {
1282 u32 val;
1283
1284 @@ -374,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
1285 register_pci_controller(&ssb_pcicore_controller);
1286 }
1287
1288 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
1289 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
1290 {
1291 struct ssb_bus *bus = pc->dev->bus;
1292 u16 chipid_top;
1293 @@ -403,25 +408,137 @@ static int pcicore_is_in_hostmode(struct
1294 }
1295 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
1296
1297 +/**************************************************
1298 + * Workarounds.
1299 + **************************************************/
1300 +
1301 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
1302 +{
1303 + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
1304 + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
1305 + tmp &= ~0xF000;
1306 + tmp |= (pc->dev->core_index << 12);
1307 + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
1308 + }
1309 +}
1310 +
1311 +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
1312 +{
1313 + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
1314 +}
1315 +
1316 +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
1317 +{
1318 + const u8 serdes_pll_device = 0x1D;
1319 + const u8 serdes_rx_device = 0x1F;
1320 + u16 tmp;
1321 +
1322 + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
1323 + ssb_pcicore_polarity_workaround(pc));
1324 + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
1325 + if (tmp & 0x4000)
1326 + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
1327 +}
1328 +
1329 +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
1330 +{
1331 + struct ssb_device *pdev = pc->dev;
1332 + struct ssb_bus *bus = pdev->bus;
1333 + u32 tmp;
1334 +
1335 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1336 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
1337 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
1338 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1339 +
1340 + if (pdev->id.revision < 5) {
1341 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
1342 + tmp &= ~SSB_IMCFGLO_SERTO;
1343 + tmp |= 2;
1344 + tmp &= ~SSB_IMCFGLO_REQTO;
1345 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
1346 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
1347 + ssb_commit_settings(bus);
1348 + } else if (pdev->id.revision >= 11) {
1349 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1350 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
1351 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1352 + }
1353 +}
1354 +
1355 +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
1356 +{
1357 + u32 tmp;
1358 + u8 rev = pc->dev->id.revision;
1359 +
1360 + if (rev == 0 || rev == 1) {
1361 + /* TLP Workaround register. */
1362 + tmp = ssb_pcie_read(pc, 0x4);
1363 + tmp |= 0x8;
1364 + ssb_pcie_write(pc, 0x4, tmp);
1365 + }
1366 + if (rev == 1) {
1367 + /* DLLP Link Control register. */
1368 + tmp = ssb_pcie_read(pc, 0x100);
1369 + tmp |= 0x40;
1370 + ssb_pcie_write(pc, 0x100, tmp);
1371 + }
1372 +
1373 + if (rev == 0) {
1374 + const u8 serdes_rx_device = 0x1F;
1375 +
1376 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1377 + 2 /* Timer */, 0x8128);
1378 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1379 + 6 /* CDR */, 0x0100);
1380 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1381 + 7 /* CDR BW */, 0x1466);
1382 + } else if (rev == 3 || rev == 4 || rev == 5) {
1383 + /* TODO: DLLP Power Management Threshold */
1384 + ssb_pcicore_serdes_workaround(pc);
1385 + /* TODO: ASPM */
1386 + } else if (rev == 7) {
1387 + /* TODO: No PLL down */
1388 + }
1389 +
1390 + if (rev >= 6) {
1391 + /* Miscellaneous Configuration Fixup */
1392 + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
1393 + if (!(tmp & 0x8000))
1394 + pcicore_write16(pc, SSB_PCICORE_SPROM(5),
1395 + tmp | 0x8000);
1396 + }
1397 +}
1398
1399 /**************************************************
1400 * Generic and Clientmode operation code.
1401 **************************************************/
1402
1403 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
1404 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
1405 {
1406 + struct ssb_device *pdev = pc->dev;
1407 + struct ssb_bus *bus = pdev->bus;
1408 +
1409 + if (bus->bustype == SSB_BUSTYPE_PCI)
1410 + ssb_pcicore_fix_sprom_core_index(pc);
1411 +
1412 /* Disable PCI interrupts. */
1413 - ssb_write32(pc->dev, SSB_INTVEC, 0);
1414 + ssb_write32(pdev, SSB_INTVEC, 0);
1415 +
1416 + /* Additional PCIe always once-executed workarounds */
1417 + if (pc->dev->id.coreid == SSB_DEV_PCIE) {
1418 + ssb_pcicore_serdes_workaround(pc);
1419 + /* TODO: ASPM */
1420 + /* TODO: Clock Request Update */
1421 + }
1422 }
1423
1424 -void ssb_pcicore_init(struct ssb_pcicore *pc)
1425 +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
1426 {
1427 struct ssb_device *dev = pc->dev;
1428 - struct ssb_bus *bus;
1429
1430 if (!dev)
1431 return;
1432 - bus = dev->bus;
1433 if (!ssb_device_is_enabled(dev))
1434 ssb_device_enable(dev, 0);
1435
1436 @@ -446,11 +563,35 @@ static void ssb_pcie_write(struct ssb_pc
1437 pcicore_write32(pc, 0x134, data);
1438 }
1439
1440 -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1441 - u8 address, u16 data)
1442 +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
1443 +{
1444 + const u16 mdio_control = 0x128;
1445 + const u16 mdio_data = 0x12C;
1446 + u32 v;
1447 + int i;
1448 +
1449 + v = (1 << 30); /* Start of Transaction */
1450 + v |= (1 << 28); /* Write Transaction */
1451 + v |= (1 << 17); /* Turnaround */
1452 + v |= (0x1F << 18);
1453 + v |= (phy << 4);
1454 + pcicore_write32(pc, mdio_data, v);
1455 +
1456 + udelay(10);
1457 + for (i = 0; i < 200; i++) {
1458 + v = pcicore_read32(pc, mdio_control);
1459 + if (v & 0x100 /* Trans complete */)
1460 + break;
1461 + msleep(1);
1462 + }
1463 +}
1464 +
1465 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
1466 {
1467 const u16 mdio_control = 0x128;
1468 const u16 mdio_data = 0x12C;
1469 + int max_retries = 10;
1470 + u16 ret = 0;
1471 u32 v;
1472 int i;
1473
1474 @@ -458,46 +599,68 @@ static void ssb_pcie_mdio_write(struct s
1475 v |= 0x2; /* MDIO Clock Divisor */
1476 pcicore_write32(pc, mdio_control, v);
1477
1478 + if (pc->dev->id.revision >= 10) {
1479 + max_retries = 200;
1480 + ssb_pcie_mdio_set_phy(pc, device);
1481 + }
1482 +
1483 v = (1 << 30); /* Start of Transaction */
1484 - v |= (1 << 28); /* Write Transaction */
1485 + v |= (1 << 29); /* Read Transaction */
1486 v |= (1 << 17); /* Turnaround */
1487 - v |= (u32)device << 22;
1488 + if (pc->dev->id.revision < 10)
1489 + v |= (u32)device << 22;
1490 v |= (u32)address << 18;
1491 - v |= data;
1492 pcicore_write32(pc, mdio_data, v);
1493 /* Wait for the device to complete the transaction */
1494 udelay(10);
1495 - for (i = 0; i < 10; i++) {
1496 + for (i = 0; i < max_retries; i++) {
1497 v = pcicore_read32(pc, mdio_control);
1498 - if (v & 0x100 /* Trans complete */)
1499 + if (v & 0x100 /* Trans complete */) {
1500 + udelay(10);
1501 + ret = pcicore_read32(pc, mdio_data);
1502 break;
1503 + }
1504 msleep(1);
1505 }
1506 pcicore_write32(pc, mdio_control, 0);
1507 + return ret;
1508 }
1509
1510 -static void ssb_broadcast_value(struct ssb_device *dev,
1511 - u32 address, u32 data)
1512 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1513 + u8 address, u16 data)
1514 {
1515 - /* This is used for both, PCI and ChipCommon core, so be careful. */
1516 - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1517 - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1518 + const u16 mdio_control = 0x128;
1519 + const u16 mdio_data = 0x12C;
1520 + int max_retries = 10;
1521 + u32 v;
1522 + int i;
1523
1524 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
1525 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
1526 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
1527 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
1528 -}
1529 + v = 0x80; /* Enable Preamble Sequence */
1530 + v |= 0x2; /* MDIO Clock Divisor */
1531 + pcicore_write32(pc, mdio_control, v);
1532
1533 -static void ssb_commit_settings(struct ssb_bus *bus)
1534 -{
1535 - struct ssb_device *dev;
1536 + if (pc->dev->id.revision >= 10) {
1537 + max_retries = 200;
1538 + ssb_pcie_mdio_set_phy(pc, device);
1539 + }
1540
1541 - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1542 - if (WARN_ON(!dev))
1543 - return;
1544 - /* This forces an update of the cached registers. */
1545 - ssb_broadcast_value(dev, 0xFD8, 0);
1546 + v = (1 << 30); /* Start of Transaction */
1547 + v |= (1 << 28); /* Write Transaction */
1548 + v |= (1 << 17); /* Turnaround */
1549 + if (pc->dev->id.revision < 10)
1550 + v |= (u32)device << 22;
1551 + v |= (u32)address << 18;
1552 + v |= data;
1553 + pcicore_write32(pc, mdio_data, v);
1554 + /* Wait for the device to complete the transaction */
1555 + udelay(10);
1556 + for (i = 0; i < max_retries; i++) {
1557 + v = pcicore_read32(pc, mdio_control);
1558 + if (v & 0x100 /* Trans complete */)
1559 + break;
1560 + msleep(1);
1561 + }
1562 + pcicore_write32(pc, mdio_control, 0);
1563 }
1564
1565 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
1566 @@ -550,48 +713,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc
1567 if (pc->setup_done)
1568 goto out;
1569 if (pdev->id.coreid == SSB_DEV_PCI) {
1570 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1571 - tmp |= SSB_PCICORE_SBTOPCI_PREF;
1572 - tmp |= SSB_PCICORE_SBTOPCI_BURST;
1573 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1574 -
1575 - if (pdev->id.revision < 5) {
1576 - tmp = ssb_read32(pdev, SSB_IMCFGLO);
1577 - tmp &= ~SSB_IMCFGLO_SERTO;
1578 - tmp |= 2;
1579 - tmp &= ~SSB_IMCFGLO_REQTO;
1580 - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
1581 - ssb_write32(pdev, SSB_IMCFGLO, tmp);
1582 - ssb_commit_settings(bus);
1583 - } else if (pdev->id.revision >= 11) {
1584 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1585 - tmp |= SSB_PCICORE_SBTOPCI_MRM;
1586 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1587 - }
1588 + ssb_pcicore_pci_setup_workarounds(pc);
1589 } else {
1590 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
1591 - //TODO: Better make defines for all these magic PCIE values.
1592 - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
1593 - /* TLP Workaround register. */
1594 - tmp = ssb_pcie_read(pc, 0x4);
1595 - tmp |= 0x8;
1596 - ssb_pcie_write(pc, 0x4, tmp);
1597 - }
1598 - if (pdev->id.revision == 0) {
1599 - const u8 serdes_rx_device = 0x1F;
1600 -
1601 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1602 - 2 /* Timer */, 0x8128);
1603 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1604 - 6 /* CDR */, 0x0100);
1605 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1606 - 7 /* CDR BW */, 0x1466);
1607 - } else if (pdev->id.revision == 1) {
1608 - /* DLLP Link Control register. */
1609 - tmp = ssb_pcie_read(pc, 0x100);
1610 - tmp |= 0x40;
1611 - ssb_pcie_write(pc, 0x100, tmp);
1612 - }
1613 + ssb_pcicore_pcie_setup_workarounds(pc);
1614 }
1615 pc->setup_done = 1;
1616 out:
1617 --- a/drivers/ssb/sprom.c
1618 +++ b/drivers/ssb/sprom.c
1619 @@ -2,7 +2,7 @@
1620 * Sonics Silicon Backplane
1621 * Common SPROM support routines
1622 *
1623 - * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de>
1624 + * Copyright (C) 2005-2008 Michael Buesch <m@bues.ch>
1625 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
1626 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
1627 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
1628 @@ -17,7 +17,7 @@
1629 #include <linux/slab.h>
1630
1631
1632 -static const struct ssb_sprom *fallback_sprom;
1633 +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
1634
1635
1636 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
1637 @@ -145,36 +145,43 @@ out:
1638 }
1639
1640 /**
1641 - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
1642 + * ssb_arch_register_fallback_sprom - Registers a method providing a
1643 + * fallback SPROM if no SPROM is found.
1644 *
1645 - * @sprom: The SPROM data structure to register.
1646 + * @sprom_callback: The callback function.
1647 *
1648 - * With this function the architecture implementation may register a fallback
1649 - * SPROM data structure. The fallback is only used for PCI based SSB devices,
1650 - * where no valid SPROM can be found in the shadow registers.
1651 + * With this function the architecture implementation may register a
1652 + * callback handler which fills the SPROM data structure. The fallback is
1653 + * only used for PCI based SSB devices, where no valid SPROM can be found
1654 + * in the shadow registers.
1655 + *
1656 + * This function is useful for weird architectures that have a half-assed
1657 + * SSB device hardwired to their PCI bus.
1658 + *
1659 + * Note that it does only work with PCI attached SSB devices. PCMCIA
1660 + * devices currently don't use this fallback.
1661 + * Architectures must provide the SPROM for native SSB devices anyway, so
1662 + * the fallback also isn't used for native devices.
1663 *
1664 - * This function is useful for weird architectures that have a half-assed SSB device
1665 - * hardwired to their PCI bus.
1666 - *
1667 - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
1668 - * don't use this fallback.
1669 - * Architectures must provide the SPROM for native SSB devices anyway,
1670 - * so the fallback also isn't used for native devices.
1671 - *
1672 - * This function is available for architecture code, only. So it is not exported.
1673 + * This function is available for architecture code, only. So it is not
1674 + * exported.
1675 */
1676 -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
1677 +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
1678 + struct ssb_sprom *out))
1679 {
1680 - if (fallback_sprom)
1681 + if (get_fallback_sprom)
1682 return -EEXIST;
1683 - fallback_sprom = sprom;
1684 + get_fallback_sprom = sprom_callback;
1685
1686 return 0;
1687 }
1688
1689 -const struct ssb_sprom *ssb_get_fallback_sprom(void)
1690 +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
1691 {
1692 - return fallback_sprom;
1693 + if (!get_fallback_sprom)
1694 + return -ENOENT;
1695 +
1696 + return get_fallback_sprom(bus, out);
1697 }
1698
1699 /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
1700 @@ -185,7 +192,7 @@ bool ssb_is_sprom_available(struct ssb_b
1701 /* this routine differs from specs as we do not access SPROM directly
1702 on PCMCIA */
1703 if (bus->bustype == SSB_BUSTYPE_PCI &&
1704 - bus->chipco.dev && /* can be unavailible! */
1705 + bus->chipco.dev && /* can be unavailable! */
1706 bus->chipco.dev->id.revision >= 31)
1707 return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
1708
1709 --- a/drivers/ssb/ssb_private.h
1710 +++ b/drivers/ssb/ssb_private.h
1711 @@ -171,7 +171,8 @@ ssize_t ssb_attr_sprom_store(struct ssb_
1712 const char *buf, size_t count,
1713 int (*sprom_check_crc)(const u16 *sprom, size_t size),
1714 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
1715 -extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
1716 +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
1717 + struct ssb_sprom *out);
1718
1719
1720 /* core.c */
1721 --- a/include/linux/ssb/ssb_driver_chipcommon.h
1722 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
1723 @@ -8,7 +8,7 @@
1724 * gpio interface, extbus, and support for serial and parallel flashes.
1725 *
1726 * Copyright 2005, Broadcom Corporation
1727 - * Copyright 2006, Michael Buesch <mb@bu3sch.de>
1728 + * Copyright 2006, Michael Buesch <m@bues.ch>
1729 *
1730 * Licensed under the GPL version 2. See COPYING for details.
1731 */
1732 @@ -123,6 +123,8 @@
1733 #define SSB_CHIPCO_FLASHDATA 0x0048
1734 #define SSB_CHIPCO_BCAST_ADDR 0x0050
1735 #define SSB_CHIPCO_BCAST_DATA 0x0054
1736 +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
1737 +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
1738 #define SSB_CHIPCO_GPIOIN 0x0060
1739 #define SSB_CHIPCO_GPIOOUT 0x0064
1740 #define SSB_CHIPCO_GPIOOUTEN 0x0068
1741 @@ -131,6 +133,9 @@
1742 #define SSB_CHIPCO_GPIOIRQ 0x0074
1743 #define SSB_CHIPCO_WATCHDOG 0x0080
1744 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
1745 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
1746 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
1747 +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
1748 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
1749 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
1750 #define SSB_CHIPCO_CLOCK_N 0x0090
1751 @@ -189,8 +194,10 @@
1752 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
1753 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
1754 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
1755 -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
1756 -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
1757 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
1758 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
1759 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
1760 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
1761 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
1762 #define SSB_CHIPCO_UART0_DATA 0x0300
1763 #define SSB_CHIPCO_UART0_IMR 0x0304
1764 --- a/drivers/ssb/b43_pci_bridge.c
1765 +++ b/drivers/ssb/b43_pci_bridge.c
1766 @@ -5,12 +5,13 @@
1767 * because of its small size we include it in the SSB core
1768 * instead of creating a standalone module.
1769 *
1770 - * Copyright 2007 Michael Buesch <mb@bu3sch.de>
1771 + * Copyright 2007 Michael Buesch <m@bues.ch>
1772 *
1773 * Licensed under the GNU/GPL. See COPYING for details.
1774 */
1775
1776 #include <linux/pci.h>
1777 +#include <linux/module.h>
1778 #include <linux/ssb/ssb.h>
1779
1780 #include "ssb_private.h"
1781 --- a/drivers/ssb/driver_extif.c
1782 +++ b/drivers/ssb/driver_extif.c
1783 @@ -3,7 +3,7 @@
1784 * Broadcom EXTIF core driver
1785 *
1786 * Copyright 2005, Broadcom Corporation
1787 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1788 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1789 * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
1790 * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net>
1791 *
1792 --- a/drivers/ssb/driver_mipscore.c
1793 +++ b/drivers/ssb/driver_mipscore.c
1794 @@ -3,7 +3,7 @@
1795 * Broadcom MIPS core driver
1796 *
1797 * Copyright 2005, Broadcom Corporation
1798 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1799 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1800 *
1801 * Licensed under the GNU/GPL. See COPYING for details.
1802 */
1803 --- a/drivers/ssb/embedded.c
1804 +++ b/drivers/ssb/embedded.c
1805 @@ -3,7 +3,7 @@
1806 * Embedded systems support code
1807 *
1808 * Copyright 2005-2008, Broadcom Corporation
1809 - * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
1810 + * Copyright 2006-2008, Michael Buesch <m@bues.ch>
1811 *
1812 * Licensed under the GNU/GPL. See COPYING for details.
1813 */
1814 --- a/drivers/ssb/pcmcia.c
1815 +++ b/drivers/ssb/pcmcia.c
1816 @@ -3,7 +3,7 @@
1817 * PCMCIA-Hostbus related functions
1818 *
1819 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
1820 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
1821 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
1822 *
1823 * Licensed under the GNU/GPL. See COPYING for details.
1824 */
1825 --- a/drivers/ssb/sdio.c
1826 +++ b/drivers/ssb/sdio.c
1827 @@ -6,7 +6,7 @@
1828 *
1829 * Based on drivers/ssb/pcmcia.c
1830 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
1831 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
1832 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
1833 *
1834 * Licensed under the GNU/GPL. See COPYING for details.
1835 *
Personal OpenWRT clone
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