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ramips: refresh 2.6.34 patches
[openwrt.git] / target / linux / coldfire / patches / 080-mcfv4e_dspi_update.patch
1 From 771f4741de2cd8a103d96cd1e8281926448ff56d Mon Sep 17 00:00:00 2001
2 From: Kurt Mahan <kmahan@freescale.com>
3 Date: Tue, 15 Jul 2008 11:44:08 -0600
4 Subject: [PATCH] Fix DSPI driver.
5
6 Update to latest Matt Coldfire driver. Fix timing issues with
7 M547x/M548x END-OF-QUEUE notification.
8
9 LTIBName: mcfv4e-dspi-update
10 Signed-off-by: Kurt Mahan <kmahan@freescale.com>
11 ---
12 arch/m68k/coldfire/m547x_8x-devices.c | 35 +-
13 drivers/spi/Kconfig | 6 +
14 drivers/spi/Makefile | 2 +-
15 drivers/spi/dspi_mcf.c | 1217 +++++++++++++++++++++++++++++++++
16 include/asm-m68k/mcfdspi.h | 48 ++
17 5 files changed, 1296 insertions(+), 12 deletions(-)
18 create mode 100644 drivers/spi/dspi_mcf.c
19 create mode 100644 include/asm-m68k/mcfdspi.h
20
21 --- a/arch/m68k/coldfire/m547x_8x-devices.c
22 +++ b/arch/m68k/coldfire/m547x_8x-devices.c
23 @@ -26,26 +26,40 @@
24 */
25
26 /* number of supported SPI selects */
27 -#define SPI_NUM_CHIPSELECTS 4
28 +#define SPI_NUM_CHIPSELECTS 8
29
30 void coldfire_spi_cs_control(u8 cs, u8 command)
31 {
32 /* nothing special required */
33 }
34
35 +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
36 +static struct coldfire_spi_chip spidev_chip_info = {
37 + .bits_per_word = 8,
38 +};
39 +#endif
40 +
41 static struct spi_board_info spi_board_info[] = {
42 - /* no board info */
43 +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
44 + {
45 + .modalias = "spidev",
46 + .max_speed_hz = 16000000, /* max clk (SCK) speed in HZ */
47 + .bus_num = 1,
48 + .chip_select = 0, /* CS0 */
49 + .controller_data = &spidev_chip_info,
50 + }
51 +#endif
52 };
53
54 static int spi_irq_list[] = {
55 - /* IRQ, ICR Offset, ICR Val, Mask */
56 - 64 + ISC_DSPI_OVRFW, 0, 0, 0,
57 - 64 + ISC_DSPI_RFOF, 0, 0, 0,
58 - 64 + ISC_DSPI_RFDF, 0, 0, 0,
59 - 64 + ISC_DSPI_TFUF, 0, 0, 0,
60 - 64 + ISC_DSPI_TCF, 0, 0, 0,
61 - 64 + ISC_DSPI_TFFF, 0, 0, 0,
62 - 64 + ISC_DSPI_EOQF, 0, 0, 0,
63 + /* IRQ, ICR Offset, ICR Val,Mask */
64 + 64 + ISC_DSPI_OVRFW, ISC_DSPI_OVRFW, 0x18, 0,
65 + 64 + ISC_DSPI_RFOF, ISC_DSPI_RFOF, 0x18, 0,
66 + 64 + ISC_DSPI_RFDF, ISC_DSPI_RFDF, 0x18, 0,
67 + 64 + ISC_DSPI_TFUF, ISC_DSPI_TFUF, 0x18, 0,
68 + 64 + ISC_DSPI_TCF, ISC_DSPI_TCF, 0x18, 0,
69 + 64 + ISC_DSPI_TFFF, ISC_DSPI_TFFF, 0x18, 0,
70 + 64 + ISC_DSPI_EOQF, ISC_DSPI_EOQF, 0x18, 0,
71 0,0,0,0,
72 };
73
74 @@ -120,7 +134,6 @@ static int __init m547x_8x_spi_init(void
75 /* register device */
76 retval = platform_device_register(&coldfire_spi);
77 if (retval < 0) {
78 - printk(KERN_ERR "SPI-m547x_8x: platform_device_register failed with code=%d\n", retval);
79 goto out;
80 }
81
82 --- a/drivers/spi/Kconfig
83 +++ b/drivers/spi/Kconfig
84 @@ -130,6 +130,12 @@ config SPI_COLDFIRE
85 Tested with the 5282 processor, but should also work with other
86 Coldfire variants.
87
88 +config SPI_DSPI
89 + tristate "Coldfire DSPI"
90 + depends on SPI_MASTER && COLDFIRE
91 + help
92 + SPI driver for Coldfire DSPI driver only.
93 +
94 config SPI_COLDFIRE_DSPI_EDMA
95 boolean "Coldfire DSPI master driver uses eDMA"
96 depends on SPI_MASTER && COLDFIRE && SPI_COLDFIRE && EXPERIMENTAL && COLDFIRE_EDMA
97 --- a/drivers/spi/Makefile
98 +++ b/drivers/spi/Makefile
99 @@ -19,7 +19,7 @@ obj-$(CONFIG_SPI_BITBANG) += spi_bitban
100 obj-$(CONFIG_SPI_AU1550) += au1550_spi.o
101 obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
102 # obj-$(CONFIG_SPI_COLDFIRE) += spi_coldfire.o spi-m5445x.o
103 -obj-$(CONFIG_SPI_COLDFIRE) += spi_coldfire.o
104 +obj-$(CONFIG_SPI_DSPI) += dspi_mcf.o
105 obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
106 obj-$(CONFIG_SPI_IMX) += spi_imx.o
107 obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
108 --- /dev/null
109 +++ b/drivers/spi/dspi_mcf.c
110 @@ -0,0 +1,1217 @@
111 +/*
112 + * dspi_mcf.c - DSPI controller for ColdFire processors
113 + *
114 + *
115 + * Matt Waddel Matt.Waddel@freescale.com
116 + * Copyright Freescale Semiconductor, Inc. 2008
117 + *
118 + * M547x/M548x changes by Kurt Mahan kmahan@freescale.com
119 + * Copyright Freescale Semiconductor, Inc. 2008
120 + *
121 + * Based on spi_coldfire.c done by:
122 + * Andrey Butok
123 + * Yaroslav Vinogradov
124 + * Copyright Freescale Semiconductor, Inc. 2006-2007
125 + * Mike Lavender (mike@steroidmicros)
126 + * (C) Copyright 2005, Intec Automation,
127 + *
128 + * This program is free software; you can redistribute it and/or modify it
129 + * under the terms of the GNU General Public License as published by the
130 + * Free Software Foundation; either version 2 of the License, or (at your
131 + * option) any later version.
132 + *
133 + * This program is distributed in the hope that it will be useful,
134 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
135 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
136 + * GNU General Public License for more details.
137 + *
138 + * You should have received a copy of the GNU General Public License
139 + * along with this program; if not, write to the Free Software
140 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
141 + *
142 + ***************************************************************************
143 + * Changes:
144 + * v0.002 M547x/M548x support.
145 + * v0.001 Initial version. Coldfire DSPI master driver.
146 + ****************************************************************************/
147 +
148 +/*
149 + * Includes
150 + */
151 +
152 +#include <linux/autoconf.h>
153 +#include <linux/init.h>
154 +#include <linux/module.h>
155 +#include <linux/device.h>
156 +#include <linux/interrupt.h>
157 +#include <linux/platform_device.h>
158 +#include <linux/spi/spi.h>
159 +#include <linux/workqueue.h>
160 +#include <linux/delay.h>
161 +#include <asm/mcfsim.h>
162 +#include <asm/mcfqspi.h>
163 +#include <asm/coldfire.h>
164 +#include <linux/io.h>
165 +#include <asm/mcfdspi.h>
166 +#include <linux/dma-mapping.h>
167 +
168 +#undef DSPI_COLDFIRE_DEBUG
169 +
170 +#ifdef DSPI_COLDFIRE_DEBUG
171 +#define DBG(fmt, args...) \
172 + printk(KERN_INFO "[%s] " fmt , __FUNCTION__, ## args)
173 +#else
174 +#define DBG(fmt, args...) do {} while (0)
175 +#endif
176 +
177 +#if defined(CONFIG_M54455)
178 +#include <asm/mcf5445x_dspi.h>
179 +#if defined(CONFIG_SPI_COLDFIRE_DSPI_EDMA)
180 + #include <asm/mcf5445x_edma.h>
181 +#endif
182 +#endif
183 +
184 +#if defined(CONFIG_M547X_8X)
185 +#include <asm/virtconvert.h>
186 +#include <asm/m5485dspi.h>
187 +#endif
188 +
189 +#if defined(CONFIG_SPI_COLDFIRE_DSPI_EDMA)
190 +#include <asm/mcf_edma.h>
191 +#define SPI_DSPI_EDMA
192 +#define EDMA_BUFSIZE_KMALLOC (DSPI_FIFO_SIZE*4)
193 +#define DSPI_DMA_RX_TCD MCF_EDMA_CHAN_DSPI_RX
194 +#define DSPI_DMA_TX_TCD MCF_EDMA_CHAN_DSPI_TX
195 +#endif
196 +
197 +#define DSPI_BITS MCF_DSPI_DCTAR_FMSZ(0xF)
198 +#define DSPI_BITS_16 MCF_DSPI_DCTAR_FMSZ(0xF)
199 +#define DSPI_BITS_8 MCF_DSPI_DCTAR_FMSZ(0x7)
200 +#define DSPI_FIFO_SIZE 16
201 +
202 +#define DRIVER_NAME "Coldfire DSPI"
203 +
204 +/****************************************************************************/
205 +
206 +/*
207 + * Local constants and macros
208 + */
209 +
210 +#define START_STATE ((void *)0)
211 +#define RUNNING_STATE ((void *)1)
212 +#define DONE_STATE ((void *)2)
213 +#define ERROR_STATE ((void *)-1)
214 +
215 +#define QUEUE_RUNNING 0
216 +#define QUEUE_STOPPED 1
217 +
218 +/****************************************************************************/
219 +
220 +/*
221 + * Local Data Structures
222 + */
223 +
224 +struct DSPI_MCR {
225 + unsigned master:1;
226 + unsigned cont_scke:1;
227 + unsigned dconf:2;
228 + unsigned frz:1;
229 + unsigned mtfe:1;
230 + unsigned pcsse:1;
231 + unsigned rooe:1;
232 + unsigned pcsis:8;
233 + unsigned reserved15:1;
234 + unsigned mdis:1;
235 + unsigned dis_tx:1;
236 + unsigned dis_rxf:1;
237 + unsigned clr_tx:1;
238 + unsigned clr_rxf:1;
239 + unsigned smpl_pt:2;
240 + unsigned reserved71:7;
241 + unsigned halt:1;
242 +};
243 +
244 +struct DSPI_CTAR {
245 + unsigned dbr:1;
246 + unsigned fmsz:4;
247 + unsigned cpol:1;
248 + unsigned cpha:1;
249 + unsigned lsbfe:1;
250 + unsigned pcssck:2;
251 + unsigned pasc:2;
252 + unsigned pdt:2;
253 + unsigned pbr:2;
254 + unsigned cssck:4;
255 + unsigned asc:4;
256 + unsigned dt:4;
257 + unsigned br:4;
258 +};
259 +
260 +struct chip_data {
261 + /* dspi data */
262 + union {
263 + u32 mcr_val;
264 + struct DSPI_MCR mcr;
265 + };
266 + union {
267 + u32 ctar_val;
268 + struct DSPI_CTAR ctar;
269 + };
270 + u16 void_write_data;
271 +};
272 +
273 +
274 +struct driver_data {
275 + /* Driver model hookup */
276 + struct platform_device *pdev;
277 +
278 + /* SPI framework hookup */
279 + struct spi_master *master;
280 +
281 + /* Driver message queue */
282 + struct workqueue_struct *workqueue;
283 + struct work_struct pump_messages;
284 + spinlock_t lock; /* lock */
285 + struct list_head queue;
286 + int busy;
287 + int run;
288 +
289 + /* Message Transfer pump */
290 + struct tasklet_struct pump_transfers;
291 +
292 + /* Current message transfer state info */
293 + struct spi_message *cur_msg;
294 + struct spi_transfer *cur_transfer;
295 + struct chip_data *cur_chip;
296 + size_t len;
297 + void *tx;
298 + void *tx_end;
299 + void *rx;
300 + void *rx_end;
301 + char flags;
302 +#define TRAN_STATE_RX_VOID 0x01
303 +#define TRAN_STATE_TX_VOID 0x02
304 +#define TRAN_STATE_WORD_ODD_NUM 0x04
305 + u8 cs;
306 + u16 void_write_data;
307 + unsigned cs_change:1;
308 +
309 + u32 trans_cnt;
310 + u32 wce_cnt;
311 + u32 abrt_cnt;
312 + u32 *mcr; /* DSPI MCR register */
313 + u32 *ctar; /* DSPI CTAR register */
314 + u32 *dspi_dtfr; /* DSPI DTFR register */
315 + u32 *dspi_drfr; /* DSPI DRFR register */
316 + u32 *dspi_rser; /* DSPI RSER register */
317 + u32 *dspi_sr; /* DSPI status register */
318 +
319 +#if defined(SPI_DSPI_EDMA)
320 + void *edma_tx_buf;
321 + void *edma_rx_buf;
322 +#endif
323 +
324 +#if defined(CONFIG_M532x) || defined(CONFIG_M537x)
325 + u16 *par; /* Pin assignment register */
326 +#else
327 + u8 *par; /* Pin assignment register */
328 +#endif
329 + u8 *int_icr; /* Interrupt level and priority register */
330 + u32 *int_mr; /* Interrupt mask register */
331 + void (*cs_control)(u8 cs, u8 command);
332 +};
333 +
334 +#define DSPI_CS(cs) ((1<<(cs))<<16)
335 +
336 +/****************************************************************************/
337 +
338 +/*
339 + * SPI local functions
340 + */
341 +
342 +static void *next_transfer(struct driver_data *drv_data)
343 +{
344 + struct spi_message *msg = drv_data->cur_msg;
345 + struct spi_transfer *trans = drv_data->cur_transfer;
346 +
347 + DBG("\n");
348 + /* Move to next transfer */
349 + if (trans->transfer_list.next != &msg->transfers) {
350 + drv_data->cur_transfer = list_entry(trans->transfer_list.next,
351 + struct spi_transfer,
352 + transfer_list);
353 +
354 + if (drv_data->cur_transfer->transfer_list.next
355 + == &msg->transfers) /* last transfer */
356 + drv_data->cur_transfer->cs_change = 1;
357 +
358 + return RUNNING_STATE;
359 + } else
360 + return DONE_STATE;
361 +}
362 +
363 +
364 +static inline int is_word_transfer(struct driver_data *drv_data)
365 +{
366 + return ((*(drv_data->ctar+drv_data->cs) & DSPI_BITS_16) ==
367 + DSPI_BITS_8) ? 0 : 1;
368 +}
369 +
370 +static inline void set_8bit_transfer_mode(struct driver_data *drv_data)
371 +{
372 + DBG("\n");
373 + *(drv_data->ctar+drv_data->cs) =
374 + (*(drv_data->ctar + drv_data->cs) & ~DSPI_BITS) | DSPI_BITS_8;
375 +}
376 +
377 +static inline void set_16bit_transfer_mode(struct driver_data *drv_data)
378 +{
379 + DBG("\n");
380 + *(drv_data->ctar+drv_data->cs) =
381 + (*(drv_data->ctar + drv_data->cs) & ~DSPI_BITS) | DSPI_BITS_16;
382 +}
383 +
384 +static unsigned char hz_to_spi_baud(int pbr, int dbr, int speed_hz)
385 +{
386 + int pbr_tbl[4] = {2, 3, 5, 7}; /* Valid baud rate pre-scaler values */
387 + int brs[16] = { 2, 4, 6, 8,
388 + 16, 32, 64, 128,
389 + 256, 512, 1024, 2048,
390 + 4096, 8192, 16384, 32768 };
391 + int temp, index = 0;
392 +
393 + if ((pbr < 0) || (pbr > 3) ||
394 + (dbr < 0) || (dbr > 1))
395 + return 15; /* table indexes out of range, go slow */
396 +
397 + temp = ((((MCF_CLK / 2) / pbr_tbl[pbr]) * (1 + dbr)) / speed_hz);
398 +
399 + while (temp >= brs[index])
400 + if (index++ >= 15)
401 + break;
402 +
403 + DBG("baud rate scaler = 0x%x - %d\n", index, brs[index]);
404 + return(index);
405 +}
406 +
407 +static int write(struct driver_data *drv_data)
408 +{
409 + int tx_count = 0;
410 + int tx_word = is_word_transfer(drv_data);
411 + u16 d16;
412 + u8 d8;
413 + u32 dspi_pushr = 0;
414 + int first = 1;
415 +#if defined(SPI_DSPI_EDMA)
416 + u32 *edma_wr = (u32 *)(drv_data->edma_tx_buf);
417 +#endif
418 +
419 + /* If we are in word mode, but only have a single byte to transfer
420 + * then switch to byte mode temporarily. Will switch back at the
421 + * end of the transfer. */
422 + if (tx_word && ((drv_data->tx_end - drv_data->tx) == 1)) {
423 + drv_data->flags |= TRAN_STATE_WORD_ODD_NUM;
424 + set_8bit_transfer_mode(drv_data);
425 + tx_word = 0;
426 + }
427 +
428 + while ((drv_data->tx < drv_data->tx_end) && (tx_count < DSPI_FIFO_SIZE)) {
429 +// DBG("while\n");
430 + if (tx_word) {
431 + if ((drv_data->tx_end - drv_data->tx) == 1)
432 + break;
433 +
434 + if (!(drv_data->flags & TRAN_STATE_TX_VOID))
435 + d16 = *(u16 *)drv_data->tx;
436 + else
437 + d16 = drv_data->void_write_data;
438 +
439 + dspi_pushr = MCF_DSPI_DTFR_TXDATA(d16) |
440 + DSPI_CS(drv_data->cs) |
441 + MCF_DSPI_DTFR_CTAS(drv_data->cs) |
442 + MCF_DSPI_DTFR_CONT;
443 +
444 + drv_data->tx += 2;
445 + } else {
446 + if (!(drv_data->flags & TRAN_STATE_TX_VOID))
447 + d8 = *(u8 *)drv_data->tx;
448 + else
449 + d8 = *(u8 *)&drv_data->void_write_data;
450 +
451 + dspi_pushr = MCF_DSPI_DTFR_TXDATA(d8) |
452 + DSPI_CS(drv_data->cs) |
453 + MCF_DSPI_DTFR_CTAS(drv_data->cs) |
454 + MCF_DSPI_DTFR_CONT;
455 +
456 + drv_data->tx++;
457 + }
458 +
459 + if (drv_data->tx == drv_data->tx_end
460 + || tx_count == DSPI_FIFO_SIZE-1) {
461 + /* last transfer in the queue */
462 + dspi_pushr |= MCF_DSPI_DTFR_EOQ;
463 + if ((drv_data->cs_change)
464 + && (drv_data->tx == drv_data->tx_end))
465 + dspi_pushr &= ~MCF_DSPI_DTFR_CONT;
466 +#ifdef CONFIG_M547X_8X
467 + /* EOQ gets missed if we don't delay */
468 + udelay(100);
469 +#endif
470 + } else if (tx_word && ((drv_data->tx_end - drv_data->tx) == 1))
471 + dspi_pushr |= MCF_DSPI_DTFR_EOQ;
472 +
473 + if (first) {
474 + first = 0;
475 + dspi_pushr |= MCF_DSPI_DTFR_CTCNT; /* clear counter */
476 + }
477 +#if defined(SPI_DSPI_EDMA)
478 + *edma_wr = dspi_pushr;
479 + edma_wr++;
480 +#else
481 + *drv_data->dspi_dtfr = dspi_pushr;
482 +#endif
483 + tx_count++;
484 + }
485 +
486 +#if defined(SPI_DSPI_EDMA)
487 + if (tx_count > 0) {
488 +
489 + mcf_edma_set_tcd_params(DSPI_DMA_TX_TCD,
490 + virt_to_phys(drv_data->edma_tx_buf),
491 + (u32)drv_data->dspi_dtfr,
492 + MCF_EDMA_TCD_ATTR_SSIZE_32BIT
493 + | MCF_EDMA_TCD_ATTR_DSIZE_32BIT,
494 + 4, /* soff */
495 + 4 * tx_count, /* nbytes */
496 + 0, /* slast */
497 + 1, /* citer */
498 + 1, /* biter */
499 + 0, /* doff */
500 + 0, /* dlastsga */
501 + 0, /* major_int */
502 + 1); /* disable_req */
503 +
504 + mcf_edma_set_tcd_params(DSPI_DMA_RX_TCD,
505 + (u32)drv_data->dspi_drfr,
506 + virt_to_phys(drv_data->edma_rx_buf),
507 + MCF_EDMA_TCD_ATTR_SSIZE_32BIT
508 + | MCF_EDMA_TCD_ATTR_DSIZE_32BIT,
509 + 0, /* soff */
510 + 4 * tx_count, /* nbytes */
511 + 0, /* slast */
512 + 1, /* citer */
513 + 1, /* biter */
514 + 4, /* doff */
515 + 0, /* dlastsga */
516 + 0, /* major_int */
517 + 1); /* disable_req */
518 +
519 + mcf_edma_start_transfer(DSPI_DMA_TX_TCD);
520 + }
521 +#endif
522 + return (tx_count * (tx_word + 1));
523 +}
524 +
525 +static int read(struct driver_data *drv_data)
526 +{
527 + int rx_count = 0;
528 + int rx_word = is_word_transfer(drv_data);
529 + u16 d;
530 +#if defined(SPI_DSPI_EDMA)
531 + u32 *rx_edma = (u32 *) drv_data->edma_rx_buf;
532 +
533 + /* receive SPI data */
534 + mcf_edma_start_transfer(DSPI_DMA_RX_TCD);
535 +#endif
536 + while ((drv_data->rx < drv_data->rx_end)
537 + && (rx_count < DSPI_FIFO_SIZE)) {
538 +
539 + if (rx_word) {
540 + if ((drv_data->rx_end - drv_data->rx) == 1)
541 + break;
542 +#if defined(SPI_DSPI_EDMA)
543 + d = MCF_DSPI_DRFR_RXDATA(*rx_edma);
544 + rx_edma++;
545 +#else
546 + d = MCF_DSPI_DRFR_RXDATA(*drv_data->dspi_drfr);
547 +#endif
548 + if (!(drv_data->flags & TRAN_STATE_RX_VOID))
549 + *(u16 *)drv_data->rx = d;
550 + drv_data->rx += 2;
551 +
552 + } else {
553 +#if defined(SPI_DSPI_EDMA)
554 + d = MCF_DSPI_DRFR_RXDATA(*rx_edma);
555 + rx_edma++;
556 +#else
557 + d = MCF_DSPI_DRFR_RXDATA(*drv_data->dspi_drfr);
558 +#endif
559 + if (!(drv_data->flags & TRAN_STATE_RX_VOID))
560 + *(u8 *)drv_data->rx = d;
561 + drv_data->rx++;
562 + }
563 + rx_count++;
564 + DBG("rxd=0x%x\n", d);
565 + }
566 + return rx_count;
567 +}
568 +
569 +
570 +static inline void dspi_setup_chip(struct driver_data *drv_data)
571 +{
572 + struct chip_data *chip = drv_data->cur_chip;
573 +
574 + DBG("\n");
575 + *drv_data->mcr = chip->mcr_val;
576 + *(drv_data->ctar+drv_data->cs) = chip->ctar_val;
577 + *drv_data->dspi_rser = MCF_DSPI_DRSER_EOQFE;
578 +}
579 +
580 +#if defined(SPI_DSPI_EDMA)
581 +static int edma_tx_handler(int channel, void *dev)
582 +{
583 + DBG("\n");
584 + if (channel == DSPI_DMA_TX_TCD)
585 + mcf_edma_stop_transfer(DSPI_DMA_TX_TCD);
586 + return IRQ_HANDLED;
587 +}
588 +
589 +static int edma_rx_handler(int channel, void *dev)
590 +{
591 + DBG("\n");
592 + if (channel == DSPI_DMA_RX_TCD)
593 + mcf_edma_stop_transfer(DSPI_DMA_RX_TCD);
594 + return IRQ_HANDLED;
595 +}
596 +#endif
597 +
598 +static irqreturn_t dspi_interrupt(int irq, void *dev_id)
599 +{
600 + struct driver_data *drv_data = (struct driver_data *)dev_id;
601 + struct spi_message *msg = drv_data->cur_msg;
602 +
603 + /* Clear all flags immediately */
604 + *drv_data->dspi_sr = MCF_DSPI_DSR_EOQF;
605 +
606 + if (!drv_data->cur_msg || !drv_data->cur_msg->state) {
607 +#if !defined(SPI_DSPI_EDMA)
608 + u32 irq_status = *drv_data->dspi_sr;
609 + /* if eDMA is used it happens some time (at least once)*/
610 + printk(KERN_ERR "Bad message or transfer state handler. \
611 + IRQ status = %x\n", irq_status);
612 +#endif
613 + return IRQ_NONE;
614 + }
615 +
616 + DBG("\n");
617 + /*
618 + * Read the data into the buffer and reload and start
619 + * queue with new data if not finished. If finished
620 + * then setup the next transfer
621 + */
622 + read(drv_data);
623 +
624 + if (drv_data->rx == drv_data->rx_end) {
625 + /*
626 + * Finished now - fall through and schedule next
627 + * transfer tasklet
628 + */
629 + if (drv_data->flags & TRAN_STATE_WORD_ODD_NUM)
630 + set_16bit_transfer_mode(drv_data);
631 +
632 + msg->state = next_transfer(drv_data);
633 + } else {
634 + /* not finished yet - keep going */
635 + msg->actual_length += write(drv_data);
636 + return IRQ_HANDLED;
637 + }
638 +
639 + tasklet_schedule(&drv_data->pump_transfers);
640 +
641 + return IRQ_HANDLED;
642 +}
643 +
644 +/* caller already set message->status; dma and pio irqs are blocked */
645 +static void giveback(struct driver_data *drv_data)
646 +{
647 + struct spi_transfer *last_transfer;
648 + unsigned long flags;
649 + struct spi_message *msg;
650 + DBG("\n");
651 +
652 + spin_lock_irqsave(&drv_data->lock, flags);
653 + msg = drv_data->cur_msg;
654 + drv_data->cur_msg = NULL;
655 + drv_data->cur_transfer = NULL;
656 + drv_data->cur_chip = NULL;
657 + queue_work(drv_data->workqueue, &drv_data->pump_messages);
658 + spin_unlock_irqrestore(&drv_data->lock, flags);
659 +
660 + last_transfer = list_entry(msg->transfers.prev,
661 + struct spi_transfer, transfer_list);
662 +
663 + if (!last_transfer->cs_change)
664 + drv_data->cs_control(drv_data->cs, QSPI_CS_DROP);
665 +
666 + msg->state = NULL;
667 + if (msg->complete)
668 + msg->complete(msg->context);
669 +}
670 +
671 +
672 +static void pump_transfers(unsigned long data)
673 +{
674 + struct driver_data *drv_data = (struct driver_data *)data;
675 + struct spi_message *message = NULL;
676 + struct spi_transfer *transfer = NULL;
677 + struct spi_transfer *previous = NULL;
678 + struct chip_data *chip = NULL;
679 + unsigned long flags;
680 + DBG("\n");
681 + /* Get current state information */
682 + message = drv_data->cur_msg;
683 + transfer = drv_data->cur_transfer;
684 + chip = drv_data->cur_chip;
685 +
686 + /* Handle for abort */
687 + if (message->state == ERROR_STATE) {
688 + message->status = -EIO;
689 + giveback(drv_data);
690 + return;
691 + }
692 +
693 + /* Handle end of message */
694 + if (message->state == DONE_STATE) {
695 + message->status = 0;
696 + giveback(drv_data);
697 + return;
698 + }
699 +
700 + if (message->state == START_STATE) {
701 + dspi_setup_chip(drv_data);
702 +
703 + if (drv_data->cs_control)
704 + drv_data->cs_control(message->spi->chip_select,
705 + QSPI_CS_ASSERT);
706 + }
707 +
708 + /* Delay if requested at end of transfer*/
709 + if (message->state == RUNNING_STATE) {
710 + previous = list_entry(transfer->transfer_list.prev,
711 + struct spi_transfer,
712 + transfer_list);
713 +
714 + if (drv_data->cs_control && transfer->cs_change)
715 + drv_data->cs_control(message->spi->chip_select,
716 + QSPI_CS_DROP);
717 +
718 + if (previous->delay_usecs)
719 + udelay(previous->delay_usecs);
720 +
721 + if (drv_data->cs_control && transfer->cs_change)
722 + drv_data->cs_control(message->spi->chip_select,
723 + QSPI_CS_ASSERT);
724 + }
725 +
726 + drv_data->flags = 0;
727 + drv_data->tx = (void *)transfer->tx_buf;
728 + drv_data->tx_end = drv_data->tx + transfer->len;
729 + drv_data->rx = transfer->rx_buf;
730 + drv_data->rx_end = drv_data->rx + transfer->len;
731 +
732 + if (!drv_data->rx)
733 + drv_data->flags |= TRAN_STATE_RX_VOID;
734 + if (!drv_data->tx)
735 + drv_data->flags |= TRAN_STATE_TX_VOID;
736 + drv_data->cs = message->spi->chip_select;
737 + drv_data->cs_change = transfer->cs_change;
738 + drv_data->void_write_data = chip->void_write_data;
739 + if (transfer->speed_hz) {
740 + *(drv_data->ctar + drv_data->cs) = \
741 + ((chip->ctar_val & ~0xF) | \
742 + hz_to_spi_baud(chip->ctar.pbr, \
743 + chip->ctar.dbr, \
744 + transfer->speed_hz));
745 + }
746 +
747 + message->state = RUNNING_STATE;
748 + /* Go baby, go */
749 + local_irq_save(flags);
750 + message->actual_length += write(drv_data);
751 + local_irq_restore(flags);
752 +}
753 +
754 +
755 +static void pump_messages(struct work_struct *work)
756 +{
757 + struct driver_data *drv_data;
758 + unsigned long flags;
759 + DBG("\n");
760 +
761 + drv_data = container_of(work, struct driver_data, pump_messages);
762 +
763 + /* Lock queue and check for queue work */
764 + spin_lock_irqsave(&drv_data->lock, flags);
765 + if (list_empty(&drv_data->queue)
766 + || drv_data->run == QUEUE_STOPPED) {
767 + drv_data->busy = 0;
768 + spin_unlock_irqrestore(&drv_data->lock, flags);
769 + return;
770 + }
771 +
772 + /* Make sure we are not already running a message */
773 + if (drv_data->cur_msg) {
774 + spin_unlock_irqrestore(&drv_data->lock, flags);
775 + return;
776 + }
777 +
778 + /* Extract head of queue */
779 + drv_data->cur_msg = list_entry(drv_data->queue.next,
780 + struct spi_message, queue);
781 + list_del_init(&drv_data->cur_msg->queue);
782 +
783 + /* Initial message state*/
784 + drv_data->cur_msg->state = START_STATE;
785 + drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
786 + struct spi_transfer,
787 + transfer_list);
788 +
789 + if (drv_data->cur_transfer->transfer_list.next
790 + == &drv_data->cur_msg->transfers)
791 + drv_data->cur_transfer->cs_change = 1; /* last */
792 +
793 +
794 + /* Setup the SPI Registers using the per chip configuration */
795 + drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
796 +
797 + /* Mark as busy and launch transfers */
798 + tasklet_schedule(&drv_data->pump_transfers);
799 +
800 + drv_data->busy = 1;
801 + spin_unlock_irqrestore(&drv_data->lock, flags);
802 +}
803 +
804 +/****************************************************************************/
805 +
806 +/*
807 + * SPI master implementation
808 + */
809 +
810 +static int transfer(struct spi_device *spi, struct spi_message *msg)
811 +{
812 + struct driver_data *drv_data = spi_master_get_devdata(spi->master);
813 + unsigned long flags;
814 +
815 + DBG("\n");
816 + spin_lock_irqsave(&drv_data->lock, flags);
817 +
818 + if (drv_data->run == QUEUE_STOPPED) {
819 + spin_unlock_irqrestore(&drv_data->lock, flags);
820 + return -ESHUTDOWN;
821 + }
822 +
823 + msg->actual_length = 0;
824 + msg->status = -EINPROGRESS;
825 + msg->state = START_STATE;
826 +
827 + list_add_tail(&msg->queue, &drv_data->queue);
828 +
829 + if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
830 + queue_work(drv_data->workqueue, &drv_data->pump_messages);
831 +
832 + spin_unlock_irqrestore(&drv_data->lock, flags);
833 +
834 + return 0;
835 +}
836 +
837 +
838 +static int setup(struct spi_device *spi)
839 +{
840 +
841 + struct chip_data *chip;
842 + struct coldfire_dspi_chip *chip_info
843 + = (struct coldfire_dspi_chip *)spi->controller_data;
844 + DBG("\n");
845 +
846 + /* Only alloc on first setup */
847 + chip = spi_get_ctldata(spi);
848 + if (chip == NULL) {
849 + chip = kcalloc(1, sizeof(struct chip_data), GFP_KERNEL);
850 + if (!chip)
851 + return -ENOMEM;
852 + spi->mode = chip_info->mode;
853 + spi->bits_per_word = chip_info->bits_per_word;
854 + }
855 +
856 + chip->mcr.master = 1;
857 + chip->mcr.cont_scke = 0;
858 + chip->mcr.dconf = 0;
859 + chip->mcr.frz = 0;
860 + chip->mcr.mtfe = 0;
861 + chip->mcr.pcsse = 0;
862 + chip->mcr.rooe = 0;
863 + chip->mcr.pcsis = 0xFF;
864 + chip->mcr.reserved15 = 0;
865 + chip->mcr.mdis = 0;
866 + chip->mcr.dis_tx = 0;
867 + chip->mcr.dis_rxf = 0;
868 + chip->mcr.clr_tx = 1;
869 + chip->mcr.clr_rxf = 1;
870 + chip->mcr.smpl_pt = 0;
871 + chip->mcr.reserved71 = 0;
872 + chip->mcr.halt = 0;
873 +
874 + if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
875 + chip->ctar.fmsz = spi->bits_per_word-1;
876 + } else {
877 + printk(KERN_ERR "Invalid wordsize\n");
878 + kfree(chip);
879 + return -ENODEV;
880 + }
881 +
882 + chip->void_write_data = chip_info->void_write_data;
883 +
884 + if (spi->max_speed_hz != 0)
885 + chip_info->br = hz_to_spi_baud(chip_info->pbr, chip_info->dbr, \
886 + spi->max_speed_hz);
887 +
888 + chip->ctar.cpha = (spi->mode & SPI_CPHA) ? 1 : 0;
889 + chip->ctar.cpol = (spi->mode & SPI_CPOL) ? 1 : 0;
890 + chip->ctar.lsbfe = (spi->mode & SPI_LSB_FIRST) ? 1 : 0;
891 + chip->ctar.dbr = chip_info->dbr;
892 + chip->ctar.pbr = chip_info->pbr;
893 + chip->ctar.br = chip_info->br;
894 + chip->ctar.pcssck = chip_info->pcssck;
895 + chip->ctar.pasc = chip_info->pasc;
896 + chip->ctar.pdt = chip_info->pdt;
897 + chip->ctar.cssck = chip_info->cssck;
898 + chip->ctar.asc = chip_info->asc;
899 + chip->ctar.dt = chip_info->dt;
900 +
901 + spi_set_ctldata(spi, chip);
902 +
903 + return 0;
904 +}
905 +
906 +static int init_queue(struct driver_data *drv_data)
907 +{
908 + INIT_LIST_HEAD(&drv_data->queue);
909 + spin_lock_init(&drv_data->lock);
910 +
911 + drv_data->run = QUEUE_STOPPED;
912 + drv_data->busy = 0;
913 +
914 + tasklet_init(&drv_data->pump_transfers,
915 + pump_transfers, (unsigned long)drv_data);
916 +
917 + INIT_WORK(&drv_data->pump_messages, pump_messages);
918 +
919 + drv_data->workqueue = create_singlethread_workqueue(
920 + drv_data->master->dev.parent->bus_id);
921 + if (drv_data->workqueue == NULL)
922 + return -EBUSY;
923 +
924 + return 0;
925 +}
926 +
927 +static int start_queue(struct driver_data *drv_data)
928 +{
929 + unsigned long flags;
930 +
931 + spin_lock_irqsave(&drv_data->lock, flags);
932 +
933 + if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
934 + spin_unlock_irqrestore(&drv_data->lock, flags);
935 + return -EBUSY;
936 + }
937 +
938 + drv_data->run = QUEUE_RUNNING;
939 + drv_data->cur_msg = NULL;
940 + drv_data->cur_transfer = NULL;
941 + drv_data->cur_chip = NULL;
942 + spin_unlock_irqrestore(&drv_data->lock, flags);
943 +
944 + queue_work(drv_data->workqueue, &drv_data->pump_messages);
945 +
946 + return 0;
947 +}
948 +
949 +static int stop_queue(struct driver_data *drv_data)
950 +{
951 + unsigned long flags;
952 + unsigned limit = 500;
953 + int status = 0;
954 +
955 + spin_lock_irqsave(&drv_data->lock, flags);
956 +
957 + /* This is a bit lame, but is optimized for the common execution path.
958 + * A wait_queue on the drv_data->busy could be used, but then the common
959 + * execution path (pump_messages) would be required to call wake_up or
960 + * friends on every SPI message. Do this instead */
961 + drv_data->run = QUEUE_STOPPED;
962 + while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
963 + spin_unlock_irqrestore(&drv_data->lock, flags);
964 + msleep(10);
965 + spin_lock_irqsave(&drv_data->lock, flags);
966 + }
967 +
968 + if (!list_empty(&drv_data->queue) || drv_data->busy)
969 + status = -EBUSY;
970 +
971 + spin_unlock_irqrestore(&drv_data->lock, flags);
972 +
973 + return status;
974 +}
975 +
976 +static int destroy_queue(struct driver_data *drv_data)
977 +{
978 + int status;
979 +
980 + status = stop_queue(drv_data);
981 + if (status != 0)
982 + return status;
983 +
984 + destroy_workqueue(drv_data->workqueue);
985 +
986 + return 0;
987 +}
988 +
989 +
990 +static void cleanup(struct spi_device *spi)
991 +{
992 + struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
993 +
994 + dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
995 + spi->master->bus_num, spi->chip_select);
996 +
997 + kfree(chip);
998 +}
999 +
1000 +
1001 +/****************************************************************************/
1002 +
1003 +/*
1004 + * Generic Device driver routines and interface implementation
1005 + */
1006 +
1007 +static int coldfire_spi_probe(struct platform_device *pdev)
1008 +{
1009 + struct device *dev = &pdev->dev;
1010 + struct coldfire_spi_master *platform_info;
1011 + struct spi_master *master;
1012 + struct driver_data *drv_data = 0;
1013 + struct resource *memory_resource;
1014 + int irq;
1015 + int status = 0;
1016 + int i;
1017 +#if defined(SPI_DSPI_EDMA)
1018 + dma_addr_t dma_handle;
1019 +#endif
1020 +
1021 + platform_info = (struct coldfire_spi_master *)dev->platform_data;
1022 +
1023 + master = spi_alloc_master(dev, sizeof(struct driver_data));
1024 + if (!master)
1025 + return -ENOMEM;
1026 +
1027 + drv_data = spi_master_get_devdata(master);
1028 + drv_data->master = master;
1029 +
1030 + INIT_LIST_HEAD(&drv_data->queue);
1031 + spin_lock_init(&drv_data->lock);
1032 +
1033 + master->bus_num = platform_info->bus_num;
1034 + master->num_chipselect = platform_info->num_chipselect;
1035 + master->cleanup = cleanup;
1036 + master->setup = setup;
1037 + master->transfer = transfer;
1038 +
1039 + drv_data->cs_control = platform_info->cs_control;
1040 + if (drv_data->cs_control)
1041 + for (i = 0; i < master->num_chipselect; i++)
1042 + drv_data->cs_control(i, QSPI_CS_INIT | QSPI_CS_DROP);
1043 +
1044 + /* Setup register addresses */
1045 + memory_resource = platform_get_resource_byname(pdev,
1046 + IORESOURCE_MEM, "spi-module");
1047 + if (!memory_resource) {
1048 + dev_dbg(dev, "can not find platform module memory\n");
1049 + goto out_error_master_alloc;
1050 + }
1051 +
1052 +#if defined(SPI_DSPI_EDMA)
1053 + drv_data->edma_tx_buf = dma_alloc_coherent(NULL, EDMA_BUFSIZE_KMALLOC, \
1054 + &dma_handle, GFP_DMA);
1055 + if (!drv_data->edma_tx_buf) {
1056 + dev_dbg(dev, "cannot allocate eDMA TX memory\n");
1057 + goto out_error_master_alloc;
1058 + }
1059 + drv_data->edma_rx_buf = dma_alloc_coherent(NULL, EDMA_BUFSIZE_KMALLOC, \
1060 + &dma_handle, GFP_DMA);
1061 + if (!drv_data->edma_rx_buf) {
1062 + dma_free_coherent(NULL, EDMA_BUFSIZE_KMALLOC, \
1063 + drv_data->edma_tx_buf, dma_handle);
1064 + kfree(drv_data->edma_tx_buf);
1065 + dev_dbg(dev, "cannot allocate eDMA RX memory\n");
1066 + goto out_error_master_alloc;
1067 + }
1068 +#endif
1069 +
1070 + drv_data->mcr = (void *)&MCF_DSPI_DMCR;
1071 + drv_data->ctar = (void *)&MCF_DSPI_DCTAR0;
1072 + drv_data->dspi_sr = (void *)&MCF_DSPI_DSR;
1073 + drv_data->dspi_rser = (void *)&MCF_DSPI_DRSER;
1074 + drv_data->dspi_dtfr = (void *)&MCF_DSPI_DTFR;
1075 + drv_data->dspi_drfr = (void *)&MCF_DSPI_DRFR;
1076 +
1077 + memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1078 + "spi-par");
1079 + if (!memory_resource) {
1080 + dev_dbg(dev, "No spi-par memory\n");
1081 + goto out_error_master_alloc;
1082 + }
1083 + drv_data->par = (void *)memory_resource->start;
1084 +
1085 + memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1086 + "spi-int-level");
1087 + if (!memory_resource) {
1088 + dev_dbg(dev, "No spi-int-level memory\n");
1089 + goto out_error_master_alloc;
1090 + }
1091 + drv_data->int_icr = (void *)memory_resource->start;
1092 +
1093 + memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1094 + "spi-int-mask");
1095 + if (!memory_resource) {
1096 + dev_dbg(dev, "No spi-int-mask memory\n");
1097 + goto out_error_master_alloc;
1098 + }
1099 + drv_data->int_mr = (void *)memory_resource->start;
1100 +
1101 + if (platform_info->irq_list) {
1102 + /* multiple IRQs */
1103 + int *irqlist = platform_info->irq_list;
1104 + while ((irq = *irqlist++)) {
1105 + int off = *irqlist++;
1106 + int lvl = *irqlist++;
1107 + int msk = *irqlist++;
1108 + status = request_irq(irq, dspi_interrupt, IRQF_DISABLED,
1109 + dev->bus_id, drv_data);
1110 + if (status < 0) {
1111 + dev_err(&pdev->dev,
1112 + "Unable to attach ColdFire DSPI interrupt\n");
1113 + goto out_error_master_alloc;
1114 + }
1115 +
1116 + if (lvl)
1117 + *(drv_data->int_icr + off) = lvl;
1118 +
1119 + if (msk)
1120 + *drv_data->int_mr &= ~msk;
1121 + }
1122 + }
1123 + else {
1124 + irq = platform_info->irq_vector;
1125 +
1126 + status = request_irq(platform_info->irq_vector, dspi_interrupt,
1127 + IRQF_DISABLED, dev->bus_id, drv_data);
1128 + if (status < 0) {
1129 + dev_err(&pdev->dev, "Unable to attach ColdFire DSPI interrupt\n");
1130 + goto out_error_master_alloc;
1131 + }
1132 +
1133 + *drv_data->int_icr = platform_info->irq_lp;
1134 + *drv_data->int_mr &= ~platform_info->irq_mask;
1135 + }
1136 +
1137 + /* Now that we have all the addresses etc. Let's set it up */
1138 + if (platform_info->par_val)
1139 + *drv_data->par = platform_info->par_val;
1140 +
1141 + /* Initial and start queue */
1142 + status = init_queue(drv_data);
1143 + if (status != 0) {
1144 + dev_err(&pdev->dev, "Problem initializing DSPI queue\n");
1145 + goto out_error_irq_alloc;
1146 + }
1147 + status = start_queue(drv_data);
1148 + if (status != 0) {
1149 + dev_err(&pdev->dev, "Problem starting DSPI queue\n");
1150 + goto out_error_irq_alloc;
1151 + }
1152 +
1153 + /* Register with the SPI framework */
1154 + platform_set_drvdata(pdev, drv_data);
1155 + status = spi_register_master(master);
1156 + if (status != 0) {
1157 + dev_err(&pdev->dev, "Problem registering DSPI master\n");
1158 + status = -EINVAL;
1159 + goto out_error_queue_alloc;
1160 + }
1161 +
1162 +#if defined(SPI_DSPI_EDMA)
1163 + if (mcf_edma_request_channel(DSPI_DMA_TX_TCD,
1164 + edma_tx_handler,
1165 + NULL,
1166 + 0x0,
1167 + pdev,
1168 + NULL, /* spinlock */
1169 + DRIVER_NAME) < 0){
1170 + dev_err(&pdev->dev, "eDMA transmit channel request\n");
1171 + status = -EINVAL;
1172 + goto out_error_queue_alloc;
1173 + }
1174 +
1175 + if (mcf_edma_request_channel(DSPI_DMA_RX_TCD,
1176 + edma_rx_handler,
1177 + NULL,
1178 + 0x0,
1179 + pdev,
1180 + NULL, /* spinlock */
1181 + DRIVER_NAME) < 0){
1182 + dev_err(&pdev->dev, "eDAM receive channel request\n");
1183 + status = -EINVAL;
1184 + mcf_edma_free_channel(DSPI_DMA_TX_TCD, pdev);
1185 + goto out_error_queue_alloc;
1186 + }
1187 +#endif
1188 +
1189 + printk(KERN_INFO "DSPI: Coldfire master initialized\n");
1190 + return status;
1191 +
1192 +out_error_queue_alloc:
1193 + destroy_queue(drv_data);
1194 +
1195 +out_error_irq_alloc:
1196 + free_irq(platform_info->irq_vector, drv_data);
1197 +
1198 +out_error_master_alloc:
1199 + spi_master_put(master);
1200 + return status;
1201 +
1202 +}
1203 +
1204 +static int coldfire_spi_remove(struct platform_device *pdev)
1205 +{
1206 + struct driver_data *drv_data = platform_get_drvdata(pdev);
1207 + int irq;
1208 + int status = 0;
1209 +
1210 + if (!drv_data)
1211 + return 0;
1212 +
1213 +#if defined(SPI_DSPI_EDMA)
1214 + mcf_edma_free_channel(DSPI_DMA_TX_TCD, pdev);
1215 + mcf_edma_free_channel(DSPI_DMA_RX_TCD, pdev);
1216 +#endif
1217 +
1218 + /* Remove the queue */
1219 + status = destroy_queue(drv_data);
1220 + if (status != 0)
1221 + return status;
1222 +
1223 + /* Release IRQ */
1224 + irq = platform_get_irq(pdev, 0);
1225 + if (irq >= 0)
1226 + free_irq(irq, drv_data);
1227 +
1228 + /* Disconnect from the SPI framework */
1229 + spi_unregister_master(drv_data->master);
1230 +
1231 + /* Prevent double remove */
1232 + platform_set_drvdata(pdev, NULL);
1233 +
1234 + return 0;
1235 +}
1236 +
1237 +static void coldfire_spi_shutdown(struct platform_device *pdev)
1238 +{
1239 + int status = coldfire_spi_remove(pdev);
1240 +
1241 + if (status != 0)
1242 + dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1243 +}
1244 +
1245 +
1246 +#ifdef CONFIG_PM
1247 +static int suspend_devices(struct device *dev, void *pm_message)
1248 +{
1249 + pm_message_t *state = pm_message;
1250 +
1251 + if (dev->power.power_state.event != state->event) {
1252 + dev_warn(dev, "pm state does not match request\n");
1253 + return -1;
1254 + }
1255 +
1256 + return 0;
1257 +}
1258 +
1259 +static int coldfire_spi_suspend(struct platform_device *pdev,
1260 + pm_message_t state)
1261 +{
1262 + struct driver_data *drv_data = platform_get_drvdata(pdev);
1263 + int status = 0;
1264 +
1265 + /* Check all childern for current power state */
1266 + if (device_for_each_child(&pdev->dev,
1267 + &state, suspend_devices) != 0) {
1268 + dev_warn(&pdev->dev, "suspend aborted\n");
1269 + return -1;
1270 + }
1271 +
1272 + status = stop_queue(drv_data);
1273 + if (status != 0)
1274 + return status;
1275 +
1276 + return 0;
1277 +}
1278 +
1279 +static int coldfire_spi_resume(struct platform_device *pdev)
1280 +{
1281 + struct driver_data *drv_data = platform_get_drvdata(pdev);
1282 + int status = 0;
1283 +
1284 + /* Start the queue running */
1285 + status = start_queue(drv_data);
1286 + if (status != 0) {
1287 + dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1288 + return status;
1289 + }
1290 +
1291 + return 0;
1292 +}
1293 +#else
1294 +#define coldfire_spi_suspend NULL
1295 +#define coldfire_spi_resume NULL
1296 +#endif /* CONFIG_PM */
1297 +
1298 +static struct platform_driver driver = {
1299 + .driver = {
1300 + .name = "spi_coldfire",
1301 + .bus = &platform_bus_type,
1302 + .owner = THIS_MODULE,
1303 + },
1304 + .probe = coldfire_spi_probe,
1305 + .remove = __devexit_p(coldfire_spi_remove),
1306 + .shutdown = coldfire_spi_shutdown,
1307 + .suspend = coldfire_spi_suspend,
1308 + .resume = coldfire_spi_resume,
1309 +};
1310 +
1311 +static int __init coldfire_spi_init(void)
1312 +{
1313 + platform_driver_register(&driver);
1314 +
1315 + return 0;
1316 +}
1317 +module_init(coldfire_spi_init);
1318 +
1319 +static void __exit coldfire_spi_exit(void)
1320 +{
1321 + platform_driver_unregister(&driver);
1322 +}
1323 +module_exit(coldfire_spi_exit);
1324 +
1325 +MODULE_AUTHOR("Matt Waddel");
1326 +MODULE_DESCRIPTION("ColdFire DSPI Contoller");
1327 +MODULE_LICENSE("GPL");
1328 --- /dev/null
1329 +++ b/include/asm-m68k/mcfdspi.h
1330 @@ -0,0 +1,48 @@
1331 +/*
1332 + * mcfdspi.h-DSPI controller for the ColdFire processors.
1333 + *
1334 + * Andrey Butok
1335 + * Copyright Freescale Semiconductor, Inc. 2008
1336 + *
1337 + * This file is based on mcfqspi.h
1338 + *
1339 + * This program is free software; you can redistribute it and/or modify it
1340 + * under the terms of the GNU General Public License as published by the
1341 + * Free Software Foundation; either version 2 of the License, or (at your
1342 + * option) any later version.
1343 + *
1344 + * This program is distributed in the hope that it will be useful,
1345 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1346 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1347 + * GNU General Public License for more details.
1348 + *
1349 + * You should have received a copy of the GNU General Public License
1350 + * along with this program; if not, write to the Free Software
1351 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1352 + *
1353 + ***************************************************************************
1354 + * Changes:
1355 + * v0.001 25 March 2008 Andrey Butok
1356 + * Initial Release - developed on uClinux with 2.6.23 kernel.
1357 + *
1358 + */
1359 +
1360 +#ifndef MCFDSPI_H_
1361 +#define MCFDSPI_H_
1362 +
1363 +struct coldfire_dspi_chip {
1364 + u8 mode;
1365 + u8 bits_per_word;
1366 + u16 void_write_data;
1367 + /* Only used in master mode */
1368 + u8 dbr; /* Double baud rate */
1369 + u8 pbr; /* Baud rate prescaler */
1370 + u8 br; /* Baud rate scaler */
1371 + u8 pcssck; /* PCS to SCK delay prescaler */
1372 + u8 pasc; /* After SCK delay prescaler */
1373 + u8 pdt; /* Delay after transfer prescaler */
1374 + u8 cssck; /* PCS to SCK delay scaler */
1375 + u8 asc; /* After SCK delay scaler */
1376 + u8 dt; /* Delay after transfer scaler */
1377 +};
1378 +#endif /*MCFDSPI_H_*/
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