target/linux/adm5120/files/drivers/usb/host/adm5120.h

   1 /*
   2  * OHCI HCD (Host Controller Driver) for USB.
   3  *
   4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5  * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
   6  *
   7  * This file is licenced under the GPL.
   8  */
   9
  10 /*
  11  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  12  * __leXX (normally) or __beXX (given OHCI_BIG_ENDIAN), depending on the
  13  * host controller implementation.
  14  */
  15 typedef __u32 __bitwise __hc32;
  16 typedef __u16 __bitwise __hc16;
  17
  18 /*
  19  * OHCI Endpoint Descriptor (ED) ... holds TD queue
  20  * See OHCI spec, section 4.2
  21  *
  22  * This is a "Queue Head" for those transfers, which is why
  23  * both EHCI and UHCI call similar structures a "QH".
  24  */
  25
  26 #define TD_DATALEN_MAX  4096
  27
  28 #define ED_ALIGN        16
  29 #define ED_MASK ((u32)~(ED_ALIGN-1))    /* strip hw status in low addr bits */
  30
  31 struct ed {
  32         /* first fields are hardware-specified */
  33         __hc32                  hwINFO;      /* endpoint config bitmap */
  34         /* info bits defined by hcd */
  35 #define ED_DEQUEUE      (1 << 27)
  36         /* info bits defined by the hardware */
  37 #define ED_MPS_SHIFT    16
  38 #define ED_MPS_MASK     ((1 << 11)-1)
  39 #define ED_MPS_GET(x)   (((x) >> ED_MPS_SHIFT) & ED_MPS_MASK)
  40 #define ED_ISO          (1 << 15)               /* isochronous endpoint */
  41 #define ED_SKIP         (1 << 14)
  42 #define ED_SPEED_FULL   (1 << 13)               /* fullspeed device */
  43 #define ED_INT          (1 << 11)               /* interrupt endpoint */
  44 #define ED_EN_SHIFT     7                       /* endpoint shift */
  45 #define ED_EN_MASK      ((1 << 4)-1)            /* endpoint mask */
  46 #define ED_EN_GET(x)    (((x) >> ED_EN_SHIFT) & ED_EN_MASK)
  47 #define ED_FA_MASK      ((1 << 7)-1)            /* function address mask */
  48 #define ED_FA_GET(x)    ((x) & ED_FA_MASK)
  49         __hc32                  hwTailP;        /* tail of TD list */
  50         __hc32                  hwHeadP;        /* head of TD list (hc r/w) */
  51 #define ED_C            (0x02)                  /* toggle carry */
  52 #define ED_H            (0x01)                  /* halted */
  53         __hc32                  hwNextED;       /* next ED in list */
  54
  55         /* rest are purely for the driver's use */
  56         dma_addr_t              dma;            /* addr of ED */
  57         struct td               *dummy;         /* next TD to activate */
  58
  59         struct list_head        urb_list;       /* list of our URBs */
  60
  61         /* host's view of schedule */
  62         struct ed               *ed_next;       /* on schedule list */
  63         struct ed               *ed_prev;       /* for non-interrupt EDs */
  64         struct ed               *ed_rm_next;    /* on rm list */
  65         struct list_head        td_list;        /* "shadow list" of our TDs */
  66
  67         /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
  68          * usually:  OPER --> UNLINK --> (IDLE | OPER) --> ...
  69          */
  70         u8                      state;          /* ED_{IDLE,UNLINK,OPER} */
  71 #define ED_IDLE         0x00            /* NOT linked to HC */
  72 #define ED_UNLINK       0x01            /* being unlinked from hc */
  73 #define ED_OPER         0x02            /* IS linked to hc */
  74
  75         u8                      type;           /* PIPE_{BULK,...} */
  76
  77         /* periodic scheduling params (for intr and iso) */
  78         u8                      branch;
  79         u16                     interval;
  80         u16                     load;
  81         u16                     last_iso;       /* iso only */
  82
  83         /* HC may see EDs on rm_list until next frame (frame_no == tick) */
  84         u16                     tick;
  85 } __attribute__ ((aligned(ED_ALIGN)));
  86
  87 /*
  88  * OHCI Transfer Descriptor (TD) ... one per transfer segment
  89  * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt)
  90  * and 4.3.2 (iso)
  91  */
  92
  93 #define TD_ALIGN        32
  94 #define TD_MASK ((u32)~(TD_ALIGN-1))    /* strip hw status in low addr bits */
  95
  96 struct td {
  97         /* first fields are hardware-specified */
  98         __hc32          hwINFO;         /* transfer info bitmask */
  99
 100         /* hwINFO bits */
 101 #define TD_OWN          (1 << 31)               /* owner of the descriptor */
 102 #define TD_CC_SHIFT     27                      /* condition code */
 103 #define TD_CC_MASK      0xf
 104 #define TD_CC           (TD_CC_MASK << TD_CC_SHIFT)
 105 #define TD_CC_GET(x)    (((x) >> TD_CC_SHIFT) & TD_CC_MASK)
 106
 107 #define TD_EC_SHIFT     25                      /* error count */
 108 #define TD_EC_MASK      0x3
 109 #define TD_EC           (TD_EC_MASK << TD_EC_SHIFT)
 110 #define TD_EC_GET(x)    ((x >> TD_EC_SHIFT) & TD_EC_MASK)
 111 #define TD_T_SHIFT      23                      /* data toggle state */
 112 #define TD_T_MASK       0x3
 113 #define TD_T            (TD_T_MASK << TD_T_SHIFT)
 114 #define TD_T_DATA0      (0x2 << TD_T_SHIFT)     /* DATA0 */
 115 #define TD_T_DATA1      (0x3 << TD_T_SHIFT)     /* DATA1 */
 116 #define TD_T_CARRY      (0x0 << TD_T_SHIFT)     /* uses ED_C */
 117 #define TD_T_GET(x)     (((x) >> TD_T_SHIFT) & TD_T_MASK)
 118 #define TD_DP_SHIFT     21                      /* direction/pid */
 119 #define TD_DP_MASK      0x3
 120 #define TD_DP           (TD_DP_MASK << TD_DP_SHIFT)
 121 #define TD_DP_GET       (((x) >> TD_DP_SHIFT) & TD_DP_MASK)
 122 #define TD_DP_SETUP     (0x0 << TD_DP_SHIFT)    /* SETUP pid */
 123 #define TD_DP_OUT       (0x1 << TD_DP_SHIFT)    /* OUT pid */
 124 #define TD_DP_IN        (0x2 << TD_DP_SHIFT)    /* IN pid */
 125 #define TD_ISI_SHIFT    8                       /* Interrupt Service Interval */
 126 #define TD_ISI_MASK     0x3f
 127 #define TD_ISI_GET(x)   (((x) >> TD_ISI_SHIFT) & TD_ISI_MASK)
 128 #define TD_FN_MASK      0x3f                    /* frame number */
 129 #define TD_FN_GET(x)    ((x) & TD_FN_MASK)
 130
 131         __hc32          hwDBP;          /* Data Buffer Pointer (or 0) */
 132         __hc32          hwCBL;          /* Controller/Buffer Length */
 133
 134         /* hwCBL bits */
 135 #define TD_BL_MASK      0xffff          /* buffer length */
 136 #define TD_BL_GET(x)    ((x) & TD_BL_MASK)
 137 #define TD_IE           (1 << 16)       /* interrupt enable */
 138         __hc32          hwNextTD;       /* Next TD Pointer */
 139
 140         /* rest are purely for the driver's use */
 141         __u8            index;
 142         struct ed       *ed;
 143         struct td       *td_hash;       /* dma-->td hashtable */
 144         struct td       *next_dl_td;
 145         struct urb      *urb;
 146
 147         dma_addr_t      td_dma;         /* addr of this TD */
 148         dma_addr_t      data_dma;       /* addr of data it points to */
 149
 150         struct list_head td_list;       /* "shadow list", TDs on same ED */
 151
 152         u32             flags;
 153 #define TD_FLAG_DONE    (1 << 17)       /* retired to done list */
 154 #define TD_FLAG_ISO     (1 << 16)       /* copy of ED_ISO */
 155 } __attribute__ ((aligned(TD_ALIGN)));  /* c/b/i need 16; only iso needs 32 */
 156
 157 /*
 158  * Hardware transfer status codes -- CC from td->hwINFO
 159  */
 160 #define TD_CC_NOERROR           0x00
 161 #define TD_CC_CRC               0x01
 162 #define TD_CC_BITSTUFFING       0x02
 163 #define TD_CC_DATATOGGLEM       0x03
 164 #define TD_CC_STALL             0x04
 165 #define TD_CC_DEVNOTRESP        0x05
 166 #define TD_CC_PIDCHECKFAIL      0x06
 167 #define TD_CC_UNEXPECTEDPID     0x07
 168 #define TD_CC_DATAOVERRUN       0x08
 169 #define TD_CC_DATAUNDERRUN      0x09
 170     /* 0x0A, 0x0B reserved for hardware */
 171 #define TD_CC_BUFFEROVERRUN     0x0C
 172 #define TD_CC_BUFFERUNDERRUN    0x0D
 173     /* 0x0E, 0x0F reserved for HCD */
 174 #define TD_CC_HCD0              0x0E
 175 #define TD_CC_NOTACCESSED       0x0F
 176
 177 /*
 178  * preshifted status codes
 179  */
 180 #define TD_SCC_NOTACCESSED      (TD_CC_NOTACCESSED << TD_CC_SHIFT)
 181
 182
 183 /* map OHCI TD status codes (CC) to errno values */
 184 static const int cc_to_error [16] = {
 185         /* No  Error  */        0,
 186         /* CRC Error  */        -EILSEQ,
 187         /* Bit Stuff  */        -EPROTO,
 188         /* Data Togg  */        -EILSEQ,
 189         /* Stall      */        -EPIPE,
 190         /* DevNotResp */        -ETIME,
 191         /* PIDCheck   */        -EPROTO,
 192         /* UnExpPID   */        -EPROTO,
 193         /* DataOver   */        -EOVERFLOW,
 194         /* DataUnder  */        -EREMOTEIO,
 195         /* (for hw)   */        -EIO,
 196         /* (for hw)   */        -EIO,
 197         /* BufferOver */        -ECOMM,
 198         /* BuffUnder  */        -ENOSR,
 199         /* (for HCD)  */        -EALREADY,
 200         /* (for HCD)  */        -EALREADY
 201 };
 202
 203 #define NUM_INTS        32
 204
 205 /*
 206  * This is the structure of the OHCI controller's memory mapped I/O region.
 207  * You must use readl() and writel() (in <asm/io.h>) to access these fields!!
 208  * Layout is in section 7 (and appendix B) of the spec.
 209  */
 210 struct admhcd_regs {
 211         __hc32  gencontrol;     /* General Control */
 212         __hc32  int_status;     /* Interrupt Status */
 213         __hc32  int_enable;     /* Interrupt Enable */
 214         __hc32  reserved00;
 215         __hc32  host_control;   /* Host General Control */
 216         __hc32  reserved01;
 217         __hc32  fminterval;     /* Frame Interval */
 218         __hc32  fmnumber;       /* Frame Number */
 219         __hc32  reserved02;
 220         __hc32  reserved03;
 221         __hc32  reserved04;
 222         __hc32  reserved05;
 223         __hc32  reserved06;
 224         __hc32  reserved07;
 225         __hc32  reserved08;
 226         __hc32  reserved09;
 227         __hc32  reserved10;
 228         __hc32  reserved11;
 229         __hc32  reserved12;
 230         __hc32  reserved13;
 231         __hc32  reserved14;
 232         __hc32  reserved15;
 233         __hc32  reserved16;
 234         __hc32  reserved17;
 235         __hc32  reserved18;
 236         __hc32  reserved19;
 237         __hc32  reserved20;
 238         __hc32  reserved21;
 239         __hc32  lsthresh;       /* Low Speed Threshold */
 240         __hc32  rhdesc;         /* Root Hub Descriptor */
 241 #define MAX_ROOT_PORTS  2
 242         __hc32  portstatus[MAX_ROOT_PORTS]; /* Port Status */
 243         __hc32  hosthead;       /* Host Descriptor Head */
 244 } __attribute__ ((aligned(32)));
 245
 246 /*
 247  * General Control register bits
 248  */
 249 #define ADMHC_CTRL_UHFE (1 << 0)        /* USB Host Function Enable */
 250 #define ADMHC_CTRL_SIR  (1 << 1)        /* Software Interrupt request */
 251 #define ADMHC_CTRL_DMAA (1 << 2)        /* DMA Arbitration Control */
 252 #define ADMHC_CTRL_SR   (1 << 3)        /* Software Reset */
 253
 254 /*
 255  * Host General Control register bits
 256  */
 257 #define ADMHC_HC_BUSS           0x3             /* USB bus state */
 258 #define   ADMHC_BUSS_RESET      0x0
 259 #define   ADMHC_BUSS_RESUME     0x1
 260 #define   ADMHC_BUSS_OPER       0x2
 261 #define   ADMHC_BUSS_SUSPEND    0x3
 262 #define ADMHC_HC_DMAE           (1 << 2)        /* DMA enable */
 263
 264 /*
 265  * Interrupt Status/Enable register bits
 266  */
 267 #define ADMHC_INTR_SOFI (1 << 4)        /* start of frame */
 268 #define ADMHC_INTR_RESI (1 << 5)        /* resume detected */
 269 #define ADMHC_INTR_6    (1 << 6)        /* unknown */
 270 #define ADMHC_INTR_7    (1 << 7)        /* unknown */
 271 #define ADMHC_INTR_BABI (1 << 8)        /* babble detected */
 272 #define ADMHC_INTR_INSM (1 << 9)        /* root hub status change */
 273 #define ADMHC_INTR_SO   (1 << 10)       /* scheduling overrun */
 274 #define ADMHC_INTR_FNO  (1 << 11)       /* frame number overflow */
 275 #define ADMHC_INTR_TDC  (1 << 20)       /* transfer descriptor completed */
 276 #define ADMHC_INTR_SWI  (1 << 29)       /* software interrupt */
 277 #define ADMHC_INTR_FATI (1 << 30)       /* fatal error */
 278 #define ADMHC_INTR_INTA (1 << 31)       /* interrupt active */
 279
 280 #define ADMHC_INTR_MIE  (1 << 31)       /* master interrupt enable */
 281
 282 /*
 283  * SOF Frame Interval register bits
 284  */
 285 #define ADMHC_SFI_FI_MASK       ((1 << 14)-1)   /* Frame Interval value */
 286 #define ADMHC_SFI_FSLDP_SHIFT   16
 287 #define ADMHC_SFI_FSLDP_MASK    ((1 << 15)-1)
 288 #define ADMHC_SFI_FIT           (1 << 31)       /* Frame Interval Toggle */
 289
 290 /*
 291  * SOF Frame Number register bits
 292  */
 293 #define ADMHC_SFN_FN_MASK       ((1 << 16)-1)   /* Frame Number Mask */
 294 #define ADMHC_SFN_FR_SHIFT      16              /* Frame Remaining Shift */
 295 #define ADMHC_SFN_FR_MASK       ((1 << 14)-1)   /* Frame Remaining Mask */
 296 #define ADMHC_SFN_FRT           (1 << 31)       /* Frame Remaining Toggle */
 297
 298 /*
 299  * Root Hub Descriptor register bits
 300  */
 301 #define ADMHC_RH_NUMP   0xff            /* number of ports */
 302 #define ADMHC_RH_PSM    (1 << 8)        /* power switching mode */
 303 #define ADMHC_RH_NPS    (1 << 9)        /* no power switching */
 304 #define ADMHC_RH_OCPM   (1 << 10)       /* over current protection mode */
 305 #define ADMHC_RH_NOCP   (1 << 11)       /* no over current protection */
 306 #define ADMHC_RH_PPCM   (0xff << 16)    /* port power control */
 307
 308 #define ADMHC_RH_LPS    (1 << 24)       /* local power switch */
 309 #define ADMHC_RH_OCI    (1 << 25)       /* over current indicator */
 310
 311 /* status change bits */
 312 #define ADMHC_RH_LPSC   (1 << 26)       /* local power switch change */
 313 #define ADMHC_RH_OCIC   (1 << 27)       /* over current indicator change */
 314
 315 #define ADMHC_RH_DRWE   (1 << 28)       /* device remote wakeup enable */
 316 #define ADMHC_RH_CRWE   (1 << 29)       /* clear remote wakeup enable */
 317
 318 #define ADMHC_RH_CGP    (1 << 24)       /* clear global power */
 319 #define ADMHC_RH_SGP    (1 << 26)       /* set global power */
 320
 321 /*
 322  * Port Status register bits
 323  */
 324 #define ADMHC_PS_CCS    (1 << 0)        /* current connect status */
 325 #define ADMHC_PS_PES    (1 << 1)        /* port enable status */
 326 #define ADMHC_PS_PSS    (1 << 2)        /* port suspend status */
 327 #define ADMHC_PS_POCI   (1 << 3)        /* port over current indicator */
 328 #define ADMHC_PS_PRS    (1 << 4)        /* port reset status */
 329 #define ADMHC_PS_PPS    (1 << 8)        /* port power status */
 330 #define ADMHC_PS_LSDA   (1 << 9)        /* low speed device attached */
 331
 332 /* status change bits */
 333 #define ADMHC_PS_CSC    (1 << 16)       /* connect status change */
 334 #define ADMHC_PS_PESC   (1 << 17)       /* port enable status change */
 335 #define ADMHC_PS_PSSC   (1 << 18)       /* port suspend status change */
 336 #define ADMHC_PS_OCIC   (1 << 19)       /* over current indicator change */
 337 #define ADMHC_PS_PRSC   (1 << 20)       /* port reset status change */
 338
 339 /* port feature bits */
 340 #define ADMHC_PS_CPE    (1 << 0)        /* clear port enable */
 341 #define ADMHC_PS_SPE    (1 << 1)        /* set port enable */
 342 #define ADMHC_PS_SPS    (1 << 2)        /* set port suspend */
 343 #define ADMHC_PS_CPS    (1 << 3)        /* clear suspend status */
 344 #define ADMHC_PS_SPR    (1 << 4)        /* set port reset */
 345 #define ADMHC_PS_SPP    (1 << 8)        /* set port power */
 346 #define ADMHC_PS_CPP    (1 << 9)        /* clear port power */
 347
 348 /*
 349  * the POTPGT value is not defined in the ADMHC, so define a dummy value
 350  */
 351 #define ADMHC_POTPGT    2               /* in ms */
 352
 353 /* hcd-private per-urb state */
 354 struct urb_priv {
 355         struct ed               *ed;
 356         struct list_head        pending;        /* URBs on the same ED */
 357
 358         u32                     td_cnt;         /* # tds in this request */
 359         u32                     td_idx;         /* index of the current td */
 360         struct td               *td[0];         /* all TDs in this request */
 361 };
 362
 363 #define TD_HASH_SIZE    64    /* power'o'two */
 364 /* sizeof (struct td) ~= 64 == 2^6 ... */
 365 #define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE)
 366
 367 /*
 368  * This is the full ADMHCD controller description
 369  *
 370  * Note how the "proper" USB information is just
 371  * a subset of what the full implementation needs. (Linus)
 372  */
 373
 374 struct admhcd {
 375         spinlock_t              lock;
 376
 377         /*
 378          * I/O memory used to communicate with the HC (dma-consistent)
 379          */
 380         struct admhcd_regs __iomem *regs;
 381
 382         /*
 383          * hcd adds to schedule for a live hc any time, but removals finish
 384          * only at the start of the next frame.
 385          */
 386
 387         struct ed               *ed_head;
 388         struct ed               *ed_tails[4];
 389
 390         struct ed               *ed_rm_list;    /* to be removed */
 391
 392         struct ed               *periodic[NUM_INTS];    /* shadow int_table */
 393
 394 #if 0   /* TODO: remove? */
 395         /*
 396          * OTG controllers and transceivers need software interaction;
 397          * other external transceivers should be software-transparent
 398          */
 399         struct otg_transceiver  *transceiver;
 400 #endif
 401
 402         /*
 403          * memory management for queue data structures
 404          */
 405         struct dma_pool         *td_cache;
 406         struct dma_pool         *ed_cache;
 407         struct td               *td_hash[TD_HASH_SIZE];
 408         struct list_head        pending;
 409
 410         /*
 411          * driver state
 412          */
 413         int                     num_ports;
 414         int                     load[NUM_INTS];
 415         u32                     host_control;   /* copy of the host_control reg */
 416         unsigned long           next_statechange;       /* suspend/resume */
 417         u32                     fminterval;             /* saved register */
 418         unsigned                autostop:1;     /* rh auto stopping/stopped */
 419
 420         unsigned long           flags;          /* for HC bugs */
 421 #define OHCI_QUIRK_AMD756       0x01                    /* erratum #4 */
 422 #define OHCI_QUIRK_SUPERIO      0x02                    /* natsemi */
 423 #define OHCI_QUIRK_INITRESET    0x04                    /* SiS, OPTi, ... */
 424 #define OHCI_QUIRK_BE_DESC      0x08                    /* BE descriptors */
 425 #define OHCI_QUIRK_BE_MMIO      0x10                    /* BE registers */
 426 #define OHCI_QUIRK_ZFMICRO      0x20                    /* Compaq ZFMicro chipset*/
 427         // there are also chip quirks/bugs in init logic
 428 };
 429
 430 /* convert between an hcd pointer and the corresponding ahcd_hcd */
 431 static inline struct admhcd *hcd_to_admhcd(struct usb_hcd *hcd)
 432 {
 433         return (struct admhcd *)(hcd->hcd_priv);
 434 }
 435 static inline struct usb_hcd *admhcd_to_hcd(const struct admhcd *ahcd)
 436 {
 437         return container_of((void *)ahcd, struct usb_hcd, hcd_priv);
 438 }
 439
 440 /*-------------------------------------------------------------------------*/
 441
 442 #ifndef DEBUG
 443 #define STUB_DEBUG_FILES
 444 #endif  /* DEBUG */
 445
 446 #ifdef DEBUG
 447 #       define admhc_dbg(ahcd, fmt, args...) \
 448                 printk(KERN_DEBUG "adm5120-hcd: " fmt , ## args )
 449 #else
 450 #       define admhc_dbg(ahcd, fmt, args...) do { } while (0)
 451 #endif
 452
 453 #define admhc_err(ahcd, fmt, args...) \
 454         printk(KERN_ERR "adm5120-hcd: " fmt , ## args )
 455 #define admhc_info(ahcd, fmt, args...) \
 456         printk(KERN_INFO "adm5120-hcd: " fmt , ## args )
 457 #define admhc_warn(ahcd, fmt, args...) \
 458         printk(KERN_WARNING "adm5120-hcd: " fmt , ## args )
 459
 460 #ifdef ADMHC_VERBOSE_DEBUG
 461 #       define admhc_vdbg admhc_dbg
 462 #else
 463 #       define admhc_vdbg(ahcd, fmt, args...) do { } while (0)
 464 #endif
 465
 466 /*-------------------------------------------------------------------------*/
 467
 468 /*
 469  * While most USB host controllers implement their registers and
 470  * in-memory communication descriptors in little-endian format,
 471  * a minority (notably the IBM STB04XXX and the Motorola MPC5200
 472  * processors) implement them in big endian format.
 473  *
 474  * In addition some more exotic implementations like the Toshiba
 475  * Spider (aka SCC) cell southbridge are "mixed" endian, that is,
 476  * they have a different endianness for registers vs. in-memory
 477  * descriptors.
 478  *
 479  * This attempts to support either format at compile time without a
 480  * runtime penalty, or both formats with the additional overhead
 481  * of checking a flag bit.
 482  *
 483  * That leads to some tricky Kconfig rules howevber. There are
 484  * different defaults based on some arch/ppc platforms, though
 485  * the basic rules are:
 486  *
 487  * Controller type              Kconfig options needed
 488  * ---------------              ----------------------
 489  * little endian                CONFIG_USB_ADMHC_LITTLE_ENDIAN
 490  *
 491  * fully big endian             CONFIG_USB_ADMHC_BIG_ENDIAN_DESC _and_
 492  *                              CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
 493  *
 494  * mixed endian                 CONFIG_USB_ADMHC_LITTLE_ENDIAN _and_
 495  *                              CONFIG_USB_OHCI_BIG_ENDIAN_{MMIO,DESC}
 496  *
 497  * (If you have a mixed endian controller, you -must- also define
 498  * CONFIG_USB_ADMHC_LITTLE_ENDIAN or things will not work when building
 499  * both your mixed endian and a fully big endian controller support in
 500  * the same kernel image).
 501  */
 502
 503 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_DESC
 504 #ifdef CONFIG_USB_ADMHC_LITTLE_ENDIAN
 505 #define big_endian_desc(ahcd)   (ahcd->flags & OHCI_QUIRK_BE_DESC)
 506 #else
 507 #define big_endian_desc(ahcd)   1               /* only big endian */
 508 #endif
 509 #else
 510 #define big_endian_desc(ahcd)   0               /* only little endian */
 511 #endif
 512
 513 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
 514 #ifdef CONFIG_USB_ADMHC_LITTLE_ENDIAN
 515 #define big_endian_mmio(ahcd)   (ahcd->flags & OHCI_QUIRK_BE_MMIO)
 516 #else
 517 #define big_endian_mmio(ahcd)   1               /* only big endian */
 518 #endif
 519 #else
 520 #define big_endian_mmio(ahcd)   0               /* only little endian */
 521 #endif
 522
 523 /*
 524  * Big-endian read/write functions are arch-specific.
 525  * Other arches can be added if/when they're needed.
 526  *
 527  * REVISIT: arch/powerpc now has readl/writel_be, so the
 528  * definition below can die once the STB04xxx support is
 529  * finally ported over.
 530  */
 531 #if defined(CONFIG_PPC) && !defined(CONFIG_PPC_MERGE)
 532 #define readl_be(addr)          in_be32((__force unsigned *)addr)
 533 #define writel_be(val, addr)    out_be32((__force unsigned *)addr, val)
 534 #endif
 535
 536 static inline unsigned int admhc_readl(const struct admhcd *ahcd,
 537         __hc32 __iomem *regs)
 538 {
 539 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
 540         return big_endian_mmio(ahcd) ?
 541                 readl_be(regs) :
 542                 readl(regs);
 543 #else
 544         return readl(regs);
 545 #endif
 546 }
 547
 548 static inline void admhc_writel(const struct admhcd *ahcd,
 549         const unsigned int val, __hc32 __iomem *regs)
 550 {
 551 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
 552         big_endian_mmio(ahcd) ?
 553                 writel_be(val, regs) :
 554                 writel(val, regs);
 555 #else
 556                 writel(val, regs);
 557 #endif
 558 }
 559
 560 static inline void admhc_writel_flush(const struct admhcd *ahcd)
 561 {
 562 #if 0
 563         /* TODO: remove? */
 564         (void) admhc_readl(ahcd, &ahcd->regs->gencontrol);
 565 #endif
 566 }
 567
 568
 569 /*-------------------------------------------------------------------------*/
 570
 571 /* cpu to ahcd */
 572 static inline __hc16 cpu_to_hc16(const struct admhcd *ahcd, const u16 x)
 573 {
 574         return big_endian_desc(ahcd) ?
 575                 (__force __hc16)cpu_to_be16(x) :
 576                 (__force __hc16)cpu_to_le16(x);
 577 }
 578
 579 static inline __hc16 cpu_to_hc16p(const struct admhcd *ahcd, const u16 *x)
 580 {
 581         return big_endian_desc(ahcd) ?
 582                 cpu_to_be16p(x) :
 583                 cpu_to_le16p(x);
 584 }
 585
 586 static inline __hc32 cpu_to_hc32(const struct admhcd *ahcd, const u32 x)
 587 {
 588         return big_endian_desc(ahcd) ?
 589                 (__force __hc32)cpu_to_be32(x) :
 590                 (__force __hc32)cpu_to_le32(x);
 591 }
 592
 593 static inline __hc32 cpu_to_hc32p(const struct admhcd *ahcd, const u32 *x)
 594 {
 595         return big_endian_desc(ahcd) ?
 596                 cpu_to_be32p(x) :
 597                 cpu_to_le32p(x);
 598 }
 599
 600 /* ahcd to cpu */
 601 static inline u16 hc16_to_cpu(const struct admhcd *ahcd, const __hc16 x)
 602 {
 603         return big_endian_desc(ahcd) ?
 604                 be16_to_cpu((__force __be16)x) :
 605                 le16_to_cpu((__force __le16)x);
 606 }
 607
 608 static inline u16 hc16_to_cpup(const struct admhcd *ahcd, const __hc16 *x)
 609 {
 610         return big_endian_desc(ahcd) ?
 611                 be16_to_cpup((__force __be16 *)x) :
 612                 le16_to_cpup((__force __le16 *)x);
 613 }
 614
 615 static inline u32 hc32_to_cpu(const struct admhcd *ahcd, const __hc32 x)
 616 {
 617         return big_endian_desc(ahcd) ?
 618                 be32_to_cpu((__force __be32)x) :
 619                 le32_to_cpu((__force __le32)x);
 620 }
 621
 622 static inline u32 hc32_to_cpup(const struct admhcd *ahcd, const __hc32 *x)
 623 {
 624         return big_endian_desc(ahcd) ?
 625                 be32_to_cpup((__force __be32 *)x) :
 626                 le32_to_cpup((__force __le32 *)x);
 627 }
 628
 629 /*-------------------------------------------------------------------------*/
 630
 631 static inline u16 admhc_frame_no(const struct admhcd *ahcd)
 632 {
 633         u32     t;
 634
 635         t = admhc_readl(ahcd, &ahcd->regs->fmnumber) & ADMHC_SFN_FN_MASK;
 636         return (u16)t;
 637 }
 638
 639 static inline u16 admhc_frame_remain(const struct admhcd *ahcd)
 640 {
 641         u32     t;
 642
 643         t = admhc_readl(ahcd, &ahcd->regs->fmnumber) >> ADMHC_SFN_FR_SHIFT;
 644         t &= ADMHC_SFN_FR_MASK;
 645         return (u16)t;
 646 }
 647
 648 /*-------------------------------------------------------------------------*/
 649
 650 static inline void admhc_disable(struct admhcd *ahcd)
 651 {
 652         admhcd_to_hcd(ahcd)->state = HC_STATE_HALT;
 653 }
 654
 655 #define FI              0x2edf          /* 12000 bits per frame (-1) */
 656 #define FSLDP(fi)       (0x7fff & ((6 * ((fi) - 1200)) / 7))
 657 #define FIT             ADMHC_SFI_FIT
 658 #define LSTHRESH        0x628           /* lowspeed bit threshold */
 659
 660 static inline void periodic_reinit(struct admhcd *ahcd)
 661 {
 662 #if 0
 663         u32     fi = ahcd->fminterval & ADMHC_SFI_FI_MASK;
 664         u32     fit = admhc_readl(ahcd, &ahcd->regs->fminterval) & FIT;
 665
 666         /* TODO: adjust FSLargestDataPacket value too? */
 667         admhc_writel(ahcd, (fit ^ FIT) | ahcd->fminterval,
 668                                         &ahcd->regs->fminterval);
 669 #else
 670         u32     fit = admhc_readl(ahcd, &ahcd->regs->fminterval) & FIT;
 671
 672         /* TODO: adjust FSLargestDataPacket value too? */
 673         admhc_writel(ahcd, (fit ^ FIT) | ahcd->fminterval,
 674                                         &ahcd->regs->fminterval);
 675 #endif
 676 }
 677
 678 static inline u32 admhc_read_rhdesc(struct admhcd *ahcd)
 679 {
 680         return admhc_readl(ahcd, &ahcd->regs->rhdesc);
 681 }
 682
 683 static inline u32 admhc_read_portstatus(struct admhcd *ahcd, int port)
 684 {
 685         return admhc_readl(ahcd, &ahcd->regs->portstatus[port]);
 686 }
 687
 688 static inline void admhc_write_portstatus(struct admhcd *ahcd, int port,
 689                 u32 value)
 690 {
 691         admhc_writel(ahcd, value, &ahcd->regs->portstatus[port]);
 692 }
 693
 694 static inline void roothub_write_status(struct admhcd *ahcd, u32 value)
 695 {
 696         /* FIXME: read-only bits must be masked out */
 697         admhc_writel(ahcd, value, &ahcd->regs->rhdesc);
 698 }
 699
 700 static inline void admhc_intr_disable(struct admhcd *ahcd, u32 ints)
 701 {
 702         u32     t;
 703
 704         t = admhc_readl(ahcd, &ahcd->regs->int_enable);
 705         t &= ~(ints);
 706         admhc_writel(ahcd, t, &ahcd->regs->int_enable);
 707         /* TODO: flush writes ?*/
 708 }
 709
 710 static inline void admhc_intr_enable(struct admhcd *ahcd, u32 ints)
 711 {
 712         u32     t;
 713
 714         t = admhc_readl(ahcd, &ahcd->regs->int_enable);
 715         t |= ints;
 716         admhc_writel(ahcd, t, &ahcd->regs->int_enable);
 717         /* TODO: flush writes ?*/
 718 }
 719
 720 static inline void admhc_intr_ack(struct admhcd *ahcd, u32 ints)
 721 {
 722         admhc_writel(ahcd, ints, &ahcd->regs->int_status);
 723 }
 724
 725 static inline void admhc_dma_enable(struct admhcd *ahcd)
 726 {
 727         u32 t;
 728
 729         t = admhc_readl(ahcd, &ahcd->regs->host_control);
 730         if (t & ADMHC_HC_DMAE)
 731                 return;
 732
 733         t |= ADMHC_HC_DMAE;
 734         admhc_writel(ahcd, t, &ahcd->regs->host_control);
 735         admhc_vdbg(ahcd,"DMA enabled\n");
 736 }
 737
 738 static inline void admhc_dma_disable(struct admhcd *ahcd)
 739 {
 740         u32 t;
 741
 742         t = admhc_readl(ahcd, &ahcd->regs->host_control);
 743         if (!(t & ADMHC_HC_DMAE))
 744                 return;
 745
 746         t &= ~ADMHC_HC_DMAE;
 747         admhc_writel(ahcd, t, &ahcd->regs->host_control);
 748         admhc_vdbg(ahcd,"DMA disabled\n");
 749 }