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fix a timeout on amd flash chips (patch from #874)
[openwrt.git] / target / linux / brcm-2.4 / patches / 001-bcm47xx.patch
1 diff -urN linux.old/arch/mips/bcm947xx/bcmsrom.c linux.dev/arch/mips/bcm947xx/bcmsrom.c
2 --- linux.old/arch/mips/bcm947xx/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
3 +++ linux.dev/arch/mips/bcm947xx/bcmsrom.c 2006-10-02 21:19:59.000000000 +0200
4 @@ -0,0 +1,1212 @@
5 +/*
6 + * Misc useful routines to access NIC SROM/OTP .
7 + *
8 + * Copyright 2006, Broadcom Corporation
9 + * All Rights Reserved.
10 + *
11 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15 + * $Id: bcmsrom.c,v 1.1.1.14 2006/04/15 01:28:25 michael Exp $
16 + */
17 +
18 +#include <typedefs.h>
19 +#include <bcmdefs.h>
20 +#include <osl.h>
21 +#include <bcmutils.h>
22 +#include <bcmsrom.h>
23 +#include <bcmdevs.h>
24 +#include <bcmendian.h>
25 +#include <sbpcmcia.h>
26 +#include <pcicfg.h>
27 +#include <sbutils.h>
28 +#include <bcmnvram.h>
29 +
30 +/* debug/trace */
31 +#if defined(WLTEST)
32 +#define BS_ERROR(args) printf args
33 +#else
34 +#define BS_ERROR(args)
35 +#endif /* BCMDBG_ERR || WLTEST */
36 +
37 +#define VARS_MAX 4096 /* should be reduced */
38 +
39 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
40 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
41 +
42 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, uint *count);
43 +static int initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, uint *count);
44 +static int initvars_flash_sb(void *sbh, char **vars, uint *count);
45 +static int srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, char **vars, uint *count);
46 +static int sprom_cmd_pcmcia(osl_t *osh, uint8 cmd);
47 +static int sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data);
48 +static int sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data);
49 +static int sprom_read_pci(osl_t *osh, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords,
50 + bool check_crc);
51 +
52 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
53 +static int initvars_flash(osl_t *osh, char **vp, uint len, char *devpath);
54 +
55 +/*
56 + * Initialize local vars from the right source for this platform.
57 + * Return 0 on success, nonzero on error.
58 + */
59 +int
60 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, uint *count)
61 +{
62 + ASSERT(bustype == BUSTYPE(bustype));
63 + if (vars == NULL || count == NULL)
64 + return (0);
65 +
66 + switch (BUSTYPE(bustype)) {
67 + case SB_BUS:
68 + case JTAG_BUS:
69 + return initvars_flash_sb(sbh, vars, count);
70 +
71 + case PCI_BUS:
72 + ASSERT(curmap); /* can not be NULL */
73 + return initvars_srom_pci(sbh, curmap, vars, count);
74 +
75 + case PCMCIA_BUS:
76 + return initvars_cis_pcmcia(sbh, osh, vars, count);
77 +
78 +
79 + default:
80 + ASSERT(0);
81 + }
82 + return (-1);
83 +}
84 +
85 +/* support only 16-bit word read from srom */
86 +int
87 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
88 +{
89 + void *srom;
90 + uint i, off, nw;
91 +
92 + ASSERT(bustype == BUSTYPE(bustype));
93 +
94 + /* check input - 16-bit access only */
95 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
96 + return 1;
97 +
98 + off = byteoff / 2;
99 + nw = nbytes / 2;
100 +
101 + if (BUSTYPE(bustype) == PCI_BUS) {
102 + if (!curmap)
103 + return 1;
104 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
105 + if (sprom_read_pci(osh, srom, off, buf, nw, FALSE))
106 + return 1;
107 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
108 + for (i = 0; i < nw; i++) {
109 + if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
110 + return 1;
111 + }
112 + } else {
113 + return 1;
114 + }
115 +
116 + return 0;
117 +}
118 +
119 +/* support only 16-bit word write into srom */
120 +int
121 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
122 +{
123 + uint16 *srom;
124 + uint i, nw, crc_range;
125 + uint16 image[SPROM_SIZE];
126 + uint8 crc;
127 + volatile uint32 val32;
128 +
129 + ASSERT(bustype == BUSTYPE(bustype));
130 +
131 + /* check input - 16-bit access only */
132 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
133 + return 1;
134 +
135 + /* Are we writing the whole thing at once? */
136 + if ((byteoff == 0) &&
137 + ((nbytes == SPROM_SIZE) ||
138 + (nbytes == (SPROM_CRC_RANGE * 2)) ||
139 + (nbytes == (SROM4_WORDS * 2)))) {
140 + crc_range = nbytes;
141 + bcopy((void*)buf, (void*)image, nbytes);
142 + nw = nbytes / 2;
143 + } else {
144 + if ((BUSTYPE(bustype) == PCMCIA_BUS) || (BUSTYPE(bustype) == SDIO_BUS))
145 + crc_range = SPROM_SIZE;
146 + else
147 + crc_range = SPROM_CRC_RANGE * 2; /* Tentative */
148 +
149 + nw = crc_range / 2;
150 + /* read first 64 words from srom */
151 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
152 + return 1;
153 + if (image[SROM4_SIGN] == SROM4_SIGNATURE) {
154 + crc_range = SROM4_WORDS;
155 + nw = crc_range / 2;
156 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
157 + return 1;
158 + }
159 + /* make changes */
160 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
161 + }
162 +
163 + /* calculate crc */
164 + htol16_buf(image, crc_range);
165 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
166 + ltoh16_buf(image, crc_range);
167 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
168 +
169 + if (BUSTYPE(bustype) == PCI_BUS) {
170 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
171 + /* enable writes to the SPROM */
172 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
173 + val32 |= SPROM_WRITEEN;
174 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
175 + bcm_mdelay(WRITE_ENABLE_DELAY);
176 + /* write srom */
177 + for (i = 0; i < nw; i++) {
178 + W_REG(osh, &srom[i], image[i]);
179 + bcm_mdelay(WRITE_WORD_DELAY);
180 + }
181 + /* disable writes to the SPROM */
182 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 &
183 + ~SPROM_WRITEEN);
184 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
185 + /* enable writes to the SPROM */
186 + if (sprom_cmd_pcmcia(osh, SROM_WEN))
187 + return 1;
188 + bcm_mdelay(WRITE_ENABLE_DELAY);
189 + /* write srom */
190 + for (i = 0; i < nw; i++) {
191 + sprom_write_pcmcia(osh, (uint16)(i), image[i]);
192 + bcm_mdelay(WRITE_WORD_DELAY);
193 + }
194 + /* disable writes to the SPROM */
195 + if (sprom_cmd_pcmcia(osh, SROM_WDS))
196 + return 1;
197 + } else {
198 + return 1;
199 + }
200 +
201 + bcm_mdelay(WRITE_ENABLE_DELAY);
202 + return 0;
203 +}
204 +
205 +
206 +static int
207 +srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, char **vars, uint *count)
208 +{
209 + char eabuf[32];
210 + char *vp, *base;
211 + uint8 *cis, tup, tlen, sromrev = 1;
212 + int i, j;
213 + uint varsize;
214 + bool ag_init = FALSE;
215 + uint32 w32;
216 +
217 + ASSERT(vars);
218 + ASSERT(count);
219 +
220 + base = vp = MALLOC(osh, VARS_MAX);
221 + ASSERT(vp);
222 + if (!vp)
223 + return -2;
224 +
225 + while (ciscnt--) {
226 + cis = *pcis++;
227 + i = 0;
228 + do {
229 + tup = cis[i++];
230 + tlen = cis[i++];
231 + if ((i + tlen) >= CIS_SIZE)
232 + break;
233 +
234 + switch (tup) {
235 + case CISTPL_MANFID:
236 + vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
237 + vp++;
238 + vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
239 + vp++;
240 + break;
241 +
242 + case CISTPL_FUNCE:
243 + switch (cis[i]) {
244 + case LAN_NID:
245 + ASSERT(cis[i + 1] == 6);
246 + bcm_ether_ntoa((struct ether_addr *)&cis[i + 2], eabuf);
247 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
248 + vp++;
249 + break;
250 + case 1: /* SDIO Extended Data */
251 + vp += sprintf(vp, "sdmaxblk=%d",
252 + (cis[i + 13] << 8) | cis[i + 12]);
253 + vp++;
254 + break;
255 + }
256 + break;
257 +
258 + case CISTPL_CFTABLE:
259 + vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
260 + vp++;
261 + break;
262 +
263 + case CISTPL_BRCM_HNBU:
264 + switch (cis[i]) {
265 + case HNBU_SROMREV:
266 + sromrev = cis[i + 1];
267 + break;
268 +
269 + case HNBU_CHIPID:
270 + vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) +
271 + cis[i + 1]);
272 + vp++;
273 + vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) +
274 + cis[i + 3]);
275 + vp++;
276 + if (tlen == 7) {
277 + vp += sprintf(vp, "chiprev=%d",
278 + (cis[i + 6] << 8) + cis[i + 5]);
279 + vp++;
280 + }
281 + break;
282 +
283 + case HNBU_BOARDREV:
284 + vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
285 + vp++;
286 + break;
287 +
288 + case HNBU_AA:
289 + vp += sprintf(vp, "aa2g=%d", cis[i + 1]);
290 + vp++;
291 + break;
292 +
293 + case HNBU_AG:
294 + vp += sprintf(vp, "ag0=%d", cis[i + 1]);
295 + vp++;
296 + ag_init = TRUE;
297 + break;
298 +
299 + case HNBU_CC:
300 + ASSERT(sromrev == 1);
301 + vp += sprintf(vp, "cc=%d", cis[i + 1]);
302 + vp++;
303 + break;
304 +
305 + case HNBU_PAPARMS:
306 + if (tlen == 2) {
307 + ASSERT(sromrev == 1);
308 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 1]);
309 + vp++;
310 + } else if (tlen >= 9) {
311 + if (tlen == 10) {
312 + ASSERT(sromrev == 2);
313 + vp += sprintf(vp, "opo=%d", cis[i + 9]);
314 + vp++;
315 + } else
316 + ASSERT(tlen == 9);
317 +
318 + for (j = 0; j < 3; j++) {
319 + vp += sprintf(vp, "pa0b%d=%d", j,
320 + (cis[i + (j * 2) + 2] << 8) +
321 + cis[i + (j * 2) + 1]);
322 + vp++;
323 + }
324 + vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
325 + vp++;
326 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 8]);
327 + vp++;
328 + } else
329 + ASSERT(tlen >= 9);
330 + break;
331 +
332 + case HNBU_OEM:
333 + ASSERT(sromrev == 1);
334 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
335 + cis[i + 1], cis[i + 2],
336 + cis[i + 3], cis[i + 4],
337 + cis[i + 5], cis[i + 6],
338 + cis[i + 7], cis[i + 8]);
339 + vp++;
340 + break;
341 +
342 + case HNBU_BOARDFLAGS:
343 + w32 = (cis[i + 2] << 8) + cis[i + 1];
344 + if (tlen == 5)
345 + w32 |= (cis[i + 4] << 24) + (cis[i + 3] << 16);
346 + vp += sprintf(vp, "boardflags=0x%x", w32);
347 + vp++;
348 + break;
349 +
350 + case HNBU_LEDS:
351 + if (cis[i + 1] != 0xff) {
352 + vp += sprintf(vp, "ledbh0=%d", cis[i + 1]);
353 + vp++;
354 + }
355 + if (cis[i + 2] != 0xff) {
356 + vp += sprintf(vp, "ledbh1=%d", cis[i + 2]);
357 + vp++;
358 + }
359 + if (cis[i + 3] != 0xff) {
360 + vp += sprintf(vp, "ledbh2=%d", cis[i + 3]);
361 + vp++;
362 + }
363 + if (cis[i + 4] != 0xff) {
364 + vp += sprintf(vp, "ledbh3=%d", cis[i + 4]);
365 + vp++;
366 + }
367 + break;
368 +
369 + case HNBU_CCODE:
370 + {
371 + char str[3];
372 + ASSERT(sromrev > 1);
373 + str[0] = cis[i + 1];
374 + str[1] = cis[i + 2];
375 + str[2] = 0;
376 + vp += sprintf(vp, "ccode=%s", str);
377 + vp++;
378 + vp += sprintf(vp, "cctl=0x%x", cis[i + 3]);
379 + vp++;
380 + break;
381 + }
382 +
383 + case HNBU_CCKPO:
384 + ASSERT(sromrev > 2);
385 + vp += sprintf(vp, "cckpo=0x%x",
386 + (cis[i + 2] << 8) | cis[i + 1]);
387 + vp++;
388 + break;
389 +
390 + case HNBU_OFDMPO:
391 + ASSERT(sromrev > 2);
392 + vp += sprintf(vp, "ofdmpo=0x%x",
393 + (cis[i + 4] << 24) |
394 + (cis[i + 3] << 16) |
395 + (cis[i + 2] << 8) |
396 + cis[i + 1]);
397 + vp++;
398 + break;
399 + }
400 + break;
401 +
402 + }
403 + i += tlen;
404 + } while (tup != 0xff);
405 + }
406 +
407 + /* Set the srom version */
408 + vp += sprintf(vp, "sromrev=%d", sromrev);
409 + vp++;
410 +
411 + /* if there is no antenna gain field, set default */
412 + if (ag_init == FALSE) {
413 + ASSERT(sromrev == 1);
414 + vp += sprintf(vp, "ag0=%d", 0xff);
415 + vp++;
416 + }
417 +
418 + /* final nullbyte terminator */
419 + *vp++ = '\0';
420 + varsize = (uint)(vp - base);
421 +
422 + ASSERT((vp - base) < VARS_MAX);
423 +
424 + if (varsize == VARS_MAX) {
425 + *vars = base;
426 + } else {
427 + vp = MALLOC(osh, varsize);
428 + ASSERT(vp);
429 + if (vp)
430 + bcopy(base, vp, varsize);
431 + MFREE(osh, base, VARS_MAX);
432 + *vars = vp;
433 + if (!vp) {
434 + *count = 0;
435 + return -2;
436 + }
437 + }
438 + *count = varsize;
439 +
440 + return (0);
441 +}
442 +
443 +
444 +/* set PCMCIA sprom command register */
445 +static int
446 +sprom_cmd_pcmcia(osl_t *osh, uint8 cmd)
447 +{
448 + uint8 status = 0;
449 + uint wait_cnt = 1000;
450 +
451 + /* write sprom command register */
452 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
453 +
454 + /* wait status */
455 + while (wait_cnt--) {
456 + OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
457 + if (status & SROM_DONE)
458 + return 0;
459 + }
460 +
461 + return 1;
462 +}
463 +
464 +/* read a word from the PCMCIA srom */
465 +static int
466 +sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data)
467 +{
468 + uint8 addr_l, addr_h, data_l, data_h;
469 +
470 + addr_l = (uint8)((addr * 2) & 0xff);
471 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
472 +
473 + /* set address */
474 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
475 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
476 +
477 + /* do read */
478 + if (sprom_cmd_pcmcia(osh, SROM_READ))
479 + return 1;
480 +
481 + /* read data */
482 + data_h = data_l = 0;
483 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
484 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
485 +
486 + *data = (data_h << 8) | data_l;
487 + return 0;
488 +}
489 +
490 +/* write a word to the PCMCIA srom */
491 +static int
492 +sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data)
493 +{
494 + uint8 addr_l, addr_h, data_l, data_h;
495 +
496 + addr_l = (uint8)((addr * 2) & 0xff);
497 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
498 + data_l = (uint8)(data & 0xff);
499 + data_h = (uint8)((data >> 8) & 0xff);
500 +
501 + /* set address */
502 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
503 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
504 +
505 + /* write data */
506 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
507 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
508 +
509 + /* do write */
510 + return sprom_cmd_pcmcia(osh, SROM_WRITE);
511 +}
512 +
513 +/*
514 + * Read in and validate sprom.
515 + * Return 0 on success, nonzero on error.
516 + */
517 +static int
518 +sprom_read_pci(osl_t *osh, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
519 +{
520 + int err = 0;
521 + uint i;
522 +
523 + /* read the sprom */
524 + for (i = 0; i < nwords; i++)
525 + buf[i] = R_REG(osh, &sprom[wordoff + i]);
526 +
527 + if (check_crc) {
528 + /* fixup the endianness so crc8 will pass */
529 + htol16_buf(buf, nwords * 2);
530 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
531 + err = 1;
532 + /* now correct the endianness of the byte array */
533 + ltoh16_buf(buf, nwords * 2);
534 + }
535 +
536 + return err;
537 +}
538 +
539 +/*
540 +* Create variable table from memory.
541 +* Return 0 on success, nonzero on error.
542 +*/
543 +static int
544 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
545 +{
546 + int c = (int)(end - start);
547 +
548 + /* do it only when there is more than just the null string */
549 + if (c > 1) {
550 + char *vp = MALLOC(osh, c);
551 + ASSERT(vp);
552 + if (!vp)
553 + return BCME_NOMEM;
554 + bcopy(start, vp, c);
555 + *vars = vp;
556 + *count = c;
557 + }
558 + else {
559 + *vars = NULL;
560 + *count = 0;
561 + }
562 +
563 + return 0;
564 +}
565 +
566 +/*
567 + * Find variables with <devpath> from flash. 'base' points to the beginning
568 + * of the table upon enter and to the end of the table upon exit when success.
569 + * Return 0 on success, nonzero on error.
570 + */
571 +static int
572 +initvars_flash(osl_t *osh, char **base, uint len, char *devpath)
573 +{
574 + char *vp = *base;
575 + char *flash;
576 + int err;
577 + char *s;
578 + uint l, dl, copy_len;
579 +
580 + /* allocate memory and read in flash */
581 + if (!(flash = MALLOC(osh, NVRAM_SPACE)))
582 + return BCME_NOMEM;
583 + if ((err = nvram_getall(flash, NVRAM_SPACE)))
584 + goto exit;
585 +
586 + /* grab vars with the <devpath> prefix in name */
587 + dl = strlen(devpath);
588 + for (s = flash; s && *s; s += l + 1) {
589 + l = strlen(s);
590 +
591 + /* skip non-matching variable */
592 + if (strncmp(s, devpath, dl))
593 + continue;
594 +
595 + /* is there enough room to copy? */
596 + copy_len = l - dl + 1;
597 + if (len < copy_len) {
598 + err = BCME_BUFTOOSHORT;
599 + goto exit;
600 + }
601 +
602 + /* no prefix, just the name=value */
603 + strcpy(vp, &s[dl]);
604 + vp += copy_len;
605 + len -= copy_len;
606 + }
607 +
608 + /* add null string as terminator */
609 + if (len < 1) {
610 + err = BCME_BUFTOOSHORT;
611 + goto exit;
612 + }
613 + *vp++ = '\0';
614 +
615 + *base = vp;
616 +
617 +exit: MFREE(osh, flash, NVRAM_SPACE);
618 + return err;
619 +}
620 +
621 +/*
622 + * Initialize nonvolatile variable table from flash.
623 + * Return 0 on success, nonzero on error.
624 + */
625 +static int
626 +initvars_flash_sb(void *sbh, char **vars, uint *count)
627 +{
628 + osl_t *osh = sb_osh(sbh);
629 + char devpath[SB_DEVPATH_BUFSZ];
630 + char *vp, *base;
631 + int err;
632 +
633 + ASSERT(vars);
634 + ASSERT(count);
635 +
636 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
637 + return err;
638 +
639 + base = vp = MALLOC(osh, VARS_MAX);
640 + ASSERT(vp);
641 + if (!vp)
642 + return BCME_NOMEM;
643 +
644 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
645 + goto err;
646 +
647 + err = initvars_table(osh, base, vp, vars, count);
648 +
649 +err: MFREE(osh, base, VARS_MAX);
650 + return err;
651 +}
652 +
653 +#ifdef WLTEST
654 +char mfgsromvars[256];
655 +char *defaultsromvars = "il0macaddr=00:11:22:33:44:51\0"
656 + "et0macaddr=00:11:22:33:44:52\0"
657 + "et1macaddr=00:11:22:33:44:53\0"
658 + "boardtype=0xffff\0"
659 + "boardrev=0x10\0"
660 + "boardflags=8\0"
661 + "sromrev=2\0"
662 + "aa2g=3";
663 +#define MFGSROM_DEFVARSLEN 147 /* default srom len */
664 +#endif /* WL_TEST */
665 +
666 +/*
667 + * Initialize nonvolatile variable table from sprom.
668 + * Return 0 on success, nonzero on error.
669 + */
670 +static int
671 +initvars_srom_pci(void *sbh, void *curmap, char **vars, uint *count)
672 +{
673 + uint16 w, *b;
674 + uint8 sromrev = 0;
675 + struct ether_addr ea;
676 + char eabuf[32];
677 + uint32 w32;
678 + int woff, i;
679 + char *vp, *base;
680 + osl_t *osh = sb_osh(sbh);
681 + bool flash = FALSE;
682 + char name[SB_DEVPATH_BUFSZ+16], *value;
683 + char devpath[SB_DEVPATH_BUFSZ];
684 + int err;
685 +
686 + /*
687 + * Apply CRC over SROM content regardless SROM is present or not,
688 + * and use variable <devpath>sromrev's existance in flash to decide
689 + * if we should return an error when CRC fails or read SROM variables
690 + * from flash.
691 + */
692 + b = MALLOC(osh, SROM_MAX);
693 + ASSERT(b);
694 + if (!b)
695 + return -2;
696 +
697 + err = sprom_read_pci(osh, (void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b,
698 + 64, TRUE);
699 + if (err == 0) {
700 + /* srom is good and is rev < 4 */
701 + /* top word of sprom contains version and crc8 */
702 + sromrev = b[63] & 0xff;
703 + /* bcm4401 sroms misprogrammed */
704 + if (sromrev == 0x10)
705 + sromrev = 1;
706 + } else if (b[SROM4_SIGN] == SROM4_SIGNATURE) {
707 + /* If sromrev >= 4, read more */
708 + err = sprom_read_pci(osh, (void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b,
709 + SROM4_WORDS, TRUE);
710 + sromrev = b[SROM4_WORDS - 1] & 0xff;
711 + }
712 +
713 + if (err) {
714 +#ifdef WLTEST
715 + BS_ERROR(("SROM Crc Error, so see if we could use a default\n"));
716 + w32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
717 + if (w32 & SPROM_OTPIN_USE) {
718 + BS_ERROR(("srom crc failed with OTP, use default vars....\n"));
719 + vp = base = mfgsromvars;
720 + if (sb_chip(sbh) == BCM4311_CHIP_ID) {
721 + BS_ERROR(("setting the devid to be 4311\n"));
722 + vp += sprintf(vp, "devid=0x4311");
723 + vp++;
724 + }
725 + bcopy(defaultsromvars, vp, MFGSROM_DEFVARSLEN);
726 + vp += MFGSROM_DEFVARSLEN;
727 + goto varsdone;
728 + } else {
729 + BS_ERROR(("srom crc failed with SPROM....\n"));
730 +#endif /* WLTEST */
731 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
732 + return err;
733 + sprintf(name, "%ssromrev", devpath);
734 + if (!(value = getvar(NULL, name)))
735 + return (-1);
736 + sromrev = (uint8)bcm_strtoul(value, NULL, 0);
737 + flash = TRUE;
738 +#ifdef WLTEST
739 + }
740 +#endif /* WLTEST */
741 + }
742 +
743 + /* srom version check */
744 + if (sromrev > 4)
745 + return (-2);
746 +
747 + ASSERT(vars);
748 + ASSERT(count);
749 +
750 + base = vp = MALLOC(osh, VARS_MAX);
751 + ASSERT(vp);
752 + if (!vp)
753 + return -2;
754 +
755 + /* read variables from flash */
756 + if (flash) {
757 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
758 + goto err;
759 + goto varsdone;
760 + }
761 +
762 + vp += sprintf(vp, "sromrev=%d", sromrev);
763 + vp++;
764 +
765 + if (sromrev >= 4) {
766 + uint path, pathbase;
767 + const uint pathbases[MAX_PATH] = {SROM4_PATH0, SROM4_PATH1,
768 + SROM4_PATH2, SROM4_PATH3};
769 +
770 + vp += sprintf(vp, "boardrev=%d", b[SROM4_BREV]);
771 + vp++;
772 +
773 + vp += sprintf(vp, "boardflags=%d", (b[SROM4_BFL1] << 16) | b[SROM4_BFL0]);
774 + vp++;
775 +
776 + vp += sprintf(vp, "boardflags2=%d", (b[SROM4_BFL3] << 16) | b[SROM4_BFL2]);
777 + vp++;
778 +
779 + /* The macaddr */
780 + ea.octet[0] = (b[SROM4_MACHI] >> 8) & 0xff;
781 + ea.octet[1] = b[SROM4_MACHI] & 0xff;
782 + ea.octet[2] = (b[SROM4_MACMID] >> 8) & 0xff;
783 + ea.octet[3] = b[SROM4_MACMID] & 0xff;
784 + ea.octet[4] = (b[SROM4_MACLO] >> 8) & 0xff;
785 + ea.octet[5] = b[SROM4_MACLO] & 0xff;
786 + bcm_ether_ntoa(&ea, eabuf);
787 + vp += sprintf(vp, "macaddr=%s", eabuf);
788 + vp++;
789 +
790 + w = b[SROM4_CCODE];
791 + if (w == 0)
792 + vp += sprintf(vp, "ccode=");
793 + else
794 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
795 + vp++;
796 + vp += sprintf(vp, "regrev=%d", b[SROM4_REGREV]);
797 + vp++;
798 +
799 + w = b[SROM4_LEDBH10];
800 + if ((w != 0) && (w != 0xffff)) {
801 + /* ledbh0 */
802 + vp += sprintf(vp, "ledbh0=%d", (w & 0xff));
803 + vp++;
804 +
805 + /* ledbh1 */
806 + vp += sprintf(vp, "ledbh1=%d", (w >> 8) & 0xff);
807 + vp++;
808 + }
809 + w = b[SROM4_LEDBH32];
810 + if ((w != 0) && (w != 0xffff)) {
811 + /* ledbh2 */
812 + vp += sprintf(vp, "ledbh2=%d", w & 0xff);
813 + vp++;
814 +
815 + /* ledbh3 */
816 + vp += sprintf(vp, "ledbh3=%d", (w >> 8) & 0xff);
817 + vp++;
818 + }
819 + /* LED Powersave duty cycle (oncount >> 24) (offcount >> 8) */
820 + w = b[SROM4_LEDDC];
821 + w32 = ((uint32)((unsigned char)(w >> 8) & 0xff) << 24) | /* oncount */
822 + ((uint32)((unsigned char)(w & 0xff)) << 8); /* offcount */
823 + vp += sprintf(vp, "leddc=%d", w32);
824 + vp++;
825 +
826 + w = b[SROM4_AA];
827 + vp += sprintf(vp, "aa2g=%d", w & SROM4_AA2G_MASK);
828 + vp++;
829 + vp += sprintf(vp, "aa5g=%d", w >> SROM4_AA5G_SHIFT);
830 + vp++;
831 +
832 + w = b[SROM4_AG10];
833 + vp += sprintf(vp, "ag0=%d", w & 0xff);
834 + vp++;
835 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
836 + vp++;
837 + w = b[SROM4_AG32];
838 + vp += sprintf(vp, "ag2=%d", w & 0xff);
839 + vp++;
840 + vp += sprintf(vp, "ag3=%d", (w >> 8) & 0xff);
841 + vp++;
842 +
843 + /* Fixed power indices when power control is disabled */
844 + for (i = 0; i < 2; i++) {
845 + w = b[SROM4_TXPID2G + i];
846 + vp += sprintf(vp, "txpid2ga%d=%d", 2 * i, w & 0xff);
847 + vp++;
848 + vp += sprintf(vp, "txpid2ga%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
849 + vp++;
850 + w = b[SROM4_TXPID5G + i];
851 + vp += sprintf(vp, "txpid5ga%d=%d", 2 * i, w & 0xff);
852 + vp++;
853 + vp += sprintf(vp, "txpid5ga%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
854 + vp++;
855 + w = b[SROM4_TXPID5GL + i];
856 + vp += sprintf(vp, "txpid5gla%d=%d", 2 * i, w & 0xff);
857 + vp++;
858 + vp += sprintf(vp, "txpid5gla%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
859 + vp++;
860 + w = b[SROM4_TXPID5GH + i];
861 + vp += sprintf(vp, "txpid5gha%d=%d", 2 * i, w & 0xff);
862 + vp++;
863 + vp += sprintf(vp, "txpid5gha%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
864 + vp++;
865 + }
866 +
867 + /* Per path variables */
868 + for (path = 0; path < MAX_PATH; path++) {
869 + pathbase = pathbases[path];
870 + w = b[pathbase + SROM4_2G_ITT_MAXP];
871 + vp += sprintf(vp, "itt2ga%d=%d", path, w >> B2G_ITT_SHIFT);
872 + vp++;
873 + vp += sprintf(vp, "maxp2ga%d=%d", path, w & B2G_MAXP_MASK);
874 + vp++;
875 +
876 + for (i = 0; i < 4; i++) {
877 + vp += sprintf(vp, "pa2gw%da%d=%d", i, path,
878 + b[pathbase + SROM4_2G_PA + i]);
879 + vp++;
880 + }
881 +
882 + w = b[pathbase + SROM4_5G_ITT_MAXP];
883 + vp += sprintf(vp, "itt5ga%d=%d", path, w >> B5G_ITT_SHIFT);
884 + vp++;
885 + vp += sprintf(vp, "maxp5ga%d=%d", path, w & B5G_MAXP_MASK);
886 + vp++;
887 +
888 + w = b[pathbase + SROM4_5GLH_MAXP];
889 + vp += sprintf(vp, "maxp5lga%d=%d", path, w >> B5GL_MAXP_SHIFT);
890 + vp++;
891 + vp += sprintf(vp, "maxp5gha%d=%d", path, w & B5GH_MAXP_MASK);
892 + vp++;
893 +
894 + for (i = 0; i < 4; i++) {
895 + vp += sprintf(vp, "pa5gw%da%d=%d", i, path,
896 + b[pathbase + SROM4_5G_PA + i]);
897 + vp++;
898 + vp += sprintf(vp, "pa5glw%da%d=%d", i, path,
899 + b[pathbase + SROM4_5GL_PA + i]);
900 + vp++;
901 + vp += sprintf(vp, "pa5hgw%da%d=%d", i, path,
902 + b[pathbase + SROM4_5GH_PA + i]);
903 + vp++;
904 + }
905 + }
906 +
907 + vp += sprintf(vp, "cck2gpo=%d", b[SROM4_2G_CCKPO]);
908 + vp++;
909 +
910 + w32 = ((uint32)b[SROM4_2G_OFDMPO + 1] << 16) | b[SROM4_2G_OFDMPO];
911 + vp += sprintf(vp, "ofdm2gpo=%d", w32);
912 + vp++;
913 +
914 + w32 = ((uint32)b[SROM4_5G_OFDMPO + 1] << 16) | b[SROM4_5G_OFDMPO];
915 + vp += sprintf(vp, "ofdm5gpo=%d", w32);
916 + vp++;
917 +
918 + w32 = ((uint32)b[SROM4_5GL_OFDMPO + 1] << 16) | b[SROM4_5GL_OFDMPO];
919 + vp += sprintf(vp, "ofdm5glpo=%d", w32);
920 + vp++;
921 +
922 + w32 = ((uint32)b[SROM4_5GH_OFDMPO + 1] << 16) | b[SROM4_5GH_OFDMPO];
923 + vp += sprintf(vp, "ofdm5ghpo=%d", w32);
924 + vp++;
925 +
926 + for (i = 0; i < 8; i++) {
927 + vp += sprintf(vp, "mcs2gpo%d=%d", i, b[SROM4_2G_MCSPO]);
928 + vp++;
929 + vp += sprintf(vp, "mcs5gpo%d=%d", i, b[SROM4_5G_MCSPO]);
930 + vp++;
931 + vp += sprintf(vp, "mcs5glpo%d=%d", i, b[SROM4_5GL_MCSPO]);
932 + vp++;
933 + vp += sprintf(vp, "mcs5ghpo%d=%d", i, b[SROM4_5GH_MCSPO]);
934 + vp++;
935 + }
936 +
937 + vp += sprintf(vp, "ccdpo%d=%d", i, b[SROM4_CCDPO]);
938 + vp++;
939 + vp += sprintf(vp, "stbcpo%d=%d", i, b[SROM4_STBCPO]);
940 + vp++;
941 + vp += sprintf(vp, "bw40po%d=%d", i, b[SROM4_BW40PO]);
942 + vp++;
943 + vp += sprintf(vp, "bwduppo%d=%d", i, b[SROM4_BWDUPPO]);
944 + vp++;
945 +
946 + goto done;
947 + }
948 + if (sromrev >= 3) {
949 + /* New section takes over the 3th hardware function space */
950 +
951 + /* Words 22+23 are 11a (mid) ofdm power offsets */
952 + w32 = ((uint32)b[23] << 16) | b[22];
953 + vp += sprintf(vp, "ofdmapo=%d", w32);
954 + vp++;
955 +
956 + /* Words 24+25 are 11a (low) ofdm power offsets */
957 + w32 = ((uint32)b[25] << 16) | b[24];
958 + vp += sprintf(vp, "ofdmalpo=%d", w32);
959 + vp++;
960 +
961 + /* Words 26+27 are 11a (high) ofdm power offsets */
962 + w32 = ((uint32)b[27] << 16) | b[26];
963 + vp += sprintf(vp, "ofdmahpo=%d", w32);
964 + vp++;
965 +
966 + /* LED Powersave duty cycle (oncount >> 24) (offcount >> 8) */
967 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xff) << 24) | /* oncount */
968 + ((uint32)((unsigned char)(b[21] & 0xff)) << 8); /* offcount */
969 + vp += sprintf(vp, "leddc=%d", w32);
970 +
971 + vp++;
972 + }
973 +
974 + if (sromrev >= 2) {
975 + /* New section takes over the 4th hardware function space */
976 +
977 + /* Word 29 is max power 11a high/low */
978 + w = b[29];
979 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
980 + vp++;
981 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
982 + vp++;
983 +
984 + /* Words 30-32 set the 11alow pa settings,
985 + * 33-35 are the 11ahigh ones.
986 + */
987 + for (i = 0; i < 3; i++) {
988 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
989 + vp++;
990 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
991 + vp++;
992 + }
993 + w = b[59];
994 + if (w == 0)
995 + vp += sprintf(vp, "ccode=");
996 + else
997 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
998 + vp++;
999 +
1000 + }
1001 +
1002 + /* parameter section of sprom starts at byte offset 72 */
1003 + woff = 72/2;
1004 +
1005 + /* first 6 bytes are il0macaddr */
1006 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1007 + ea.octet[1] = b[woff] & 0xff;
1008 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1009 + ea.octet[3] = b[woff+1] & 0xff;
1010 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1011 + ea.octet[5] = b[woff+2] & 0xff;
1012 + woff += 3;
1013 + bcm_ether_ntoa(&ea, eabuf);
1014 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
1015 + vp++;
1016 +
1017 + /* next 6 bytes are et0macaddr */
1018 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1019 + ea.octet[1] = b[woff] & 0xff;
1020 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1021 + ea.octet[3] = b[woff+1] & 0xff;
1022 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1023 + ea.octet[5] = b[woff+2] & 0xff;
1024 + woff += 3;
1025 + bcm_ether_ntoa(&ea, eabuf);
1026 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
1027 + vp++;
1028 +
1029 + /* next 6 bytes are et1macaddr */
1030 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1031 + ea.octet[1] = b[woff] & 0xff;
1032 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1033 + ea.octet[3] = b[woff+1] & 0xff;
1034 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1035 + ea.octet[5] = b[woff+2] & 0xff;
1036 + woff += 3;
1037 + bcm_ether_ntoa(&ea, eabuf);
1038 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
1039 + vp++;
1040 +
1041 + /*
1042 + * Enet phy settings one or two singles or a dual
1043 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
1044 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
1045 + * Bit 14 : Mdio for enet0
1046 + * Bit 15 : Mdio for enet1
1047 + */
1048 + w = b[woff];
1049 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
1050 + vp++;
1051 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
1052 + vp++;
1053 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
1054 + vp++;
1055 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
1056 + vp++;
1057 +
1058 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
1059 + w = b[46];
1060 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
1061 + vp++;
1062 +
1063 + if (sromrev > 1)
1064 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
1065 + else
1066 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
1067 + vp++;
1068 +
1069 + vp += sprintf(vp, "aa2g=%d", (w >> 12) & 0x3);
1070 + vp++;
1071 +
1072 + vp += sprintf(vp, "aa5g=%d", (w >> 14) & 0x3);
1073 + vp++;
1074 +
1075 + /* Words 47-49 set the (wl) pa settings */
1076 + woff = 47;
1077 +
1078 + for (i = 0; i < 3; i++) {
1079 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
1080 + vp++;
1081 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
1082 + vp++;
1083 + }
1084 +
1085 + /*
1086 + * Words 50-51 set the customer-configured wl led behavior.
1087 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
1088 + * LED behavior values defined in wlioctl.h .
1089 + */
1090 + w = b[50];
1091 + if ((w != 0) && (w != 0xffff)) {
1092 + /* ledbh0 */
1093 + vp += sprintf(vp, "ledbh0=%d", (w & 0xff));
1094 + vp++;
1095 +
1096 + /* ledbh1 */
1097 + vp += sprintf(vp, "ledbh1=%d", (w >> 8) & 0xff);
1098 + vp++;
1099 + }
1100 + w = b[51];
1101 + if ((w != 0) && (w != 0xffff)) {
1102 + /* ledbh2 */
1103 + vp += sprintf(vp, "ledbh2=%d", w & 0xff);
1104 + vp++;
1105 +
1106 + /* ledbh */
1107 + vp += sprintf(vp, "ledbh3=%d", (w >> 8) & 0xff);
1108 + vp++;
1109 + }
1110 +
1111 + /* Word 52 is max power 0/1 */
1112 + w = b[52];
1113 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
1114 + vp++;
1115 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
1116 + vp++;
1117 +
1118 + /* Word 56 is idle tssi target 0/1 */
1119 + w = b[56];
1120 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
1121 + vp++;
1122 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
1123 + vp++;
1124 +
1125 + /* Word 57 is boardflags, if not programmed make it zero */
1126 + w32 = (uint32)b[57];
1127 + if (w32 == 0xffff) w32 = 0;
1128 + if (sromrev > 1) {
1129 + /* Word 28 is the high bits of boardflags */
1130 + w32 |= (uint32)b[28] << 16;
1131 + }
1132 + vp += sprintf(vp, "boardflags=%d", w32);
1133 + vp++;
1134 +
1135 + /* Word 58 is antenna gain 0/1 */
1136 + w = b[58];
1137 + vp += sprintf(vp, "ag0=%d", w & 0xff);
1138 + vp++;
1139 +
1140 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
1141 + vp++;
1142 +
1143 + if (sromrev == 1) {
1144 + /* set the oem string */
1145 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
1146 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
1147 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
1148 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
1149 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
1150 + vp++;
1151 + } else if (sromrev == 2) {
1152 + /* Word 60 OFDM tx power offset from CCK level */
1153 + /* OFDM Power Offset - opo */
1154 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
1155 + vp++;
1156 + } else {
1157 + /* Word 60: cck power offsets */
1158 + vp += sprintf(vp, "cckpo=%d", b[60]);
1159 + vp++;
1160 +
1161 + /* Words 61+62: 11g ofdm power offsets */
1162 + w32 = ((uint32)b[62] << 16) | b[61];
1163 + vp += sprintf(vp, "ofdmgpo=%d", w32);
1164 + vp++;
1165 + }
1166 +
1167 + /* final nullbyte terminator */
1168 +done: *vp++ = '\0';
1169 +
1170 + ASSERT((vp - base) <= VARS_MAX);
1171 +
1172 +varsdone:
1173 + err = initvars_table(osh, base, vp, vars, count);
1174 +
1175 +err:
1176 +#ifdef WLTEST
1177 + if (base != mfgsromvars)
1178 +#endif
1179 + MFREE(osh, base, VARS_MAX);
1180 + MFREE(osh, b, SROM_MAX);
1181 + return err;
1182 +}
1183 +
1184 +/*
1185 + * Read the cis and call parsecis to initialize the vars.
1186 + * Return 0 on success, nonzero on error.
1187 + */
1188 +static int
1189 +initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, uint *count)
1190 +{
1191 + uint8 *cis = NULL;
1192 + int rc;
1193 + uint data_sz;
1194 +
1195 + data_sz = (sb_pcmciarev(sbh) == 1) ? (SPROM_SIZE * 2) : CIS_SIZE;
1196 +
1197 + if ((cis = MALLOC(osh, data_sz)) == NULL)
1198 + return (-2);
1199 +
1200 + if (sb_pcmciarev(sbh) == 1) {
1201 + if (srom_read(PCMCIA_BUS, (void *)NULL, osh, 0, data_sz, (uint16 *)cis)) {
1202 + MFREE(osh, cis, data_sz);
1203 + return (-1);
1204 + }
1205 + /* fix up endianess for 16-bit data vs 8-bit parsing */
1206 + ltoh16_buf((uint16 *)cis, data_sz);
1207 + } else
1208 + OSL_PCMCIA_READ_ATTR(osh, 0, cis, data_sz);
1209 +
1210 + rc = srom_parsecis(osh, &cis, 1, vars, count);
1211 +
1212 + MFREE(osh, cis, data_sz);
1213 +
1214 + return (rc);
1215 +}
1216 +
1217 diff -urN linux.old/arch/mips/bcm947xx/bcmutils.c linux.dev/arch/mips/bcm947xx/bcmutils.c
1218 --- linux.old/arch/mips/bcm947xx/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
1219 +++ linux.dev/arch/mips/bcm947xx/bcmutils.c 2006-10-02 21:19:59.000000000 +0200
1220 @@ -0,0 +1,247 @@
1221 +/*
1222 + * Misc useful OS-independent routines.
1223 + *
1224 + * Copyright 2006, Broadcom Corporation
1225 + * All Rights Reserved.
1226 + *
1227 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1228 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1229 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1230 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1231 + * $Id: bcmutils.c,v 1.1.1.12 2006/02/27 03:43:16 honor Exp $
1232 + */
1233 +
1234 +#include <typedefs.h>
1235 +#include <bcmdefs.h>
1236 +#include <stdarg.h>
1237 +#include <bcmutils.h>
1238 +#include <osl.h>
1239 +#include <sbutils.h>
1240 +#include <bcmnvram.h>
1241 +#include <bcmendian.h>
1242 +#include <bcmdevs.h>
1243 +
1244 +unsigned char bcm_ctype[] = {
1245 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
1246 + _BCM_C, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C,
1247 + _BCM_C, /* 8-15 */
1248 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
1249 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
1250 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
1251 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
1252 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
1253 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
1254 + _BCM_P, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X,
1255 + _BCM_U|_BCM_X, _BCM_U, /* 64-71 */
1256 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
1257 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
1258 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
1259 + _BCM_P, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X,
1260 + _BCM_L|_BCM_X, _BCM_L, /* 96-103 */
1261 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
1262 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
1263 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
1264 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 128-143 */
1265 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 144-159 */
1266 + _BCM_S|_BCM_SP, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
1267 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 160-175 */
1268 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
1269 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 176-191 */
1270 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U,
1271 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, /* 192-207 */
1272 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_P, _BCM_U, _BCM_U, _BCM_U,
1273 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_L, /* 208-223 */
1274 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L,
1275 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, /* 224-239 */
1276 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_P, _BCM_L, _BCM_L, _BCM_L,
1277 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L /* 240-255 */
1278 +};
1279 +
1280 +
1281 +ulong
1282 +bcm_strtoul(char *cp, char **endp, uint base)
1283 +{
1284 + ulong result, value;
1285 + bool minus;
1286 +
1287 + minus = FALSE;
1288 +
1289 + while (bcm_isspace(*cp))
1290 + cp++;
1291 +
1292 + if (cp[0] == '+')
1293 + cp++;
1294 + else if (cp[0] == '-') {
1295 + minus = TRUE;
1296 + cp++;
1297 + }
1298 +
1299 + if (base == 0) {
1300 + if (cp[0] == '0') {
1301 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
1302 + base = 16;
1303 + cp = &cp[2];
1304 + } else {
1305 + base = 8;
1306 + cp = &cp[1];
1307 + }
1308 + } else
1309 + base = 10;
1310 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
1311 + cp = &cp[2];
1312 + }
1313 +
1314 + result = 0;
1315 +
1316 + while (bcm_isxdigit(*cp) &&
1317 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
1318 + result = result*base + value;
1319 + cp++;
1320 + }
1321 +
1322 + if (minus)
1323 + result = (ulong)(result * -1);
1324 +
1325 + if (endp)
1326 + *endp = (char *)cp;
1327 +
1328 + return (result);
1329 +}
1330 +
1331 +uchar
1332 +bcm_toupper(uchar c)
1333 +{
1334 + if (bcm_islower(c))
1335 + c -= 'a'-'A';
1336 + return (c);
1337 +}
1338 +
1339 +char*
1340 +bcm_ether_ntoa(struct ether_addr *ea, char *buf)
1341 +{
1342 + sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
1343 + ea->octet[0]&0xff, ea->octet[1]&0xff, ea->octet[2]&0xff,
1344 + ea->octet[3]&0xff, ea->octet[4]&0xff, ea->octet[5]&0xff);
1345 + return (buf);
1346 +}
1347 +
1348 +
1349 +/*
1350 + * Search the name=value vars for a specific one and return its value.
1351 + * Returns NULL if not found.
1352 + */
1353 +char*
1354 +getvar(char *vars, char *name)
1355 +{
1356 + char *s;
1357 + int len;
1358 +
1359 + len = strlen(name);
1360 +
1361 + /* first look in vars[] */
1362 + for (s = vars; s && *s;) {
1363 + /* CSTYLED */
1364 + if ((memcmp(s, name, len) == 0) && (s[len] == '='))
1365 + return (&s[len+1]);
1366 +
1367 + while (*s++)
1368 + ;
1369 + }
1370 +
1371 + /* then query nvram */
1372 + return (nvram_get(name));
1373 +}
1374 +
1375 +/*
1376 + * Search the vars for a specific one and return its value as
1377 + * an integer. Returns 0 if not found.
1378 + */
1379 +int
1380 +getintvar(char *vars, char *name)
1381 +{
1382 + char *val;
1383 +
1384 + if ((val = getvar(vars, name)) == NULL)
1385 + return (0);
1386 +
1387 + return (bcm_strtoul(val, NULL, 0));
1388 +}
1389 +
1390 +
1391 +/*******************************************************************************
1392 + * crc8
1393 + *
1394 + * Computes a crc8 over the input data using the polynomial:
1395 + *
1396 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
1397 + *
1398 + * The caller provides the initial value (either CRC8_INIT_VALUE
1399 + * or the previous returned value) to allow for processing of
1400 + * discontiguous blocks of data. When generating the CRC the
1401 + * caller is responsible for complementing the final return value
1402 + * and inserting it into the byte stream. When checking, a final
1403 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
1404 + *
1405 + * Reference: Dallas Semiconductor Application Note 27
1406 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
1407 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
1408 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
1409 + *
1410 + * ****************************************************************************
1411 + */
1412 +
1413 +static uint8 crc8_table[256] = {
1414 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
1415 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
1416 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
1417 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
1418 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
1419 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
1420 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
1421 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
1422 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
1423 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
1424 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
1425 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
1426 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
1427 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
1428 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
1429 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
1430 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
1431 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
1432 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
1433 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
1434 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
1435 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
1436 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
1437 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
1438 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
1439 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
1440 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
1441 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
1442 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
1443 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
1444 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
1445 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
1446 +};
1447 +
1448 +#define CRC_INNER_LOOP(n, c, x) \
1449 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
1450 +
1451 +uint8
1452 +hndcrc8(
1453 + uint8 *pdata, /* pointer to array of data to process */
1454 + uint nbytes, /* number of input data bytes to process */
1455 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
1456 +)
1457 +{
1458 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
1459 + * to avoid the undefined and unnecessary (uint8 >> 8) operation.
1460 + */
1461 + while (nbytes-- > 0)
1462 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
1463 +
1464 + return crc;
1465 +}
1466 +
1467 +
1468 diff -urN linux.old/arch/mips/bcm947xx/cfe_env.c linux.dev/arch/mips/bcm947xx/cfe_env.c
1469 --- linux.old/arch/mips/bcm947xx/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
1470 +++ linux.dev/arch/mips/bcm947xx/cfe_env.c 2006-10-02 21:19:59.000000000 +0200
1471 @@ -0,0 +1,234 @@
1472 +/*
1473 + * NVRAM variable manipulation (Linux kernel half)
1474 + *
1475 + * Copyright 2001-2003, Broadcom Corporation
1476 + * All Rights Reserved.
1477 + *
1478 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1479 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1480 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1481 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1482 + *
1483 + * $Id$
1484 + */
1485 +
1486 +#include <linux/config.h>
1487 +#include <linux/init.h>
1488 +#include <linux/module.h>
1489 +#include <linux/kernel.h>
1490 +#include <linux/string.h>
1491 +#include <asm/io.h>
1492 +#include <asm/uaccess.h>
1493 +
1494 +#include <typedefs.h>
1495 +#include <osl.h>
1496 +#include <bcmendian.h>
1497 +#include <bcmutils.h>
1498 +
1499 +#define NVRAM_SIZE (0x1ff0)
1500 +static char _nvdata[NVRAM_SIZE] __initdata;
1501 +static char _valuestr[256] __initdata;
1502 +
1503 +/*
1504 + * TLV types. These codes are used in the "type-length-value"
1505 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
1506 + *
1507 + * The layout of the flash/nvram is as follows:
1508 + *
1509 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
1510 + *
1511 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
1512 + * The "length" field marks the length of the data section, not
1513 + * including the type and length fields.
1514 + *
1515 + * Environment variables are stored as follows:
1516 + *
1517 + * <type_env> <length> <flags> <name> = <value>
1518 + *
1519 + * If bit 0 (low bit) is set, the length is an 8-bit value.
1520 + * If bit 0 (low bit) is clear, the length is a 16-bit value
1521 + *
1522 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
1523 + * indicates the size of the length field.
1524 + *
1525 + * Flags are from the constants below:
1526 + *
1527 + */
1528 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
1529 +#define ENV_LENGTH_8BITS 0x01
1530 +
1531 +#define ENV_TYPE_USER 0x80
1532 +
1533 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
1534 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
1535 +
1536 +/*
1537 + * The actual TLV types we support
1538 + */
1539 +
1540 +#define ENV_TLV_TYPE_END 0x00
1541 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
1542 +
1543 +/*
1544 + * Environment variable flags
1545 + */
1546 +
1547 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
1548 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
1549 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
1550 +
1551 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
1552 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
1553 +
1554 +
1555 +/* *********************************************************************
1556 + * _nvram_read(buffer,offset,length)
1557 + *
1558 + * Read data from the NVRAM device
1559 + *
1560 + * Input parameters:
1561 + * buffer - destination buffer
1562 + * offset - offset of data to read
1563 + * length - number of bytes to read
1564 + *
1565 + * Return value:
1566 + * number of bytes read, or <0 if error occured
1567 + ********************************************************************* */
1568 +static int
1569 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
1570 +{
1571 + int i;
1572 + if (offset > NVRAM_SIZE)
1573 + return -1;
1574 +
1575 + for ( i = 0; i < length; i++) {
1576 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
1577 + }
1578 + return length;
1579 +}
1580 +
1581 +
1582 +static char*
1583 +_strnchr(const char *dest,int c,size_t cnt)
1584 +{
1585 + while (*dest && (cnt > 0)) {
1586 + if (*dest == c) return (char *) dest;
1587 + dest++;
1588 + cnt--;
1589 + }
1590 + return NULL;
1591 +}
1592 +
1593 +
1594 +
1595 +/*
1596 + * Core support API: Externally visible.
1597 + */
1598 +
1599 +/*
1600 + * Get the value of an NVRAM variable
1601 + * @param name name of variable to get
1602 + * @return value of variable or NULL if undefined
1603 + */
1604 +
1605 +char*
1606 +cfe_env_get(unsigned char *nv_buf, char* name)
1607 +{
1608 + int size;
1609 + unsigned char *buffer;
1610 + unsigned char *ptr;
1611 + unsigned char *envval;
1612 + unsigned int reclen;
1613 + unsigned int rectype;
1614 + int offset;
1615 + int flg;
1616 +
1617 + size = NVRAM_SIZE;
1618 + buffer = &_nvdata[0];
1619 +
1620 + ptr = buffer;
1621 + offset = 0;
1622 +
1623 + /* Read the record type and length */
1624 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1625 + goto error;
1626 + }
1627 +
1628 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
1629 +
1630 + /* Adjust pointer for TLV type */
1631 + rectype = *(ptr);
1632 + offset++;
1633 + size--;
1634 +
1635 + /*
1636 + * Read the length. It can be either 1 or 2 bytes
1637 + * depending on the code
1638 + */
1639 + if (rectype & ENV_LENGTH_8BITS) {
1640 + /* Read the record type and length - 8 bits */
1641 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1642 + goto error;
1643 + }
1644 + reclen = *(ptr);
1645 + size--;
1646 + offset++;
1647 + }
1648 + else {
1649 + /* Read the record type and length - 16 bits, MSB first */
1650 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
1651 + goto error;
1652 + }
1653 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
1654 + size -= 2;
1655 + offset += 2;
1656 + }
1657 +
1658 + if (reclen > size)
1659 + break; /* should not happen, bad NVRAM */
1660 +
1661 + switch (rectype) {
1662 + case ENV_TLV_TYPE_ENV:
1663 + /* Read the TLV data */
1664 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
1665 + goto error;
1666 + flg = *ptr++;
1667 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
1668 + if (envval) {
1669 + *envval++ = '\0';
1670 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
1671 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
1672 +#if 0
1673 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
1674 +#endif
1675 + if(!strcmp(ptr, name)){
1676 + return _valuestr;
1677 + }
1678 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
1679 + return _valuestr;
1680 + }
1681 + break;
1682 +
1683 + default:
1684 + /* Unknown TLV type, skip it. */
1685 + break;
1686 + }
1687 +
1688 + /*
1689 + * Advance to next TLV
1690 + */
1691 +
1692 + size -= (int)reclen;
1693 + offset += reclen;
1694 +
1695 + /* Read the next record type */
1696 + ptr = buffer;
1697 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
1698 + goto error;
1699 + }
1700 +
1701 +error:
1702 + return NULL;
1703 +
1704 +}
1705 +
1706 diff -urN linux.old/arch/mips/bcm947xx/compressed/Makefile linux.dev/arch/mips/bcm947xx/compressed/Makefile
1707 --- linux.old/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
1708 +++ linux.dev/arch/mips/bcm947xx/compressed/Makefile 2006-10-02 21:19:59.000000000 +0200
1709 @@ -0,0 +1,33 @@
1710 +#
1711 +# Makefile for Broadcom BCM947XX boards
1712 +#
1713 +# Copyright 2001-2003, Broadcom Corporation
1714 +# All Rights Reserved.
1715 +#
1716 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1717 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1718 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1719 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1720 +#
1721 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
1722 +#
1723 +
1724 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
1725 +SYSTEM ?= $(TOPDIR)/vmlinux
1726 +
1727 +all: vmlinuz
1728 +
1729 +# Don't build dependencies, this may die if $(CC) isn't gcc
1730 +dep:
1731 +
1732 +# Create a gzipped version named vmlinuz for compatibility
1733 +vmlinuz: piggy
1734 + gzip -c9 $< > $@
1735 +
1736 +piggy: $(SYSTEM)
1737 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
1738 +
1739 +mrproper: clean
1740 +
1741 +clean:
1742 + rm -f vmlinuz piggy
1743 diff -urN linux.old/arch/mips/bcm947xx/export.c linux.dev/arch/mips/bcm947xx/export.c
1744 --- linux.old/arch/mips/bcm947xx/export.c 1970-01-01 01:00:00.000000000 +0100
1745 +++ linux.dev/arch/mips/bcm947xx/export.c 2006-10-02 21:19:59.000000000 +0200
1746 @@ -0,0 +1,65 @@
1747 +#include <linux/module.h>
1748 +
1749 +#define _export(n) \
1750 + void n(void); \
1751 + EXPORT_SYMBOL(n);
1752 +
1753 +_export(bcm947xx_sbh)
1754 +
1755 +_export(sb_attach)
1756 +_export(sb_kattach)
1757 +_export(sb_boardtype)
1758 +_export(sb_boardvendor)
1759 +_export(sb_btcgpiowar)
1760 +_export(sb_bus)
1761 +_export(sb_chip)
1762 +_export(sb_chiprev)
1763 +_export(sb_chipcrev)
1764 +_export(sb_chippkg)
1765 +_export(sb_clkctl_clk)
1766 +_export(sb_clkctl_fast_pwrup_delay)
1767 +_export(sb_clkctl_init)
1768 +_export(sb_clkctl_xtal)
1769 +_export(sb_core_disable)
1770 +_export(sb_core_reset)
1771 +_export(sb_core_tofixup)
1772 +_export(sb_coreflags)
1773 +_export(sb_coreflagshi)
1774 +_export(sb_coreidx)
1775 +_export(sb_corerev)
1776 +_export(sb_coreunit)
1777 +_export(sb_detach)
1778 +_export(sb_deviceremoved)
1779 +_export(sb_gpiosetcore)
1780 +_export(sb_gpiocontrol)
1781 +_export(sb_gpioled)
1782 +_export(sb_gpioin)
1783 +_export(sb_gpioout)
1784 +_export(sb_gpioouten)
1785 +_export(sb_gpiotimerval)
1786 +_export(sb_iscoreup)
1787 +_export(sb_pci_setup)
1788 +_export(sb_pcirev)
1789 +_export(sb_pcmcia_init)
1790 +_export(sb_pcmciarev)
1791 +_export(sb_register_intr_callback)
1792 +_export(sb_setcore)
1793 +_export(sb_war16165)
1794 +_export(sb_osh)
1795 +
1796 +_export(getvar)
1797 +_export(getintvar)
1798 +_export(bcm_strtoul)
1799 +_export(bcm_ctype)
1800 +_export(bcm_toupper)
1801 +_export(bcm_ether_ntoa)
1802 +
1803 +_export(nvram_get)
1804 +_export(nvram_getall)
1805 +_export(nvram_set)
1806 +_export(nvram_unset)
1807 +_export(nvram_commit)
1808 +
1809 +_export(srom_read)
1810 +_export(srom_write)
1811 +
1812 diff -urN linux.old/arch/mips/bcm947xx/generic/int-handler.S linux.dev/arch/mips/bcm947xx/generic/int-handler.S
1813 --- linux.old/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
1814 +++ linux.dev/arch/mips/bcm947xx/generic/int-handler.S 2006-10-02 21:19:59.000000000 +0200
1815 @@ -0,0 +1,51 @@
1816 +/*
1817 + * Generic interrupt handler for Broadcom MIPS boards
1818 + *
1819 + * Copyright 2004, Broadcom Corporation
1820 + * All Rights Reserved.
1821 + *
1822 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1823 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1824 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1825 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1826 + *
1827 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
1828 + */
1829 +
1830 +#include <linux/config.h>
1831 +
1832 +#include <asm/asm.h>
1833 +#include <asm/mipsregs.h>
1834 +#include <asm/regdef.h>
1835 +#include <asm/stackframe.h>
1836 +
1837 +/*
1838 + * MIPS IRQ Source
1839 + * -------- ------
1840 + * 0 Software (ignored)
1841 + * 1 Software (ignored)
1842 + * 2 Combined hardware interrupt (hw0)
1843 + * 3 Hardware
1844 + * 4 Hardware
1845 + * 5 Hardware
1846 + * 6 Hardware
1847 + * 7 R4k timer
1848 + */
1849 +
1850 + .text
1851 + .set noreorder
1852 + .set noat
1853 + .align 5
1854 + NESTED(brcmIRQ, PT_SIZE, sp)
1855 + SAVE_ALL
1856 + CLI
1857 + .set at
1858 + .set noreorder
1859 +
1860 + jal brcm_irq_dispatch
1861 + move a0, sp
1862 +
1863 + j ret_from_irq
1864 + nop
1865 +
1866 + END(brcmIRQ)
1867 diff -urN linux.old/arch/mips/bcm947xx/generic/irq.c linux.dev/arch/mips/bcm947xx/generic/irq.c
1868 --- linux.old/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
1869 +++ linux.dev/arch/mips/bcm947xx/generic/irq.c 2006-10-02 21:19:59.000000000 +0200
1870 @@ -0,0 +1,130 @@
1871 +/*
1872 + * Generic interrupt control functions for Broadcom MIPS boards
1873 + *
1874 + * Copyright 2004, Broadcom Corporation
1875 + * All Rights Reserved.
1876 + *
1877 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1878 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1879 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1880 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1881 + *
1882 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
1883 + */
1884 +
1885 +#include <linux/config.h>
1886 +#include <linux/init.h>
1887 +#include <linux/kernel.h>
1888 +#include <linux/types.h>
1889 +#include <linux/interrupt.h>
1890 +#include <linux/irq.h>
1891 +
1892 +#include <asm/irq.h>
1893 +#include <asm/mipsregs.h>
1894 +#include <asm/gdb-stub.h>
1895 +
1896 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
1897 +
1898 +extern asmlinkage void brcmIRQ(void);
1899 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
1900 +
1901 +void
1902 +brcm_irq_dispatch(struct pt_regs *regs)
1903 +{
1904 + u32 cause;
1905 +
1906 + cause = read_c0_cause() &
1907 + read_c0_status() &
1908 + CAUSEF_IP;
1909 +
1910 +#ifdef CONFIG_KERNPROF
1911 + change_c0_status(cause | 1, 1);
1912 +#else
1913 + clear_c0_status(cause);
1914 +#endif
1915 +
1916 + if (cause & CAUSEF_IP7)
1917 + do_IRQ(7, regs);
1918 + if (cause & CAUSEF_IP2)
1919 + do_IRQ(2, regs);
1920 + if (cause & CAUSEF_IP3)
1921 + do_IRQ(3, regs);
1922 + if (cause & CAUSEF_IP4)
1923 + do_IRQ(4, regs);
1924 + if (cause & CAUSEF_IP5)
1925 + do_IRQ(5, regs);
1926 + if (cause & CAUSEF_IP6)
1927 + do_IRQ(6, regs);
1928 +}
1929 +
1930 +static void
1931 +enable_brcm_irq(unsigned int irq)
1932 +{
1933 + if (irq < 8)
1934 + set_c0_status(1 << (irq + 8));
1935 + else
1936 + set_c0_status(IE_IRQ0);
1937 +}
1938 +
1939 +static void
1940 +disable_brcm_irq(unsigned int irq)
1941 +{
1942 + if (irq < 8)
1943 + clear_c0_status(1 << (irq + 8));
1944 + else
1945 + clear_c0_status(IE_IRQ0);
1946 +}
1947 +
1948 +static void
1949 +ack_brcm_irq(unsigned int irq)
1950 +{
1951 + /* Already done in brcm_irq_dispatch */
1952 +}
1953 +
1954 +static unsigned int
1955 +startup_brcm_irq(unsigned int irq)
1956 +{
1957 + enable_brcm_irq(irq);
1958 +
1959 + return 0; /* never anything pending */
1960 +}
1961 +
1962 +static void
1963 +end_brcm_irq(unsigned int irq)
1964 +{
1965 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
1966 + enable_brcm_irq(irq);
1967 +}
1968 +
1969 +static struct hw_interrupt_type brcm_irq_type = {
1970 + typename: "MIPS",
1971 + startup: startup_brcm_irq,
1972 + shutdown: disable_brcm_irq,
1973 + enable: enable_brcm_irq,
1974 + disable: disable_brcm_irq,
1975 + ack: ack_brcm_irq,
1976 + end: end_brcm_irq,
1977 + NULL
1978 +};
1979 +
1980 +void __init
1981 +init_IRQ(void)
1982 +{
1983 + int i;
1984 +
1985 + for (i = 0; i < NR_IRQS; i++) {
1986 + irq_desc[i].status = IRQ_DISABLED;
1987 + irq_desc[i].action = 0;
1988 + irq_desc[i].depth = 1;
1989 + irq_desc[i].handler = &brcm_irq_type;
1990 + }
1991 +
1992 + set_except_vector(0, brcmIRQ);
1993 + change_c0_status(ST0_IM, ALLINTS);
1994 +
1995 +#ifdef CONFIG_REMOTE_DEBUG
1996 + printk("Breaking into debugger...\n");
1997 + set_debug_traps();
1998 + breakpoint();
1999 +#endif
2000 +}
2001 diff -urN linux.old/arch/mips/bcm947xx/generic/Makefile linux.dev/arch/mips/bcm947xx/generic/Makefile
2002 --- linux.old/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
2003 +++ linux.dev/arch/mips/bcm947xx/generic/Makefile 2006-10-02 21:26:29.000000000 +0200
2004 @@ -0,0 +1,12 @@
2005 +#
2006 +# Makefile for the BCM947xx specific kernel interface routines
2007 +# under Linux.
2008 +#
2009 +EXTRA_CFLAGS += -fno-delayed-branch
2010 +USE_STANDARD_AS_RULE := true
2011 +
2012 +O_TARGET := brcm.o
2013 +
2014 +obj-y := int-handler.o irq.o
2015 +
2016 +include $(TOPDIR)/Rules.make
2017 diff -urN linux.old/arch/mips/bcm947xx/gpio.c linux.dev/arch/mips/bcm947xx/gpio.c
2018 --- linux.old/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
2019 +++ linux.dev/arch/mips/bcm947xx/gpio.c 2006-10-02 21:19:59.000000000 +0200
2020 @@ -0,0 +1,159 @@
2021 +/*
2022 + * GPIO char driver
2023 + *
2024 + * Copyright 2005, Broadcom Corporation
2025 + * All Rights Reserved.
2026 + *
2027 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2028 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2029 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2030 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2031 + *
2032 + * $Id$
2033 + */
2034 +
2035 +#include <linux/module.h>
2036 +#include <linux/init.h>
2037 +#include <linux/fs.h>
2038 +#include <linux/miscdevice.h>
2039 +#include <asm/uaccess.h>
2040 +
2041 +#include <typedefs.h>
2042 +#include <osl.h>
2043 +#include <bcmutils.h>
2044 +#include <sbutils.h>
2045 +#include <bcmdevs.h>
2046 +
2047 +static sb_t *gpio_sbh;
2048 +static int gpio_major;
2049 +static devfs_handle_t gpio_dir;
2050 +static struct {
2051 + char *name;
2052 + devfs_handle_t handle;
2053 +} gpio_file[] = {
2054 + { "in", NULL },
2055 + { "out", NULL },
2056 + { "outen", NULL },
2057 + { "control", NULL }
2058 +};
2059 +
2060 +static int
2061 +gpio_open(struct inode *inode, struct file * file)
2062 +{
2063 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
2064 + return -ENODEV;
2065 +
2066 + MOD_INC_USE_COUNT;
2067 + return 0;
2068 +}
2069 +
2070 +static int
2071 +gpio_release(struct inode *inode, struct file * file)
2072 +{
2073 + MOD_DEC_USE_COUNT;
2074 + return 0;
2075 +}
2076 +
2077 +static ssize_t
2078 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
2079 +{
2080 + u32 val;
2081 +
2082 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
2083 + case 0:
2084 + val = sb_gpioin(gpio_sbh);
2085 + break;
2086 + case 1:
2087 + val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2088 + break;
2089 + case 2:
2090 + val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2091 + break;
2092 + case 3:
2093 + val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2094 + break;
2095 + default:
2096 + return -ENODEV;
2097 + }
2098 +
2099 + if (put_user(val, (u32 *) buf))
2100 + return -EFAULT;
2101 +
2102 + return sizeof(val);
2103 +}
2104 +
2105 +static ssize_t
2106 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
2107 +{
2108 + u32 val;
2109 +
2110 + if (get_user(val, (u32 *) buf))
2111 + return -EFAULT;
2112 +
2113 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
2114 + case 0:
2115 + return -EACCES;
2116 + case 1:
2117 + sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2118 + break;
2119 + case 2:
2120 + sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2121 + break;
2122 + case 3:
2123 + sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2124 + break;
2125 + default:
2126 + return -ENODEV;
2127 + }
2128 +
2129 + return sizeof(val);
2130 +}
2131 +
2132 +static struct file_operations gpio_fops = {
2133 + owner: THIS_MODULE,
2134 + open: gpio_open,
2135 + release: gpio_release,
2136 + read: gpio_read,
2137 + write: gpio_write,
2138 +};
2139 +
2140 +static int __init
2141 +gpio_init(void)
2142 +{
2143 + int i;
2144 +
2145 + if (!(gpio_sbh = sb_kattach()))
2146 + return -ENODEV;
2147 +
2148 + sb_gpiosetcore(gpio_sbh);
2149 +
2150 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
2151 + return gpio_major;
2152 +
2153 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
2154 +
2155 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
2156 + gpio_file[i].handle = devfs_register(gpio_dir,
2157 + gpio_file[i].name,
2158 + DEVFS_FL_DEFAULT, gpio_major, i,
2159 + S_IFCHR | S_IRUGO | S_IWUGO,
2160 + &gpio_fops, NULL);
2161 + }
2162 +
2163 + return 0;
2164 +}
2165 +
2166 +static void __exit
2167 +gpio_exit(void)
2168 +{
2169 + int i;
2170 +
2171 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
2172 + devfs_unregister(gpio_file[i].handle);
2173 + devfs_unregister(gpio_dir);
2174 + devfs_unregister_chrdev(gpio_major, "gpio");
2175 + sb_detach(gpio_sbh);
2176 +}
2177 +
2178 +module_init(gpio_init);
2179 +module_exit(gpio_exit);
2180 diff -urN linux.old/arch/mips/bcm947xx/hndchipc.c linux.dev/arch/mips/bcm947xx/hndchipc.c
2181 --- linux.old/arch/mips/bcm947xx/hndchipc.c 1970-01-01 01:00:00.000000000 +0100
2182 +++ linux.dev/arch/mips/bcm947xx/hndchipc.c 2006-10-02 21:19:59.000000000 +0200
2183 @@ -0,0 +1,158 @@
2184 +/*
2185 + * BCM47XX support code for some chipcommon (old extif) facilities (uart)
2186 + *
2187 + * Copyright 2006, Broadcom Corporation
2188 + * All Rights Reserved.
2189 + *
2190 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2191 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2192 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2193 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2194 + *
2195 + * $Id: hndchipc.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
2196 + */
2197 +
2198 +#include <typedefs.h>
2199 +#include <bcmdefs.h>
2200 +#include <osl.h>
2201 +#include <bcmutils.h>
2202 +#include <sbutils.h>
2203 +#include <bcmdevs.h>
2204 +#include <bcmnvram.h>
2205 +#include <sbconfig.h>
2206 +#include <sbextif.h>
2207 +#include <sbchipc.h>
2208 +#include <hndcpu.h>
2209 +
2210 +/*
2211 + * Returns TRUE if an external UART exists at the given base
2212 + * register.
2213 + */
2214 +static bool
2215 +BCMINITFN(serial_exists)(osl_t *osh, uint8 *regs)
2216 +{
2217 + uint8 save_mcr, status1;
2218 +
2219 + save_mcr = R_REG(osh, &regs[UART_MCR]);
2220 + W_REG(osh, &regs[UART_MCR], UART_MCR_LOOP | 0x0a);
2221 + status1 = R_REG(osh, &regs[UART_MSR]) & 0xf0;
2222 + W_REG(osh, &regs[UART_MCR], save_mcr);
2223 +
2224 + return (status1 == 0x90);
2225 +}
2226 +
2227 +/*
2228 + * Initializes UART access. The callback function will be called once
2229 + * per found UART.
2230 + */
2231 +void
2232 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base,
2233 + uint reg_shift))
2234 +{
2235 + osl_t *osh;
2236 + void *regs;
2237 + ulong base;
2238 + uint irq;
2239 + int i, n;
2240 +
2241 + osh = sb_osh(sbh);
2242 +
2243 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
2244 + extifregs_t *eir = (extifregs_t *) regs;
2245 + sbconfig_t *sb;
2246 +
2247 + /* Determine external UART register base */
2248 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
2249 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(osh, &sb->sbadmatch1)));
2250 +
2251 + /* Determine IRQ */
2252 + irq = sb_irq(sbh);
2253 +
2254 + /* Disable GPIO interrupt initially */
2255 + W_REG(osh, &eir->gpiointpolarity, 0);
2256 + W_REG(osh, &eir->gpiointmask, 0);
2257 +
2258 + /* Search for external UARTs */
2259 + n = 2;
2260 + for (i = 0; i < 2; i++) {
2261 + regs = (void *) REG_MAP(base + (i * 8), 8);
2262 + if (serial_exists(osh, regs)) {
2263 + /* Set GPIO 1 to be the external UART IRQ */
2264 + W_REG(osh, &eir->gpiointmask, 2);
2265 + /* XXXDetermine external UART clock */
2266 + if (add)
2267 + add(regs, irq, 13500000, 0);
2268 + }
2269 + }
2270 +
2271 + /* Add internal UART if enabled */
2272 + if (R_REG(osh, &eir->corecontrol) & CC_UE)
2273 + if (add)
2274 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
2275 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
2276 + chipcregs_t *cc = (chipcregs_t *) regs;
2277 + uint32 rev, cap, pll, baud_base, div;
2278 +
2279 + /* Determine core revision and capabilities */
2280 + rev = sb_corerev(sbh);
2281 + cap = R_REG(osh, &cc->capabilities);
2282 + pll = cap & CAP_PLL_MASK;
2283 +
2284 + /* Determine IRQ */
2285 + irq = sb_irq(sbh);
2286 +
2287 + if (pll == PLL_TYPE1) {
2288 + /* PLL clock */
2289 + baud_base = sb_clock_rate(pll,
2290 + R_REG(osh, &cc->clockcontrol_n),
2291 + R_REG(osh, &cc->clockcontrol_m2));
2292 + div = 1;
2293 + } else {
2294 + /* Fixed ALP clock */
2295 + if (rev >= 11 && rev != 15) {
2296 + baud_base = 20000000;
2297 + div = 1;
2298 + /* Set the override bit so we don't divide it */
2299 + W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
2300 + }
2301 + /* Internal backplane clock */
2302 + else if (rev >= 3) {
2303 + baud_base = sb_clock(sbh);
2304 + div = 2; /* Minimum divisor */
2305 + W_REG(osh, &cc->clkdiv,
2306 + ((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
2307 + }
2308 + /* Fixed internal backplane clock */
2309 + else {
2310 + baud_base = 88000000;
2311 + div = 48;
2312 + }
2313 +
2314 + /* Clock source depends on strapping if UartClkOverride is unset */
2315 + if ((rev > 0) &&
2316 + ((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0)) {
2317 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
2318 + /* Internal divided backplane clock */
2319 + baud_base /= div;
2320 + } else {
2321 + /* Assume external clock of 1.8432 MHz */
2322 + baud_base = 1843200;
2323 + }
2324 + }
2325 + }
2326 +
2327 + /* Add internal UARTs */
2328 + n = cap & CAP_UARTS_MASK;
2329 + for (i = 0; i < n; i++) {
2330 + /* Register offset changed after revision 0 */
2331 + if (rev)
2332 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
2333 + else
2334 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
2335 +
2336 + if (add)
2337 + add(regs, irq, baud_base, 0);
2338 + }
2339 + }
2340 +}
2341 +
2342 diff -urN linux.old/arch/mips/bcm947xx/include/bcm4710.h linux.dev/arch/mips/bcm947xx/include/bcm4710.h
2343 --- linux.old/arch/mips/bcm947xx/include/bcm4710.h 1970-01-01 01:00:00.000000000 +0100
2344 +++ linux.dev/arch/mips/bcm947xx/include/bcm4710.h 2006-10-02 21:19:59.000000000 +0200
2345 @@ -0,0 +1,91 @@
2346 +/*
2347 + * BCM4710 address space map and definitions
2348 + * Think twice before adding to this file, this is not the kitchen sink
2349 + * These definitions are not guaranteed for all 47xx chips, only the 4710
2350 + *
2351 + * Copyright 2004, Broadcom Corporation
2352 + * All Rights Reserved.
2353 + *
2354 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2355 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2356 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2357 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2358 + *
2359 + * $Id: bcm4710.h,v 1.3 2004/09/27 07:23:30 tallest Exp $
2360 + */
2361 +
2362 +#ifndef _bcm4710_h_
2363 +#define _bcm4710_h_
2364 +
2365 +/* Address map */
2366 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
2367 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
2368 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
2369 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
2370 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
2371 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
2372 +
2373 +/* Core register space */
2374 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
2375 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
2376 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
2377 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
2378 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
2379 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
2380 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
2381 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
2382 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
2383 +
2384 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
2385 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
2386 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
2387 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
2388 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
2389 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
2390 +
2391 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
2392 +
2393 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
2394 +
2395 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
2396 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
2397 +
2398 +#define SBFLAG_PCI 0
2399 +#define SBFLAG_ENET0 1
2400 +#define SBFLAG_ILINE20 2
2401 +#define SBFLAG_CODEC 3
2402 +#define SBFLAG_USB 4
2403 +#define SBFLAG_EXTIF 5
2404 +#define SBFLAG_ENET1 6
2405 +
2406 +#ifdef CONFIG_HWSIM
2407 +#define BCM4710_TRACE(trval) do { *((int *)0xa0000f18) = (trval); } while (0)
2408 +#else
2409 +#define BCM4710_TRACE(trval)
2410 +#endif
2411 +
2412 +
2413 +/* BCM94702 CPCI -ExtIF used for LocalBus devs */
2414 +
2415 +#define BCM94702_CPCI_RESET_ADDR BCM4710_EXTIF
2416 +#define BCM94702_CPCI_BOARDID_ADDR (BCM4710_EXTIF | 0x4000)
2417 +#define BCM94702_CPCI_DOC_ADDR (BCM4710_EXTIF | 0x6000)
2418 +#define BCM94702_DOC_ADDR BCM94702_CPCI_DOC_ADDR
2419 +#define BCM94702_CPCI_LED_ADDR (BCM4710_EXTIF | 0xc000)
2420 +#define BCM94702_CPCI_NVRAM_ADDR (BCM4710_EXTIF | 0xe000)
2421 +#define BCM94702_CPCI_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
2422 +#define BCM94702_CPCI_TOD_REG_BASE (BCM94702_CPCI_NVRAM_ADDR | 0x1ff0)
2423 +
2424 +#define LED_REG(x) \
2425 + (*(volatile unsigned char *) (KSEG1ADDR(BCM94702_CPCI_LED_ADDR) + (x)))
2426 +
2427 +/*
2428 + * Reset function implemented in PLD. Read or write should trigger hard reset
2429 + */
2430 +#define SYS_HARD_RESET() \
2431 + { for (;;) \
2432 + *( (volatile unsigned char *)\
2433 + KSEG1ADDR(BCM94702_CPCI_RESET_ADDR) ) = 0x80; \
2434 + }
2435 +
2436 +#endif /* _bcm4710_h_ */
2437 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdefs.h linux.dev/arch/mips/bcm947xx/include/bcmdefs.h
2438 --- linux.old/arch/mips/bcm947xx/include/bcmdefs.h 1970-01-01 01:00:00.000000000 +0100
2439 +++ linux.dev/arch/mips/bcm947xx/include/bcmdefs.h 2006-10-02 21:19:59.000000000 +0200
2440 @@ -0,0 +1,106 @@
2441 +/*
2442 + * Misc system wide definitions
2443 + *
2444 + * Copyright 2006, Broadcom Corporation
2445 + * All Rights Reserved.
2446 + *
2447 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2448 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2449 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2450 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2451 + * $Id: bcmdefs.h,v 1.1.1.3 2006/04/08 06:13:39 honor Exp $
2452 + */
2453 +
2454 +#ifndef _bcmdefs_h_
2455 +#define _bcmdefs_h_
2456 +
2457 +/*
2458 + * One doesn't need to include this file explicitly, gets included automatically if
2459 + * typedefs.h is included.
2460 + */
2461 +
2462 +/* Reclaiming text and data :
2463 + * The following macros specify special linker sections that can be reclaimed
2464 + * after a system is considered 'up'.
2465 + */
2466 +#if defined(__GNUC__) && defined(BCMRECLAIM)
2467 +extern bool bcmreclaimed;
2468 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data
2469 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn
2470 +#else /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
2471 +#define BCMINITDATA(_data) _data
2472 +#define BCMINITFN(_fn) _fn
2473 +#define bcmreclaimed 0
2474 +#endif /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
2475 +
2476 +/* Reclaim uninit functions if BCMNODOWN is defined */
2477 +/* and if they are not already removed by -gc-sections */
2478 +#ifdef BCMNODOWN
2479 +#define BCMUNINITFN(_fn) BCMINITFN(_fn)
2480 +#else
2481 +#define BCMUNINITFN(_fn) _fn
2482 +#endif
2483 +
2484 +#ifdef BCMRECLAIM
2485 +#define CONST
2486 +#else
2487 +#define CONST const
2488 +#endif /* BCMRECLAIM */
2489 +
2490 +/* Compatibility with old-style BCMRECLAIM */
2491 +#define BCMINIT(_id) _id
2492 +
2493 +
2494 +/* Put some library data/code into ROM to reduce RAM requirements */
2495 +#if defined(__GNUC__) && defined(BCMROMOFFLOAD)
2496 +#define BCMROMDATA(_data) __attribute__ ((__section__ (".datarom." #_data))) _data
2497 +#define BCMROMFN(_fn) __attribute__ ((__section__ (".textrom." #_fn))) _fn
2498 +#else
2499 +#define BCMROMDATA(_data) _data
2500 +#define BCMROMFN(_fn) _fn
2501 +#endif
2502 +
2503 +/* Bus types */
2504 +#define SB_BUS 0 /* Silicon Backplane */
2505 +#define PCI_BUS 1 /* PCI target */
2506 +#define PCMCIA_BUS 2 /* PCMCIA target */
2507 +#define SDIO_BUS 3 /* SDIO target */
2508 +#define JTAG_BUS 4 /* JTAG */
2509 +#define NO_BUS 0xFF /* Bus that does not support R/W REG */
2510 +
2511 +/* Allows optimization for single-bus support */
2512 +#ifdef BCMBUSTYPE
2513 +#define BUSTYPE(bus) (BCMBUSTYPE)
2514 +#else
2515 +#define BUSTYPE(bus) (bus)
2516 +#endif
2517 +
2518 +/* Defines for DMA Address Width - Shared between OSL and HNDDMA */
2519 +#define DMADDR_MASK_32 0x0 /* Address mask for 32-bits */
2520 +#define DMADDR_MASK_30 0xc0000000 /* Address mask for 30-bits */
2521 +#define DMADDR_MASK_0 0xffffffff /* Address mask for 0-bits (hi-part) */
2522 +
2523 +#define DMADDRWIDTH_30 30 /* 30-bit addressing capability */
2524 +#define DMADDRWIDTH_32 32 /* 32-bit addressing capability */
2525 +#define DMADDRWIDTH_63 63 /* 64-bit addressing capability */
2526 +#define DMADDRWIDTH_64 64 /* 64-bit addressing capability */
2527 +
2528 +/* packet headroom necessary to accomodate the largest header in the system, (i.e TXOFF).
2529 + * By doing, we avoid the need to allocate an extra buffer for the header when bridging to WL.
2530 + * There is a compile time check in wlc.c which ensure that this value is at least as big
2531 + * as TXOFF. This value is used in dma_rxfill (hnddma.c).
2532 + */
2533 +#define BCMEXTRAHDROOM 160
2534 +
2535 +/* Headroom required for dongle-to-host communication. Packets allocated
2536 + * locally in the dongle (e.g. for CDC ioctls or RNDIS messages) should
2537 + * leave this much room in front for low-level message headers which may
2538 + * be needed to get across the dongle bus to the host. (These messages
2539 + * don't go over the network, so room for the full WL header above would
2540 + * be a waste.)
2541 + */
2542 +#define BCMDONGLEHDRSZ 8
2543 +
2544 +
2545 +
2546 +#endif /* _bcmdefs_h_ */
2547 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs1.h linux.dev/arch/mips/bcm947xx/include/bcmdevs1.h
2548 --- linux.old/arch/mips/bcm947xx/include/bcmdevs1.h 1970-01-01 01:00:00.000000000 +0100
2549 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs1.h 2006-10-02 21:19:59.000000000 +0200
2550 @@ -0,0 +1,391 @@
2551 +/*
2552 + * Broadcom device-specific manifest constants.
2553 + *
2554 + * Copyright 2005, Broadcom Corporation
2555 + * All Rights Reserved.
2556 + *
2557 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2558 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2559 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2560 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2561 + * $Id$
2562 + */
2563 +
2564 +#ifndef _BCMDEVS_H
2565 +#define _BCMDEVS_H
2566 +
2567 +
2568 +/* Known PCI vendor Id's */
2569 +#define VENDOR_EPIGRAM 0xfeda
2570 +#define VENDOR_BROADCOM 0x14e4
2571 +#define VENDOR_3COM 0x10b7
2572 +#define VENDOR_NETGEAR 0x1385
2573 +#define VENDOR_DIAMOND 0x1092
2574 +#define VENDOR_DELL 0x1028
2575 +#define VENDOR_HP 0x0e11
2576 +#define VENDOR_APPLE 0x106b
2577 +
2578 +/* PCI Device Id's */
2579 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
2580 +#define BCM4211_DEVICE_ID 0x4211
2581 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
2582 +#define BCM4231_DEVICE_ID 0x4231
2583 +
2584 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
2585 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
2586 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
2587 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
2588 +
2589 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
2590 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
2591 +
2592 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
2593 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
2594 +
2595 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
2596 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
2597 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
2598 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
2599 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
2600 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
2601 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
2602 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
2603 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
2604 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
2605 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
2606 +
2607 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
2608 +
2609 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
2610 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
2611 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
2612 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
2613 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
2614 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
2615 +
2616 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
2617 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
2618 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
2619 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
2620 +
2621 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
2622 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
2623 +
2624 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
2625 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
2626 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
2627 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
2628 +
2629 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
2630 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
2631 +#define BCM4306_D11G_ID2 0x4325
2632 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
2633 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
2634 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
2635 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
2636 +
2637 +#define BCM4309_PKG_ID 1 /* 4309 package id */
2638 +
2639 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
2640 +#define BCM4303_PKG_ID 2 /* 4303 package id */
2641 +
2642 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
2643 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
2644 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
2645 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
2646 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
2647 +
2648 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
2649 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
2650 +
2651 +
2652 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
2653 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
2654 +
2655 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
2656 +
2657 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
2658 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
2659 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
2660 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
2661 +
2662 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
2663 +
2664 +/* Address map */
2665 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
2666 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
2667 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
2668 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
2669 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
2670 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
2671 +
2672 +/* Core register space */
2673 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
2674 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
2675 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
2676 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
2677 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
2678 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
2679 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
2680 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
2681 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
2682 +
2683 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
2684 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
2685 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
2686 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
2687 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
2688 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
2689 +
2690 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
2691 +
2692 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
2693 +
2694 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
2695 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
2696 +
2697 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
2698 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
2699 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
2700 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
2701 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
2702 +
2703 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
2704 +
2705 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
2706 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
2707 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
2708 +
2709 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
2710 +
2711 +/* PCMCIA vendor Id's */
2712 +
2713 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
2714 +
2715 +/* SDIO vendor Id's */
2716 +#define VENDOR_BROADCOM_SDIO 0x00BF
2717 +
2718 +
2719 +/* boardflags */
2720 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
2721 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
2722 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
2723 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
2724 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
2725 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
2726 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
2727 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
2728 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
2729 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
2730 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
2731 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
2732 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
2733 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
2734 +
2735 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
2736 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
2737 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
2738 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
2739 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
2740 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
2741 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
2742 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
2743 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
2744 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
2745 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
2746 +
2747 +/* Bus types */
2748 +#define SB_BUS 0 /* Silicon Backplane */
2749 +#define PCI_BUS 1 /* PCI target */
2750 +#define PCMCIA_BUS 2 /* PCMCIA target */
2751 +#define SDIO_BUS 3 /* SDIO target */
2752 +#define JTAG_BUS 4 /* JTAG */
2753 +
2754 +/* Allows optimization for single-bus support */
2755 +#ifdef BCMBUSTYPE
2756 +#define BUSTYPE(bus) (BCMBUSTYPE)
2757 +#else
2758 +#define BUSTYPE(bus) (bus)
2759 +#endif
2760 +
2761 +/* power control defines */
2762 +#define PLL_DELAY 150 /* us pll on delay */
2763 +#define FREF_DELAY 200 /* us fref change delay */
2764 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
2765 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
2766 +
2767 +/* Reference Board Types */
2768 +
2769 +#define BU4710_BOARD 0x0400
2770 +#define VSIM4710_BOARD 0x0401
2771 +#define QT4710_BOARD 0x0402
2772 +
2773 +#define BU4610_BOARD 0x0403
2774 +#define VSIM4610_BOARD 0x0404
2775 +
2776 +#define BU4307_BOARD 0x0405
2777 +#define BCM94301CB_BOARD 0x0406
2778 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
2779 +#define BCM94301MP_BOARD 0x0407
2780 +#define BCM94307MP_BOARD 0x0408
2781 +#define BCMAP4307_BOARD 0x0409
2782 +
2783 +#define BU4309_BOARD 0x040a
2784 +#define BCM94309CB_BOARD 0x040b
2785 +#define BCM94309MP_BOARD 0x040c
2786 +#define BCM4309AP_BOARD 0x040d
2787 +
2788 +#define BCM94302MP_BOARD 0x040e
2789 +
2790 +#define VSIM4310_BOARD 0x040f
2791 +#define BU4711_BOARD 0x0410
2792 +#define BCM94310U_BOARD 0x0411
2793 +#define BCM94310AP_BOARD 0x0412
2794 +#define BCM94310MP_BOARD 0x0414
2795 +
2796 +#define BU4306_BOARD 0x0416
2797 +#define BCM94306CB_BOARD 0x0417
2798 +#define BCM94306MP_BOARD 0x0418
2799 +
2800 +#define BCM94710D_BOARD 0x041a
2801 +#define BCM94710R1_BOARD 0x041b
2802 +#define BCM94710R4_BOARD 0x041c
2803 +#define BCM94710AP_BOARD 0x041d
2804 +
2805 +
2806 +#define BU2050_BOARD 0x041f
2807 +
2808 +
2809 +#define BCM94309G_BOARD 0x0421
2810 +
2811 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
2812 +
2813 +#define BU4704_BOARD 0x0423
2814 +#define BU4702_BOARD 0x0424
2815 +
2816 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
2817 +
2818 +#define BU4317_BOARD 0x0426
2819 +
2820 +
2821 +#define BCM94702MN_BOARD 0x0428
2822 +
2823 +/* BCM4702 1U CompactPCI Board */
2824 +#define BCM94702CPCI_BOARD 0x0429
2825 +
2826 +/* BCM4702 with BCM95380 VLAN Router */
2827 +#define BCM95380RR_BOARD 0x042a
2828 +
2829 +/* cb4306 with SiGe PA */
2830 +#define BCM94306CBSG_BOARD 0x042b
2831 +
2832 +/* mp4301 with 2050 radio */
2833 +#define BCM94301MPL_BOARD 0x042c
2834 +
2835 +/* cb4306 with SiGe PA */
2836 +#define PCSG94306_BOARD 0x042d
2837 +
2838 +/* bu4704 with sdram */
2839 +#define BU4704SD_BOARD 0x042e
2840 +
2841 +/* Dual 11a/11g Router */
2842 +#define BCM94704AGR_BOARD 0x042f
2843 +
2844 +/* 11a-only minipci */
2845 +#define BCM94308MP_BOARD 0x0430
2846 +
2847 +
2848 +
2849 +/* BCM94317 boards */
2850 +#define BCM94317CB_BOARD 0x0440
2851 +#define BCM94317MP_BOARD 0x0441
2852 +#define BCM94317PCMCIA_BOARD 0x0442
2853 +#define BCM94317SDIO_BOARD 0x0443
2854 +
2855 +#define BU4712_BOARD 0x0444
2856 +#define BU4712SD_BOARD 0x045d
2857 +#define BU4712L_BOARD 0x045f
2858 +
2859 +/* BCM4712 boards */
2860 +#define BCM94712AP_BOARD 0x0445
2861 +#define BCM94712P_BOARD 0x0446
2862 +
2863 +/* BCM4318 boards */
2864 +#define BU4318_BOARD 0x0447
2865 +#define CB4318_BOARD 0x0448
2866 +#define MPG4318_BOARD 0x0449
2867 +#define MP4318_BOARD 0x044a
2868 +#define SD4318_BOARD 0x044b
2869 +
2870 +/* BCM63XX boards */
2871 +#define BCM96338_BOARD 0x6338
2872 +#define BCM96345_BOARD 0x6345
2873 +#define BCM96348_BOARD 0x6348
2874 +
2875 +/* Another mp4306 with SiGe */
2876 +#define BCM94306P_BOARD 0x044c
2877 +
2878 +/* CF-like 4317 modules */
2879 +#define BCM94317CF_BOARD 0x044d
2880 +
2881 +/* mp4303 */
2882 +#define BCM94303MP_BOARD 0x044e
2883 +
2884 +/* mpsgh4306 */
2885 +#define BCM94306MPSGH_BOARD 0x044f
2886 +
2887 +/* BRCM 4306 w/ Front End Modules */
2888 +#define BCM94306MPM 0x0450
2889 +#define BCM94306MPL 0x0453
2890 +
2891 +/* 4712agr */
2892 +#define BCM94712AGR_BOARD 0x0451
2893 +
2894 +/* The real CF 4317 board */
2895 +#define CFI4317_BOARD 0x0452
2896 +
2897 +/* pcmcia 4303 */
2898 +#define PC4303_BOARD 0x0454
2899 +
2900 +/* 5350K */
2901 +#define BCM95350K_BOARD 0x0455
2902 +
2903 +/* 5350R */
2904 +#define BCM95350R_BOARD 0x0456
2905 +
2906 +/* 4306mplna */
2907 +#define BCM94306MPLNA_BOARD 0x0457
2908 +
2909 +/* 4320 boards */
2910 +#define BU4320_BOARD 0x0458
2911 +#define BU4320S_BOARD 0x0459
2912 +#define BCM94320PH_BOARD 0x045a
2913 +
2914 +/* 4306mph */
2915 +#define BCM94306MPH_BOARD 0x045b
2916 +
2917 +/* 4306pciv */
2918 +#define BCM94306PCIV_BOARD 0x045c
2919 +
2920 +#define BU4712SD_BOARD 0x045d
2921 +
2922 +#define BCM94320PFLSH_BOARD 0x045e
2923 +
2924 +#define BU4712L_BOARD 0x045f
2925 +#define BCM94712LGR_BOARD 0x0460
2926 +#define BCM94320R_BOARD 0x0461
2927 +
2928 +#define BU5352_BOARD 0x0462
2929 +
2930 +#define BCM94318MPGH_BOARD 0x0463
2931 +
2932 +
2933 +#define BCM95352GR_BOARD 0x0467
2934 +
2935 +/* bcm95351agr */
2936 +#define BCM95351AGR_BOARD 0x0470
2937 +
2938 +/* # of GPIO pins */
2939 +#define GPIO_NUMPINS 16
2940 +
2941 +#endif /* _BCMDEVS_H */
2942 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
2943 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
2944 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2006-10-02 21:19:59.000000000 +0200
2945 @@ -0,0 +1,369 @@
2946 +/*
2947 + * Broadcom device-specific manifest constants.
2948 + *
2949 + * Copyright 2006, Broadcom Corporation
2950 + * All Rights Reserved.
2951 + *
2952 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2953 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2954 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2955 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2956 + * $Id: bcmdevs.h,v 1.1.1.17 2006/04/15 01:29:08 michael Exp $
2957 + */
2958 +
2959 +#ifndef _BCMDEVS_H
2960 +#define _BCMDEVS_H
2961 +
2962 +#include "bcm4710.h"
2963 +
2964 +/* Known PCI vendor Id's */
2965 +#define VENDOR_EPIGRAM 0xfeda
2966 +#define VENDOR_BROADCOM 0x14e4
2967 +#define VENDOR_3COM 0x10b7
2968 +#define VENDOR_NETGEAR 0x1385
2969 +#define VENDOR_DIAMOND 0x1092
2970 +#define VENDOR_DELL 0x1028
2971 +#define VENDOR_HP 0x0e11
2972 +#define VENDOR_APPLE 0x106b
2973 +
2974 +/* PCI Device Id's */
2975 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
2976 +#define BCM4211_DEVICE_ID 0x4211
2977 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
2978 +#define BCM4231_DEVICE_ID 0x4231
2979 +
2980 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
2981 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
2982 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
2983 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
2984 +
2985 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
2986 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
2987 +
2988 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
2989 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
2990 +
2991 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
2992 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
2993 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
2994 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
2995 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
2996 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
2997 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
2998 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
2999 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
3000 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
3001 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
3002 +#define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */
3003 +#define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */
3004 +#define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */
3005 +
3006 +#define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */
3007 +#define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */
3008 +
3009 +#define BCM4710_CHIP_ID 0x4710 /* 4710 chipid returned by sb_chip() */
3010 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
3011 +
3012 +#define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */
3013 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
3014 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
3015 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
3016 +
3017 +#define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */
3018 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
3019 +#define BCM4306_D11G_ID2 0x4325
3020 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
3021 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
3022 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
3023 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
3024 +
3025 +#define BCM4309_PKG_ID 1 /* 4309 package id */
3026 +
3027 +#define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */
3028 +#define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */
3029 +#define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */
3030 +#define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */
3031 +
3032 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
3033 +#define BCM4303_PKG_ID 2 /* 4303 package id */
3034 +
3035 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
3036 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
3037 +
3038 +#define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */
3039 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
3040 +
3041 +#define BCM4318_CHIP_ID 0x4318 /* 4318 chip common chipid */
3042 +#define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */
3043 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */
3044 +#define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */
3045 +
3046 +#define BCM4321_CHIP_ID 0x4321 /* 4321 chip common chipid */
3047 +#define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */
3048 +#define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Hgz band id */
3049 +#define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */
3050 +
3051 +#define BCM4331_CHIP_ID 0x4331 /* 4331 chip common chipid */
3052 +#define BCM4331_D11N2G_ID 0x4330 /* 4331 802.11n 2.4Ghz band id */
3053 +#define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */
3054 +#define BCM4331_D11N5G_ID 0x4332 /* 4331 802.11n 5Ghz band id */
3055 +
3056 +#define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */
3057 +#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
3058 +#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
3059 +
3060 +#define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */
3061 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
3062 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
3063 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
3064 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
3065 +
3066 +#define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
3067 +#define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */
3068 +#define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */
3069 +
3070 +#define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */
3071 +
3072 +#define BCM4328_CHIP_ID 0x4328 /* bcm4328 chipcommon chipid */
3073 +
3074 +#define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */
3075 +#define BCM43XX_JTAGM_ID 0x43f1 /* 43xx jtagm device id */
3076 +#define BCM43XXOLD_JTAGM_ID 0x4331 /* 43xx old jtagm device id */
3077 +
3078 +#define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */
3079 +#define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */
3080 +
3081 +#define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */
3082 +
3083 +#define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */
3084 +
3085 +/* PCMCIA vendor Id's */
3086 +
3087 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
3088 +
3089 +/* SDIO vendor Id's */
3090 +#define VENDOR_BROADCOM_SDIO 0x00BF
3091 +
3092 +
3093 +/* boardflags */
3094 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
3095 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
3096 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
3097 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
3098 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
3099 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
3100 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
3101 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
3102 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
3103 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
3104 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
3105 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
3106 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
3107 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
3108 +
3109 +/* boardflags2 */
3110 +#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* This board has an external rxbb regulator */
3111 +#define BFL2_SSWITCH_AVAIL 0x00000002 /* This board has a superswitch for > 2 antennas */
3112 +#define BFL2_TXPWRCTRL_EN 0x00000004 /* This board permits TX Power Control to be enabled */
3113 +
3114 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
3115 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
3116 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
3117 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
3118 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
3119 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
3120 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
3121 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
3122 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
3123 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
3124 +
3125 +/* power control defines */
3126 +#define PLL_DELAY 150 /* us pll on delay */
3127 +#define FREF_DELAY 200 /* us fref change delay */
3128 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
3129 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
3130 +
3131 +/* Reference Board Types */
3132 +
3133 +#define BU4710_BOARD 0x0400
3134 +#define VSIM4710_BOARD 0x0401
3135 +#define QT4710_BOARD 0x0402
3136 +
3137 +#define BU4309_BOARD 0x040a
3138 +#define BCM94309CB_BOARD 0x040b
3139 +#define BCM94309MP_BOARD 0x040c
3140 +#define BCM4309AP_BOARD 0x040d
3141 +
3142 +#define BCM94302MP_BOARD 0x040e
3143 +
3144 +#define BU4306_BOARD 0x0416
3145 +#define BCM94306CB_BOARD 0x0417
3146 +#define BCM94306MP_BOARD 0x0418
3147 +
3148 +#define BCM94710D_BOARD 0x041a
3149 +#define BCM94710R1_BOARD 0x041b
3150 +#define BCM94710R4_BOARD 0x041c
3151 +#define BCM94710AP_BOARD 0x041d
3152 +
3153 +#define BU2050_BOARD 0x041f
3154 +
3155 +
3156 +#define BCM94309G_BOARD 0x0421
3157 +
3158 +#define BU4704_BOARD 0x0423
3159 +#define BU4702_BOARD 0x0424
3160 +
3161 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
3162 +
3163 +
3164 +#define BCM94702MN_BOARD 0x0428
3165 +
3166 +/* BCM4702 1U CompactPCI Board */
3167 +#define BCM94702CPCI_BOARD 0x0429
3168 +
3169 +/* BCM4702 with BCM95380 VLAN Router */
3170 +#define BCM95380RR_BOARD 0x042a
3171 +
3172 +/* cb4306 with SiGe PA */
3173 +#define BCM94306CBSG_BOARD 0x042b
3174 +
3175 +/* cb4306 with SiGe PA */
3176 +#define PCSG94306_BOARD 0x042d
3177 +
3178 +/* bu4704 with sdram */
3179 +#define BU4704SD_BOARD 0x042e
3180 +
3181 +/* Dual 11a/11g Router */
3182 +#define BCM94704AGR_BOARD 0x042f
3183 +
3184 +/* 11a-only minipci */
3185 +#define BCM94308MP_BOARD 0x0430
3186 +
3187 +
3188 +
3189 +#define BU4712_BOARD 0x0444
3190 +#define BU4712SD_BOARD 0x045d
3191 +#define BU4712L_BOARD 0x045f
3192 +
3193 +/* BCM4712 boards */
3194 +#define BCM94712AP_BOARD 0x0445
3195 +#define BCM94712P_BOARD 0x0446
3196 +
3197 +/* BCM4318 boards */
3198 +#define BU4318_BOARD 0x0447
3199 +#define CB4318_BOARD 0x0448
3200 +#define MPG4318_BOARD 0x0449
3201 +#define MP4318_BOARD 0x044a
3202 +#define SD4318_BOARD 0x044b
3203 +
3204 +/* BCM63XX boards */
3205 +#define BCM96338_BOARD 0x6338
3206 +#define BCM96348_BOARD 0x6348
3207 +
3208 +/* Another mp4306 with SiGe */
3209 +#define BCM94306P_BOARD 0x044c
3210 +
3211 +/* mp4303 */
3212 +#define BCM94303MP_BOARD 0x044e
3213 +
3214 +/* mpsgh4306 */
3215 +#define BCM94306MPSGH_BOARD 0x044f
3216 +
3217 +/* BRCM 4306 w/ Front End Modules */
3218 +#define BCM94306MPM 0x0450
3219 +#define BCM94306MPL 0x0453
3220 +
3221 +/* 4712agr */
3222 +#define BCM94712AGR_BOARD 0x0451
3223 +
3224 +/* pcmcia 4303 */
3225 +#define PC4303_BOARD 0x0454
3226 +
3227 +/* 5350K */
3228 +#define BCM95350K_BOARD 0x0455
3229 +
3230 +/* 5350R */
3231 +#define BCM95350R_BOARD 0x0456
3232 +
3233 +/* 4306mplna */
3234 +#define BCM94306MPLNA_BOARD 0x0457
3235 +
3236 +/* 4320 boards */
3237 +#define BU4320_BOARD 0x0458
3238 +#define BU4320S_BOARD 0x0459
3239 +#define BCM94320PH_BOARD 0x045a
3240 +
3241 +/* 4306mph */
3242 +#define BCM94306MPH_BOARD 0x045b
3243 +
3244 +/* 4306pciv */
3245 +#define BCM94306PCIV_BOARD 0x045c
3246 +
3247 +#define BU4712SD_BOARD 0x045d
3248 +
3249 +#define BCM94320PFLSH_BOARD 0x045e
3250 +
3251 +#define BU4712L_BOARD 0x045f
3252 +#define BCM94712LGR_BOARD 0x0460
3253 +#define BCM94320R_BOARD 0x0461
3254 +
3255 +#define BU5352_BOARD 0x0462
3256 +
3257 +#define BCM94318MPGH_BOARD 0x0463
3258 +
3259 +#define BU4311_BOARD 0x0464
3260 +#define BCM94311MC_BOARD 0x0465
3261 +#define BCM94311MCAG_BOARD 0x0466
3262 +
3263 +#define BCM95352GR_BOARD 0x0467
3264 +
3265 +/* bcm95351agr */
3266 +#define BCM95351AGR_BOARD 0x0470
3267 +
3268 +/* bcm94704mpcb */
3269 +#define BCM94704MPCB_BOARD 0x0472
3270 +
3271 +/* 4785 boards */
3272 +#define BU4785_BOARD 0x0478
3273 +
3274 +/* 4321 boards */
3275 +#define BU4321_BOARD 0x046b
3276 +#define BU4321E_BOARD 0x047c
3277 +#define MP4321_BOARD 0x046c
3278 +#define CB2_4321_BOARD 0x046d
3279 +#define MC4321_BOARD 0x046e
3280 +
3281 +/* # of GPIO pins */
3282 +#define GPIO_NUMPINS 16
3283 +
3284 +/* radio ID codes */
3285 +#define NORADIO_ID 0xe4f5
3286 +#define NORADIO_IDCODE 0x4e4f5246
3287 +
3288 +#define BCM2050_ID 0x2050
3289 +#define BCM2050_IDCODE 0x02050000
3290 +#define BCM2050A0_IDCODE 0x1205017f
3291 +#define BCM2050A1_IDCODE 0x2205017f
3292 +#define BCM2050R8_IDCODE 0x8205017f
3293 +
3294 +#define BCM2055_ID 0x2055
3295 +#define BCM2055_IDCODE 0x02055000
3296 +#define BCM2055A0_IDCODE 0x1205517f
3297 +
3298 +#define BCM2060_ID 0x2060
3299 +#define BCM2060_IDCODE 0x02060000
3300 +#define BCM2060WW_IDCODE 0x1206017f
3301 +
3302 +#define BCM2062_ID 0x2062
3303 +#define BCM2062_IDCODE 0x02062000
3304 +#define BCM2062A0_IDCODE 0x0206217f
3305 +
3306 +/* parts of an idcode: */
3307 +#define IDCODE_MFG_MASK 0x00000fff
3308 +#define IDCODE_MFG_SHIFT 0
3309 +#define IDCODE_ID_MASK 0x0ffff000
3310 +#define IDCODE_ID_SHIFT 12
3311 +#define IDCODE_REV_MASK 0xf0000000
3312 +#define IDCODE_REV_SHIFT 28
3313 +
3314 +#endif /* _BCMDEVS_H */
3315 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
3316 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
3317 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2006-10-02 21:19:59.000000000 +0200
3318 @@ -0,0 +1,198 @@
3319 +/*
3320 + * local version of endian.h - byte order defines
3321 + *
3322 + * Copyright 2006, Broadcom Corporation
3323 + * All Rights Reserved.
3324 + *
3325 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3326 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3327 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3328 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3329 + *
3330 + * $Id: bcmendian.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
3331 +*/
3332 +
3333 +#ifndef _BCMENDIAN_H_
3334 +#define _BCMENDIAN_H_
3335 +
3336 +#include <typedefs.h>
3337 +
3338 +/* Byte swap a 16 bit value */
3339 +#define BCMSWAP16(val) \
3340 + ((uint16)(\
3341 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
3342 + (((uint16)(val) & (uint16)0xff00U) >> 8)))
3343 +
3344 +/* Byte swap a 32 bit value */
3345 +#define BCMSWAP32(val) \
3346 + ((uint32)(\
3347 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
3348 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
3349 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
3350 + (((uint32)(val) & (uint32)0xff000000UL) >> 24)))
3351 +
3352 +/* 2 Byte swap a 32 bit value */
3353 +#define BCMSWAP32BY16(val) \
3354 + ((uint32)(\
3355 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
3356 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16)))
3357 +
3358 +
3359 +static INLINE uint16
3360 +bcmswap16(uint16 val)
3361 +{
3362 + return BCMSWAP16(val);
3363 +}
3364 +
3365 +static INLINE uint32
3366 +bcmswap32(uint32 val)
3367 +{
3368 + return BCMSWAP32(val);
3369 +}
3370 +
3371 +static INLINE uint32
3372 +bcmswap32by16(uint32 val)
3373 +{
3374 + return BCMSWAP32BY16(val);
3375 +}
3376 +
3377 +/* buf - start of buffer of shorts to swap */
3378 +/* len - byte length of buffer */
3379 +static INLINE void
3380 +bcmswap16_buf(uint16 *buf, uint len)
3381 +{
3382 + len = len/2;
3383 +
3384 + while (len--) {
3385 + *buf = bcmswap16(*buf);
3386 + buf++;
3387 + }
3388 +}
3389 +
3390 +#ifndef hton16
3391 +#ifndef IL_BIGENDIAN
3392 +#define HTON16(i) BCMSWAP16(i)
3393 +#define hton16(i) bcmswap16(i)
3394 +#define hton32(i) bcmswap32(i)
3395 +#define ntoh16(i) bcmswap16(i)
3396 +#define ntoh32(i) bcmswap32(i)
3397 +#define ltoh16(i) (i)
3398 +#define ltoh32(i) (i)
3399 +#define htol16(i) (i)
3400 +#define htol32(i) (i)
3401 +#else
3402 +#define HTON16(i) (i)
3403 +#define hton16(i) (i)
3404 +#define hton32(i) (i)
3405 +#define ntoh16(i) (i)
3406 +#define ntoh32(i) (i)
3407 +#define ltoh16(i) bcmswap16(i)
3408 +#define ltoh32(i) bcmswap32(i)
3409 +#define htol16(i) bcmswap16(i)
3410 +#define htol32(i) bcmswap32(i)
3411 +#endif /* IL_BIGENDIAN */
3412 +#endif /* hton16 */
3413 +
3414 +#ifndef IL_BIGENDIAN
3415 +#define ltoh16_buf(buf, i)
3416 +#define htol16_buf(buf, i)
3417 +#else
3418 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
3419 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
3420 +#endif /* IL_BIGENDIAN */
3421 +
3422 +/*
3423 +* store 16-bit value to unaligned little endian byte array.
3424 +*/
3425 +static INLINE void
3426 +htol16_ua_store(uint16 val, uint8 *bytes)
3427 +{
3428 + bytes[0] = val&0xff;
3429 + bytes[1] = val>>8;
3430 +}
3431 +
3432 +/*
3433 +* store 32-bit value to unaligned little endian byte array.
3434 +*/
3435 +static INLINE void
3436 +htol32_ua_store(uint32 val, uint8 *bytes)
3437 +{
3438 + bytes[0] = val&0xff;
3439 + bytes[1] = (val>>8)&0xff;
3440 + bytes[2] = (val>>16)&0xff;
3441 + bytes[3] = val>>24;
3442 +}
3443 +
3444 +/*
3445 +* store 16-bit value to unaligned network(big) endian byte array.
3446 +*/
3447 +static INLINE void
3448 +hton16_ua_store(uint16 val, uint8 *bytes)
3449 +{
3450 + bytes[1] = val&0xff;
3451 + bytes[0] = val>>8;
3452 +}
3453 +
3454 +/*
3455 +* store 32-bit value to unaligned network(big) endian byte array.
3456 +*/
3457 +static INLINE void
3458 +hton32_ua_store(uint32 val, uint8 *bytes)
3459 +{
3460 + bytes[3] = val&0xff;
3461 + bytes[2] = (val>>8)&0xff;
3462 + bytes[1] = (val>>16)&0xff;
3463 + bytes[0] = val>>24;
3464 +}
3465 +
3466 +/*
3467 +* load 16-bit value from unaligned little endian byte array.
3468 +*/
3469 +static INLINE uint16
3470 +ltoh16_ua(void *bytes)
3471 +{
3472 + return (((uint8*)bytes)[1]<<8)+((uint8 *)bytes)[0];
3473 +}
3474 +
3475 +/*
3476 +* load 32-bit value from unaligned little endian byte array.
3477 +*/
3478 +static INLINE uint32
3479 +ltoh32_ua(void *bytes)
3480 +{
3481 + return (((uint8*)bytes)[3]<<24)+(((uint8*)bytes)[2]<<16)+
3482 + (((uint8*)bytes)[1]<<8)+((uint8*)bytes)[0];
3483 +}
3484 +
3485 +/*
3486 +* load 16-bit value from unaligned big(network) endian byte array.
3487 +*/
3488 +static INLINE uint16
3489 +ntoh16_ua(void *bytes)
3490 +{
3491 + return (((uint8*)bytes)[0]<<8)+((uint8*)bytes)[1];
3492 +}
3493 +
3494 +/*
3495 +* load 32-bit value from unaligned big(network) endian byte array.
3496 +*/
3497 +static INLINE uint32
3498 +ntoh32_ua(void *bytes)
3499 +{
3500 + return (((uint8*)bytes)[0]<<24)+(((uint8*)bytes)[1]<<16)+
3501 + (((uint8*)bytes)[2]<<8)+((uint8*)bytes)[3];
3502 +}
3503 +
3504 +#define ltoh_ua(ptr) (\
3505 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
3506 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
3507 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
3508 +)
3509 +
3510 +#define ntoh_ua(ptr) (\
3511 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
3512 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
3513 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
3514 +)
3515 +
3516 +#endif /* _BCMENDIAN_H_ */
3517 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
3518 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
3519 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2006-10-02 21:19:59.000000000 +0200
3520 @@ -0,0 +1,159 @@
3521 +/*
3522 + * NVRAM variable manipulation
3523 + *
3524 + * Copyright 2006, Broadcom Corporation
3525 + * All Rights Reserved.
3526 + *
3527 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3528 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3529 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3530 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3531 + *
3532 + * $Id: bcmnvram.h,v 1.17 2006/03/02 12:33:44 honor Exp $
3533 + */
3534 +
3535 +#ifndef _bcmnvram_h_
3536 +#define _bcmnvram_h_
3537 +
3538 +#ifndef _LANGUAGE_ASSEMBLY
3539 +
3540 +#include <typedefs.h>
3541 +#include <bcmdefs.h>
3542 +
3543 +struct nvram_header {
3544 + uint32 magic;
3545 + uint32 len;
3546 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
3547 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
3548 + uint32 config_ncdl; /* ncdl values for memc */
3549 +};
3550 +
3551 +struct nvram_tuple {
3552 + char *name;
3553 + char *value;
3554 + struct nvram_tuple *next;
3555 +};
3556 +
3557 +/*
3558 + * Initialize NVRAM access. May be unnecessary or undefined on certain
3559 + * platforms.
3560 + */
3561 +extern int nvram_init(void *sbh);
3562 +
3563 +/*
3564 + * Disable NVRAM access. May be unnecessary or undefined on certain
3565 + * platforms.
3566 + */
3567 +extern void nvram_exit(void *sbh);
3568 +
3569 +/*
3570 + * Get the value of an NVRAM variable. The pointer returned may be
3571 + * invalid after a set.
3572 + * @param name name of variable to get
3573 + * @return value of variable or NULL if undefined
3574 + */
3575 +extern char * nvram_get(const char *name);
3576 +
3577 +/*
3578 + * Read the reset GPIO value from the nvram and set the GPIO
3579 + * as input
3580 + */
3581 +extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
3582 +extern int BCMINITFN(nvram_gpio_init)(const char *name, void *sbh);
3583 +extern int BCMINITFN(nvram_gpio_set)(const char *name, void *sbh, int type);
3584 +
3585 +/*
3586 + * Get the value of an NVRAM variable.
3587 + * @param name name of variable to get
3588 + * @return value of variable or NUL if undefined
3589 + */
3590 +#define nvram_safe_get(name) (nvram_get(name) ? : "")
3591 +
3592 +#define nvram_safe_unset(name) ({ \
3593 + if(nvram_get(name)) \
3594 + nvram_unset(name); \
3595 +})
3596 +
3597 +#define nvram_safe_set(name, value) ({ \
3598 + if(!nvram_get(name) || strcmp(nvram_get(name), value)) \
3599 + nvram_set(name, value); \
3600 +})
3601 +
3602 +/*
3603 + * Match an NVRAM variable.
3604 + * @param name name of variable to match
3605 + * @param match value to compare against value of variable
3606 + * @return TRUE if variable is defined and its value is string equal
3607 + * to match or FALSE otherwise
3608 + */
3609 +static INLINE int
3610 +nvram_match(char *name, char *match) {
3611 + const char *value = nvram_get(name);
3612 + return (value && !strcmp(value, match));
3613 +}
3614 +
3615 +/*
3616 + * Inversely match an NVRAM variable.
3617 + * @param name name of variable to match
3618 + * @param match value to compare against value of variable
3619 + * @return TRUE if variable is defined and its value is not string
3620 + * equal to invmatch or FALSE otherwise
3621 + */
3622 +static INLINE int
3623 +nvram_invmatch(char *name, char *invmatch) {
3624 + const char *value = nvram_get(name);
3625 + return (value && strcmp(value, invmatch));
3626 +}
3627 +
3628 +/*
3629 + * Set the value of an NVRAM variable. The name and value strings are
3630 + * copied into private storage. Pointers to previously set values
3631 + * may become invalid. The new value may be immediately
3632 + * retrieved but will not be permanently stored until a commit.
3633 + * @param name name of variable to set
3634 + * @param value value of variable
3635 + * @return 0 on success and errno on failure
3636 + */
3637 +extern int nvram_set(const char *name, const char *value);
3638 +
3639 +/*
3640 + * Unset an NVRAM variable. Pointers to previously set values
3641 + * remain valid until a set.
3642 + * @param name name of variable to unset
3643 + * @return 0 on success and errno on failure
3644 + * NOTE: use nvram_commit to commit this change to flash.
3645 + */
3646 +extern int nvram_unset(const char *name);
3647 +
3648 +/*
3649 + * Commit NVRAM variables to permanent storage. All pointers to values
3650 + * may be invalid after a commit.
3651 + * NVRAM values are undefined after a commit.
3652 + * @return 0 on success and errno on failure
3653 + */
3654 +extern int nvram_commit(void);
3655 +
3656 +/*
3657 + * Get all NVRAM variables (format name=value\0 ... \0\0).
3658 + * @param buf buffer to store variables
3659 + * @param count size of buffer in bytes
3660 + * @return 0 on success and errno on failure
3661 + */
3662 +extern int nvram_getall(char *buf, int count);
3663 +
3664 +extern int file2nvram(char *filename, char *varname);
3665 +extern int nvram2file(char *varname, char *filename);
3666 +
3667 +#endif /* _LANGUAGE_ASSEMBLY */
3668 +
3669 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
3670 +#define NVRAM_CLEAR_MAGIC 0x0
3671 +#define NVRAM_INVALID_MAGIC 0xFFFFFFFF
3672 +#define NVRAM_VERSION 1
3673 +#define NVRAM_HEADER_SIZE 20
3674 +#define NVRAM_SPACE 0x8000
3675 +
3676 +#define NVRAM_MAX_VALUE_LEN 255
3677 +#define NVRAM_MAX_PARAM_LEN 64
3678 +
3679 +#endif /* _bcmnvram_h_ */
3680 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
3681 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
3682 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2006-10-02 21:19:59.000000000 +0200
3683 @@ -0,0 +1,108 @@
3684 +/*
3685 + * Misc useful routines to access NIC local SROM/OTP .
3686 + *
3687 + * Copyright 2006, Broadcom Corporation
3688 + * All Rights Reserved.
3689 + *
3690 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3691 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3692 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3693 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3694 + *
3695 + * $Id: bcmsrom.h,v 1.1.1.13 2006/04/15 01:29:08 michael Exp $
3696 + */
3697 +
3698 +#ifndef _bcmsrom_h_
3699 +#define _bcmsrom_h_
3700 +
3701 +/* Maximum srom: 4 Kilobits == 512 bytes */
3702 +#define SROM_MAX 512
3703 +
3704 +/* SROM Rev 4: Reallocate the software part of the srom to accomodate
3705 + * MIMO features. It assumes up to two PCIE functions and 440 bytes
3706 + * of useable srom i.e. the useable storage in chips with OTP that
3707 + * implements hardware redundancy.
3708 + */
3709 +
3710 +#define SROM4_WORDS 220
3711 +
3712 +#define SROM4_SIGN 32
3713 +#define SROM4_SIGNATURE 0x5372
3714 +
3715 +#define SROM4_BREV 33
3716 +
3717 +#define SROM4_BFL0 34
3718 +#define SROM4_BFL1 35
3719 +#define SROM4_BFL2 36
3720 +#define SROM4_BFL3 37
3721 +
3722 +#define SROM4_MACHI 38
3723 +#define SROM4_MACMID 39
3724 +#define SROM4_MACLO 40
3725 +
3726 +#define SROM4_CCODE 41
3727 +#define SROM4_REGREV 42
3728 +
3729 +#define SROM4_LEDBH10 43
3730 +#define SROM4_LEDBH32 44
3731 +
3732 +#define SROM4_LEDDC 45
3733 +
3734 +#define SROM4_AA 46
3735 +#define SROM4_AA2G_MASK 0x00ff
3736 +#define SROM4_AA2G_SHIFT 0
3737 +#define SROM4_AA5G_MASK 0xff00
3738 +#define SROM4_AA5G_SHIFT 8
3739 +
3740 +#define SROM4_AG10 47
3741 +#define SROM4_AG32 48
3742 +
3743 +#define SROM4_TXPID2G 49
3744 +#define SROM4_TXPID5G 51
3745 +#define SROM4_TXPID5GL 53
3746 +#define SROM4_TXPID5GH 55
3747 +
3748 +/* Per-path fields */
3749 +#define MAX_PATH 4
3750 +#define SROM4_PATH0 64
3751 +#define SROM4_PATH1 87
3752 +#define SROM4_PATH2 110
3753 +#define SROM4_PATH3 133
3754 +
3755 +#define SROM4_2G_ITT_MAXP 0
3756 +#define SROM4_2G_PA 1
3757 +#define SROM4_5G_ITT_MAXP 5
3758 +#define SROM4_5GLH_MAXP 6
3759 +#define SROM4_5G_PA 7
3760 +#define SROM4_5GL_PA 11
3761 +#define SROM4_5GH_PA 15
3762 +
3763 +/* Fields in the ITT_MAXP and 5GLH_MAXP words */
3764 +#define B2G_MAXP_MASK 0xff
3765 +#define B2G_ITT_SHIFT 8
3766 +#define B5G_MAXP_MASK 0xff
3767 +#define B5G_ITT_SHIFT 8
3768 +#define B5GH_MAXP_MASK 0xff
3769 +#define B5GL_MAXP_SHIFT 8
3770 +
3771 +/* All the miriad power offsets */
3772 +#define SROM4_2G_CCKPO 156
3773 +#define SROM4_2G_OFDMPO 157
3774 +#define SROM4_5G_OFDMPO 159
3775 +#define SROM4_5GL_OFDMPO 161
3776 +#define SROM4_5GH_OFDMPO 163
3777 +#define SROM4_2G_MCSPO 165
3778 +#define SROM4_5G_MCSPO 173
3779 +#define SROM4_5GL_MCSPO 181
3780 +#define SROM4_5GH_MCSPO 189
3781 +#define SROM4_CCDPO 197
3782 +#define SROM4_STBCPO 198
3783 +#define SROM4_BW40PO 199
3784 +#define SROM4_BWDUPPO 200
3785 +
3786 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, uint *count);
3787 +
3788 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
3789 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
3790 +
3791 +#endif /* _bcmsrom_h_ */
3792 diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
3793 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
3794 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2006-10-02 21:19:59.000000000 +0200
3795 @@ -0,0 +1,433 @@
3796 +/*
3797 + * Misc useful os-independent macros and functions.
3798 + *
3799 + * Copyright 2006, Broadcom Corporation
3800 + * All Rights Reserved.
3801 + *
3802 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3803 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3804 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3805 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3806 + * $Id: bcmutils.h,v 1.1.1.16 2006/04/08 06:13:39 honor Exp $
3807 + */
3808 +
3809 +#ifndef _bcmutils_h_
3810 +#define _bcmutils_h_
3811 +
3812 +/* ** driver-only section ** */
3813 +#ifdef BCMDRIVER
3814 +
3815 +#define _BCM_U 0x01 /* upper */
3816 +#define _BCM_L 0x02 /* lower */
3817 +#define _BCM_D 0x04 /* digit */
3818 +#define _BCM_C 0x08 /* cntrl */
3819 +#define _BCM_P 0x10 /* punct */
3820 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
3821 +#define _BCM_X 0x40 /* hex digit */
3822 +#define _BCM_SP 0x80 /* hard space (0x20) */
3823 +
3824 +#define GPIO_PIN_NOTDEFINED 0x20 /* Pin not defined */
3825 +
3826 +extern unsigned char bcm_ctype[];
3827 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
3828 +
3829 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
3830 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
3831 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
3832 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
3833 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
3834 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
3835 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
3836 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
3837 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
3838 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
3839 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
3840 +
3841 +/*
3842 + * Spin at most 'us' microseconds while 'exp' is true.
3843 + * Caller should explicitly test 'exp' when this completes
3844 + * and take appropriate error action if 'exp' is still true.
3845 + */
3846 +#define SPINWAIT(exp, us) { \
3847 + uint countdown = (us) + 9; \
3848 + while ((exp) && (countdown >= 10)) {\
3849 + OSL_DELAY(10); \
3850 + countdown -= 10; \
3851 + } \
3852 +}
3853 +
3854 +struct ether_addr {
3855 + uint8 octet[6];
3856 +} __attribute__((packed));
3857 +
3858 +/* string */
3859 +extern uchar bcm_toupper(uchar c);
3860 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
3861 +extern char *bcmstrstr(char *haystack, char *needle);
3862 +extern char *bcmstrcat(char *dest, const char *src);
3863 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
3864 +/* ethernet address */
3865 +extern char *bcm_ether_ntoa(struct ether_addr *ea, char *buf);
3866 +/* variable access */
3867 +extern char *getvar(char *vars, char *name);
3868 +extern int getintvar(char *vars, char *name);
3869 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
3870 +#ifdef BCMPERFSTATS
3871 +extern void bcm_perf_enable(void);
3872 +extern void bcmstats(char *fmt);
3873 +extern void bcmlog(char *fmt, uint a1, uint a2);
3874 +extern void bcmdumplog(char *buf, int size);
3875 +extern int bcmdumplogent(char *buf, uint idx);
3876 +#else
3877 +#define bcm_perf_enable()
3878 +#define bcmstats(fmt)
3879 +#define bcmlog(fmt, a1, a2)
3880 +#define bcmdumplog(buf, size) *buf = '\0'
3881 +#define bcmdumplogent(buf, idx) -1
3882 +#endif /* BCMPERFSTATS */
3883 +extern char *bcm_nvram_vars(uint *length);
3884 +extern int bcm_nvram_cache(void *sbh);
3885 +
3886 +/* Support for sharing code across in-driver iovar implementations.
3887 + * The intent is that a driver use this structure to map iovar names
3888 + * to its (private) iovar identifiers, and the lookup function to
3889 + * find the entry. Macros are provided to map ids and get/set actions
3890 + * into a single number space for a switch statement.
3891 + */
3892 +
3893 +/* iovar structure */
3894 +typedef struct bcm_iovar {
3895 + const char *name; /* name for lookup and display */
3896 + uint16 varid; /* id for switch */
3897 + uint16 flags; /* driver-specific flag bits */
3898 + uint16 type; /* base type of argument */
3899 + uint16 minlen; /* min length for buffer vars */
3900 +} bcm_iovar_t;
3901 +
3902 +/* varid definitions are per-driver, may use these get/set bits */
3903 +
3904 +/* IOVar action bits for id mapping */
3905 +#define IOV_GET 0 /* Get an iovar */
3906 +#define IOV_SET 1 /* Set an iovar */
3907 +
3908 +/* Varid to actionid mapping */
3909 +#define IOV_GVAL(id) ((id)*2)
3910 +#define IOV_SVAL(id) (((id)*2)+IOV_SET)
3911 +#define IOV_ISSET(actionid) ((actionid & IOV_SET) == IOV_SET)
3912 +
3913 +/* flags are per-driver based on driver attributes */
3914 +
3915 +/* Base type definitions */
3916 +#define IOVT_VOID 0 /* no value (implictly set only) */
3917 +#define IOVT_BOOL 1 /* any value ok (zero/nonzero) */
3918 +#define IOVT_INT8 2 /* integer values are range-checked */
3919 +#define IOVT_UINT8 3 /* unsigned int 8 bits */
3920 +#define IOVT_INT16 4 /* int 16 bits */
3921 +#define IOVT_UINT16 5 /* unsigned int 16 bits */
3922 +#define IOVT_INT32 6 /* int 32 bits */
3923 +#define IOVT_UINT32 7 /* unsigned int 32 bits */
3924 +#define IOVT_BUFFER 8 /* buffer is size-checked as per minlen */
3925 +
3926 +extern const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name);
3927 +extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool set);
3928 +
3929 +#endif /* #ifdef BCMDRIVER */
3930 +
3931 +/* ** driver/apps-shared section ** */
3932 +
3933 +#define BCME_STRLEN 64 /* Max string length for BCM errors */
3934 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
3935 +
3936 +
3937 +/*
3938 + * error codes could be added but the defined ones shouldn't be changed/deleted
3939 + * these error codes are exposed to the user code
3940 + * when ever a new error code is added to this list
3941 + * please update errorstring table with the related error string and
3942 + * update osl files with os specific errorcode map
3943 +*/
3944 +
3945 +#define BCME_OK 0 /* Success */
3946 +#define BCME_ERROR -1 /* Error generic */
3947 +#define BCME_BADARG -2 /* Bad Argument */
3948 +#define BCME_BADOPTION -3 /* Bad option */
3949 +#define BCME_NOTUP -4 /* Not up */
3950 +#define BCME_NOTDOWN -5 /* Not down */
3951 +#define BCME_NOTAP -6 /* Not AP */
3952 +#define BCME_NOTSTA -7 /* Not STA */
3953 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
3954 +#define BCME_RADIOOFF -9 /* Radio Off */
3955 +#define BCME_NOTBANDLOCKED -10 /* Not band locked */
3956 +#define BCME_NOCLK -11 /* No Clock */
3957 +#define BCME_BADRATESET -12 /* BAD Rate valueset */
3958 +#define BCME_BADBAND -13 /* BAD Band */
3959 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
3960 +#define BCME_BUFTOOLONG -15 /* Buffer too long */
3961 +#define BCME_BUSY -16 /* Busy */
3962 +#define BCME_NOTASSOCIATED -17 /* Not Associated */
3963 +#define BCME_BADSSIDLEN -18 /* Bad SSID len */
3964 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel */
3965 +#define BCME_BADCHAN -20 /* Bad Channel */
3966 +#define BCME_BADADDR -21 /* Bad Address */
3967 +#define BCME_NORESOURCE -22 /* Not Enough Resources */
3968 +#define BCME_UNSUPPORTED -23 /* Unsupported */
3969 +#define BCME_BADLEN -24 /* Bad length */
3970 +#define BCME_NOTREADY -25 /* Not Ready */
3971 +#define BCME_EPERM -26 /* Not Permitted */
3972 +#define BCME_NOMEM -27 /* No Memory */
3973 +#define BCME_ASSOCIATED -28 /* Associated */
3974 +#define BCME_RANGE -29 /* Not In Range */
3975 +#define BCME_NOTFOUND -30 /* Not Found */
3976 +#define BCME_WME_NOT_ENABLED -31 /* WME Not Enabled */
3977 +#define BCME_TSPEC_NOTFOUND -32 /* TSPEC Not Found */
3978 +#define BCME_ACM_NOTSUPPORTED -33 /* ACM Not Supported */
3979 +#define BCME_NOT_WME_ASSOCIATION -34 /* Not WME Association */
3980 +#define BCME_SDIO_ERROR -35 /* SDIO Bus Error */
3981 +#define BCME_DONGLE_DOWN -36 /* Dongle Not Accessible */
3982 +#define BCME_LAST BCME_DONGLE_DOWN
3983 +
3984 +/* These are collection of BCME Error strings */
3985 +#define BCMERRSTRINGTABLE { \
3986 + "OK", \
3987 + "Undefined error", \
3988 + "Bad Argument", \
3989 + "Bad Option", \
3990 + "Not up", \
3991 + "Not down", \
3992 + "Not AP", \
3993 + "Not STA", \
3994 + "Bad Key Index", \
3995 + "Radio Off", \
3996 + "Not band locked", \
3997 + "No clock", \
3998 + "Bad Rate valueset", \
3999 + "Bad Band", \
4000 + "Buffer too short", \
4001 + "Buffer too long", \
4002 + "Busy", \
4003 + "Not Associated", \
4004 + "Bad SSID len", \
4005 + "Out of Range Channel", \
4006 + "Bad Channel", \
4007 + "Bad Address", \
4008 + "Not Enough Resources", \
4009 + "Unsupported", \
4010 + "Bad length", \
4011 + "Not Ready", \
4012 + "Not Permitted", \
4013 + "No Memory", \
4014 + "Associated", \
4015 + "Not In Range", \
4016 + "Not Found", \
4017 + "WME Not Enabled", \
4018 + "TSPEC Not Found", \
4019 + "ACM Not Supported", \
4020 + "Not WME Association", \
4021 + "SDIO Bus Error", \
4022 + "Dongle Not Accessible" \
4023 +}
4024 +
4025 +#ifndef ABS
4026 +#define ABS(a) (((a) < 0)?-(a):(a))
4027 +#endif /* ABS */
4028 +
4029 +#ifndef MIN
4030 +#define MIN(a, b) (((a) < (b))?(a):(b))
4031 +#endif /* MIN */
4032 +
4033 +#ifndef MAX
4034 +#define MAX(a, b) (((a) > (b))?(a):(b))
4035 +#endif /* MAX */
4036 +
4037 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
4038 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
4039 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
4040 +#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0)
4041 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
4042 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
4043 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
4044 +
4045 +/* bit map related macros */
4046 +#ifndef setbit
4047 +#ifndef NBBY /* the BSD family defines NBBY */
4048 +#define NBBY 8 /* 8 bits per byte */
4049 +#endif /* #ifndef NBBY */
4050 +#define setbit(a, i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
4051 +#define clrbit(a, i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
4052 +#define isset(a, i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
4053 +#define isclr(a, i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
4054 +#endif /* setbit */
4055 +
4056 +#define NBITS(type) (sizeof(type) * 8)
4057 +#define NBITVAL(nbits) (1 << (nbits))
4058 +#define MAXBITVAL(nbits) ((1 << (nbits)) - 1)
4059 +#define NBITMASK(nbits) MAXBITVAL(nbits)
4060 +#define MAXNBVAL(nbyte) MAXBITVAL((nbyte) * 8)
4061 +
4062 +/* basic mux operation - can be optimized on several architectures */
4063 +#define MUX(pred, true, false) ((pred) ? (true) : (false))
4064 +
4065 +/* modulo inc/dec - assumes x E [0, bound - 1] */
4066 +#define MODDEC(x, bound) MUX((x) == 0, (bound) - 1, (x) - 1)
4067 +#define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
4068 +
4069 +/* modulo inc/dec, bound = 2^k */
4070 +#define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1))
4071 +#define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1))
4072 +
4073 +/* modulo add/sub - assumes x, y E [0, bound - 1] */
4074 +#define MODADD(x, y, bound) \
4075 + MUX((x) + (y) >= (bound), (x) + (y) - (bound), (x) + (y))
4076 +#define MODSUB(x, y, bound) \
4077 + MUX(((int)(x)) - ((int)(y)) < 0, (x) - (y) + (bound), (x) - (y))
4078 +
4079 +/* module add/sub, bound = 2^k */
4080 +#define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
4081 +#define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
4082 +
4083 +/* crc defines */
4084 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
4085 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
4086 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
4087 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
4088 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
4089 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
4090 +
4091 +/* bcm_format_flags() bit description structure */
4092 +typedef struct bcm_bit_desc {
4093 + uint32 bit;
4094 + char* name;
4095 +} bcm_bit_desc_t;
4096 +
4097 +/* tag_ID/length/value_buffer tuple */
4098 +typedef struct bcm_tlv {
4099 + uint8 id;
4100 + uint8 len;
4101 + uint8 data[1];
4102 +} bcm_tlv_t;
4103 +
4104 +/* Check that bcm_tlv_t fits into the given buflen */
4105 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
4106 +
4107 +/* buffer length for ethernet address from bcm_ether_ntoa() */
4108 +#define ETHER_ADDR_STR_LEN 18 /* 18-bytes of Ethernet address buffer length */
4109 +
4110 +/* unaligned load and store macros */
4111 +#ifdef IL_BIGENDIAN
4112 +static INLINE uint32
4113 +load32_ua(uint8 *a)
4114 +{
4115 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
4116 +}
4117 +
4118 +static INLINE void
4119 +store32_ua(uint8 *a, uint32 v)
4120 +{
4121 + a[0] = (v >> 24) & 0xff;
4122 + a[1] = (v >> 16) & 0xff;
4123 + a[2] = (v >> 8) & 0xff;
4124 + a[3] = v & 0xff;
4125 +}
4126 +
4127 +static INLINE uint16
4128 +load16_ua(uint8 *a)
4129 +{
4130 + return ((a[0] << 8) | a[1]);
4131 +}
4132 +
4133 +static INLINE void
4134 +store16_ua(uint8 *a, uint16 v)
4135 +{
4136 + a[0] = (v >> 8) & 0xff;
4137 + a[1] = v & 0xff;
4138 +}
4139 +
4140 +#else
4141 +
4142 +static INLINE uint32
4143 +load32_ua(uint8 *a)
4144 +{
4145 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
4146 +}
4147 +
4148 +static INLINE void
4149 +store32_ua(uint8 *a, uint32 v)
4150 +{
4151 + a[3] = (v >> 24) & 0xff;
4152 + a[2] = (v >> 16) & 0xff;
4153 + a[1] = (v >> 8) & 0xff;
4154 + a[0] = v & 0xff;
4155 +}
4156 +
4157 +static INLINE uint16
4158 +load16_ua(uint8 *a)
4159 +{
4160 + return ((a[1] << 8) | a[0]);
4161 +}
4162 +
4163 +static INLINE void
4164 +store16_ua(uint8 *a, uint16 v)
4165 +{
4166 + a[1] = (v >> 8) & 0xff;
4167 + a[0] = v & 0xff;
4168 +}
4169 +
4170 +#endif /* IL_BIGENDIAN */
4171 +
4172 +/* externs */
4173 +/* crc */
4174 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
4175 +extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
4176 +extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
4177 +/* format/print */
4178 +extern void printfbig(char *buf);
4179 +
4180 +/* IE parsing */
4181 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
4182 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
4183 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
4184 +
4185 +/* bcmerror */
4186 +extern const char *bcmerrorstr(int bcmerror);
4187 +
4188 +/* multi-bool data type: set of bools, mbool is true if any is set */
4189 +typedef uint32 mbool;
4190 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
4191 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
4192 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
4193 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
4194 +
4195 +/* power conversion */
4196 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
4197 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
4198 +
4199 +/* generic datastruct to help dump routines */
4200 +struct fielddesc {
4201 + char *nameandfmt;
4202 + uint32 offset;
4203 + uint32 len;
4204 +};
4205 +
4206 +/* Buffer structure for collecting string-formatted data
4207 +* using bcm_bprintf() API.
4208 +* Use bcm_binit() to initialize before use
4209 +*/
4210 +struct bcmstrbuf
4211 +{
4212 + char *buf; /* pointer to current position in origbuf */
4213 + uint size; /* current (residual) size in bytes */
4214 + char *origbuf; /* unmodified pointer to orignal buffer */
4215 + uint origsize; /* unmodified orignal buffer size in bytes */
4216 +};
4217 +
4218 +extern void bcm_binit(struct bcmstrbuf *b, char *buf, uint size);
4219 +extern int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...);
4220 +
4221 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
4222 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str,
4223 + char *buf, uint32 bufsize);
4224 +
4225 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
4226 +extern uint bcm_bitcount(uint8 *bitmap, uint bytelength);
4227 +
4228 +#endif /* _bcmutils_h_ */
4229 diff -urN linux.old/arch/mips/bcm947xx/include/hndcpu.h linux.dev/arch/mips/bcm947xx/include/hndcpu.h
4230 --- linux.old/arch/mips/bcm947xx/include/hndcpu.h 1970-01-01 01:00:00.000000000 +0100
4231 +++ linux.dev/arch/mips/bcm947xx/include/hndcpu.h 2006-10-02 21:19:59.000000000 +0200
4232 @@ -0,0 +1,28 @@
4233 +/*
4234 + * HND SiliconBackplane MIPS/ARM cores software interface.
4235 + *
4236 + * Copyright 2006, Broadcom Corporation
4237 + * All Rights Reserved.
4238 + *
4239 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4240 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4241 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4242 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4243 + *
4244 + * $Id: hndcpu.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
4245 + */
4246 +
4247 +#ifndef _hndcpu_h_
4248 +#define _hndcpu_h_
4249 +
4250 +#if defined(mips)
4251 +#include <hndmips.h>
4252 +#elif defined(__ARM_ARCH_4T__)
4253 +#include <hndarm.h>
4254 +#endif
4255 +
4256 +extern uint sb_irq(sb_t *sbh);
4257 +extern uint32 sb_cpu_clock(sb_t *sbh);
4258 +extern void sb_cpu_wait(void);
4259 +
4260 +#endif /* _hndcpu_h_ */
4261 diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
4262 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
4263 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2006-10-02 21:19:59.000000000 +0200
4264 @@ -0,0 +1,45 @@
4265 +/*
4266 + * HND SiliconBackplane MIPS core software interface.
4267 + *
4268 + * Copyright 2006, Broadcom Corporation
4269 + * All Rights Reserved.
4270 + *
4271 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4272 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4273 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4274 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4275 + *
4276 + * $Id: hndmips.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
4277 + */
4278 +
4279 +#ifndef _hndmips_h_
4280 +#define _hndmips_h_
4281 +
4282 +extern void sb_mips_init(sb_t *sbh, uint shirq_map_base);
4283 +extern bool sb_mips_setclock(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
4284 +extern void enable_pfc(uint32 mode);
4285 +extern uint32 sb_memc_get_ncdl(sb_t *sbh);
4286 +
4287 +#if defined(BCMPERFSTATS)
4288 +/* enable counting - exclusive version. Only one set of counters allowed at a time */
4289 +extern void hndmips_perf_instrcount_enable(void);
4290 +extern void hndmips_perf_icachecount_enable(void);
4291 +extern void hndmips_perf_dcachecount_enable(void);
4292 +/* start and stop counting */
4293 +#define hndmips_perf_start01() \
4294 + MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) | 0x80008000)
4295 +#define hndmips_perf_stop01() \
4296 + MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) & ~0x80008000)
4297 +/* retrieve coutners - counters *decrement* */
4298 +#define hndmips_perf_read0() -(long)(MFC0(C0_PERFORMANCE, 0))
4299 +#define hndmips_perf_read1() -(long)(MFC0(C0_PERFORMANCE, 1))
4300 +#define hndmips_perf_read2() -(long)(MFC0(C0_PERFORMANCE, 2))
4301 +/* enable counting - modular version. Each counters can be enabled separately. */
4302 +extern void hndmips_perf_icache_hit_enable(void);
4303 +extern void hndmips_perf_icache_miss_enable(void);
4304 +extern uint32 hndmips_perf_read_instrcount(void);
4305 +extern uint32 hndmips_perf_read_cache_miss(void);
4306 +extern uint32 hndmips_perf_read_cache_hit(void);
4307 +#endif /* defined(BCMINTERNAL) || defined (BCMPERFSTATS) */
4308 +
4309 +#endif /* _hndmips_h_ */
4310 diff -urN linux.old/arch/mips/bcm947xx/include/hndpci.h linux.dev/arch/mips/bcm947xx/include/hndpci.h
4311 --- linux.old/arch/mips/bcm947xx/include/hndpci.h 1970-01-01 01:00:00.000000000 +0100
4312 +++ linux.dev/arch/mips/bcm947xx/include/hndpci.h 2006-10-02 21:19:59.000000000 +0200
4313 @@ -0,0 +1,30 @@
4314 +/*
4315 + * HND SiliconBackplane PCI core software interface.
4316 + *
4317 + * $Id: hndpci.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
4318 + * Copyright 2006, Broadcom Corporation
4319 + * All Rights Reserved.
4320 + *
4321 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4322 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4323 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4324 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4325 + */
4326 +
4327 +#ifndef _hndpci_h_
4328 +#define _hndpci_h_
4329 +
4330 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4331 + int len);
4332 +extern int extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4333 + int len);
4334 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4335 + int len);
4336 +extern int extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4337 + int len);
4338 +extern void sbpci_ban(uint16 core);
4339 +extern int sbpci_init(sb_t *sbh);
4340 +extern int sbpci_init_pci(sb_t *sbh);
4341 +extern void sbpci_check(sb_t *sbh);
4342 +
4343 +#endif /* _hndpci_h_ */
4344 diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
4345 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
4346 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2006-10-02 21:19:59.000000000 +0200
4347 @@ -0,0 +1,417 @@
4348 +/*
4349 + * Linux-specific abstractions to gain some independence from linux kernel versions.
4350 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
4351 + *
4352 + * Copyright 2006, Broadcom Corporation
4353 + * All Rights Reserved.
4354 + *
4355 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4356 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4357 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4358 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4359 + *
4360 + * $Id: linuxver.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
4361 + */
4362 +
4363 +#ifndef _linuxver_h_
4364 +#define _linuxver_h_
4365 +
4366 +#include <linux/config.h>
4367 +#include <linux/version.h>
4368 +
4369 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0))
4370 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
4371 +#ifdef __UNDEF_NO_VERSION__
4372 +#undef __NO_VERSION__
4373 +#else
4374 +#define __NO_VERSION__
4375 +#endif
4376 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0) */
4377 +
4378 +#if defined(MODULE) && defined(MODVERSIONS)
4379 +#include <linux/modversions.h>
4380 +#endif
4381 +
4382 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 0)
4383 +#include <linux/moduleparam.h>
4384 +#endif
4385 +
4386 +
4387 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)
4388 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
4389 +#define module_param_string(_name_, _string_, _size_, _perm_) \
4390 + MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
4391 +#endif
4392 +
4393 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
4394 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 9))
4395 +#include <linux/malloc.h>
4396 +#else
4397 +#include <linux/slab.h>
4398 +#endif
4399 +
4400 +#include <linux/types.h>
4401 +#include <linux/init.h>
4402 +#include <linux/mm.h>
4403 +#include <linux/string.h>
4404 +#include <linux/pci.h>
4405 +#include <linux/interrupt.h>
4406 +#include <linux/netdevice.h>
4407 +#include <asm/io.h>
4408 +
4409 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
4410 +#include <linux/workqueue.h>
4411 +#else
4412 +#include <linux/tqueue.h>
4413 +#ifndef work_struct
4414 +#define work_struct tq_struct
4415 +#endif
4416 +#ifndef INIT_WORK
4417 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
4418 +#endif
4419 +#ifndef schedule_work
4420 +#define schedule_work(_work) schedule_task((_work))
4421 +#endif
4422 +#ifndef flush_scheduled_work
4423 +#define flush_scheduled_work() flush_scheduled_tasks()
4424 +#endif
4425 +#endif /* LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41) */
4426 +
4427 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
4428 +/* Some distributions have their own 2.6.x compatibility layers */
4429 +#ifndef IRQ_NONE
4430 +typedef void irqreturn_t;
4431 +#define IRQ_NONE
4432 +#define IRQ_HANDLED
4433 +#define IRQ_RETVAL(x)
4434 +#endif
4435 +#else
4436 +typedef irqreturn_t(*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
4437 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0) */
4438 +
4439 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
4440 +
4441 +#include <pcmcia/version.h>
4442 +#include <pcmcia/cs_types.h>
4443 +#include <pcmcia/cs.h>
4444 +#include <pcmcia/cistpl.h>
4445 +#include <pcmcia/cisreg.h>
4446 +#include <pcmcia/ds.h>
4447 +
4448 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 69))
4449 +/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
4450 + * does this, but it's not in 2.4 so we do our own for now.
4451 + */
4452 +static inline void
4453 +cs_error(client_handle_t handle, int func, int ret)
4454 +{
4455 + error_info_t err = { func, ret };
4456 + CardServices(ReportError, handle, &err);
4457 +}
4458 +#endif
4459 +
4460 +#endif /* CONFIG_PCMCIA */
4461 +
4462 +#ifndef __exit
4463 +#define __exit
4464 +#endif
4465 +#ifndef __devexit
4466 +#define __devexit
4467 +#endif
4468 +#ifndef __devinit
4469 +#define __devinit __init
4470 +#endif
4471 +#ifndef __devinitdata
4472 +#define __devinitdata
4473 +#endif
4474 +#ifndef __devexit_p
4475 +#define __devexit_p(x) x
4476 +#endif
4477 +
4478 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0))
4479 +
4480 +#define pci_get_drvdata(dev) (dev)->sysdata
4481 +#define pci_set_drvdata(dev, value) (dev)->sysdata = (value)
4482 +
4483 +/*
4484 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
4485 + */
4486 +
4487 +struct pci_device_id {
4488 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
4489 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
4490 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
4491 + unsigned long driver_data; /* Data private to the driver */
4492 +};
4493 +
4494 +struct pci_driver {
4495 + struct list_head node;
4496 + char *name;
4497 + const struct pci_device_id *id_table; /* NULL if wants all devices */
4498 + int (*probe)(struct pci_dev *dev,
4499 + const struct pci_device_id *id); /* New device inserted */
4500 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug
4501 + * capable driver)
4502 + */
4503 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
4504 + void (*resume)(struct pci_dev *dev); /* Device woken up */
4505 +};
4506 +
4507 +#define MODULE_DEVICE_TABLE(type, name)
4508 +#define PCI_ANY_ID (~0)
4509 +
4510 +/* compatpci.c */
4511 +#define pci_module_init pci_register_driver
4512 +extern int pci_register_driver(struct pci_driver *drv);
4513 +extern void pci_unregister_driver(struct pci_driver *drv);
4514 +
4515 +#endif /* PCI registration */
4516 +
4517 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18))
4518 +#ifdef MODULE
4519 +#define module_init(x) int init_module(void) { return x(); }
4520 +#define module_exit(x) void cleanup_module(void) { x(); }
4521 +#else
4522 +#define module_init(x) __initcall(x);
4523 +#define module_exit(x) __exitcall(x);
4524 +#endif
4525 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18) */
4526 +
4527 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 48))
4528 +#define list_for_each(pos, head) \
4529 + for (pos = (head)->next; pos != (head); pos = pos->next)
4530 +#endif
4531 +
4532 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 13))
4533 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
4534 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 44))
4535 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
4536 +#endif
4537 +
4538 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 23))
4539 +#define pci_enable_device(dev) do { } while (0)
4540 +#endif
4541 +
4542 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 14))
4543 +#define net_device device
4544 +#endif
4545 +
4546 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 42))
4547 +
4548 +/*
4549 + * DMA mapping
4550 + *
4551 + * See linux/Documentation/DMA-mapping.txt
4552 + */
4553 +
4554 +#ifndef PCI_DMA_TODEVICE
4555 +#define PCI_DMA_TODEVICE 1
4556 +#define PCI_DMA_FROMDEVICE 2
4557 +#endif
4558 +
4559 +typedef u32 dma_addr_t;
4560 +
4561 +/* Pure 2^n version of get_order */
4562 +static inline int get_order(unsigned long size)
4563 +{
4564 + int order;
4565 +
4566 + size = (size-1) >> (PAGE_SHIFT-1);
4567 + order = -1;
4568 + do {
4569 + size >>= 1;
4570 + order++;
4571 + } while (size);
4572 + return order;
4573 +}
4574 +
4575 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
4576 + dma_addr_t *dma_handle)
4577 +{
4578 + void *ret;
4579 + int gfp = GFP_ATOMIC | GFP_DMA;
4580 +
4581 + ret = (void *)__get_free_pages(gfp, get_order(size));
4582 +
4583 + if (ret != NULL) {
4584 + memset(ret, 0, size);
4585 + *dma_handle = virt_to_bus(ret);
4586 + }
4587 + return ret;
4588 +}
4589 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
4590 + void *vaddr, dma_addr_t dma_handle)
4591 +{
4592 + free_pages((unsigned long)vaddr, get_order(size));
4593 +}
4594 +#ifdef ILSIM
4595 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
4596 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
4597 +#else
4598 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
4599 +#define pci_unmap_single(cookie, address, size, dir)
4600 +#endif
4601 +
4602 +#endif /* DMA mapping */
4603 +
4604 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 43))
4605 +
4606 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
4607 +#define netif_down(dev) do { (dev)->start = 0; } while (0)
4608 +
4609 +/* pcmcia-cs provides its own netdevice compatibility layer */
4610 +#ifndef _COMPAT_NETDEVICE_H
4611 +
4612 +/*
4613 + * SoftNet
4614 + *
4615 + * For pre-softnet kernels we need to tell the upper layer not to
4616 + * re-enter start_xmit() while we are in there. However softnet
4617 + * guarantees not to enter while we are in there so there is no need
4618 + * to do the netif_stop_queue() dance unless the transmit queue really
4619 + * gets stuck. This should also improve performance according to tests
4620 + * done by Aman Singla.
4621 + */
4622 +
4623 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
4624 +#define netif_wake_queue(dev) \
4625 + do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while (0)
4626 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
4627 +
4628 +static inline void netif_start_queue(struct net_device *dev)
4629 +{
4630 + dev->tbusy = 0;
4631 + dev->interrupt = 0;
4632 + dev->start = 1;
4633 +}
4634 +
4635 +#define netif_queue_stopped(dev) (dev)->tbusy
4636 +#define netif_running(dev) (dev)->start
4637 +
4638 +#endif /* _COMPAT_NETDEVICE_H */
4639 +
4640 +#define netif_device_attach(dev) netif_start_queue(dev)
4641 +#define netif_device_detach(dev) netif_stop_queue(dev)
4642 +
4643 +/* 2.4.x renamed bottom halves to tasklets */
4644 +#define tasklet_struct tq_struct
4645 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
4646 +{
4647 + queue_task(tasklet, &tq_immediate);
4648 + mark_bh(IMMEDIATE_BH);
4649 +}
4650 +
4651 +static inline void tasklet_init(struct tasklet_struct *tasklet,
4652 + void (*func)(unsigned long),
4653 + unsigned long data)
4654 +{
4655 + tasklet->next = NULL;
4656 + tasklet->sync = 0;
4657 + tasklet->routine = (void (*)(void *))func;
4658 + tasklet->data = (void *)data;
4659 +}
4660 +#define tasklet_kill(tasklet) { do{} while (0); }
4661 +
4662 +/* 2.4.x introduced del_timer_sync() */
4663 +#define del_timer_sync(timer) del_timer(timer)
4664 +
4665 +#else
4666 +
4667 +#define netif_down(dev)
4668 +
4669 +#endif /* SoftNet */
4670 +
4671 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3))
4672 +
4673 +/*
4674 + * Emit code to initialise a tq_struct's routine and data pointers
4675 + */
4676 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
4677 + do { \
4678 + (_tq)->routine = _routine; \
4679 + (_tq)->data = _data; \
4680 + } while (0)
4681 +
4682 +/*
4683 + * Emit code to initialise all of a tq_struct
4684 + */
4685 +#define INIT_TQUEUE(_tq, _routine, _data) \
4686 + do { \
4687 + INIT_LIST_HEAD(&(_tq)->list); \
4688 + (_tq)->sync = 0; \
4689 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
4690 + } while (0)
4691 +
4692 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3) */
4693 +
4694 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 6))
4695 +
4696 +/* Power management related routines */
4697 +
4698 +static inline int
4699 +pci_save_state(struct pci_dev *dev, u32 *buffer)
4700 +{
4701 + int i;
4702 + if (buffer) {
4703 + for (i = 0; i < 16; i++)
4704 + pci_read_config_dword(dev, i * 4, &buffer[i]);
4705 + }
4706 + return 0;
4707 +}
4708 +
4709 +static inline int
4710 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
4711 +{
4712 + int i;
4713 +
4714 + if (buffer) {
4715 + for (i = 0; i < 16; i++)
4716 + pci_write_config_dword(dev, i * 4, buffer[i]);
4717 + }
4718 + /*
4719 + * otherwise, write the context information we know from bootup.
4720 + * This works around a problem where warm-booting from Windows
4721 + * combined with a D3(hot)->D0 transition causes PCI config
4722 + * header data to be forgotten.
4723 + */
4724 + else {
4725 + for (i = 0; i < 6; i ++)
4726 + pci_write_config_dword(dev,
4727 + PCI_BASE_ADDRESS_0 + (i * 4),
4728 + pci_resource_start(dev, i));
4729 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
4730 + }
4731 + return 0;
4732 +}
4733 +
4734 +#endif /* PCI power management */
4735 +
4736 +/* Old cp0 access macros deprecated in 2.4.19 */
4737 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 19))
4738 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
4739 +#endif
4740 +
4741 +/* Module refcount handled internally in 2.6.x */
4742 +#ifndef SET_MODULE_OWNER
4743 +#define SET_MODULE_OWNER(dev) do {} while (0)
4744 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
4745 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
4746 +#else
4747 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
4748 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
4749 +#endif
4750 +
4751 +#ifndef SET_NETDEV_DEV
4752 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
4753 +#endif
4754 +
4755 +#ifndef HAVE_FREE_NETDEV
4756 +#define free_netdev(dev) kfree(dev)
4757 +#endif
4758 +
4759 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
4760 +/* struct packet_type redefined in 2.6.x */
4761 +#define af_packet_priv data
4762 +#endif
4763 +
4764 +#endif /* _linuxver_h_ */
4765 diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
4766 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
4767 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2006-10-02 21:19:59.000000000 +0200
4768 @@ -0,0 +1,541 @@
4769 +/*
4770 + * HND Run Time Environment for standalone MIPS programs.
4771 + *
4772 + * Copyright 2006, Broadcom Corporation
4773 + * All Rights Reserved.
4774 + *
4775 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4776 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4777 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4778 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4779 + *
4780 + * $Id: mipsinc.h,v 1.1.1.5 2006/02/27 03:43:16 honor Exp $
4781 + */
4782 +
4783 +#ifndef _MISPINC_H
4784 +#define _MISPINC_H
4785 +
4786 +
4787 +/* MIPS defines */
4788 +
4789 +#ifdef _LANGUAGE_ASSEMBLY
4790 +
4791 +/*
4792 + * Symbolic register names for 32 bit ABI
4793 + */
4794 +#define zero $0 /* wired zero */
4795 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
4796 +#define v0 $2 /* return value */
4797 +#define v1 $3
4798 +#define a0 $4 /* argument registers */
4799 +#define a1 $5
4800 +#define a2 $6
4801 +#define a3 $7
4802 +#define t0 $8 /* caller saved */
4803 +#define t1 $9
4804 +#define t2 $10
4805 +#define t3 $11
4806 +#define t4 $12
4807 +#define t5 $13
4808 +#define t6 $14
4809 +#define t7 $15
4810 +#define s0 $16 /* callee saved */
4811 +#define s1 $17
4812 +#define s2 $18
4813 +#define s3 $19
4814 +#define s4 $20
4815 +#define s5 $21
4816 +#define s6 $22
4817 +#define s7 $23
4818 +#define t8 $24 /* caller saved */
4819 +#define t9 $25
4820 +#define jp $25 /* PIC jump register */
4821 +#define k0 $26 /* kernel scratch */
4822 +#define k1 $27
4823 +#define gp $28 /* global pointer */
4824 +#define sp $29 /* stack pointer */
4825 +#define fp $30 /* frame pointer */
4826 +#define s8 $30 /* same like fp! */
4827 +#define ra $31 /* return address */
4828 +
4829 +
4830 +/* CP0 Registers */
4831 +
4832 +#define C0_INX $0
4833 +#define C0_RAND $1
4834 +#define C0_TLBLO0 $2
4835 +#define C0_TLBLO C0_TLBLO0
4836 +#define C0_TLBLO1 $3
4837 +#define C0_CTEXT $4
4838 +#define C0_PGMASK $5
4839 +#define C0_WIRED $6
4840 +#define C0_BADVADDR $8
4841 +#define C0_COUNT $9
4842 +#define C0_TLBHI $10
4843 +#define C0_COMPARE $11
4844 +#define C0_SR $12
4845 +#define C0_STATUS C0_SR
4846 +#define C0_CAUSE $13
4847 +#define C0_EPC $14
4848 +#define C0_PRID $15
4849 +#define C0_CONFIG $16
4850 +#define C0_LLADDR $17
4851 +#define C0_WATCHLO $18
4852 +#define C0_WATCHHI $19
4853 +#define C0_XCTEXT $20
4854 +#define C0_DIAGNOSTIC $22
4855 +#define C0_BROADCOM C0_DIAGNOSTIC
4856 +#define C0_PERFORMANCE $25
4857 +#define C0_ECC $26
4858 +#define C0_CACHEERR $27
4859 +#define C0_TAGLO $28
4860 +#define C0_TAGHI $29
4861 +#define C0_ERREPC $30
4862 +#define C0_DESAVE $31
4863 +
4864 +/*
4865 + * LEAF - declare leaf routine
4866 + */
4867 +#define LEAF(symbol) \
4868 + .globl symbol; \
4869 + .align 2; \
4870 + .type symbol, @function; \
4871 + .ent symbol, 0; \
4872 +symbol: .frame sp, 0, ra
4873 +
4874 +/*
4875 + * END - mark end of function
4876 + */
4877 +#define END(function) \
4878 + .end function; \
4879 + .size function, . - function
4880 +
4881 +#define _ULCAST_
4882 +
4883 +#define MFC0_SEL(dst, src, sel) \
4884 + .word\t(0x40000000 | ((dst) << 16) | ((src) << 11) | (sel))
4885 +
4886 +
4887 +#define MTC0_SEL(dst, src, sel) \
4888 + .word\t(0x40800000 | ((dst) << 16) | ((src) << 11) | (sel))
4889 +
4890 +#else
4891 +
4892 +/*
4893 + * The following macros are especially useful for __asm__
4894 + * inline assembler.
4895 + */
4896 +#ifndef __STR
4897 +#define __STR(x) #x
4898 +#endif
4899 +#ifndef STR
4900 +#define STR(x) __STR(x)
4901 +#endif
4902 +
4903 +#define _ULCAST_ (unsigned long)
4904 +
4905 +
4906 +/* CP0 Registers */
4907 +
4908 +#define C0_INX 0 /* CP0: TLB Index */
4909 +#define C0_RAND 1 /* CP0: TLB Random */
4910 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
4911 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
4912 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
4913 +#define C0_CTEXT 4 /* CP0: Context */
4914 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
4915 +#define C0_WIRED 6 /* CP0: TLB Wired */
4916 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
4917 +#define C0_COUNT 9 /* CP0: Count */
4918 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
4919 +#define C0_COMPARE 11 /* CP0: Compare */
4920 +#define C0_SR 12 /* CP0: Processor Status */
4921 +#define C0_STATUS C0_SR /* CP0: Processor Status */
4922 +#define C0_CAUSE 13 /* CP0: Exception Cause */
4923 +#define C0_EPC 14 /* CP0: Exception PC */
4924 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
4925 +#define C0_CONFIG 16 /* CP0: Config */
4926 +#define C0_LLADDR 17 /* CP0: LLAddr */
4927 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
4928 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
4929 +#define C0_XCTEXT 20 /* CP0: XContext */
4930 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
4931 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
4932 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
4933 +#define C0_ECC 26 /* CP0: ECC */
4934 +#define C0_CACHEERR 27 /* CP0: CacheErr */
4935 +#define C0_TAGLO 28 /* CP0: TagLo */
4936 +#define C0_TAGHI 29 /* CP0: TagHi */
4937 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
4938 +#define C0_DESAVE 31 /* CP0: DebugSave */
4939 +
4940 +#endif /* _LANGUAGE_ASSEMBLY */
4941 +
4942 +/*
4943 + * Memory segments (32bit kernel mode addresses)
4944 + */
4945 +#undef KUSEG
4946 +#undef KSEG0
4947 +#undef KSEG1
4948 +#undef KSEG2
4949 +#undef KSEG3
4950 +#define KUSEG 0x00000000
4951 +#define KSEG0 0x80000000
4952 +#define KSEG1 0xa0000000
4953 +#define KSEG2 0xc0000000
4954 +#define KSEG3 0xe0000000
4955 +#define PHYSADDR_MASK 0x1fffffff
4956 +
4957 +/*
4958 + * Map an address to a certain kernel segment
4959 + */
4960 +#undef PHYSADDR
4961 +#undef KSEG0ADDR
4962 +#undef KSEG1ADDR
4963 +#undef KSEG2ADDR
4964 +#undef KSEG3ADDR
4965 +
4966 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
4967 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
4968 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
4969 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
4970 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
4971 +
4972 +
4973 +#ifndef Index_Invalidate_I
4974 +/*
4975 + * Cache Operations
4976 + */
4977 +#define Index_Invalidate_I 0x00
4978 +#define Index_Writeback_Inv_D 0x01
4979 +#define Index_Invalidate_SI 0x02
4980 +#define Index_Writeback_Inv_SD 0x03
4981 +#define Index_Load_Tag_I 0x04
4982 +#define Index_Load_Tag_D 0x05
4983 +#define Index_Load_Tag_SI 0x06
4984 +#define Index_Load_Tag_SD 0x07
4985 +#define Index_Store_Tag_I 0x08
4986 +#define Index_Store_Tag_D 0x09
4987 +#define Index_Store_Tag_SI 0x0A
4988 +#define Index_Store_Tag_SD 0x0B
4989 +#define Create_Dirty_Excl_D 0x0d
4990 +#define Create_Dirty_Excl_SD 0x0f
4991 +#define Hit_Invalidate_I 0x10
4992 +#define Hit_Invalidate_D 0x11
4993 +#define Hit_Invalidate_SI 0x12
4994 +#define Hit_Invalidate_SD 0x13
4995 +#define Fill_I 0x14
4996 +#define Hit_Writeback_Inv_D 0x15
4997 + /* 0x16 is unused */
4998 +#define Hit_Writeback_Inv_SD 0x17
4999 +#define R5K_Page_Invalidate_S 0x17
5000 +#define Hit_Writeback_I 0x18
5001 +#define Hit_Writeback_D 0x19
5002 + /* 0x1a is unused */
5003 +#define Hit_Writeback_SD 0x1b
5004 + /* 0x1c is unused */
5005 + /* 0x1e is unused */
5006 +#define Hit_Set_Virtual_SI 0x1e
5007 +#define Hit_Set_Virtual_SD 0x1f
5008 +#endif /* !Index_Invalidate_I */
5009 +
5010 +
5011 +/*
5012 + * R4x00 interrupt enable / cause bits
5013 + */
5014 +#define IE_SW0 (_ULCAST_(1) << 8)
5015 +#define IE_SW1 (_ULCAST_(1) << 9)
5016 +#define IE_IRQ0 (_ULCAST_(1) << 10)
5017 +#define IE_IRQ1 (_ULCAST_(1) << 11)
5018 +#define IE_IRQ2 (_ULCAST_(1) << 12)
5019 +#define IE_IRQ3 (_ULCAST_(1) << 13)
5020 +#define IE_IRQ4 (_ULCAST_(1) << 14)
5021 +#define IE_IRQ5 (_ULCAST_(1) << 15)
5022 +
5023 +#ifndef ST0_UM
5024 +/*
5025 + * Bitfields in the mips32 cp0 status register
5026 + */
5027 +#define ST0_IE 0x00000001
5028 +#define ST0_EXL 0x00000002
5029 +#define ST0_ERL 0x00000004
5030 +#define ST0_UM 0x00000010
5031 +#define ST0_SWINT0 0x00000100
5032 +#define ST0_SWINT1 0x00000200
5033 +#define ST0_HWINT0 0x00000400
5034 +#define ST0_HWINT1 0x00000800
5035 +#define ST0_HWINT2 0x00001000
5036 +#define ST0_HWINT3 0x00002000
5037 +#define ST0_HWINT4 0x00004000
5038 +#define ST0_HWINT5 0x00008000
5039 +#define ST0_IM 0x0000ff00
5040 +#define ST0_NMI 0x00080000
5041 +#define ST0_SR 0x00100000
5042 +#define ST0_TS 0x00200000
5043 +#define ST0_BEV 0x00400000
5044 +#define ST0_RE 0x02000000
5045 +#define ST0_RP 0x08000000
5046 +#define ST0_CU 0xf0000000
5047 +#define ST0_CU0 0x10000000
5048 +#define ST0_CU1 0x20000000
5049 +#define ST0_CU2 0x40000000
5050 +#define ST0_CU3 0x80000000
5051 +#endif /* !ST0_UM */
5052 +
5053 +
5054 +/*
5055 + * Bitfields in the mips32 cp0 cause register
5056 + */
5057 +#define C_EXC 0x0000007c
5058 +#define C_EXC_SHIFT 2
5059 +#define C_INT 0x0000ff00
5060 +#define C_INT_SHIFT 8
5061 +#define C_SW0 (_ULCAST_(1) << 8)
5062 +#define C_SW1 (_ULCAST_(1) << 9)
5063 +#define C_IRQ0 (_ULCAST_(1) << 10)
5064 +#define C_IRQ1 (_ULCAST_(1) << 11)
5065 +#define C_IRQ2 (_ULCAST_(1) << 12)
5066 +#define C_IRQ3 (_ULCAST_(1) << 13)
5067 +#define C_IRQ4 (_ULCAST_(1) << 14)
5068 +#define C_IRQ5 (_ULCAST_(1) << 15)
5069 +#define C_WP 0x00400000
5070 +#define C_IV 0x00800000
5071 +#define C_CE 0x30000000
5072 +#define C_CE_SHIFT 28
5073 +#define C_BD 0x80000000
5074 +
5075 +/* Values in C_EXC */
5076 +#define EXC_INT 0
5077 +#define EXC_TLBM 1
5078 +#define EXC_TLBL 2
5079 +#define EXC_TLBS 3
5080 +#define EXC_AEL 4
5081 +#define EXC_AES 5
5082 +#define EXC_IBE 6
5083 +#define EXC_DBE 7
5084 +#define EXC_SYS 8
5085 +#define EXC_BPT 9
5086 +#define EXC_RI 10
5087 +#define EXC_CU 11
5088 +#define EXC_OV 12
5089 +#define EXC_TR 13
5090 +#define EXC_WATCH 23
5091 +#define EXC_MCHK 24
5092 +
5093 +
5094 +/*
5095 + * Bits in the cp0 config register.
5096 + */
5097 +#define CONF_CM_CACHABLE_NO_WA 0
5098 +#define CONF_CM_CACHABLE_WA 1
5099 +#define CONF_CM_UNCACHED 2
5100 +#define CONF_CM_CACHABLE_NONCOHERENT 3
5101 +#define CONF_CM_CACHABLE_CE 4
5102 +#define CONF_CM_CACHABLE_COW 5
5103 +#define CONF_CM_CACHABLE_CUW 6
5104 +#define CONF_CM_CACHABLE_ACCELERATED 7
5105 +#define CONF_CM_CMASK 7
5106 +#define CONF_CU (_ULCAST_(1) << 3)
5107 +#define CONF_DB (_ULCAST_(1) << 4)
5108 +#define CONF_IB (_ULCAST_(1) << 5)
5109 +#define CONF_SE (_ULCAST_(1) << 12)
5110 +#ifndef CONF_BE /* duplicate in mipsregs.h */
5111 +#define CONF_BE (_ULCAST_(1) << 15)
5112 +#endif
5113 +#define CONF_SC (_ULCAST_(1) << 17)
5114 +#define CONF_AC (_ULCAST_(1) << 23)
5115 +#define CONF_HALT (_ULCAST_(1) << 25)
5116 +#ifndef CONF_M /* duplicate in mipsregs.h */
5117 +#define CONF_M (_ULCAST_(1) << 31)
5118 +#endif
5119 +
5120 +
5121 +/*
5122 + * Bits in the cp0 config register select 1.
5123 + */
5124 +#define CONF1_FP 0x00000001 /* FPU present */
5125 +#define CONF1_EP 0x00000002 /* EJTAG present */
5126 +#define CONF1_CA 0x00000004 /* mips16 implemented */
5127 +#define CONF1_WR 0x00000008 /* Watch registers present */
5128 +#define CONF1_PC 0x00000010 /* Performance counters present */
5129 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
5130 +#define CONF1_DA_MASK 0x00000380
5131 +#define CONF1_DA_BASE 1
5132 +#define CONF1_DL_SHIFT 10 /* D$ line size */
5133 +#define CONF1_DL_MASK 0x00001c00
5134 +#define CONF1_DL_BASE 2
5135 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
5136 +#define CONF1_DS_MASK 0x0000e000
5137 +#define CONF1_DS_BASE 64
5138 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
5139 +#define CONF1_IA_MASK 0x00070000
5140 +#define CONF1_IA_BASE 1
5141 +#define CONF1_IL_SHIFT 19 /* I$ line size */
5142 +#define CONF1_IL_MASK 0x00380000
5143 +#define CONF1_IL_BASE 2
5144 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
5145 +#define CONF1_IS_MASK 0x01c00000
5146 +#define CONF1_IS_BASE 64
5147 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
5148 +#define CONF1_MS_SHIFT 25
5149 +
5150 +/* PRID register */
5151 +#define PRID_COPT_MASK 0xff000000
5152 +#define PRID_COMP_MASK 0x00ff0000
5153 +#define PRID_IMP_MASK 0x0000ff00
5154 +#define PRID_REV_MASK 0x000000ff
5155 +
5156 +#define PRID_COMP_LEGACY 0x000000
5157 +#define PRID_COMP_MIPS 0x010000
5158 +#define PRID_COMP_BROADCOM 0x020000
5159 +#define PRID_COMP_ALCHEMY 0x030000
5160 +#define PRID_COMP_SIBYTE 0x040000
5161 +#define PRID_IMP_BCM4710 0x4000
5162 +#define PRID_IMP_BCM3302 0x9000
5163 +#define PRID_IMP_BCM3303 0x9100
5164 +
5165 +#define PRID_IMP_UNKNOWN 0xff00
5166 +
5167 +#define BCM330X(id) \
5168 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
5169 + (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) || \
5170 + ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
5171 + (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
5172 +
5173 +/* Bits in C0_BROADCOM */
5174 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
5175 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
5176 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
5177 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
5178 +#define BRCM_CLF_ENABLE 0x00100000 /* Enable cache line first feature */
5179 +
5180 +/* PreFetch Cache aka Read Ahead Cache */
5181 +
5182 +#define PFC_CR0 0xff400000 /* control reg 0 */
5183 +#define PFC_CR1 0xff400004 /* control reg 1 */
5184 +
5185 +/* PFC operations */
5186 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
5187 +#define PFC_D 0x00000002 /* Enable PFC use for data */
5188 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
5189 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
5190 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
5191 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
5192 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
5193 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
5194 +#define PFC_BRR 0x40000000 /* Bus error indication */
5195 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
5196 +
5197 +/* Handy defaults */
5198 +#define PFC_DISABLED 0
5199 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
5200 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
5201 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
5202 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
5203 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
5204 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
5205 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
5206 +
5207 +#ifndef _LANGUAGE_ASSEMBLY
5208 +
5209 +/*
5210 + * Macros to access the system control coprocessor
5211 + */
5212 +
5213 +#define MFC0(source, sel) \
5214 +({ \
5215 + int __res; \
5216 + __asm__ __volatile__(" \
5217 + .set\tnoreorder; \
5218 + .set\tnoat; \
5219 + .word\t"STR(0x40010000 | ((source) << 11) | (sel))"; \
5220 + move\t%0, $1; \
5221 + .set\tat; \
5222 + .set\treorder" \
5223 + :"=r" (__res) \
5224 + : \
5225 + :"$1"); \
5226 + __res; \
5227 +})
5228 +
5229 +#define MTC0(source, sel, value) \
5230 +do { \
5231 + __asm__ __volatile__(" \
5232 + .set\tnoreorder; \
5233 + .set\tnoat; \
5234 + move\t$1, %z0; \
5235 + .word\t"STR(0x40810000 | ((source) << 11) | (sel))"; \
5236 + .set\tat; \
5237 + .set\treorder" \
5238 + : \
5239 + :"jr" (value) \
5240 + :"$1"); \
5241 +} while (0)
5242 +
5243 +#define get_c0_count() \
5244 +({ \
5245 + int __res; \
5246 + __asm__ __volatile__(" \
5247 + .set\tnoreorder; \
5248 + .set\tnoat; \
5249 + mfc0\t%0, $9; \
5250 + .set\tat; \
5251 + .set\treorder" \
5252 + :"=r" (__res)); \
5253 + __res; \
5254 +})
5255 +
5256 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
5257 +{
5258 + uint lsz, sets, ways;
5259 +
5260 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
5261 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
5262 + lsz = CONF1_IL_BASE << lsz;
5263 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
5264 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
5265 + *size = lsz * sets * ways;
5266 + *lsize = lsz;
5267 +}
5268 +
5269 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
5270 +{
5271 + uint lsz, sets, ways;
5272 +
5273 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
5274 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
5275 + lsz = CONF1_DL_BASE << lsz;
5276 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
5277 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
5278 + *size = lsz * sets * ways;
5279 + *lsize = lsz;
5280 +}
5281 +
5282 +#define cache_op(base, op) \
5283 + __asm__ __volatile__(" \
5284 + .set noreorder; \
5285 + .set mips3; \
5286 + cache %1, (%0); \
5287 + .set mips0; \
5288 + .set reorder" \
5289 + : \
5290 + : "r" (base), \
5291 + "i" (op));
5292 +
5293 +#define cache_unroll4(base, delta, op) \
5294 + __asm__ __volatile__(" \
5295 + .set noreorder; \
5296 + .set mips3; \
5297 + cache %1, 0(%0); \
5298 + cache %1, delta(%0); \
5299 + cache %1, (2 * delta)(%0); \
5300 + cache %1, (3 * delta)(%0); \
5301 + .set mips0; \
5302 + .set reorder" \
5303 + : \
5304 + : "r" (base), \
5305 + "i" (op));
5306 +
5307 +#endif /* !_LANGUAGE_ASSEMBLY */
5308 +
5309 +#endif /* _MISPINC_H */
5310 diff -urN linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
5311 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
5312 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2006-10-02 21:19:59.000000000 +0200
5313 @@ -0,0 +1,179 @@
5314 +#ifndef __osl_h
5315 +#define __osl_h
5316 +
5317 +#include <linux/delay.h>
5318 +#include <typedefs.h>
5319 +#include <linuxver.h>
5320 +#include <bcmutils.h>
5321 +#include <pcicfg.h>
5322 +
5323 +#define ASSERT(n)
5324 +
5325 +/* Pkttag flag should be part of public information */
5326 +struct osl_pubinfo {
5327 + bool pkttag;
5328 + uint pktalloced; /* Number of allocated packet buffers */
5329 +};
5330 +
5331 +struct osl_info {
5332 + struct osl_pubinfo pub;
5333 + uint magic;
5334 + void *pdev;
5335 + uint malloced;
5336 + uint failed;
5337 + void *dbgmem_list;
5338 +};
5339 +
5340 +typedef struct osl_info osl_t;
5341 +
5342 +#define PCI_CFG_RETRY 10
5343 +
5344 +/* map/unmap direction */
5345 +#define DMA_TX 1 /* TX direction for DMA */
5346 +#define DMA_RX 2 /* RX direction for DMA */
5347 +
5348 +#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v))
5349 +#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v))
5350 +#define SET_REG(osh, r, mask, val) W_REG((osh), (r), ((R_REG((osh), r) & ~(mask)) | (val)))
5351 +
5352 +/* bcopy, bcmp, and bzero */
5353 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
5354 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
5355 +#define bzero(b, len) memset((b), '\0', (len))
5356 +
5357 +/* uncached virtual address */
5358 +#ifdef mips
5359 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
5360 +#include <asm/addrspace.h>
5361 +#else
5362 +#define OSL_UNCACHED(va) (va)
5363 +#endif /* mips */
5364 +
5365 +
5366 +#ifndef IL_BIGENDIAN
5367 +#define R_REG(osh, r) (\
5368 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
5369 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
5370 + readl((volatile uint32*)(r)) \
5371 +)
5372 +#define W_REG(osh, r, v) do { \
5373 + switch (sizeof(*(r))) { \
5374 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
5375 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
5376 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
5377 + } \
5378 +} while (0)
5379 +#else /* IL_BIGENDIAN */
5380 +#define R_REG(osh, r) ({ \
5381 + __typeof(*(r)) __osl_v; \
5382 + switch (sizeof(*(r))) { \
5383 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
5384 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
5385 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
5386 + } \
5387 + __osl_v; \
5388 +})
5389 +#define W_REG(osh, r, v) do { \
5390 + switch (sizeof(*(r))) { \
5391 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
5392 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
5393 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
5394 + } \
5395 +} while (0)
5396 +#endif /* IL_BIGENDIAN */
5397 +
5398 +/* dereference an address that may cause a bus exception */
5399 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
5400 +#include <asm/paccess.h>
5401 +
5402 +/* map/unmap physical to virtual I/O */
5403 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
5404 +#define REG_UNMAP(va) iounmap((void *)(va))
5405 +
5406 +/* shared (dma-able) memory access macros */
5407 +#define R_SM(r) *(r)
5408 +#define W_SM(r, v) (*(r) = (v))
5409 +#define BZERO_SM(r, len) memset((r), '\0', (len))
5410 +
5411 +#define MALLOC(osh, size) kmalloc((size), GFP_ATOMIC)
5412 +#define MFREE(osh, addr, size) kfree((addr))
5413 +#define MALLOCED(osh) (0)
5414 +
5415 +#define osl_delay OSL_DELAY
5416 +static inline void OSL_DELAY(uint usec)
5417 +{
5418 + uint d;
5419 +
5420 + while (usec > 0) {
5421 + d = MIN(usec, 1000);
5422 + udelay(d);
5423 + usec -= d;
5424 + }
5425 +}
5426 +
5427 +static inline void
5428 +bcm_mdelay(uint ms)
5429 +{
5430 + uint i;
5431 +
5432 + for (i = 0; i < ms; i++) {
5433 + OSL_DELAY(1000);
5434 + }
5435 +}
5436 +
5437 +
5438 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size)
5439 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size)
5440 +
5441 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
5442 + osl_pci_read_config((osh), (offset), (size))
5443 +
5444 +static inline uint32
5445 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
5446 +{
5447 + uint val;
5448 + uint retry = PCI_CFG_RETRY;
5449 +
5450 + do {
5451 + pci_read_config_dword(osh->pdev, offset, &val);
5452 + if (val != 0xffffffff)
5453 + break;
5454 + } while (retry--);
5455 +
5456 + return (val);
5457 +}
5458 +
5459 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
5460 + osl_pci_write_config((osh), (offset), (size), (val))
5461 +static inline void
5462 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
5463 +{
5464 + uint retry = PCI_CFG_RETRY;
5465 +
5466 + do {
5467 + pci_write_config_dword(osh->pdev, offset, val);
5468 + if (offset != PCI_BAR0_WIN)
5469 + break;
5470 + if (osl_pci_read_config(osh, offset, size) == val)
5471 + break;
5472 + } while (retry--);
5473 +}
5474 +
5475 +
5476 +/* return bus # for the pci device pointed by osh->pdev */
5477 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
5478 +static inline uint
5479 +osl_pci_bus(osl_t *osh)
5480 +{
5481 + return ((struct pci_dev *)osh->pdev)->bus->number;
5482 +}
5483 +
5484 +/* return slot # for the pci device pointed by osh->pdev */
5485 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
5486 +static inline uint
5487 +osl_pci_slot(osl_t *osh)
5488 +{
5489 + return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
5490 +}
5491 +
5492 +#endif
5493 diff -urN linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
5494 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
5495 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2006-10-02 21:19:59.000000000 +0200
5496 @@ -0,0 +1,495 @@
5497 +/*
5498 + * pcicfg.h: PCI configuration constants and structures.
5499 + *
5500 + * Copyright 2006, Broadcom Corporation
5501 + * All Rights Reserved.
5502 + *
5503 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5504 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5505 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5506 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5507 + *
5508 + * $Id: pcicfg.h,v 1.1.1.11 2006/04/08 06:13:40 honor Exp $
5509 + */
5510 +
5511 +#ifndef _h_pcicfg_
5512 +#define _h_pcicfg_
5513 +
5514 +/* The following inside ifndef's so we don't collide with NTDDK.H */
5515 +#ifndef PCI_MAX_BUS
5516 +#define PCI_MAX_BUS 0x100
5517 +#endif
5518 +#ifndef PCI_MAX_DEVICES
5519 +#define PCI_MAX_DEVICES 0x20
5520 +#endif
5521 +#ifndef PCI_MAX_FUNCTION
5522 +#define PCI_MAX_FUNCTION 0x8
5523 +#endif
5524 +
5525 +#ifndef PCI_INVALID_VENDORID
5526 +#define PCI_INVALID_VENDORID 0xffff
5527 +#endif
5528 +#ifndef PCI_INVALID_DEVICEID
5529 +#define PCI_INVALID_DEVICEID 0xffff
5530 +#endif
5531 +
5532 +
5533 +/* Convert between bus-slot-function-register and config addresses */
5534 +
5535 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
5536 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
5537 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
5538 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
5539 +
5540 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
5541 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
5542 +#define PCICFG_FUN_MASK 7 /* Function mask */
5543 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
5544 +
5545 +#define PCI_CONFIG_ADDR(b, s, f, o) \
5546 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
5547 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
5548 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
5549 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
5550 +
5551 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
5552 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
5553 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
5554 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
5555 +
5556 +/* PCIE Config space accessing MACROS */
5557 +
5558 +#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
5559 +#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
5560 +#define PCIECFG_FUN_SHIFT 16 /* Function shift */
5561 +#define PCIECFG_OFF_SHIFT 0 /* Register shift */
5562 +
5563 +#define PCIECFG_BUS_MASK 0xff /* Bus mask */
5564 +#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
5565 +#define PCIECFG_FUN_MASK 7 /* Function mask */
5566 +#define PCIECFG_OFF_MASK 0x3ff /* Register mask */
5567 +
5568 +#define PCIE_CONFIG_ADDR(b, s, f, o) \
5569 + ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
5570 + | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
5571 + | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
5572 + | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
5573 +
5574 +#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
5575 +#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
5576 +#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
5577 +#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
5578 +
5579 +/* The actual config space */
5580 +
5581 +#define PCI_BAR_MAX 6
5582 +
5583 +#define PCI_ROM_BAR 8
5584 +
5585 +#define PCR_RSVDA_MAX 2
5586 +
5587 +/* Bits in PCI bars' flags */
5588 +
5589 +#define PCIBAR_FLAGS 0xf
5590 +#define PCIBAR_IO 0x1
5591 +#define PCIBAR_MEM1M 0x2
5592 +#define PCIBAR_MEM64 0x4
5593 +#define PCIBAR_PREFETCH 0x8
5594 +#define PCIBAR_MEM32_MASK 0xFFFFFF80
5595 +
5596 +/* pci config status reg has a bit to indicate that capability ptr is present */
5597 +
5598 +#define PCI_CAPPTR_PRESENT 0x0010
5599 +
5600 +typedef struct _pci_config_regs {
5601 + unsigned short vendor;
5602 + unsigned short device;
5603 + unsigned short command;
5604 + unsigned short status;
5605 + unsigned char rev_id;
5606 + unsigned char prog_if;
5607 + unsigned char sub_class;
5608 + unsigned char base_class;
5609 + unsigned char cache_line_size;
5610 + unsigned char latency_timer;
5611 + unsigned char header_type;
5612 + unsigned char bist;
5613 + unsigned long base[PCI_BAR_MAX];
5614 + unsigned long cardbus_cis;
5615 + unsigned short subsys_vendor;
5616 + unsigned short subsys_id;
5617 + unsigned long baserom;
5618 + unsigned long rsvd_a[PCR_RSVDA_MAX];
5619 + unsigned char int_line;
5620 + unsigned char int_pin;
5621 + unsigned char min_gnt;
5622 + unsigned char max_lat;
5623 + unsigned char dev_dep[192];
5624 +} pci_config_regs;
5625 +
5626 +#define SZPCR (sizeof (pci_config_regs))
5627 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
5628 +
5629 +/* A structure for the config registers is nice, but in most
5630 + * systems the config space is not memory mapped, so we need
5631 + * filed offsetts. :-(
5632 + */
5633 +#define PCI_CFG_VID 0
5634 +#define PCI_CFG_DID 2
5635 +#define PCI_CFG_CMD 4
5636 +#define PCI_CFG_STAT 6
5637 +#define PCI_CFG_REV 8
5638 +#define PCI_CFG_PROGIF 9
5639 +#define PCI_CFG_SUBCL 0xa
5640 +#define PCI_CFG_BASECL 0xb
5641 +#define PCI_CFG_CLSZ 0xc
5642 +#define PCI_CFG_LATTIM 0xd
5643 +#define PCI_CFG_HDR 0xe
5644 +#define PCI_CFG_BIST 0xf
5645 +#define PCI_CFG_BAR0 0x10
5646 +#define PCI_CFG_BAR1 0x14
5647 +#define PCI_CFG_BAR2 0x18
5648 +#define PCI_CFG_BAR3 0x1c
5649 +#define PCI_CFG_BAR4 0x20
5650 +#define PCI_CFG_BAR5 0x24
5651 +#define PCI_CFG_CIS 0x28
5652 +#define PCI_CFG_SVID 0x2c
5653 +#define PCI_CFG_SSID 0x2e
5654 +#define PCI_CFG_ROMBAR 0x30
5655 +#define PCI_CFG_CAPPTR 0x34
5656 +#define PCI_CFG_INT 0x3c
5657 +#define PCI_CFG_PIN 0x3d
5658 +#define PCI_CFG_MINGNT 0x3e
5659 +#define PCI_CFG_MAXLAT 0x3f
5660 +
5661 +#ifdef __NetBSD__
5662 +#undef PCI_CLASS_DISPLAY
5663 +#undef PCI_CLASS_MEMORY
5664 +#undef PCI_CLASS_BRIDGE
5665 +#undef PCI_CLASS_INPUT
5666 +#undef PCI_CLASS_DOCK
5667 +#endif /* __NetBSD__ */
5668 +
5669 +/* Classes and subclasses */
5670 +
5671 +typedef enum {
5672 + PCI_CLASS_OLD = 0,
5673 + PCI_CLASS_DASDI,
5674 + PCI_CLASS_NET,
5675 + PCI_CLASS_DISPLAY,
5676 + PCI_CLASS_MMEDIA,
5677 + PCI_CLASS_MEMORY,
5678 + PCI_CLASS_BRIDGE,
5679 + PCI_CLASS_COMM,
5680 + PCI_CLASS_BASE,
5681 + PCI_CLASS_INPUT,
5682 + PCI_CLASS_DOCK,
5683 + PCI_CLASS_CPU,
5684 + PCI_CLASS_SERIAL,
5685 + PCI_CLASS_INTELLIGENT = 0xe,
5686 + PCI_CLASS_SATELLITE,
5687 + PCI_CLASS_CRYPT,
5688 + PCI_CLASS_DSP,
5689 + PCI_CLASS_XOR = 0xfe
5690 +} pci_classes;
5691 +
5692 +typedef enum {
5693 + PCI_DASDI_SCSI,
5694 + PCI_DASDI_IDE,
5695 + PCI_DASDI_FLOPPY,
5696 + PCI_DASDI_IPI,
5697 + PCI_DASDI_RAID,
5698 + PCI_DASDI_OTHER = 0x80
5699 +} pci_dasdi_subclasses;
5700 +
5701 +typedef enum {
5702 + PCI_NET_ETHER,
5703 + PCI_NET_TOKEN,
5704 + PCI_NET_FDDI,
5705 + PCI_NET_ATM,
5706 + PCI_NET_OTHER = 0x80
5707 +} pci_net_subclasses;
5708 +
5709 +typedef enum {
5710 + PCI_DISPLAY_VGA,
5711 + PCI_DISPLAY_XGA,
5712 + PCI_DISPLAY_3D,
5713 + PCI_DISPLAY_OTHER = 0x80
5714 +} pci_display_subclasses;
5715 +
5716 +typedef enum {
5717 + PCI_MMEDIA_VIDEO,
5718 + PCI_MMEDIA_AUDIO,
5719 + PCI_MMEDIA_PHONE,
5720 + PCI_MEDIA_OTHER = 0x80
5721 +} pci_mmedia_subclasses;
5722 +
5723 +typedef enum {
5724 + PCI_MEMORY_RAM,
5725 + PCI_MEMORY_FLASH,
5726 + PCI_MEMORY_OTHER = 0x80
5727 +} pci_memory_subclasses;
5728 +
5729 +typedef enum {
5730 + PCI_BRIDGE_HOST,
5731 + PCI_BRIDGE_ISA,
5732 + PCI_BRIDGE_EISA,
5733 + PCI_BRIDGE_MC,
5734 + PCI_BRIDGE_PCI,
5735 + PCI_BRIDGE_PCMCIA,
5736 + PCI_BRIDGE_NUBUS,
5737 + PCI_BRIDGE_CARDBUS,
5738 + PCI_BRIDGE_RACEWAY,
5739 + PCI_BRIDGE_OTHER = 0x80
5740 +} pci_bridge_subclasses;
5741 +
5742 +typedef enum {
5743 + PCI_COMM_UART,
5744 + PCI_COMM_PARALLEL,
5745 + PCI_COMM_MULTIUART,
5746 + PCI_COMM_MODEM,
5747 + PCI_COMM_OTHER = 0x80
5748 +} pci_comm_subclasses;
5749 +
5750 +typedef enum {
5751 + PCI_BASE_PIC,
5752 + PCI_BASE_DMA,
5753 + PCI_BASE_TIMER,
5754 + PCI_BASE_RTC,
5755 + PCI_BASE_PCI_HOTPLUG,
5756 + PCI_BASE_OTHER = 0x80
5757 +} pci_base_subclasses;
5758 +
5759 +typedef enum {
5760 + PCI_INPUT_KBD,
5761 + PCI_INPUT_PEN,
5762 + PCI_INPUT_MOUSE,
5763 + PCI_INPUT_SCANNER,
5764 + PCI_INPUT_GAMEPORT,
5765 + PCI_INPUT_OTHER = 0x80
5766 +} pci_input_subclasses;
5767 +
5768 +typedef enum {
5769 + PCI_DOCK_GENERIC,
5770 + PCI_DOCK_OTHER = 0x80
5771 +} pci_dock_subclasses;
5772 +
5773 +typedef enum {
5774 + PCI_CPU_386,
5775 + PCI_CPU_486,
5776 + PCI_CPU_PENTIUM,
5777 + PCI_CPU_ALPHA = 0x10,
5778 + PCI_CPU_POWERPC = 0x20,
5779 + PCI_CPU_MIPS = 0x30,
5780 + PCI_CPU_COPROC = 0x40,
5781 + PCI_CPU_OTHER = 0x80
5782 +} pci_cpu_subclasses;
5783 +
5784 +typedef enum {
5785 + PCI_SERIAL_IEEE1394,
5786 + PCI_SERIAL_ACCESS,
5787 + PCI_SERIAL_SSA,
5788 + PCI_SERIAL_USB,
5789 + PCI_SERIAL_FIBER,
5790 + PCI_SERIAL_SMBUS,
5791 + PCI_SERIAL_OTHER = 0x80
5792 +} pci_serial_subclasses;
5793 +
5794 +typedef enum {
5795 + PCI_INTELLIGENT_I2O
5796 +} pci_intelligent_subclasses;
5797 +
5798 +typedef enum {
5799 + PCI_SATELLITE_TV,
5800 + PCI_SATELLITE_AUDIO,
5801 + PCI_SATELLITE_VOICE,
5802 + PCI_SATELLITE_DATA,
5803 + PCI_SATELLITE_OTHER = 0x80
5804 +} pci_satellite_subclasses;
5805 +
5806 +typedef enum {
5807 + PCI_CRYPT_NETWORK,
5808 + PCI_CRYPT_ENTERTAINMENT,
5809 + PCI_CRYPT_OTHER = 0x80
5810 +} pci_crypt_subclasses;
5811 +
5812 +typedef enum {
5813 + PCI_DSP_DPIO,
5814 + PCI_DSP_OTHER = 0x80
5815 +} pci_dsp_subclasses;
5816 +
5817 +typedef enum {
5818 + PCI_XOR_QDMA,
5819 + PCI_XOR_OTHER = 0x80
5820 +} pci_xor_subclasses;
5821 +
5822 +/* Header types */
5823 +typedef enum {
5824 + PCI_HEADER_NORMAL,
5825 + PCI_HEADER_BRIDGE,
5826 + PCI_HEADER_CARDBUS
5827 +} pci_header_types;
5828 +
5829 +
5830 +/* Overlay for a PCI-to-PCI bridge */
5831 +
5832 +#define PPB_RSVDA_MAX 2
5833 +#define PPB_RSVDD_MAX 8
5834 +
5835 +typedef struct _ppb_config_regs {
5836 + unsigned short vendor;
5837 + unsigned short device;
5838 + unsigned short command;
5839 + unsigned short status;
5840 + unsigned char rev_id;
5841 + unsigned char prog_if;
5842 + unsigned char sub_class;
5843 + unsigned char base_class;
5844 + unsigned char cache_line_size;
5845 + unsigned char latency_timer;
5846 + unsigned char header_type;
5847 + unsigned char bist;
5848 + unsigned long rsvd_a[PPB_RSVDA_MAX];
5849 + unsigned char prim_bus;
5850 + unsigned char sec_bus;
5851 + unsigned char sub_bus;
5852 + unsigned char sec_lat;
5853 + unsigned char io_base;
5854 + unsigned char io_lim;
5855 + unsigned short sec_status;
5856 + unsigned short mem_base;
5857 + unsigned short mem_lim;
5858 + unsigned short pf_mem_base;
5859 + unsigned short pf_mem_lim;
5860 + unsigned long pf_mem_base_hi;
5861 + unsigned long pf_mem_lim_hi;
5862 + unsigned short io_base_hi;
5863 + unsigned short io_lim_hi;
5864 + unsigned short subsys_vendor;
5865 + unsigned short subsys_id;
5866 + unsigned long rsvd_b;
5867 + unsigned char rsvd_c;
5868 + unsigned char int_pin;
5869 + unsigned short bridge_ctrl;
5870 + unsigned char chip_ctrl;
5871 + unsigned char diag_ctrl;
5872 + unsigned short arb_ctrl;
5873 + unsigned long rsvd_d[PPB_RSVDD_MAX];
5874 + unsigned char dev_dep[192];
5875 +} ppb_config_regs;
5876 +
5877 +
5878 +/* PCI CAPABILITY DEFINES */
5879 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
5880 +#define PCI_CAP_MSICAP_ID 0x05
5881 +#define PCI_CAP_PCIECAP_ID 0x10
5882 +
5883 +/* Data structure to define the Message Signalled Interrupt facility
5884 + * Valid for PCI and PCIE configurations
5885 + */
5886 +typedef struct _pciconfig_cap_msi {
5887 + unsigned char capID;
5888 + unsigned char nextptr;
5889 + unsigned short msgctrl;
5890 + unsigned int msgaddr;
5891 +} pciconfig_cap_msi;
5892 +
5893 +/* Data structure to define the Power managment facility
5894 + * Valid for PCI and PCIE configurations
5895 + */
5896 +typedef struct _pciconfig_cap_pwrmgmt {
5897 + unsigned char capID;
5898 + unsigned char nextptr;
5899 + unsigned short pme_cap;
5900 + unsigned short pme_sts_ctrl;
5901 + unsigned char pme_bridge_ext;
5902 + unsigned char data;
5903 +} pciconfig_cap_pwrmgmt;
5904 +
5905 +/* Data structure to define the PCIE capability */
5906 +typedef struct _pciconfig_cap_pcie {
5907 + unsigned char capID;
5908 + unsigned char nextptr;
5909 + unsigned short pcie_cap;
5910 + unsigned int dev_cap;
5911 + unsigned short dev_ctrl;
5912 + unsigned short dev_status;
5913 + unsigned int link_cap;
5914 + unsigned short link_ctrl;
5915 + unsigned short link_status;
5916 +} pciconfig_cap_pcie;
5917 +
5918 +/* PCIE Enhanced CAPABILITY DEFINES */
5919 +#define PCIE_EXTCFG_OFFSET 0x100
5920 +#define PCIE_ADVERRREP_CAPID 0x0001
5921 +#define PCIE_VC_CAPID 0x0002
5922 +#define PCIE_DEVSNUM_CAPID 0x0003
5923 +#define PCIE_PWRBUDGET_CAPID 0x0004
5924 +
5925 +/* Header to define the PCIE specific capabilities in the extended config space */
5926 +typedef struct _pcie_enhanced_caphdr {
5927 + unsigned short capID;
5928 + unsigned short cap_ver : 4;
5929 + unsigned short next_ptr : 12;
5930 +} pcie_enhanced_caphdr;
5931 +
5932 +
5933 +/* Everything below is BRCM HND proprietary */
5934 +
5935 +
5936 +/* Brcm PCI configuration registers */
5937 +#define cap_list rsvd_a[0]
5938 +#define bar0_window dev_dep[0x80 - 0x40]
5939 +#define bar1_window dev_dep[0x84 - 0x40]
5940 +#define sprom_control dev_dep[0x88 - 0x40]
5941 +
5942 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
5943 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
5944 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
5945 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
5946 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
5947 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
5948 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
5949 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
5950 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address */
5951 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
5952 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
5953 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
5954 +
5955 +#define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */
5956 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
5957 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
5958 +#define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the
5959 + * 8KB window, so their address is the "regular"
5960 + * address plus 4K
5961 + */
5962 +#define PCI_BAR0_WINSZ 8192 /* bar0 window size */
5963 +
5964 +/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
5965 +#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */
5966 +#define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */
5967 +#define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */
5968 +
5969 +/* PCI_INT_STATUS */
5970 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
5971 +
5972 +/* PCI_INT_MASK */
5973 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
5974 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
5975 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
5976 +
5977 +/* PCI_SPROM_CONTROL */
5978 +#define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */
5979 +#define SPROM_LOCKED 0x08 /* SPROM Locked */
5980 +#define SPROM_BLANK 0x04 /* indicating a blank SPROM */
5981 +#define SPROM_WRITEEN 0x10 /* SPROM write enable */
5982 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
5983 +#define SPROM_OTPIN_USE 0x80 /* device OTP In use */
5984 +
5985 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
5986 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
5987 +
5988 +/* PCI_CFG_CMD_STAT */
5989 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
5990 +
5991 +#endif /* _h_pcicfg_ */
5992 diff -urN linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
5993 --- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
5994 +++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2006-10-02 21:19:59.000000000 +0200
5995 @@ -0,0 +1,516 @@
5996 +/*
5997 + * SiliconBackplane Chipcommon core hardware definitions.
5998 + *
5999 + * The chipcommon core provides chip identification, SB control,
6000 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
6001 + * gpio interface, extbus, and support for serial and parallel flashes.
6002 + *
6003 + * $Id: sbchipc.h,v 1.1.1.14 2006/04/15 01:29:08 michael Exp $
6004 + * Copyright 2006, Broadcom Corporation
6005 + * All Rights Reserved.
6006 + *
6007 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6008 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6009 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6010 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6011 + *
6012 + */
6013 +
6014 +#ifndef _SBCHIPC_H
6015 +#define _SBCHIPC_H
6016 +
6017 +
6018 +#ifndef _LANGUAGE_ASSEMBLY
6019 +
6020 +/* cpp contortions to concatenate w/arg prescan */
6021 +#ifndef PAD
6022 +#define _PADLINE(line) pad ## line
6023 +#define _XSTR(line) _PADLINE(line)
6024 +#define PAD _XSTR(__LINE__)
6025 +#endif /* PAD */
6026 +
6027 +typedef volatile struct {
6028 + uint32 chipid; /* 0x0 */
6029 + uint32 capabilities;
6030 + uint32 corecontrol; /* corerev >= 1 */
6031 + uint32 bist;
6032 +
6033 + /* OTP */
6034 + uint32 otpstatus; /* 0x10, corerev >= 10 */
6035 + uint32 otpcontrol;
6036 + uint32 otpprog;
6037 + uint32 PAD;
6038 +
6039 + /* Interrupt control */
6040 + uint32 intstatus; /* 0x20 */
6041 + uint32 intmask;
6042 + uint32 chipcontrol; /* 0x28, rev >= 11 */
6043 + uint32 chipstatus; /* 0x2c, rev >= 11 */
6044 +
6045 + /* Jtag Master */
6046 + uint32 jtagcmd; /* 0x30, rev >= 10 */
6047 + uint32 jtagir;
6048 + uint32 jtagdr;
6049 + uint32 jtagctrl;
6050 +
6051 + /* serial flash interface registers */
6052 + uint32 flashcontrol; /* 0x40 */
6053 + uint32 flashaddress;
6054 + uint32 flashdata;
6055 + uint32 PAD[1];
6056 +
6057 + /* Silicon backplane configuration broadcast control */
6058 + uint32 broadcastaddress; /* 0x50 */
6059 + uint32 broadcastdata;
6060 + uint32 PAD[2];
6061 +
6062 + /* gpio - cleared only by power-on-reset */
6063 + uint32 gpioin; /* 0x60 */
6064 + uint32 gpioout;
6065 + uint32 gpioouten;
6066 + uint32 gpiocontrol;
6067 + uint32 gpiointpolarity;
6068 + uint32 gpiointmask;
6069 + uint32 PAD[2];
6070 +
6071 + /* Watchdog timer */
6072 + uint32 watchdog; /* 0x80 */
6073 + uint32 PAD[1];
6074 +
6075 + /* GPIO based LED powersave registers corerev >= 16 */
6076 + uint32 gpiotimerval; /* 0x88 */
6077 + uint32 gpiotimeroutmask;
6078 +
6079 + /* clock control */
6080 + uint32 clockcontrol_n; /* 0x90 */
6081 + uint32 clockcontrol_sb; /* aka m0 */
6082 + uint32 clockcontrol_pci; /* aka m1 */
6083 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
6084 + uint32 clockcontrol_m3; /* cpu */
6085 + uint32 clkdiv; /* corerev >= 3 */
6086 + uint32 PAD[2];
6087 +
6088 + /* pll delay registers (corerev >= 4) */
6089 + uint32 pll_on_delay; /* 0xb0 */
6090 + uint32 fref_sel_delay;
6091 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
6092 + uint32 PAD[1];
6093 +
6094 + /* Instaclock registers (corerev >= 10) */
6095 + uint32 system_clk_ctl; /* 0xc0 */
6096 + uint32 clkstatestretch;
6097 + uint32 PAD[14];
6098 +
6099 + /* ExtBus control registers (corerev >= 3) */
6100 + uint32 pcmcia_config; /* 0x100 */
6101 + uint32 pcmcia_memwait;
6102 + uint32 pcmcia_attrwait;
6103 + uint32 pcmcia_iowait;
6104 + uint32 ide_config;
6105 + uint32 ide_memwait;
6106 + uint32 ide_attrwait;
6107 + uint32 ide_iowait;
6108 + uint32 prog_config;
6109 + uint32 prog_waitcount;
6110 + uint32 flash_config;
6111 + uint32 flash_waitcount;
6112 + uint32 PAD[44];
6113 +
6114 + /* Clock control and hardware workarounds */
6115 + uint32 clk_ctl_st;
6116 + uint32 hw_war;
6117 + uint32 PAD[70];
6118 +
6119 + /* uarts */
6120 + uint8 uart0data; /* 0x300 */
6121 + uint8 uart0imr;
6122 + uint8 uart0fcr;
6123 + uint8 uart0lcr;
6124 + uint8 uart0mcr;
6125 + uint8 uart0lsr;
6126 + uint8 uart0msr;
6127 + uint8 uart0scratch;
6128 + uint8 PAD[248]; /* corerev >= 1 */
6129 +
6130 + uint8 uart1data; /* 0x400 */
6131 + uint8 uart1imr;
6132 + uint8 uart1fcr;
6133 + uint8 uart1lcr;
6134 + uint8 uart1mcr;
6135 + uint8 uart1lsr;
6136 + uint8 uart1msr;
6137 + uint8 uart1scratch;
6138 +} chipcregs_t;
6139 +
6140 +#endif /* _LANGUAGE_ASSEMBLY */
6141 +
6142 +#define CC_CHIPID 0
6143 +#define CC_CAPABILITIES 4
6144 +#define CC_JTAGCMD 0x30
6145 +#define CC_JTAGIR 0x34
6146 +#define CC_JTAGDR 0x38
6147 +#define CC_JTAGCTRL 0x3c
6148 +#define CC_WATCHDOG 0x80
6149 +#define CC_CLKC_N 0x90
6150 +#define CC_CLKC_M0 0x94
6151 +#define CC_CLKC_M1 0x98
6152 +#define CC_CLKC_M2 0x9c
6153 +#define CC_CLKC_M3 0xa0
6154 +#define CC_CLKDIV 0xa4
6155 +#define CC_SYS_CLK_CTL 0xc0
6156 +#define CC_OTP 0x800
6157 +
6158 +/* chipid */
6159 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
6160 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
6161 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
6162 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
6163 +#define CID_PKG_SHIFT 20 /* Package Option shift */
6164 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
6165 +#define CID_CC_SHIFT 24
6166 +
6167 +/* capabilities */
6168 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
6169 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
6170 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
6171 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
6172 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
6173 +#define CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
6174 +#define CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
6175 +#define CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
6176 +#define CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
6177 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
6178 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
6179 +#define CAP_PWR_CTL 0x00040000 /* Power control */
6180 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
6181 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
6182 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
6183 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
6184 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
6185 +#define CAP_BKPLN64 0x08000000 /* 64-bit backplane */
6186 +
6187 +/* PLL type */
6188 +#define PLL_NONE 0x00000000
6189 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
6190 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
6191 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
6192 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
6193 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
6194 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
6195 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
6196 +
6197 +/* corecontrol */
6198 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
6199 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
6200 +
6201 +/* chipcontrol */
6202 +#define CHIPCTRL_4321A0_DEFAULT 0x3a4
6203 +#define CHIPCTRL_4321A1_DEFAULT 0x0a4
6204 +
6205 +/* Fields in the otpstatus register */
6206 +#define OTPS_PROGFAIL 0x80000000
6207 +#define OTPS_PROTECT 0x00000007
6208 +#define OTPS_HW_PROTECT 0x00000001
6209 +#define OTPS_SW_PROTECT 0x00000002
6210 +#define OTPS_CID_PROTECT 0x00000004
6211 +
6212 +/* Fields in the otpcontrol register */
6213 +#define OTPC_RECWAIT 0xff000000
6214 +#define OTPC_PROGWAIT 0x00ffff00
6215 +#define OTPC_PRW_SHIFT 8
6216 +#define OTPC_MAXFAIL 0x00000038
6217 +#define OTPC_VSEL 0x00000006
6218 +#define OTPC_SELVL 0x00000001
6219 +
6220 +/* Fields in otpprog */
6221 +#define OTPP_COL_MASK 0x000000ff
6222 +#define OTPP_ROW_MASK 0x0000ff00
6223 +#define OTPP_ROW_SHIFT 8
6224 +#define OTPP_READERR 0x10000000
6225 +#define OTPP_VALUE 0x20000000
6226 +#define OTPP_VALUE_SHIFT 29
6227 +#define OTPP_READ 0x40000000
6228 +#define OTPP_START 0x80000000
6229 +#define OTPP_BUSY 0x80000000
6230 +
6231 +/* jtagcmd */
6232 +#define JCMD_START 0x80000000
6233 +#define JCMD_BUSY 0x80000000
6234 +#define JCMD_PAUSE 0x40000000
6235 +#define JCMD0_ACC_MASK 0x0000f000
6236 +#define JCMD0_ACC_IRDR 0x00000000
6237 +#define JCMD0_ACC_DR 0x00001000
6238 +#define JCMD0_ACC_IR 0x00002000
6239 +#define JCMD0_ACC_RESET 0x00003000
6240 +#define JCMD0_ACC_IRPDR 0x00004000
6241 +#define JCMD0_ACC_PDR 0x00005000
6242 +#define JCMD0_IRW_MASK 0x00000f00
6243 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
6244 +#define JCMD_ACC_IRDR 0x00000000
6245 +#define JCMD_ACC_DR 0x00010000
6246 +#define JCMD_ACC_IR 0x00020000
6247 +#define JCMD_ACC_RESET 0x00030000
6248 +#define JCMD_ACC_IRPDR 0x00040000
6249 +#define JCMD_ACC_PDR 0x00050000
6250 +#define JCMD_IRW_MASK 0x00001f00
6251 +#define JCMD_IRW_SHIFT 8
6252 +#define JCMD_DRW_MASK 0x0000003f
6253 +
6254 +/* jtagctrl */
6255 +#define JCTRL_FORCE_CLK 4 /* Force clock */
6256 +#define JCTRL_EXT_EN 2 /* Enable external targets */
6257 +#define JCTRL_EN 1 /* Enable Jtag master */
6258 +
6259 +/* Fields in clkdiv */
6260 +#define CLKD_SFLASH 0x0f000000
6261 +#define CLKD_SFLASH_SHIFT 24
6262 +#define CLKD_OTP 0x000f0000
6263 +#define CLKD_OTP_SHIFT 16
6264 +#define CLKD_JTAG 0x00000f00
6265 +#define CLKD_JTAG_SHIFT 8
6266 +#define CLKD_UART 0x000000ff
6267 +
6268 +/* intstatus/intmask */
6269 +#define CI_GPIO 0x00000001 /* gpio intr */
6270 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
6271 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
6272 +
6273 +/* slow_clk_ctl */
6274 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
6275 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
6276 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
6277 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
6278 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
6279 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled,
6280 + * 0: LPO is enabled
6281 + */
6282 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock,
6283 + * 0: power logic control
6284 + */
6285 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors
6286 + * PLL clock disable requests from core
6287 + */
6288 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't
6289 + * disable crystal when appropriate
6290 + */
6291 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
6292 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
6293 +#define SCC_CD_SHIFT 16
6294 +
6295 +/* system_clk_ctl */
6296 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
6297 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
6298 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
6299 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
6300 +#define SYCC_HR 0x00000010 /* Force HT */
6301 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
6302 +#define SYCC_CD_SHIFT 16
6303 +
6304 +/* gpiotimerval */
6305 +#define GPIO_ONTIME_SHIFT 16
6306 +
6307 +/* clockcontrol_n */
6308 +#define CN_N1_MASK 0x3f /* n1 control */
6309 +#define CN_N2_MASK 0x3f00 /* n2 control */
6310 +#define CN_N2_SHIFT 8
6311 +#define CN_PLLC_MASK 0xf0000 /* pll control */
6312 +#define CN_PLLC_SHIFT 16
6313 +
6314 +/* clockcontrol_sb/pci/uart */
6315 +#define CC_M1_MASK 0x3f /* m1 control */
6316 +#define CC_M2_MASK 0x3f00 /* m2 control */
6317 +#define CC_M2_SHIFT 8
6318 +#define CC_M3_MASK 0x3f0000 /* m3 control */
6319 +#define CC_M3_SHIFT 16
6320 +#define CC_MC_MASK 0x1f000000 /* mux control */
6321 +#define CC_MC_SHIFT 24
6322 +
6323 +/* N3M Clock control magic field values */
6324 +#define CC_F6_2 0x02 /* A factor of 2 in */
6325 +#define CC_F6_3 0x03 /* 6-bit fields like */
6326 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
6327 +#define CC_F6_5 0x09
6328 +#define CC_F6_6 0x11
6329 +#define CC_F6_7 0x21
6330 +
6331 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
6332 +
6333 +#define CC_MC_BYPASS 0x08
6334 +#define CC_MC_M1 0x04
6335 +#define CC_MC_M1M2 0x02
6336 +#define CC_MC_M1M2M3 0x01
6337 +#define CC_MC_M1M3 0x11
6338 +
6339 +/* Type 2 Clock control magic field values */
6340 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
6341 +#define CC_T2M2_BIAS 3 /* m2 bias */
6342 +
6343 +#define CC_T2MC_M1BYP 1
6344 +#define CC_T2MC_M2BYP 2
6345 +#define CC_T2MC_M3BYP 4
6346 +
6347 +/* Type 6 Clock control magic field values */
6348 +#define CC_T6_MMASK 1 /* bits of interest in m */
6349 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
6350 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
6351 +#define SB2MIPS_T6(sb) (2 * (sb))
6352 +
6353 +/* Common clock base */
6354 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
6355 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
6356 +
6357 +/* Clock control values for 200Mhz in 5350 */
6358 +#define CLKC_5350_N 0x0311
6359 +#define CLKC_5350_M 0x04020009
6360 +
6361 +/* Flash types in the chipcommon capabilities register */
6362 +#define FLASH_NONE 0x000 /* No flash */
6363 +#define SFLASH_ST 0x100 /* ST serial flash */
6364 +#define SFLASH_AT 0x200 /* Atmel serial flash */
6365 +#define PFLASH 0x700 /* Parallel flash */
6366 +
6367 +/* Bits in the ExtBus config registers */
6368 +#define CC_CFG_EN 0x0001 /* Enable */
6369 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
6370 +#define CC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */
6371 +#define CC_CFG_EM_SYNC 0x0002 /* Synchronous */
6372 +#define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */
6373 +#define CC_CFG_EM_IDE 0x0006 /* IDE */
6374 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
6375 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
6376 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
6377 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
6378 +
6379 +/* ExtBus address space */
6380 +#define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */
6381 +#define CC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */
6382 +#define CC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */
6383 +#define CC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */
6384 +#define CC_EB_IDE 0x1a800000 /* IDE memory base */
6385 +#define CC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */
6386 +#define CC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */
6387 +#define CC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */
6388 +#define CC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */
6389 +
6390 +
6391 +/* Start/busy bit in flashcontrol */
6392 +#define SFLASH_OPCODE 0x000000ff
6393 +#define SFLASH_ACTION 0x00000700
6394 +#define SFLASH_START 0x80000000
6395 +#define SFLASH_BUSY SFLASH_START
6396 +
6397 +/* flashcontrol action codes */
6398 +#define SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */
6399 +#define SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */
6400 +#define SFLASH_ACT_OP3A 0x0200 /* opcode + 3 address bytes */
6401 +#define SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addres & 1 data bytes */
6402 +#define SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addres & 4 data bytes */
6403 +#define SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addres, 4 don't care & 4 data bytes */
6404 +#define SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addres, 1 don't care & 4 data bytes */
6405 +
6406 +/* flashcontrol action+opcodes for ST flashes */
6407 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
6408 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
6409 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
6410 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
6411 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
6412 +#define SFLASH_ST_PP 0x0302 /* Page Program */
6413 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
6414 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
6415 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
6416 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
6417 +
6418 +/* Status register bits for ST flashes */
6419 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
6420 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
6421 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
6422 +#define SFLASH_ST_BP_SHIFT 2
6423 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
6424 +
6425 +/* flashcontrol action+opcodes for Atmel flashes */
6426 +#define SFLASH_AT_READ 0x07e8
6427 +#define SFLASH_AT_PAGE_READ 0x07d2
6428 +#define SFLASH_AT_BUF1_READ
6429 +#define SFLASH_AT_BUF2_READ
6430 +#define SFLASH_AT_STATUS 0x01d7
6431 +#define SFLASH_AT_BUF1_WRITE 0x0384
6432 +#define SFLASH_AT_BUF2_WRITE 0x0387
6433 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
6434 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
6435 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
6436 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
6437 +#define SFLASH_AT_PAGE_ERASE 0x0281
6438 +#define SFLASH_AT_BLOCK_ERASE 0x0250
6439 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
6440 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
6441 +#define SFLASH_AT_BUF1_LOAD 0x0253
6442 +#define SFLASH_AT_BUF2_LOAD 0x0255
6443 +#define SFLASH_AT_BUF1_COMPARE 0x0260
6444 +#define SFLASH_AT_BUF2_COMPARE 0x0261
6445 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
6446 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
6447 +
6448 +/* Status register bits for Atmel flashes */
6449 +#define SFLASH_AT_READY 0x80
6450 +#define SFLASH_AT_MISMATCH 0x40
6451 +#define SFLASH_AT_ID_MASK 0x38
6452 +#define SFLASH_AT_ID_SHIFT 3
6453 +
6454 +/* OTP regions */
6455 +#define OTP_HW_REGION OTPS_HW_PROTECT
6456 +#define OTP_SW_REGION OTPS_SW_PROTECT
6457 +#define OTP_CID_REGION OTPS_CID_PROTECT
6458 +
6459 +/* OTP regions (Byte offsets from otp size) */
6460 +#define OTP_SWLIM_OFF (-8)
6461 +#define OTP_CIDBASE_OFF 0
6462 +#define OTP_CIDLIM_OFF 8
6463 +
6464 +/* Predefined OTP words (Word offset from otp size) */
6465 +#define OTP_BOUNDARY_OFF (-4)
6466 +#define OTP_HWSIGN_OFF (-3)
6467 +#define OTP_SWSIGN_OFF (-2)
6468 +#define OTP_CIDSIGN_OFF (-1)
6469 +
6470 +#define OTP_CID_OFF 0
6471 +#define OTP_PKG_OFF 1
6472 +#define OTP_FID_OFF 2
6473 +#define OTP_RSV_OFF 3
6474 +#define OTP_LIM_OFF 4
6475 +
6476 +#define OTP_SIGNATURE 0x578a
6477 +#define OTP_MAGIC 0x4e56
6478 +
6479 +/*
6480 + * These are the UART port assignments, expressed as offsets from the base
6481 + * register. These assignments should hold for any serial port based on
6482 + * a 8250, 16450, or 16550(A).
6483 + */
6484 +
6485 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
6486 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
6487 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
6488 +#define UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */
6489 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
6490 +#define UART_IIR 2 /* In: Interrupt Identity Register */
6491 +#define UART_FCR 2 /* Out: FIFO Control Register */
6492 +#define UART_LCR 3 /* Out: Line Control Register */
6493 +#define UART_MCR 4 /* Out: Modem Control Register */
6494 +#define UART_LSR 5 /* In: Line Status Register */
6495 +#define UART_MSR 6 /* In: Modem Status Register */
6496 +#define UART_SCR 7 /* I/O: Scratch Register */
6497 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
6498 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
6499 +#define UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */
6500 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
6501 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
6502 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
6503 +#define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */
6504 +
6505 +/* Interrupt Enable Register (IER) bits */
6506 +#define UART_IER_EDSSI 8 /* enable modem status interrupt */
6507 +#define UART_IER_ELSI 4 /* enable receiver line status interrupt */
6508 +#define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */
6509 +#define UART_IER_ERBFI 1 /* enable data available interrupt */
6510 +
6511 +#endif /* _SBCHIPC_H */
6512 diff -urN linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
6513 --- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
6514 +++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2006-10-02 21:19:59.000000000 +0200
6515 @@ -0,0 +1,369 @@
6516 +/*
6517 + * Broadcom SiliconBackplane hardware register definitions.
6518 + *
6519 + * Copyright 2006, Broadcom Corporation
6520 + * All Rights Reserved.
6521 + *
6522 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6523 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6524 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6525 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6526 + *
6527 + * $Id: sbconfig.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
6528 + */
6529 +
6530 +#ifndef _SBCONFIG_H
6531 +#define _SBCONFIG_H
6532 +
6533 +/* cpp contortions to concatenate w/arg prescan */
6534 +#ifndef PAD
6535 +#define _PADLINE(line) pad ## line
6536 +#define _XSTR(line) _PADLINE(line)
6537 +#define PAD _XSTR(__LINE__)
6538 +#endif
6539 +
6540 +/*
6541 + * SiliconBackplane Address Map.
6542 + * All regions may not exist on all chips.
6543 + */
6544 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
6545 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
6546 +#define SB_PCI_MEM_SZ (64 * 1024 * 1024)
6547 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
6548 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
6549 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
6550 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
6551 +
6552 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
6553 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
6554 +
6555 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
6556 +#define SB_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
6557 +#define SB_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
6558 +
6559 +#define SB_ROM 0x20000000 /* ARM ROM */
6560 +#define SB_SRAM2 0x80000000 /* ARM SRAM Region 2 */
6561 +#define SB_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */
6562 +#define SB_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */
6563 +
6564 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
6565 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
6566 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2
6567 + * (2 ZettaBytes), low 32 bits
6568 + */
6569 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2
6570 + * (2 ZettaBytes), high 32 bits
6571 + */
6572 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
6573 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
6574 +
6575 +
6576 +/* enumeration space related defs */
6577 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
6578 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
6579 +#define SB_MAXFUNCS 4 /* max. # functions per core */
6580 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
6581 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
6582 +
6583 +/* mips address */
6584 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
6585 +
6586 +/*
6587 + * Sonics Configuration Space Registers.
6588 + */
6589 +#define SBIPSFLAG 0x08
6590 +#define SBTPSFLAG 0x18
6591 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
6592 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
6593 +#define SBADMATCH3 0x60
6594 +#define SBADMATCH2 0x68
6595 +#define SBADMATCH1 0x70
6596 +#define SBIMSTATE 0x90
6597 +#define SBINTVEC 0x94
6598 +#define SBTMSTATELOW 0x98
6599 +#define SBTMSTATEHIGH 0x9c
6600 +#define SBBWA0 0xa0
6601 +#define SBIMCONFIGLOW 0xa8
6602 +#define SBIMCONFIGHIGH 0xac
6603 +#define SBADMATCH0 0xb0
6604 +#define SBTMCONFIGLOW 0xb8
6605 +#define SBTMCONFIGHIGH 0xbc
6606 +#define SBBCONFIG 0xc0
6607 +#define SBBSTATE 0xc8
6608 +#define SBACTCNFG 0xd8
6609 +#define SBFLAGST 0xe8
6610 +#define SBIDLOW 0xf8
6611 +#define SBIDHIGH 0xfc
6612 +
6613 +/* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have
6614 + * a few registers *below* that line. I think it would be very confusing to try
6615 + * and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here,
6616 + */
6617 +
6618 +#define SBIMERRLOGA 0xea8
6619 +#define SBIMERRLOG 0xeb0
6620 +#define SBTMPORTCONNID0 0xed8
6621 +#define SBTMPORTLOCK0 0xef8
6622 +
6623 +#ifndef _LANGUAGE_ASSEMBLY
6624 +
6625 +typedef volatile struct _sbconfig {
6626 + uint32 PAD[2];
6627 + uint32 sbipsflag; /* initiator port ocp slave flag */
6628 + uint32 PAD[3];
6629 + uint32 sbtpsflag; /* target port ocp slave flag */
6630 + uint32 PAD[11];
6631 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
6632 + uint32 PAD;
6633 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
6634 + uint32 PAD[3];
6635 + uint32 sbadmatch3; /* address match3 */
6636 + uint32 PAD;
6637 + uint32 sbadmatch2; /* address match2 */
6638 + uint32 PAD;
6639 + uint32 sbadmatch1; /* address match1 */
6640 + uint32 PAD[7];
6641 + uint32 sbimstate; /* initiator agent state */
6642 + uint32 sbintvec; /* interrupt mask */
6643 + uint32 sbtmstatelow; /* target state */
6644 + uint32 sbtmstatehigh; /* target state */
6645 + uint32 sbbwa0; /* bandwidth allocation table0 */
6646 + uint32 PAD;
6647 + uint32 sbimconfiglow; /* initiator configuration */
6648 + uint32 sbimconfighigh; /* initiator configuration */
6649 + uint32 sbadmatch0; /* address match0 */
6650 + uint32 PAD;
6651 + uint32 sbtmconfiglow; /* target configuration */
6652 + uint32 sbtmconfighigh; /* target configuration */
6653 + uint32 sbbconfig; /* broadcast configuration */
6654 + uint32 PAD;
6655 + uint32 sbbstate; /* broadcast state */
6656 + uint32 PAD[3];
6657 + uint32 sbactcnfg; /* activate configuration */
6658 + uint32 PAD[3];
6659 + uint32 sbflagst; /* current sbflags */
6660 + uint32 PAD[3];
6661 + uint32 sbidlow; /* identification */
6662 + uint32 sbidhigh; /* identification */
6663 +} sbconfig_t;
6664 +
6665 +#endif /* _LANGUAGE_ASSEMBLY */
6666 +
6667 +/* sbipsflag */
6668 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
6669 +#define SBIPS_INT1_SHIFT 0
6670 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
6671 +#define SBIPS_INT2_SHIFT 8
6672 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
6673 +#define SBIPS_INT3_SHIFT 16
6674 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
6675 +#define SBIPS_INT4_SHIFT 24
6676 +
6677 +/* sbtpsflag */
6678 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
6679 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
6680 +
6681 +/* sbtmerrlog */
6682 +#define SBTMEL_CM 0x00000007 /* command */
6683 +#define SBTMEL_CI 0x0000ff00 /* connection id */
6684 +#define SBTMEL_EC 0x0f000000 /* error code */
6685 +#define SBTMEL_ME 0x80000000 /* multiple error */
6686 +
6687 +/* sbimstate */
6688 +#define SBIM_PC 0xf /* pipecount */
6689 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
6690 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
6691 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
6692 +#define SBIM_AP_TK 0x20 /* use token only */
6693 +#define SBIM_AP_RSV 0x30 /* reserved */
6694 +#define SBIM_IBE 0x20000 /* inbanderror */
6695 +#define SBIM_TO 0x40000 /* timeout */
6696 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
6697 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
6698 +
6699 +/* sbtmstatelow */
6700 +#define SBTML_RESET 0x1 /* reset */
6701 +#define SBTML_REJ_MASK 0x6 /* reject */
6702 +#define SBTML_REJ_SHIFT 1
6703 +#define SBTML_CLK 0x10000 /* clock enable */
6704 +#define SBTML_FGC 0x20000 /* force gated clocks on */
6705 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
6706 +#define SBTML_PE 0x40000000 /* pme enable */
6707 +#define SBTML_BE 0x80000000 /* bist enable */
6708 +
6709 +/* sbtmstatehigh */
6710 +#define SBTMH_SERR 0x1 /* serror */
6711 +#define SBTMH_INT 0x2 /* interrupt */
6712 +#define SBTMH_BUSY 0x4 /* busy */
6713 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
6714 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
6715 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
6716 +#define SBTMH_GCR 0x20000000 /* gated clock request */
6717 +#define SBTMH_BISTF 0x40000000 /* bist failed */
6718 +#define SBTMH_BISTD 0x80000000 /* bist done */
6719 +
6720 +
6721 +/* sbbwa0 */
6722 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
6723 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
6724 +#define SBBWA_TAB1_SHIFT 16
6725 +
6726 +/* sbimconfiglow */
6727 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
6728 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
6729 +#define SBIMCL_RTO_SHIFT 4
6730 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
6731 +#define SBIMCL_CID_SHIFT 16
6732 +
6733 +/* sbimconfighigh */
6734 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
6735 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
6736 +#define SBIMCH_TEM_SHIFT 4
6737 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
6738 +#define SBIMCH_BEM_SHIFT 6
6739 +
6740 +/* sbadmatch0 */
6741 +#define SBAM_TYPE_MASK 0x3 /* address type */
6742 +#define SBAM_AD64 0x4 /* reserved */
6743 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
6744 +#define SBAM_ADINT0_SHIFT 3
6745 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
6746 +#define SBAM_ADINT1_SHIFT 3
6747 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
6748 +#define SBAM_ADINT2_SHIFT 3
6749 +#define SBAM_ADEN 0x400 /* enable */
6750 +#define SBAM_ADNEG 0x800 /* negative decode */
6751 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
6752 +#define SBAM_BASE0_SHIFT 8
6753 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
6754 +#define SBAM_BASE1_SHIFT 12
6755 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
6756 +#define SBAM_BASE2_SHIFT 16
6757 +
6758 +/* sbtmconfiglow */
6759 +#define SBTMCL_CD_MASK 0xff /* clock divide */
6760 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
6761 +#define SBTMCL_CO_SHIFT 11
6762 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
6763 +#define SBTMCL_IF_SHIFT 18
6764 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
6765 +#define SBTMCL_IM_SHIFT 24
6766 +
6767 +/* sbtmconfighigh */
6768 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
6769 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
6770 +#define SBTMCH_RM_SHIFT 2
6771 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
6772 +#define SBTMCH_SM_SHIFT 4
6773 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
6774 +#define SBTMCH_EM_SHIFT 8
6775 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
6776 +#define SBTMCH_IM_SHIFT 10
6777 +
6778 +/* sbbconfig */
6779 +#define SBBC_LAT_MASK 0x3 /* sb latency */
6780 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
6781 +#define SBBC_MAX0_SHIFT 16
6782 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
6783 +#define SBBC_MAX1_SHIFT 20
6784 +
6785 +/* sbbstate */
6786 +#define SBBS_SRD 0x1 /* st reg disable */
6787 +#define SBBS_HRD 0x2 /* hold reg disable */
6788 +
6789 +/* sbidlow */
6790 +#define SBIDL_CS_MASK 0x3 /* config space */
6791 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
6792 +#define SBIDL_AR_SHIFT 3
6793 +#define SBIDL_SYNCH 0x40 /* sync */
6794 +#define SBIDL_INIT 0x80 /* initiator */
6795 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
6796 +#define SBIDL_MINLAT_SHIFT 8
6797 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
6798 +#define SBIDL_MAXLAT_SHIFT 12
6799 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
6800 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
6801 +#define SBIDL_CW_SHIFT 18
6802 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
6803 +#define SBIDL_TP_SHIFT 20
6804 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
6805 +#define SBIDL_IP_SHIFT 24
6806 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
6807 +#define SBIDL_RV_SHIFT 28
6808 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
6809 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
6810 +
6811 +/* sbidhigh */
6812 +#define SBIDH_RC_MASK 0x000f /* revision code */
6813 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
6814 +#define SBIDH_RCE_SHIFT 8
6815 +#define SBCOREREV(sbidh) \
6816 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
6817 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
6818 +#define SBIDH_CC_SHIFT 4
6819 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
6820 +#define SBIDH_VC_SHIFT 16
6821 +
6822 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
6823 +
6824 +/* vendor codes */
6825 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
6826 +
6827 +/* core codes */
6828 +#define SB_NODEV 0x700 /* Invalid coreid */
6829 +#define SB_CC 0x800 /* chipcommon core */
6830 +#define SB_ILINE20 0x801 /* iline20 core */
6831 +#define SB_SDRAM 0x803 /* sdram core */
6832 +#define SB_PCI 0x804 /* pci core */
6833 +#define SB_MIPS 0x805 /* mips core */
6834 +#define SB_ENET 0x806 /* enet mac core */
6835 +#define SB_CODEC 0x807 /* v90 codec core */
6836 +#define SB_USB 0x808 /* usb 1.1 host/device core */
6837 +#define SB_ADSL 0x809 /* ADSL core */
6838 +#define SB_ILINE100 0x80a /* iline100 core */
6839 +#define SB_IPSEC 0x80b /* ipsec core */
6840 +#define SB_PCMCIA 0x80d /* pcmcia core */
6841 +#define SB_SDIOD SB_PCMCIA /* pcmcia core has sdio device */
6842 +#define SB_SOCRAM 0x80e /* internal memory core */
6843 +#define SB_MEMC 0x80f /* memc sdram core */
6844 +#define SB_EXTIF 0x811 /* external interface core */
6845 +#define SB_D11 0x812 /* 802.11 MAC core */
6846 +#define SB_MIPS33 0x816 /* mips3302 core */
6847 +#define SB_USB11H 0x817 /* usb 1.1 host core */
6848 +#define SB_USB11D 0x818 /* usb 1.1 device core */
6849 +#define SB_USB20H 0x819 /* usb 2.0 host core */
6850 +#define SB_USB20D 0x81a /* usb 2.0 device core */
6851 +#define SB_SDIOH 0x81b /* sdio host core */
6852 +#define SB_ROBO 0x81c /* roboswitch core */
6853 +#define SB_ATA100 0x81d /* parallel ATA core */
6854 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
6855 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
6856 +#define SB_PCIE 0x820 /* pci express core */
6857 +#define SB_MIMO 0x821 /* MIMO phy core */
6858 +#define SB_SRAMC 0x822 /* SRAM controller core */
6859 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
6860 +#define SB_ARM11 0x824 /* ARM 1176 core */
6861 +#define SB_ARM7 0x825 /* ARM 7tdmi core */
6862 +
6863 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
6864 +
6865 +/* Not really related to Silicon Backplane, but a couple of software
6866 + * conventions for the use the flash space:
6867 + */
6868 +
6869 +/* Minumum amount of flash we support */
6870 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
6871 +
6872 +/* A boot/binary may have an embedded block that describes its size */
6873 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
6874 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
6875 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
6876 +#define BISZ_TXTST_IDX 1 /* 1: text start */
6877 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
6878 +#define BISZ_DATAST_IDX 3 /* 3: text start */
6879 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
6880 +#define BISZ_BSSST_IDX 5 /* 5: text start */
6881 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
6882 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
6883 +
6884 +#endif /* _SBCONFIG_H */
6885 diff -urN linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
6886 --- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
6887 +++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2006-10-02 21:19:59.000000000 +0200
6888 @@ -0,0 +1,243 @@
6889 +/*
6890 + * Hardware-specific External Interface I/O core definitions
6891 + * for the BCM47xx family of SiliconBackplane-based chips.
6892 + *
6893 + * The External Interface core supports a total of three external chip selects
6894 + * supporting external interfaces. One of the external chip selects is
6895 + * used for Flash, one is used for PCMCIA, and the other may be
6896 + * programmed to support either a synchronous interface or an
6897 + * asynchronous interface. The asynchronous interface can be used to
6898 + * support external devices such as UARTs and the BCM2019 Bluetooth
6899 + * baseband processor.
6900 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
6901 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
6902 + *
6903 + * Copyright 2006, Broadcom Corporation
6904 + * All Rights Reserved.
6905 + *
6906 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6907 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6908 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6909 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6910 + *
6911 + * $Id: sbextif.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
6912 + */
6913 +
6914 +#ifndef _SBEXTIF_H
6915 +#define _SBEXTIF_H
6916 +
6917 +/* external interface address space */
6918 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
6919 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
6920 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
6921 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
6922 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
6923 +
6924 +/* cpp contortions to concatenate w/arg prescan */
6925 +#ifndef PAD
6926 +#define _PADLINE(line) pad ## line
6927 +#define _XSTR(line) _PADLINE(line)
6928 +#define PAD _XSTR(__LINE__)
6929 +#endif /* PAD */
6930 +
6931 +/*
6932 + * The multiple instances of output and output enable registers
6933 + * are present to allow driver software for multiple cores to control
6934 + * gpio outputs without needing to share a single register pair.
6935 + */
6936 +struct gpiouser {
6937 + uint32 out;
6938 + uint32 outen;
6939 +};
6940 +#define NGPIOUSER 5
6941 +
6942 +typedef volatile struct {
6943 + uint32 corecontrol;
6944 + uint32 extstatus;
6945 + uint32 PAD[2];
6946 +
6947 + /* pcmcia control registers */
6948 + uint32 pcmcia_config;
6949 + uint32 pcmcia_memwait;
6950 + uint32 pcmcia_attrwait;
6951 + uint32 pcmcia_iowait;
6952 +
6953 + /* programmable interface control registers */
6954 + uint32 prog_config;
6955 + uint32 prog_waitcount;
6956 +
6957 + /* flash control registers */
6958 + uint32 flash_config;
6959 + uint32 flash_waitcount;
6960 + uint32 PAD[4];
6961 +
6962 + uint32 watchdog;
6963 +
6964 + /* clock control */
6965 + uint32 clockcontrol_n;
6966 + uint32 clockcontrol_sb;
6967 + uint32 clockcontrol_pci;
6968 + uint32 clockcontrol_mii;
6969 + uint32 PAD[3];
6970 +
6971 + /* gpio */
6972 + uint32 gpioin;
6973 + struct gpiouser gpio[NGPIOUSER];
6974 + uint32 PAD;
6975 + uint32 ejtagouten;
6976 + uint32 gpiointpolarity;
6977 + uint32 gpiointmask;
6978 + uint32 PAD[153];
6979 +
6980 + uint8 uartdata;
6981 + uint8 PAD[3];
6982 + uint8 uartimer;
6983 + uint8 PAD[3];
6984 + uint8 uartfcr;
6985 + uint8 PAD[3];
6986 + uint8 uartlcr;
6987 + uint8 PAD[3];
6988 + uint8 uartmcr;
6989 + uint8 PAD[3];
6990 + uint8 uartlsr;
6991 + uint8 PAD[3];
6992 + uint8 uartmsr;
6993 + uint8 PAD[3];
6994 + uint8 uartscratch;
6995 + uint8 PAD[3];
6996 +} extifregs_t;
6997 +
6998 +/* corecontrol */
6999 +#define CC_UE (1 << 0) /* uart enable */
7000 +
7001 +/* extstatus */
7002 +#define ES_EM (1 << 0) /* endian mode (ro) */
7003 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
7004 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
7005 +
7006 +/* gpio bit mask */
7007 +#define GPIO_BIT0 (1 << 0)
7008 +#define GPIO_BIT1 (1 << 1)
7009 +#define GPIO_BIT2 (1 << 2)
7010 +#define GPIO_BIT3 (1 << 3)
7011 +#define GPIO_BIT4 (1 << 4)
7012 +#define GPIO_BIT5 (1 << 5)
7013 +#define GPIO_BIT6 (1 << 6)
7014 +#define GPIO_BIT7 (1 << 7)
7015 +
7016 +
7017 +/* pcmcia/prog/flash_config */
7018 +#define CF_EN (1 << 0) /* enable */
7019 +#define CF_EM_MASK 0xe /* mode */
7020 +#define CF_EM_SHIFT 1
7021 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
7022 +#define CF_EM_SYNC 0x2 /* synchronous mode */
7023 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
7024 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
7025 +#define CF_BS (1 << 5) /* byteswap */
7026 +#define CF_CD_MASK 0xc0 /* clock divider */
7027 +#define CF_CD_SHIFT 6
7028 +#define CF_CD_DIV2 0x0 /* backplane/2 */
7029 +#define CF_CD_DIV3 0x40 /* backplane/3 */
7030 +#define CF_CD_DIV4 0x80 /* backplane/4 */
7031 +#define CF_CE (1 << 8) /* clock enable */
7032 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
7033 +
7034 +/* pcmcia_memwait */
7035 +#define PM_W0_MASK 0x3f /* waitcount0 */
7036 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
7037 +#define PM_W1_SHIFT 8
7038 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
7039 +#define PM_W2_SHIFT 16
7040 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
7041 +#define PM_W3_SHIFT 24
7042 +
7043 +/* pcmcia_attrwait */
7044 +#define PA_W0_MASK 0x3f /* waitcount0 */
7045 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
7046 +#define PA_W1_SHIFT 8
7047 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
7048 +#define PA_W2_SHIFT 16
7049 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
7050 +#define PA_W3_SHIFT 24
7051 +
7052 +/* pcmcia_iowait */
7053 +#define PI_W0_MASK 0x3f /* waitcount0 */
7054 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
7055 +#define PI_W1_SHIFT 8
7056 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
7057 +#define PI_W2_SHIFT 16
7058 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
7059 +#define PI_W3_SHIFT 24
7060 +
7061 +/* prog_waitcount */
7062 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
7063 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
7064 +#define PW_W1_SHIFT 8
7065 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
7066 +#define PW_W2_SHIFT 16
7067 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
7068 +#define PW_W3_SHIFT 24
7069 +
7070 +#define PW_W0 0x0000000c
7071 +#define PW_W1 0x00000a00
7072 +#define PW_W2 0x00020000
7073 +#define PW_W3 0x01000000
7074 +
7075 +/* flash_waitcount */
7076 +#define FW_W0_MASK 0x1f /* waitcount0 */
7077 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
7078 +#define FW_W1_SHIFT 8
7079 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
7080 +#define FW_W2_SHIFT 16
7081 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
7082 +#define FW_W3_SHIFT 24
7083 +
7084 +/* watchdog */
7085 +#define WATCHDOG_CLOCK 48000000 /* Hz */
7086 +
7087 +/* clockcontrol_n */
7088 +#define CN_N1_MASK 0x3f /* n1 control */
7089 +#define CN_N2_MASK 0x3f00 /* n2 control */
7090 +#define CN_N2_SHIFT 8
7091 +
7092 +/* clockcontrol_sb/pci/mii */
7093 +#define CC_M1_MASK 0x3f /* m1 control */
7094 +#define CC_M2_MASK 0x3f00 /* m2 control */
7095 +#define CC_M2_SHIFT 8
7096 +#define CC_M3_MASK 0x3f0000 /* m3 control */
7097 +#define CC_M3_SHIFT 16
7098 +#define CC_MC_MASK 0x1f000000 /* mux control */
7099 +#define CC_MC_SHIFT 24
7100 +
7101 +/* Clock control default values */
7102 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
7103 +#define CC_DEF_100 0x04020011
7104 +#define CC_DEF_33 0x11030011
7105 +#define CC_DEF_25 0x11050011
7106 +
7107 +/* Clock control values for 125Mhz */
7108 +#define CC_125_N 0x0802
7109 +#define CC_125_M 0x04020009
7110 +#define CC_125_M25 0x11090009
7111 +#define CC_125_M33 0x11090005
7112 +
7113 +/* Clock control magic field values */
7114 +#define CC_F6_2 0x02 /* A factor of 2 in */
7115 +#define CC_F6_3 0x03 /* 6-bit fields like */
7116 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
7117 +#define CC_F6_5 0x09
7118 +#define CC_F6_6 0x11
7119 +#define CC_F6_7 0x21
7120 +
7121 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
7122 +
7123 +#define CC_MC_BYPASS 0x08
7124 +#define CC_MC_M1 0x04
7125 +#define CC_MC_M1M2 0x02
7126 +#define CC_MC_M1M2M3 0x01
7127 +#define CC_MC_M1M3 0x11
7128 +
7129 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
7130 +
7131 +#endif /* _SBEXTIF_H */
7132 diff -urN linux.old/arch/mips/bcm947xx/include/sbhndmips.h linux.dev/arch/mips/bcm947xx/include/sbhndmips.h
7133 --- linux.old/arch/mips/bcm947xx/include/sbhndmips.h 1970-01-01 01:00:00.000000000 +0100
7134 +++ linux.dev/arch/mips/bcm947xx/include/sbhndmips.h 2006-10-02 21:19:59.000000000 +0200
7135 @@ -0,0 +1,47 @@
7136 +/*
7137 + * Broadcom SiliconBackplane MIPS definitions
7138 + *
7139 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
7140 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
7141 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
7142 + * interface. The core revision is stored in the SB ID register in SB
7143 + * configuration space.
7144 + *
7145 + * Copyright 2006, Broadcom Corporation
7146 + * All Rights Reserved.
7147 + *
7148 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7149 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7150 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7151 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7152 + *
7153 + * $Id: sbhndmips.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
7154 + */
7155 +
7156 +#ifndef _sbhndmips_h_
7157 +#define _sbhndmips_h_
7158 +
7159 +#include <mipsinc.h>
7160 +
7161 +#ifndef _LANGUAGE_ASSEMBLY
7162 +
7163 +/* cpp contortions to concatenate w/arg prescan */
7164 +#ifndef PAD
7165 +#define _PADLINE(line) pad ## line
7166 +#define _XSTR(line) _PADLINE(line)
7167 +#define PAD _XSTR(__LINE__)
7168 +#endif /* PAD */
7169 +
7170 +typedef volatile struct {
7171 + uint32 corecontrol;
7172 + uint32 PAD[2];
7173 + uint32 biststatus;
7174 + uint32 PAD[4];
7175 + uint32 intstatus;
7176 + uint32 intmask;
7177 + uint32 timer;
7178 +} mipsregs_t;
7179 +
7180 +#endif /* _LANGUAGE_ASSEMBLY */
7181 +
7182 +#endif /* _sbhndmips_h_ */
7183 diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
7184 --- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
7185 +++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2006-10-02 21:19:59.000000000 +0200
7186 @@ -0,0 +1,147 @@
7187 +/*
7188 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
7189 + *
7190 + * Copyright 2006, Broadcom Corporation
7191 + * All Rights Reserved.
7192 + *
7193 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7194 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7195 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7196 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7197 + *
7198 + * $Id: sbmemc.h,v 1.6 2006/03/02 12:33:44 honor Exp $
7199 + */
7200 +
7201 +#ifndef _SBMEMC_H
7202 +#define _SBMEMC_H
7203 +
7204 +#ifdef _LANGUAGE_ASSEMBLY
7205 +
7206 +#define MEMC_CONTROL 0x00
7207 +#define MEMC_CONFIG 0x04
7208 +#define MEMC_REFRESH 0x08
7209 +#define MEMC_BISTSTAT 0x0c
7210 +#define MEMC_MODEBUF 0x10
7211 +#define MEMC_BKCLS 0x14
7212 +#define MEMC_PRIORINV 0x18
7213 +#define MEMC_DRAMTIM 0x1c
7214 +#define MEMC_INTSTAT 0x20
7215 +#define MEMC_INTMASK 0x24
7216 +#define MEMC_INTINFO 0x28
7217 +#define MEMC_NCDLCTL 0x30
7218 +#define MEMC_RDNCDLCOR 0x34
7219 +#define MEMC_WRNCDLCOR 0x38
7220 +#define MEMC_MISCDLYCTL 0x3c
7221 +#define MEMC_DQSGATENCDL 0x40
7222 +#define MEMC_SPARE 0x44
7223 +#define MEMC_TPADDR 0x48
7224 +#define MEMC_TPDATA 0x4c
7225 +#define MEMC_BARRIER 0x50
7226 +#define MEMC_CORE 0x54
7227 +
7228 +#else /* !_LANGUAGE_ASSEMBLY */
7229 +
7230 +/* Sonics side: MEMC core registers */
7231 +typedef volatile struct sbmemcregs {
7232 + uint32 control;
7233 + uint32 config;
7234 + uint32 refresh;
7235 + uint32 biststat;
7236 + uint32 modebuf;
7237 + uint32 bkcls;
7238 + uint32 priorinv;
7239 + uint32 dramtim;
7240 + uint32 intstat;
7241 + uint32 intmask;
7242 + uint32 intinfo;
7243 + uint32 reserved1;
7244 + uint32 ncdlctl;
7245 + uint32 rdncdlcor;
7246 + uint32 wrncdlcor;
7247 + uint32 miscdlyctl;
7248 + uint32 dqsgatencdl;
7249 + uint32 spare;
7250 + uint32 tpaddr;
7251 + uint32 tpdata;
7252 + uint32 barrier;
7253 + uint32 core;
7254 +} sbmemcregs_t;
7255 +
7256 +#endif /* _LANGUAGE_ASSEMBLY */
7257 +
7258 +/* MEMC Core Init values (OCP ID 0x80f) */
7259 +
7260 +/* For sdr: */
7261 +#define MEMC_SD_CONFIG_INIT 0x00048000
7262 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
7263 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
7264 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
7265 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
7266 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
7267 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
7268 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
7269 +#define MEMC_SD_CONTROL_INIT0 0x00000002
7270 +#define MEMC_SD_CONTROL_INIT1 0x00000008
7271 +#define MEMC_SD_CONTROL_INIT2 0x00000004
7272 +#define MEMC_SD_CONTROL_INIT3 0x00000010
7273 +#define MEMC_SD_CONTROL_INIT4 0x00000001
7274 +#define MEMC_SD_MODEBUF_INIT 0x00000000
7275 +#define MEMC_SD_REFRESH_INIT 0x0000840f
7276 +
7277 +
7278 +/* This is for SDRM8X8X4 */
7279 +#define MEMC_SDR_INIT 0x0008
7280 +#define MEMC_SDR_MODE 0x32
7281 +#define MEMC_SDR_NCDL 0x00020032
7282 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
7283 +
7284 +/* For ddr: */
7285 +#define MEMC_CONFIG_INIT 0x00048000
7286 +#define MEMC_DRAMTIM2_INIT 0x000754d8
7287 +#define MEMC_DRAMTIM25_INIT 0x000754d9
7288 +#define MEMC_RDNCDLCOR_INIT 0x00000000
7289 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
7290 +#define MEMC_WRNCDLCOR_INIT 0x49351200
7291 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
7292 +#define MEMC_DQSGATENCDL_INIT 0x00030000
7293 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
7294 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
7295 +#define MEMC_NCDLCTL_INIT 0x00002001
7296 +#define MEMC_CONTROL_INIT0 0x00000002
7297 +#define MEMC_CONTROL_INIT1 0x00000008
7298 +#define MEMC_MODEBUF_INIT0 0x00004000
7299 +#define MEMC_CONTROL_INIT2 0x00000010
7300 +#define MEMC_MODEBUF_INIT1 0x00000100
7301 +#define MEMC_CONTROL_INIT3 0x00000010
7302 +#define MEMC_CONTROL_INIT4 0x00000008
7303 +#define MEMC_REFRESH_INIT 0x0000840f
7304 +#define MEMC_CONTROL_INIT5 0x00000004
7305 +#define MEMC_MODEBUF_INIT2 0x00000000
7306 +#define MEMC_CONTROL_INIT6 0x00000010
7307 +#define MEMC_CONTROL_INIT7 0x00000001
7308 +
7309 +
7310 +/* This is for DDRM16X16X2 */
7311 +#define MEMC_DDR_INIT 0x0009
7312 +#define MEMC_DDR_MODE 0x62
7313 +#define MEMC_DDR_NCDL 0x0005050a
7314 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
7315 +
7316 +/* mask for sdr/ddr calibration registers */
7317 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
7318 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
7319 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
7320 +
7321 +/* masks for miscdlyctl registers */
7322 +#define MEMC_MISC_SM_MASK 0x30000000
7323 +#define MEMC_MISC_SM_SHIFT 28
7324 +#define MEMC_MISC_SD_MASK 0x0f000000
7325 +#define MEMC_MISC_SD_SHIFT 24
7326 +
7327 +/* hw threshhold for calculating wr/rd for sdr memc */
7328 +#define MEMC_CD_THRESHOLD 128
7329 +
7330 +/* Low bit of init register says if memc is ddr or sdr */
7331 +#define MEMC_CONFIG_DDR 0x00000001
7332 +
7333 +#endif /* _SBMEMC_H */
7334 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcie.h linux.dev/arch/mips/bcm947xx/include/sbpcie.h
7335 --- linux.old/arch/mips/bcm947xx/include/sbpcie.h 1970-01-01 01:00:00.000000000 +0100
7336 +++ linux.dev/arch/mips/bcm947xx/include/sbpcie.h 2006-10-02 21:19:59.000000000 +0200
7337 @@ -0,0 +1,200 @@
7338 +/*
7339 + * BCM43XX SiliconBackplane PCIE core hardware definitions.
7340 + *
7341 + * Copyright 2006, Broadcom Corporation
7342 + * All Rights Reserved.
7343 + *
7344 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7345 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7346 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7347 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7348 + *
7349 + * $Id: sbpcie.h,v 1.1.1.2 2006/02/27 03:43:16 honor Exp $
7350 + */
7351 +
7352 +#ifndef _SBPCIE_H
7353 +#define _SBPCIE_H
7354 +
7355 +/* cpp contortions to concatenate w/arg prescan */
7356 +#ifndef PAD
7357 +#define _PADLINE(line) pad ## line
7358 +#define _XSTR(line) _PADLINE(line)
7359 +#define PAD _XSTR(__LINE__)
7360 +#endif
7361 +
7362 +/* PCIE Enumeration space offsets */
7363 +#define PCIE_CORE_CONFIG_OFFSET 0x0
7364 +#define PCIE_FUNC0_CONFIG_OFFSET 0x400
7365 +#define PCIE_FUNC1_CONFIG_OFFSET 0x500
7366 +#define PCIE_FUNC2_CONFIG_OFFSET 0x600
7367 +#define PCIE_FUNC3_CONFIG_OFFSET 0x700
7368 +#define PCIE_SPROM_SHADOW_OFFSET 0x800
7369 +#define PCIE_SBCONFIG_OFFSET 0xE00
7370 +
7371 +/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
7372 +#define PCIE_DEV_BAR0_SIZE 0x4000
7373 +#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0
7374 +#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000
7375 +#define PCIE_BAR0_PCIECORE_OFFSET 0x2000
7376 +#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
7377 +
7378 +/* SB side: PCIE core and host control registers */
7379 +typedef struct sbpcieregs {
7380 + uint32 PAD[3];
7381 + uint32 biststatus; /* bist Status: 0x00C */
7382 + uint32 PAD[6];
7383 + uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */
7384 + uint32 PAD[54];
7385 + uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
7386 + uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
7387 + uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
7388 + uint32 PAD[4];
7389 +
7390 + /* pcie core supports in direct access to config space */
7391 + uint32 configaddr; /* pcie config space access: Address field: 0x120 */
7392 + uint32 configdata; /* pcie config space access: Data field: 0x124 */
7393 +
7394 + /* mdio access to serdes */
7395 + uint32 mdiocontrol; /* controls the mdio access: 0x128 */
7396 + uint32 mdiodata; /* Data to the mdio access: 0x12c */
7397 +
7398 + /* pcie protocol phy/dllp/tlp register access mechanism */
7399 + uint32 pcieaddr; /* address of the internal registeru: 0x130 */
7400 + uint32 pciedata; /* Data to/from the internal regsiter: 0x134 */
7401 +
7402 + uint32 PAD[434];
7403 + uint16 sprom[36]; /* SPROM shadow Area */
7404 +} sbpcieregs_t;
7405 +
7406 +/* SB to PCIE translation masks */
7407 +#define SBTOPCIE0_MASK 0xfc000000
7408 +#define SBTOPCIE1_MASK 0xfc000000
7409 +#define SBTOPCIE2_MASK 0xc0000000
7410 +
7411 +/* Access type bits (0:1) */
7412 +#define SBTOPCIE_MEM 0
7413 +#define SBTOPCIE_IO 1
7414 +#define SBTOPCIE_CFG0 2
7415 +#define SBTOPCIE_CFG1 3
7416 +
7417 +/* Prefetch enable bit 2 */
7418 +#define SBTOPCIE_PF 4
7419 +
7420 +/* Write Burst enable for memory write bit 3 */
7421 +#define SBTOPCIE_WR_BURST 8
7422 +
7423 +/* config access */
7424 +#define CONFIGADDR_FUNC_MASK 0x7000
7425 +#define CONFIGADDR_FUNC_SHF 12
7426 +#define CONFIGADDR_REG_MASK 0x0FFF
7427 +#define CONFIGADDR_REG_SHF 0
7428 +
7429 +/* PCIE protocol regs Indirect Address */
7430 +#define PCIEADDR_PROT_MASK 0x300
7431 +#define PCIEADDR_PROT_SHF 8
7432 +#define PCIEADDR_PL_TLP 0
7433 +#define PCIEADDR_PL_DLLP 1
7434 +#define PCIEADDR_PL_PLP 2
7435 +
7436 +/* PCIE protocol PHY diagnostic registers */
7437 +#define PCIE_PLP_MODEREG 0x200 /* Mode */
7438 +#define PCIE_PLP_STATUSREG 0x204 /* Status */
7439 +#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
7440 +#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
7441 +#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
7442 +#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
7443 +#define PCIE_PLP_ATTNREG 0x218 /* Attention */
7444 +#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */
7445 +#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */
7446 +#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
7447 +#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
7448 +#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg */
7449 +#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
7450 +#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
7451 +#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
7452 +#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
7453 +
7454 +/* PCIE protocol DLLP diagnostic registers */
7455 +#define PCIE_DLLP_LCREG 0x100 /* Link Control */
7456 +#define PCIE_DLLP_LSREG 0x104 /* Link Status */
7457 +#define PCIE_DLLP_LAREG 0x108 /* Link Attention */
7458 +#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
7459 +#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
7460 +#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
7461 +#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
7462 +#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
7463 +#define PCIE_DLLP_LRREG 0x120 /* Link Replay */
7464 +#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
7465 +#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
7466 +#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
7467 +#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
7468 +#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
7469 +#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
7470 +#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
7471 +#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
7472 +#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter */
7473 +#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
7474 +#define PCIE_DLLP_TESTREG 0x14C /* Test */
7475 +#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */
7476 +
7477 +/* PCIE protocol TLP diagnostic registers */
7478 +#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
7479 +#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
7480 +#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address */
7481 +#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address */
7482 +#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req */
7483 +#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address */
7484 +#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address */
7485 +#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req */
7486 +#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address */
7487 +#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address */
7488 +#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req */
7489 +#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len */
7490 +#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs */
7491 +#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req */
7492 +#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len */
7493 +#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0 */
7494 +#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1 */
7495 +#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2 */
7496 +#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */
7497 +#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */
7498 +#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */
7499 +#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len */
7500 +#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0 */
7501 +#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1 */
7502 +#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func */
7503 +#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter */
7504 +#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value */
7505 +#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1 */
7506 +#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2 */
7507 +#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3 */
7508 +#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4 */
7509 +
7510 +/* MDIO control */
7511 +#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
7512 +#define MDIOCTL_DIVISOR_VAL 0x2
7513 +#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
7514 +#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
7515 +
7516 +/* MDIO Data */
7517 +#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
7518 +#define MDIODATA_TA 0x00020000 /* Turnaround */
7519 +#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
7520 +#define MDIODATA_REGADDR_MASK 0x003c0000 /* Regaddr Mask */
7521 +#define MDIODATA_DEVADDR_SHF 22 /* Physmedia devaddr shift */
7522 +#define MDIODATA_DEVADDR_MASK 0x0fc00000 /* Physmedia devaddr Mask */
7523 +#define MDIODATA_WRITE 0x10000000 /* write Transaction */
7524 +#define MDIODATA_READ 0x20000000 /* Read Transaction */
7525 +#define MDIODATA_START 0x40000000 /* start of Transaction */
7526 +
7527 +/* MDIO devices (SERDES modules) */
7528 +#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
7529 +#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
7530 +#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
7531 +
7532 +/* SERDES registers */
7533 +#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
7534 +#define SERDES_RX_CDR 6 /* CDR */
7535 +#define SERDES_RX_CDRBW 7 /* CDR BW */
7536 +
7537 +#endif /* _SBPCIE_H */
7538 diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
7539 --- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
7540 +++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2006-10-02 21:19:59.000000000 +0200
7541 @@ -0,0 +1,114 @@
7542 +/*
7543 + * HND SiliconBackplane PCI core hardware definitions.
7544 + *
7545 + * Copyright 2006, Broadcom Corporation
7546 + * All Rights Reserved.
7547 + *
7548 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7549 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7550 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7551 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7552 + *
7553 + * $Id: sbpci.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
7554 + */
7555 +
7556 +#ifndef _sbpci_h_
7557 +#define _sbpci_h_
7558 +
7559 +#ifndef _LANGUAGE_ASSEMBLY
7560 +
7561 +/* cpp contortions to concatenate w/arg prescan */
7562 +#ifndef PAD
7563 +#define _PADLINE(line) pad ## line
7564 +#define _XSTR(line) _PADLINE(line)
7565 +#define PAD _XSTR(__LINE__)
7566 +#endif
7567 +
7568 +/* Sonics side: PCI core and host control registers */
7569 +typedef struct sbpciregs {
7570 + uint32 control; /* PCI control */
7571 + uint32 PAD[3];
7572 + uint32 arbcontrol; /* PCI arbiter control */
7573 + uint32 PAD[3];
7574 + uint32 intstatus; /* Interrupt status */
7575 + uint32 intmask; /* Interrupt mask */
7576 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
7577 + uint32 PAD[9];
7578 + uint32 bcastaddr; /* Sonics broadcast address */
7579 + uint32 bcastdata; /* Sonics broadcast data */
7580 + uint32 PAD[2];
7581 + uint32 gpioin; /* ro: gpio input (>=rev2) */
7582 + uint32 gpioout; /* rw: gpio output (>=rev2) */
7583 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
7584 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
7585 + uint32 PAD[36];
7586 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
7587 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
7588 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
7589 + uint32 PAD[189];
7590 + uint32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
7591 + uint16 sprom[36]; /* SPROM shadow Area */
7592 + uint32 PAD[46];
7593 +} sbpciregs_t;
7594 +
7595 +#endif /* _LANGUAGE_ASSEMBLY */
7596 +
7597 +/* PCI control */
7598 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
7599 +#define PCI_RST 0x02 /* Value driven out to pin */
7600 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
7601 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
7602 +
7603 +/* PCI arbiter control */
7604 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
7605 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
7606 +/* ParkID - for PCI corerev >= 8 */
7607 +#define PCI_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */
7608 +#define PCI_PARKID_SHIFT 2
7609 +#define PCI_PARKID_EXT0 0 /* External master 0 */
7610 +#define PCI_PARKID_EXT1 1 /* External master 1 */
7611 +#define PCI_PARKID_EXT2 2 /* External master 2 */
7612 +#define PCI_PARKID_INT 3 /* Internal master */
7613 +#define PCI_PARKID_LAST 4 /* Last active master */
7614 +
7615 +/* Interrupt status/mask */
7616 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
7617 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
7618 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
7619 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
7620 +#define PCI_PME 0x10 /* PCI PME# is asserted */
7621 +
7622 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
7623 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
7624 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
7625 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
7626 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
7627 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
7628 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
7629 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
7630 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
7631 +
7632 +/* Sonics broadcast address */
7633 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
7634 +
7635 +/* Sonics to PCI translation types */
7636 +#define SBTOPCI0_MASK 0xfc000000
7637 +#define SBTOPCI1_MASK 0xfc000000
7638 +#define SBTOPCI2_MASK 0xc0000000
7639 +#define SBTOPCI_MEM 0
7640 +#define SBTOPCI_IO 1
7641 +#define SBTOPCI_CFG0 2
7642 +#define SBTOPCI_CFG1 3
7643 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
7644 +#define SBTOPCI_BURST 0x8 /* burst enable */
7645 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
7646 +#define SBTOPCI_RC_READ 0x00 /* memory read */
7647 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
7648 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
7649 +
7650 +/* PCI core index in SROM shadow area */
7651 +#define SRSH_PI_OFFSET 0 /* first word */
7652 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
7653 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
7654 +
7655 +#endif /* _sbpci_h_ */
7656 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcmcia.h linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h
7657 --- linux.old/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
7658 +++ linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h 2006-10-02 21:19:59.000000000 +0200
7659 @@ -0,0 +1,147 @@
7660 +/*
7661 + * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
7662 + *
7663 + * Copyright 2006, Broadcom Corporation
7664 + * All Rights Reserved.
7665 + *
7666 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7667 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7668 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7669 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7670 + *
7671 + * $Id: sbpcmcia.h,v 1.1.1.9 2006/02/27 03:43:16 honor Exp $
7672 + */
7673 +
7674 +#ifndef _SBPCMCIA_H
7675 +#define _SBPCMCIA_H
7676 +
7677 +
7678 +/* All the addresses that are offsets in attribute space are divided
7679 + * by two to account for the fact that odd bytes are invalid in
7680 + * attribute space and our read/write routines make the space appear
7681 + * as if they didn't exist. Still we want to show the original numbers
7682 + * as documented in the hnd_pcmcia core manual.
7683 + */
7684 +
7685 +/* PCMCIA Function Configuration Registers */
7686 +#define PCMCIA_FCR (0x700 / 2)
7687 +
7688 +#define FCR0_OFF 0
7689 +#define FCR1_OFF (0x40 / 2)
7690 +#define FCR2_OFF (0x80 / 2)
7691 +#define FCR3_OFF (0xc0 / 2)
7692 +
7693 +#define PCMCIA_FCR0 (0x700 / 2)
7694 +#define PCMCIA_FCR1 (0x740 / 2)
7695 +#define PCMCIA_FCR2 (0x780 / 2)
7696 +#define PCMCIA_FCR3 (0x7c0 / 2)
7697 +
7698 +/* Standard PCMCIA FCR registers */
7699 +
7700 +#define PCMCIA_COR 0
7701 +
7702 +#define COR_RST 0x80
7703 +#define COR_LEV 0x40
7704 +#define COR_IRQEN 0x04
7705 +#define COR_BLREN 0x01
7706 +#define COR_FUNEN 0x01
7707 +
7708 +
7709 +#define PCICIA_FCSR (2 / 2)
7710 +#define PCICIA_PRR (4 / 2)
7711 +#define PCICIA_SCR (6 / 2)
7712 +#define PCICIA_ESR (8 / 2)
7713 +
7714 +
7715 +#define PCM_MEMOFF 0x0000
7716 +#define F0_MEMOFF 0x1000
7717 +#define F1_MEMOFF 0x2000
7718 +#define F2_MEMOFF 0x3000
7719 +#define F3_MEMOFF 0x4000
7720 +
7721 +/* Memory base in the function fcr's */
7722 +#define MEM_ADDR0 (0x728 / 2)
7723 +#define MEM_ADDR1 (0x72a / 2)
7724 +#define MEM_ADDR2 (0x72c / 2)
7725 +
7726 +/* PCMCIA base plus Srom access in fcr0: */
7727 +#define PCMCIA_ADDR0 (0x072e / 2)
7728 +#define PCMCIA_ADDR1 (0x0730 / 2)
7729 +#define PCMCIA_ADDR2 (0x0732 / 2)
7730 +
7731 +#define MEM_SEG (0x0734 / 2)
7732 +#define SROM_CS (0x0736 / 2)
7733 +#define SROM_DATAL (0x0738 / 2)
7734 +#define SROM_DATAH (0x073a / 2)
7735 +#define SROM_ADDRL (0x073c / 2)
7736 +#define SROM_ADDRH (0x073e / 2)
7737 +
7738 +/* Values for srom_cs: */
7739 +#define SROM_IDLE 0
7740 +#define SROM_WRITE 1
7741 +#define SROM_READ 2
7742 +#define SROM_WEN 4
7743 +#define SROM_WDS 7
7744 +#define SROM_DONE 8
7745 +
7746 +/* CIS stuff */
7747 +
7748 +/* The CIS stops where the FCRs start */
7749 +#define CIS_SIZE PCMCIA_FCR
7750 +
7751 +/* Standard tuples we know about */
7752 +
7753 +#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
7754 +#define CISTPL_FUNCE 0x22 /* Function extensions */
7755 +#define CISTPL_CFTABLE 0x1b /* Config table entry */
7756 +
7757 +/* Function extensions for LANs */
7758 +
7759 +#define LAN_TECH 1 /* Technology type */
7760 +#define LAN_SPEED 2 /* Raw bit rate */
7761 +#define LAN_MEDIA 3 /* Transmission media */
7762 +#define LAN_NID 4 /* Node identification (aka MAC addr) */
7763 +#define LAN_CONN 5 /* Connector standard */
7764 +
7765 +
7766 +/* CFTable */
7767 +#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
7768 +#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
7769 +#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
7770 +
7771 +/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
7772 + * take one for HNBU, and use "extensions" (a la FUNCE) within it.
7773 + */
7774 +
7775 +#define CISTPL_BRCM_HNBU 0x80
7776 +
7777 +/* Subtypes of BRCM_HNBU: */
7778 +
7779 +#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */
7780 +#define HNBU_CHIPID 0x01 /* Two 16bit values: PCI vendor & device id */
7781 +#define HNBU_BOARDREV 0x02 /* One byte board revision */
7782 +#define HNBU_PAPARMS 0x03 /* PA parameters: 8 (sromrev == 1)
7783 + * or 9 (sromrev > 1) bytes
7784 + */
7785 +#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */
7786 +#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */
7787 +#define HNBU_AA 0x06 /* Antennas available */
7788 +#define HNBU_AG 0x07 /* Antenna gain */
7789 +#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */
7790 +#define HNBU_LEDS 0x09 /* LED set */
7791 +#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl)
7792 + * in rev 2
7793 + */
7794 +#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
7795 +#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
7796 +#define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */
7797 +
7798 +
7799 +/* sbtmstatelow */
7800 +#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
7801 +#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
7802 +
7803 +/* sbtmstatehigh */
7804 +#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
7805 +
7806 +#endif /* _SBPCMCIA_H */
7807 diff -urN linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
7808 --- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
7809 +++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2006-10-02 21:19:59.000000000 +0200
7810 @@ -0,0 +1,85 @@
7811 +/*
7812 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
7813 + *
7814 + * Copyright 2006, Broadcom Corporation
7815 + * All Rights Reserved.
7816 + *
7817 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7818 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7819 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7820 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7821 + *
7822 + * $Id: sbsdram.h,v 1.1.1.9 2006/03/02 13:03:52 honor Exp $
7823 + */
7824 +
7825 +#ifndef _SBSDRAM_H
7826 +#define _SBSDRAM_H
7827 +
7828 +#ifndef _LANGUAGE_ASSEMBLY
7829 +
7830 +/* Sonics side: SDRAM core registers */
7831 +typedef volatile struct sbsdramregs {
7832 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
7833 + uint32 config; /* Initializes external SDRAM mode register */
7834 + uint32 refresh; /* Controls external SDRAM refresh rate */
7835 + uint32 pad1;
7836 + uint32 pad2;
7837 +} sbsdramregs_t;
7838 +
7839 +/* SDRAM simulation */
7840 +#ifdef RAMSZ
7841 +#define SDRAMSZ RAMSZ
7842 +#else
7843 +#define SDRAMSZ (4 * 1024 * 1024)
7844 +#endif
7845 +
7846 +extern uchar sdrambuf[SDRAMSZ];
7847 +
7848 +#endif /* _LANGUAGE_ASSEMBLY */
7849 +
7850 +/* SDRAM initialization control (initcontrol) register bits */
7851 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
7852 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
7853 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
7854 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
7855 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
7856 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
7857 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
7858 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
7859 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
7860 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
7861 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
7862 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
7863 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
7864 +
7865 +/* SDRAM configuration (config) register bits */
7866 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
7867 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
7868 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
7869 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
7870 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
7871 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
7872 +
7873 +/* SDRAM refresh control (refresh) register bits */
7874 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
7875 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
7876 +
7877 +/* SDRAM Core default Init values (OCP ID 0x803) */
7878 +#define SDRAM_INIT MEM4MX16X2
7879 +#define SDRAM_CONFIG SDRAM_BURSTFULL
7880 +#define SDRAM_REFRESH SDRAM_REF(0x40)
7881 +
7882 +#define MEM1MX16 0x009 /* 2 MB */
7883 +#define MEM1MX16X2 0x409 /* 4 MB */
7884 +#define MEM2MX8X2 0x809 /* 4 MB */
7885 +#define MEM2MX8X4 0xc09 /* 8 MB */
7886 +#define MEM2MX32 0x439 /* 8 MB */
7887 +#define MEM4MX16 0x019 /* 8 MB */
7888 +#define MEM4MX16X2 0x419 /* 16 MB */
7889 +#define MEM8MX8X2 0x819 /* 16 MB */
7890 +#define MEM8MX16 0x829 /* 16 MB */
7891 +#define MEM4MX32 0x429 /* 16 MB */
7892 +#define MEM8MX8X4 0xc19 /* 32 MB */
7893 +#define MEM8MX16X2 0xc29 /* 32 MB */
7894 +
7895 +#endif /* _SBSDRAM_H */
7896 diff -urN linux.old/arch/mips/bcm947xx/include/sbsocram.h linux.dev/arch/mips/bcm947xx/include/sbsocram.h
7897 --- linux.old/arch/mips/bcm947xx/include/sbsocram.h 1970-01-01 01:00:00.000000000 +0100
7898 +++ linux.dev/arch/mips/bcm947xx/include/sbsocram.h 2006-10-02 21:19:59.000000000 +0200
7899 @@ -0,0 +1,64 @@
7900 +/*
7901 + * BCM47XX Sonics SiliconBackplane embedded ram core
7902 + *
7903 + * Copyright 2006, Broadcom Corporation
7904 + * All Rights Reserved.
7905 + *
7906 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7907 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7908 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7909 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7910 + *
7911 + * $Id: sbsocram.h,v 1.1.1.3 2006/02/27 03:43:16 honor Exp $
7912 + */
7913 +
7914 +#ifndef _SBSOCRAM_H
7915 +#define _SBSOCRAM_H
7916 +
7917 +#define SR_COREINFO 0x00
7918 +#define SR_BWALLOC 0x04
7919 +#define SR_BISTSTAT 0x0c
7920 +#define SR_BANKINDEX 0x10
7921 +#define SR_BANKSTBYCTL 0x14
7922 +
7923 +
7924 +#ifndef _LANGUAGE_ASSEMBLY
7925 +
7926 +/* Memcsocram core registers */
7927 +typedef volatile struct sbsocramregs {
7928 + uint32 coreinfo;
7929 + uint32 bwalloc;
7930 + uint32 PAD;
7931 + uint32 biststat;
7932 + uint32 bankidx;
7933 + uint32 standbyctrl;
7934 +} sbsocramregs_t;
7935 +
7936 +#endif
7937 +
7938 +/* Coreinfo register */
7939 +#define SRCI_PT_MASK 0x30000
7940 +#define SRCI_PT_SHIFT 16
7941 +
7942 +/* In corerev 0, the memory size is 2 to the power of the
7943 + * base plus 16 plus to the contents of the memsize field plus 1.
7944 + */
7945 +#define SRCI_MS0_MASK 0xf
7946 +#define SR_MS0_BASE 16
7947 +
7948 +/*
7949 + * In corerev 1 the bank size is 2 ^ the bank size field plus 14,
7950 + * the memory size is number of banks times bank size.
7951 + * The same applies to rom size.
7952 + */
7953 +#define SRCI_ROMNB_MASK 0xf000
7954 +#define SRCI_ROMNB_SHIFT 12
7955 +#define SRCI_ROMBSZ_MASK 0xf00
7956 +#define SRCI_ROMBSZ_SHIFT 8
7957 +#define SRCI_SRNB_MASK 0xf0
7958 +#define SRCI_SRNB_SHIFT 4
7959 +#define SRCI_SRBSZ_MASK 0xf
7960 +#define SRCI_SRBSZ_SHIFT 0
7961 +
7962 +#define SR_BSZ_BASE 14
7963 +#endif /* _SBSOCRAM_H */
7964 diff -urN linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
7965 --- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
7966 +++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2006-10-02 21:19:59.000000000 +0200
7967 @@ -0,0 +1,150 @@
7968 +/*
7969 + * Misc utility routines for accessing chip-specific features
7970 + * of Broadcom HNBU SiliconBackplane-based chips.
7971 + *
7972 + * Copyright 2006, Broadcom Corporation
7973 + * All Rights Reserved.
7974 + *
7975 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7976 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7977 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7978 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7979 + *
7980 + * $Id: sbutils.h,v 1.4 2006/04/08 07:12:42 honor Exp $
7981 + */
7982 +
7983 +#ifndef _sbutils_h_
7984 +#define _sbutils_h_
7985 +
7986 +/*
7987 + * Datastructure to export all chip specific common variables
7988 + * public (read-only) portion of sbutils handle returned by
7989 + * sb_attach()/sb_kattach()
7990 +*/
7991 +
7992 +struct sb_pub {
7993 +
7994 + uint bustype; /* SB_BUS, PCI_BUS */
7995 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE */
7996 + uint buscorerev; /* buscore rev */
7997 + uint buscoreidx; /* buscore index */
7998 + int ccrev; /* chip common core rev */
7999 + uint boardtype; /* board type */
8000 + uint boardvendor; /* board vendor */
8001 + uint chip; /* chip number */
8002 + uint chiprev; /* chip revision */
8003 + uint chippkg; /* chip package option */
8004 + uint sonicsrev; /* sonics backplane rev */
8005 +};
8006 +
8007 +typedef const struct sb_pub sb_t;
8008 +
8009 +/*
8010 + * Many of the routines below take an 'sbh' handle as their first arg.
8011 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
8012 + * At any one time, the sbh is logically focused on one particular sb core
8013 + * (the "current core").
8014 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
8015 + */
8016 +
8017 +#define SB_OSH NULL /* Use for sb_kattach when no osh is available */
8018 +/* exported externs */
8019 +extern sb_t *sb_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
8020 + void *sdh, char **vars, uint *varsz);
8021 +extern sb_t *sb_kattach(void);
8022 +extern void sb_detach(sb_t *sbh);
8023 +extern uint sb_chip(sb_t *sbh);
8024 +extern uint sb_chiprev(sb_t *sbh);
8025 +extern uint sb_chipcrev(sb_t *sbh);
8026 +extern uint sb_chippkg(sb_t *sbh);
8027 +extern uint sb_pcirev(sb_t *sbh);
8028 +extern bool sb_war16165(sb_t *sbh);
8029 +extern uint sb_pcmciarev(sb_t *sbh);
8030 +extern uint sb_boardvendor(sb_t *sbh);
8031 +extern uint sb_boardtype(sb_t *sbh);
8032 +extern uint sb_bus(sb_t *sbh);
8033 +extern uint sb_buscoretype(sb_t *sbh);
8034 +extern uint sb_buscorerev(sb_t *sbh);
8035 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
8036 +extern uint sb_coreid(sb_t *sbh);
8037 +extern uint sb_coreidx(sb_t *sbh);
8038 +extern uint sb_coreunit(sb_t *sbh);
8039 +extern uint sb_corevendor(sb_t *sbh);
8040 +extern uint sb_corerev(sb_t *sbh);
8041 +extern void *sb_osh(sb_t *sbh);
8042 +extern void sb_setosh(sb_t *sbh, osl_t *osh);
8043 +extern void *sb_coreregs(sb_t *sbh);
8044 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
8045 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
8046 +extern bool sb_iscoreup(sb_t *sbh);
8047 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
8048 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
8049 +extern int sb_corebist(sb_t *sbh);
8050 +extern void sb_commit(sb_t *sbh);
8051 +extern uint32 sb_base(uint32 admatch);
8052 +extern uint32 sb_size(uint32 admatch);
8053 +extern void sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits);
8054 +extern void sb_core_tofixup(sb_t *sbh);
8055 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
8056 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
8057 +extern uint32 sb_clock(sb_t *sbh);
8058 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
8059 +extern void sb_pcmcia_init(sb_t *sbh);
8060 +extern void sb_watchdog(sb_t *sbh, uint ticks);
8061 +extern void *sb_gpiosetcore(sb_t *sbh);
8062 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8063 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8064 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8065 +extern uint32 sb_gpioin(sb_t *sbh);
8066 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8067 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8068 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
8069 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
8070 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
8071 +
8072 +extern void sb_clkctl_init(sb_t *sbh);
8073 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
8074 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
8075 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
8076 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
8077 + void *intrsenabled_fn, void *intr_arg);
8078 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
8079 +extern int sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
8080 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
8081 + uint8 *pciheader);
8082 +extern uint sb_pcie_readreg(void *sbh, void* arg1, uint offset);
8083 +extern uint sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val);
8084 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
8085 +extern bool sb_backplane64(sb_t *sbh);
8086 +extern void sb_btcgpiowar(sb_t *sbh);
8087 +
8088 +
8089 +
8090 +
8091 +extern bool sb_deviceremoved(sb_t *sbh);
8092 +extern uint32 sb_socram_size(sb_t *sbh);
8093 +
8094 +/*
8095 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
8096 +* The returned path is NULL terminated and has trailing '/'.
8097 +* Return 0 on success, nonzero otherwise.
8098 +*/
8099 +extern int sb_devpath(sb_t *sbh, char *path, int size);
8100 +
8101 +/* clkctl xtal what flags */
8102 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
8103 +#define PLL 0x2 /* main chip pll */
8104 +
8105 +/* clkctl clk mode */
8106 +#define CLK_FAST 0 /* force fast (pll) clock */
8107 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
8108 +
8109 +
8110 +/* GPIO usage priorities */
8111 +#define GPIO_DRV_PRIORITY 0 /* Driver */
8112 +#define GPIO_APP_PRIORITY 1 /* Application */
8113 +
8114 +/* device path */
8115 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
8116 +
8117 +#endif /* _sbutils_h_ */
8118 diff -urN linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
8119 --- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
8120 +++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2006-10-02 21:19:59.000000000 +0200
8121 @@ -0,0 +1,36 @@
8122 +/*
8123 + * Broadcom SiliconBackplane chipcommon serial flash interface
8124 + *
8125 + * Copyright 2006, Broadcom Corporation
8126 + * All Rights Reserved.
8127 + *
8128 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8129 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8130 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8131 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8132 + *
8133 + * $Id: sflash.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
8134 + */
8135 +
8136 +#ifndef _sflash_h_
8137 +#define _sflash_h_
8138 +
8139 +#include <typedefs.h>
8140 +#include <sbchipc.h>
8141 +
8142 +struct sflash {
8143 + uint blocksize; /* Block size */
8144 + uint numblocks; /* Number of blocks */
8145 + uint32 type; /* Type */
8146 + uint size; /* Total size in bytes */
8147 +};
8148 +
8149 +/* Utility functions */
8150 +extern int sflash_poll(chipcregs_t *cc, uint offset);
8151 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
8152 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8153 +extern int sflash_erase(chipcregs_t *cc, uint offset);
8154 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8155 +extern struct sflash * sflash_init(chipcregs_t *cc);
8156 +
8157 +#endif /* _sflash_h_ */
8158 diff -urN linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
8159 --- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
8160 +++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2006-10-02 21:19:59.000000000 +0200
8161 @@ -0,0 +1,33 @@
8162 +/*
8163 + * TRX image file header format.
8164 + *
8165 + * Copyright 2005, Broadcom Corporation
8166 + * All Rights Reserved.
8167 + *
8168 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8169 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8170 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8171 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8172 + *
8173 + * $Id$
8174 + */
8175 +
8176 +#include <typedefs.h>
8177 +
8178 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
8179 +#define TRX_VERSION 1
8180 +#define TRX_MAX_LEN 0x3A0000
8181 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
8182 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
8183 +#define TRX_MAX_OFFSET 3
8184 +
8185 +struct trx_header {
8186 + uint32 magic; /* "HDR0" */
8187 + uint32 len; /* Length of file including header */
8188 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
8189 + uint32 flag_version; /* 0:15 flags, 16:31 version */
8190 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
8191 +};
8192 +
8193 +/* Compatibility */
8194 +typedef struct trx_header TRXHDR, *PTRXHDR;
8195 diff -urN linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
8196 --- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
8197 +++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2006-10-02 21:19:59.000000000 +0200
8198 @@ -0,0 +1,361 @@
8199 +/*
8200 + * Copyright 2006, Broadcom Corporation
8201 + * All Rights Reserved.
8202 + *
8203 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8204 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8205 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8206 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8207 + * $Id: typedefs.h,v 1.1.1.12 2006/04/08 06:13:40 honor Exp $
8208 + */
8209 +
8210 +#ifndef _TYPEDEFS_H_
8211 +#define _TYPEDEFS_H_
8212 +
8213 +
8214 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
8215 + * typedef file "site_typedefs.h".
8216 + *
8217 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
8218 + * section of this file makes inferences about the compile environment
8219 + * based on defined symbols and possibly compiler pragmas.
8220 + *
8221 + * Following these two sections is the "Default Typedefs"
8222 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
8223 + * defined. This section has a default set of typedefs and a few
8224 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
8225 + */
8226 +
8227 +#ifdef SITE_TYPEDEFS
8228 +
8229 +/*
8230 + * Site Specific Typedefs
8231 + *
8232 + */
8233 +
8234 +#include "site_typedefs.h"
8235 +
8236 +#else
8237 +
8238 +/*
8239 + * Inferred Typedefs
8240 + *
8241 + */
8242 +
8243 +/* Infer the compile environment based on preprocessor symbols and pramas.
8244 + * Override type definitions as needed, and include configuration dependent
8245 + * header files to define types.
8246 + */
8247 +
8248 +#ifdef __cplusplus
8249 +
8250 +#define TYPEDEF_BOOL
8251 +#ifndef FALSE
8252 +#define FALSE false
8253 +#endif
8254 +#ifndef TRUE
8255 +#define TRUE true
8256 +#endif
8257 +
8258 +#else /* ! __cplusplus */
8259 +
8260 +#if defined(_WIN32)
8261 +
8262 +#define TYPEDEF_BOOL
8263 +typedef unsigned char bool; /* consistent w/BOOL */
8264 +
8265 +#endif /* _WIN32 */
8266 +
8267 +#endif /* ! __cplusplus */
8268 +
8269 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
8270 +#if defined(_WIN64)
8271 +#include <basetsd.h>
8272 +#define TYPEDEF_UINTPTR
8273 +typedef ULONG_PTR uintptr;
8274 +#endif
8275 +
8276 +
8277 +#if defined(_MINOSL_)
8278 +#define _NEED_SIZE_T_
8279 +#endif
8280 +
8281 +#if defined(_NEED_SIZE_T_)
8282 +typedef long unsigned int size_t;
8283 +#endif
8284 +
8285 +#ifdef __DJGPP__
8286 +typedef long unsigned int size_t;
8287 +#endif /* __DJGPP__ */
8288 +
8289 +#ifdef _MSC_VER /* Microsoft C */
8290 +#define TYPEDEF_INT64
8291 +#define TYPEDEF_UINT64
8292 +typedef signed __int64 int64;
8293 +typedef unsigned __int64 uint64;
8294 +#endif
8295 +
8296 +#if defined(MACOSX)
8297 +#define TYPEDEF_BOOL
8298 +#endif
8299 +
8300 +#if defined(__NetBSD__)
8301 +#define TYPEDEF_ULONG
8302 +#endif
8303 +
8304 +
8305 +#if defined(linux)
8306 +#define TYPEDEF_UINT
8307 +#define TYPEDEF_USHORT
8308 +#define TYPEDEF_ULONG
8309 +#endif
8310 +
8311 +#if !defined(linux) && !defined(_WIN32) && !defined(_CFE_) && \
8312 + !defined(_HNDRTE_) && !defined(_MINOSL_) && !defined(__DJGPP__)
8313 +#define TYPEDEF_UINT
8314 +#define TYPEDEF_USHORT
8315 +#endif
8316 +
8317 +
8318 +/* Do not support the (u)int64 types with strict ansi for GNU C */
8319 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
8320 +#define TYPEDEF_INT64
8321 +#define TYPEDEF_UINT64
8322 +#endif
8323 +
8324 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
8325 + * for singned or unsigned
8326 + */
8327 +#if defined(__ICL)
8328 +
8329 +#define TYPEDEF_INT64
8330 +
8331 +#if defined(__STDC__)
8332 +#define TYPEDEF_UINT64
8333 +#endif
8334 +
8335 +#endif /* __ICL */
8336 +
8337 +#if !defined(_WIN32) && !defined(_CFE_) && !defined(_MINOSL_) && \
8338 + !defined(__DJGPP__)
8339 +
8340 +/* pick up ushort & uint from standard types.h */
8341 +#if defined(linux) && defined(__KERNEL__)
8342 +
8343 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
8344 +
8345 +#else
8346 +
8347 +#include <sys/types.h>
8348 +
8349 +#endif
8350 +
8351 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ && !__DJGPP__ */
8352 +
8353 +#if defined(MACOSX)
8354 +
8355 +#ifdef __BIG_ENDIAN__
8356 +#define IL_BIGENDIAN
8357 +#else
8358 +#ifdef IL_BIGENDIAN
8359 +#error "IL_BIGENDIAN was defined for a little-endian compile"
8360 +#endif
8361 +#endif /* __BIG_ENDIAN__ */
8362 +
8363 +#if !defined(__cplusplus)
8364 +
8365 +#if defined(__i386__)
8366 +typedef unsigned char bool;
8367 +#else
8368 +typedef unsigned int bool;
8369 +#endif
8370 +#define TYPE_BOOL 1
8371 +enum {
8372 + false = 0,
8373 + true = 1
8374 +};
8375 +
8376 +#if defined(KERNEL)
8377 +#include <IOKit/IOTypes.h>
8378 +#endif /* KERNEL */
8379 +
8380 +#endif /* __cplusplus */
8381 +
8382 +#endif /* MACOSX */
8383 +
8384 +
8385 +/* use the default typedefs in the next section of this file */
8386 +#define USE_TYPEDEF_DEFAULTS
8387 +
8388 +#endif /* SITE_TYPEDEFS */
8389 +
8390 +
8391 +/*
8392 + * Default Typedefs
8393 + *
8394 + */
8395 +
8396 +#ifdef USE_TYPEDEF_DEFAULTS
8397 +#undef USE_TYPEDEF_DEFAULTS
8398 +
8399 +#ifndef TYPEDEF_BOOL
8400 +typedef /* @abstract@ */ unsigned char bool;
8401 +#endif
8402 +
8403 +/* define uchar, ushort, uint, ulong */
8404 +
8405 +#ifndef TYPEDEF_UCHAR
8406 +typedef unsigned char uchar;
8407 +#endif
8408 +
8409 +#ifndef TYPEDEF_USHORT
8410 +typedef unsigned short ushort;
8411 +#endif
8412 +
8413 +#ifndef TYPEDEF_UINT
8414 +typedef unsigned int uint;
8415 +#endif
8416 +
8417 +#ifndef TYPEDEF_ULONG
8418 +typedef unsigned long ulong;
8419 +#endif
8420 +
8421 +/* define [u]int8/16/32/64, uintptr */
8422 +
8423 +#ifndef TYPEDEF_UINT8
8424 +typedef unsigned char uint8;
8425 +#endif
8426 +
8427 +#ifndef TYPEDEF_UINT16
8428 +typedef unsigned short uint16;
8429 +#endif
8430 +
8431 +#ifndef TYPEDEF_UINT32
8432 +typedef unsigned int uint32;
8433 +#endif
8434 +
8435 +#ifndef TYPEDEF_UINT64
8436 +typedef unsigned long long uint64;
8437 +#endif
8438 +
8439 +#ifndef TYPEDEF_UINTPTR
8440 +typedef unsigned int uintptr;
8441 +#endif
8442 +
8443 +#ifndef TYPEDEF_INT8
8444 +typedef signed char int8;
8445 +#endif
8446 +
8447 +#ifndef TYPEDEF_INT16
8448 +typedef signed short int16;
8449 +#endif
8450 +
8451 +#ifndef TYPEDEF_INT32
8452 +typedef signed int int32;
8453 +#endif
8454 +
8455 +#ifndef TYPEDEF_INT64
8456 +typedef signed long long int64;
8457 +#endif
8458 +
8459 +/* define float32/64, float_t */
8460 +
8461 +#ifndef TYPEDEF_FLOAT32
8462 +typedef float float32;
8463 +#endif
8464 +
8465 +#ifndef TYPEDEF_FLOAT64
8466 +typedef double float64;
8467 +#endif
8468 +
8469 +/*
8470 + * abstracted floating point type allows for compile time selection of
8471 + * single or double precision arithmetic. Compiling with -DFLOAT32
8472 + * selects single precision; the default is double precision.
8473 + */
8474 +
8475 +#ifndef TYPEDEF_FLOAT_T
8476 +
8477 +#if defined(FLOAT32)
8478 +typedef float32 float_t;
8479 +#else /* default to double precision floating point */
8480 +typedef float64 float_t;
8481 +#endif
8482 +
8483 +#endif /* TYPEDEF_FLOAT_T */
8484 +
8485 +/* define macro values */
8486 +
8487 +#ifndef FALSE
8488 +#define FALSE 0
8489 +#endif
8490 +
8491 +#ifndef TRUE
8492 +#define TRUE 1 /* TRUE */
8493 +#endif
8494 +
8495 +#ifndef NULL
8496 +#define NULL 0
8497 +#endif
8498 +
8499 +#ifndef OFF
8500 +#define OFF 0
8501 +#endif
8502 +
8503 +#ifndef ON
8504 +#define ON 1 /* ON = 1 */
8505 +#endif
8506 +
8507 +#define AUTO (-1) /* Auto = -1 */
8508 +
8509 +/* define PTRSZ, INLINE */
8510 +
8511 +#ifndef PTRSZ
8512 +#define PTRSZ sizeof(char*)
8513 +#endif
8514 +
8515 +#ifndef INLINE
8516 +
8517 +#ifdef _MSC_VER
8518 +
8519 +#define INLINE __inline
8520 +
8521 +#elif __GNUC__
8522 +
8523 +#define INLINE __inline__
8524 +
8525 +#else
8526 +
8527 +#define INLINE
8528 +
8529 +#endif /* _MSC_VER */
8530 +
8531 +#endif /* INLINE */
8532 +
8533 +#undef TYPEDEF_BOOL
8534 +#undef TYPEDEF_UCHAR
8535 +#undef TYPEDEF_USHORT
8536 +#undef TYPEDEF_UINT
8537 +#undef TYPEDEF_ULONG
8538 +#undef TYPEDEF_UINT8
8539 +#undef TYPEDEF_UINT16
8540 +#undef TYPEDEF_UINT32
8541 +#undef TYPEDEF_UINT64
8542 +#undef TYPEDEF_UINTPTR
8543 +#undef TYPEDEF_INT8
8544 +#undef TYPEDEF_INT16
8545 +#undef TYPEDEF_INT32
8546 +#undef TYPEDEF_INT64
8547 +#undef TYPEDEF_FLOAT32
8548 +#undef TYPEDEF_FLOAT64
8549 +#undef TYPEDEF_FLOAT_T
8550 +
8551 +#endif /* USE_TYPEDEF_DEFAULTS */
8552 +
8553 +/*
8554 + * Including the bcmdefs.h here, to make sure everyone including typedefs.h
8555 + * gets this automatically
8556 +*/
8557 +#include "bcmdefs.h"
8558 +
8559 +#endif /* _TYPEDEFS_H_ */
8560 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
8561 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
8562 +++ linux.dev/arch/mips/bcm947xx/Makefile 2006-10-02 21:26:08.000000000 +0200
8563 @@ -0,0 +1,17 @@
8564 +#
8565 +# Makefile for the BCM947xx specific kernel interface routines
8566 +# under Linux.
8567 +#
8568 +
8569 +EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER -fno-delayed-branch
8570 +
8571 +O_TARGET := bcm947xx.o
8572 +
8573 +export-objs := export.o
8574 +obj-y := prom.o setup.o time.o sbmips.o gpio.o
8575 +obj-y += nvram.o nvram_linux.o sflash.o cfe_env.o
8576 +obj-y += sbutils.o bcmutils.o bcmsrom.o hndchipc.o
8577 +obj-$(CONFIG_PCI) += sbpci.o pcibios.o
8578 +obj-y += export.o
8579 +
8580 +include $(TOPDIR)/Rules.make
8581 diff -urN linux.old/arch/mips/bcm947xx/nvram.c linux.dev/arch/mips/bcm947xx/nvram.c
8582 --- linux.old/arch/mips/bcm947xx/nvram.c 1970-01-01 01:00:00.000000000 +0100
8583 +++ linux.dev/arch/mips/bcm947xx/nvram.c 2006-10-02 21:19:59.000000000 +0200
8584 @@ -0,0 +1,315 @@
8585 +/*
8586 + * NVRAM variable manipulation (common)
8587 + *
8588 + * Copyright 2004, Broadcom Corporation
8589 + * All Rights Reserved.
8590 + *
8591 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8592 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8593 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8594 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8595 + *
8596 + */
8597 +
8598 +#include <typedefs.h>
8599 +#include <osl.h>
8600 +#include <bcmendian.h>
8601 +#include <bcmnvram.h>
8602 +#include <bcmutils.h>
8603 +#include <sbsdram.h>
8604 +
8605 +extern struct nvram_tuple * BCMINIT(_nvram_realloc)(struct nvram_tuple *t, const char *name, const char *value);
8606 +extern void BCMINIT(_nvram_free)(struct nvram_tuple *t);
8607 +extern int BCMINIT(_nvram_read)(void *buf);
8608 +
8609 +char * BCMINIT(_nvram_get)(const char *name);
8610 +int BCMINIT(_nvram_set)(const char *name, const char *value);
8611 +int BCMINIT(_nvram_unset)(const char *name);
8612 +int BCMINIT(_nvram_getall)(char *buf, int count);
8613 +int BCMINIT(_nvram_commit)(struct nvram_header *header);
8614 +int BCMINIT(_nvram_init)(void);
8615 +void BCMINIT(_nvram_exit)(void);
8616 +
8617 +static struct nvram_tuple * BCMINITDATA(nvram_hash)[257];
8618 +static struct nvram_tuple * nvram_dead;
8619 +
8620 +/* Free all tuples. Should be locked. */
8621 +static void
8622 +BCMINITFN(nvram_free)(void)
8623 +{
8624 + uint i;
8625 + struct nvram_tuple *t, *next;
8626 +
8627 + /* Free hash table */
8628 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8629 + for (t = BCMINIT(nvram_hash)[i]; t; t = next) {
8630 + next = t->next;
8631 + BCMINIT(_nvram_free)(t);
8632 + }
8633 + BCMINIT(nvram_hash)[i] = NULL;
8634 + }
8635 +
8636 + /* Free dead table */
8637 + for (t = nvram_dead; t; t = next) {
8638 + next = t->next;
8639 + BCMINIT(_nvram_free)(t);
8640 + }
8641 + nvram_dead = NULL;
8642 +
8643 + /* Indicate to per-port code that all tuples have been freed */
8644 + BCMINIT(_nvram_free)(NULL);
8645 +}
8646 +
8647 +/* String hash */
8648 +static INLINE uint
8649 +hash(const char *s)
8650 +{
8651 + uint hash = 0;
8652 +
8653 + while (*s)
8654 + hash = 31 * hash + *s++;
8655 +
8656 + return hash;
8657 +}
8658 +
8659 +/* (Re)initialize the hash table. Should be locked. */
8660 +static int
8661 +BCMINITFN(nvram_rehash)(struct nvram_header *header)
8662 +{
8663 + char buf[] = "0xXXXXXXXX", *name, *value, *end, *eq;
8664 +
8665 + /* (Re)initialize hash table */
8666 + BCMINIT(nvram_free)();
8667 +
8668 + /* Parse and set "name=value\0 ... \0\0" */
8669 + name = (char *) &header[1];
8670 + end = (char *) header + NVRAM_SPACE - 2;
8671 + end[0] = end[1] = '\0';
8672 + for (; *name; name = value + strlen(value) + 1) {
8673 + if (!(eq = strchr(name, '=')))
8674 + break;
8675 + *eq = '\0';
8676 + value = eq + 1;
8677 + BCMINIT(_nvram_set)(name, value);
8678 + *eq = '=';
8679 + }
8680 +
8681 + /* Set special SDRAM parameters */
8682 + if (!BCMINIT(_nvram_get)("sdram_init")) {
8683 + sprintf(buf, "0x%04X", (uint16)(header->crc_ver_init >> 16));
8684 + BCMINIT(_nvram_set)("sdram_init", buf);
8685 + }
8686 + if (!BCMINIT(_nvram_get)("sdram_config")) {
8687 + sprintf(buf, "0x%04X", (uint16)(header->config_refresh & 0xffff));
8688 + BCMINIT(_nvram_set)("sdram_config", buf);
8689 + }
8690 + if (!BCMINIT(_nvram_get)("sdram_refresh")) {
8691 + sprintf(buf, "0x%04X", (uint16)((header->config_refresh >> 16) & 0xffff));
8692 + BCMINIT(_nvram_set)("sdram_refresh", buf);
8693 + }
8694 + if (!BCMINIT(_nvram_get)("sdram_ncdl")) {
8695 + sprintf(buf, "0x%08X", header->config_ncdl);
8696 + BCMINIT(_nvram_set)("sdram_ncdl", buf);
8697 + }
8698 +
8699 + return 0;
8700 +}
8701 +
8702 +/* Get the value of an NVRAM variable. Should be locked. */
8703 +char *
8704 +BCMINITFN(_nvram_get)(const char *name)
8705 +{
8706 + uint i;
8707 + struct nvram_tuple *t;
8708 + char *value;
8709 +
8710 + if (!name)
8711 + return NULL;
8712 +
8713 + /* Hash the name */
8714 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8715 +
8716 + /* Find the associated tuple in the hash table */
8717 + for (t = BCMINIT(nvram_hash)[i]; t && strcmp(t->name, name); t = t->next);
8718 +
8719 + value = t ? t->value : NULL;
8720 +
8721 + return value;
8722 +}
8723 +
8724 +/* Get the value of an NVRAM variable. Should be locked. */
8725 +int
8726 +BCMINITFN(_nvram_set)(const char *name, const char *value)
8727 +{
8728 + uint i;
8729 + struct nvram_tuple *t, *u, **prev;
8730 +
8731 + /* Hash the name */
8732 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8733 +
8734 + /* Find the associated tuple in the hash table */
8735 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
8736 +
8737 + /* (Re)allocate tuple */
8738 + if (!(u = BCMINIT(_nvram_realloc)(t, name, value)))
8739 + return -12; /* -ENOMEM */
8740 +
8741 + /* Value reallocated */
8742 + if (t && t == u)
8743 + return 0;
8744 +
8745 + /* Move old tuple to the dead table */
8746 + if (t) {
8747 + *prev = t->next;
8748 + t->next = nvram_dead;
8749 + nvram_dead = t;
8750 + }
8751 +
8752 + /* Add new tuple to the hash table */
8753 + u->next = BCMINIT(nvram_hash)[i];
8754 + BCMINIT(nvram_hash)[i] = u;
8755 +
8756 + return 0;
8757 +}
8758 +
8759 +/* Unset the value of an NVRAM variable. Should be locked. */
8760 +int
8761 +BCMINITFN(_nvram_unset)(const char *name)
8762 +{
8763 + uint i;
8764 + struct nvram_tuple *t, **prev;
8765 +
8766 + if (!name)
8767 + return 0;
8768 +
8769 + /* Hash the name */
8770 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8771 +
8772 + /* Find the associated tuple in the hash table */
8773 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
8774 +
8775 + /* Move it to the dead table */
8776 + if (t) {
8777 + *prev = t->next;
8778 + t->next = nvram_dead;
8779 + nvram_dead = t;
8780 + }
8781 +
8782 + return 0;
8783 +}
8784 +
8785 +/* Get all NVRAM variables. Should be locked. */
8786 +int
8787 +BCMINITFN(_nvram_getall)(char *buf, int count)
8788 +{
8789 + uint i;
8790 + struct nvram_tuple *t;
8791 + int len = 0;
8792 +
8793 + bzero(buf, count);
8794 +
8795 + /* Write name=value\0 ... \0\0 */
8796 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8797 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
8798 + if ((count - len) > (strlen(t->name) + 1 + strlen(t->value) + 1))
8799 + len += sprintf(buf + len, "%s=%s", t->name, t->value) + 1;
8800 + else
8801 + break;
8802 + }
8803 + }
8804 +
8805 + return 0;
8806 +}
8807 +
8808 +/* Regenerate NVRAM. Should be locked. */
8809 +int
8810 +BCMINITFN(_nvram_commit)(struct nvram_header *header)
8811 +{
8812 + char *init, *config, *refresh, *ncdl;
8813 + char *ptr, *end;
8814 + int i;
8815 + struct nvram_tuple *t;
8816 + struct nvram_header tmp;
8817 + uint8 crc;
8818 +
8819 + /* Regenerate header */
8820 + header->magic = NVRAM_MAGIC;
8821 + header->crc_ver_init = (NVRAM_VERSION << 8);
8822 + if (!(init = BCMINIT(_nvram_get)("sdram_init")) ||
8823 + !(config = BCMINIT(_nvram_get)("sdram_config")) ||
8824 + !(refresh = BCMINIT(_nvram_get)("sdram_refresh")) ||
8825 + !(ncdl = BCMINIT(_nvram_get)("sdram_ncdl"))) {
8826 + header->crc_ver_init |= SDRAM_INIT << 16;
8827 + header->config_refresh = SDRAM_CONFIG;
8828 + header->config_refresh |= SDRAM_REFRESH << 16;
8829 + header->config_ncdl = 0;
8830 + } else {
8831 + header->crc_ver_init |= (bcm_strtoul(init, NULL, 0) & 0xffff) << 16;
8832 + header->config_refresh = bcm_strtoul(config, NULL, 0) & 0xffff;
8833 + header->config_refresh |= (bcm_strtoul(refresh, NULL, 0) & 0xffff) << 16;
8834 + header->config_ncdl = bcm_strtoul(ncdl, NULL, 0);
8835 + }
8836 +
8837 + /* Clear data area */
8838 + ptr = (char *) header + sizeof(struct nvram_header);
8839 + bzero(ptr, NVRAM_SPACE - sizeof(struct nvram_header));
8840 +
8841 + /* Leave space for a double NUL at the end */
8842 + end = (char *) header + NVRAM_SPACE - 2;
8843 +
8844 + /* Write out all tuples */
8845 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8846 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
8847 + if ((ptr + strlen(t->name) + 1 + strlen(t->value) + 1) > end)
8848 + break;
8849 + ptr += sprintf(ptr, "%s=%s", t->name, t->value) + 1;
8850 + }
8851 + }
8852 +
8853 + /* End with a double NUL */
8854 + ptr += 2;
8855 +
8856 + /* Set new length */
8857 + header->len = ROUNDUP(ptr - (char *) header, 4);
8858 +
8859 + /* Little-endian CRC8 over the last 11 bytes of the header */
8860 + tmp.crc_ver_init = htol32(header->crc_ver_init);
8861 + tmp.config_refresh = htol32(header->config_refresh);
8862 + tmp.config_ncdl = htol32(header->config_ncdl);
8863 + crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, CRC8_INIT_VALUE);
8864 +
8865 + /* Continue CRC8 over data bytes */
8866 + crc = hndcrc8((char *) &header[1], header->len - sizeof(struct nvram_header), crc);
8867 +
8868 + /* Set new CRC8 */
8869 + header->crc_ver_init |= crc;
8870 +
8871 + /* Reinitialize hash table */
8872 + return BCMINIT(nvram_rehash)(header);
8873 +}
8874 +
8875 +/* Initialize hash table. Should be locked. */
8876 +int
8877 +BCMINITFN(_nvram_init)(void)
8878 +{
8879 + struct nvram_header *header;
8880 + int ret;
8881 +
8882 + if (!(header = (struct nvram_header *) kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
8883 + return -12; /* -ENOMEM */
8884 + }
8885 +
8886 + if ((ret = BCMINIT(_nvram_read)(header)) == 0 &&
8887 + header->magic == NVRAM_MAGIC)
8888 + BCMINIT(nvram_rehash)(header);
8889 +
8890 + kfree(header);
8891 + return ret;
8892 +}
8893 +
8894 +/* Free hash table. Should be locked. */
8895 +void
8896 +BCMINITFN(_nvram_exit)(void)
8897 +{
8898 + BCMINIT(nvram_free)();
8899 +}
8900 diff -urN linux.old/arch/mips/bcm947xx/nvram_linux.c linux.dev/arch/mips/bcm947xx/nvram_linux.c
8901 --- linux.old/arch/mips/bcm947xx/nvram_linux.c 1970-01-01 01:00:00.000000000 +0100
8902 +++ linux.dev/arch/mips/bcm947xx/nvram_linux.c 2006-10-02 21:19:59.000000000 +0200
8903 @@ -0,0 +1,723 @@
8904 +/*
8905 + * NVRAM variable manipulation (Linux kernel half)
8906 + *
8907 + * Copyright 2006, Broadcom Corporation
8908 + * All Rights Reserved.
8909 + *
8910 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8911 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8912 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8913 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8914 + *
8915 + * $Id: nvram_linux.c,v 1.19 2006/04/08 07:12:42 honor Exp $
8916 + */
8917 +
8918 +#include <linux/config.h>
8919 +#include <linux/init.h>
8920 +#include <linux/module.h>
8921 +#include <linux/kernel.h>
8922 +#include <linux/string.h>
8923 +#include <linux/interrupt.h>
8924 +#include <linux/spinlock.h>
8925 +#include <linux/slab.h>
8926 +#include <linux/bootmem.h>
8927 +#include <linux/wrapper.h>
8928 +#include <linux/fs.h>
8929 +#include <linux/miscdevice.h>
8930 +#include <linux/mtd/mtd.h>
8931 +#include <asm/addrspace.h>
8932 +#include <asm/io.h>
8933 +#include <asm/uaccess.h>
8934 +
8935 +#include <typedefs.h>
8936 +#include <osl.h>
8937 +#include <bcmendian.h>
8938 +#include <bcmnvram.h>
8939 +#include <bcmutils.h>
8940 +#include <sbconfig.h>
8941 +#include <sbchipc.h>
8942 +#include <sbutils.h>
8943 +#include <hndmips.h>
8944 +#include <sflash.h>
8945 +
8946 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
8947 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
8948 +
8949 +#ifdef MODULE
8950 +
8951 +#define early_nvram_get(name) nvram_get(name)
8952 +
8953 +#else /* !MODULE */
8954 +
8955 +/* Global SB handle */
8956 +extern void *bcm947xx_sbh;
8957 +extern spinlock_t bcm947xx_sbh_lock;
8958 +
8959 +static int cfe_env;
8960 +extern char *cfe_env_get(char *nv_buf, const char *name);
8961 +
8962 +/* Convenience */
8963 +#define sbh bcm947xx_sbh
8964 +#define sbh_lock bcm947xx_sbh_lock
8965 +#define KB * 1024
8966 +#define MB * 1024 * 1024
8967 +
8968 +/* Probe for NVRAM header */
8969 +static void __init
8970 +early_nvram_init(void)
8971 +{
8972 + struct nvram_header *header;
8973 + chipcregs_t *cc;
8974 + struct sflash *info = NULL;
8975 + int i;
8976 + uint32 base, off, lim;
8977 + u32 *src, *dst;
8978 +
8979 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
8980 + base = KSEG1ADDR(SB_FLASH2);
8981 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
8982 + case PFLASH:
8983 + lim = SB_FLASH2_SZ;
8984 + break;
8985 +
8986 + case SFLASH_ST:
8987 + case SFLASH_AT:
8988 + if ((info = sflash_init(cc)) == NULL)
8989 + return;
8990 + lim = info->size;
8991 + break;
8992 +
8993 + case FLASH_NONE:
8994 + default:
8995 + return;
8996 + }
8997 + } else {
8998 + /* extif assumed, Stop at 4 MB */
8999 + base = KSEG1ADDR(SB_FLASH1);
9000 + lim = SB_FLASH1_SZ;
9001 + }
9002 +
9003 + /* XXX: hack for supporting the CFE environment stuff on WGT634U */
9004 + src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
9005 + dst = (u32 *) nvram_buf;
9006 + if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) {
9007 + printk("early_nvram_init: WGT634U NVRAM found.\n");
9008 +
9009 + for (i = 0; i < 0x1ff0; i++) {
9010 + if (*src == 0xFFFFFFFF)
9011 + break;
9012 + *dst++ = *src++;
9013 + }
9014 + cfe_env = 1;
9015 + return;
9016 + }
9017 +
9018 + off = FLASH_MIN;
9019 + while (off <= lim) {
9020 + /* Windowed flash access */
9021 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
9022 + if (header->magic == NVRAM_MAGIC)
9023 + goto found;
9024 + off <<= 1;
9025 + }
9026 +
9027 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
9028 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
9029 + if (header->magic == NVRAM_MAGIC)
9030 + goto found;
9031 +
9032 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
9033 + if (header->magic == NVRAM_MAGIC)
9034 + goto found;
9035 +
9036 + printk("early_nvram_init: NVRAM not found\n");
9037 + return;
9038 +
9039 +found:
9040 + src = (u32 *) header;
9041 + dst = (u32 *) nvram_buf;
9042 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
9043 + *dst++ = *src++;
9044 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
9045 + *dst++ = ltoh32(*src++);
9046 +}
9047 +
9048 +/* Early (before mm or mtd) read-only access to NVRAM */
9049 +static char * __init
9050 +early_nvram_get(const char *name)
9051 +{
9052 + char *var, *value, *end, *eq;
9053 +
9054 + if (!name)
9055 + return NULL;
9056 +
9057 + /* Too early? */
9058 + if (sbh == NULL)
9059 + return NULL;
9060 +
9061 + if (!nvram_buf[0])
9062 + early_nvram_init();
9063 +
9064 + if (cfe_env)
9065 + return cfe_env_get(nvram_buf, name);
9066 +
9067 + /* Look for name=value and return value */
9068 + var = &nvram_buf[sizeof(struct nvram_header)];
9069 + end = nvram_buf + sizeof(nvram_buf) - 2;
9070 + end[0] = end[1] = '\0';
9071 + for (; *var; var = value + strlen(value) + 1) {
9072 + if (!(eq = strchr(var, '=')))
9073 + break;
9074 + value = eq + 1;
9075 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
9076 + return value;
9077 + }
9078 +
9079 + return NULL;
9080 +}
9081 +
9082 +static int __init
9083 +early_nvram_getall(char *buf, int count)
9084 +{
9085 + char *var, *end;
9086 + int len = 0;
9087 +
9088 + /* Too early? */
9089 + if (sbh == NULL)
9090 + return -1;
9091 +
9092 + if (!nvram_buf[0])
9093 + early_nvram_init();
9094 +
9095 + bzero(buf, count);
9096 +
9097 + /* Write name=value\0 ... \0\0 */
9098 + var = &nvram_buf[sizeof(struct nvram_header)];
9099 + end = nvram_buf + sizeof(nvram_buf) - 2;
9100 + end[0] = end[1] = '\0';
9101 + for (; *var; var += strlen(var) + 1) {
9102 + if ((count - len) <= (strlen(var) + 1))
9103 + break;
9104 + len += sprintf(buf + len, "%s", var) + 1;
9105 + }
9106 +
9107 + return 0;
9108 +}
9109 +#endif /* !MODULE */
9110 +
9111 +extern char * _nvram_get(const char *name);
9112 +extern int _nvram_set(const char *name, const char *value);
9113 +extern int _nvram_unset(const char *name);
9114 +extern int _nvram_getall(char *buf, int count);
9115 +extern int _nvram_commit(struct nvram_header *header);
9116 +extern int _nvram_init(void *sbh);
9117 +extern void _nvram_exit(void);
9118 +
9119 +/* Globals */
9120 +static spinlock_t nvram_lock = SPIN_LOCK_UNLOCKED;
9121 +static struct semaphore nvram_sem;
9122 +static unsigned long nvram_offset = 0;
9123 +static int nvram_major = -1;
9124 +static devfs_handle_t nvram_handle = NULL;
9125 +static struct mtd_info *nvram_mtd = NULL;
9126 +
9127 +int
9128 +_nvram_read(char *buf)
9129 +{
9130 + struct nvram_header *header = (struct nvram_header *) buf;
9131 + size_t len;
9132 +
9133 + if (!nvram_mtd ||
9134 + MTD_READ(nvram_mtd, nvram_mtd->size - NVRAM_SPACE, NVRAM_SPACE, &len, buf) ||
9135 + len != NVRAM_SPACE ||
9136 + header->magic != NVRAM_MAGIC) {
9137 + /* Maybe we can recover some data from early initialization */
9138 + memcpy(buf, nvram_buf, NVRAM_SPACE);
9139 + }
9140 +
9141 + return 0;
9142 +}
9143 +
9144 +struct nvram_tuple *
9145 +_nvram_realloc(struct nvram_tuple *t, const char *name, const char *value)
9146 +{
9147 + if ((nvram_offset + strlen(value) + 1) > NVRAM_SPACE)
9148 + return NULL;
9149 +
9150 + if (!t) {
9151 + if (!(t = kmalloc(sizeof(struct nvram_tuple) + strlen(name) + 1, GFP_ATOMIC)))
9152 + return NULL;
9153 +
9154 + /* Copy name */
9155 + t->name = (char *) &t[1];
9156 + strcpy(t->name, name);
9157 +
9158 + t->value = NULL;
9159 + }
9160 +
9161 + /* Copy value */
9162 + if (!t->value || strcmp(t->value, value)) {
9163 + t->value = &nvram_buf[nvram_offset];
9164 + strcpy(t->value, value);
9165 + nvram_offset += strlen(value) + 1;
9166 + }
9167 +
9168 + return t;
9169 +}
9170 +
9171 +void
9172 +_nvram_free(struct nvram_tuple *t)
9173 +{
9174 + if (!t)
9175 + nvram_offset = 0;
9176 + else
9177 + kfree(t);
9178 +}
9179 +
9180 +int
9181 +nvram_set(const char *name, const char *value)
9182 +{
9183 + unsigned long flags;
9184 + int ret;
9185 + struct nvram_header *header;
9186 +
9187 + spin_lock_irqsave(&nvram_lock, flags);
9188 + if ((ret = _nvram_set(name, value))) {
9189 + /* Consolidate space and try again */
9190 + if ((header = kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
9191 + if (_nvram_commit(header) == 0)
9192 + ret = _nvram_set(name, value);
9193 + kfree(header);
9194 + }
9195 + }
9196 + spin_unlock_irqrestore(&nvram_lock, flags);
9197 +
9198 + return ret;
9199 +}
9200 +
9201 +char *
9202 +real_nvram_get(const char *name)
9203 +{
9204 + unsigned long flags;
9205 + char *value;
9206 +
9207 + spin_lock_irqsave(&nvram_lock, flags);
9208 + value = _nvram_get(name);
9209 + spin_unlock_irqrestore(&nvram_lock, flags);
9210 +
9211 + return value;
9212 +}
9213 +
9214 +char *
9215 +nvram_get(const char *name)
9216 +{
9217 + if (nvram_major >= 0)
9218 + return real_nvram_get(name);
9219 + else
9220 + return early_nvram_get(name);
9221 +}
9222 +
9223 +int
9224 +nvram_unset(const char *name)
9225 +{
9226 + unsigned long flags;
9227 + int ret;
9228 +
9229 + spin_lock_irqsave(&nvram_lock, flags);
9230 + ret = _nvram_unset(name);
9231 + spin_unlock_irqrestore(&nvram_lock, flags);
9232 +
9233 + return ret;
9234 +}
9235 +
9236 +static void
9237 +erase_callback(struct erase_info *done)
9238 +{
9239 + wait_queue_head_t *wait_q = (wait_queue_head_t *) done->priv;
9240 + wake_up(wait_q);
9241 +}
9242 +
9243 +int
9244 +nvram_commit(void)
9245 +{
9246 + char *buf;
9247 + size_t erasesize, len, magic_len;
9248 + unsigned int i;
9249 + int ret;
9250 + struct nvram_header *header;
9251 + unsigned long flags;
9252 + u_int32_t offset;
9253 + DECLARE_WAITQUEUE(wait, current);
9254 + wait_queue_head_t wait_q;
9255 + struct erase_info erase;
9256 + u_int32_t magic_offset = 0; /* Offset for writing MAGIC # */
9257 +
9258 + if (!nvram_mtd) {
9259 + printk("nvram_commit: NVRAM not found\n");
9260 + return -ENODEV;
9261 + }
9262 +
9263 + if (in_interrupt()) {
9264 + printk("nvram_commit: not committing in interrupt\n");
9265 + return -EINVAL;
9266 + }
9267 +
9268 + /* Backup sector blocks to be erased */
9269 + erasesize = ROUNDUP(NVRAM_SPACE, nvram_mtd->erasesize);
9270 + if (!(buf = kmalloc(erasesize, GFP_KERNEL))) {
9271 + printk("nvram_commit: out of memory\n");
9272 + return -ENOMEM;
9273 + }
9274 +
9275 + down(&nvram_sem);
9276 +
9277 + if ((i = erasesize - NVRAM_SPACE) > 0) {
9278 + offset = nvram_mtd->size - erasesize;
9279 + len = 0;
9280 + ret = MTD_READ(nvram_mtd, offset, i, &len, buf);
9281 + if (ret || len != i) {
9282 + printk("nvram_commit: read error ret = %d, len = %d/%d\n", ret, len, i);
9283 + ret = -EIO;
9284 + goto done;
9285 + }
9286 + header = (struct nvram_header *)(buf + i);
9287 + magic_offset = i + ((void *)&header->magic - (void *)header);
9288 + } else {
9289 + offset = nvram_mtd->size - NVRAM_SPACE;
9290 + magic_offset = ((void *)&header->magic - (void *)header);
9291 + header = (struct nvram_header *)buf;
9292 + }
9293 +
9294 + /* clear the existing magic # to mark the NVRAM as unusable
9295 + we can pull MAGIC bits low without erase */
9296 + header->magic = NVRAM_CLEAR_MAGIC; /* All zeros magic */
9297 +
9298 + /* Unlock sector blocks (for Intel 28F320C3B flash) , 20060309 */
9299 + if(nvram_mtd->unlock)
9300 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
9301 +
9302 + ret = MTD_WRITE(nvram_mtd, offset + magic_offset, sizeof(header->magic),
9303 + &magic_len, (char *)&header->magic);
9304 + if (ret || magic_len != sizeof(header->magic)) {
9305 + printk("nvram_commit: clear MAGIC error\n");
9306 + ret = -EIO;
9307 + goto done;
9308 + }
9309 +
9310 + header->magic = NVRAM_MAGIC; /* reset MAGIC before we regenerate the NVRAM,
9311 + otherwise we'll have an incorrect CRC */
9312 + /* Regenerate NVRAM */
9313 + spin_lock_irqsave(&nvram_lock, flags);
9314 + ret = _nvram_commit(header);
9315 + spin_unlock_irqrestore(&nvram_lock, flags);
9316 + if (ret)
9317 + goto done;
9318 +
9319 + /* Erase sector blocks */
9320 + init_waitqueue_head(&wait_q);
9321 + for (; offset < nvram_mtd->size - NVRAM_SPACE + header->len; offset += nvram_mtd->erasesize) {
9322 + erase.mtd = nvram_mtd;
9323 + erase.addr = offset;
9324 + erase.len = nvram_mtd->erasesize;
9325 + erase.callback = erase_callback;
9326 + erase.priv = (u_long) &wait_q;
9327 +
9328 + set_current_state(TASK_INTERRUPTIBLE);
9329 + add_wait_queue(&wait_q, &wait);
9330 +
9331 + /* Unlock sector blocks */
9332 + if (nvram_mtd->unlock)
9333 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
9334 +
9335 + if ((ret = MTD_ERASE(nvram_mtd, &erase))) {
9336 + set_current_state(TASK_RUNNING);
9337 + remove_wait_queue(&wait_q, &wait);
9338 + printk("nvram_commit: erase error\n");
9339 + goto done;
9340 + }
9341 +
9342 + /* Wait for erase to finish */
9343 + schedule();
9344 + remove_wait_queue(&wait_q, &wait);
9345 + }
9346 +
9347 + /* Write partition up to end of data area */
9348 + header->magic = NVRAM_INVALID_MAGIC; /* All ones magic */
9349 + offset = nvram_mtd->size - erasesize;
9350 + i = erasesize - NVRAM_SPACE + header->len;
9351 + ret = MTD_WRITE(nvram_mtd, offset, i, &len, buf);
9352 + if (ret || len != i) {
9353 + printk("nvram_commit: write error\n");
9354 + ret = -EIO;
9355 + goto done;
9356 + }
9357 +
9358 + /* Now mark the NVRAM in flash as "valid" by setting the correct
9359 + MAGIC # */
9360 + header->magic = NVRAM_MAGIC;
9361 + ret = MTD_WRITE(nvram_mtd, offset + magic_offset, sizeof(header->magic),
9362 + &magic_len, (char *)&header->magic);
9363 + if (ret || magic_len != sizeof(header->magic)) {
9364 + printk("nvram_commit: write MAGIC error\n");
9365 + ret = -EIO;
9366 + goto done;
9367 + }
9368 +
9369 + /*
9370 + * Reading a few bytes back here will put the device
9371 + * back to the correct mode on certain flashes */
9372 + offset = nvram_mtd->size - erasesize;
9373 + ret = MTD_READ(nvram_mtd, offset, 4, &len, buf);
9374 +
9375 + done:
9376 + up(&nvram_sem);
9377 + kfree(buf);
9378 +
9379 + return ret;
9380 +}
9381 +
9382 +int
9383 +nvram_getall(char *buf, int count)
9384 +{
9385 + unsigned long flags;
9386 + int ret;
9387 +
9388 + spin_lock_irqsave(&nvram_lock, flags);
9389 + if (nvram_major >= 0)
9390 + ret = _nvram_getall(buf, count);
9391 + else
9392 + ret = early_nvram_getall(buf, count);
9393 + spin_unlock_irqrestore(&nvram_lock, flags);
9394 +
9395 + return ret;
9396 +}
9397 +
9398 +
9399 +
9400 +
9401 +
9402 +
9403 +
9404 +/* User mode interface below */
9405 +
9406 +static ssize_t
9407 +dev_nvram_read(struct file *file, char *buf, size_t count, loff_t *ppos)
9408 +{
9409 + char tmp[100], *name = tmp, *value;
9410 + ssize_t ret;
9411 + unsigned long off;
9412 +
9413 + if (count > sizeof(tmp)) {
9414 + if (!(name = kmalloc(count, GFP_KERNEL)))
9415 + return -ENOMEM;
9416 + }
9417 +
9418 + if (copy_from_user(name, buf, count)) {
9419 + ret = -EFAULT;
9420 + goto done;
9421 + }
9422 +
9423 + if (*name == '\0') {
9424 + /* Get all variables */
9425 + ret = nvram_getall(name, count);
9426 + if (ret == 0) {
9427 + if (copy_to_user(buf, name, count)) {
9428 + ret = -EFAULT;
9429 + goto done;
9430 + }
9431 + ret = count;
9432 + }
9433 + } else {
9434 + if (!(value = nvram_get(name))) {
9435 + ret = 0;
9436 + goto done;
9437 + }
9438 +
9439 + /* Provide the offset into mmap() space */
9440 + off = (unsigned long) value - (unsigned long) nvram_buf;
9441 +
9442 + if (put_user(off, (unsigned long *) buf)) {
9443 + ret = -EFAULT;
9444 + goto done;
9445 + }
9446 +
9447 + ret = sizeof(unsigned long);
9448 + }
9449 +
9450 + flush_cache_all();
9451 +
9452 +done:
9453 + if (name != tmp)
9454 + kfree(name);
9455 +
9456 + return ret;
9457 +}
9458 +
9459 +static ssize_t
9460 +dev_nvram_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
9461 +{
9462 + char tmp[100], *name = tmp, *value;
9463 + ssize_t ret;
9464 +
9465 + if (count > sizeof(tmp)) {
9466 + if (!(name = kmalloc(count, GFP_KERNEL)))
9467 + return -ENOMEM;
9468 + }
9469 +
9470 + if (copy_from_user(name, buf, count)) {
9471 + ret = -EFAULT;
9472 + goto done;
9473 + }
9474 +
9475 + value = name;
9476 + name = strsep(&value, "=");
9477 + if (value)
9478 + ret = nvram_set(name, value) ? : count;
9479 + else
9480 + ret = nvram_unset(name) ? : count;
9481 +
9482 + done:
9483 + if (name != tmp)
9484 + kfree(name);
9485 +
9486 + return ret;
9487 +}
9488 +
9489 +static int
9490 +dev_nvram_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
9491 +{
9492 + if (cmd != NVRAM_MAGIC)
9493 + return -EINVAL;
9494 +
9495 + return nvram_commit();
9496 +}
9497 +
9498 +static int
9499 +dev_nvram_mmap(struct file *file, struct vm_area_struct *vma)
9500 +{
9501 + unsigned long offset = virt_to_phys(nvram_buf);
9502 +
9503 + if (remap_page_range(vma->vm_start, offset, vma->vm_end-vma->vm_start,
9504 + vma->vm_page_prot))
9505 + return -EAGAIN;
9506 +
9507 + return 0;
9508 +}
9509 +
9510 +static int
9511 +dev_nvram_open(struct inode *inode, struct file * file)
9512 +{
9513 + MOD_INC_USE_COUNT;
9514 + return 0;
9515 +}
9516 +
9517 +static int
9518 +dev_nvram_release(struct inode *inode, struct file * file)
9519 +{
9520 + MOD_DEC_USE_COUNT;
9521 + return 0;
9522 +}
9523 +
9524 +static struct file_operations dev_nvram_fops = {
9525 + owner: THIS_MODULE,
9526 + open: dev_nvram_open,
9527 + release: dev_nvram_release,
9528 + read: dev_nvram_read,
9529 + write: dev_nvram_write,
9530 + ioctl: dev_nvram_ioctl,
9531 + mmap: dev_nvram_mmap,
9532 +};
9533 +
9534 +static void
9535 +dev_nvram_exit(void)
9536 +{
9537 + int order = 0;
9538 + struct page *page, *end;
9539 +
9540 + if (nvram_handle)
9541 + devfs_unregister(nvram_handle);
9542 +
9543 + if (nvram_major >= 0)
9544 + devfs_unregister_chrdev(nvram_major, "nvram");
9545 +
9546 + if (nvram_mtd)
9547 + put_mtd_device(nvram_mtd);
9548 +
9549 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
9550 + order++;
9551 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
9552 + for (page = virt_to_page(nvram_buf); page <= end; page++)
9553 + mem_map_unreserve(page);
9554 +
9555 + _nvram_exit();
9556 +}
9557 +
9558 +static int __init
9559 +dev_nvram_init(void)
9560 +{
9561 + int order = 0, ret = 0;
9562 + struct page *page, *end;
9563 + unsigned int i;
9564 +
9565 + /* Allocate and reserve memory to mmap() */
9566 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
9567 + order++;
9568 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
9569 + for (page = virt_to_page(nvram_buf); page <= end; page++)
9570 + mem_map_reserve(page);
9571 +
9572 +#ifdef CONFIG_MTD
9573 + /* Find associated MTD device */
9574 + for (i = 0; i < MAX_MTD_DEVICES; i++) {
9575 + nvram_mtd = get_mtd_device(NULL, i);
9576 + if (nvram_mtd) {
9577 + if (!strcmp(nvram_mtd->name, "nvram") &&
9578 + nvram_mtd->size >= NVRAM_SPACE)
9579 + break;
9580 + put_mtd_device(nvram_mtd);
9581 + }
9582 + }
9583 + if (i >= MAX_MTD_DEVICES)
9584 + nvram_mtd = NULL;
9585 +#endif
9586 +
9587 + /* Initialize hash table lock */
9588 + spin_lock_init(&nvram_lock);
9589 +
9590 + /* Initialize commit semaphore */
9591 + init_MUTEX(&nvram_sem);
9592 +
9593 + /* Register char device */
9594 + if ((nvram_major = devfs_register_chrdev(0, "nvram", &dev_nvram_fops)) < 0) {
9595 + ret = nvram_major;
9596 + goto err;
9597 + }
9598 +
9599 + /* Initialize hash table */
9600 + _nvram_init(sbh);
9601 +
9602 + /* Create /dev/nvram handle */
9603 + nvram_handle = devfs_register(NULL, "nvram", DEVFS_FL_NONE, nvram_major, 0,
9604 + S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, &dev_nvram_fops, NULL);
9605 +
9606 + /* Set the SDRAM NCDL value into NVRAM if not already done */
9607 + if (getintvar(NULL, "sdram_ncdl") == 0) {
9608 + unsigned int ncdl;
9609 + char buf[] = "0x00000000";
9610 +
9611 + if ((ncdl = sb_memc_get_ncdl(sbh))) {
9612 + sprintf(buf, "0x%08x", ncdl);
9613 + nvram_set("sdram_ncdl", buf);
9614 + nvram_commit();
9615 + }
9616 + }
9617 +
9618 + return 0;
9619 +
9620 + err:
9621 + dev_nvram_exit();
9622 + return ret;
9623 +}
9624 +
9625 +module_init(dev_nvram_init);
9626 +module_exit(dev_nvram_exit);
9627 diff -urN linux.old/arch/mips/bcm947xx/pcibios.c linux.dev/arch/mips/bcm947xx/pcibios.c
9628 --- linux.old/arch/mips/bcm947xx/pcibios.c 1970-01-01 01:00:00.000000000 +0100
9629 +++ linux.dev/arch/mips/bcm947xx/pcibios.c 2006-10-02 21:22:56.000000000 +0200
9630 @@ -0,0 +1,380 @@
9631 +/*
9632 + * Low-Level PCI and SB support for BCM47xx (Linux support code)
9633 + *
9634 + * Copyright 2006, Broadcom Corporation
9635 + * All Rights Reserved.
9636 + *
9637 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9638 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9639 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9640 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9641 + *
9642 + * $Id: pcibios.c,v 1.1.1.9 2006/02/27 03:42:55 honor Exp $
9643 + */
9644 +
9645 +#include <linux/config.h>
9646 +#include <linux/types.h>
9647 +#include <linux/kernel.h>
9648 +#include <linux/sched.h>
9649 +#include <linux/pci.h>
9650 +#include <linux/init.h>
9651 +#include <linux/delay.h>
9652 +#include <asm/io.h>
9653 +#include <asm/irq.h>
9654 +#include <asm/paccess.h>
9655 +
9656 +#include <typedefs.h>
9657 +#include <osl.h>
9658 +#include <bcmutils.h>
9659 +#include <sbconfig.h>
9660 +#include <sbutils.h>
9661 +#include <hndpci.h>
9662 +#include <pcicfg.h>
9663 +#include <bcmdevs.h>
9664 +#include <bcmnvram.h>
9665 +
9666 +/* Global SB handle */
9667 +extern sb_t *bcm947xx_sbh;
9668 +extern spinlock_t bcm947xx_sbh_lock;
9669 +
9670 +/* Convenience */
9671 +#define sbh bcm947xx_sbh
9672 +#define sbh_lock bcm947xx_sbh_lock
9673 +
9674 +static int
9675 +sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
9676 +{
9677 + unsigned long flags;
9678 + int ret;
9679 +
9680 + spin_lock_irqsave(&sbh_lock, flags);
9681 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9682 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9683 + spin_unlock_irqrestore(&sbh_lock, flags);
9684 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9685 +}
9686 +
9687 +static int
9688 +sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
9689 +{
9690 + unsigned long flags;
9691 + int ret;
9692 +
9693 + spin_lock_irqsave(&sbh_lock, flags);
9694 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9695 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9696 + spin_unlock_irqrestore(&sbh_lock, flags);
9697 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9698 +}
9699 +
9700 +static int
9701 +sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
9702 +{
9703 + unsigned long flags;
9704 + int ret;
9705 +
9706 + spin_lock_irqsave(&sbh_lock, flags);
9707 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9708 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9709 + spin_unlock_irqrestore(&sbh_lock, flags);
9710 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9711 +}
9712 +
9713 +static int
9714 +sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
9715 +{
9716 + unsigned long flags;
9717 + int ret;
9718 +
9719 + spin_lock_irqsave(&sbh_lock, flags);
9720 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9721 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9722 + spin_unlock_irqrestore(&sbh_lock, flags);
9723 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9724 +}
9725 +
9726 +static int
9727 +sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
9728 +{
9729 + unsigned long flags;
9730 + int ret;
9731 +
9732 + spin_lock_irqsave(&sbh_lock, flags);
9733 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9734 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9735 + spin_unlock_irqrestore(&sbh_lock, flags);
9736 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9737 +}
9738 +
9739 +static int
9740 +sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
9741 +{
9742 + unsigned long flags;
9743 + int ret;
9744 +
9745 + spin_lock_irqsave(&sbh_lock, flags);
9746 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9747 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9748 + spin_unlock_irqrestore(&sbh_lock, flags);
9749 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9750 +}
9751 +
9752 +static struct pci_ops pcibios_ops = {
9753 + sbpci_read_config_byte,
9754 + sbpci_read_config_word,
9755 + sbpci_read_config_dword,
9756 + sbpci_write_config_byte,
9757 + sbpci_write_config_word,
9758 + sbpci_write_config_dword
9759 +};
9760 +
9761 +
9762 +void __init
9763 +pcibios_init(void)
9764 +{
9765 + ulong flags;
9766 +
9767 + if (!(sbh = sb_kattach()))
9768 + panic("sb_kattach failed");
9769 + spin_lock_init(&sbh_lock);
9770 +
9771 + spin_lock_irqsave(&sbh_lock, flags);
9772 + sbpci_init(sbh);
9773 + spin_unlock_irqrestore(&sbh_lock, flags);
9774 +
9775 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
9776 +
9777 + /* Scan the SB bus */
9778 + pci_scan_bus(0, &pcibios_ops, NULL);
9779 +
9780 +}
9781 +
9782 +char * __init
9783 +pcibios_setup(char *str)
9784 +{
9785 + if (!strncmp(str, "ban=", 4)) {
9786 + sbpci_ban(simple_strtoul(str + 4, NULL, 0));
9787 + return NULL;
9788 + }
9789 +
9790 + return (str);
9791 +}
9792 +
9793 +static u32 pci_iobase = 0x100;
9794 +static u32 pci_membase = SB_PCI_DMA;
9795 +
9796 +void __init
9797 +pcibios_fixup_bus(struct pci_bus *b)
9798 +{
9799 + struct list_head *ln;
9800 + struct pci_dev *d;
9801 + struct resource *res;
9802 + int pos, size;
9803 + u32 *base;
9804 + u8 irq;
9805 +
9806 + printk("PCI: Fixing up bus %d\n", b->number);
9807 +
9808 + /* Fix up SB */
9809 + if (b->number == 0) {
9810 + for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
9811 + d = pci_dev_b(ln);
9812 + /* Fix up interrupt lines */
9813 + pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
9814 + d->irq = irq + 2;
9815 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
9816 + }
9817 + }
9818 +
9819 + /* Fix up external PCI */
9820 + else {
9821 + for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
9822 + d = pci_dev_b(ln);
9823 + /* Fix up resource bases */
9824 + for (pos = 0; pos < 6; pos++) {
9825 + res = &d->resource[pos];
9826 + base = (res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase;
9827 + if (res->end) {
9828 + size = res->end - res->start + 1;
9829 + if (*base & (size - 1))
9830 + *base = (*base + size) & ~(size - 1);
9831 + res->start = *base;
9832 + res->end = res->start + size - 1;
9833 + *base += size;
9834 + pci_write_config_dword(d,
9835 + PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
9836 + }
9837 + /* Fix up PCI bridge BAR0 only */
9838 + if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
9839 + break;
9840 + }
9841 + /* Fix up interrupt lines */
9842 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
9843 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
9844 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
9845 + }
9846 + }
9847 +}
9848 +
9849 +unsigned int
9850 +pcibios_assign_all_busses(void)
9851 +{
9852 + return 1;
9853 +}
9854 +
9855 +void
9856 +pcibios_align_resource(void *data, struct resource *res,
9857 + unsigned long size, unsigned long align)
9858 +{
9859 +}
9860 +
9861 +int
9862 +pcibios_enable_resources(struct pci_dev *dev)
9863 +{
9864 + u16 cmd, old_cmd;
9865 + int idx;
9866 + struct resource *r;
9867 +
9868 + /* External PCI only */
9869 + if (dev->bus->number == 0)
9870 + return 0;
9871 +
9872 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
9873 + old_cmd = cmd;
9874 + for (idx = 0; idx < 6; idx++) {
9875 + r = &dev->resource[idx];
9876 + if (r->flags & IORESOURCE_IO)
9877 + cmd |= PCI_COMMAND_IO;
9878 + if (r->flags & IORESOURCE_MEM)
9879 + cmd |= PCI_COMMAND_MEMORY;
9880 + }
9881 + if (dev->resource[PCI_ROM_RESOURCE].start)
9882 + cmd |= PCI_COMMAND_MEMORY;
9883 + if (cmd != old_cmd) {
9884 + printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
9885 + pci_write_config_word(dev, PCI_COMMAND, cmd);
9886 + }
9887 + return 0;
9888 +}
9889 +
9890 +int
9891 +pcibios_enable_device(struct pci_dev *dev, int mask)
9892 +{
9893 + ulong flags;
9894 + uint coreidx;
9895 + void *regs;
9896 +
9897 + /* External PCI device enable */
9898 + if (dev->bus->number != 0)
9899 + return pcibios_enable_resources(dev);
9900 +
9901 + /* These cores come out of reset enabled */
9902 + if (dev->device == SB_MIPS ||
9903 + dev->device == SB_MIPS33 ||
9904 + dev->device == SB_EXTIF ||
9905 + dev->device == SB_CC)
9906 + return 0;
9907 +
9908 + spin_lock_irqsave(&sbh_lock, flags);
9909 + coreidx = sb_coreidx(sbh);
9910 + regs = sb_setcoreidx(sbh, PCI_SLOT(dev->devfn));
9911 + if (!regs)
9912 + return PCIBIOS_DEVICE_NOT_FOUND;
9913 +
9914 + /*
9915 + * The USB core requires a special bit to be set during core
9916 + * reset to enable host (OHCI) mode. Resetting the SB core in
9917 + * pcibios_enable_device() is a hack for compatibility with
9918 + * vanilla usb-ohci so that it does not have to know about
9919 + * SB. A driver that wants to use the USB core in device mode
9920 + * should know about SB and should reset the bit back to 0
9921 + * after calling pcibios_enable_device().
9922 + */
9923 + if (sb_coreid(sbh) == SB_USB) {
9924 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
9925 + sb_core_reset(sbh, 1 << 29, 0);
9926 + }
9927 + /*
9928 + * USB 2.0 special considerations:
9929 + *
9930 + * 1. Since the core supports both OHCI and EHCI functions, it must
9931 + * only be reset once.
9932 + *
9933 + * 2. In addition to the standard SB reset sequence, the Host Control
9934 + * Register must be programmed to bring the USB core and various
9935 + * phy components out of reset.
9936 + */
9937 + else if (sb_coreid(sbh) == SB_USB20H) {
9938 + if (!sb_iscoreup(sbh)) {
9939 + sb_core_reset(sbh, 0, 0);
9940 + writel(0x7FF, (ulong)regs + 0x200);
9941 + udelay(1);
9942 + }
9943 + } else
9944 + sb_core_reset(sbh, 0, 0);
9945 +
9946 + sb_setcoreidx(sbh, coreidx);
9947 + spin_unlock_irqrestore(&sbh_lock, flags);
9948 +
9949 + return 0;
9950 +}
9951 +
9952 +void
9953 +pcibios_update_resource(struct pci_dev *dev, struct resource *root,
9954 + struct resource *res, int resource)
9955 +{
9956 + unsigned long where, size;
9957 + u32 reg;
9958 +
9959 + /* External PCI only */
9960 + if (dev->bus->number == 0)
9961 + return;
9962 +
9963 + where = PCI_BASE_ADDRESS_0 + (resource * 4);
9964 + size = res->end - res->start;
9965 + pci_read_config_dword(dev, where, &reg);
9966 + reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
9967 + pci_write_config_dword(dev, where, reg);
9968 +}
9969 +
9970 +static void __init
9971 +quirk_sbpci_bridge(struct pci_dev *dev)
9972 +{
9973 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
9974 + return;
9975 +
9976 + printk("PCI: Fixing up bridge\n");
9977 +
9978 + /* Enable PCI bridge bus mastering and memory space */
9979 + pci_set_master(dev);
9980 + pcibios_enable_resources(dev);
9981 +
9982 + /* Enable PCI bridge BAR1 prefetch and burst */
9983 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
9984 +}
9985 +
9986 +struct pci_fixup pcibios_fixups[] = {
9987 + { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
9988 + { 0 }
9989 +};
9990 +
9991 +/*
9992 + * If we set up a device for bus mastering, we need to check the latency
9993 + * timer as certain crappy BIOSes forget to set it properly.
9994 + */
9995 +unsigned int pcibios_max_latency = 255;
9996 +
9997 +void pcibios_set_master(struct pci_dev *dev)
9998 +{
9999 + u8 lat;
10000 + pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
10001 + if (lat < 16)
10002 + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
10003 + else if (lat > pcibios_max_latency)
10004 + lat = pcibios_max_latency;
10005 + else
10006 + return;
10007 + printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
10008 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
10009 +}
10010 +
10011 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
10012 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
10013 +++ linux.dev/arch/mips/bcm947xx/prom.c 2006-10-02 21:19:59.000000000 +0200
10014 @@ -0,0 +1,41 @@
10015 +/*
10016 + * Early initialization code for BCM94710 boards
10017 + *
10018 + * Copyright 2004, Broadcom Corporation
10019 + * All Rights Reserved.
10020 + *
10021 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10022 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10023 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10024 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10025 + *
10026 + * $Id: prom.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
10027 + */
10028 +
10029 +#include <linux/config.h>
10030 +#include <linux/init.h>
10031 +#include <linux/kernel.h>
10032 +#include <linux/types.h>
10033 +#include <asm/bootinfo.h>
10034 +
10035 +void __init
10036 +prom_init(int argc, const char **argv)
10037 +{
10038 + unsigned long mem;
10039 +
10040 + mips_machgroup = MACH_GROUP_BRCM;
10041 + mips_machtype = MACH_BCM947XX;
10042 +
10043 + /* Figure out memory size by finding aliases */
10044 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
10045 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
10046 + *(unsigned long *)(prom_init))
10047 + break;
10048 + }
10049 + add_memory_region(0, mem, BOOT_MEM_RAM);
10050 +}
10051 +
10052 +void __init
10053 +prom_free_prom_memory(void)
10054 +{
10055 +}
10056 diff -urN linux.old/arch/mips/bcm947xx/sbmips.c linux.dev/arch/mips/bcm947xx/sbmips.c
10057 --- linux.old/arch/mips/bcm947xx/sbmips.c 1970-01-01 01:00:00.000000000 +0100
10058 +++ linux.dev/arch/mips/bcm947xx/sbmips.c 2006-10-02 21:19:59.000000000 +0200
10059 @@ -0,0 +1,1132 @@
10060 +/*
10061 + * BCM47XX Sonics SiliconBackplane MIPS core routines
10062 + *
10063 + * Copyright 2006, Broadcom Corporation
10064 + * All Rights Reserved.
10065 + *
10066 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10067 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10068 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10069 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10070 + *
10071 + * $Id: hndmips.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
10072 + */
10073 +
10074 +#include <typedefs.h>
10075 +#include <bcmdefs.h>
10076 +#include <osl.h>
10077 +#include <bcmutils.h>
10078 +#include <sbutils.h>
10079 +#include <bcmdevs.h>
10080 +#include <bcmnvram.h>
10081 +#include <sbconfig.h>
10082 +#include <sbextif.h>
10083 +#include <sbchipc.h>
10084 +#include <sbmemc.h>
10085 +#include <mipsinc.h>
10086 +#include <sbhndmips.h>
10087 +#include <hndcpu.h>
10088 +
10089 +/* sbipsflag register format, indexed by irq. */
10090 +static const uint32 sbips_int_mask[] = {
10091 + 0, /* placeholder */
10092 + SBIPS_INT1_MASK,
10093 + SBIPS_INT2_MASK,
10094 + SBIPS_INT3_MASK,
10095 + SBIPS_INT4_MASK
10096 +};
10097 +
10098 +static const uint32 sbips_int_shift[] = {
10099 + 0, /* placeholder */
10100 + SBIPS_INT1_SHIFT,
10101 + SBIPS_INT2_SHIFT,
10102 + SBIPS_INT3_SHIFT,
10103 + SBIPS_INT4_SHIFT
10104 +};
10105 +
10106 +/*
10107 + * Map SB cores sharing the MIPS hardware IRQ0 to virtual dedicated OS IRQs.
10108 + * Per-port BSP code is required to provide necessary translations between
10109 + * the shared MIPS IRQ and the virtual OS IRQs based on SB core flag.
10110 + *
10111 + * See sb_irq() for the mapping.
10112 + */
10113 +static uint shirq_map_base = 0;
10114 +
10115 +/* Returns the SB interrupt flag of the current core. */
10116 +static uint32
10117 +sb_getflag(sb_t *sbh)
10118 +{
10119 + osl_t *osh;
10120 + void *regs;
10121 + sbconfig_t *sb;
10122 +
10123 + osh = sb_osh(sbh);
10124 + regs = sb_coreregs(sbh);
10125 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10126 +
10127 + return (R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK);
10128 +}
10129 +
10130 +/*
10131 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
10132 + * 0 is returned.
10133 + */
10134 +uint
10135 +sb_irq(sb_t *sbh)
10136 +{
10137 + osl_t *osh;
10138 + uint idx;
10139 + void *regs;
10140 + sbconfig_t *sb;
10141 + uint32 flag, sbipsflag;
10142 + uint irq = 0;
10143 +
10144 + osh = sb_osh(sbh);
10145 + flag = sb_getflag(sbh);
10146 +
10147 + idx = sb_coreidx(sbh);
10148 +
10149 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
10150 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
10151 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10152 +
10153 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
10154 + sbipsflag = R_REG(osh, &sb->sbipsflag);
10155 + for (irq = 1; irq <= 4; irq++) {
10156 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
10157 + break;
10158 + }
10159 + if (irq == 5)
10160 + irq = 0;
10161 + }
10162 +
10163 + sb_setcoreidx(sbh, idx);
10164 +
10165 + return irq;
10166 +}
10167 +
10168 +/* Clears the specified MIPS IRQ. */
10169 +static void
10170 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
10171 +{
10172 + osl_t *osh;
10173 + void *regs;
10174 + sbconfig_t *sb;
10175 +
10176 + osh = sb_osh(sbh);
10177 +
10178 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
10179 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
10180 + ASSERT(regs);
10181 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10182 +
10183 + if (irq == 0)
10184 + W_REG(osh, &sb->sbintvec, 0);
10185 + else
10186 + OR_REG(osh, &sb->sbipsflag, sbips_int_mask[irq]);
10187 +}
10188 +
10189 +/*
10190 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
10191 + * IRQ 0 may be assigned more than once.
10192 + *
10193 + * The old assignment to the specified core is removed first.
10194 + */
10195 +static void
10196 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
10197 +{
10198 + osl_t *osh;
10199 + void *regs;
10200 + sbconfig_t *sb;
10201 + uint32 flag;
10202 + uint oldirq;
10203 +
10204 + osh = sb_osh(sbh);
10205 +
10206 + regs = sb_setcore(sbh, coreid, coreunit);
10207 + ASSERT(regs);
10208 + flag = sb_getflag(sbh);
10209 + oldirq = sb_irq(sbh);
10210 + if (oldirq)
10211 + sb_clearirq(sbh, oldirq);
10212 +
10213 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
10214 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
10215 + ASSERT(regs);
10216 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10217 +
10218 + if (!oldirq)
10219 + AND_REG(osh, &sb->sbintvec, ~(1 << flag));
10220 +
10221 + if (irq == 0)
10222 + OR_REG(osh, &sb->sbintvec, 1 << flag);
10223 + else {
10224 + flag <<= sbips_int_shift[irq];
10225 + ASSERT(!(flag & ~sbips_int_mask[irq]));
10226 + flag |= R_REG(osh, &sb->sbipsflag) & ~sbips_int_mask[irq];
10227 + W_REG(osh, &sb->sbipsflag, flag);
10228 + }
10229 +}
10230 +
10231 +/*
10232 + * Initializes clocks and interrupts. SB and NVRAM access must be
10233 + * initialized prior to calling.
10234 + *
10235 + * 'shirqmap' enables virtual dedicated OS IRQ mapping if non-zero.
10236 + */
10237 +void
10238 +BCMINITFN(sb_mips_init)(sb_t *sbh, uint shirqmap)
10239 +{
10240 + osl_t *osh;
10241 + ulong hz, ns, tmp;
10242 + extifregs_t *eir;
10243 + chipcregs_t *cc;
10244 + char *value;
10245 + uint irq;
10246 +
10247 + osh = sb_osh(sbh);
10248 +
10249 + /* Figure out current SB clock speed */
10250 + if ((hz = sb_clock(sbh)) == 0)
10251 + hz = 100000000;
10252 + ns = 1000000000 / hz;
10253 +
10254 + /* Setup external interface timing */
10255 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
10256 + /* Initialize extif so we can get to the LEDs and external UART */
10257 + W_REG(osh, &eir->prog_config, CF_EN);
10258 +
10259 + /* Set timing for the flash */
10260 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10261 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
10262 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10263 + W_REG(osh, &eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10264 +
10265 + /* Set programmable interface timing for external uart */
10266 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10267 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
10268 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
10269 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10270 + W_REG(osh, &eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10271 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
10272 + /* Set timing for the flash */
10273 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10274 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
10275 + tmp |= CEIL(120, ns); /* W0 = 120nS */
10276 + if ((sb_corerev(sbh) < 9) ||
10277 + (BCMINIT(sb_chip)(sbh) == 0x5365))
10278 + W_REG(osh, &cc->flash_waitcount, tmp);
10279 +
10280 + if ((sb_corerev(sbh) < 9) ||
10281 + ((sb_chip(sbh) == BCM5350_CHIP_ID) && sb_chiprev(sbh) == 0) ||
10282 + (BCMINIT(sb_chip)(sbh) == 0x5365)) {
10283 + W_REG(osh, &cc->pcmcia_memwait, tmp);
10284 + }
10285 +
10286 + /* Save shared IRQ mapping base */
10287 + shirq_map_base = shirqmap;
10288 + }
10289 +
10290 + /* Chip specific initialization */
10291 + switch (sb_chip(sbh)) {
10292 + case BCM4710_CHIP_ID:
10293 + /* Clear interrupt map */
10294 + for (irq = 0; irq <= 4; irq++)
10295 + sb_clearirq(sbh, irq);
10296 + sb_setirq(sbh, 0, SB_CODEC, 0);
10297 + sb_setirq(sbh, 0, SB_EXTIF, 0);
10298 + sb_setirq(sbh, 2, SB_ENET, 1);
10299 + sb_setirq(sbh, 3, SB_ILINE20, 0);
10300 + sb_setirq(sbh, 4, SB_PCI, 0);
10301 + ASSERT(eir);
10302 + value = nvram_get("et0phyaddr");
10303 + if (value && !strcmp(value, "31")) {
10304 + /* Enable internal UART */
10305 + W_REG(osh, &eir->corecontrol, CC_UE);
10306 + /* Give USB its own interrupt */
10307 + sb_setirq(sbh, 1, SB_USB, 0);
10308 + } else {
10309 + /* Disable internal UART */
10310 + W_REG(osh, &eir->corecontrol, 0);
10311 + /* Give Ethernet its own interrupt */
10312 + sb_setirq(sbh, 1, SB_ENET, 0);
10313 + sb_setirq(sbh, 0, SB_USB, 0);
10314 + }
10315 + break;
10316 + case BCM5350_CHIP_ID:
10317 + /* Clear interrupt map */
10318 + for (irq = 0; irq <= 4; irq++)
10319 + sb_clearirq(sbh, irq);
10320 + sb_setirq(sbh, 0, SB_CC, 0);
10321 + sb_setirq(sbh, 0, SB_MIPS33, 0);
10322 + sb_setirq(sbh, 1, SB_D11, 0);
10323 + sb_setirq(sbh, 2, SB_ENET, 0);
10324 + sb_setirq(sbh, 3, SB_PCI, 0);
10325 + sb_setirq(sbh, 4, SB_USB, 0);
10326 + break;
10327 + case BCM4785_CHIP_ID:
10328 + /* Reassign PCI to irq 4 */
10329 + sb_setirq(sbh, 4, SB_PCI, 0);
10330 + break;
10331 + }
10332 +}
10333 +
10334 +uint32
10335 +BCMINITFN(sb_cpu_clock)(sb_t *sbh)
10336 +{
10337 + extifregs_t *eir;
10338 + chipcregs_t *cc;
10339 + uint32 n, m;
10340 + uint idx;
10341 + uint32 pll_type, rate = 0;
10342 +
10343 + /* get index of the current core */
10344 + idx = sb_coreidx(sbh);
10345 + pll_type = PLL_TYPE1;
10346 +
10347 + /* switch to extif or chipc core */
10348 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
10349 + n = R_REG(osh, &eir->clockcontrol_n);
10350 + m = R_REG(osh, &eir->clockcontrol_sb);
10351 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
10352 + pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
10353 + n = R_REG(osh, &cc->clockcontrol_n);
10354 + if ((pll_type == PLL_TYPE2) ||
10355 + (pll_type == PLL_TYPE4) ||
10356 + (pll_type == PLL_TYPE6) ||
10357 + (pll_type == PLL_TYPE7))
10358 + m = R_REG(osh, &cc->clockcontrol_m3);
10359 + else if (pll_type == PLL_TYPE5) {
10360 + rate = 200000000;
10361 + goto out;
10362 + }
10363 + else if (pll_type == PLL_TYPE3) {
10364 + if (sb_chip(sbh) == BCM5365_CHIP_ID) {
10365 + rate = 200000000;
10366 + goto out;
10367 + }
10368 + /* 5350 uses m2 to control mips */
10369 + else
10370 + m = R_REG(osh, &cc->clockcontrol_m2);
10371 + } else
10372 + m = R_REG(osh, &cc->clockcontrol_sb);
10373 + } else
10374 + goto out;
10375 +
10376 +
10377 + /* calculate rate */
10378 + if (BCMINIT(sb_chip)(sbh) == 0x5365)
10379 + rate = 100000000;
10380 + else
10381 + rate = sb_clock_rate(pll_type, n, m);
10382 +
10383 + if (pll_type == PLL_TYPE6)
10384 + rate = SB2MIPS_T6(rate);
10385 +
10386 +out:
10387 + /* switch back to previous core */
10388 + sb_setcoreidx(sbh, idx);
10389 +
10390 + return rate;
10391 +}
10392 +
10393 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
10394 +
10395 +static void
10396 +BCMINITFN(handler)(void)
10397 +{
10398 + __asm__(
10399 + ".set\tmips32\n\t"
10400 + "ssnop\n\t"
10401 + "ssnop\n\t"
10402 + /* Disable interrupts */
10403 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
10404 + "mfc0 $15, $12\n\t"
10405 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
10406 + "li $14, -31746\n\t"
10407 + "and $15, $15, $14\n\t"
10408 + "mtc0 $15, $12\n\t"
10409 + "eret\n\t"
10410 + "nop\n\t"
10411 + "nop\n\t"
10412 + ".set\tmips0");
10413 +}
10414 +
10415 +/* The following MUST come right after handler() */
10416 +static void
10417 +BCMINITFN(afterhandler)(void)
10418 +{
10419 +}
10420 +
10421 +/*
10422 + * Set the MIPS, backplane and PCI clocks as closely as possible.
10423 + *
10424 + * MIPS clocks synchronization function has been moved from PLL in chipcommon
10425 + * core rev. 15 to a DLL inside the MIPS core in 4785.
10426 + */
10427 +bool
10428 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
10429 +{
10430 + extifregs_t *eir = NULL;
10431 + chipcregs_t *cc = NULL;
10432 + mipsregs_t *mipsr = NULL;
10433 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
10434 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
10435 + uint32 pll_type, sync_mode;
10436 + uint ic_size, ic_lsize;
10437 + uint idx, i;
10438 +
10439 + /* PLL configuration: type 1 */
10440 + typedef struct {
10441 + uint32 mipsclock;
10442 + uint16 n;
10443 + uint32 sb;
10444 + uint32 pci33;
10445 + uint32 pci25;
10446 + } n3m_table_t;
10447 + static n3m_table_t BCMINITDATA(type1_table)[] = {
10448 + /* 96.000 32.000 24.000 */
10449 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 },
10450 + /* 100.000 33.333 25.000 */
10451 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 },
10452 + /* 104.000 31.200 24.960 */
10453 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 },
10454 + /* 108.000 32.400 24.923 */
10455 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 },
10456 + /* 112.000 32.000 24.889 */
10457 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 },
10458 + /* 115.200 32.000 24.000 */
10459 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 },
10460 + /* 120.000 30.000 24.000 */
10461 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 },
10462 + /* 124.800 31.200 24.960 */
10463 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 },
10464 + /* 128.000 32.000 24.000 */
10465 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 },
10466 + /* 132.000 33.000 24.750 */
10467 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 },
10468 + /* 136.000 32.640 24.727 */
10469 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 },
10470 + /* 140.000 30.000 24.706 */
10471 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 },
10472 + /* 144.000 30.857 24.686 */
10473 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 },
10474 + /* 150.857 33.000 24.000 */
10475 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 },
10476 + /* 152.000 32.571 24.000 */
10477 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 },
10478 + /* 156.000 31.200 24.960 */
10479 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 },
10480 + /* 160.000 32.000 24.000 */
10481 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 },
10482 + /* 163.200 32.640 24.727 */
10483 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 },
10484 + /* 168.000 32.000 24.889 */
10485 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 },
10486 + /* 176.000 33.000 24.000 */
10487 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 },
10488 + };
10489 +
10490 + /* PLL configuration: type 3 */
10491 + typedef struct {
10492 + uint32 mipsclock;
10493 + uint16 n;
10494 + uint32 m2; /* that is the clockcontrol_m2 */
10495 + } type3_table_t;
10496 + static type3_table_t type3_table[] = {
10497 + /* for 5350, mips clock is always double sb clock */
10498 + { 150000000, 0x311, 0x4020005 },
10499 + { 200000000, 0x311, 0x4020003 },
10500 + };
10501 +
10502 + /* PLL configuration: type 2, 4, 7 */
10503 + typedef struct {
10504 + uint32 mipsclock;
10505 + uint32 sbclock;
10506 + uint16 n;
10507 + uint32 sb;
10508 + uint32 pci33;
10509 + uint32 m2;
10510 + uint32 m3;
10511 + uint32 ratio_cfg;
10512 + uint32 ratio_parm;
10513 + uint32 d11_r1;
10514 + uint32 d11_r2;
10515 + } n4m_table_t;
10516 + static n4m_table_t BCMINITDATA(type2_table)[] = {
10517 + { 120000000, 60000000, 0x0303, 0x01000200, 0x01000600, 0x01000200, 0x05000200, 11,
10518 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10519 + { 150000000, 75000000, 0x0303, 0x01000100, 0x01000600, 0x01000100, 0x05000100, 11,
10520 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10521 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8,
10522 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10523 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11,
10524 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10525 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11,
10526 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10527 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11,
10528 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10529 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11,
10530 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10531 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11,
10532 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10533 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8,
10534 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10535 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11,
10536 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10537 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11,
10538 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10539 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11,
10540 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10541 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10542 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10543 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10544 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10545 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11,
10546 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10547 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10548 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10549 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11,
10550 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10551 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01010100, 0x05000100, 8,
10552 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10553 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01010100, 0x05000100, 11,
10554 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10555 + { 330000000, 132000000, 0x0903, 0x01000200, 0x00020200, 0x01010100, 0x05000100, 0,
10556 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10557 + { 330000000, 146666666, 0x0903, 0x01010000, 0x00020200, 0x01010100, 0x05000100, 0,
10558 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10559 + { 330000000, 165000000, 0x0903, 0x01000100, 0x00020200, 0x01010100, 0x05000100, 0,
10560 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10561 + { 360000000, 120000000, 0x0a03, 0x01000300, 0x00010201, 0x01010200, 0x05000100, 0,
10562 + 0, 12 /* ratio 4/12 */, 0x04920492 },
10563 + { 360000000, 144000000, 0x0a03, 0x01000200, 0x00010201, 0x01010200, 0x05000100, 0,
10564 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10565 + { 360000000, 160000000, 0x0a03, 0x01010000, 0x00010201, 0x01010200, 0x05000100, 0,
10566 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10567 + { 360000000, 180000000, 0x0a03, 0x01000100, 0x00010201, 0x01010200, 0x05000100, 0,
10568 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10569 + { 390000000, 130000000, 0x0b03, 0x01010100, 0x00020101, 0x01020100, 0x05000100, 0,
10570 + 0, 12 /* ratio 4/12 */, 0x04920492 },
10571 + { 390000000, 156000000, 0x0b03, 0x01000200, 0x00020101, 0x01020100, 0x05000100, 0,
10572 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10573 + { 390000000, 173000000, 0x0b03, 0x01010000, 0x00020101, 0x01020100, 0x05000100, 0,
10574 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10575 + { 390000000, 195000000, 0x0b03, 0x01000100, 0x00020101, 0x01020100, 0x05000100, 0,
10576 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10577 + };
10578 + static n4m_table_t BCMINITDATA(type4_table)[] = {
10579 + { 120000000, 60000000, 0x0009, 0x11020009, 0x01030203, 0x11020009, 0x04000009, 11,
10580 + 0x0aaa0555 },
10581 + { 150000000, 75000000, 0x0009, 0x11050002, 0x01030203, 0x11050002, 0x04000005, 11,
10582 + 0x0aaa0555 },
10583 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10584 + 0x0aaa0555 },
10585 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11,
10586 + 0x0aaa0555 },
10587 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11,
10588 + 0x0aaa0555 },
10589 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10590 + 0x0aaa0555 },
10591 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11,
10592 + 0x0aaa0555 },
10593 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10594 + 0x0aaa0555 },
10595 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10596 + 0x0aaa0555 },
10597 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11,
10598 + 0x0aaa0555 },
10599 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8,
10600 + 0x012a00a9 },
10601 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11,
10602 + 0x0aaa0555 },
10603 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13,
10604 + 0x254a14a9 },
10605 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11,
10606 + 0x0aaa0555 },
10607 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9,
10608 + 0x02520129 },
10609 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11,
10610 + 0x0aaa0555 },
10611 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11,
10612 + 0x0aaa0555 },
10613 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13,
10614 + 0x254a14a9 },
10615 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13,
10616 + 0x254a14a9 },
10617 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13,
10618 + 0x254a14a9 },
10619 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9,
10620 + 0x02520129 },
10621 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11,
10622 + 0x0aaa0555 }
10623 + };
10624 + static n4m_table_t BCMINITDATA(type7_table)[] = {
10625 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10626 + 0x0aaa0555 },
10627 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10628 + 0x0aaa0555 },
10629 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11,
10630 + 0x0aaa0555 },
10631 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11,
10632 + 0x0aaa0555 },
10633 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11,
10634 + 0x0aaa0555 },
10635 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11,
10636 + 0x0aaa0555 },
10637 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10638 + 0x0aaa0555 },
10639 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11,
10640 + 0x0aaa0555 },
10641 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10642 + 0x0aaa0555 },
10643 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10644 + 0x0aaa0555 },
10645 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10646 + 0x0aaa0555 },
10647 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11,
10648 + 0x0aaa0555 },
10649 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11,
10650 + 0x0aaa0555 },
10651 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11,
10652 + 0x0aaa0555 }
10653 + };
10654 +
10655 + ulong start, end, dst;
10656 + bool ret = FALSE;
10657 +
10658 + volatile uint32 *dll_ctrl = (volatile uint32 *)0xff400008;
10659 + volatile uint32 *dll_r1 = (volatile uint32 *)0xff400010;
10660 + volatile uint32 *dll_r2 = (volatile uint32 *)0xff400018;
10661 +
10662 + /* get index of the current core */
10663 + idx = sb_coreidx(sbh);
10664 + clockcontrol_m2 = NULL;
10665 +
10666 + /* switch to extif or chipc core */
10667 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
10668 + pll_type = PLL_TYPE1;
10669 + clockcontrol_n = &eir->clockcontrol_n;
10670 + clockcontrol_sb = &eir->clockcontrol_sb;
10671 + clockcontrol_pci = &eir->clockcontrol_pci;
10672 + clockcontrol_m2 = &cc->clockcontrol_m2;
10673 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
10674 + pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
10675 + if (pll_type == PLL_TYPE6) {
10676 + clockcontrol_n = NULL;
10677 + clockcontrol_sb = NULL;
10678 + clockcontrol_pci = NULL;
10679 + } else {
10680 + clockcontrol_n = &cc->clockcontrol_n;
10681 + clockcontrol_sb = &cc->clockcontrol_sb;
10682 + clockcontrol_pci = &cc->clockcontrol_pci;
10683 + clockcontrol_m2 = &cc->clockcontrol_m2;
10684 + }
10685 + } else
10686 + goto done;
10687 +
10688 + if (pll_type == PLL_TYPE6) {
10689 + /* Silence compilers */
10690 + orig_n = orig_sb = orig_pci = 0;
10691 + } else {
10692 + /* Store the current clock register values */
10693 + orig_n = R_REG(osh, clockcontrol_n);
10694 + orig_sb = R_REG(osh, clockcontrol_sb);
10695 + orig_pci = R_REG(osh, clockcontrol_pci);
10696 + }
10697 +
10698 + if (pll_type == PLL_TYPE1) {
10699 + /* Keep the current PCI clock if not specified */
10700 + if (pciclock == 0) {
10701 + pciclock = sb_clock_rate(pll_type, R_REG(osh, clockcontrol_n),
10702 + R_REG(osh, clockcontrol_pci));
10703 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
10704 + }
10705 +
10706 + /* Search for the closest MIPS clock less than or equal to a preferred value */
10707 + for (i = 0; i < ARRAYSIZE(type1_table); i++) {
10708 + ASSERT(type1_table[i].mipsclock ==
10709 + sb_clock_rate(pll_type, type1_table[i].n,
10710 + type1_table[i].sb));
10711 + if (type1_table[i].mipsclock > mipsclock)
10712 + break;
10713 + }
10714 + if (i == 0) {
10715 + ret = FALSE;
10716 + goto done;
10717 + } else {
10718 + ret = TRUE;
10719 + i--;
10720 + }
10721 + ASSERT(type1_table[i].mipsclock <= mipsclock);
10722 +
10723 + /* No PLL change */
10724 + if ((orig_n == type1_table[i].n) &&
10725 + (orig_sb == type1_table[i].sb) &&
10726 + (orig_pci == type1_table[i].pci33))
10727 + goto done;
10728 +
10729 + /* Set the PLL controls */
10730 + W_REG(osh, clockcontrol_n, type1_table[i].n);
10731 + W_REG(osh, clockcontrol_sb, type1_table[i].sb);
10732 + if (pciclock == 25000000)
10733 + W_REG(osh, clockcontrol_pci, type1_table[i].pci25);
10734 + else
10735 + W_REG(osh, clockcontrol_pci, type1_table[i].pci33);
10736 +
10737 + /* Reset */
10738 + sb_watchdog(sbh, 1);
10739 + while (1);
10740 + } else if (pll_type == PLL_TYPE3) {
10741 + /* 5350 */
10742 + if (sb_chip(sbh) != BCM5365_CHIP_ID) {
10743 + /*
10744 + * Search for the closest MIPS clock less than or equal to
10745 + * a preferred value.
10746 + */
10747 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
10748 + if (type3_table[i].mipsclock > mipsclock)
10749 + break;
10750 + }
10751 + if (i == 0) {
10752 + ret = FALSE;
10753 + goto done;
10754 + } else {
10755 + ret = TRUE;
10756 + i--;
10757 + }
10758 + ASSERT(type3_table[i].mipsclock <= mipsclock);
10759 +
10760 + /* No PLL change */
10761 + orig_m2 = R_REG(osh, &cc->clockcontrol_m2);
10762 + if ((orig_n == type3_table[i].n) &&
10763 + (orig_m2 == type3_table[i].m2)) {
10764 + goto done;
10765 + }
10766 +
10767 + /* Set the PLL controls */
10768 + W_REG(osh, clockcontrol_n, type3_table[i].n);
10769 + W_REG(osh, clockcontrol_m2, type3_table[i].m2);
10770 +
10771 + /* Reset */
10772 + sb_watchdog(sbh, 1);
10773 + while (1);
10774 + }
10775 + } else if ((pll_type == PLL_TYPE2) ||
10776 + (pll_type == PLL_TYPE4) ||
10777 + (pll_type == PLL_TYPE6) ||
10778 + (pll_type == PLL_TYPE7)) {
10779 + n4m_table_t *table = NULL, *te;
10780 + uint tabsz = 0;
10781 +
10782 + ASSERT(cc);
10783 +
10784 + orig_mips = R_REG(osh, &cc->clockcontrol_m3);
10785 +
10786 + switch (pll_type) {
10787 + case PLL_TYPE6: {
10788 + uint32 new_mips = 0;
10789 +
10790 + ret = TRUE;
10791 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
10792 + new_mips = CC_T6_MMASK;
10793 +
10794 + if (orig_mips == new_mips)
10795 + goto done;
10796 +
10797 + W_REG(osh, &cc->clockcontrol_m3, new_mips);
10798 + goto end_fill;
10799 + }
10800 + case PLL_TYPE2:
10801 + table = type2_table;
10802 + tabsz = ARRAYSIZE(type2_table);
10803 + break;
10804 + case PLL_TYPE4:
10805 + table = type4_table;
10806 + tabsz = ARRAYSIZE(type4_table);
10807 + break;
10808 + case PLL_TYPE7:
10809 + table = type7_table;
10810 + tabsz = ARRAYSIZE(type7_table);
10811 + break;
10812 + default:
10813 + ASSERT("No table for plltype" == NULL);
10814 + break;
10815 + }
10816 +
10817 + /* Store the current clock register values */
10818 + orig_m2 = R_REG(osh, &cc->clockcontrol_m2);
10819 + orig_ratio_parm = 0;
10820 + orig_ratio_cfg = 0;
10821 +
10822 + /* Look up current ratio */
10823 + for (i = 0; i < tabsz; i++) {
10824 + if ((orig_n == table[i].n) &&
10825 + (orig_sb == table[i].sb) &&
10826 + (orig_pci == table[i].pci33) &&
10827 + (orig_m2 == table[i].m2) &&
10828 + (orig_mips == table[i].m3)) {
10829 + orig_ratio_parm = table[i].ratio_parm;
10830 + orig_ratio_cfg = table[i].ratio_cfg;
10831 + break;
10832 + }
10833 + }
10834 +
10835 + /* Search for the closest MIPS clock greater or equal to a preferred value */
10836 + for (i = 0; i < tabsz; i++) {
10837 + ASSERT(table[i].mipsclock ==
10838 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
10839 + if ((mipsclock <= table[i].mipsclock) &&
10840 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
10841 + break;
10842 + }
10843 + if (i == tabsz) {
10844 + ret = FALSE;
10845 + goto done;
10846 + } else {
10847 + te = &table[i];
10848 + ret = TRUE;
10849 + }
10850 +
10851 + /* No PLL change */
10852 + if ((orig_n == te->n) &&
10853 + (orig_sb == te->sb) &&
10854 + (orig_pci == te->pci33) &&
10855 + (orig_m2 == te->m2) &&
10856 + (orig_mips == te->m3))
10857 + goto done;
10858 +
10859 + /* Set the PLL controls */
10860 + W_REG(osh, clockcontrol_n, te->n);
10861 + W_REG(osh, clockcontrol_sb, te->sb);
10862 + W_REG(osh, clockcontrol_pci, te->pci33);
10863 + W_REG(osh, &cc->clockcontrol_m2, te->m2);
10864 + W_REG(osh, &cc->clockcontrol_m3, te->m3);
10865 +
10866 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
10867 + if ((pll_type == PLL_TYPE7) && (te->sb != te->m2) &&
10868 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
10869 + W_REG(osh, &cc->chipcontrol,
10870 + R_REG(osh, &cc->chipcontrol) | 0x100);
10871 +
10872 + /* No ratio change */
10873 + if (sb_chip(sbh) != BCM4785_CHIP_ID) {
10874 + if (orig_ratio_parm == te->ratio_parm)
10875 + goto end_fill;
10876 + }
10877 +
10878 + /* Preload the code into the cache */
10879 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
10880 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
10881 + start = ((ulong) &&start_fill_4785) & ~(ic_lsize - 1);
10882 + end = ((ulong) &&end_fill_4785 + (ic_lsize - 1)) & ~(ic_lsize - 1);
10883 + }
10884 + else {
10885 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
10886 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
10887 + }
10888 + while (start < end) {
10889 + cache_op(start, Fill_I);
10890 + start += ic_lsize;
10891 + }
10892 +
10893 + /* Copy the handler */
10894 + start = (ulong) &handler;
10895 + end = (ulong) &afterhandler;
10896 + dst = KSEG1ADDR(0x180);
10897 + for (i = 0; i < (end - start); i += 4)
10898 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
10899 +
10900 + /* Preload the handler into the cache one line at a time */
10901 + for (i = 0; i < (end - start); i += ic_lsize)
10902 + cache_op(dst + i, Fill_I);
10903 +
10904 + /* Clear BEV bit */
10905 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
10906 +
10907 + /* Enable interrupts */
10908 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
10909 +
10910 + /* 4785 clock freq change procedures */
10911 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
10912 + start_fill_4785:
10913 + /* Switch to async */
10914 + MTC0(C0_BROADCOM, 4, (1 << 22));
10915 +
10916 + /* Set clock ratio in MIPS */
10917 + *dll_r1 = (*dll_r1 & 0xfffffff0) | (te->d11_r1 - 1);
10918 + *dll_r2 = te->d11_r2;
10919 +
10920 + /* Enable new settings in MIPS */
10921 + *dll_r1 = *dll_r1 | 0xc0000000;
10922 +
10923 + /* Set active cfg */
10924 + MTC0(C0_BROADCOM, 2, MFC0(C0_BROADCOM, 2) | (1 << 3) | 1);
10925 +
10926 + /* Fake soft reset (clock cfg registers not reset) */
10927 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | (1 << 2));
10928 +
10929 + /* Clear active cfg */
10930 + MTC0(C0_BROADCOM, 2, MFC0(C0_BROADCOM, 2) & ~(1 << 3));
10931 +
10932 + /* set watchdog timer */
10933 + W_REG(osh, &cc->watchdog, 20);
10934 + (void) R_REG(osh, &cc->chipid);
10935 +
10936 + /* wait for timer interrupt */
10937 + __asm__ __volatile__(
10938 + ".set\tmips3\n\t"
10939 + "sync\n\t"
10940 + "wait\n\t"
10941 + ".set\tmips0");
10942 + end_fill_4785:
10943 + while (1);
10944 + }
10945 + /* Generic clock freq change procedures */
10946 + else {
10947 + /* Enable MIPS timer interrupt */
10948 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
10949 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
10950 + ASSERT(mipsr);
10951 + W_REG(osh, &mipsr->intmask, 1);
10952 +
10953 + start_fill:
10954 + /* step 1, set clock ratios */
10955 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
10956 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
10957 +
10958 + /* step 2: program timer intr */
10959 + W_REG(osh, &mipsr->timer, 100);
10960 + (void) R_REG(osh, &mipsr->timer);
10961 +
10962 + /* step 3, switch to async */
10963 + sync_mode = MFC0(C0_BROADCOM, 4);
10964 + MTC0(C0_BROADCOM, 4, 1 << 22);
10965 +
10966 + /* step 4, set cfg active */
10967 + MTC0(C0_BROADCOM, 2, (1 << 3) | 1);
10968 +
10969 + /* steps 5 & 6 */
10970 + __asm__ __volatile__(
10971 + ".set\tmips3\n\t"
10972 + "wait\n\t"
10973 + ".set\tmips0");
10974 +
10975 + /* step 7, clear cfg active */
10976 + MTC0(C0_BROADCOM, 2, 0);
10977 +
10978 + /* Additional Step: set back to orig sync mode */
10979 + MTC0(C0_BROADCOM, 4, sync_mode);
10980 +
10981 + /* step 8, fake soft reset */
10982 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | (1 << 2));
10983 +
10984 + end_fill:
10985 + /* set watchdog timer */
10986 + W_REG(osh, &cc->watchdog, 20);
10987 + (void) R_REG(osh, &cc->chipid);
10988 +
10989 + /* wait for timer interrupt */
10990 + __asm__ __volatile__(
10991 + ".set\tmips3\n\t"
10992 + "sync\n\t"
10993 + "wait\n\t"
10994 + ".set\tmips0");
10995 + while (1);
10996 + }
10997 + }
10998 +
10999 +done:
11000 + /* Enable 4785 DLL */
11001 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
11002 + uint32 tmp;
11003 +
11004 + /* set mask to 1e, enable DLL (bit 0) */
11005 + *dll_ctrl |= 0x0041e021;
11006 +
11007 + /* enable aggressive hardware mode */
11008 + *dll_ctrl |= 0x00000080;
11009 +
11010 + /* wait for lock flag to clear */
11011 + while ((*dll_ctrl & 0x2) == 0);
11012 +
11013 + /* clear sticky flags (clear on write 1) */
11014 + tmp = *dll_ctrl;
11015 + *dll_ctrl = tmp;
11016 +
11017 + /* set mask to 5b'10001 */
11018 + *dll_ctrl = (*dll_ctrl & 0xfffc1fff) | 0x00022000;
11019 +
11020 + /* enable sync mode */
11021 + MTC0(C0_BROADCOM, 4, MFC0(C0_BROADCOM, 4) & 0xfe3fffff);
11022 + (void)MFC0(C0_BROADCOM, 4);
11023 + }
11024 +
11025 + /* switch back to previous core */
11026 + sb_setcoreidx(sbh, idx);
11027 +
11028 + return ret;
11029 +}
11030 +
11031 +void
11032 +BCMINITFN(enable_pfc)(uint32 mode)
11033 +{
11034 + ulong start, end;
11035 + uint ic_size, ic_lsize;
11036 +
11037 + /* If auto then choose the correct mode for this
11038 + * platform, currently we only ever select one mode
11039 + */
11040 + if (mode == PFC_AUTO)
11041 + mode = PFC_INST;
11042 +
11043 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
11044 +
11045 + /* enable prefetch cache if available */
11046 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
11047 + start = ((ulong) &&setpfc_start) & ~(ic_lsize - 1);
11048 + end = ((ulong) &&setpfc_end + (ic_lsize - 1)) & ~(ic_lsize - 1);
11049 +
11050 + /* Preload setpfc code into the cache one line at a time */
11051 + while (start < end) {
11052 + cache_op(start, Fill_I);
11053 + start += ic_lsize;
11054 + }
11055 +
11056 + /* Now set the pfc */
11057 + setpfc_start:
11058 + /* write range */
11059 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
11060 +
11061 + /* enable */
11062 + *(volatile uint32 *)PFC_CR0 = mode;
11063 + setpfc_end:
11064 + /* Compiler foder */
11065 + ic_size = 0;
11066 + }
11067 +}
11068 +
11069 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
11070 +uint32
11071 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
11072 +{
11073 + osl_t *osh;
11074 + sbmemcregs_t *memc;
11075 + uint32 ret = 0;
11076 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
11077 + uint idx, rev;
11078 +
11079 + osh = sb_osh(sbh);
11080 +
11081 + idx = sb_coreidx(sbh);
11082 +
11083 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
11084 + if (memc == 0)
11085 + goto out;
11086 +
11087 + rev = sb_corerev(sbh);
11088 +
11089 + config = R_REG(osh, &memc->config);
11090 + wr = R_REG(osh, &memc->wrncdlcor);
11091 + rd = R_REG(osh, &memc->rdncdlcor);
11092 + misc = R_REG(osh, &memc->miscdlyctl);
11093 + dqsg = R_REG(osh, &memc->dqsgatencdl);
11094 +
11095 + rd &= MEMC_RDNCDLCOR_RD_MASK;
11096 + wr &= MEMC_WRNCDLCOR_WR_MASK;
11097 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
11098 +
11099 + if (config & MEMC_CONFIG_DDR) {
11100 + ret = (wr << 16) | (rd << 8) | dqsg;
11101 + } else {
11102 + if (rev > 0)
11103 + cd = rd;
11104 + else
11105 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
11106 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
11107 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
11108 + ret = (sm << 16) | (sd << 8) | cd;
11109 + }
11110 +
11111 +out:
11112 + /* switch back to previous core */
11113 + sb_setcoreidx(sbh, idx);
11114 +
11115 + return ret;
11116 +}
11117 +
11118 +#if defined(BCMPERFSTATS)
11119 +/*
11120 + * CP0 Register 25 supports 4 semi-independent 32bit performance counters.
11121 + * $25 select 0, 1, 2, and 3 are the counters. The counters *decrement* (who thought this one up?)
11122 + * $25 select 4 and 5 each contain 2-16bit control fields, one for each of the 4 counters
11123 + * $25 select 6 is the global perf control register.
11124 + */
11125 +/* enable and start instruction counting */
11126 +
11127 +void
11128 +hndmips_perf_instrcount_enable()
11129 +{
11130 + MTC0(C0_PERFORMANCE, 6, 0x80000200); /* global enable perf counters */
11131 + MTC0(C0_PERFORMANCE, 4,
11132 + 0x8044 | MFC0(C0_PERFORMANCE, 4)); /* enable instruction counting for counter 0 */
11133 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter zero */
11134 +}
11135 +
11136 +/* enable and start I$ hit and I$ miss counting */
11137 +void
11138 +hndmips_perf_icachecount_enable(void)
11139 +{
11140 + MTC0(C0_PERFORMANCE, 6, 0x80000218); /* enable I$ counting */
11141 + MTC0(C0_PERFORMANCE, 4, 0x80148018); /* count I$ hits in cntr 0 and misses in cntr 1 */
11142 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter 0 - # I$ hits */
11143 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter 1 - # I$ misses */
11144 +}
11145 +
11146 +/* enable and start D$ hit and I$ miss counting */
11147 +void
11148 +hndmips_perf_dcachecount_enable(void)
11149 +{
11150 + MTC0(C0_PERFORMANCE, 6, 0x80000211); /* enable D$ counting */
11151 + MTC0(C0_PERFORMANCE, 4, 0x80248028); /* count D$ hits in cntr 0 and misses in cntr 1 */
11152 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter 0 - # D$ hits */
11153 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter 1 - # D$ misses */
11154 +}
11155 +
11156 +void
11157 +hndmips_perf_icache_miss_enable()
11158 +{
11159 + MTC0(C0_PERFORMANCE, 4,
11160 + 0x80140000 | MFC0(C0_PERFORMANCE, 4)); /* enable cache misses counting for counter 1 */
11161 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter one */
11162 +}
11163 +
11164 +
11165 +void
11166 +hndmips_perf_icache_hit_enable()
11167 +{
11168 + MTC0(C0_PERFORMANCE, 5, 0x8018 | MFC0(C0_PERFORMANCE, 5));
11169 + /* enable cache hits counting for counter 2 */
11170 + MTC0(C0_PERFORMANCE, 2, 0); /* zero counter 2 */
11171 +}
11172 +
11173 +uint32
11174 +hndmips_perf_read_instrcount()
11175 +{
11176 + return -(long)(MFC0(C0_PERFORMANCE, 0));
11177 +}
11178 +
11179 +uint32
11180 +hndmips_perf_read_cache_miss()
11181 +{
11182 + return -(long)(MFC0(C0_PERFORMANCE, 1));
11183 +}
11184 +
11185 +uint32
11186 +hndmips_perf_read_cache_hit()
11187 +{
11188 + return -(long)(MFC0(C0_PERFORMANCE, 2));
11189 +}
11190 +
11191 +#endif /* BCMINTERNAL | BCMPERFSTATS */
11192 diff -urN linux.old/arch/mips/bcm947xx/sbpci.c linux.dev/arch/mips/bcm947xx/sbpci.c
11193 --- linux.old/arch/mips/bcm947xx/sbpci.c 1970-01-01 01:00:00.000000000 +0100
11194 +++ linux.dev/arch/mips/bcm947xx/sbpci.c 2006-10-02 21:19:59.000000000 +0200
11195 @@ -0,0 +1,768 @@
11196 +/*
11197 + * Low-Level PCI and SB support for BCM47xx
11198 + *
11199 + * Copyright 2006, Broadcom Corporation
11200 + * All Rights Reserved.
11201 + *
11202 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11203 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11204 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11205 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11206 + *
11207 + * $Id: hndpci.c,v 1.1.1.3 2006/04/08 06:13:39 honor Exp $
11208 + */
11209 +
11210 +#include <typedefs.h>
11211 +#include <osl.h>
11212 +#include <pcicfg.h>
11213 +#include <bcmdevs.h>
11214 +#include <sbconfig.h>
11215 +#include <bcmutils.h>
11216 +#include <sbutils.h>
11217 +#include <sbpci.h>
11218 +#include <bcmendian.h>
11219 +#include <bcmnvram.h>
11220 +#include <hndcpu.h>
11221 +#include <hndmips.h>
11222 +#include <hndpci.h>
11223 +
11224 +/* debug/trace */
11225 +#ifdef BCMDBG_PCI
11226 +#define PCI_MSG(args) printf args
11227 +#else
11228 +#define PCI_MSG(args)
11229 +#endif /* BCMDBG_PCI */
11230 +
11231 +/* Can free sbpci_init() memory after boot */
11232 +#ifndef linux
11233 +#define __init
11234 +#endif /* linux */
11235 +
11236 +/* Emulated configuration space */
11237 +typedef struct {
11238 + int n;
11239 + uint size0;
11240 + uint size1;
11241 + uint size2;
11242 + uint size3;
11243 +} sb_bar_cfg_t;
11244 +static pci_config_regs sb_config_regs[SB_MAXCORES];
11245 +static sb_bar_cfg_t sb_bar_cfg[SB_MAXCORES];
11246 +
11247 +/* Links to emulated and real PCI configuration spaces */
11248 +#define MAXFUNCS 2
11249 +typedef struct {
11250 + pci_config_regs *emu; /* emulated PCI config */
11251 + pci_config_regs *pci; /* real PCI config */
11252 + sb_bar_cfg_t *bar; /* region sizes */
11253 +} sb_pci_cfg_t;
11254 +static sb_pci_cfg_t sb_pci_cfg[SB_MAXCORES][MAXFUNCS];
11255 +
11256 +/* Special emulated config space for non-existing device */
11257 +static pci_config_regs sb_pci_null = { 0xffff, 0xffff };
11258 +
11259 +/* Banned cores */
11260 +static uint16 pci_ban[SB_MAXCORES] = { 0 };
11261 +static uint pci_banned = 0;
11262 +
11263 +/* CardBus mode */
11264 +static bool cardbus = FALSE;
11265 +
11266 +/* Disable PCI host core */
11267 +static bool pci_disabled = FALSE;
11268 +
11269 +/* Host bridge slot #, default to 0 */
11270 +static uint8 pci_hbslot = 0;
11271 +
11272 +/* Internal macros */
11273 +#define PCI_SLOTAD_MAP 16 /* SLOT<n> mapps to AD<n+16> */
11274 +#define PCI_HBSBCFG_REV 8 /* MIN. core rev. required to
11275 + * access host bridge PCI cfg space
11276 + * from SB
11277 + */
11278 +
11279 +/*
11280 + * Functions for accessing external PCI configuration space
11281 + */
11282 +
11283 +/* Assume one-hot slot wiring */
11284 +#define PCI_SLOT_MAX 16 /* Max. PCI Slots */
11285 +
11286 +static uint32
11287 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
11288 +{
11289 + uint coreidx;
11290 + sbpciregs_t *regs;
11291 + uint32 addr = 0;
11292 + osl_t *osh;
11293 +
11294 + /* CardBusMode supports only one device */
11295 + if (cardbus && dev > 1)
11296 + return 0;
11297 +
11298 + osh = sb_osh(sbh);
11299 +
11300 + coreidx = sb_coreidx(sbh);
11301 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
11302 +
11303 + /* Type 0 transaction */
11304 + if (bus == 1) {
11305 + /* Skip unwired slots */
11306 + if (dev < PCI_SLOT_MAX) {
11307 + uint32 win;
11308 +
11309 + /* Slide the PCI window to the appropriate slot */
11310 + win = (SBTOPCI_CFG0 | ((1 << (dev + PCI_SLOTAD_MAP)) & SBTOPCI1_MASK));
11311 + W_REG(osh, &regs->sbtopci1, win);
11312 + addr = SB_PCI_CFG |
11313 + ((1 << (dev + PCI_SLOTAD_MAP)) & ~SBTOPCI1_MASK) |
11314 + (func << PCICFG_FUN_SHIFT) |
11315 + (off & ~3);
11316 + }
11317 + } else {
11318 + /* Type 1 transaction */
11319 + W_REG(osh, &regs->sbtopci1, SBTOPCI_CFG1);
11320 + addr = SB_PCI_CFG |
11321 + (bus << PCICFG_BUS_SHIFT) |
11322 + (dev << PCICFG_SLOT_SHIFT) |
11323 + (func << PCICFG_FUN_SHIFT) |
11324 + (off & ~3);
11325 + }
11326 +
11327 + sb_setcoreidx(sbh, coreidx);
11328 +
11329 + return addr;
11330 +}
11331 +
11332 +/*
11333 + * Read host bridge PCI config registers from Silicon Backplane (>=rev8).
11334 + *
11335 + * It returns TRUE to indicate that access to the host bridge's pci config
11336 + * from SB is ok, and values in 'addr' and 'val' are valid.
11337 + *
11338 + * It can only read registers at multiple of 4-bytes. Callers must pick up
11339 + * needed bytes from 'val' based on 'off' value. Value in 'addr' reflects
11340 + * the register address where value in 'val' is read.
11341 + */
11342 +static bool
11343 +sb_pcihb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off,
11344 + uint32 **addr, uint32 *val)
11345 +{
11346 + sbpciregs_t *regs;
11347 + osl_t *osh;
11348 + uint coreidx;
11349 + bool ret = FALSE;
11350 +
11351 + /* sanity check */
11352 + ASSERT(bus == 1);
11353 + ASSERT(dev == pci_hbslot);
11354 + ASSERT(func == 0);
11355 +
11356 + osh = sb_osh(sbh);
11357 +
11358 + /* read pci config when core rev >= 8 */
11359 + coreidx = sb_coreidx(sbh);
11360 + regs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
11361 + if (regs && sb_corerev(sbh) >= PCI_HBSBCFG_REV) {
11362 + *addr = (uint32 *)&regs->pcicfg[func][off >> 2];
11363 + *val = R_REG(osh, *addr);
11364 + ret = TRUE;
11365 + }
11366 + sb_setcoreidx(sbh, coreidx);
11367 +
11368 + return ret;
11369 +}
11370 +
11371 +int
11372 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11373 +{
11374 + uint32 addr = 0, *reg = NULL, val;
11375 + int ret = 0;
11376 +
11377 + /*
11378 + * Set value to -1 when:
11379 + * flag 'pci_disabled' is true;
11380 + * value of 'addr' is zero;
11381 + * REG_MAP() fails;
11382 + * BUSPROBE() fails;
11383 + */
11384 + if (pci_disabled)
11385 + val = 0xffffffff;
11386 + else if (bus == 1 && dev == pci_hbslot && func == 0 &&
11387 + sb_pcihb_read_config(sbh, bus, dev, func, off, &reg, &val))
11388 + ;
11389 + else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
11390 + ((reg = (uint32 *)REG_MAP(addr, len)) == 0) ||
11391 + (BUSPROBE(val, reg) != 0))
11392 + val = 0xffffffff;
11393 +
11394 + PCI_MSG(("%s: 0x%x <= 0x%p(0x%x), len %d, off 0x%x, buf 0x%p\n",
11395 + __FUNCTION__, val, reg, addr, len, off, buf));
11396 +
11397 + val >>= 8 * (off & 3);
11398 + if (len == 4)
11399 + *((uint32 *) buf) = val;
11400 + else if (len == 2)
11401 + *((uint16 *) buf) = (uint16) val;
11402 + else if (len == 1)
11403 + *((uint8 *) buf) = (uint8) val;
11404 + else
11405 + ret = -1;
11406 +
11407 + if (reg && addr)
11408 + REG_UNMAP(reg);
11409 +
11410 + return ret;
11411 +}
11412 +
11413 +int
11414 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11415 +{
11416 + osl_t *osh;
11417 + uint32 addr = 0, *reg = NULL, val;
11418 + int ret = 0;
11419 +
11420 + osh = sb_osh(sbh);
11421 +
11422 + /*
11423 + * Ignore write attempt when:
11424 + * flag 'pci_disabled' is true;
11425 + * value of 'addr' is zero;
11426 + * REG_MAP() fails;
11427 + * BUSPROBE() fails;
11428 + */
11429 + if (pci_disabled)
11430 + return 0;
11431 + else if (bus == 1 && dev == pci_hbslot && func == 0 &&
11432 + sb_pcihb_read_config(sbh, bus, dev, func, off, &reg, &val))
11433 + ;
11434 + else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
11435 + ((reg = (uint32 *) REG_MAP(addr, len)) == 0) ||
11436 + (BUSPROBE(val, reg) != 0))
11437 + goto done;
11438 +
11439 + if (len == 4)
11440 + val = *((uint32 *) buf);
11441 + else if (len == 2) {
11442 + val &= ~(0xffff << (8 * (off & 3)));
11443 + val |= *((uint16 *) buf) << (8 * (off & 3));
11444 + } else if (len == 1) {
11445 + val &= ~(0xff << (8 * (off & 3)));
11446 + val |= *((uint8 *) buf) << (8 * (off & 3));
11447 + } else {
11448 + ret = -1;
11449 + goto done;
11450 + }
11451 +
11452 + PCI_MSG(("%s: 0x%x => 0x%p\n", __FUNCTION__, val, reg));
11453 +
11454 + W_REG(osh, reg, val);
11455 +
11456 +done:
11457 + if (reg && addr)
11458 + REG_UNMAP(reg);
11459 +
11460 + return ret;
11461 +}
11462 +
11463 +/*
11464 + * Must access emulated PCI configuration at these locations even when
11465 + * the real PCI config space exists and is accessible.
11466 + *
11467 + * PCI_CFG_VID (0x00)
11468 + * PCI_CFG_DID (0x02)
11469 + * PCI_CFG_PROGIF (0x09)
11470 + * PCI_CFG_SUBCL (0x0a)
11471 + * PCI_CFG_BASECL (0x0b)
11472 + * PCI_CFG_HDR (0x0e)
11473 + * PCI_CFG_INT (0x3c)
11474 + * PCI_CFG_PIN (0x3d)
11475 + */
11476 +#define FORCE_EMUCFG(off, len) \
11477 + ((off == PCI_CFG_VID) || (off == PCI_CFG_DID) || \
11478 + (off == PCI_CFG_PROGIF) || \
11479 + (off == PCI_CFG_SUBCL) || (off == PCI_CFG_BASECL) || \
11480 + (off == PCI_CFG_HDR) || \
11481 + (off == PCI_CFG_INT) || (off == PCI_CFG_PIN))
11482 +
11483 +/* Sync the emulation registers and the real PCI config registers. */
11484 +static void
11485 +sb_pcid_read_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
11486 + uint off, uint len)
11487 +{
11488 + osl_t *osh;
11489 + uint oldidx;
11490 +
11491 + ASSERT(cfg);
11492 + ASSERT(cfg->emu);
11493 + ASSERT(cfg->pci);
11494 +
11495 + /* decide if real PCI config register access is necessary */
11496 + if (FORCE_EMUCFG(off, len))
11497 + return;
11498 +
11499 + osh = sb_osh(sbh);
11500 +
11501 + /* access to the real pci config space only when the core is up */
11502 + oldidx = sb_coreidx(sbh);
11503 + sb_setcoreidx(sbh, coreidx);
11504 + if (sb_iscoreup(sbh)) {
11505 + if (len == 4)
11506 + *(uint32 *)((ulong)cfg->emu + off) =
11507 + htol32(R_REG(osh, (uint32 *)((ulong)cfg->pci + off)));
11508 + else if (len == 2)
11509 + *(uint16 *)((ulong)cfg->emu + off) =
11510 + htol16(R_REG(osh, (uint16 *)((ulong)cfg->pci + off)));
11511 + else if (len == 1)
11512 + *(uint8 *)((ulong)cfg->emu + off) =
11513 + R_REG(osh, (uint8 *)((ulong)cfg->pci + off));
11514 + }
11515 + sb_setcoreidx(sbh, oldidx);
11516 +}
11517 +
11518 +static void
11519 +sb_pcid_write_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
11520 + uint off, uint len)
11521 +{
11522 + osl_t *osh;
11523 + uint oldidx;
11524 +
11525 + ASSERT(cfg);
11526 + ASSERT(cfg->emu);
11527 + ASSERT(cfg->pci);
11528 +
11529 + osh = sb_osh(sbh);
11530 +
11531 + /* decide if real PCI config register access is necessary */
11532 + if (FORCE_EMUCFG(off, len))
11533 + return;
11534 +
11535 + /* access to the real pci config space only when the core is up */
11536 + oldidx = sb_coreidx(sbh);
11537 + sb_setcoreidx(sbh, coreidx);
11538 + if (sb_iscoreup(sbh)) {
11539 + if (len == 4)
11540 + W_REG(osh, (uint32 *)((ulong)cfg->pci + off),
11541 + ltoh32(*(uint32 *)((ulong)cfg->emu + off)));
11542 + else if (len == 2)
11543 + W_REG(osh, (uint16 *)((ulong)cfg->pci + off),
11544 + ltoh16(*(uint16 *)((ulong)cfg->emu + off)));
11545 + else if (len == 1)
11546 + W_REG(osh, (uint8 *)((ulong)cfg->pci + off),
11547 + *(uint8 *)((ulong)cfg->emu + off));
11548 + }
11549 + sb_setcoreidx(sbh, oldidx);
11550 +}
11551 +
11552 +/*
11553 + * Functions for accessing translated SB configuration space
11554 + */
11555 +static int
11556 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11557 +{
11558 + pci_config_regs *cfg;
11559 +
11560 + if (dev >= SB_MAXCORES || func >= MAXFUNCS || (off + len) > sizeof(pci_config_regs))
11561 + return -1;
11562 + cfg = sb_pci_cfg[dev][func].emu;
11563 +
11564 + ASSERT(ISALIGNED(off, len));
11565 + ASSERT(ISALIGNED((uintptr)buf, len));
11566 +
11567 + /* use special config space if the device does not exist */
11568 + if (!cfg)
11569 + cfg = &sb_pci_null;
11570 + /* sync emulation with real PCI config if necessary */
11571 + else if (sb_pci_cfg[dev][func].pci)
11572 + sb_pcid_read_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
11573 +
11574 + if (len == 4)
11575 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
11576 + else if (len == 2)
11577 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
11578 + else if (len == 1)
11579 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
11580 + else
11581 + return -1;
11582 +
11583 + return 0;
11584 +}
11585 +
11586 +static int
11587 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11588 +{
11589 + uint coreidx;
11590 + void *regs;
11591 + pci_config_regs *cfg;
11592 + osl_t *osh;
11593 + sb_bar_cfg_t *bar;
11594 +
11595 + if (dev >= SB_MAXCORES || func >= MAXFUNCS || (off + len) > sizeof(pci_config_regs))
11596 + return -1;
11597 + cfg = sb_pci_cfg[dev][func].emu;
11598 + if (!cfg)
11599 + return -1;
11600 +
11601 + ASSERT(ISALIGNED(off, len));
11602 + ASSERT(ISALIGNED((uintptr)buf, len));
11603 +
11604 + osh = sb_osh(sbh);
11605 +
11606 + /* Emulate BAR sizing */
11607 + if (off >= OFFSETOF(pci_config_regs, base[0]) &&
11608 + off <= OFFSETOF(pci_config_regs, base[3]) &&
11609 + len == 4 && *((uint32 *) buf) == ~0) {
11610 + coreidx = sb_coreidx(sbh);
11611 + if ((regs = sb_setcoreidx(sbh, dev))) {
11612 + bar = sb_pci_cfg[dev][func].bar;
11613 + /* Highest numbered address match register */
11614 + if (off == OFFSETOF(pci_config_regs, base[0]))
11615 + cfg->base[0] = ~(bar->size0 - 1);
11616 + else if (off == OFFSETOF(pci_config_regs, base[1]) && bar->n >= 1)
11617 + cfg->base[1] = ~(bar->size1 - 1);
11618 + else if (off == OFFSETOF(pci_config_regs, base[2]) && bar->n >= 2)
11619 + cfg->base[2] = ~(bar->size2 - 1);
11620 + else if (off == OFFSETOF(pci_config_regs, base[3]) && bar->n >= 3)
11621 + cfg->base[3] = ~(bar->size3 - 1);
11622 + }
11623 + sb_setcoreidx(sbh, coreidx);
11624 + }
11625 + else if (len == 4)
11626 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
11627 + else if (len == 2)
11628 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
11629 + else if (len == 1)
11630 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
11631 + else
11632 + return -1;
11633 +
11634 + /* sync emulation with real PCI config if necessary */
11635 + if (sb_pci_cfg[dev][func].pci)
11636 + sb_pcid_write_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
11637 +
11638 + return 0;
11639 +}
11640 +
11641 +int
11642 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11643 +{
11644 + if (bus == 0)
11645 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
11646 + else
11647 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
11648 +}
11649 +
11650 +int
11651 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11652 +{
11653 + if (bus == 0)
11654 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
11655 + else
11656 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
11657 +}
11658 +
11659 +void
11660 +sbpci_ban(uint16 core)
11661 +{
11662 + if (pci_banned < ARRAYSIZE(pci_ban))
11663 + pci_ban[pci_banned++] = core;
11664 +}
11665 +
11666 +/*
11667 + * Initiliaze PCI core. Return 0 after a successful initialization.
11668 + * Otherwise return -1 to indicate there is no PCI core and return 1
11669 + * to indicate PCI core is disabled.
11670 + */
11671 +int __init
11672 +sbpci_init_pci(sb_t *sbh)
11673 +{
11674 + uint chip, chiprev, chippkg, host;
11675 + uint32 boardflags;
11676 + sbpciregs_t *pci;
11677 + sbconfig_t *sb;
11678 + uint32 val;
11679 + int ret = 0;
11680 + char *hbslot;
11681 + osl_t *osh;
11682 +
11683 + chip = sb_chip(sbh);
11684 + chiprev = sb_chiprev(sbh);
11685 + chippkg = sb_chippkg(sbh);
11686 +
11687 + osh = sb_osh(sbh);
11688 +
11689 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
11690 + printk("PCI: no core\n");
11691 + pci_disabled = TRUE;
11692 + return -1;
11693 + }
11694 +
11695 + if ((chip == 0x4310) && (chiprev == 0))
11696 + pci_disabled = TRUE;
11697 +
11698 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
11699 +
11700 + boardflags = (uint32) getintvar(NULL, "boardflags");
11701 +
11702 + /*
11703 + * The 200-pin BCM4712 package does not bond out PCI. Even when
11704 + * PCI is bonded out, some boards may leave the pins
11705 + * floating.
11706 + */
11707 + if (((chip == BCM4712_CHIP_ID) &&
11708 + ((chippkg == BCM4712SMALL_PKG_ID) ||
11709 + (chippkg == BCM4712MID_PKG_ID))) ||
11710 + (boardflags & BFL_NOPCI))
11711 + pci_disabled = TRUE;
11712 +
11713 + /* Enable the core */
11714 + sb_core_reset(sbh, 0, 0);
11715 +
11716 + /*
11717 + * If the PCI core should not be touched (disabled, not bonded
11718 + * out, or pins floating), do not even attempt to access core
11719 + * registers. Otherwise, try to determine if it is in host
11720 + * mode.
11721 + */
11722 + if (pci_disabled)
11723 + host = 0;
11724 + else
11725 + host = !BUSPROBE(val, &pci->control);
11726 +
11727 + if (!host) {
11728 + ret = 1;
11729 +
11730 + /* Disable PCI interrupts in client mode */
11731 + W_REG(osh, &sb->sbintvec, 0);
11732 +
11733 + /* Disable the PCI bridge in client mode */
11734 + sbpci_ban(SB_PCI);
11735 + sb_core_disable(sbh, 0);
11736 +
11737 + printk("PCI: Disabled\n");
11738 + } else {
11739 + printk("PCI: Initializing host\n");
11740 +
11741 + /* Disable PCI SBReqeustTimeout for BCM4785 */
11742 + if (chip == BCM4785_CHIP_ID) {
11743 + AND_REG(osh, &sb->sbimconfiglow, ~0x00000070);
11744 + sb_commit(sbh);
11745 + }
11746 +
11747 + /* Reset the external PCI bus and enable the clock */
11748 + W_REG(osh, &pci->control, 0x5); /* enable the tristate drivers */
11749 + W_REG(osh, &pci->control, 0xd); /* enable the PCI clock */
11750 + OSL_DELAY(150); /* delay > 100 us */
11751 + W_REG(osh, &pci->control, 0xf); /* deassert PCI reset */
11752 + /* Use internal arbiter and park REQ/GRNT at external master 0 */
11753 + W_REG(osh, &pci->arbcontrol, PCI_INT_ARB);
11754 + OSL_DELAY(1); /* delay 1 us */
11755 + if (sb_corerev(sbh) >= 8) {
11756 + val = getintvar(NULL, "parkid");
11757 + ASSERT(val <= PCI_PARKID_LAST);
11758 + OR_REG(osh, &pci->arbcontrol, val << PCI_PARKID_SHIFT);
11759 + OSL_DELAY(1);
11760 + }
11761 +
11762 + /* Enable CardBusMode */
11763 + cardbus = getintvar(NULL, "cardbus") == 1;
11764 + if (cardbus) {
11765 + printk("PCI: Enabling CardBus\n");
11766 + /* GPIO 1 resets the CardBus device on bcm94710ap */
11767 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
11768 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
11769 + W_REG(osh, &pci->sprom[0], R_REG(osh, &pci->sprom[0]) | 0x400);
11770 + }
11771 +
11772 + /* 64 MB I/O access window */
11773 + W_REG(osh, &pci->sbtopci0, SBTOPCI_IO);
11774 + /* 64 MB configuration access window */
11775 + W_REG(osh, &pci->sbtopci1, SBTOPCI_CFG0);
11776 + /* 1 GB memory access window */
11777 + W_REG(osh, &pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
11778 +
11779 + /* Host bridge slot # nvram overwrite */
11780 + if ((hbslot = nvram_get("pcihbslot"))) {
11781 + pci_hbslot = bcm_strtoul(hbslot, NULL, 0);
11782 + ASSERT(pci_hbslot < PCI_MAX_DEVICES);
11783 + }
11784 +
11785 + /* Enable PCI bridge BAR0 prefetch and burst */
11786 + val = 6;
11787 + sbpci_write_config(sbh, 1, pci_hbslot, 0, PCI_CFG_CMD, &val, sizeof(val));
11788 +
11789 + /* Enable PCI interrupts */
11790 + W_REG(osh, &pci->intmask, PCI_INTA);
11791 + }
11792 +
11793 + return ret;
11794 +}
11795 +
11796 +/*
11797 + * Get the PCI region address and size information.
11798 + */
11799 +static void __init
11800 +sbpci_init_regions(sb_t *sbh, uint func, pci_config_regs *cfg, sb_bar_cfg_t *bar)
11801 +{
11802 + osl_t *osh;
11803 + uint16 coreid;
11804 + void *regs;
11805 + sbconfig_t *sb;
11806 + uint32 base;
11807 +
11808 + osh = sb_osh(sbh);
11809 + coreid = sb_coreid(sbh);
11810 + regs = sb_coreregs(sbh);
11811 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11812 +
11813 + switch (coreid) {
11814 + case SB_USB20H:
11815 + base = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
11816 +
11817 + cfg->base[0] = func == 0 ? base : base + 0x800; /* OHCI/EHCI */
11818 + cfg->base[1] = 0;
11819 + cfg->base[2] = 0;
11820 + cfg->base[3] = 0;
11821 + cfg->base[4] = 0;
11822 + cfg->base[5] = 0;
11823 + bar->n = 1;
11824 + bar->size0 = func == 0 ? 0x200 : 0x100; /* OHCI/EHCI */
11825 + bar->size1 = 0;
11826 + bar->size2 = 0;
11827 + bar->size3 = 0;
11828 + break;
11829 + default:
11830 + cfg->base[0] = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
11831 + cfg->base[1] = htol32(sb_base(R_REG(osh, &sb->sbadmatch1)));
11832 + cfg->base[2] = htol32(sb_base(R_REG(osh, &sb->sbadmatch2)));
11833 + cfg->base[3] = htol32(sb_base(R_REG(osh, &sb->sbadmatch3)));
11834 + cfg->base[4] = 0;
11835 + cfg->base[5] = 0;
11836 + bar->n = (R_REG(osh, &sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
11837 + bar->size0 = sb_size(R_REG(osh, &sb->sbadmatch0));
11838 + bar->size1 = sb_size(R_REG(osh, &sb->sbadmatch1));
11839 + bar->size2 = sb_size(R_REG(osh, &sb->sbadmatch2));
11840 + bar->size3 = sb_size(R_REG(osh, &sb->sbadmatch3));
11841 + break;
11842 + }
11843 +}
11844 +
11845 +/*
11846 + * Construct PCI config spaces for SB cores so that they
11847 + * can be accessed as if they were PCI devices.
11848 + */
11849 +static void __init
11850 +sbpci_init_cores(sb_t *sbh)
11851 +{
11852 + uint chiprev, coreidx, i;
11853 + sbconfig_t *sb;
11854 + pci_config_regs *cfg, *pci;
11855 + sb_bar_cfg_t *bar;
11856 + void *regs;
11857 + osl_t *osh;
11858 + uint16 vendor, device;
11859 + uint16 coreid;
11860 + uint8 class, subclass, progif;
11861 + uint dev;
11862 + uint8 header;
11863 + uint func;
11864 +
11865 + chiprev = sb_chiprev(sbh);
11866 + coreidx = sb_coreidx(sbh);
11867 +
11868 + osh = sb_osh(sbh);
11869 +
11870 + /* Scan the SB bus */
11871 + bzero(sb_config_regs, sizeof(sb_config_regs));
11872 + bzero(sb_bar_cfg, sizeof(sb_bar_cfg));
11873 + bzero(sb_pci_cfg, sizeof(sb_pci_cfg));
11874 + memset(&sb_pci_null, -1, sizeof(sb_pci_null));
11875 + cfg = sb_config_regs;
11876 + bar = sb_bar_cfg;
11877 + for (dev = 0; dev < SB_MAXCORES; dev ++) {
11878 + /* Check if the core exists */
11879 + if (!(regs = sb_setcoreidx(sbh, dev)))
11880 + continue;
11881 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11882 +
11883 + /* Check if this core is banned */
11884 + coreid = sb_coreid(sbh);
11885 + for (i = 0; i < pci_banned; i++)
11886 + if (coreid == pci_ban[i])
11887 + break;
11888 + if (i < pci_banned)
11889 + continue;
11890 +
11891 + for (func = 0; func < MAXFUNCS; ++func) {
11892 + /* Make sure we won't go beyond the limit */
11893 + if (cfg >= &sb_config_regs[SB_MAXCORES]) {
11894 + printk("PCI: too many emulated devices\n");
11895 + goto done;
11896 + }
11897 +
11898 + /* Convert core id to pci id */
11899 + if (sb_corepciid(sbh, func, &vendor, &device, &class, &subclass,
11900 + &progif, &header))
11901 + continue;
11902 +
11903 + /*
11904 + * Differentiate real PCI config from emulated.
11905 + * non zero 'pci' indicate there is a real PCI config space
11906 + * for this device.
11907 + */
11908 + switch (device) {
11909 + case BCM47XX_GIGETH_ID:
11910 + pci = (pci_config_regs *)((uint32)regs + 0x800);
11911 + break;
11912 + case BCM47XX_SATAXOR_ID:
11913 + pci = (pci_config_regs *)((uint32)regs + 0x400);
11914 + break;
11915 + case BCM47XX_ATA100_ID:
11916 + pci = (pci_config_regs *)((uint32)regs + 0x800);
11917 + break;
11918 + default:
11919 + pci = NULL;
11920 + break;
11921 + }
11922 + /* Supported translations */
11923 + cfg->vendor = htol16(vendor);
11924 + cfg->device = htol16(device);
11925 + cfg->rev_id = chiprev;
11926 + cfg->prog_if = progif;
11927 + cfg->sub_class = subclass;
11928 + cfg->base_class = class;
11929 + cfg->header_type = header;
11930 + sbpci_init_regions(sbh, func, cfg, bar);
11931 + /* Save core interrupt flag */
11932 + cfg->int_pin = R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
11933 + /* Save core interrupt assignment */
11934 + cfg->int_line = sb_irq(sbh);
11935 + /* Indicate there is no SROM */
11936 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
11937 +
11938 + /* Point to the PCI config spaces */
11939 + sb_pci_cfg[dev][func].emu = cfg;
11940 + sb_pci_cfg[dev][func].pci = pci;
11941 + sb_pci_cfg[dev][func].bar = bar;
11942 + cfg ++;
11943 + bar ++;
11944 + }
11945 + }
11946 +
11947 +done:
11948 + sb_setcoreidx(sbh, coreidx);
11949 +}
11950 +
11951 +/*
11952 + * Initialize PCI core and construct PCI config spaces for SB cores.
11953 + * Must propagate sbpci_init_pci() return value to the caller to let
11954 + * them know the PCI core initialization status.
11955 + */
11956 +int __init
11957 +sbpci_init(sb_t *sbh)
11958 +{
11959 + int status = sbpci_init_pci(sbh);
11960 + sbpci_init_cores(sbh);
11961 + return status;
11962 +}
11963 +
11964 diff -urN linux.old/arch/mips/bcm947xx/sbutils.c linux.dev/arch/mips/bcm947xx/sbutils.c
11965 --- linux.old/arch/mips/bcm947xx/sbutils.c 1970-01-01 01:00:00.000000000 +0100
11966 +++ linux.dev/arch/mips/bcm947xx/sbutils.c 2006-10-02 21:19:59.000000000 +0200
11967 @@ -0,0 +1,3081 @@
11968 +/*
11969 + * Misc utility routines for accessing chip-specific features
11970 + * of the SiliconBackplane-based Broadcom chips.
11971 + *
11972 + * Copyright 2006, Broadcom Corporation
11973 + * All Rights Reserved.
11974 + *
11975 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11976 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11977 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11978 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11979 + * $Id: sbutils.c,v 1.10 2006/04/08 07:12:42 honor Exp $
11980 + */
11981 +
11982 +#include <typedefs.h>
11983 +#include <bcmdefs.h>
11984 +#include <osl.h>
11985 +#include <bcmutils.h>
11986 +#include <sbutils.h>
11987 +#include <bcmdevs.h>
11988 +#include <sbconfig.h>
11989 +#include <sbchipc.h>
11990 +#include <sbpci.h>
11991 +#include <sbpcie.h>
11992 +#include <pcicfg.h>
11993 +#include <sbpcmcia.h>
11994 +#include <sbextif.h>
11995 +#include <sbsocram.h>
11996 +#include <bcmsrom.h>
11997 +#ifdef __mips__
11998 +#include <mipsinc.h>
11999 +#endif /* __mips__ */
12000 +
12001 +/* debug/trace */
12002 +#define SB_ERROR(args)
12003 +
12004 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
12005 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
12006 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
12007 +
12008 +/* misc sb info needed by some of the routines */
12009 +typedef struct sb_info {
12010 +
12011 + struct sb_pub sb; /* back plane public state (must be first field) */
12012 +
12013 + void *osh; /* osl os handle */
12014 + void *sdh; /* bcmsdh handle */
12015 +
12016 + void *curmap; /* current regs va */
12017 + void *regs[SB_MAXCORES]; /* other regs va */
12018 +
12019 + uint curidx; /* current core index */
12020 + uint dev_coreid; /* the core provides driver functions */
12021 +
12022 + bool memseg; /* flag to toggle MEM_SEG register */
12023 +
12024 + uint gpioidx; /* gpio control core index */
12025 + uint gpioid; /* gpio control coretype */
12026 +
12027 + uint numcores; /* # discovered cores */
12028 + uint coreid[SB_MAXCORES]; /* id of each core */
12029 +
12030 + void *intr_arg; /* interrupt callback function arg */
12031 + sb_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
12032 + sb_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
12033 + sb_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
12034 +
12035 +} sb_info_t;
12036 +
12037 +/* local prototypes */
12038 +static sb_info_t * sb_doattach(sb_info_t *si, uint devid, osl_t *osh, void *regs,
12039 + uint bustype, void *sdh, char **vars, uint *varsz);
12040 +static void sb_scan(sb_info_t *si);
12041 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
12042 +static uint _sb_coreidx(sb_info_t *si);
12043 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
12044 +static uint sb_pcidev2chip(uint pcidev);
12045 +static uint sb_chip2numcores(uint chip);
12046 +static bool sb_ispcie(sb_info_t *si);
12047 +static bool sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen);
12048 +static int sb_pci_fixcfg(sb_info_t *si);
12049 +
12050 +/* routines to access mdio slave device registers */
12051 +static int sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint readdr, uint val);
12052 +static void sb_war30841(sb_info_t *si);
12053 +
12054 +/* delay needed between the mdio control/ mdiodata register data access */
12055 +#define PR28829_DELAY() OSL_DELAY(10)
12056 +
12057 +/* size that can take bitfielddump */
12058 +#define BITFIELD_DUMP_SIZE 32
12059 +
12060 +/* global variable to indicate reservation/release of gpio's */
12061 +static uint32 sb_gpioreservation = 0;
12062 +
12063 +#define SB_INFO(sbh) (sb_info_t*)sbh
12064 +#define SET_SBREG(si, r, mask, val) \
12065 + W_SBREG((si), (r), ((R_SBREG((si), (r)) & ~(mask)) | (val)))
12066 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && \
12067 + ISALIGNED((x), SB_CORE_SIZE))
12068 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
12069 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
12070 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
12071 +#define BADIDX (SB_MAXCORES+1)
12072 +#define NOREV -1 /* Invalid rev */
12073 +
12074 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
12075 +#define PCIE(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCIE))
12076 +
12077 +/* sonicsrev */
12078 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
12079 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
12080 +
12081 +#define R_SBREG(si, sbr) sb_read_sbreg((si), (sbr))
12082 +#define W_SBREG(si, sbr, v) sb_write_sbreg((si), (sbr), (v))
12083 +#define AND_SBREG(si, sbr, v) W_SBREG((si), (sbr), (R_SBREG((si), (sbr)) & (v)))
12084 +#define OR_SBREG(si, sbr, v) W_SBREG((si), (sbr), (R_SBREG((si), (sbr)) | (v)))
12085 +
12086 +/*
12087 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
12088 + * after core switching to avoid invalid register accesss inside ISR.
12089 + */
12090 +#define INTR_OFF(si, intr_val) \
12091 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
12092 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
12093 +#define INTR_RESTORE(si, intr_val) \
12094 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
12095 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
12096 +
12097 +/* dynamic clock control defines */
12098 +#define LPOMINFREQ 25000 /* low power oscillator min */
12099 +#define LPOMAXFREQ 43000 /* low power oscillator max */
12100 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
12101 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
12102 +#define PCIMINFREQ 25000000 /* 25 MHz */
12103 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
12104 +
12105 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
12106 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
12107 +
12108 +/* different register spaces to access thr'u pcie indirect access */
12109 +#define PCIE_CONFIGREGS 1 /* Access to config space */
12110 +#define PCIE_PCIEREGS 2 /* Access to pcie registers */
12111 +
12112 +/* GPIO Based LED powersave defines */
12113 +#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
12114 +#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
12115 +
12116 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
12117 +
12118 +static uint32
12119 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
12120 +{
12121 + uint8 tmp;
12122 + uint32 val, intr_val = 0;
12123 +
12124 +
12125 + /*
12126 + * compact flash only has 11 bits address, while we needs 12 bits address.
12127 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
12128 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
12129 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
12130 + */
12131 + if (si->memseg) {
12132 + INTR_OFF(si, intr_val);
12133 + tmp = 1;
12134 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12135 + sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
12136 + }
12137 +
12138 + val = R_REG(si->osh, sbr);
12139 +
12140 + if (si->memseg) {
12141 + tmp = 0;
12142 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12143 + INTR_RESTORE(si, intr_val);
12144 + }
12145 +
12146 + return (val);
12147 +}
12148 +
12149 +static void
12150 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
12151 +{
12152 + uint8 tmp;
12153 + volatile uint32 dummy;
12154 + uint32 intr_val = 0;
12155 +
12156 +
12157 + /*
12158 + * compact flash only has 11 bits address, while we needs 12 bits address.
12159 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
12160 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
12161 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
12162 + */
12163 + if (si->memseg) {
12164 + INTR_OFF(si, intr_val);
12165 + tmp = 1;
12166 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12167 + sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
12168 + }
12169 +
12170 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12171 +#ifdef IL_BIGENDIAN
12172 + dummy = R_REG(si->osh, sbr);
12173 + W_REG(si->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
12174 + dummy = R_REG(si->osh, sbr);
12175 + W_REG(si->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
12176 +#else
12177 + dummy = R_REG(si->osh, sbr);
12178 + W_REG(si->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
12179 + dummy = R_REG(si->osh, sbr);
12180 + W_REG(si->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
12181 +#endif /* IL_BIGENDIAN */
12182 + } else
12183 + W_REG(si->osh, sbr, v);
12184 +
12185 + if (si->memseg) {
12186 + tmp = 0;
12187 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12188 + INTR_RESTORE(si, intr_val);
12189 + }
12190 +}
12191 +
12192 +/*
12193 + * Allocate a sb handle.
12194 + * devid - pci device id (used to determine chip#)
12195 + * osh - opaque OS handle
12196 + * regs - virtual address of initial core registers
12197 + * bustype - pci/pcmcia/sb/sdio/etc
12198 + * vars - pointer to a pointer area for "environment" variables
12199 + * varsz - pointer to int to return the size of the vars
12200 + */
12201 +sb_t *
12202 +BCMINITFN(sb_attach)(uint devid, osl_t *osh, void *regs,
12203 + uint bustype, void *sdh, char **vars, uint *varsz)
12204 +{
12205 + sb_info_t *si;
12206 +
12207 + /* alloc sb_info_t */
12208 + if ((si = MALLOC(osh, sizeof (sb_info_t))) == NULL) {
12209 + SB_ERROR(("sb_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
12210 + return (NULL);
12211 + }
12212 +
12213 + if (sb_doattach(si, devid, osh, regs, bustype, sdh, vars, (uint*)varsz) == NULL) {
12214 + MFREE(osh, si, sizeof(sb_info_t));
12215 + return (NULL);
12216 + }
12217 +
12218 + return (sb_t *)si;
12219 +}
12220 +
12221 +/* Using sb_kattach depends on SB_BUS support, either implicit */
12222 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
12223 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
12224 +
12225 +/* global kernel resource */
12226 +static sb_info_t ksi;
12227 +static bool ksi_attached = FALSE;
12228 +
12229 +/* generic kernel variant of sb_attach() */
12230 +sb_t *
12231 +BCMINITFN(sb_kattach)(void)
12232 +{
12233 + osl_t *osh = NULL;
12234 + uint32 *regs;
12235 +
12236 + if (!ksi_attached) {
12237 + uint32 cid;
12238 +
12239 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
12240 + cid = R_REG(osh, (uint32 *)regs);
12241 + if (((cid & CID_ID_MASK) == BCM4712_CHIP_ID) &&
12242 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
12243 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
12244 + uint32 *scc, val;
12245 +
12246 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
12247 + val = R_REG(osh, scc);
12248 + SB_ERROR((" initial scc = 0x%x\n", val));
12249 + val |= SCC_SS_XTAL;
12250 + W_REG(osh, scc, val);
12251 + }
12252 +
12253 + if (sb_doattach(&ksi, BCM4710_DEVICE_ID, osh, (void*)regs,
12254 + SB_BUS, NULL, NULL, NULL) == NULL) {
12255 + return NULL;
12256 + }
12257 + else
12258 + ksi_attached = TRUE;
12259 + }
12260 +
12261 + return (sb_t *)&ksi;
12262 +}
12263 +#endif /* !BCMBUSTYPE || (BCMBUSTYPE == SB_BUS) */
12264 +
12265 +static sb_info_t *
12266 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
12267 + uint bustype, void *sdh, char **vars, uint *varsz)
12268 +{
12269 + uint origidx;
12270 + chipcregs_t *cc;
12271 + sbconfig_t *sb;
12272 + uint32 w;
12273 +
12274 + ASSERT(GOODREGS(regs));
12275 +
12276 + bzero((uchar*)si, sizeof(sb_info_t));
12277 +
12278 + si->sb.buscoreidx = si->gpioidx = BADIDX;
12279 +
12280 + si->curmap = regs;
12281 + si->sdh = sdh;
12282 + si->osh = osh;
12283 +
12284 + /* check to see if we are a sb core mimic'ing a pci core */
12285 + if (bustype == PCI_BUS) {
12286 + if (OSL_PCI_READ_CONFIG(si->osh, PCI_SPROM_CONTROL, sizeof(uint32)) == 0xffffffff) {
12287 + SB_ERROR(("%s: incoming bus is PCI but it's a lie, switching to SB "
12288 + "devid:0x%x\n", __FUNCTION__, devid));
12289 + bustype = SB_BUS;
12290 + }
12291 + }
12292 +
12293 + si->sb.bustype = bustype;
12294 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
12295 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
12296 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
12297 + return NULL;
12298 + }
12299 +
12300 + /* need to set memseg flag for CF card first before any sb registers access */
12301 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
12302 + si->memseg = TRUE;
12303 +
12304 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
12305 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
12306 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
12307 +
12308 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12309 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32));
12310 + if (!GOODCOREADDR(w))
12311 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32), SB_ENUM_BASE);
12312 + }
12313 +
12314 + /* initialize current core index value */
12315 + si->curidx = _sb_coreidx(si);
12316 +
12317 + if (si->curidx == BADIDX) {
12318 + SB_ERROR(("sb_doattach: bad core index\n"));
12319 + return NULL;
12320 + }
12321 +
12322 + /* get sonics backplane revision */
12323 + sb = REGS2SB(si->curmap);
12324 + si->sb.sonicsrev = (R_SBREG(si, &sb->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
12325 +
12326 + /* keep and reuse the initial register mapping */
12327 + origidx = si->curidx;
12328 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
12329 + si->regs[origidx] = regs;
12330 +
12331 + /* is core-0 a chipcommon core? */
12332 + si->numcores = 1;
12333 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
12334 + if (sb_coreid(&si->sb) != SB_CC)
12335 + cc = NULL;
12336 +
12337 + /* determine chip id and rev */
12338 + if (cc) {
12339 + /* chip common core found! */
12340 + si->sb.chip = R_REG(si->osh, &cc->chipid) & CID_ID_MASK;
12341 + si->sb.chiprev = (R_REG(si->osh, &cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
12342 + si->sb.chippkg = (R_REG(si->osh, &cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
12343 + } else {
12344 + /* no chip common core -- must convert device id to chip id */
12345 + if ((si->sb.chip = sb_pcidev2chip(devid)) == 0) {
12346 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
12347 + sb_setcoreidx(&si->sb, origidx);
12348 + return NULL;
12349 + }
12350 + }
12351 +
12352 + /* get chipcommon rev */
12353 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
12354 +
12355 + /* determine numcores */
12356 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
12357 + si->numcores = (R_REG(si->osh, &cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
12358 + else
12359 + si->numcores = sb_chip2numcores(si->sb.chip);
12360 +
12361 + /* return to original core */
12362 + sb_setcoreidx(&si->sb, origidx);
12363 +
12364 + /* sanity checks */
12365 + ASSERT(si->sb.chip);
12366 +
12367 + /* scan for cores */
12368 + sb_scan(si);
12369 +
12370 + /* fixup necessary chip/core configurations */
12371 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12372 + if (sb_pci_fixcfg(si)) {
12373 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
12374 + return NULL;
12375 + }
12376 + }
12377 +
12378 + /* srom_var_init() depends on sb_scan() info */
12379 + if (srom_var_init(si, si->sb.bustype, si->curmap, si->osh, vars, varsz)) {
12380 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
12381 + return (NULL);
12382 + }
12383 +
12384 + if (cc == NULL) {
12385 + /*
12386 + * The chip revision number is hardwired into all
12387 + * of the pci function config rev fields and is
12388 + * independent from the individual core revision numbers.
12389 + * For example, the "A0" silicon of each chip is chip rev 0.
12390 + * For PCMCIA we get it from the CIS instead.
12391 + */
12392 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12393 + ASSERT(vars);
12394 + si->sb.chiprev = getintvar(*vars, "chiprev");
12395 + } else if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12396 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_REV, sizeof(uint32));
12397 + si->sb.chiprev = w & 0xff;
12398 + } else
12399 + si->sb.chiprev = 0;
12400 + }
12401 +
12402 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12403 + w = getintvar(*vars, "regwindowsz");
12404 + si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
12405 + }
12406 +
12407 + /* gpio control core is required */
12408 + if (!GOODIDX(si->gpioidx)) {
12409 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
12410 + return NULL;
12411 + }
12412 +
12413 + /* get boardtype and boardrev */
12414 + switch (BUSTYPE(si->sb.bustype)) {
12415 + case PCI_BUS:
12416 + /* do a pci config read to get subsystem id and subvendor id */
12417 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_SVID, sizeof(uint32));
12418 + si->sb.boardvendor = w & 0xffff;
12419 + si->sb.boardtype = (w >> 16) & 0xffff;
12420 + break;
12421 +
12422 + case PCMCIA_BUS:
12423 + case SDIO_BUS:
12424 + si->sb.boardvendor = getintvar(*vars, "manfid");
12425 + si->sb.boardtype = getintvar(*vars, "prodid");
12426 + break;
12427 +
12428 + case SB_BUS:
12429 + case JTAG_BUS:
12430 + si->sb.boardvendor = VENDOR_BROADCOM;
12431 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
12432 + si->sb.boardtype = 0xffff;
12433 + break;
12434 + }
12435 +
12436 + if (si->sb.boardtype == 0) {
12437 + SB_ERROR(("sb_doattach: unknown board type\n"));
12438 + ASSERT(si->sb.boardtype);
12439 + }
12440 +
12441 + /* setup the GPIO based LED powersave register */
12442 + if (si->sb.ccrev >= 16) {
12443 + if ((vars == NULL) || ((w = getintvar(*vars, "leddc")) == 0))
12444 + w = DEFAULT_GPIOTIMERVAL;
12445 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
12446 + }
12447 + if ((si->sb.chip == BCM4311_CHIP_ID) && (si->sb.chiprev <= 1)) {
12448 + /* set proper clk setup delays before forcing HT */
12449 + sb_clkctl_init((void *)si);
12450 + sb_corereg((void*)si, SB_CC_IDX, OFFSETOF(chipcregs_t, system_clk_ctl),
12451 + SYCC_HR, SYCC_HR);
12452 + }
12453 +
12454 +
12455 + return (si);
12456 +}
12457 +
12458 +uint
12459 +sb_coreid(sb_t *sbh)
12460 +{
12461 + sb_info_t *si;
12462 + sbconfig_t *sb;
12463 +
12464 + si = SB_INFO(sbh);
12465 + sb = REGS2SB(si->curmap);
12466 +
12467 + return ((R_SBREG(si, &sb->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
12468 +}
12469 +
12470 +uint
12471 +sb_coreidx(sb_t *sbh)
12472 +{
12473 + sb_info_t *si;
12474 +
12475 + si = SB_INFO(sbh);
12476 + return (si->curidx);
12477 +}
12478 +
12479 +/* return current index of core */
12480 +static uint
12481 +_sb_coreidx(sb_info_t *si)
12482 +{
12483 + sbconfig_t *sb;
12484 + uint32 sbaddr = 0;
12485 +
12486 + ASSERT(si);
12487 +
12488 + switch (BUSTYPE(si->sb.bustype)) {
12489 + case SB_BUS:
12490 + sb = REGS2SB(si->curmap);
12491 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
12492 + break;
12493 +
12494 + case PCI_BUS:
12495 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32));
12496 + break;
12497 +
12498 + case PCMCIA_BUS: {
12499 + uint8 tmp = 0;
12500 +
12501 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
12502 + sbaddr = (uint)tmp << 12;
12503 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
12504 + sbaddr |= (uint)tmp << 16;
12505 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
12506 + sbaddr |= (uint)tmp << 24;
12507 + break;
12508 + }
12509 +
12510 +#ifdef BCMJTAG
12511 + case JTAG_BUS:
12512 + sbaddr = (uint32)si->curmap;
12513 + break;
12514 +#endif /* BCMJTAG */
12515 +
12516 + default:
12517 + ASSERT(0);
12518 + }
12519 +
12520 + if (!GOODCOREADDR(sbaddr))
12521 + return BADIDX;
12522 +
12523 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
12524 +}
12525 +
12526 +uint
12527 +sb_corevendor(sb_t *sbh)
12528 +{
12529 + sb_info_t *si;
12530 + sbconfig_t *sb;
12531 +
12532 + si = SB_INFO(sbh);
12533 + sb = REGS2SB(si->curmap);
12534 +
12535 + return ((R_SBREG(si, &sb->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
12536 +}
12537 +
12538 +uint
12539 +sb_corerev(sb_t *sbh)
12540 +{
12541 + sb_info_t *si;
12542 + sbconfig_t *sb;
12543 + uint sbidh;
12544 +
12545 + si = SB_INFO(sbh);
12546 + sb = REGS2SB(si->curmap);
12547 + sbidh = R_SBREG(si, &sb->sbidhigh);
12548 +
12549 + return (SBCOREREV(sbidh));
12550 +}
12551 +
12552 +void *
12553 +sb_osh(sb_t *sbh)
12554 +{
12555 + sb_info_t *si;
12556 +
12557 + si = SB_INFO(sbh);
12558 + return si->osh;
12559 +}
12560 +
12561 +void
12562 +sb_setosh(sb_t *sbh, osl_t *osh)
12563 +{
12564 + sb_info_t *si;
12565 +
12566 + si = SB_INFO(sbh);
12567 + if (si->osh != NULL) {
12568 + SB_ERROR(("osh is already set....\n"));
12569 + ASSERT(!si->osh);
12570 + }
12571 + si->osh = osh;
12572 +}
12573 +
12574 +/* set/clear sbtmstatelow core-specific flags */
12575 +uint32
12576 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
12577 +{
12578 + sb_info_t *si;
12579 + sbconfig_t *sb;
12580 + uint32 w;
12581 +
12582 + si = SB_INFO(sbh);
12583 + sb = REGS2SB(si->curmap);
12584 +
12585 + ASSERT((val & ~mask) == 0);
12586 +
12587 + /* mask and set */
12588 + if (mask || val) {
12589 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
12590 + W_SBREG(si, &sb->sbtmstatelow, w);
12591 + }
12592 +
12593 + /* return the new value */
12594 + return (R_SBREG(si, &sb->sbtmstatelow));
12595 +}
12596 +
12597 +/* set/clear sbtmstatehigh core-specific flags */
12598 +uint32
12599 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
12600 +{
12601 + sb_info_t *si;
12602 + sbconfig_t *sb;
12603 + uint32 w;
12604 +
12605 + si = SB_INFO(sbh);
12606 + sb = REGS2SB(si->curmap);
12607 +
12608 + ASSERT((val & ~mask) == 0);
12609 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
12610 +
12611 + /* mask and set */
12612 + if (mask || val) {
12613 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
12614 + W_SBREG(si, &sb->sbtmstatehigh, w);
12615 + }
12616 +
12617 + /* return the new value */
12618 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
12619 +}
12620 +
12621 +/* Run bist on current core. Caller needs to take care of core-specific bist hazards */
12622 +int
12623 +sb_corebist(sb_t *sbh)
12624 +{
12625 + uint32 sblo;
12626 + sb_info_t *si;
12627 + sbconfig_t *sb;
12628 + int result = 0;
12629 +
12630 + si = SB_INFO(sbh);
12631 + sb = REGS2SB(si->curmap);
12632 +
12633 + sblo = R_SBREG(si, &sb->sbtmstatelow);
12634 + W_SBREG(si, &sb->sbtmstatelow, (sblo | SBTML_FGC | SBTML_BE));
12635 +
12636 + SPINWAIT(((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BISTD) == 0), 100000);
12637 +
12638 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BISTF)
12639 + result = BCME_ERROR;
12640 +
12641 + W_SBREG(si, &sb->sbtmstatelow, sblo);
12642 +
12643 + return result;
12644 +}
12645 +
12646 +bool
12647 +sb_iscoreup(sb_t *sbh)
12648 +{
12649 + sb_info_t *si;
12650 + sbconfig_t *sb;
12651 +
12652 + si = SB_INFO(sbh);
12653 + sb = REGS2SB(si->curmap);
12654 +
12655 + return ((R_SBREG(si, &sb->sbtmstatelow) &
12656 + (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
12657 +}
12658 +
12659 +/*
12660 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
12661 + * switch back to the original core, and return the new value.
12662 + *
12663 + * When using the silicon backplane, no fidleing with interrupts or core switches are needed.
12664 + *
12665 + * Also, when using pci/pcie, we can optimize away the core switching for pci registers
12666 + * and (on newer pci cores) chipcommon registers.
12667 + */
12668 +static uint
12669 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
12670 +{
12671 + uint origidx = 0;
12672 + uint32 *r = NULL;
12673 + uint w;
12674 + uint intr_val = 0;
12675 + bool fast = FALSE;
12676 +
12677 + ASSERT(GOODIDX(coreidx));
12678 + ASSERT(regoff < SB_CORE_SIZE);
12679 + ASSERT((val & ~mask) == 0);
12680 +
12681 +#ifdef notyet
12682 + if (si->sb.bustype == SB_BUS) {
12683 + /* If internal bus, we can always get at everything */
12684 + fast = TRUE;
12685 + r = (uint32 *)((uchar *)si->regs[coreidx] + regoff);
12686 + } else if (si->sb.bustype == PCI_BUS) {
12687 + /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
12688 +
12689 + if ((si->coreid[coreidx] == SB_CC) &&
12690 + ((si->sb.buscoretype == SB_PCIE) ||
12691 + (si->sb.buscorerev >= 13))) {
12692 + /* Chipc registers are mapped at 12KB */
12693 +
12694 + fast = TRUE;
12695 + r = (uint32 *)((char *)si->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
12696 + } else if (si->sb.buscoreidx == coreidx) {
12697 + /* pci registers are at either in the last 2KB of an 8KB window
12698 + * or, in pcie and pci rev 13 at 8KB
12699 + */
12700 + fast = TRUE;
12701 + if ((si->sb.buscoretype == SB_PCIE) ||
12702 + (si->sb.buscorerev >= 13))
12703 + r = (uint32 *)((char *)si->curmap +
12704 + PCI_16KB0_PCIREGS_OFFSET + regoff);
12705 + else
12706 + r = (uint32 *)((char *)si->curmap +
12707 + ((regoff >= SBCONFIGOFF) ?
12708 + PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
12709 + regoff);
12710 + }
12711 + }
12712 +#endif /* notyet */
12713 +
12714 + if (!fast) {
12715 + INTR_OFF(si, intr_val);
12716 +
12717 + /* save current core index */
12718 + origidx = sb_coreidx(&si->sb);
12719 +
12720 + /* switch core */
12721 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
12722 + }
12723 + ASSERT(r);
12724 +
12725 + /* mask and set */
12726 + if (mask || val) {
12727 + if (regoff >= SBCONFIGOFF) {
12728 + w = (R_SBREG(si, r) & ~mask) | val;
12729 + W_SBREG(si, r, w);
12730 + } else {
12731 + w = (R_REG(si->osh, r) & ~mask) | val;
12732 + W_REG(si->osh, r, w);
12733 + }
12734 + }
12735 +
12736 + /* readback */
12737 + if (regoff >= SBCONFIGOFF)
12738 + w = R_SBREG(si, r);
12739 + else
12740 + w = R_REG(si->osh, r);
12741 +
12742 + if (!fast) {
12743 + /* restore core index */
12744 + if (origidx != coreidx)
12745 + sb_setcoreidx(&si->sb, origidx);
12746 +
12747 + INTR_RESTORE(si, intr_val);
12748 + }
12749 +
12750 + return (w);
12751 +}
12752 +
12753 +#define DWORD_ALIGN(x) (x & ~(0x03))
12754 +#define BYTE_POS(x) (x & 0x3)
12755 +#define WORD_POS(x) (x & 0x1)
12756 +
12757 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
12758 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
12759 +
12760 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
12761 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
12762 +
12763 +#define read_pci_cfg_byte(a) \
12764 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
12765 +
12766 +#define read_pci_cfg_write(a) \
12767 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
12768 +
12769 +
12770 +/* return TRUE if requested capability exists in the PCI config space */
12771 +static bool
12772 +sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen)
12773 +{
12774 + uint8 cap_id;
12775 + uint8 cap_ptr;
12776 + uint32 bufsize;
12777 + uint8 byte_val;
12778 +
12779 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
12780 + return FALSE;
12781 +
12782 + /* check for Header type 0 */
12783 + byte_val = read_pci_cfg_byte(PCI_CFG_HDR);
12784 + if ((byte_val & 0x7f) != PCI_HEADER_NORMAL)
12785 + return FALSE;
12786 +
12787 + /* check if the capability pointer field exists */
12788 + byte_val = read_pci_cfg_byte(PCI_CFG_STAT);
12789 + if (!(byte_val & PCI_CAPPTR_PRESENT))
12790 + return FALSE;
12791 +
12792 + cap_ptr = read_pci_cfg_byte(PCI_CFG_CAPPTR);
12793 + /* check if the capability pointer is 0x00 */
12794 + if (cap_ptr == 0x00)
12795 + return FALSE;
12796 +
12797 +
12798 + /* loop thr'u the capability list and see if the pcie capabilty exists */
12799 +
12800 + cap_id = read_pci_cfg_byte(cap_ptr);
12801 +
12802 + while (cap_id != req_cap_id) {
12803 + cap_ptr = read_pci_cfg_byte((cap_ptr+1));
12804 + if (cap_ptr == 0x00) break;
12805 + cap_id = read_pci_cfg_byte(cap_ptr);
12806 + }
12807 + if (cap_id != req_cap_id) {
12808 + return FALSE;
12809 + }
12810 + /* found the caller requested capability */
12811 + if ((buf != NULL) && (buflen != NULL)) {
12812 + bufsize = *buflen;
12813 + if (!bufsize) goto end;
12814 + *buflen = 0;
12815 + /* copy the cpability data excluding cap ID and next ptr */
12816 + cap_ptr += 2;
12817 + if ((bufsize + cap_ptr) > SZPCR)
12818 + bufsize = SZPCR - cap_ptr;
12819 + *buflen = bufsize;
12820 + while (bufsize--) {
12821 + *buf = read_pci_cfg_byte(cap_ptr);
12822 + cap_ptr++;
12823 + buf++;
12824 + }
12825 + }
12826 +end:
12827 + return TRUE;
12828 +}
12829 +
12830 +/* return TRUE if PCIE capability exists the pci config space */
12831 +static inline bool
12832 +sb_ispcie(sb_info_t *si)
12833 +{
12834 + return (sb_find_pci_capability(si, PCI_CAP_PCIECAP_ID, NULL, NULL));
12835 +}
12836 +
12837 +/* scan the sb enumerated space to identify all cores */
12838 +static void
12839 +BCMINITFN(sb_scan)(sb_info_t *si)
12840 +{
12841 + uint origidx;
12842 + uint i;
12843 + bool pci;
12844 + bool pcie;
12845 + uint pciidx;
12846 + uint pcieidx;
12847 + uint pcirev;
12848 + uint pcierev;
12849 +
12850 +
12851 + /* numcores should already be set */
12852 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
12853 +
12854 + /* save current core index */
12855 + origidx = sb_coreidx(&si->sb);
12856 +
12857 + si->sb.buscorerev = NOREV;
12858 + si->sb.buscoreidx = BADIDX;
12859 +
12860 + si->gpioidx = BADIDX;
12861 +
12862 + pci = pcie = FALSE;
12863 + pcirev = pcierev = NOREV;
12864 + pciidx = pcieidx = BADIDX;
12865 +
12866 + for (i = 0; i < si->numcores; i++) {
12867 + sb_setcoreidx(&si->sb, i);
12868 + si->coreid[i] = sb_coreid(&si->sb);
12869 +
12870 + if (si->coreid[i] == SB_PCI) {
12871 + pciidx = i;
12872 + pcirev = sb_corerev(&si->sb);
12873 + pci = TRUE;
12874 + } else if (si->coreid[i] == SB_PCIE) {
12875 + pcieidx = i;
12876 + pcierev = sb_corerev(&si->sb);
12877 + pcie = TRUE;
12878 + } else if (si->coreid[i] == SB_PCMCIA) {
12879 + si->sb.buscorerev = sb_corerev(&si->sb);
12880 + si->sb.buscoretype = si->coreid[i];
12881 + si->sb.buscoreidx = i;
12882 + }
12883 + }
12884 + if (pci && pcie) {
12885 + if (sb_ispcie(si))
12886 + pci = FALSE;
12887 + else
12888 + pcie = FALSE;
12889 + }
12890 + if (pci) {
12891 + si->sb.buscoretype = SB_PCI;
12892 + si->sb.buscorerev = pcirev;
12893 + si->sb.buscoreidx = pciidx;
12894 + } else if (pcie) {
12895 + si->sb.buscoretype = SB_PCIE;
12896 + si->sb.buscorerev = pcierev;
12897 + si->sb.buscoreidx = pcieidx;
12898 + }
12899 +
12900 + /*
12901 + * Find the gpio "controlling core" type and index.
12902 + * Precedence:
12903 + * - if there's a chip common core - use that
12904 + * - else if there's a pci core (rev >= 2) - use that
12905 + * - else there had better be an extif core (4710 only)
12906 + */
12907 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
12908 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
12909 + si->gpioid = SB_CC;
12910 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
12911 + si->gpioidx = si->sb.buscoreidx;
12912 + si->gpioid = SB_PCI;
12913 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
12914 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
12915 + si->gpioid = SB_EXTIF;
12916 + } else
12917 + ASSERT(si->gpioidx != BADIDX);
12918 +
12919 + /* return to original core index */
12920 + sb_setcoreidx(&si->sb, origidx);
12921 +}
12922 +
12923 +/* may be called with core in reset */
12924 +void
12925 +sb_detach(sb_t *sbh)
12926 +{
12927 + sb_info_t *si;
12928 + uint idx;
12929 +
12930 + si = SB_INFO(sbh);
12931 +
12932 + if (si == NULL)
12933 + return;
12934 +
12935 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
12936 + for (idx = 0; idx < SB_MAXCORES; idx++)
12937 + if (si->regs[idx]) {
12938 + REG_UNMAP(si->regs[idx]);
12939 + si->regs[idx] = NULL;
12940 + }
12941 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
12942 + if (si != &ksi)
12943 +#endif /* !BCMBUSTYPE || (BCMBUSTYPE == SB_BUS) */
12944 + MFREE(si->osh, si, sizeof(sb_info_t));
12945 +
12946 +}
12947 +
12948 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
12949 +static uint
12950 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
12951 +{
12952 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
12953 + return (BCM4710_CHIP_ID);
12954 + if ((pcidev >= BCM4402_ENET_ID) && (pcidev <= BCM4402_V90_ID))
12955 + return (BCM4402_CHIP_ID);
12956 + if (pcidev == BCM4401_ENET_ID)
12957 + return (BCM4402_CHIP_ID);
12958 +
12959 + return (0);
12960 +}
12961 +
12962 +/* convert chip number to number of i/o cores */
12963 +static uint
12964 +BCMINITFN(sb_chip2numcores)(uint chip)
12965 +{
12966 + if (chip == BCM4710_CHIP_ID)
12967 + return (9);
12968 + if (chip == BCM4402_CHIP_ID)
12969 + return (3);
12970 + if (chip == BCM4306_CHIP_ID) /* < 4306c0 */
12971 + return (6);
12972 + if (chip == BCM4704_CHIP_ID)
12973 + return (9);
12974 + if (chip == BCM5365_CHIP_ID)
12975 + return (7);
12976 +
12977 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
12978 + ASSERT(0);
12979 + return (1);
12980 +}
12981 +
12982 +/* return index of coreid or BADIDX if not found */
12983 +static uint
12984 +sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit)
12985 +{
12986 + uint found;
12987 + uint i;
12988 +
12989 + found = 0;
12990 +
12991 + for (i = 0; i < si->numcores; i++)
12992 + if (si->coreid[i] == coreid) {
12993 + if (found == coreunit)
12994 + return (i);
12995 + found++;
12996 + }
12997 +
12998 + return (BADIDX);
12999 +}
13000 +
13001 +/*
13002 + * this function changes logical "focus" to the indiciated core,
13003 + * must be called with interrupt off.
13004 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
13005 + */
13006 +void*
13007 +sb_setcoreidx(sb_t *sbh, uint coreidx)
13008 +{
13009 + sb_info_t *si;
13010 + uint32 sbaddr;
13011 + uint8 tmp;
13012 +
13013 + si = SB_INFO(sbh);
13014 +
13015 + if (coreidx >= si->numcores)
13016 + return (NULL);
13017 +
13018 + /*
13019 + * If the user has provided an interrupt mask enabled function,
13020 + * then assert interrupts are disabled before switching the core.
13021 + */
13022 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
13023 +
13024 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
13025 +
13026 + switch (BUSTYPE(si->sb.bustype)) {
13027 + case SB_BUS:
13028 + /* map new one */
13029 + if (!si->regs[coreidx]) {
13030 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
13031 + ASSERT(GOODREGS(si->regs[coreidx]));
13032 + }
13033 + si->curmap = si->regs[coreidx];
13034 + break;
13035 +
13036 + case PCI_BUS:
13037 + /* point bar0 window */
13038 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
13039 + break;
13040 +
13041 + case PCMCIA_BUS:
13042 + tmp = (sbaddr >> 12) & 0x0f;
13043 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
13044 + tmp = (sbaddr >> 16) & 0xff;
13045 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
13046 + tmp = (sbaddr >> 24) & 0xff;
13047 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
13048 + break;
13049 +#ifdef BCMJTAG
13050 + case JTAG_BUS:
13051 + /* map new one */
13052 + if (!si->regs[coreidx]) {
13053 + si->regs[coreidx] = (void *)sbaddr;
13054 + ASSERT(GOODREGS(si->regs[coreidx]));
13055 + }
13056 + si->curmap = si->regs[coreidx];
13057 + break;
13058 +#endif /* BCMJTAG */
13059 + }
13060 +
13061 + si->curidx = coreidx;
13062 +
13063 + return (si->curmap);
13064 +}
13065 +
13066 +/*
13067 + * this function changes logical "focus" to the indiciated core,
13068 + * must be called with interrupt off.
13069 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
13070 + */
13071 +void*
13072 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
13073 +{
13074 + sb_info_t *si;
13075 + uint idx;
13076 +
13077 + si = SB_INFO(sbh);
13078 + idx = sb_findcoreidx(si, coreid, coreunit);
13079 + if (!GOODIDX(idx))
13080 + return (NULL);
13081 +
13082 + return (sb_setcoreidx(sbh, idx));
13083 +}
13084 +
13085 +/* return chip number */
13086 +uint
13087 +sb_chip(sb_t *sbh)
13088 +{
13089 + sb_info_t *si;
13090 +
13091 + si = SB_INFO(sbh);
13092 + return (si->sb.chip);
13093 +}
13094 +
13095 +/* return chip revision number */
13096 +uint
13097 +sb_chiprev(sb_t *sbh)
13098 +{
13099 + sb_info_t *si;
13100 +
13101 + si = SB_INFO(sbh);
13102 + return (si->sb.chiprev);
13103 +}
13104 +
13105 +/* return chip common revision number */
13106 +uint
13107 +sb_chipcrev(sb_t *sbh)
13108 +{
13109 + sb_info_t *si;
13110 +
13111 + si = SB_INFO(sbh);
13112 + return (si->sb.ccrev);
13113 +}
13114 +
13115 +/* return chip package option */
13116 +uint
13117 +sb_chippkg(sb_t *sbh)
13118 +{
13119 + sb_info_t *si;
13120 +
13121 + si = SB_INFO(sbh);
13122 + return (si->sb.chippkg);
13123 +}
13124 +
13125 +/* return PCI core rev. */
13126 +uint
13127 +sb_pcirev(sb_t *sbh)
13128 +{
13129 + sb_info_t *si;
13130 +
13131 + si = SB_INFO(sbh);
13132 + return (si->sb.buscorerev);
13133 +}
13134 +
13135 +bool
13136 +BCMINITFN(sb_war16165)(sb_t *sbh)
13137 +{
13138 + sb_info_t *si;
13139 +
13140 + si = SB_INFO(sbh);
13141 +
13142 + return (PCI(si) && (si->sb.buscorerev <= 10));
13143 +}
13144 +
13145 +static void
13146 +BCMINITFN(sb_war30841)(sb_info_t *si)
13147 +{
13148 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
13149 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
13150 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
13151 +}
13152 +
13153 +/* return PCMCIA core rev. */
13154 +uint
13155 +BCMINITFN(sb_pcmciarev)(sb_t *sbh)
13156 +{
13157 + sb_info_t *si;
13158 +
13159 + si = SB_INFO(sbh);
13160 + return (si->sb.buscorerev);
13161 +}
13162 +
13163 +/* return board vendor id */
13164 +uint
13165 +sb_boardvendor(sb_t *sbh)
13166 +{
13167 + sb_info_t *si;
13168 +
13169 + si = SB_INFO(sbh);
13170 + return (si->sb.boardvendor);
13171 +}
13172 +
13173 +/* return boardtype */
13174 +uint
13175 +sb_boardtype(sb_t *sbh)
13176 +{
13177 + sb_info_t *si;
13178 + char *var;
13179 +
13180 + si = SB_INFO(sbh);
13181 +
13182 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
13183 + /* boardtype format is a hex string */
13184 + si->sb.boardtype = getintvar(NULL, "boardtype");
13185 +
13186 + /* backward compatibility for older boardtype string format */
13187 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
13188 + if (!strcmp(var, "bcm94710dev"))
13189 + si->sb.boardtype = BCM94710D_BOARD;
13190 + else if (!strcmp(var, "bcm94710ap"))
13191 + si->sb.boardtype = BCM94710AP_BOARD;
13192 + else if (!strcmp(var, "bu4710"))
13193 + si->sb.boardtype = BU4710_BOARD;
13194 + else if (!strcmp(var, "bcm94702mn"))
13195 + si->sb.boardtype = BCM94702MN_BOARD;
13196 + else if (!strcmp(var, "bcm94710r1"))
13197 + si->sb.boardtype = BCM94710R1_BOARD;
13198 + else if (!strcmp(var, "bcm94710r4"))
13199 + si->sb.boardtype = BCM94710R4_BOARD;
13200 + else if (!strcmp(var, "bcm94702cpci"))
13201 + si->sb.boardtype = BCM94702CPCI_BOARD;
13202 + else if (!strcmp(var, "bcm95380_rr"))
13203 + si->sb.boardtype = BCM95380RR_BOARD;
13204 + }
13205 + }
13206 +
13207 + return (si->sb.boardtype);
13208 +}
13209 +
13210 +/* return bus type of sbh device */
13211 +uint
13212 +sb_bus(sb_t *sbh)
13213 +{
13214 + sb_info_t *si;
13215 +
13216 + si = SB_INFO(sbh);
13217 + return (si->sb.bustype);
13218 +}
13219 +
13220 +/* return bus core type */
13221 +uint
13222 +sb_buscoretype(sb_t *sbh)
13223 +{
13224 + sb_info_t *si;
13225 +
13226 + si = SB_INFO(sbh);
13227 +
13228 + return (si->sb.buscoretype);
13229 +}
13230 +
13231 +/* return bus core revision */
13232 +uint
13233 +sb_buscorerev(sb_t *sbh)
13234 +{
13235 + sb_info_t *si;
13236 + si = SB_INFO(sbh);
13237 +
13238 + return (si->sb.buscorerev);
13239 +}
13240 +
13241 +/* return list of found cores */
13242 +uint
13243 +sb_corelist(sb_t *sbh, uint coreid[])
13244 +{
13245 + sb_info_t *si;
13246 +
13247 + si = SB_INFO(sbh);
13248 +
13249 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof(uint)));
13250 + return (si->numcores);
13251 +}
13252 +
13253 +/* return current register mapping */
13254 +void *
13255 +sb_coreregs(sb_t *sbh)
13256 +{
13257 + sb_info_t *si;
13258 +
13259 + si = SB_INFO(sbh);
13260 + ASSERT(GOODREGS(si->curmap));
13261 +
13262 + return (si->curmap);
13263 +}
13264 +
13265 +
13266 +/* do buffered registers update */
13267 +void
13268 +sb_commit(sb_t *sbh)
13269 +{
13270 + sb_info_t *si;
13271 + uint origidx;
13272 + uint intr_val = 0;
13273 +
13274 + si = SB_INFO(sbh);
13275 +
13276 + origidx = si->curidx;
13277 + ASSERT(GOODIDX(origidx));
13278 +
13279 + INTR_OFF(si, intr_val);
13280 +
13281 + /* switch over to chipcommon core if there is one, else use pci */
13282 + if (si->sb.ccrev != NOREV) {
13283 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
13284 +
13285 + /* do the buffer registers update */
13286 + W_REG(si->osh, &ccregs->broadcastaddress, SB_COMMIT);
13287 + W_REG(si->osh, &ccregs->broadcastdata, 0x0);
13288 + } else if (PCI(si)) {
13289 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
13290 +
13291 + /* do the buffer registers update */
13292 + W_REG(si->osh, &pciregs->bcastaddr, SB_COMMIT);
13293 + W_REG(si->osh, &pciregs->bcastdata, 0x0);
13294 + } else
13295 + ASSERT(0);
13296 +
13297 + /* restore core index */
13298 + sb_setcoreidx(sbh, origidx);
13299 + INTR_RESTORE(si, intr_val);
13300 +}
13301 +
13302 +/* reset and re-enable a core
13303 + * inputs:
13304 + * bits - core specific bits that are set during and after reset sequence
13305 + * resetbits - core specific bits that are set only during reset sequence
13306 + */
13307 +void
13308 +sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits)
13309 +{
13310 + sb_info_t *si;
13311 + sbconfig_t *sb;
13312 + volatile uint32 dummy;
13313 +
13314 + si = SB_INFO(sbh);
13315 + ASSERT(GOODREGS(si->curmap));
13316 + sb = REGS2SB(si->curmap);
13317 +
13318 + /*
13319 + * Must do the disable sequence first to work for arbitrary current core state.
13320 + */
13321 + sb_core_disable(sbh, (bits | resetbits));
13322 +
13323 + /*
13324 + * Now do the initialization sequence.
13325 + */
13326 +
13327 + /* set reset while enabling the clock and forcing them on throughout the core */
13328 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits | resetbits));
13329 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13330 + OSL_DELAY(1);
13331 +
13332 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
13333 + W_SBREG(si, &sb->sbtmstatehigh, 0);
13334 + }
13335 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
13336 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
13337 + }
13338 +
13339 + /* clear reset and allow it to propagate throughout the core */
13340 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
13341 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13342 + OSL_DELAY(1);
13343 +
13344 + /* leave clock enabled */
13345 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
13346 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13347 + OSL_DELAY(1);
13348 +}
13349 +
13350 +void
13351 +sb_core_tofixup(sb_t *sbh)
13352 +{
13353 + sb_info_t *si;
13354 + sbconfig_t *sb;
13355 +
13356 + si = SB_INFO(sbh);
13357 +
13358 + if ((BUSTYPE(si->sb.bustype) != PCI_BUS) || PCIE(si) ||
13359 + (PCI(si) && (si->sb.buscorerev >= 5)))
13360 + return;
13361 +
13362 + ASSERT(GOODREGS(si->curmap));
13363 + sb = REGS2SB(si->curmap);
13364 +
13365 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
13366 + SET_SBREG(si, &sb->sbimconfiglow,
13367 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13368 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
13369 + } else {
13370 + if (sb_coreid(sbh) == SB_PCI) {
13371 + SET_SBREG(si, &sb->sbimconfiglow,
13372 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13373 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
13374 + } else {
13375 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
13376 + }
13377 + }
13378 +
13379 + sb_commit(sbh);
13380 +}
13381 +
13382 +/*
13383 + * Set the initiator timeout for the "master core".
13384 + * The master core is defined to be the core in control
13385 + * of the chip and so it issues accesses to non-memory
13386 + * locations (Because of dma *any* core can access memeory).
13387 + *
13388 + * The routine uses the bus to decide who is the master:
13389 + * SB_BUS => mips
13390 + * JTAG_BUS => chipc
13391 + * PCI_BUS => pci or pcie
13392 + * PCMCIA_BUS => pcmcia
13393 + * SDIO_BUS => pcmcia
13394 + *
13395 + * This routine exists so callers can disable initiator
13396 + * timeouts so accesses to very slow devices like otp
13397 + * won't cause an abort. The routine allows arbitrary
13398 + * settings of the service and request timeouts, though.
13399 + *
13400 + * Returns the timeout state before changing it or -1
13401 + * on error.
13402 + */
13403 +
13404 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
13405 +
13406 +uint32
13407 +sb_set_initiator_to(sb_t *sbh, uint32 to)
13408 +{
13409 + sb_info_t *si;
13410 + uint origidx, idx;
13411 + uint intr_val = 0;
13412 + uint32 tmp, ret = 0xffffffff;
13413 + sbconfig_t *sb;
13414 +
13415 + si = SB_INFO(sbh);
13416 +
13417 + if ((to & ~TO_MASK) != 0)
13418 + return ret;
13419 +
13420 + /* Figure out the master core */
13421 + idx = BADIDX;
13422 + switch (BUSTYPE(si->sb.bustype)) {
13423 + case PCI_BUS:
13424 + idx = si->sb.buscoreidx;
13425 + break;
13426 + case JTAG_BUS:
13427 + idx = SB_CC_IDX;
13428 + break;
13429 + case PCMCIA_BUS:
13430 + case SDIO_BUS:
13431 + idx = sb_findcoreidx(si, SB_PCMCIA, 0);
13432 + break;
13433 + case SB_BUS:
13434 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
13435 + idx = sb_findcoreidx(si, SB_MIPS, 0);
13436 + break;
13437 + default:
13438 + ASSERT(0);
13439 + }
13440 + if (idx == BADIDX)
13441 + return ret;
13442 +
13443 + INTR_OFF(si, intr_val);
13444 + origidx = sb_coreidx(sbh);
13445 +
13446 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
13447 +
13448 + tmp = R_SBREG(si, &sb->sbimconfiglow);
13449 + ret = tmp & TO_MASK;
13450 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
13451 +
13452 + sb_commit(sbh);
13453 + sb_setcoreidx(sbh, origidx);
13454 + INTR_RESTORE(si, intr_val);
13455 + return ret;
13456 +}
13457 +
13458 +void
13459 +sb_core_disable(sb_t *sbh, uint32 bits)
13460 +{
13461 + sb_info_t *si;
13462 + volatile uint32 dummy;
13463 + uint32 rej;
13464 + sbconfig_t *sb;
13465 +
13466 + si = SB_INFO(sbh);
13467 +
13468 + ASSERT(GOODREGS(si->curmap));
13469 + sb = REGS2SB(si->curmap);
13470 +
13471 + /* if core is already in reset, just return */
13472 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
13473 + return;
13474 +
13475 + /* reject value changed between sonics 2.2 and 2.3 */
13476 + if (si->sb.sonicsrev == SONICS_2_2)
13477 + rej = (1 << SBTML_REJ_SHIFT);
13478 + else
13479 + rej = (2 << SBTML_REJ_SHIFT);
13480 +
13481 + /* if clocks are not enabled, put into reset and return */
13482 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
13483 + goto disable;
13484 +
13485 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
13486 + OR_SBREG(si, &sb->sbtmstatelow, rej);
13487 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13488 + OSL_DELAY(1);
13489 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
13490 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY)
13491 + SB_ERROR(("%s: target state still busy\n", __FUNCTION__));
13492 +
13493 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
13494 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
13495 + dummy = R_SBREG(si, &sb->sbimstate);
13496 + OSL_DELAY(1);
13497 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
13498 + }
13499 +
13500 + /* set reset and reject while enabling the clocks */
13501 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
13502 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13503 + OSL_DELAY(10);
13504 +
13505 + /* don't forget to clear the initiator reject bit */
13506 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
13507 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
13508 +
13509 +disable:
13510 + /* leave reset and reject asserted */
13511 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
13512 + OSL_DELAY(1);
13513 +}
13514 +
13515 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
13516 +void
13517 +sb_watchdog(sb_t *sbh, uint ticks)
13518 +{
13519 + sb_info_t *si = SB_INFO(sbh);
13520 +
13521 + /* make sure we come up in fast clock mode */
13522 + sb_clkctl_clk(sbh, CLK_FAST);
13523 +
13524 + /* instant NMI */
13525 + switch (si->gpioid) {
13526 + case SB_CC:
13527 +#ifdef __mips__
13528 + if (sb_chip(sbh) == BCM4785_CHIP_ID && ticks <= 1)
13529 + MTC0(C0_BROADCOM, 4, (1 << 22));
13530 +#endif /* __mips__ */
13531 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
13532 +#ifdef __mips__
13533 + if (sb_chip(sbh) == BCM4785_CHIP_ID && ticks <= 1) {
13534 + __asm__ __volatile__ (
13535 + ".set\tmips3\n\t"
13536 + "sync\n\t"
13537 + "wait\n\t"
13538 + ".set\tmips0"
13539 + );
13540 + while (1);
13541 + }
13542 +#endif /* __mips__ */
13543 + break;
13544 + case SB_EXTIF:
13545 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
13546 + break;
13547 + }
13548 +}
13549 +
13550 +/* initialize the pcmcia core */
13551 +void
13552 +sb_pcmcia_init(sb_t *sbh)
13553 +{
13554 + sb_info_t *si;
13555 + uint8 cor = 0;
13556 +
13557 + si = SB_INFO(sbh);
13558 +
13559 + /* enable d11 mac interrupts */
13560 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
13561 + cor |= COR_IRQEN | COR_FUNEN;
13562 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
13563 +
13564 +}
13565 +
13566 +
13567 +/*
13568 + * Configure the pci core for pci client (NIC) action
13569 + * coremask is the bitvec of cores by index to be enabled.
13570 + */
13571 +void
13572 +BCMINITFN(sb_pci_setup)(sb_t *sbh, uint coremask)
13573 +{
13574 + sb_info_t *si;
13575 + sbconfig_t *sb;
13576 + sbpciregs_t *pciregs;
13577 + uint32 sbflag;
13578 + uint32 w;
13579 + uint idx;
13580 + int reg_val;
13581 +
13582 + si = SB_INFO(sbh);
13583 +
13584 + /* if not pci bus, we're done */
13585 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
13586 + return;
13587 +
13588 + ASSERT(PCI(si) || PCIE(si));
13589 + ASSERT(si->sb.buscoreidx != BADIDX);
13590 +
13591 + /* get current core index */
13592 + idx = si->curidx;
13593 +
13594 + /* we interrupt on this backplane flag number */
13595 + ASSERT(GOODREGS(si->curmap));
13596 + sb = REGS2SB(si->curmap);
13597 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
13598 +
13599 + /* switch over to pci core */
13600 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
13601 + sb = REGS2SB(pciregs);
13602 +
13603 + /*
13604 + * Enable sb->pci interrupts. Assume
13605 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
13606 + */
13607 + if (PCIE(si) || (PCI(si) && ((si->sb.buscorerev) >= 6))) {
13608 + /* pci config write to set this core bit in PCIIntMask */
13609 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
13610 + w |= (coremask << PCI_SBIM_SHIFT);
13611 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
13612 + } else {
13613 + /* set sbintvec bit for our flag number */
13614 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
13615 + }
13616 +
13617 + if (PCI(si)) {
13618 + OR_REG(si->osh, &pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
13619 + if (si->sb.buscorerev >= 11)
13620 + OR_REG(si->osh, &pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
13621 + if (si->sb.buscorerev < 5) {
13622 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13623 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
13624 + sb_commit(sbh);
13625 + }
13626 + }
13627 +
13628 +#ifdef PCIE_SUPPOER
13629 + /* PCIE workarounds */
13630 + if (PCIE(si)) {
13631 + if ((si->sb.buscorerev == 0) || (si->sb.buscorerev == 1)) {
13632 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS,
13633 + PCIE_TLP_WORKAROUNDSREG);
13634 + reg_val |= 0x8;
13635 + sb_pcie_writereg((void *)sbh, (void *)PCIE_PCIEREGS,
13636 + PCIE_TLP_WORKAROUNDSREG, reg_val);
13637 + }
13638 +
13639 + if (si->sb.buscorerev == 1) {
13640 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS,
13641 + PCIE_DLLP_LCREG);
13642 + reg_val |= (0x40);
13643 + sb_pcie_writereg(sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG, reg_val);
13644 + }
13645 +
13646 + if (si->sb.buscorerev == 0)
13647 + sb_war30841(si);
13648 + }
13649 +#endif
13650 +
13651 + /* switch back to previous core */
13652 + sb_setcoreidx(sbh, idx);
13653 +}
13654 +
13655 +uint32
13656 +sb_base(uint32 admatch)
13657 +{
13658 + uint32 base;
13659 + uint type;
13660 +
13661 + type = admatch & SBAM_TYPE_MASK;
13662 + ASSERT(type < 3);
13663 +
13664 + base = 0;
13665 +
13666 + if (type == 0) {
13667 + base = admatch & SBAM_BASE0_MASK;
13668 + } else if (type == 1) {
13669 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13670 + base = admatch & SBAM_BASE1_MASK;
13671 + } else if (type == 2) {
13672 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13673 + base = admatch & SBAM_BASE2_MASK;
13674 + }
13675 +
13676 + return (base);
13677 +}
13678 +
13679 +uint32
13680 +sb_size(uint32 admatch)
13681 +{
13682 + uint32 size;
13683 + uint type;
13684 +
13685 + type = admatch & SBAM_TYPE_MASK;
13686 + ASSERT(type < 3);
13687 +
13688 + size = 0;
13689 +
13690 + if (type == 0) {
13691 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
13692 + } else if (type == 1) {
13693 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13694 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
13695 + } else if (type == 2) {
13696 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13697 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
13698 + }
13699 +
13700 + return (size);
13701 +}
13702 +
13703 +/* return the core-type instantiation # of the current core */
13704 +uint
13705 +sb_coreunit(sb_t *sbh)
13706 +{
13707 + sb_info_t *si;
13708 + uint idx;
13709 + uint coreid;
13710 + uint coreunit;
13711 + uint i;
13712 +
13713 + si = SB_INFO(sbh);
13714 + coreunit = 0;
13715 +
13716 + idx = si->curidx;
13717 +
13718 + ASSERT(GOODREGS(si->curmap));
13719 + coreid = sb_coreid(sbh);
13720 +
13721 + /* count the cores of our type */
13722 + for (i = 0; i < idx; i++)
13723 + if (si->coreid[i] == coreid)
13724 + coreunit++;
13725 +
13726 + return (coreunit);
13727 +}
13728 +
13729 +static INLINE uint32
13730 +factor6(uint32 x)
13731 +{
13732 + switch (x) {
13733 + case CC_F6_2: return 2;
13734 + case CC_F6_3: return 3;
13735 + case CC_F6_4: return 4;
13736 + case CC_F6_5: return 5;
13737 + case CC_F6_6: return 6;
13738 + case CC_F6_7: return 7;
13739 + default: return 0;
13740 + }
13741 +}
13742 +
13743 +/* calculate the speed the SB would run at given a set of clockcontrol values */
13744 +uint32
13745 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
13746 +{
13747 + uint32 n1, n2, clock, m1, m2, m3, mc;
13748 +
13749 + n1 = n & CN_N1_MASK;
13750 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
13751 +
13752 + if (pll_type == PLL_TYPE6) {
13753 + if (m & CC_T6_MMASK)
13754 + return CC_T6_M1;
13755 + else
13756 + return CC_T6_M0;
13757 + } else if ((pll_type == PLL_TYPE1) ||
13758 + (pll_type == PLL_TYPE3) ||
13759 + (pll_type == PLL_TYPE4) ||
13760 + (pll_type == PLL_TYPE7)) {
13761 + n1 = factor6(n1);
13762 + n2 += CC_F5_BIAS;
13763 + } else if (pll_type == PLL_TYPE2) {
13764 + n1 += CC_T2_BIAS;
13765 + n2 += CC_T2_BIAS;
13766 + ASSERT((n1 >= 2) && (n1 <= 7));
13767 + ASSERT((n2 >= 5) && (n2 <= 23));
13768 + } else if (pll_type == PLL_TYPE5) {
13769 + return (100000000);
13770 + } else
13771 + ASSERT(0);
13772 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
13773 + if ((pll_type == PLL_TYPE3) ||
13774 + (pll_type == PLL_TYPE7)) {
13775 + clock = CC_CLOCK_BASE2 * n1 * n2;
13776 + } else
13777 + clock = CC_CLOCK_BASE1 * n1 * n2;
13778 +
13779 + if (clock == 0)
13780 + return 0;
13781 +
13782 + m1 = m & CC_M1_MASK;
13783 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
13784 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
13785 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
13786 +
13787 + if ((pll_type == PLL_TYPE1) ||
13788 + (pll_type == PLL_TYPE3) ||
13789 + (pll_type == PLL_TYPE4) ||
13790 + (pll_type == PLL_TYPE7)) {
13791 + m1 = factor6(m1);
13792 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
13793 + m2 += CC_F5_BIAS;
13794 + else
13795 + m2 = factor6(m2);
13796 + m3 = factor6(m3);
13797 +
13798 + switch (mc) {
13799 + case CC_MC_BYPASS: return (clock);
13800 + case CC_MC_M1: return (clock / m1);
13801 + case CC_MC_M1M2: return (clock / (m1 * m2));
13802 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
13803 + case CC_MC_M1M3: return (clock / (m1 * m3));
13804 + default: return (0);
13805 + }
13806 + } else {
13807 + ASSERT(pll_type == PLL_TYPE2);
13808 +
13809 + m1 += CC_T2_BIAS;
13810 + m2 += CC_T2M2_BIAS;
13811 + m3 += CC_T2_BIAS;
13812 + ASSERT((m1 >= 2) && (m1 <= 7));
13813 + ASSERT((m2 >= 3) && (m2 <= 10));
13814 + ASSERT((m3 >= 2) && (m3 <= 7));
13815 +
13816 + if ((mc & CC_T2MC_M1BYP) == 0)
13817 + clock /= m1;
13818 + if ((mc & CC_T2MC_M2BYP) == 0)
13819 + clock /= m2;
13820 + if ((mc & CC_T2MC_M3BYP) == 0)
13821 + clock /= m3;
13822 +
13823 + return (clock);
13824 + }
13825 +}
13826 +
13827 +/* returns the current speed the SB is running at */
13828 +uint32
13829 +sb_clock(sb_t *sbh)
13830 +{
13831 + sb_info_t *si;
13832 + extifregs_t *eir;
13833 + chipcregs_t *cc;
13834 + uint32 n, m;
13835 + uint idx;
13836 + uint32 pll_type, rate;
13837 + uint intr_val = 0;
13838 +
13839 + si = SB_INFO(sbh);
13840 + idx = si->curidx;
13841 + pll_type = PLL_TYPE1;
13842 +
13843 + INTR_OFF(si, intr_val);
13844 +
13845 + /* switch to extif or chipc core */
13846 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
13847 + n = R_REG(si->osh, &eir->clockcontrol_n);
13848 + m = R_REG(si->osh, &eir->clockcontrol_sb);
13849 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
13850 + pll_type = R_REG(si->osh, &cc->capabilities) & CAP_PLL_MASK;
13851 + if (pll_type == PLL_NONE) {
13852 + INTR_RESTORE(si, intr_val);
13853 + return 80000000;
13854 + }
13855 + n = R_REG(si->osh, &cc->clockcontrol_n);
13856 + if (pll_type == PLL_TYPE6)
13857 + m = R_REG(si->osh, &cc->clockcontrol_m3);
13858 + else if ((pll_type == PLL_TYPE3) && !(BCMINIT(sb_chip)(sbh) == 0x5365))
13859 + m = R_REG(si->osh, &cc->clockcontrol_m2);
13860 + else
13861 + m = R_REG(si->osh, &cc->clockcontrol_sb);
13862 + } else {
13863 + INTR_RESTORE(si, intr_val);
13864 + return 0;
13865 + }
13866 +
13867 + /* calculate rate */
13868 + if (BCMINIT(sb_chip)(sbh) == 0x5365)
13869 + rate = 100000000;
13870 + else {
13871 + rate = sb_clock_rate(pll_type, n, m);
13872 +
13873 + if (pll_type == PLL_TYPE3)
13874 + rate = rate / 2;
13875 + }
13876 +
13877 + /* switch back to previous core */
13878 + sb_setcoreidx(sbh, idx);
13879 +
13880 + INTR_RESTORE(si, intr_val);
13881 +
13882 + return rate;
13883 +}
13884 +
13885 +/* change logical "focus" to the gpio core for optimized access */
13886 +void*
13887 +sb_gpiosetcore(sb_t *sbh)
13888 +{
13889 + sb_info_t *si;
13890 +
13891 + si = SB_INFO(sbh);
13892 +
13893 + return (sb_setcoreidx(sbh, si->gpioidx));
13894 +}
13895 +
13896 +/* mask&set gpiocontrol bits */
13897 +uint32
13898 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
13899 +{
13900 + sb_info_t *si;
13901 + uint regoff;
13902 +
13903 + si = SB_INFO(sbh);
13904 + regoff = 0;
13905 +
13906 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
13907 +
13908 + /* gpios could be shared on router platforms */
13909 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
13910 + mask = priority ? (sb_gpioreservation & mask) :
13911 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
13912 + val &= mask;
13913 + }
13914 +
13915 + switch (si->gpioid) {
13916 + case SB_CC:
13917 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
13918 + break;
13919 +
13920 + case SB_PCI:
13921 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
13922 + break;
13923 +
13924 + case SB_EXTIF:
13925 + return (0);
13926 + }
13927 +
13928 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
13929 +}
13930 +
13931 +/* mask&set gpio output enable bits */
13932 +uint32
13933 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
13934 +{
13935 + sb_info_t *si;
13936 + uint regoff;
13937 +
13938 + si = SB_INFO(sbh);
13939 + regoff = 0;
13940 +
13941 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
13942 +
13943 + /* gpios could be shared on router platforms */
13944 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
13945 + mask = priority ? (sb_gpioreservation & mask) :
13946 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
13947 + val &= mask;
13948 + }
13949 +
13950 + switch (si->gpioid) {
13951 + case SB_CC:
13952 + regoff = OFFSETOF(chipcregs_t, gpioouten);
13953 + break;
13954 +
13955 + case SB_PCI:
13956 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
13957 + break;
13958 +
13959 + case SB_EXTIF:
13960 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
13961 + break;
13962 + }
13963 +
13964 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
13965 +}
13966 +
13967 +/* mask&set gpio output bits */
13968 +uint32
13969 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
13970 +{
13971 + sb_info_t *si;
13972 + uint regoff;
13973 +
13974 + si = SB_INFO(sbh);
13975 + regoff = 0;
13976 +
13977 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
13978 +
13979 + /* gpios could be shared on router platforms */
13980 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
13981 + mask = priority ? (sb_gpioreservation & mask) :
13982 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
13983 + val &= mask;
13984 + }
13985 +
13986 + switch (si->gpioid) {
13987 + case SB_CC:
13988 + regoff = OFFSETOF(chipcregs_t, gpioout);
13989 + break;
13990 +
13991 + case SB_PCI:
13992 + regoff = OFFSETOF(sbpciregs_t, gpioout);
13993 + break;
13994 +
13995 + case SB_EXTIF:
13996 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
13997 + break;
13998 + }
13999 +
14000 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14001 +}
14002 +
14003 +/* reserve one gpio */
14004 +uint32
14005 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
14006 +{
14007 + sb_info_t *si;
14008 +
14009 + si = SB_INFO(sbh);
14010 +
14011 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14012 +
14013 + /* only cores on SB_BUS share GPIO's and only applcation users need to
14014 + * reserve/release GPIO
14015 + */
14016 + if ((BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
14017 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
14018 + return -1;
14019 + }
14020 + /* make sure only one bit is set */
14021 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
14022 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
14023 + return -1;
14024 + }
14025 +
14026 + /* already reserved */
14027 + if (sb_gpioreservation & gpio_bitmask)
14028 + return -1;
14029 + /* set reservation */
14030 + sb_gpioreservation |= gpio_bitmask;
14031 +
14032 + return sb_gpioreservation;
14033 +}
14034 +
14035 +/* release one gpio */
14036 +/*
14037 + * releasing the gpio doesn't change the current value on the GPIO last write value
14038 + * persists till some one overwrites it
14039 +*/
14040 +
14041 +uint32
14042 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
14043 +{
14044 + sb_info_t *si;
14045 +
14046 + si = SB_INFO(sbh);
14047 +
14048 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14049 +
14050 + /* only cores on SB_BUS share GPIO's and only applcation users need to
14051 + * reserve/release GPIO
14052 + */
14053 + if ((BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
14054 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
14055 + return -1;
14056 + }
14057 + /* make sure only one bit is set */
14058 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
14059 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
14060 + return -1;
14061 + }
14062 +
14063 + /* already released */
14064 + if (!(sb_gpioreservation & gpio_bitmask))
14065 + return -1;
14066 +
14067 + /* clear reservation */
14068 + sb_gpioreservation &= ~gpio_bitmask;
14069 +
14070 + return sb_gpioreservation;
14071 +}
14072 +
14073 +/* return the current gpioin register value */
14074 +uint32
14075 +sb_gpioin(sb_t *sbh)
14076 +{
14077 + sb_info_t *si;
14078 + uint regoff;
14079 +
14080 + si = SB_INFO(sbh);
14081 + regoff = 0;
14082 +
14083 + switch (si->gpioid) {
14084 + case SB_CC:
14085 + regoff = OFFSETOF(chipcregs_t, gpioin);
14086 + break;
14087 +
14088 + case SB_PCI:
14089 + regoff = OFFSETOF(sbpciregs_t, gpioin);
14090 + break;
14091 +
14092 + case SB_EXTIF:
14093 + regoff = OFFSETOF(extifregs_t, gpioin);
14094 + break;
14095 + }
14096 +
14097 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
14098 +}
14099 +
14100 +/* mask&set gpio interrupt polarity bits */
14101 +uint32
14102 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14103 +{
14104 + sb_info_t *si;
14105 + uint regoff;
14106 +
14107 + si = SB_INFO(sbh);
14108 + regoff = 0;
14109 +
14110 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14111 +
14112 + /* gpios could be shared on router platforms */
14113 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14114 + mask = priority ? (sb_gpioreservation & mask) :
14115 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14116 + val &= mask;
14117 + }
14118 +
14119 + switch (si->gpioid) {
14120 + case SB_CC:
14121 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
14122 + break;
14123 +
14124 + case SB_PCI:
14125 + /* pci gpio implementation does not support interrupt polarity */
14126 + ASSERT(0);
14127 + break;
14128 +
14129 + case SB_EXTIF:
14130 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
14131 + break;
14132 + }
14133 +
14134 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14135 +}
14136 +
14137 +/* mask&set gpio interrupt mask bits */
14138 +uint32
14139 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14140 +{
14141 + sb_info_t *si;
14142 + uint regoff;
14143 +
14144 + si = SB_INFO(sbh);
14145 + regoff = 0;
14146 +
14147 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14148 +
14149 + /* gpios could be shared on router platforms */
14150 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14151 + mask = priority ? (sb_gpioreservation & mask) :
14152 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14153 + val &= mask;
14154 + }
14155 +
14156 + switch (si->gpioid) {
14157 + case SB_CC:
14158 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
14159 + break;
14160 +
14161 + case SB_PCI:
14162 + /* pci gpio implementation does not support interrupt mask */
14163 + ASSERT(0);
14164 + break;
14165 +
14166 + case SB_EXTIF:
14167 + regoff = OFFSETOF(extifregs_t, gpiointmask);
14168 + break;
14169 + }
14170 +
14171 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14172 +}
14173 +
14174 +/* assign the gpio to an led */
14175 +uint32
14176 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
14177 +{
14178 + sb_info_t *si;
14179 +
14180 + si = SB_INFO(sbh);
14181 + if (si->sb.ccrev < 16)
14182 + return -1;
14183 +
14184 + /* gpio led powersave reg */
14185 + return (sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
14186 +}
14187 +
14188 +/* mask & set gpio timer val */
14189 +uint32
14190 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
14191 +{
14192 + sb_info_t *si;
14193 + si = SB_INFO(sbh);
14194 +
14195 + if (si->sb.ccrev < 16)
14196 + return -1;
14197 +
14198 + return (sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
14199 +}
14200 +
14201 +
14202 +/* return the slow clock source - LPO, XTAL, or PCI */
14203 +static uint
14204 +sb_slowclk_src(sb_info_t *si)
14205 +{
14206 + chipcregs_t *cc;
14207 +
14208 +
14209 + ASSERT(sb_coreid(&si->sb) == SB_CC);
14210 +
14211 + if (si->sb.ccrev < 6) {
14212 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS) &&
14213 + (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32)) &
14214 + PCI_CFG_GPIO_SCS))
14215 + return (SCC_SS_PCI);
14216 + else
14217 + return (SCC_SS_XTAL);
14218 + } else if (si->sb.ccrev < 10) {
14219 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
14220 + return (R_REG(si->osh, &cc->slow_clk_ctl) & SCC_SS_MASK);
14221 + } else /* Insta-clock */
14222 + return (SCC_SS_XTAL);
14223 +}
14224 +
14225 +/* return the ILP (slowclock) min or max frequency */
14226 +static uint
14227 +sb_slowclk_freq(sb_info_t *si, bool max)
14228 +{
14229 + chipcregs_t *cc;
14230 + uint32 slowclk;
14231 + uint div;
14232 +
14233 +
14234 + ASSERT(sb_coreid(&si->sb) == SB_CC);
14235 +
14236 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
14237 +
14238 + /* shouldn't be here unless we've established the chip has dynamic clk control */
14239 + ASSERT(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL);
14240 +
14241 + slowclk = sb_slowclk_src(si);
14242 + if (si->sb.ccrev < 6) {
14243 + if (slowclk == SCC_SS_PCI)
14244 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
14245 + else
14246 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
14247 + } else if (si->sb.ccrev < 10) {
14248 + div = 4 * (((R_REG(si->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
14249 + if (slowclk == SCC_SS_LPO)
14250 + return (max? LPOMAXFREQ : LPOMINFREQ);
14251 + else if (slowclk == SCC_SS_XTAL)
14252 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
14253 + else if (slowclk == SCC_SS_PCI)
14254 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
14255 + else
14256 + ASSERT(0);
14257 + } else {
14258 + /* Chipc rev 10 is InstaClock */
14259 + div = R_REG(si->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT;
14260 + div = 4 * (div + 1);
14261 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
14262 + }
14263 + return (0);
14264 +}
14265 +
14266 +static void
14267 +BCMINITFN(sb_clkctl_setdelay)(sb_info_t *si, void *chipcregs)
14268 +{
14269 + chipcregs_t * cc;
14270 + uint slowmaxfreq, pll_delay, slowclk;
14271 + uint pll_on_delay, fref_sel_delay;
14272 +
14273 + pll_delay = PLL_DELAY;
14274 +
14275 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
14276 + * since the xtal will also be powered down by dynamic clk control logic.
14277 + */
14278 +
14279 + slowclk = sb_slowclk_src(si);
14280 + if (slowclk != SCC_SS_XTAL)
14281 + pll_delay += XTAL_ON_DELAY;
14282 +
14283 + /* Starting with 4318 it is ILP that is used for the delays */
14284 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
14285 +
14286 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
14287 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
14288 +
14289 + cc = (chipcregs_t *)chipcregs;
14290 + W_REG(si->osh, &cc->pll_on_delay, pll_on_delay);
14291 + W_REG(si->osh, &cc->fref_sel_delay, fref_sel_delay);
14292 +}
14293 +
14294 +/* initialize power control delay registers */
14295 +void
14296 +BCMINITFN(sb_clkctl_init)(sb_t *sbh)
14297 +{
14298 + sb_info_t *si;
14299 + uint origidx;
14300 + chipcregs_t *cc;
14301 +
14302 + si = SB_INFO(sbh);
14303 +
14304 + origidx = si->curidx;
14305 +
14306 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
14307 + return;
14308 +
14309 + if ((si->sb.chip == BCM4321_CHIP_ID) && (si->sb.chiprev < 2))
14310 + W_REG(si->osh, &cc->chipcontrol,
14311 + (si->sb.chiprev == 0) ? CHIPCTRL_4321A0_DEFAULT : CHIPCTRL_4321A1_DEFAULT);
14312 +
14313 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14314 + goto done;
14315 +
14316 + /* set all Instaclk chip ILP to 1 MHz */
14317 + else if (si->sb.ccrev >= 10)
14318 + SET_REG(si->osh, &cc->system_clk_ctl, SYCC_CD_MASK,
14319 + (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
14320 +
14321 + sb_clkctl_setdelay(si, (void *)cc);
14322 +
14323 +done:
14324 + sb_setcoreidx(sbh, origidx);
14325 +}
14326 +
14327 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
14328 +uint16
14329 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
14330 +{
14331 + sb_info_t *si;
14332 + uint origidx;
14333 + chipcregs_t *cc;
14334 + uint slowminfreq;
14335 + uint16 fpdelay;
14336 + uint intr_val = 0;
14337 +
14338 + si = SB_INFO(sbh);
14339 + fpdelay = 0;
14340 + origidx = si->curidx;
14341 +
14342 + INTR_OFF(si, intr_val);
14343 +
14344 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
14345 + goto done;
14346 +
14347 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14348 + goto done;
14349 +
14350 + slowminfreq = sb_slowclk_freq(si, FALSE);
14351 + fpdelay = (((R_REG(si->osh, &cc->pll_on_delay) + 2) * 1000000) +
14352 + (slowminfreq - 1)) / slowminfreq;
14353 +
14354 +done:
14355 + sb_setcoreidx(sbh, origidx);
14356 + INTR_RESTORE(si, intr_val);
14357 + return (fpdelay);
14358 +}
14359 +
14360 +/* turn primary xtal and/or pll off/on */
14361 +int
14362 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
14363 +{
14364 + sb_info_t *si;
14365 + uint32 in, out, outen;
14366 +
14367 + si = SB_INFO(sbh);
14368 +
14369 + switch (BUSTYPE(si->sb.bustype)) {
14370 +
14371 +
14372 + case PCMCIA_BUS:
14373 + return (0);
14374 +
14375 +
14376 + case PCI_BUS:
14377 +
14378 + /* pcie core doesn't have any mapping to control the xtal pu */
14379 + if (PCIE(si))
14380 + return -1;
14381 +
14382 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof(uint32));
14383 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32));
14384 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof(uint32));
14385 +
14386 + /*
14387 + * Avoid glitching the clock if GPRS is already using it.
14388 + * We can't actually read the state of the PLLPD so we infer it
14389 + * by the value of XTAL_PU which *is* readable via gpioin.
14390 + */
14391 + if (on && (in & PCI_CFG_GPIO_XTAL))
14392 + return (0);
14393 +
14394 + if (what & XTAL)
14395 + outen |= PCI_CFG_GPIO_XTAL;
14396 + if (what & PLL)
14397 + outen |= PCI_CFG_GPIO_PLL;
14398 +
14399 + if (on) {
14400 + /* turn primary xtal on */
14401 + if (what & XTAL) {
14402 + out |= PCI_CFG_GPIO_XTAL;
14403 + if (what & PLL)
14404 + out |= PCI_CFG_GPIO_PLL;
14405 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT,
14406 + sizeof(uint32), out);
14407 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN,
14408 + sizeof(uint32), outen);
14409 + OSL_DELAY(XTAL_ON_DELAY);
14410 + }
14411 +
14412 + /* turn pll on */
14413 + if (what & PLL) {
14414 + out &= ~PCI_CFG_GPIO_PLL;
14415 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT,
14416 + sizeof(uint32), out);
14417 + OSL_DELAY(2000);
14418 + }
14419 + } else {
14420 + if (what & XTAL)
14421 + out &= ~PCI_CFG_GPIO_XTAL;
14422 + if (what & PLL)
14423 + out |= PCI_CFG_GPIO_PLL;
14424 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32), out);
14425 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof(uint32),
14426 + outen);
14427 + }
14428 +
14429 + default:
14430 + return (-1);
14431 + }
14432 +
14433 + return (0);
14434 +}
14435 +
14436 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
14437 +/* returns true if we are forcing fast clock */
14438 +bool
14439 +sb_clkctl_clk(sb_t *sbh, uint mode)
14440 +{
14441 + sb_info_t *si;
14442 + uint origidx;
14443 + chipcregs_t *cc;
14444 + uint32 scc;
14445 + uint intr_val = 0;
14446 +
14447 + si = SB_INFO(sbh);
14448 +
14449 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
14450 + if (si->sb.ccrev < 6)
14451 + return (FALSE);
14452 +
14453 +
14454 + /* Chips with ccrev 10 are EOL and they don't have SYCC_HR which we use below */
14455 + ASSERT(si->sb.ccrev != 10);
14456 +
14457 + INTR_OFF(si, intr_val);
14458 +
14459 + origidx = si->curidx;
14460 +
14461 + if (sb_setcore(sbh, SB_MIPS33, 0) && (sb_corerev(&si->sb) <= 7) &&
14462 + (BUSTYPE(si->sb.bustype) == SB_BUS) && (si->sb.ccrev >= 10))
14463 + goto done;
14464 +
14465 + /* PR32414WAR "Force HT clock on" all the time, no dynamic clk ctl */
14466 + if ((si->sb.chip == BCM4311_CHIP_ID) && (si->sb.chiprev <= 1))
14467 + goto done;
14468 +
14469 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
14470 + ASSERT(cc != NULL);
14471 +
14472 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14473 + goto done;
14474 +
14475 + switch (mode) {
14476 + case CLK_FAST: /* force fast (pll) clock */
14477 + if (si->sb.ccrev < 10) {
14478 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
14479 + sb_clkctl_xtal(&si->sb, XTAL, ON);
14480 +
14481 + SET_REG(si->osh, &cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
14482 + } else
14483 + OR_REG(si->osh, &cc->system_clk_ctl, SYCC_HR);
14484 + /* wait for the PLL */
14485 + OSL_DELAY(PLL_DELAY);
14486 + break;
14487 +
14488 + case CLK_DYNAMIC: /* enable dynamic clock control */
14489 +
14490 + if (si->sb.ccrev < 10) {
14491 + scc = R_REG(si->osh, &cc->slow_clk_ctl);
14492 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
14493 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
14494 + scc |= SCC_XC;
14495 + W_REG(si->osh, &cc->slow_clk_ctl, scc);
14496 +
14497 + /* for dynamic control, we have to release our xtal_pu "force on" */
14498 + if (scc & SCC_XC)
14499 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
14500 + } else {
14501 + /* Instaclock */
14502 + AND_REG(si->osh, &cc->system_clk_ctl, ~SYCC_HR);
14503 + }
14504 + break;
14505 +
14506 + default:
14507 + ASSERT(0);
14508 + }
14509 +
14510 +done:
14511 + sb_setcoreidx(sbh, origidx);
14512 + INTR_RESTORE(si, intr_val);
14513 + return (mode == CLK_FAST);
14514 +}
14515 +
14516 +/* register driver interrupt disabling and restoring callback functions */
14517 +void
14518 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
14519 + void *intrsenabled_fn, void *intr_arg)
14520 +{
14521 + sb_info_t *si;
14522 +
14523 + si = SB_INFO(sbh);
14524 + si->intr_arg = intr_arg;
14525 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
14526 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
14527 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
14528 + /* save current core id. when this function called, the current core
14529 + * must be the core which provides driver functions(il, et, wl, etc.)
14530 + */
14531 + si->dev_coreid = si->coreid[si->curidx];
14532 +}
14533 +
14534 +
14535 +int
14536 +sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
14537 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
14538 + uint8 *pciheader)
14539 +{
14540 + uint16 vendor = 0xffff, device = 0xffff;
14541 + uint core, unit;
14542 + uint chip, chippkg;
14543 + uint nfunc;
14544 + char varname[SB_DEVPATH_BUFSZ + 8];
14545 + uint8 class, subclass, progif;
14546 + char devpath[SB_DEVPATH_BUFSZ];
14547 + uint8 header;
14548 +
14549 + core = sb_coreid(sbh);
14550 + unit = sb_coreunit(sbh);
14551 +
14552 + chip = sb_chip(sbh);
14553 + chippkg = sb_chippkg(sbh);
14554 +
14555 + progif = 0;
14556 + header = PCI_HEADER_NORMAL;
14557 +
14558 + /* Verify whether the function exists for the core */
14559 + nfunc = (core == SB_USB20H) ? 2 : 1;
14560 + if (func >= nfunc)
14561 + return BCME_ERROR;
14562 +
14563 + /* Known vendor translations */
14564 + switch (sb_corevendor(sbh)) {
14565 + case SB_VEND_BCM:
14566 + vendor = VENDOR_BROADCOM;
14567 + break;
14568 + default:
14569 + return BCME_ERROR;
14570 + }
14571 +
14572 + /* Determine class based on known core codes */
14573 + switch (core) {
14574 + case SB_ILINE20:
14575 + class = PCI_CLASS_NET;
14576 + subclass = PCI_NET_ETHER;
14577 + device = BCM47XX_ILINE_ID;
14578 + break;
14579 + case SB_ENET:
14580 + class = PCI_CLASS_NET;
14581 + subclass = PCI_NET_ETHER;
14582 + device = BCM47XX_ENET_ID;
14583 + break;
14584 + case SB_GIGETH:
14585 + class = PCI_CLASS_NET;
14586 + subclass = PCI_NET_ETHER;
14587 + device = BCM47XX_GIGETH_ID;
14588 + break;
14589 + case SB_SDRAM:
14590 + case SB_MEMC:
14591 + class = PCI_CLASS_MEMORY;
14592 + subclass = PCI_MEMORY_RAM;
14593 + device = (uint16)core;
14594 + break;
14595 + case SB_PCI:
14596 + case SB_PCIE:
14597 + class = PCI_CLASS_BRIDGE;
14598 + subclass = PCI_BRIDGE_PCI;
14599 + device = (uint16)core;
14600 + header = PCI_HEADER_BRIDGE;
14601 + break;
14602 + case SB_MIPS:
14603 + case SB_MIPS33:
14604 + class = PCI_CLASS_CPU;
14605 + subclass = PCI_CPU_MIPS;
14606 + device = (uint16)core;
14607 + break;
14608 + case SB_CODEC:
14609 + class = PCI_CLASS_COMM;
14610 + subclass = PCI_COMM_MODEM;
14611 + device = BCM47XX_V90_ID;
14612 + break;
14613 + case SB_USB:
14614 + class = PCI_CLASS_SERIAL;
14615 + subclass = PCI_SERIAL_USB;
14616 + progif = 0x10; /* OHCI */
14617 + device = BCM47XX_USB_ID;
14618 + break;
14619 + case SB_USB11H:
14620 + class = PCI_CLASS_SERIAL;
14621 + subclass = PCI_SERIAL_USB;
14622 + progif = 0x10; /* OHCI */
14623 + device = BCM47XX_USBH_ID;
14624 + break;
14625 + case SB_USB20H:
14626 + class = PCI_CLASS_SERIAL;
14627 + subclass = PCI_SERIAL_USB;
14628 + progif = func == 0 ? 0x10 : 0x20; /* OHCI/EHCI */
14629 + device = BCM47XX_USB20H_ID;
14630 + header = 0x80; /* multifunction */
14631 + break;
14632 + case SB_USB11D:
14633 + class = PCI_CLASS_SERIAL;
14634 + subclass = PCI_SERIAL_USB;
14635 + device = BCM47XX_USBD_ID;
14636 + break;
14637 + case SB_USB20D:
14638 + class = PCI_CLASS_SERIAL;
14639 + subclass = PCI_SERIAL_USB;
14640 + device = BCM47XX_USB20D_ID;
14641 + break;
14642 + case SB_IPSEC:
14643 + class = PCI_CLASS_CRYPT;
14644 + subclass = PCI_CRYPT_NETWORK;
14645 + device = BCM47XX_IPSEC_ID;
14646 + break;
14647 + case SB_ROBO:
14648 + class = PCI_CLASS_NET;
14649 + subclass = PCI_NET_OTHER;
14650 + device = BCM47XX_ROBO_ID;
14651 + break;
14652 + case SB_EXTIF:
14653 + case SB_CC:
14654 + class = PCI_CLASS_MEMORY;
14655 + subclass = PCI_MEMORY_FLASH;
14656 + device = (uint16)core;
14657 + break;
14658 + case SB_D11:
14659 + class = PCI_CLASS_NET;
14660 + subclass = PCI_NET_OTHER;
14661 + /* Let nvram variable override core ID */
14662 + sb_devpath(sbh, devpath, sizeof(devpath));
14663 + sprintf(varname, "%sdevid", devpath);
14664 + if ((device = (uint16)getintvar(NULL, varname)))
14665 + break;
14666 + /*
14667 + * no longer support wl%did, but keep the code
14668 + * here for backward compatibility.
14669 + */
14670 + sprintf(varname, "wl%did", unit);
14671 + if ((device = (uint16)getintvar(NULL, varname)))
14672 + break;
14673 + /* Chip specific conversion */
14674 + if (chip == BCM4712_CHIP_ID) {
14675 + if (chippkg == BCM4712SMALL_PKG_ID)
14676 + device = BCM4306_D11G_ID;
14677 + else
14678 + device = BCM4306_D11DUAL_ID;
14679 + break;
14680 + }
14681 + /* ignore it */
14682 + device = 0xffff;
14683 + break;
14684 + case SB_SATAXOR:
14685 + class = PCI_CLASS_XOR;
14686 + subclass = PCI_XOR_QDMA;
14687 + device = BCM47XX_SATAXOR_ID;
14688 + break;
14689 + case SB_ATA100:
14690 + class = PCI_CLASS_DASDI;
14691 + subclass = PCI_DASDI_IDE;
14692 + device = BCM47XX_ATA100_ID;
14693 + break;
14694 +
14695 + default:
14696 + class = subclass = progif = 0xff;
14697 + device = (uint16)core;
14698 + break;
14699 + }
14700 +
14701 + *pcivendor = vendor;
14702 + *pcidevice = device;
14703 + *pciclass = class;
14704 + *pcisubclass = subclass;
14705 + *pciprogif = progif;
14706 + *pciheader = header;
14707 +
14708 + return 0;
14709 +}
14710 +
14711 +
14712 +
14713 +/* use the mdio interface to write to mdio slaves */
14714 +static int
14715 +sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint regaddr, uint val)
14716 +{
14717 + uint mdiodata;
14718 + uint i = 0;
14719 + sbpcieregs_t *pcieregs;
14720 +
14721 + pcieregs = (sbpcieregs_t*) sb_setcoreidx(&si->sb, si->sb.buscoreidx);
14722 + ASSERT(pcieregs);
14723 +
14724 + /* enable mdio access to SERDES */
14725 + W_REG(si->osh, (&pcieregs->mdiocontrol), MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
14726 +
14727 + mdiodata = MDIODATA_START | MDIODATA_WRITE |
14728 + (physmedia << MDIODATA_DEVADDR_SHF) |
14729 + (regaddr << MDIODATA_REGADDR_SHF) | MDIODATA_TA | val;
14730 +
14731 + W_REG(si->osh, (&pcieregs->mdiodata), mdiodata);
14732 +
14733 + PR28829_DELAY();
14734 +
14735 + /* retry till the transaction is complete */
14736 + while (i < 10) {
14737 + if (R_REG(si->osh, &(pcieregs->mdiocontrol)) & MDIOCTL_ACCESS_DONE) {
14738 + /* Disable mdio access to SERDES */
14739 + W_REG(si->osh, (&pcieregs->mdiocontrol), 0);
14740 + return 0;
14741 + }
14742 + OSL_DELAY(1000);
14743 + i++;
14744 + }
14745 +
14746 + SB_ERROR(("sb_pcie_mdiowrite: timed out\n"));
14747 + /* Disable mdio access to SERDES */
14748 + W_REG(si->osh, (&pcieregs->mdiocontrol), 0);
14749 + ASSERT(0);
14750 + return 1;
14751 +
14752 +}
14753 +
14754 +/* indirect way to read pcie config regs */
14755 +uint
14756 +sb_pcie_readreg(void *sb, void* arg1, uint offset)
14757 +{
14758 + sb_info_t *si;
14759 + sb_t *sbh;
14760 + uint retval = 0xFFFFFFFF;
14761 + sbpcieregs_t *pcieregs;
14762 + uint addrtype;
14763 +
14764 + sbh = (sb_t *)sb;
14765 + si = SB_INFO(sbh);
14766 + ASSERT(PCIE(si));
14767 +
14768 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
14769 + ASSERT(pcieregs);
14770 +
14771 + addrtype = (uint)((uintptr)arg1);
14772 + switch (addrtype) {
14773 + case PCIE_CONFIGREGS:
14774 + W_REG(si->osh, (&pcieregs->configaddr), offset);
14775 + retval = R_REG(si->osh, &(pcieregs->configdata));
14776 + break;
14777 + case PCIE_PCIEREGS:
14778 + W_REG(si->osh, &(pcieregs->pcieaddr), offset);
14779 + retval = R_REG(si->osh, &(pcieregs->pciedata));
14780 + break;
14781 + default:
14782 + ASSERT(0);
14783 + break;
14784 + }
14785 + return retval;
14786 +}
14787 +
14788 +/* indirect way to write pcie config/mdio/pciecore regs */
14789 +uint
14790 +sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val)
14791 +{
14792 + sb_info_t *si;
14793 + sbpcieregs_t *pcieregs;
14794 + uint addrtype;
14795 +
14796 + si = SB_INFO(sbh);
14797 + ASSERT(PCIE(si));
14798 +
14799 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
14800 + ASSERT(pcieregs);
14801 +
14802 + addrtype = (uint)((uintptr)arg1);
14803 +
14804 + switch (addrtype) {
14805 + case PCIE_CONFIGREGS:
14806 + W_REG(si->osh, (&pcieregs->configaddr), offset);
14807 + W_REG(si->osh, (&pcieregs->configdata), val);
14808 + break;
14809 + case PCIE_PCIEREGS:
14810 + W_REG(si->osh, (&pcieregs->pcieaddr), offset);
14811 + W_REG(si->osh, (&pcieregs->pciedata), val);
14812 + break;
14813 + default:
14814 + ASSERT(0);
14815 + break;
14816 + }
14817 + return 0;
14818 +}
14819 +
14820 +/* Build device path. Support SB, PCI, and JTAG for now. */
14821 +int
14822 +sb_devpath(sb_t *sbh, char *path, int size)
14823 +{
14824 + ASSERT(path);
14825 + ASSERT(size >= SB_DEVPATH_BUFSZ);
14826 +
14827 + switch (BUSTYPE((SB_INFO(sbh))->sb.bustype)) {
14828 + case SB_BUS:
14829 + case JTAG_BUS:
14830 + sprintf(path, "sb/%u/", sb_coreidx(sbh));
14831 + break;
14832 + case PCI_BUS:
14833 + ASSERT((SB_INFO(sbh))->osh);
14834 + sprintf(path, "pci/%u/%u/", OSL_PCI_BUS((SB_INFO(sbh))->osh),
14835 + OSL_PCI_SLOT((SB_INFO(sbh))->osh));
14836 + break;
14837 + case PCMCIA_BUS:
14838 + SB_ERROR(("sb_devpath: OSL_PCMCIA_BUS() not implemented, bus 1 assumed\n"));
14839 + SB_ERROR(("sb_devpath: OSL_PCMCIA_SLOT() not implemented, slot 1 assumed\n"));
14840 + sprintf(path, "pc/%u/%u/", 1, 1);
14841 + break;
14842 + case SDIO_BUS:
14843 + SB_ERROR(("sb_devpath: device 0 assumed\n"));
14844 + sprintf(path, "sd/%u/", sb_coreidx(sbh));
14845 + break;
14846 + default:
14847 + ASSERT(0);
14848 + break;
14849 + }
14850 +
14851 + return 0;
14852 +}
14853 +
14854 +/*
14855 + * Fixup SROMless PCI device's configuration.
14856 + * The current core may be changed upon return.
14857 + */
14858 +static int
14859 +sb_pci_fixcfg(sb_info_t *si)
14860 +{
14861 + uint origidx, pciidx;
14862 + sbpciregs_t *pciregs;
14863 + sbpcieregs_t *pcieregs;
14864 + uint16 val16, *reg16;
14865 + char name[SB_DEVPATH_BUFSZ+16], *value;
14866 + char devpath[SB_DEVPATH_BUFSZ];
14867 +
14868 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
14869 +
14870 + /* Fixup PI in SROM shadow area to enable the correct PCI core access */
14871 + /* save the current index */
14872 + origidx = sb_coreidx(&si->sb);
14873 +
14874 + /* check 'pi' is correct and fix it if not */
14875 + if (si->sb.buscoretype == SB_PCIE) {
14876 + pcieregs = (sbpcieregs_t *)sb_setcore(&si->sb, SB_PCIE, 0);
14877 + ASSERT(pcieregs);
14878 + reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
14879 + } else if (si->sb.buscoretype == SB_PCI) {
14880 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
14881 + ASSERT(pciregs);
14882 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
14883 + } else {
14884 + ASSERT(0);
14885 + return -1;
14886 + }
14887 + pciidx = sb_coreidx(&si->sb);
14888 + val16 = R_REG(si->osh, reg16);
14889 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
14890 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
14891 + W_REG(si->osh, reg16, val16);
14892 + }
14893 +
14894 + /* restore the original index */
14895 + sb_setcoreidx(&si->sb, origidx);
14896 +
14897 + /*
14898 + * Fixup bar0window in PCI config space to make the core indicated
14899 + * by the nvram variable the current core.
14900 + * !Do it last, it may change the current core!
14901 + */
14902 + if (sb_devpath(&si->sb, devpath, sizeof(devpath)))
14903 + return -1;
14904 + sprintf(name, "%sb0w", devpath);
14905 + if ((value = getvar(NULL, name))) {
14906 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32),
14907 + bcm_strtoul(value, NULL, 16));
14908 + /* update curidx since the current core is changed */
14909 + si->curidx = _sb_coreidx(si);
14910 + if (si->curidx == BADIDX) {
14911 + SB_ERROR(("sb_pci_fixcfg: bad core index\n"));
14912 + return -1;
14913 + }
14914 + }
14915 +
14916 + return 0;
14917 +}
14918 +
14919 +static uint
14920 +sb_chipc_capability(sb_t *sbh)
14921 +{
14922 + sb_info_t *si;
14923 +
14924 + si = SB_INFO(sbh);
14925 +
14926 + /* Make sure that there is ChipCommon core present */
14927 + if (si->coreid[SB_CC_IDX] == SB_CC)
14928 + return (sb_corereg(si, SB_CC_IDX, OFFSETOF(chipcregs_t, capabilities),
14929 + 0, 0));
14930 + return 0;
14931 +}
14932 +
14933 +/* Return ADDR64 capability of the backplane */
14934 +bool
14935 +sb_backplane64(sb_t *sbh)
14936 +{
14937 + return ((sb_chipc_capability(sbh) & CAP_BKPLN64) != 0);
14938 +}
14939 +
14940 +void
14941 +sb_btcgpiowar(sb_t *sbh)
14942 +{
14943 + sb_info_t *si;
14944 + uint origidx;
14945 + uint intr_val = 0;
14946 + chipcregs_t *cc;
14947 + si = SB_INFO(sbh);
14948 +
14949 + /* Make sure that there is ChipCommon core present &&
14950 + * UART_TX is strapped to 1
14951 + */
14952 + if (!(sb_chipc_capability(sbh) & CAP_UARTGPIO))
14953 + return;
14954 +
14955 + /* sb_corereg cannot be used as we have to guarantee 8-bit read/writes */
14956 + INTR_OFF(si, intr_val);
14957 +
14958 + origidx = sb_coreidx(sbh);
14959 +
14960 + cc = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
14961 + if (cc == NULL)
14962 + goto end;
14963 +
14964 + W_REG(si->osh, &cc->uart0mcr, R_REG(si->osh, &cc->uart0mcr) | 0x04);
14965 +
14966 +end:
14967 + /* restore the original index */
14968 + sb_setcoreidx(sbh, origidx);
14969 +
14970 + INTR_RESTORE(si, intr_val);
14971 +}
14972 +
14973 +/* check if the device is removed */
14974 +bool
14975 +sb_deviceremoved(sb_t *sbh)
14976 +{
14977 + uint32 w;
14978 + sb_info_t *si;
14979 +
14980 + si = SB_INFO(sbh);
14981 +
14982 + switch (BUSTYPE(si->sb.bustype)) {
14983 + case PCI_BUS:
14984 + ASSERT(si->osh);
14985 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_VID, sizeof(uint32));
14986 + if ((w & 0xFFFF) != VENDOR_BROADCOM)
14987 + return TRUE;
14988 + else
14989 + return FALSE;
14990 + default:
14991 + return FALSE;
14992 + }
14993 + return FALSE;
14994 +}
14995 +
14996 +/* Return the RAM size of the SOCRAM core */
14997 +uint32
14998 +sb_socram_size(sb_t *sbh)
14999 +{
15000 + sb_info_t *si;
15001 + uint origidx;
15002 + uint intr_val = 0;
15003 +
15004 + sbsocramregs_t *regs;
15005 + bool wasup;
15006 + uint corerev;
15007 + uint32 coreinfo;
15008 + uint memsize = 0;
15009 +
15010 + si = SB_INFO(sbh);
15011 + ASSERT(si);
15012 +
15013 + /* Block ints and save current core */
15014 + INTR_OFF(si, intr_val);
15015 + origidx = sb_coreidx(sbh);
15016 +
15017 + /* Switch to SOCRAM core */
15018 + if (!(regs = sb_setcore(sbh, SB_SOCRAM, 0)))
15019 + goto done;
15020 +
15021 + /* Get info for determining size */
15022 + if (!(wasup = sb_iscoreup(sbh)))
15023 + sb_core_reset(sbh, 0, 0);
15024 + corerev = sb_corerev(sbh);
15025 + coreinfo = R_REG(si->osh, &regs->coreinfo);
15026 +
15027 + /* Calculate size from coreinfo based on rev */
15028 + switch (corerev) {
15029 + case 0:
15030 + memsize = 1 << (16 + (coreinfo & SRCI_MS0_MASK));
15031 + break;
15032 + default: /* rev >= 1 */
15033 + memsize = 1 << (SR_BSZ_BASE + (coreinfo & SRCI_SRBSZ_MASK));
15034 + memsize *= (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
15035 + break;
15036 + }
15037 +
15038 + /* Return to previous state and core */
15039 + if (!wasup)
15040 + sb_core_disable(sbh, 0);
15041 + sb_setcoreidx(sbh, origidx);
15042 +
15043 +done:
15044 + INTR_RESTORE(si, intr_val);
15045 + return memsize;
15046 +}
15047 +
15048 +
15049 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
15050 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
15051 +++ linux.dev/arch/mips/bcm947xx/setup.c 2006-10-02 21:19:59.000000000 +0200
15052 @@ -0,0 +1,241 @@
15053 +/*
15054 + * Generic setup routines for Broadcom MIPS boards
15055 + *
15056 + * Copyright (C) 2005 Felix Fietkau <nbd@openwrt.org>
15057 + *
15058 + * This program is free software; you can redistribute it and/or modify it
15059 + * under the terms of the GNU General Public License as published by the
15060 + * Free Software Foundation; either version 2 of the License, or (at your
15061 + * option) any later version.
15062 + *
15063 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15064 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15065 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15066 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15067 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15068 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15069 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
15070 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15071 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
15072 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15073 + *
15074 + * You should have received a copy of the GNU General Public License along
15075 + * with this program; if not, write to the Free Software Foundation, Inc.,
15076 + * 675 Mass Ave, Cambridge, MA 02139, USA.
15077 + *
15078 + *
15079 + * Copyright 2005, Broadcom Corporation
15080 + * All Rights Reserved.
15081 + *
15082 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15083 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15084 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15085 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15086 + *
15087 + */
15088 +
15089 +#include <linux/config.h>
15090 +#include <linux/init.h>
15091 +#include <linux/kernel.h>
15092 +#include <linux/module.h>
15093 +#include <linux/serialP.h>
15094 +#include <linux/ide.h>
15095 +#include <asm/bootinfo.h>
15096 +#include <asm/cpu.h>
15097 +#include <asm/time.h>
15098 +#include <asm/reboot.h>
15099 +
15100 +#include <typedefs.h>
15101 +#include <osl.h>
15102 +#include <sbutils.h>
15103 +#include <bcmutils.h>
15104 +#include <bcmnvram.h>
15105 +#include <sbhndmips.h>
15106 +#include <hndmips.h>
15107 +#include <trxhdr.h>
15108 +
15109 +/* Virtual IRQ base, after last hw IRQ */
15110 +#define SBMIPS_VIRTIRQ_BASE 6
15111 +
15112 +/* # IRQs, hw and sw IRQs */
15113 +#define SBMIPS_NUMIRQS 8
15114 +
15115 +/* Global SB handle */
15116 +sb_t *bcm947xx_sbh = NULL;
15117 +spinlock_t bcm947xx_sbh_lock = SPIN_LOCK_UNLOCKED;
15118 +
15119 +/* Convenience */
15120 +#define sbh bcm947xx_sbh
15121 +#define sbh_lock bcm947xx_sbh_lock
15122 +
15123 +extern void bcm947xx_time_init(void);
15124 +extern void bcm947xx_timer_setup(struct irqaction *irq);
15125 +
15126 +#ifdef CONFIG_REMOTE_DEBUG
15127 +extern void set_debug_traps(void);
15128 +extern void rs_kgdb_hook(struct serial_state *);
15129 +extern void breakpoint(void);
15130 +#endif
15131 +
15132 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
15133 +extern struct ide_ops std_ide_ops;
15134 +#endif
15135 +
15136 +/* Kernel command line */
15137 +char arcs_cmdline[CL_SIZE] __initdata = CONFIG_CMDLINE;
15138 +extern void sb_serial_init(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
15139 +
15140 +void
15141 +bcm947xx_machine_restart(char *command)
15142 +{
15143 + printk("Please stand by while rebooting the system...\n");
15144 +
15145 + /* Set the watchdog timer to reset immediately */
15146 + __cli();
15147 + sb_watchdog(sbh, 1);
15148 + while (1);
15149 +}
15150 +
15151 +void
15152 +bcm947xx_machine_halt(void)
15153 +{
15154 + printk("System halted\n");
15155 +
15156 + /* Disable interrupts and watchdog and spin forever */
15157 + __cli();
15158 + sb_watchdog(sbh, 0);
15159 + while (1);
15160 +}
15161 +
15162 +#ifdef CONFIG_SERIAL
15163 +
15164 +static int ser_line = 0;
15165 +
15166 +typedef struct {
15167 + void *regs;
15168 + uint irq;
15169 + uint baud_base;
15170 + uint reg_shift;
15171 +} serial_port;
15172 +
15173 +static serial_port ports[4];
15174 +static int num_ports = 0;
15175 +
15176 +static void
15177 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
15178 +{
15179 + ports[num_ports].regs = regs;
15180 + ports[num_ports].irq = irq;
15181 + ports[num_ports].baud_base = baud_base;
15182 + ports[num_ports].reg_shift = reg_shift;
15183 + num_ports++;
15184 +}
15185 +
15186 +static void
15187 +do_serial_add(serial_port *port)
15188 +{
15189 + void *regs;
15190 + uint irq;
15191 + uint baud_base;
15192 + uint reg_shift;
15193 + struct serial_struct s;
15194 +
15195 + regs = port->regs;
15196 + irq = port->irq;
15197 + baud_base = port->baud_base;
15198 + reg_shift = port->reg_shift;
15199 +
15200 + memset(&s, 0, sizeof(s));
15201 +
15202 + s.line = ser_line++;
15203 + s.iomem_base = regs;
15204 + s.irq = irq + 2;
15205 + s.baud_base = baud_base / 16;
15206 + s.flags = ASYNC_BOOT_AUTOCONF;
15207 + s.io_type = SERIAL_IO_MEM;
15208 + s.iomem_reg_shift = reg_shift;
15209 +
15210 + if (early_serial_setup(&s) != 0) {
15211 + printk(KERN_ERR "Serial setup failed!\n");
15212 + }
15213 +}
15214 +
15215 +#endif /* CONFIG_SERIAL */
15216 +
15217 +void __init
15218 +brcm_setup(void)
15219 +{
15220 + char *s;
15221 + int i;
15222 + char *value;
15223 +
15224 + /* Get global SB handle */
15225 + sbh = sb_kattach();
15226 +
15227 + /* Initialize clocks and interrupts */
15228 + sb_mips_init(sbh, SBMIPS_VIRTIRQ_BASE);
15229 +
15230 + if (BCM330X(current_cpu_data.processor_id) &&
15231 + (read_c0_diag() & BRCM_PFC_AVAIL)) {
15232 + /*
15233 + * Now that the sbh is inited set the proper PFC value
15234 + */
15235 + printk("Setting the PFC to its default value\n");
15236 + enable_pfc(PFC_AUTO);
15237 + }
15238 +
15239 +
15240 +#ifdef CONFIG_SERIAL
15241 + sb_serial_init(sbh, serial_add);
15242 +
15243 + /* reverse serial ports if nvram variable starts with console=ttyS1 */
15244 + /* Initialize UARTs */
15245 + s = nvram_get("kernel_args");
15246 + if (!s) s = "";
15247 + if (!strncmp(s, "console=ttyS1", 13)) {
15248 + for (i = num_ports; i; i--)
15249 + do_serial_add(&ports[i - 1]);
15250 + } else {
15251 + for (i = 0; i < num_ports; i++)
15252 + do_serial_add(&ports[i]);
15253 + }
15254 +#endif
15255 +
15256 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
15257 + ide_ops = &std_ide_ops;
15258 +#endif
15259 +
15260 + /* Override default command line arguments */
15261 + value = nvram_get("kernel_cmdline");
15262 + if (value && strlen(value) && strncmp(value, "empty", 5))
15263 + strncpy(arcs_cmdline, value, sizeof(arcs_cmdline));
15264 +
15265 +
15266 + /* Generic setup */
15267 + _machine_restart = bcm947xx_machine_restart;
15268 + _machine_halt = bcm947xx_machine_halt;
15269 + _machine_power_off = bcm947xx_machine_halt;
15270 +
15271 + board_time_init = bcm947xx_time_init;
15272 + board_timer_setup = bcm947xx_timer_setup;
15273 +}
15274 +
15275 +const char *
15276 +get_system_type(void)
15277 +{
15278 + static char s[32];
15279 +
15280 + if (bcm947xx_sbh) {
15281 + sprintf(s, "Broadcom BCM%X chip rev %d", sb_chip(bcm947xx_sbh),
15282 + sb_chiprev(bcm947xx_sbh));
15283 + return s;
15284 + }
15285 + else
15286 + return "Broadcom BCM947XX";
15287 +}
15288 +
15289 +void __init
15290 +bus_error_init(void)
15291 +{
15292 +}
15293 +
15294 diff -urN linux.old/arch/mips/bcm947xx/sflash.c linux.dev/arch/mips/bcm947xx/sflash.c
15295 --- linux.old/arch/mips/bcm947xx/sflash.c 1970-01-01 01:00:00.000000000 +0100
15296 +++ linux.dev/arch/mips/bcm947xx/sflash.c 2006-10-02 21:19:59.000000000 +0200
15297 @@ -0,0 +1,422 @@
15298 +/*
15299 + * Broadcom SiliconBackplane chipcommon serial flash interface
15300 + *
15301 + * Copyright 2006, Broadcom Corporation
15302 + * All Rights Reserved.
15303 + *
15304 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15305 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15306 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15307 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15308 + *
15309 + * $Id: sflash.c,v 1.1.1.13 2006/02/27 03:43:16 honor Exp $
15310 + */
15311 +
15312 +#include <osl.h>
15313 +#include <typedefs.h>
15314 +#include <sbconfig.h>
15315 +#include <sbchipc.h>
15316 +#include <mipsinc.h>
15317 +#include <bcmutils.h>
15318 +#include <bcmdevs.h>
15319 +#include <sflash.h>
15320 +
15321 +/* Private global state */
15322 +static struct sflash sflash;
15323 +
15324 +/* Issue a serial flash command */
15325 +static INLINE void
15326 +sflash_cmd(chipcregs_t *cc, uint opcode)
15327 +{
15328 + W_REG(NULL, &cc->flashcontrol, SFLASH_START | opcode);
15329 + while (R_REG(NULL, &cc->flashcontrol) & SFLASH_BUSY);
15330 +}
15331 +
15332 +/* Initialize serial flash access */
15333 +struct sflash *
15334 +sflash_init(chipcregs_t *cc)
15335 +{
15336 + uint32 id, id2;
15337 +
15338 + bzero(&sflash, sizeof(sflash));
15339 +
15340 + sflash.type = R_REG(NULL, &cc->capabilities) & CAP_FLASH_MASK;
15341 +
15342 + switch (sflash.type) {
15343 + case SFLASH_ST:
15344 + /* Probe for ST chips */
15345 + sflash_cmd(cc, SFLASH_ST_DP);
15346 + sflash_cmd(cc, SFLASH_ST_RES);
15347 + id = R_REG(NULL, &cc->flashdata);
15348 + switch (id) {
15349 + case 0x11:
15350 + /* ST M25P20 2 Mbit Serial Flash */
15351 + sflash.blocksize = 64 * 1024;
15352 + sflash.numblocks = 4;
15353 + break;
15354 + case 0x12:
15355 + /* ST M25P40 4 Mbit Serial Flash */
15356 + sflash.blocksize = 64 * 1024;
15357 + sflash.numblocks = 8;
15358 + break;
15359 + case 0x13:
15360 + /* ST M25P80 8 Mbit Serial Flash */
15361 + sflash.blocksize = 64 * 1024;
15362 + sflash.numblocks = 16;
15363 + break;
15364 + case 0x14:
15365 + /* ST M25P16 16 Mbit Serial Flash */
15366 + sflash.blocksize = 64 * 1024;
15367 + sflash.numblocks = 32;
15368 + break;
15369 + case 0x15:
15370 + /* ST M25P32 32 Mbit Serial Flash */
15371 + sflash.blocksize = 64 * 1024;
15372 + sflash.numblocks = 64;
15373 + break;
15374 + case 0x16:
15375 + /* ST M25P64 64 Mbit Serial Flash */
15376 + sflash.blocksize = 64 * 1024;
15377 + sflash.numblocks = 128;
15378 + break;
15379 + case 0xbf:
15380 + W_REG(NULL, &cc->flashaddress, 1);
15381 + sflash_cmd(cc, SFLASH_ST_RES);
15382 + id2 = R_REG(NULL, &cc->flashdata);
15383 + if (id2 == 0x44) {
15384 + /* SST M25VF80 4 Mbit Serial Flash */
15385 + sflash.blocksize = 64 * 1024;
15386 + sflash.numblocks = 8;
15387 + }
15388 + break;
15389 + }
15390 + break;
15391 +
15392 + case SFLASH_AT:
15393 + /* Probe for Atmel chips */
15394 + sflash_cmd(cc, SFLASH_AT_STATUS);
15395 + id = R_REG(NULL, &cc->flashdata) & 0x3c;
15396 + switch (id) {
15397 + case 0xc:
15398 + /* Atmel AT45DB011 1Mbit Serial Flash */
15399 + sflash.blocksize = 256;
15400 + sflash.numblocks = 512;
15401 + break;
15402 + case 0x14:
15403 + /* Atmel AT45DB021 2Mbit Serial Flash */
15404 + sflash.blocksize = 256;
15405 + sflash.numblocks = 1024;
15406 + break;
15407 + case 0x1c:
15408 + /* Atmel AT45DB041 4Mbit Serial Flash */
15409 + sflash.blocksize = 256;
15410 + sflash.numblocks = 2048;
15411 + break;
15412 + case 0x24:
15413 + /* Atmel AT45DB081 8Mbit Serial Flash */
15414 + sflash.blocksize = 256;
15415 + sflash.numblocks = 4096;
15416 + break;
15417 + case 0x2c:
15418 + /* Atmel AT45DB161 16Mbit Serial Flash */
15419 + sflash.blocksize = 512;
15420 + sflash.numblocks = 4096;
15421 + break;
15422 + case 0x34:
15423 + /* Atmel AT45DB321 32Mbit Serial Flash */
15424 + sflash.blocksize = 512;
15425 + sflash.numblocks = 8192;
15426 + break;
15427 + case 0x3c:
15428 + /* Atmel AT45DB642 64Mbit Serial Flash */
15429 + sflash.blocksize = 1024;
15430 + sflash.numblocks = 8192;
15431 + break;
15432 + }
15433 + break;
15434 + }
15435 +
15436 + sflash.size = sflash.blocksize * sflash.numblocks;
15437 + return sflash.size ? &sflash : NULL;
15438 +}
15439 +
15440 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
15441 +int
15442 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
15443 +{
15444 + int cnt;
15445 + uint32 *from, *to;
15446 +
15447 + if (!len)
15448 + return 0;
15449 +
15450 + if ((offset + len) > sflash.size)
15451 + return -22;
15452 +
15453 + if ((len >= 4) && (offset & 3))
15454 + cnt = 4 - (offset & 3);
15455 + else if ((len >= 4) && ((uint32)buf & 3))
15456 + cnt = 4 - ((uint32)buf & 3);
15457 + else
15458 + cnt = len;
15459 +
15460 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
15461 + to = (uint32 *)buf;
15462 +
15463 + if (cnt < 4) {
15464 + bcopy(from, to, cnt);
15465 + return cnt;
15466 + }
15467 +
15468 + while (cnt >= 4) {
15469 + *to++ = *from++;
15470 + cnt -= 4;
15471 + }
15472 +
15473 + return (len - cnt);
15474 +}
15475 +
15476 +/* Poll for command completion. Returns zero when complete. */
15477 +int
15478 +sflash_poll(chipcregs_t *cc, uint offset)
15479 +{
15480 + if (offset >= sflash.size)
15481 + return -22;
15482 +
15483 + switch (sflash.type) {
15484 + case SFLASH_ST:
15485 + /* Check for ST Write In Progress bit */
15486 + sflash_cmd(cc, SFLASH_ST_RDSR);
15487 + return R_REG(NULL, &cc->flashdata) & SFLASH_ST_WIP;
15488 + case SFLASH_AT:
15489 + /* Check for Atmel Ready bit */
15490 + sflash_cmd(cc, SFLASH_AT_STATUS);
15491 + return !(R_REG(NULL, &cc->flashdata) & SFLASH_AT_READY);
15492 + }
15493 +
15494 + return 0;
15495 +}
15496 +
15497 +/* Write len bytes starting at offset into buf. Returns number of bytes
15498 + * written. Caller should poll for completion.
15499 + */
15500 +int
15501 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
15502 +{
15503 + struct sflash *sfl;
15504 + int ret = 0;
15505 + bool is4712b0;
15506 + uint32 page, byte, mask;
15507 +
15508 + if (!len)
15509 + return 0;
15510 +
15511 + if ((offset + len) > sflash.size)
15512 + return -22;
15513 +
15514 + sfl = &sflash;
15515 + switch (sfl->type) {
15516 + case SFLASH_ST:
15517 + mask = R_REG(NULL, &cc->chipid);
15518 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_CHIP_ID) &&
15519 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
15520 + /* Enable writes */
15521 + sflash_cmd(cc, SFLASH_ST_WREN);
15522 + if (is4712b0) {
15523 + mask = 1 << 14;
15524 + W_REG(NULL, &cc->flashaddress, offset);
15525 + W_REG(NULL, &cc->flashdata, *buf++);
15526 + /* Set chip select */
15527 + OR_REG(NULL, &cc->gpioout, mask);
15528 + /* Issue a page program with the first byte */
15529 + sflash_cmd(cc, SFLASH_ST_PP);
15530 + ret = 1;
15531 + offset++;
15532 + len--;
15533 + while (len > 0) {
15534 + if ((offset & 255) == 0) {
15535 + /* Page boundary, drop cs and return */
15536 + AND_REG(NULL, &cc->gpioout, ~mask);
15537 + if (!sflash_poll(cc, offset)) {
15538 + /* Flash rejected command */
15539 + return -11;
15540 + }
15541 + return ret;
15542 + } else {
15543 + /* Write single byte */
15544 + sflash_cmd(cc, *buf++);
15545 + }
15546 + ret++;
15547 + offset++;
15548 + len--;
15549 + }
15550 + /* All done, drop cs if needed */
15551 + if ((offset & 255) != 1) {
15552 + /* Drop cs */
15553 + AND_REG(NULL, &cc->gpioout, ~mask);
15554 + if (!sflash_poll(cc, offset)) {
15555 + /* Flash rejected command */
15556 + return -12;
15557 + }
15558 + }
15559 + } else {
15560 + ret = 1;
15561 + W_REG(NULL, &cc->flashaddress, offset);
15562 + W_REG(NULL, &cc->flashdata, *buf);
15563 + /* Page program */
15564 + sflash_cmd(cc, SFLASH_ST_PP);
15565 + }
15566 + break;
15567 + case SFLASH_AT:
15568 + mask = sfl->blocksize - 1;
15569 + page = (offset & ~mask) << 1;
15570 + byte = offset & mask;
15571 + /* Read main memory page into buffer 1 */
15572 + if (byte || (len < sfl->blocksize)) {
15573 + W_REG(NULL, &cc->flashaddress, page);
15574 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
15575 + /* 250 us for AT45DB321B */
15576 + SPINWAIT(sflash_poll(cc, offset), 1000);
15577 + ASSERT(!sflash_poll(cc, offset));
15578 + }
15579 + /* Write into buffer 1 */
15580 + for (ret = 0; (ret < (int)len) && (byte < sfl->blocksize); ret++) {
15581 + W_REG(NULL, &cc->flashaddress, byte++);
15582 + W_REG(NULL, &cc->flashdata, *buf++);
15583 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
15584 + }
15585 + /* Write buffer 1 into main memory page */
15586 + W_REG(NULL, &cc->flashaddress, page);
15587 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
15588 + break;
15589 + }
15590 +
15591 + return ret;
15592 +}
15593 +
15594 +/* Erase a region. Returns number of bytes scheduled for erasure.
15595 + * Caller should poll for completion.
15596 + */
15597 +int
15598 +sflash_erase(chipcregs_t *cc, uint offset)
15599 +{
15600 + struct sflash *sfl;
15601 +
15602 + if (offset >= sflash.size)
15603 + return -22;
15604 +
15605 + sfl = &sflash;
15606 + switch (sfl->type) {
15607 + case SFLASH_ST:
15608 + sflash_cmd(cc, SFLASH_ST_WREN);
15609 + W_REG(NULL, &cc->flashaddress, offset);
15610 + sflash_cmd(cc, SFLASH_ST_SE);
15611 + return sfl->blocksize;
15612 + case SFLASH_AT:
15613 + W_REG(NULL, &cc->flashaddress, offset << 1);
15614 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
15615 + return sfl->blocksize;
15616 + }
15617 +
15618 + return 0;
15619 +}
15620 +
15621 +/*
15622 + * writes the appropriate range of flash, a NULL buf simply erases
15623 + * the region of flash
15624 + */
15625 +int
15626 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
15627 +{
15628 + struct sflash *sfl;
15629 + uchar *block = NULL, *cur_ptr, *blk_ptr;
15630 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
15631 + uint blk_offset, blk_len, copied;
15632 + int bytes, ret = 0;
15633 +
15634 + /* Check address range */
15635 + if (len <= 0)
15636 + return 0;
15637 +
15638 + sfl = &sflash;
15639 + if ((offset + len) > sfl->size)
15640 + return -1;
15641 +
15642 + blocksize = sfl->blocksize;
15643 + mask = blocksize - 1;
15644 +
15645 + /* Allocate a block of mem */
15646 + if (!(block = MALLOC(NULL, blocksize)))
15647 + return -1;
15648 +
15649 + while (len) {
15650 + /* Align offset */
15651 + cur_offset = offset & ~mask;
15652 + cur_length = blocksize;
15653 + cur_ptr = block;
15654 +
15655 + remainder = blocksize - (offset & mask);
15656 + if (len < remainder)
15657 + cur_retlen = len;
15658 + else
15659 + cur_retlen = remainder;
15660 +
15661 + /* buf == NULL means erase only */
15662 + if (buf) {
15663 + /* Copy existing data into holding block if necessary */
15664 + if ((offset & mask) || (len < blocksize)) {
15665 + blk_offset = cur_offset;
15666 + blk_len = cur_length;
15667 + blk_ptr = cur_ptr;
15668 +
15669 + /* Copy entire block */
15670 + while (blk_len) {
15671 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
15672 + blk_offset += copied;
15673 + blk_len -= copied;
15674 + blk_ptr += copied;
15675 + }
15676 + }
15677 +
15678 + /* Copy input data into holding block */
15679 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
15680 + }
15681 +
15682 + /* Erase block */
15683 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
15684 + goto done;
15685 + while (sflash_poll(cc, (uint) cur_offset));
15686 +
15687 + /* buf == NULL means erase only */
15688 + if (!buf) {
15689 + offset += cur_retlen;
15690 + len -= cur_retlen;
15691 + continue;
15692 + }
15693 +
15694 + /* Write holding block */
15695 + while (cur_length > 0) {
15696 + if ((bytes = sflash_write(cc,
15697 + (uint) cur_offset,
15698 + (uint) cur_length,
15699 + (uchar *) cur_ptr)) < 0) {
15700 + ret = bytes;
15701 + goto done;
15702 + }
15703 + while (sflash_poll(cc, (uint) cur_offset));
15704 + cur_offset += bytes;
15705 + cur_length -= bytes;
15706 + cur_ptr += bytes;
15707 + }
15708 +
15709 + offset += cur_retlen;
15710 + len -= cur_retlen;
15711 + buf += cur_retlen;
15712 + }
15713 +
15714 + ret = len;
15715 +done:
15716 + if (block)
15717 + MFREE(NULL, block, blocksize);
15718 + return ret;
15719 +}
15720 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
15721 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
15722 +++ linux.dev/arch/mips/bcm947xx/time.c 2006-10-02 21:19:59.000000000 +0200
15723 @@ -0,0 +1,104 @@
15724 +/*
15725 + * Copyright 2006, Broadcom Corporation
15726 + * All Rights Reserved.
15727 + *
15728 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15729 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15730 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15731 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15732 + *
15733 + * $Id: time.c,v 1.1.1.10 2006/02/27 03:42:55 honor Exp $
15734 + */
15735 +#include <linux/config.h>
15736 +#include <linux/init.h>
15737 +#include <linux/kernel.h>
15738 +#include <linux/sched.h>
15739 +#include <linux/serial_reg.h>
15740 +#include <linux/interrupt.h>
15741 +#include <asm/addrspace.h>
15742 +#include <asm/io.h>
15743 +#include <asm/time.h>
15744 +
15745 +#include <typedefs.h>
15746 +#include <osl.h>
15747 +#include <bcmnvram.h>
15748 +#include <sbconfig.h>
15749 +#include <sbextif.h>
15750 +#include <sbutils.h>
15751 +#include <hndmips.h>
15752 +#include <mipsinc.h>
15753 +#include <hndcpu.h>
15754 +
15755 +/* Global SB handle */
15756 +extern void *bcm947xx_sbh;
15757 +extern spinlock_t bcm947xx_sbh_lock;
15758 +
15759 +/* Convenience */
15760 +#define sbh bcm947xx_sbh
15761 +#define sbh_lock bcm947xx_sbh_lock
15762 +
15763 +extern int panic_timeout;
15764 +static int watchdog = 0;
15765 +static u8 *mcr = NULL;
15766 +
15767 +void __init
15768 +bcm947xx_time_init(void)
15769 +{
15770 + unsigned int hz;
15771 + extifregs_t *eir;
15772 +
15773 + /*
15774 + * Use deterministic values for initial counter interrupt
15775 + * so that calibrate delay avoids encountering a counter wrap.
15776 + */
15777 + write_c0_count(0);
15778 + write_c0_compare(0xffff);
15779 +
15780 + if (!(hz = sb_cpu_clock(sbh)))
15781 + hz = 100000000;
15782 +
15783 + printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
15784 + (hz + 500000) / 1000000);
15785 +
15786 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
15787 + mips_hpt_frequency = hz / 2;
15788 +
15789 + /* Set watchdog interval in ms */
15790 + watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
15791 +
15792 + /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
15793 + if (watchdog > 0) {
15794 + if (watchdog < 3000)
15795 + watchdog = 3000;
15796 + }
15797 +
15798 + /* Set panic timeout in seconds */
15799 + panic_timeout = watchdog / 1000;
15800 +}
15801 +
15802 +static void
15803 +bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
15804 +{
15805 + /* Generic MIPS timer code */
15806 + timer_interrupt(irq, dev_id, regs);
15807 +
15808 + /* Set the watchdog timer to reset after the specified number of ms */
15809 + if (watchdog > 0)
15810 + sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
15811 +}
15812 +
15813 +static struct irqaction bcm947xx_timer_irqaction = {
15814 + bcm947xx_timer_interrupt,
15815 + SA_INTERRUPT,
15816 + 0,
15817 + "timer",
15818 + NULL,
15819 + NULL
15820 +};
15821 +
15822 +void __init
15823 +bcm947xx_timer_setup(struct irqaction *irq)
15824 +{
15825 + /* Enable the timer interrupt */
15826 + setup_irq(7, &bcm947xx_timer_irqaction);
15827 +}
15828 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
15829 --- linux.old/arch/mips/config-shared.in 2006-10-02 21:23:10.000000000 +0200
15830 +++ linux.dev/arch/mips/config-shared.in 2006-10-02 21:19:59.000000000 +0200
15831 @@ -208,6 +208,14 @@
15832 fi
15833 define_bool CONFIG_MIPS_RTC y
15834 fi
15835 +dep_bool 'Support for Broadcom MIPS-based boards' CONFIG_MIPS_BRCM $CONFIG_EXPERIMENTAL
15836 +dep_bool 'Support for Broadcom BCM947XX' CONFIG_BCM947XX $CONFIG_MIPS_BRCM
15837 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15838 + bool ' Support for Broadcom BCM4710' CONFIG_BCM4710
15839 + bool ' Support for Broadcom BCM4310' CONFIG_BCM4310
15840 + bool ' Support for Broadcom BCM4704' CONFIG_BCM4704
15841 + bool ' Support for Broadcom BCM5365' CONFIG_BCM5365
15842 +fi
15843 bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
15844 bool 'Support for TANBAC TB0226 (Mbase)' CONFIG_TANBAC_TB0226
15845 bool 'Support for TANBAC TB0229 (VR4131DIMM)' CONFIG_TANBAC_TB0229
15846 @@ -229,6 +237,11 @@
15847 define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
15848
15849 #
15850 +# Provide an option for a default kernel command line
15851 +#
15852 +string 'Default kernel command string' CONFIG_CMDLINE ""
15853 +
15854 +#
15855 # Select some configuration options automatically based on user selections.
15856 #
15857 if [ "$CONFIG_ACER_PICA_61" = "y" ]; then
15858 @@ -554,6 +567,12 @@
15859 define_bool CONFIG_SWAP_IO_SPACE_L y
15860 define_bool CONFIG_BOOT_ELF32 y
15861 fi
15862 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15863 + define_bool CONFIG_PCI y
15864 + define_bool CONFIG_NONCOHERENT_IO y
15865 + define_bool CONFIG_NEW_TIME_C y
15866 + define_bool CONFIG_NEW_IRQ y
15867 +fi
15868 if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
15869 define_bool CONFIG_ARC32 y
15870 define_bool CONFIG_ARC_MEMORY y
15871 @@ -1042,7 +1061,11 @@
15872
15873 bool 'Are you using a crosscompiler' CONFIG_CROSSCOMPILE
15874 bool 'Enable run-time debugging' CONFIG_RUNTIME_DEBUG
15875 -bool 'Remote GDB kernel debugging' CONFIG_KGDB
15876 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15877 + bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG
15878 +else
15879 + bool 'Remote GDB kernel debugging' CONFIG_KGDB
15880 +fi
15881 dep_bool ' Console output to GDB' CONFIG_GDB_CONSOLE $CONFIG_KGDB
15882 if [ "$CONFIG_KGDB" = "y" ]; then
15883 define_bool CONFIG_DEBUG_INFO y
15884 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
15885 --- linux.old/arch/mips/kernel/cpu-probe.c 2006-10-02 21:23:10.000000000 +0200
15886 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2006-10-02 21:19:59.000000000 +0200
15887 @@ -162,7 +162,7 @@
15888
15889 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
15890 {
15891 - switch (c->processor_id & 0xff00) {
15892 + switch (c->processor_id & PRID_IMP_MASK) {
15893 case PRID_IMP_R2000:
15894 c->cputype = CPU_R2000;
15895 c->isa_level = MIPS_CPU_ISA_I;
15896 @@ -172,7 +172,7 @@
15897 c->tlbsize = 64;
15898 break;
15899 case PRID_IMP_R3000:
15900 - if ((c->processor_id & 0xff) == PRID_REV_R3000A)
15901 + if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A)
15902 if (cpu_has_confreg())
15903 c->cputype = CPU_R3081E;
15904 else
15905 @@ -187,12 +187,12 @@
15906 break;
15907 case PRID_IMP_R4000:
15908 if (read_c0_config() & CONF_SC) {
15909 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
15910 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
15911 c->cputype = CPU_R4400PC;
15912 else
15913 c->cputype = CPU_R4000PC;
15914 } else {
15915 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
15916 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
15917 c->cputype = CPU_R4400SC;
15918 else
15919 c->cputype = CPU_R4000SC;
15920 @@ -438,7 +438,7 @@
15921 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
15922 {
15923 decode_config1(c);
15924 - switch (c->processor_id & 0xff00) {
15925 + switch (c->processor_id & PRID_IMP_MASK) {
15926 case PRID_IMP_4KC:
15927 c->cputype = CPU_4KC;
15928 c->isa_level = MIPS_CPU_ISA_M32;
15929 @@ -479,10 +479,10 @@
15930 {
15931 decode_config1(c);
15932 c->options |= MIPS_CPU_PREFETCH;
15933 - switch (c->processor_id & 0xff00) {
15934 + switch (c->processor_id & PRID_IMP_MASK) {
15935 case PRID_IMP_AU1_REV1:
15936 case PRID_IMP_AU1_REV2:
15937 - switch ((c->processor_id >> 24) & 0xff) {
15938 + switch ((c->processor_id >> 24) & PRID_REV_MASK) {
15939 case 0:
15940 c->cputype = CPU_AU1000;
15941 break;
15942 @@ -510,10 +510,34 @@
15943 }
15944 }
15945
15946 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
15947 +{
15948 + decode_config1(c);
15949 + c->options |= MIPS_CPU_PREFETCH;
15950 + switch (c->processor_id & PRID_IMP_MASK) {
15951 + case PRID_IMP_BCM4710:
15952 + c->cputype = CPU_BCM4710;
15953 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
15954 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
15955 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
15956 + break;
15957 + case PRID_IMP_4KC:
15958 + case PRID_IMP_BCM3302:
15959 + c->cputype = CPU_BCM3302;
15960 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
15961 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
15962 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
15963 + break;
15964 + default:
15965 + c->cputype = CPU_UNKNOWN;
15966 + break;
15967 + }
15968 +}
15969 +
15970 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
15971 {
15972 decode_config1(c);
15973 - switch (c->processor_id & 0xff00) {
15974 + switch (c->processor_id & PRID_IMP_MASK) {
15975 case PRID_IMP_SB1:
15976 c->cputype = CPU_SB1;
15977 c->isa_level = MIPS_CPU_ISA_M64;
15978 @@ -535,7 +559,7 @@
15979 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
15980 {
15981 decode_config1(c);
15982 - switch (c->processor_id & 0xff00) {
15983 + switch (c->processor_id & PRID_IMP_MASK) {
15984 case PRID_IMP_SR71000:
15985 c->cputype = CPU_SR71000;
15986 c->isa_level = MIPS_CPU_ISA_M64;
15987 @@ -560,7 +584,7 @@
15988 c->cputype = CPU_UNKNOWN;
15989
15990 c->processor_id = read_c0_prid();
15991 - switch (c->processor_id & 0xff0000) {
15992 + switch (c->processor_id & PRID_COMP_MASK) {
15993
15994 case PRID_COMP_LEGACY:
15995 cpu_probe_legacy(c);
15996 @@ -571,6 +595,9 @@
15997 case PRID_COMP_ALCHEMY:
15998 cpu_probe_alchemy(c);
15999 break;
16000 + case PRID_COMP_BROADCOM:
16001 + cpu_probe_broadcom(c);
16002 + break;
16003 case PRID_COMP_SIBYTE:
16004 cpu_probe_sibyte(c);
16005 break;
16006 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
16007 --- linux.old/arch/mips/kernel/head.S 2006-10-02 21:23:10.000000000 +0200
16008 +++ linux.dev/arch/mips/kernel/head.S 2006-10-02 21:19:59.000000000 +0200
16009 @@ -28,12 +28,20 @@
16010 #include <asm/mipsregs.h>
16011 #include <asm/stackframe.h>
16012
16013 +#ifdef CONFIG_BCM4710
16014 +#undef eret
16015 +#define eret nop; nop; eret
16016 +#endif
16017 +
16018 .text
16019 + j kernel_entry
16020 + nop
16021 +
16022 /*
16023 * Reserved space for exception handlers.
16024 * Necessary for machines which link their kernels at KSEG0.
16025 */
16026 - .fill 0x400
16027 + .fill 0x3f4
16028
16029 /* The following two symbols are used for kernel profiling. */
16030 EXPORT(stext)
16031 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
16032 --- linux.old/arch/mips/kernel/proc.c 2006-10-02 21:23:10.000000000 +0200
16033 +++ linux.dev/arch/mips/kernel/proc.c 2006-10-02 21:19:59.000000000 +0200
16034 @@ -78,9 +78,10 @@
16035 [CPU_AU1550] "Au1550",
16036 [CPU_24K] "MIPS 24K",
16037 [CPU_AU1200] "Au1200",
16038 + [CPU_BCM4710] "BCM4710",
16039 + [CPU_BCM3302] "BCM3302",
16040 };
16041
16042 -
16043 static int show_cpuinfo(struct seq_file *m, void *v)
16044 {
16045 unsigned int version = current_cpu_data.processor_id;
16046 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
16047 --- linux.old/arch/mips/kernel/setup.c 2006-10-02 21:23:10.000000000 +0200
16048 +++ linux.dev/arch/mips/kernel/setup.c 2006-10-02 21:19:59.000000000 +0200
16049 @@ -493,6 +493,7 @@
16050 void swarm_setup(void);
16051 void hp_setup(void);
16052 void au1x00_setup(void);
16053 + void brcm_setup(void);
16054 void frame_info_init(void);
16055
16056 frame_info_init();
16057 @@ -691,6 +692,11 @@
16058 pmc_yosemite_setup();
16059 break;
16060 #endif
16061 +#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4310)
16062 + case MACH_GROUP_BRCM:
16063 + brcm_setup();
16064 + break;
16065 +#endif
16066 default:
16067 panic("Unsupported architecture");
16068 }
16069 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
16070 --- linux.old/arch/mips/kernel/traps.c 2006-10-02 21:23:10.000000000 +0200
16071 +++ linux.dev/arch/mips/kernel/traps.c 2006-10-02 21:19:59.000000000 +0200
16072 @@ -920,6 +920,7 @@
16073 void __init trap_init(void)
16074 {
16075 extern char except_vec1_generic;
16076 + extern char except_vec2_generic;
16077 extern char except_vec3_generic, except_vec3_r4000;
16078 extern char except_vec_ejtag_debug;
16079 extern char except_vec4;
16080 @@ -927,6 +928,7 @@
16081
16082 /* Copy the generic exception handler code to it's final destination. */
16083 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
16084 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
16085
16086 /*
16087 * Setup default vectors
16088 @@ -985,6 +987,12 @@
16089 set_except_vector(13, handle_tr);
16090 set_except_vector(22, handle_mdmx);
16091
16092 + if (current_cpu_data.cputype == CPU_SB1) {
16093 + /* Enable timer interrupt and scd mapped interrupt */
16094 + clear_c0_status(0xf000);
16095 + set_c0_status(0xc00);
16096 + }
16097 +
16098 if (cpu_has_fpu && !cpu_has_nofpuex)
16099 set_except_vector(15, handle_fpe);
16100
16101 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
16102 --- linux.old/arch/mips/Makefile 2006-10-02 21:23:10.000000000 +0200
16103 +++ linux.dev/arch/mips/Makefile 2006-10-02 21:19:59.000000000 +0200
16104 @@ -726,6 +726,19 @@
16105 endif
16106
16107 #
16108 +# Broadcom BCM947XX variants
16109 +#
16110 +ifdef CONFIG_BCM947XX
16111 +LIBS += arch/mips/bcm947xx/generic/brcm.o arch/mips/bcm947xx/bcm947xx.o
16112 +SUBDIRS += arch/mips/bcm947xx/generic arch/mips/bcm947xx
16113 +LOADADDR := 0x80001000
16114 +
16115 +zImage: vmlinux
16116 + $(MAKE) -C arch/$(ARCH)/bcm947xx/compressed
16117 +export LOADADDR
16118 +endif
16119 +
16120 +#
16121 # Choosing incompatible machines durings configuration will result in
16122 # error messages during linking. Select a default linkscript if
16123 # none has been choosen above.
16124 @@ -778,6 +791,7 @@
16125 $(MAKE) -C arch/$(ARCH)/tools clean
16126 $(MAKE) -C arch/mips/baget clean
16127 $(MAKE) -C arch/mips/lasat clean
16128 + $(MAKE) -C arch/mips/bcm947xx/compressed clean
16129
16130 archmrproper:
16131 @$(MAKEBOOT) mrproper
16132 diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
16133 --- linux.old/arch/mips/mm/c-r4k.c 2006-10-02 21:23:10.000000000 +0200
16134 +++ linux.dev/arch/mips/mm/c-r4k.c 2006-10-02 21:19:59.000000000 +0200
16135 @@ -1166,3 +1166,47 @@
16136 build_clear_page();
16137 build_copy_page();
16138 }
16139 +
16140 +#ifdef CONFIG_BCM4704
16141 +static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
16142 +{
16143 + unsigned long ic_lsize = current_cpu_data.icache.linesz;
16144 + int i;
16145 + for (i = 0; i < nbytes; i += ic_lsize)
16146 + fill_icache_line((addr + i));
16147 +}
16148 +
16149 +/*
16150 + * This must be run from the cache on 4704A0
16151 + * so there are no mips core BIU ops in progress
16152 + * when the PFC is enabled.
16153 + */
16154 +#define PFC_CR0 0xff400000 /* control reg 0 */
16155 +#define PFC_CR1 0xff400004 /* control reg 1 */
16156 +static void __init enable_pfc(u32 mode)
16157 +{
16158 + /* write range */
16159 + *(volatile u32 *)PFC_CR1 = 0xffff0000;
16160 +
16161 + /* enable */
16162 + *(volatile u32 *)PFC_CR0 = mode;
16163 +}
16164 +#endif
16165 +
16166 +
16167 +void check_enable_mips_pfc(int val)
16168 +{
16169 +
16170 +#ifdef CONFIG_BCM4704
16171 + struct cpuinfo_mips *c = &current_cpu_data;
16172 +
16173 + /* enable prefetch cache */
16174 + if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
16175 + && (read_c0_diag() & (1 << 29))) {
16176 + mips32_icache_fill((unsigned long) &enable_pfc, 64);
16177 + enable_pfc(val);
16178 + }
16179 +#endif
16180 +}
16181 +
16182 +
16183 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
16184 --- linux.old/arch/mips/pci/Makefile 2006-10-02 21:23:10.000000000 +0200
16185 +++ linux.dev/arch/mips/pci/Makefile 2006-10-02 21:19:59.000000000 +0200
16186 @@ -13,7 +13,9 @@
16187 obj-$(CONFIG_MIPS_MSC) += ops-msc.o
16188 obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
16189 obj-$(CONFIG_SNI_RM200_PCI) += ops-sni.o
16190 +ifndef CONFIG_BCM947XX
16191 obj-y += pci.o
16192 +endif
16193 obj-$(CONFIG_PCI_AUTO) += pci_auto.o
16194
16195 include $(TOPDIR)/Rules.make
16196 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
16197 --- linux.old/drivers/char/serial.c 2006-10-02 21:23:10.000000000 +0200
16198 +++ linux.dev/drivers/char/serial.c 2006-10-02 21:19:59.000000000 +0200
16199 @@ -444,6 +444,10 @@
16200 return inb(info->port+1);
16201 #endif
16202 case SERIAL_IO_MEM:
16203 +#ifdef CONFIG_BCM4310
16204 + readb((unsigned long) info->iomem_base +
16205 + (UART_SCR<<info->iomem_reg_shift));
16206 +#endif
16207 return readb((unsigned long) info->iomem_base +
16208 (offset<<info->iomem_reg_shift));
16209 default:
16210 @@ -464,6 +468,9 @@
16211 case SERIAL_IO_MEM:
16212 writeb(value, (unsigned long) info->iomem_base +
16213 (offset<<info->iomem_reg_shift));
16214 +#ifdef CONFIG_BCM4704
16215 + *((volatile unsigned int *) KSEG1ADDR(0x18000000));
16216 +#endif
16217 break;
16218 default:
16219 outb(value, info->port+offset);
16220 @@ -1728,7 +1735,7 @@
16221 /* Special case since 134 is really 134.5 */
16222 quot = (2*baud_base / 269);
16223 else if (baud)
16224 - quot = baud_base / baud;
16225 + quot = (baud_base + (baud / 2)) / baud;
16226 }
16227 /* If the quotient is zero refuse the change */
16228 if (!quot && old_termios) {
16229 @@ -1745,12 +1752,12 @@
16230 /* Special case since 134 is really 134.5 */
16231 quot = (2*baud_base / 269);
16232 else if (baud)
16233 - quot = baud_base / baud;
16234 + quot = (baud_base + (baud / 2)) / baud;
16235 }
16236 }
16237 /* As a last resort, if the quotient is zero, default to 9600 bps */
16238 if (!quot)
16239 - quot = baud_base / 9600;
16240 + quot = (baud_base + 4800) / 9600;
16241 /*
16242 * Work around a bug in the Oxford Semiconductor 952 rev B
16243 * chip which causes it to seriously miscalculate baud rates
16244 @@ -5994,6 +6001,13 @@
16245 * Divisor, bytesize and parity
16246 */
16247 state = rs_table + co->index;
16248 + /*
16249 + * Safe guard: state structure must have been initialized
16250 + */
16251 + if (state->iomem_base == NULL) {
16252 + printk("!unable to setup serial console!\n");
16253 + return -1;
16254 + }
16255 if (doflow)
16256 state->flags |= ASYNC_CONS_FLOW;
16257 info = &async_sercons;
16258 @@ -6007,7 +6021,7 @@
16259 info->io_type = state->io_type;
16260 info->iomem_base = state->iomem_base;
16261 info->iomem_reg_shift = state->iomem_reg_shift;
16262 - quot = state->baud_base / baud;
16263 + quot = (state->baud_base + (baud / 2)) / baud;
16264 cval = cflag & (CSIZE | CSTOPB);
16265 #if defined(__powerpc__) || defined(__alpha__)
16266 cval >>= 8;
16267 diff -urN linux.old/drivers/net/Makefile linux.dev/drivers/net/Makefile
16268 --- linux.old/drivers/net/Makefile 2006-10-02 21:23:10.000000000 +0200
16269 +++ linux.dev/drivers/net/Makefile 2006-10-02 21:19:59.000000000 +0200
16270 @@ -3,6 +3,8 @@
16271 # Makefile for the Linux network (ethercard) device drivers.
16272 #
16273
16274 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
16275 +
16276 obj-y :=
16277 obj-m :=
16278 obj-n :=
16279 diff -urN linux.old/drivers/parport/Config.in linux.dev/drivers/parport/Config.in
16280 --- linux.old/drivers/parport/Config.in 2006-10-02 21:23:10.000000000 +0200
16281 +++ linux.dev/drivers/parport/Config.in 2006-10-02 21:19:59.000000000 +0200
16282 @@ -11,6 +11,7 @@
16283 tristate 'Parallel port support' CONFIG_PARPORT
16284 if [ "$CONFIG_PARPORT" != "n" ]; then
16285 dep_tristate ' PC-style hardware' CONFIG_PARPORT_PC $CONFIG_PARPORT
16286 + dep_tristate ' Asus WL500g parallel port' CONFIG_PARPORT_SPLINK $CONFIG_PARPORT
16287 if [ "$CONFIG_PARPORT_PC" != "n" -a "$CONFIG_SERIAL" != "n" ]; then
16288 if [ "$CONFIG_SERIAL" = "m" ]; then
16289 define_tristate CONFIG_PARPORT_PC_CML1 m
16290 diff -urN linux.old/drivers/parport/Makefile linux.dev/drivers/parport/Makefile
16291 --- linux.old/drivers/parport/Makefile 2006-10-02 21:23:10.000000000 +0200
16292 +++ linux.dev/drivers/parport/Makefile 2006-10-02 21:19:59.000000000 +0200
16293 @@ -22,6 +22,7 @@
16294
16295 obj-$(CONFIG_PARPORT) += parport.o
16296 obj-$(CONFIG_PARPORT_PC) += parport_pc.o
16297 +obj-$(CONFIG_PARPORT_SPLINK) += parport_splink.o
16298 obj-$(CONFIG_PARPORT_PC_PCMCIA) += parport_cs.o
16299 obj-$(CONFIG_PARPORT_AMIGA) += parport_amiga.o
16300 obj-$(CONFIG_PARPORT_MFC3) += parport_mfc3.o
16301 diff -urN linux.old/drivers/parport/parport_splink.c linux.dev/drivers/parport/parport_splink.c
16302 --- linux.old/drivers/parport/parport_splink.c 1970-01-01 01:00:00.000000000 +0100
16303 +++ linux.dev/drivers/parport/parport_splink.c 2006-10-02 21:19:59.000000000 +0200
16304 @@ -0,0 +1,345 @@
16305 +/* Low-level parallel port routines for the ASUS WL-500g built-in port
16306 + *
16307 + * Author: Nuno Grilo <nuno.grilo@netcabo.pt>
16308 + * Based on parport_pc source
16309 + */
16310 +
16311 +#include <linux/config.h>
16312 +#include <linux/module.h>
16313 +#include <linux/init.h>
16314 +#include <linux/ioport.h>
16315 +#include <linux/kernel.h>
16316 +#include <linux/slab.h>
16317 +#include <linux/parport.h>
16318 +#include <linux/parport_pc.h>
16319 +
16320 +#define SPLINK_ADDRESS 0xBF800010
16321 +
16322 +#undef DEBUG
16323 +
16324 +#ifdef DEBUG
16325 +#define DPRINTK printk
16326 +#else
16327 +#define DPRINTK(stuff...)
16328 +#endif
16329 +
16330 +
16331 +/* __parport_splink_frob_control differs from parport_splink_frob_control in that
16332 + * it doesn't do any extra masking. */
16333 +static __inline__ unsigned char __parport_splink_frob_control (struct parport *p,
16334 + unsigned char mask,
16335 + unsigned char val)
16336 +{
16337 + struct parport_pc_private *priv = p->physport->private_data;
16338 + unsigned char *io = (unsigned char *) p->base;
16339 + unsigned char ctr = priv->ctr;
16340 +#ifdef DEBUG_PARPORT
16341 + printk (KERN_DEBUG
16342 + "__parport_splink_frob_control(%02x,%02x): %02x -> %02x\n",
16343 + mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable);
16344 +#endif
16345 + ctr = (ctr & ~mask) ^ val;
16346 + ctr &= priv->ctr_writable; /* only write writable bits. */
16347 + *(io+2) = ctr;
16348 + priv->ctr = ctr; /* Update soft copy */
16349 + return ctr;
16350 +}
16351 +
16352 +
16353 +
16354 +static void parport_splink_data_forward (struct parport *p)
16355 +{
16356 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
16357 + __parport_splink_frob_control (p, 0x20, 0);
16358 +}
16359 +
16360 +static void parport_splink_data_reverse (struct parport *p)
16361 +{
16362 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
16363 + __parport_splink_frob_control (p, 0x20, 0x20);
16364 +}
16365 +
16366 +/*
16367 +static void parport_splink_interrupt(int irq, void *dev_id, struct pt_regs *regs)
16368 +{
16369 + DPRINTK(KERN_DEBUG "parport_splink: IRQ handler called\n");
16370 + parport_generic_irq(irq, (struct parport *) dev_id, regs);
16371 +}
16372 +*/
16373 +
16374 +static void parport_splink_enable_irq(struct parport *p)
16375 +{
16376 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_enable_irq called\n");
16377 + __parport_splink_frob_control (p, 0x10, 0x10);
16378 +}
16379 +
16380 +static void parport_splink_disable_irq(struct parport *p)
16381 +{
16382 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_disable_irq called\n");
16383 + __parport_splink_frob_control (p, 0x10, 0);
16384 +}
16385 +
16386 +static void parport_splink_init_state(struct pardevice *dev, struct parport_state *s)
16387 +{
16388 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_init_state called\n");
16389 + s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0);
16390 + if (dev->irq_func &&
16391 + dev->port->irq != PARPORT_IRQ_NONE)
16392 + /* Set ackIntEn */
16393 + s->u.pc.ctr |= 0x10;
16394 +}
16395 +
16396 +static void parport_splink_save_state(struct parport *p, struct parport_state *s)
16397 +{
16398 + const struct parport_pc_private *priv = p->physport->private_data;
16399 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_save_state called\n");
16400 + s->u.pc.ctr = priv->ctr;
16401 +}
16402 +
16403 +static void parport_splink_restore_state(struct parport *p, struct parport_state *s)
16404 +{
16405 + struct parport_pc_private *priv = p->physport->private_data;
16406 + unsigned char *io = (unsigned char *) p->base;
16407 + unsigned char ctr = s->u.pc.ctr;
16408 +
16409 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_restore_state called\n");
16410 + *(io+2) = ctr;
16411 + priv->ctr = ctr;
16412 +}
16413 +
16414 +static void parport_splink_setup_interrupt(void) {
16415 + return;
16416 +}
16417 +
16418 +static void parport_splink_write_data(struct parport *p, unsigned char d) {
16419 + DPRINTK(KERN_DEBUG "parport_splink: write data called\n");
16420 + unsigned char *io = (unsigned char *) p->base;
16421 + *io = d;
16422 +}
16423 +
16424 +static unsigned char parport_splink_read_data(struct parport *p) {
16425 + DPRINTK(KERN_DEBUG "parport_splink: read data called\n");
16426 + unsigned char *io = (unsigned char *) p->base;
16427 + return *io;
16428 +}
16429 +
16430 +static void parport_splink_write_control(struct parport *p, unsigned char d)
16431 +{
16432 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16433 + PARPORT_CONTROL_AUTOFD |
16434 + PARPORT_CONTROL_INIT |
16435 + PARPORT_CONTROL_SELECT);
16436 +
16437 + DPRINTK(KERN_DEBUG "parport_splink: write control called\n");
16438 + /* Take this out when drivers have adapted to the newer interface. */
16439 + if (d & 0x20) {
16440 + printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n",
16441 + p->name, p->cad->name);
16442 + parport_splink_data_reverse (p);
16443 + }
16444 +
16445 + __parport_splink_frob_control (p, wm, d & wm);
16446 +}
16447 +
16448 +static unsigned char parport_splink_read_control(struct parport *p)
16449 +{
16450 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16451 + PARPORT_CONTROL_AUTOFD |
16452 + PARPORT_CONTROL_INIT |
16453 + PARPORT_CONTROL_SELECT);
16454 + DPRINTK(KERN_DEBUG "parport_splink: read control called\n");
16455 + const struct parport_pc_private *priv = p->physport->private_data;
16456 + return priv->ctr & wm; /* Use soft copy */
16457 +}
16458 +
16459 +static unsigned char parport_splink_frob_control (struct parport *p, unsigned char mask,
16460 + unsigned char val)
16461 +{
16462 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16463 + PARPORT_CONTROL_AUTOFD |
16464 + PARPORT_CONTROL_INIT |
16465 + PARPORT_CONTROL_SELECT);
16466 +
16467 + DPRINTK(KERN_DEBUG "parport_splink: frob control called\n");
16468 + /* Take this out when drivers have adapted to the newer interface. */
16469 + if (mask & 0x20) {
16470 + printk (KERN_DEBUG "%s (%s): use data_%s for this!\n",
16471 + p->name, p->cad->name,
16472 + (val & 0x20) ? "reverse" : "forward");
16473 + if (val & 0x20)
16474 + parport_splink_data_reverse (p);
16475 + else
16476 + parport_splink_data_forward (p);
16477 + }
16478 +
16479 + /* Restrict mask and val to control lines. */
16480 + mask &= wm;
16481 + val &= wm;
16482 +
16483 + return __parport_splink_frob_control (p, mask, val);
16484 +}
16485 +
16486 +static unsigned char parport_splink_read_status(struct parport *p)
16487 +{
16488 + DPRINTK(KERN_DEBUG "parport_splink: read status called\n");
16489 + unsigned char *io = (unsigned char *) p->base;
16490 + return *(io+1);
16491 +}
16492 +
16493 +static void parport_splink_inc_use_count(void)
16494 +{
16495 +#ifdef MODULE
16496 + MOD_INC_USE_COUNT;
16497 +#endif
16498 +}
16499 +
16500 +static void parport_splink_dec_use_count(void)
16501 +{
16502 +#ifdef MODULE
16503 + MOD_DEC_USE_COUNT;
16504 +#endif
16505 +}
16506 +
16507 +static struct parport_operations parport_splink_ops =
16508 +{
16509 + parport_splink_write_data,
16510 + parport_splink_read_data,
16511 +
16512 + parport_splink_write_control,
16513 + parport_splink_read_control,
16514 + parport_splink_frob_control,
16515 +
16516 + parport_splink_read_status,
16517 +
16518 + parport_splink_enable_irq,
16519 + parport_splink_disable_irq,
16520 +
16521 + parport_splink_data_forward,
16522 + parport_splink_data_reverse,
16523 +
16524 + parport_splink_init_state,
16525 + parport_splink_save_state,
16526 + parport_splink_restore_state,
16527 +
16528 + parport_splink_inc_use_count,
16529 + parport_splink_dec_use_count,
16530 +
16531 + parport_ieee1284_epp_write_data,
16532 + parport_ieee1284_epp_read_data,
16533 + parport_ieee1284_epp_write_addr,
16534 + parport_ieee1284_epp_read_addr,
16535 +
16536 + parport_ieee1284_ecp_write_data,
16537 + parport_ieee1284_ecp_read_data,
16538 + parport_ieee1284_ecp_write_addr,
16539 +
16540 + parport_ieee1284_write_compat,
16541 + parport_ieee1284_read_nibble,
16542 + parport_ieee1284_read_byte,
16543 +};
16544 +
16545 +/* --- Initialisation code -------------------------------- */
16546 +
16547 +static struct parport *parport_splink_probe_port (unsigned long int base)
16548 +{
16549 + struct parport_pc_private *priv;
16550 + struct parport_operations *ops;
16551 + struct parport *p;
16552 +
16553 + if (check_mem_region(base, 3)) {
16554 + printk (KERN_DEBUG "parport (0x%lx): iomem region not available\n", base);
16555 + return NULL;
16556 + }
16557 + priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
16558 + if (!priv) {
16559 + printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base);
16560 + return NULL;
16561 + }
16562 + ops = kmalloc (sizeof (struct parport_operations), GFP_KERNEL);
16563 + if (!ops) {
16564 + printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n",
16565 + base);
16566 + kfree (priv);
16567 + return NULL;
16568 + }
16569 + memcpy (ops, &parport_splink_ops, sizeof (struct parport_operations));
16570 + priv->ctr = 0xc;
16571 + priv->ctr_writable = 0xff;
16572 +
16573 + if (!(p = parport_register_port(base, PARPORT_IRQ_NONE,
16574 + PARPORT_DMA_NONE, ops))) {
16575 + printk (KERN_DEBUG "parport (0x%lx): registration failed!\n",
16576 + base);
16577 + kfree (priv);
16578 + kfree (ops);
16579 + return NULL;
16580 + }
16581 +
16582 + p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
16583 + p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
16584 + p->private_data = priv;
16585 +
16586 + parport_proc_register(p);
16587 + request_mem_region (p->base, 3, p->name);
16588 +
16589 + /* Done probing. Now put the port into a sensible start-up state. */
16590 + parport_splink_write_data(p, 0);
16591 + parport_splink_data_forward (p);
16592 +
16593 + /* Now that we've told the sharing engine about the port, and
16594 + found out its characteristics, let the high-level drivers
16595 + know about it. */
16596 + parport_announce_port (p);
16597 +
16598 + DPRINTK(KERN_DEBUG "parport (0x%lx): init ok!\n",
16599 + base);
16600 + return p;
16601 +}
16602 +
16603 +static void parport_splink_unregister_port(struct parport *p) {
16604 + struct parport_pc_private *priv = p->private_data;
16605 + struct parport_operations *ops = p->ops;
16606 +
16607 + if (p->irq != PARPORT_IRQ_NONE)
16608 + free_irq(p->irq, p);
16609 + release_mem_region(p->base, 3);
16610 + parport_proc_unregister(p);
16611 + kfree (priv);
16612 + parport_unregister_port(p);
16613 + kfree (ops);
16614 +}
16615 +
16616 +
16617 +int parport_splink_init(void)
16618 +{
16619 + int ret;
16620 +
16621 + DPRINTK(KERN_DEBUG "parport_splink init called\n");
16622 + parport_splink_setup_interrupt();
16623 + ret = !parport_splink_probe_port(SPLINK_ADDRESS);
16624 +
16625 + return ret;
16626 +}
16627 +
16628 +void parport_splink_cleanup(void) {
16629 + struct parport *p = parport_enumerate(), *tmp;
16630 + DPRINTK(KERN_DEBUG "parport_splink cleanup called\n");
16631 + if (p->size) {
16632 + if (p->modes & PARPORT_MODE_PCSPP) {
16633 + while(p) {
16634 + tmp = p->next;
16635 + parport_splink_unregister_port(p);
16636 + p = tmp;
16637 + }
16638 + }
16639 + }
16640 +}
16641 +
16642 +MODULE_AUTHOR("Nuno Grilo <nuno.grilo@netcabo.pt>");
16643 +MODULE_DESCRIPTION("Parport Driver for ASUS WL-500g router builtin Port");
16644 +MODULE_SUPPORTED_DEVICE("ASUS WL-500g builtin Parallel Port");
16645 +MODULE_LICENSE("GPL");
16646 +
16647 +module_init(parport_splink_init)
16648 +module_exit(parport_splink_cleanup)
16649 +
16650 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
16651 --- linux.old/include/asm-mips/bootinfo.h 2006-10-02 21:23:10.000000000 +0200
16652 +++ linux.dev/include/asm-mips/bootinfo.h 2006-10-02 21:19:59.000000000 +0200
16653 @@ -37,6 +37,7 @@
16654 #define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */
16655 #define MACH_GROUP_LASAT 21
16656 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
16657 +#define MACH_GROUP_BRCM 23 /* Broadcom */
16658
16659 /*
16660 * Valid machtype values for group unknown (low order halfword of mips_machtype)
16661 @@ -197,6 +198,15 @@
16662 #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
16663
16664 /*
16665 + * Valid machtypes for group Broadcom
16666 + */
16667 +#define MACH_BCM93725 0
16668 +#define MACH_BCM93725_VJ 1
16669 +#define MACH_BCM93730 2
16670 +#define MACH_BCM947XX 3
16671 +#define MACH_BCM933XX 4
16672 +
16673 +/*
16674 * Valid machtype for group TITAN
16675 */
16676 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
16677 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
16678 --- linux.old/include/asm-mips/cpu.h 2006-10-02 21:23:10.000000000 +0200
16679 +++ linux.dev/include/asm-mips/cpu.h 2006-10-02 21:19:59.000000000 +0200
16680 @@ -22,6 +22,11 @@
16681 spec.
16682 */
16683
16684 +#define PRID_COPT_MASK 0xff000000
16685 +#define PRID_COMP_MASK 0x00ff0000
16686 +#define PRID_IMP_MASK 0x0000ff00
16687 +#define PRID_REV_MASK 0x000000ff
16688 +
16689 #define PRID_COMP_LEGACY 0x000000
16690 #define PRID_COMP_MIPS 0x010000
16691 #define PRID_COMP_BROADCOM 0x020000
16692 @@ -58,6 +63,7 @@
16693 #define PRID_IMP_RM7000 0x2700
16694 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
16695 #define PRID_IMP_RM9000 0x3400
16696 +#define PRID_IMP_BCM4710 0x4000
16697 #define PRID_IMP_R5432 0x5400
16698 #define PRID_IMP_R5500 0x5500
16699 #define PRID_IMP_4KC 0x8000
16700 @@ -66,10 +72,16 @@
16701 #define PRID_IMP_4KEC 0x8400
16702 #define PRID_IMP_4KSC 0x8600
16703 #define PRID_IMP_25KF 0x8800
16704 +#define PRID_IMP_BCM3302 0x9000
16705 +#define PRID_IMP_BCM3303 0x9100
16706 #define PRID_IMP_24K 0x9300
16707
16708 #define PRID_IMP_UNKNOWN 0xff00
16709
16710 +#define BCM330X(id) \
16711 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
16712 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
16713 +
16714 /*
16715 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
16716 */
16717 @@ -174,7 +186,9 @@
16718 #define CPU_AU1550 57
16719 #define CPU_24K 58
16720 #define CPU_AU1200 59
16721 -#define CPU_LAST 59
16722 +#define CPU_BCM4710 60
16723 +#define CPU_BCM3302 61
16724 +#define CPU_LAST 61
16725
16726 /*
16727 * ISA Level encodings
16728 diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
16729 --- linux.old/include/asm-mips/r4kcache.h 2006-10-02 21:23:10.000000000 +0200
16730 +++ linux.dev/include/asm-mips/r4kcache.h 2006-10-02 21:19:59.000000000 +0200
16731 @@ -658,4 +658,17 @@
16732 cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
16733 }
16734
16735 +extern inline void fill_icache_line(unsigned long addr)
16736 +{
16737 + __asm__ __volatile__(
16738 + ".set noreorder\n\t"
16739 + ".set mips3\n\t"
16740 + "cache %1, (%0)\n\t"
16741 + ".set mips0\n\t"
16742 + ".set reorder"
16743 + :
16744 + : "r" (addr),
16745 + "i" (Fill));
16746 +}
16747 +
16748 #endif /* __ASM_R4KCACHE_H */
16749 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
16750 --- linux.old/include/asm-mips/serial.h 2006-10-02 21:23:10.000000000 +0200
16751 +++ linux.dev/include/asm-mips/serial.h 2006-10-02 21:19:59.000000000 +0200
16752 @@ -223,6 +223,13 @@
16753 #define TXX927_SERIAL_PORT_DEFNS
16754 #endif
16755
16756 +#ifdef CONFIG_BCM947XX
16757 +/* reserve 4 ports to be configured at runtime */
16758 +#define BCM947XX_SERIAL_PORT_DEFNS { 0, }, { 0, }, { 0, }, { 0, },
16759 +#else
16760 +#define BCM947XX_SERIAL_PORT_DEFNS
16761 +#endif
16762 +
16763 #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
16764 #define STD_SERIAL_PORT_DEFNS \
16765 /* UART CLK PORT IRQ FLAGS */ \
16766 @@ -470,6 +477,7 @@
16767 #define SERIAL_PORT_DFNS \
16768 ATLAS_SERIAL_PORT_DEFNS \
16769 AU1000_SERIAL_PORT_DEFNS \
16770 + BCM947XX_SERIAL_PORT_DEFNS \
16771 COBALT_SERIAL_PORT_DEFNS \
16772 DDB5477_SERIAL_PORT_DEFNS \
16773 EV96100_SERIAL_PORT_DEFNS \
16774 diff -urN linux.old/init/do_mounts.c linux.dev/init/do_mounts.c
16775 --- linux.old/init/do_mounts.c 2006-10-02 21:23:10.000000000 +0200
16776 +++ linux.dev/init/do_mounts.c 2006-10-02 21:19:59.000000000 +0200
16777 @@ -254,7 +254,13 @@
16778 { "ftlb", 0x2c08 },
16779 { "ftlc", 0x2c10 },
16780 { "ftld", 0x2c18 },
16781 +#if defined(CONFIG_MTD_BLOCK) || defined(CONFIG_MTD_BLOCK_RO)
16782 { "mtdblock", 0x1f00 },
16783 + { "mtdblock0",0x1f00 },
16784 + { "mtdblock1",0x1f01 },
16785 + { "mtdblock2",0x1f02 },
16786 + { "mtdblock3",0x1f03 },
16787 +#endif
16788 { "nb", 0x2b00 },
16789 { NULL, 0 }
16790 };
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