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linux/mpc83xx: add preliminary 2.6.36 kernel support
[openwrt.git] / target / linux / atheros / patches-2.6.35 / 110-ar2313_ethernet.patch
1 --- a/drivers/net/Kconfig
2 +++ b/drivers/net/Kconfig
3 @@ -371,6 +371,12 @@ config AX88796_93CX6
4 help
5 Select this if your platform comes with an external 93CX6 eeprom.
6
7 +config AR231X_ETHERNET
8 + tristate "AR231x Ethernet support"
9 + depends on ATHEROS_AR231X
10 + help
11 + Support for the AR231x/531x ethernet controller
12 +
13 config MACE
14 tristate "MACE (Power Mac ethernet) support"
15 depends on PPC_PMAC && PPC32
16 --- a/drivers/net/Makefile
17 +++ b/drivers/net/Makefile
18 @@ -221,6 +221,7 @@ obj-$(CONFIG_EQUALIZER) += eql.o
19 obj-$(CONFIG_KORINA) += korina.o
20 obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o
21 obj-$(CONFIG_MIPS_AU1X00_ENET) += au1000_eth.o
22 +obj-$(CONFIG_AR231X_ETHERNET) += ar231x.o
23 obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o
24 obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o
25 obj-$(CONFIG_DECLANCE) += declance.o
26 --- /dev/null
27 +++ b/drivers/net/ar231x.c
28 @@ -0,0 +1,1278 @@
29 +/*
30 + * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
31 + *
32 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
33 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
34 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
35 + *
36 + * Thanks to Atheros for providing hardware and documentation
37 + * enabling me to write this driver.
38 + *
39 + * This program is free software; you can redistribute it and/or modify
40 + * it under the terms of the GNU General Public License as published by
41 + * the Free Software Foundation; either version 2 of the License, or
42 + * (at your option) any later version.
43 + *
44 + * Additional credits:
45 + * This code is taken from John Taylor's Sibyte driver and then
46 + * modified for the AR2313.
47 + */
48 +
49 +#include <linux/module.h>
50 +#include <linux/version.h>
51 +#include <linux/types.h>
52 +#include <linux/errno.h>
53 +#include <linux/ioport.h>
54 +#include <linux/pci.h>
55 +#include <linux/netdevice.h>
56 +#include <linux/etherdevice.h>
57 +#include <linux/skbuff.h>
58 +#include <linux/init.h>
59 +#include <linux/delay.h>
60 +#include <linux/mm.h>
61 +#include <linux/highmem.h>
62 +#include <linux/sockios.h>
63 +#include <linux/pkt_sched.h>
64 +#include <linux/mii.h>
65 +#include <linux/phy.h>
66 +#include <linux/ethtool.h>
67 +#include <linux/ctype.h>
68 +#include <linux/platform_device.h>
69 +
70 +#include <net/sock.h>
71 +#include <net/ip.h>
72 +
73 +#include <asm/system.h>
74 +#include <asm/io.h>
75 +#include <asm/irq.h>
76 +#include <asm/byteorder.h>
77 +#include <asm/uaccess.h>
78 +#include <asm/bootinfo.h>
79 +
80 +#define AR2313_MTU 1692
81 +#define AR2313_PRIOS 1
82 +#define AR2313_QUEUES (2*AR2313_PRIOS)
83 +#define AR2313_DESCR_ENTRIES 64
84 +
85 +
86 +#ifndef min
87 +#define min(a,b) (((a)<(b))?(a):(b))
88 +#endif
89 +
90 +#ifndef SMP_CACHE_BYTES
91 +#define SMP_CACHE_BYTES L1_CACHE_BYTES
92 +#endif
93 +
94 +#define AR2313_MBOX_SET_BIT 0x8
95 +
96 +#include "ar231x.h"
97 +
98 +/*
99 + * New interrupt handler strategy:
100 + *
101 + * An old interrupt handler worked using the traditional method of
102 + * replacing an skbuff with a new one when a packet arrives. However
103 + * the rx rings do not need to contain a static number of buffer
104 + * descriptors, thus it makes sense to move the memory allocation out
105 + * of the main interrupt handler and do it in a bottom half handler
106 + * and only allocate new buffers when the number of buffers in the
107 + * ring is below a certain threshold. In order to avoid starving the
108 + * NIC under heavy load it is however necessary to force allocation
109 + * when hitting a minimum threshold. The strategy for alloction is as
110 + * follows:
111 + *
112 + * RX_LOW_BUF_THRES - allocate buffers in the bottom half
113 + * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
114 + * the buffers in the interrupt handler
115 + * RX_RING_THRES - maximum number of buffers in the rx ring
116 + *
117 + * One advantagous side effect of this allocation approach is that the
118 + * entire rx processing can be done without holding any spin lock
119 + * since the rx rings and registers are totally independent of the tx
120 + * ring and its registers. This of course includes the kmalloc's of
121 + * new skb's. Thus start_xmit can run in parallel with rx processing
122 + * and the memory allocation on SMP systems.
123 + *
124 + * Note that running the skb reallocation in a bottom half opens up
125 + * another can of races which needs to be handled properly. In
126 + * particular it can happen that the interrupt handler tries to run
127 + * the reallocation while the bottom half is either running on another
128 + * CPU or was interrupted on the same CPU. To get around this the
129 + * driver uses bitops to prevent the reallocation routines from being
130 + * reentered.
131 + *
132 + * TX handling can also be done without holding any spin lock, wheee
133 + * this is fun! since tx_csm is only written to by the interrupt
134 + * handler.
135 + */
136 +
137 +/*
138 + * Threshold values for RX buffer allocation - the low water marks for
139 + * when to start refilling the rings are set to 75% of the ring
140 + * sizes. It seems to make sense to refill the rings entirely from the
141 + * intrrupt handler once it gets below the panic threshold, that way
142 + * we don't risk that the refilling is moved to another CPU when the
143 + * one running the interrupt handler just got the slab code hot in its
144 + * cache.
145 + */
146 +#define RX_RING_SIZE AR2313_DESCR_ENTRIES
147 +#define RX_PANIC_THRES (RX_RING_SIZE/4)
148 +#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
149 +#define CRC_LEN 4
150 +#define RX_OFFSET 2
151 +
152 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
153 +#define VLAN_HDR 4
154 +#else
155 +#define VLAN_HDR 0
156 +#endif
157 +
158 +#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + RX_OFFSET)
159 +
160 +#ifdef MODULE
161 +MODULE_LICENSE("GPL");
162 +MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@openwrt.org>");
163 +MODULE_DESCRIPTION("AR231x Ethernet driver");
164 +#endif
165 +
166 +#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
167 +
168 +// prototypes
169 +static void ar231x_halt(struct net_device *dev);
170 +static void rx_tasklet_func(unsigned long data);
171 +static void rx_tasklet_cleanup(struct net_device *dev);
172 +static void ar231x_multicast_list(struct net_device *dev);
173 +static void ar231x_tx_timeout(struct net_device *dev);
174 +
175 +static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
176 +static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value);
177 +static int ar231x_mdiobus_reset(struct mii_bus *bus);
178 +static int ar231x_mdiobus_probe (struct net_device *dev);
179 +static void ar231x_adjust_link(struct net_device *dev);
180 +
181 +#ifndef ERR
182 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
183 +#endif
184 +
185 +static const struct net_device_ops ar231x_ops = {
186 + .ndo_open = ar231x_open,
187 + .ndo_stop = ar231x_close,
188 + .ndo_start_xmit = ar231x_start_xmit,
189 + .ndo_set_multicast_list = ar231x_multicast_list,
190 + .ndo_do_ioctl = ar231x_ioctl,
191 + .ndo_change_mtu = eth_change_mtu,
192 + .ndo_validate_addr = eth_validate_addr,
193 + .ndo_set_mac_address = eth_mac_addr,
194 + .ndo_tx_timeout = ar231x_tx_timeout,
195 +};
196 +
197 +int __init ar231x_probe(struct platform_device *pdev)
198 +{
199 + struct net_device *dev;
200 + struct ar231x_private *sp;
201 + struct resource *res;
202 + unsigned long ar_eth_base;
203 + char buf[64];
204 +
205 + dev = alloc_etherdev(sizeof(struct ar231x_private));
206 +
207 + if (dev == NULL) {
208 + printk(KERN_ERR
209 + "ar231x: Unable to allocate net_device structure!\n");
210 + return -ENOMEM;
211 + }
212 +
213 + platform_set_drvdata(pdev, dev);
214 +
215 + sp = netdev_priv(dev);
216 + sp->dev = dev;
217 + sp->cfg = pdev->dev.platform_data;
218 +
219 + sprintf(buf, "eth%d_membase", pdev->id);
220 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
221 + if (!res)
222 + return -ENODEV;
223 +
224 + sp->link = 0;
225 + ar_eth_base = res->start;
226 +
227 + sprintf(buf, "eth%d_irq", pdev->id);
228 + dev->irq = platform_get_irq_byname(pdev, buf);
229 +
230 + spin_lock_init(&sp->lock);
231 +
232 + dev->features |= NETIF_F_HIGHDMA;
233 + dev->netdev_ops = &ar231x_ops;
234 +
235 + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev);
236 + tasklet_disable(&sp->rx_tasklet);
237 +
238 + sp->eth_regs =
239 + ioremap_nocache(virt_to_phys(ar_eth_base), sizeof(*sp->eth_regs));
240 + if (!sp->eth_regs) {
241 + printk("Can't remap eth registers\n");
242 + return (-ENXIO);
243 + }
244 +
245 + /*
246 + * When there's only one MAC, PHY regs are typically on ENET0,
247 + * even though the MAC might be on ENET1.
248 + * Needto remap PHY regs separately in this case
249 + */
250 + if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs))
251 + sp->phy_regs = sp->eth_regs;
252 + else {
253 + sp->phy_regs =
254 + ioremap_nocache(virt_to_phys(sp->cfg->phy_base),
255 + sizeof(*sp->phy_regs));
256 + if (!sp->phy_regs) {
257 + printk("Can't remap phy registers\n");
258 + return (-ENXIO);
259 + }
260 + }
261 +
262 + sp->dma_regs =
263 + ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000),
264 + sizeof(*sp->dma_regs));
265 + dev->base_addr = (unsigned int) sp->dma_regs;
266 + if (!sp->dma_regs) {
267 + printk("Can't remap DMA registers\n");
268 + return (-ENXIO);
269 + }
270 +
271 + sp->int_regs = ioremap_nocache(virt_to_phys(sp->cfg->reset_base), 4);
272 + if (!sp->int_regs) {
273 + printk("Can't remap INTERRUPT registers\n");
274 + return (-ENXIO);
275 + }
276 +
277 + strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
278 + sp->name[sizeof(sp->name) - 1] = '\0';
279 + memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
280 +
281 + if (ar231x_init(dev)) {
282 + /*
283 + * ar231x_init() calls ar231x_init_cleanup() on error.
284 + */
285 + kfree(dev);
286 + return -ENODEV;
287 + }
288 +
289 + if (register_netdev(dev)) {
290 + printk("%s: register_netdev failed\n", __func__);
291 + return -1;
292 + }
293 +
294 + printk("%s: %s: %02x:%02x:%02x:%02x:%02x:%02x, irq %d\n",
295 + dev->name, sp->name,
296 + dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
297 + dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], dev->irq);
298 +
299 + sp->mii_bus = mdiobus_alloc();
300 + if (sp->mii_bus == NULL)
301 + return -1;
302 +
303 + sp->mii_bus->priv = dev;
304 + sp->mii_bus->read = ar231x_mdiobus_read;
305 + sp->mii_bus->write = ar231x_mdiobus_write;
306 + sp->mii_bus->reset = ar231x_mdiobus_reset;
307 + sp->mii_bus->name = "ar231x_eth_mii";
308 + snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
309 + sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL);
310 + *sp->mii_bus->irq = PHY_POLL;
311 +
312 + mdiobus_register(sp->mii_bus);
313 +
314 + if (ar231x_mdiobus_probe(dev) != 0) {
315 + printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
316 + rx_tasklet_cleanup(dev);
317 + ar231x_init_cleanup(dev);
318 + unregister_netdev(dev);
319 + kfree(dev);
320 + return -ENODEV;
321 + }
322 +
323 + /* start link poll timer */
324 + ar231x_setup_timer(dev);
325 +
326 + return 0;
327 +}
328 +
329 +
330 +static void ar231x_multicast_list(struct net_device *dev)
331 +{
332 + struct ar231x_private *sp = netdev_priv(dev);
333 + unsigned int filter;
334 +
335 + filter = sp->eth_regs->mac_control;
336 +
337 + if (dev->flags & IFF_PROMISC)
338 + filter |= MAC_CONTROL_PR;
339 + else
340 + filter &= ~MAC_CONTROL_PR;
341 + if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0))
342 + filter |= MAC_CONTROL_PM;
343 + else
344 + filter &= ~MAC_CONTROL_PM;
345 +
346 + sp->eth_regs->mac_control = filter;
347 +}
348 +
349 +static void rx_tasklet_cleanup(struct net_device *dev)
350 +{
351 + struct ar231x_private *sp = netdev_priv(dev);
352 +
353 + /*
354 + * Tasklet may be scheduled. Need to get it removed from the list
355 + * since we're about to free the struct.
356 + */
357 +
358 + sp->unloading = 1;
359 + tasklet_enable(&sp->rx_tasklet);
360 + tasklet_kill(&sp->rx_tasklet);
361 +}
362 +
363 +static int __devexit ar231x_remove(struct platform_device *pdev)
364 +{
365 + struct net_device *dev = platform_get_drvdata(pdev);
366 + struct ar231x_private *sp = netdev_priv(dev);
367 + rx_tasklet_cleanup(dev);
368 + ar231x_init_cleanup(dev);
369 + unregister_netdev(dev);
370 + mdiobus_unregister(sp->mii_bus);
371 + mdiobus_free(sp->mii_bus);
372 + kfree(dev);
373 + return 0;
374 +}
375 +
376 +
377 +/*
378 + * Restart the AR2313 ethernet controller.
379 + */
380 +static int ar231x_restart(struct net_device *dev)
381 +{
382 + /* disable interrupts */
383 + disable_irq(dev->irq);
384 +
385 + /* stop mac */
386 + ar231x_halt(dev);
387 +
388 + /* initialize */
389 + ar231x_init(dev);
390 +
391 + /* enable interrupts */
392 + enable_irq(dev->irq);
393 +
394 + return 0;
395 +}
396 +
397 +static struct platform_driver ar231x_driver = {
398 + .driver.name = "ar231x-eth",
399 + .probe = ar231x_probe,
400 + .remove = __devexit_p(ar231x_remove),
401 +};
402 +
403 +int __init ar231x_module_init(void)
404 +{
405 + return platform_driver_register(&ar231x_driver);
406 +}
407 +
408 +void __exit ar231x_module_cleanup(void)
409 +{
410 + platform_driver_unregister(&ar231x_driver);
411 +}
412 +
413 +module_init(ar231x_module_init);
414 +module_exit(ar231x_module_cleanup);
415 +
416 +
417 +static void ar231x_free_descriptors(struct net_device *dev)
418 +{
419 + struct ar231x_private *sp = netdev_priv(dev);
420 + if (sp->rx_ring != NULL) {
421 + kfree((void *) KSEG0ADDR(sp->rx_ring));
422 + sp->rx_ring = NULL;
423 + sp->tx_ring = NULL;
424 + }
425 +}
426 +
427 +
428 +static int ar231x_allocate_descriptors(struct net_device *dev)
429 +{
430 + struct ar231x_private *sp = netdev_priv(dev);
431 + int size;
432 + int j;
433 + ar231x_descr_t *space;
434 +
435 + if (sp->rx_ring != NULL) {
436 + printk("%s: already done.\n", __FUNCTION__);
437 + return 0;
438 + }
439 +
440 + size =
441 + (sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES));
442 + space = kmalloc(size, GFP_KERNEL);
443 + if (space == NULL)
444 + return 1;
445 +
446 + /* invalidate caches */
447 + dma_cache_inv((unsigned int) space, size);
448 +
449 + /* now convert pointer to KSEG1 */
450 + space = (ar231x_descr_t *) KSEG1ADDR(space);
451 +
452 + memset((void *) space, 0, size);
453 +
454 + sp->rx_ring = space;
455 + space += AR2313_DESCR_ENTRIES;
456 +
457 + sp->tx_ring = space;
458 + space += AR2313_DESCR_ENTRIES;
459 +
460 + /* Initialize the transmit Descriptors */
461 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
462 + ar231x_descr_t *td = &sp->tx_ring[j];
463 + td->status = 0;
464 + td->devcs = DMA_TX1_CHAINED;
465 + td->addr = 0;
466 + td->descr =
467 + virt_to_phys(&sp->
468 + tx_ring[(j + 1) & (AR2313_DESCR_ENTRIES - 1)]);
469 + }
470 +
471 + return 0;
472 +}
473 +
474 +
475 +/*
476 + * Generic cleanup handling data allocated during init. Used when the
477 + * module is unloaded or if an error occurs during initialization
478 + */
479 +static void ar231x_init_cleanup(struct net_device *dev)
480 +{
481 + struct ar231x_private *sp = netdev_priv(dev);
482 + struct sk_buff *skb;
483 + int j;
484 +
485 + ar231x_free_descriptors(dev);
486 +
487 + if (sp->eth_regs)
488 + iounmap((void *) sp->eth_regs);
489 + if (sp->dma_regs)
490 + iounmap((void *) sp->dma_regs);
491 +
492 + if (sp->rx_skb) {
493 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
494 + skb = sp->rx_skb[j];
495 + if (skb) {
496 + sp->rx_skb[j] = NULL;
497 + dev_kfree_skb(skb);
498 + }
499 + }
500 + kfree(sp->rx_skb);
501 + sp->rx_skb = NULL;
502 + }
503 +
504 + if (sp->tx_skb) {
505 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
506 + skb = sp->tx_skb[j];
507 + if (skb) {
508 + sp->tx_skb[j] = NULL;
509 + dev_kfree_skb(skb);
510 + }
511 + }
512 + kfree(sp->tx_skb);
513 + sp->tx_skb = NULL;
514 + }
515 +}
516 +
517 +static int ar231x_setup_timer(struct net_device *dev)
518 +{
519 + struct ar231x_private *sp = netdev_priv(dev);
520 +
521 + init_timer(&sp->link_timer);
522 +
523 + sp->link_timer.function = ar231x_link_timer_fn;
524 + sp->link_timer.data = (int) dev;
525 + sp->link_timer.expires = jiffies + HZ;
526 +
527 + add_timer(&sp->link_timer);
528 + return 0;
529 +
530 +}
531 +
532 +static void ar231x_link_timer_fn(unsigned long data)
533 +{
534 + struct net_device *dev = (struct net_device *) data;
535 + struct ar231x_private *sp = netdev_priv(dev);
536 +
537 + // see if the link status changed
538 + // This was needed to make sure we set the PHY to the
539 + // autonegotiated value of half or full duplex.
540 + ar231x_check_link(dev);
541 +
542 + // Loop faster when we don't have link.
543 + // This was needed to speed up the AP bootstrap time.
544 + if (sp->link == 0) {
545 + mod_timer(&sp->link_timer, jiffies + HZ / 2);
546 + } else {
547 + mod_timer(&sp->link_timer, jiffies + LINK_TIMER);
548 + }
549 +}
550 +
551 +static void ar231x_check_link(struct net_device *dev)
552 +{
553 + struct ar231x_private *sp = netdev_priv(dev);
554 + u16 phyData;
555 +
556 + phyData = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR);
557 + if (sp->phyData != phyData) {
558 + if (phyData & BMSR_LSTATUS) {
559 + /* link is present, ready link partner ability to deterine
560 + duplexity */
561 + int duplex = 0;
562 + u16 reg;
563 +
564 + sp->link = 1;
565 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMCR);
566 + if (reg & BMCR_ANENABLE) {
567 + /* auto neg enabled */
568 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_LPA);
569 + duplex = (reg & (LPA_100FULL | LPA_10FULL)) ? 1 : 0;
570 + } else {
571 + /* no auto neg, just read duplex config */
572 + duplex = (reg & BMCR_FULLDPLX) ? 1 : 0;
573 + }
574 +
575 + printk(KERN_INFO "%s: Configuring MAC for %s duplex\n",
576 + dev->name, (duplex) ? "full" : "half");
577 +
578 + if (duplex) {
579 + /* full duplex */
580 + sp->eth_regs->mac_control =
581 + ((sp->eth_regs->
582 + mac_control | MAC_CONTROL_F) & ~MAC_CONTROL_DRO);
583 + } else {
584 + /* half duplex */
585 + sp->eth_regs->mac_control =
586 + ((sp->eth_regs->
587 + mac_control | MAC_CONTROL_DRO) & ~MAC_CONTROL_F);
588 + }
589 + } else {
590 + /* no link */
591 + sp->link = 0;
592 + }
593 + sp->phyData = phyData;
594 + }
595 +}
596 +
597 +static int ar231x_reset_reg(struct net_device *dev)
598 +{
599 + struct ar231x_private *sp = netdev_priv(dev);
600 + unsigned int ethsal, ethsah;
601 + unsigned int flags;
602 +
603 + *sp->int_regs |= sp->cfg->reset_mac;
604 + mdelay(10);
605 + *sp->int_regs &= ~sp->cfg->reset_mac;
606 + mdelay(10);
607 + *sp->int_regs |= sp->cfg->reset_phy;
608 + mdelay(10);
609 + *sp->int_regs &= ~sp->cfg->reset_phy;
610 + mdelay(10);
611 +
612 + sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
613 + mdelay(10);
614 + sp->dma_regs->bus_mode =
615 + ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
616 +
617 + /* enable interrupts */
618 + sp->dma_regs->intr_ena = (DMA_STATUS_AIS |
619 + DMA_STATUS_NIS |
620 + DMA_STATUS_RI |
621 + DMA_STATUS_TI | DMA_STATUS_FBE);
622 + sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
623 + sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
624 + sp->dma_regs->control =
625 + (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
626 +
627 + sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
628 + sp->eth_regs->vlan_tag = (0x8100);
629 +
630 + /* Enable Ethernet Interface */
631 + flags = (MAC_CONTROL_TE | /* transmit enable */
632 + MAC_CONTROL_PM | /* pass mcast */
633 + MAC_CONTROL_F | /* full duplex */
634 + MAC_CONTROL_HBD); /* heart beat disabled */
635 +
636 + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
637 + flags |= MAC_CONTROL_PR;
638 + }
639 + sp->eth_regs->mac_control = flags;
640 +
641 + /* Set all Ethernet station address registers to their initial values */
642 + ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
643 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF));
644 +
645 + ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
646 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
647 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
648 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF));
649 +
650 + sp->eth_regs->mac_addr[0] = ethsah;
651 + sp->eth_regs->mac_addr[1] = ethsal;
652 +
653 + mdelay(10);
654 +
655 + return (0);
656 +}
657 +
658 +
659 +static int ar231x_init(struct net_device *dev)
660 +{
661 + struct ar231x_private *sp = netdev_priv(dev);
662 + int ecode = 0;
663 +
664 + /*
665 + * Allocate descriptors
666 + */
667 + if (ar231x_allocate_descriptors(dev)) {
668 + printk("%s: %s: ar231x_allocate_descriptors failed\n",
669 + dev->name, __FUNCTION__);
670 + ecode = -EAGAIN;
671 + goto init_error;
672 + }
673 +
674 + /*
675 + * Get the memory for the skb rings.
676 + */
677 + if (sp->rx_skb == NULL) {
678 + sp->rx_skb =
679 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
680 + GFP_KERNEL);
681 + if (!(sp->rx_skb)) {
682 + printk("%s: %s: rx_skb kmalloc failed\n",
683 + dev->name, __FUNCTION__);
684 + ecode = -EAGAIN;
685 + goto init_error;
686 + }
687 + }
688 + memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
689 +
690 + if (sp->tx_skb == NULL) {
691 + sp->tx_skb =
692 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
693 + GFP_KERNEL);
694 + if (!(sp->tx_skb)) {
695 + printk("%s: %s: tx_skb kmalloc failed\n",
696 + dev->name, __FUNCTION__);
697 + ecode = -EAGAIN;
698 + goto init_error;
699 + }
700 + }
701 + memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
702 +
703 + /*
704 + * Set tx_csm before we start receiving interrupts, otherwise
705 + * the interrupt handler might think it is supposed to process
706 + * tx ints before we are up and running, which may cause a null
707 + * pointer access in the int handler.
708 + */
709 + sp->rx_skbprd = 0;
710 + sp->cur_rx = 0;
711 + sp->tx_prd = 0;
712 + sp->tx_csm = 0;
713 +
714 + /*
715 + * Zero the stats before starting the interface
716 + */
717 + memset(&dev->stats, 0, sizeof(dev->stats));
718 +
719 + /*
720 + * We load the ring here as there seem to be no way to tell the
721 + * firmware to wipe the ring without re-initializing it.
722 + */
723 + ar231x_load_rx_ring(dev, RX_RING_SIZE);
724 +
725 + /*
726 + * Init hardware
727 + */
728 + ar231x_reset_reg(dev);
729 +
730 + /*
731 + * Get the IRQ
732 + */
733 + ecode =
734 + request_irq(dev->irq, &ar231x_interrupt,
735 + IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
736 + dev->name, dev);
737 + if (ecode) {
738 + printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
739 + dev->name, __FUNCTION__, dev->irq);
740 + goto init_error;
741 + }
742 +
743 +
744 + tasklet_enable(&sp->rx_tasklet);
745 +
746 + return 0;
747 +
748 + init_error:
749 + ar231x_init_cleanup(dev);
750 + return ecode;
751 +}
752 +
753 +/*
754 + * Load the rx ring.
755 + *
756 + * Loading rings is safe without holding the spin lock since this is
757 + * done only before the device is enabled, thus no interrupts are
758 + * generated and by the interrupt handler/tasklet handler.
759 + */
760 +static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
761 +{
762 +
763 + struct ar231x_private *sp = netdev_priv(dev);
764 + short i, idx;
765 +
766 + idx = sp->rx_skbprd;
767 +
768 + for (i = 0; i < nr_bufs; i++) {
769 + struct sk_buff *skb;
770 + ar231x_descr_t *rd;
771 +
772 + if (sp->rx_skb[idx])
773 + break;
774 +
775 + skb = netdev_alloc_skb(dev, AR2313_BUFSIZE);
776 + if (!skb) {
777 + printk("\n\n\n\n %s: No memory in system\n\n\n\n",
778 + __FUNCTION__);
779 + break;
780 + }
781 +
782 + /*
783 + * Make sure IP header starts on a fresh cache line.
784 + */
785 + skb->dev = dev;
786 + skb_reserve(skb, RX_OFFSET);
787 + sp->rx_skb[idx] = skb;
788 +
789 + rd = (ar231x_descr_t *) & sp->rx_ring[idx];
790 +
791 + /* initialize dma descriptor */
792 + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
793 + DMA_RX1_CHAINED);
794 + rd->addr = virt_to_phys(skb->data);
795 + rd->descr =
796 + virt_to_phys(&sp->
797 + rx_ring[(idx + 1) & (AR2313_DESCR_ENTRIES - 1)]);
798 + rd->status = DMA_RX_OWN;
799 +
800 + idx = DSC_NEXT(idx);
801 + }
802 +
803 + if (i)
804 + sp->rx_skbprd = idx;
805 +
806 + return;
807 +}
808 +
809 +#define AR2313_MAX_PKTS_PER_CALL 64
810 +
811 +static int ar231x_rx_int(struct net_device *dev)
812 +{
813 + struct ar231x_private *sp = netdev_priv(dev);
814 + struct sk_buff *skb, *skb_new;
815 + ar231x_descr_t *rxdesc;
816 + unsigned int status;
817 + u32 idx;
818 + int pkts = 0;
819 + int rval;
820 +
821 + idx = sp->cur_rx;
822 +
823 + /* process at most the entire ring and then wait for another interrupt
824 + */
825 + while (1) {
826 +
827 + rxdesc = &sp->rx_ring[idx];
828 + status = rxdesc->status;
829 + if (status & DMA_RX_OWN) {
830 + /* SiByte owns descriptor or descr not yet filled in */
831 + rval = 0;
832 + break;
833 + }
834 +
835 + if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
836 + rval = 1;
837 + break;
838 + }
839 +
840 + if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
841 + dev->stats.rx_errors++;
842 + dev->stats.rx_dropped++;
843 +
844 + /* add statistics counters */
845 + if (status & DMA_RX_ERR_CRC)
846 + dev->stats.rx_crc_errors++;
847 + if (status & DMA_RX_ERR_COL)
848 + dev->stats.rx_over_errors++;
849 + if (status & DMA_RX_ERR_LENGTH)
850 + dev->stats.rx_length_errors++;
851 + if (status & DMA_RX_ERR_RUNT)
852 + dev->stats.rx_over_errors++;
853 + if (status & DMA_RX_ERR_DESC)
854 + dev->stats.rx_over_errors++;
855 +
856 + } else {
857 + /* alloc new buffer. */
858 + skb_new = netdev_alloc_skb(dev, AR2313_BUFSIZE + RX_OFFSET);
859 + if (skb_new != NULL) {
860 +
861 + skb = sp->rx_skb[idx];
862 + /* set skb */
863 + skb_put(skb,
864 + ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN);
865 +
866 + dev->stats.rx_bytes += skb->len;
867 + skb->protocol = eth_type_trans(skb, dev);
868 + /* pass the packet to upper layers */
869 + netif_rx(skb);
870 +
871 + skb_new->dev = dev;
872 + /* 16 bit align */
873 + skb_reserve(skb_new, RX_OFFSET);
874 + /* reset descriptor's curr_addr */
875 + rxdesc->addr = virt_to_phys(skb_new->data);
876 +
877 + dev->stats.rx_packets++;
878 + sp->rx_skb[idx] = skb_new;
879 + } else {
880 + dev->stats.rx_dropped++;
881 + }
882 + }
883 +
884 + rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
885 + DMA_RX1_CHAINED);
886 + rxdesc->status = DMA_RX_OWN;
887 +
888 + idx = DSC_NEXT(idx);
889 + }
890 +
891 + sp->cur_rx = idx;
892 +
893 + return rval;
894 +}
895 +
896 +
897 +static void ar231x_tx_int(struct net_device *dev)
898 +{
899 + struct ar231x_private *sp = netdev_priv(dev);
900 + u32 idx;
901 + struct sk_buff *skb;
902 + ar231x_descr_t *txdesc;
903 + unsigned int status = 0;
904 +
905 + idx = sp->tx_csm;
906 +
907 + while (idx != sp->tx_prd) {
908 + txdesc = &sp->tx_ring[idx];
909 +
910 + if ((status = txdesc->status) & DMA_TX_OWN) {
911 + /* ar231x dma still owns descr */
912 + break;
913 + }
914 + /* done with this descriptor */
915 + dma_unmap_single(NULL, txdesc->addr,
916 + txdesc->devcs & DMA_TX1_BSIZE_MASK,
917 + DMA_TO_DEVICE);
918 + txdesc->status = 0;
919 +
920 + if (status & DMA_TX_ERROR) {
921 + dev->stats.tx_errors++;
922 + dev->stats.tx_dropped++;
923 + if (status & DMA_TX_ERR_UNDER)
924 + dev->stats.tx_fifo_errors++;
925 + if (status & DMA_TX_ERR_HB)
926 + dev->stats.tx_heartbeat_errors++;
927 + if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
928 + dev->stats.tx_carrier_errors++;
929 + if (status & (DMA_TX_ERR_LATE |
930 + DMA_TX_ERR_COL |
931 + DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
932 + dev->stats.tx_aborted_errors++;
933 + } else {
934 + /* transmit OK */
935 + dev->stats.tx_packets++;
936 + }
937 +
938 + skb = sp->tx_skb[idx];
939 + sp->tx_skb[idx] = NULL;
940 + idx = DSC_NEXT(idx);
941 + dev->stats.tx_bytes += skb->len;
942 + dev_kfree_skb_irq(skb);
943 + }
944 +
945 + sp->tx_csm = idx;
946 +
947 + return;
948 +}
949 +
950 +
951 +static void rx_tasklet_func(unsigned long data)
952 +{
953 + struct net_device *dev = (struct net_device *) data;
954 + struct ar231x_private *sp = netdev_priv(dev);
955 +
956 + if (sp->unloading) {
957 + return;
958 + }
959 +
960 + if (ar231x_rx_int(dev)) {
961 + tasklet_hi_schedule(&sp->rx_tasklet);
962 + } else {
963 + unsigned long flags;
964 + spin_lock_irqsave(&sp->lock, flags);
965 + sp->dma_regs->intr_ena |= DMA_STATUS_RI;
966 + spin_unlock_irqrestore(&sp->lock, flags);
967 + }
968 +}
969 +
970 +static void rx_schedule(struct net_device *dev)
971 +{
972 + struct ar231x_private *sp = netdev_priv(dev);
973 +
974 + sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
975 +
976 + tasklet_hi_schedule(&sp->rx_tasklet);
977 +}
978 +
979 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
980 +{
981 + struct net_device *dev = (struct net_device *) dev_id;
982 + struct ar231x_private *sp = netdev_priv(dev);
983 + unsigned int status, enabled;
984 +
985 + /* clear interrupt */
986 + /*
987 + * Don't clear RI bit if currently disabled.
988 + */
989 + status = sp->dma_regs->status;
990 + enabled = sp->dma_regs->intr_ena;
991 + sp->dma_regs->status = status & enabled;
992 +
993 + if (status & DMA_STATUS_NIS) {
994 + /* normal status */
995 + /*
996 + * Don't schedule rx processing if interrupt
997 + * is already disabled.
998 + */
999 + if (status & enabled & DMA_STATUS_RI) {
1000 + /* receive interrupt */
1001 + rx_schedule(dev);
1002 + }
1003 + if (status & DMA_STATUS_TI) {
1004 + /* transmit interrupt */
1005 + ar231x_tx_int(dev);
1006 + }
1007 + }
1008 +
1009 + /* abnormal status */
1010 + if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS)) {
1011 + ar231x_restart(dev);
1012 + }
1013 + return IRQ_HANDLED;
1014 +}
1015 +
1016 +
1017 +static int ar231x_open(struct net_device *dev)
1018 +{
1019 + struct ar231x_private *sp = netdev_priv(dev);
1020 + unsigned int ethsal, ethsah;
1021 +
1022 + /* reset the hardware, in case the MAC address changed */
1023 + ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
1024 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF));
1025 +
1026 + ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
1027 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
1028 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
1029 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF));
1030 +
1031 + sp->eth_regs->mac_addr[0] = ethsah;
1032 + sp->eth_regs->mac_addr[1] = ethsal;
1033 +
1034 + mdelay(10);
1035 +
1036 + dev->mtu = 1500;
1037 + netif_start_queue(dev);
1038 +
1039 + sp->eth_regs->mac_control |= MAC_CONTROL_RE;
1040 +
1041 + return 0;
1042 +}
1043 +
1044 +static void ar231x_tx_timeout(struct net_device *dev)
1045 +{
1046 + struct ar231x_private *sp = netdev_priv(dev);
1047 + unsigned long flags;
1048 +
1049 + spin_lock_irqsave(&sp->lock, flags);
1050 + ar231x_restart(dev);
1051 + spin_unlock_irqrestore(&sp->lock, flags);
1052 +}
1053 +
1054 +static void ar231x_halt(struct net_device *dev)
1055 +{
1056 + struct ar231x_private *sp = netdev_priv(dev);
1057 + int j;
1058 +
1059 + tasklet_disable(&sp->rx_tasklet);
1060 +
1061 + /* kill the MAC */
1062 + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
1063 + MAC_CONTROL_TE); /* disable Transmits */
1064 + /* stop dma */
1065 + sp->dma_regs->control = 0;
1066 + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
1067 +
1068 + /* place phy and MAC in reset */
1069 + *sp->int_regs |= (sp->cfg->reset_mac | sp->cfg->reset_phy);
1070 +
1071 + /* free buffers on tx ring */
1072 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
1073 + struct sk_buff *skb;
1074 + ar231x_descr_t *txdesc;
1075 +
1076 + txdesc = &sp->tx_ring[j];
1077 + txdesc->descr = 0;
1078 +
1079 + skb = sp->tx_skb[j];
1080 + if (skb) {
1081 + dev_kfree_skb(skb);
1082 + sp->tx_skb[j] = NULL;
1083 + }
1084 + }
1085 +}
1086 +
1087 +/*
1088 + * close should do nothing. Here's why. It's called when
1089 + * 'ifconfig bond0 down' is run. If it calls free_irq then
1090 + * the irq is gone forever ! When bond0 is made 'up' again,
1091 + * the ar231x_open () does not call request_irq (). Worse,
1092 + * the call to ar231x_halt() generates a WDOG reset due to
1093 + * the write to 'sp->int_regs' and the box reboots.
1094 + * Commenting this out is good since it allows the
1095 + * system to resume when bond0 is made up again.
1096 + */
1097 +static int ar231x_close(struct net_device *dev)
1098 +{
1099 +#if 0
1100 + /*
1101 + * Disable interrupts
1102 + */
1103 + disable_irq(dev->irq);
1104 +
1105 + /*
1106 + * Without (or before) releasing irq and stopping hardware, this
1107 + * is an absolute non-sense, by the way. It will be reset instantly
1108 + * by the first irq.
1109 + */
1110 + netif_stop_queue(dev);
1111 +
1112 + /* stop the MAC and DMA engines */
1113 + ar231x_halt(dev);
1114 +
1115 + /* release the interrupt */
1116 + free_irq(dev->irq, dev);
1117 +
1118 +#endif
1119 + return 0;
1120 +}
1121 +
1122 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
1123 +{
1124 + struct ar231x_private *sp = netdev_priv(dev);
1125 + ar231x_descr_t *td;
1126 + u32 idx;
1127 +
1128 + idx = sp->tx_prd;
1129 + td = &sp->tx_ring[idx];
1130 +
1131 + if (td->status & DMA_TX_OWN) {
1132 + /* free skbuf and lie to the caller that we sent it out */
1133 + dev->stats.tx_dropped++;
1134 + dev_kfree_skb(skb);
1135 +
1136 + /* restart transmitter in case locked */
1137 + sp->dma_regs->xmt_poll = 0;
1138 + return 0;
1139 + }
1140 +
1141 + /* Setup the transmit descriptor. */
1142 + td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
1143 + (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
1144 + td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
1145 + td->status = DMA_TX_OWN;
1146 +
1147 + /* kick transmitter last */
1148 + sp->dma_regs->xmt_poll = 0;
1149 +
1150 + sp->tx_skb[idx] = skb;
1151 + idx = DSC_NEXT(idx);
1152 + sp->tx_prd = idx;
1153 +
1154 + return 0;
1155 +}
1156 +
1157 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1158 +{
1159 + struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
1160 + struct ar231x_private *sp = netdev_priv(dev);
1161 + int ret;
1162 +
1163 + switch (cmd) {
1164 +
1165 + case SIOCETHTOOL:
1166 + spin_lock_irq(&sp->lock);
1167 + ret = phy_ethtool_ioctl(sp->phy_dev, (void *) ifr->ifr_data);
1168 + spin_unlock_irq(&sp->lock);
1169 + return ret;
1170 +
1171 + case SIOCSIFHWADDR:
1172 + if (copy_from_user
1173 + (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
1174 + return -EFAULT;
1175 + return 0;
1176 +
1177 + case SIOCGIFHWADDR:
1178 + if (copy_to_user
1179 + (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
1180 + return -EFAULT;
1181 + return 0;
1182 +
1183 + case SIOCGMIIPHY:
1184 + case SIOCGMIIREG:
1185 + case SIOCSMIIREG:
1186 + return phy_mii_ioctl(sp->phy_dev, data, cmd);
1187 +
1188 + default:
1189 + break;
1190 + }
1191 +
1192 + return -EOPNOTSUPP;
1193 +}
1194 +
1195 +static void ar231x_adjust_link(struct net_device *dev)
1196 +{
1197 + struct ar231x_private *sp = netdev_priv(dev);
1198 + unsigned int mc;
1199 +
1200 + if (!sp->phy_dev->link)
1201 + return;
1202 +
1203 + if (sp->phy_dev->duplex != sp->oldduplex) {
1204 + mc = readl(&sp->eth_regs->mac_control);
1205 + mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO);
1206 + if (sp->phy_dev->duplex)
1207 + mc |= MAC_CONTROL_F;
1208 + else
1209 + mc |= MAC_CONTROL_DRO;
1210 + writel(mc, &sp->eth_regs->mac_control);
1211 + sp->oldduplex = sp->phy_dev->duplex;
1212 + }
1213 +}
1214 +
1215 +#define MII_ADDR(phy, reg) \
1216 + ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
1217 +
1218 +static int
1219 +ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1220 +{
1221 + struct net_device *const dev = bus->priv;
1222 + struct ar231x_private *sp = netdev_priv(dev);
1223 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1224 +
1225 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
1226 + while (ethernet->mii_addr & MII_ADDR_BUSY);
1227 + return (ethernet->mii_data >> MII_DATA_SHIFT);
1228 +}
1229 +
1230 +static int
1231 +ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
1232 + u16 value)
1233 +{
1234 + struct net_device *const dev = bus->priv;
1235 + struct ar231x_private *sp = netdev_priv(dev);
1236 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1237 +
1238 + while (ethernet->mii_addr & MII_ADDR_BUSY);
1239 + ethernet->mii_data = value << MII_DATA_SHIFT;
1240 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
1241 +
1242 + return 0;
1243 +}
1244 +
1245 +static int ar231x_mdiobus_reset(struct mii_bus *bus)
1246 +{
1247 + struct net_device *const dev = bus->priv;
1248 +
1249 + ar231x_reset_reg(dev);
1250 +
1251 + return 0;
1252 +}
1253 +
1254 +static int ar231x_mdiobus_probe (struct net_device *dev)
1255 +{
1256 + struct ar231x_private *const sp = netdev_priv(dev);
1257 + struct phy_device *phydev = NULL;
1258 + int phy_addr;
1259 +
1260 + /* find the first (lowest address) PHY on the current MAC's MII bus */
1261 + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
1262 + if (sp->mii_bus->phy_map[phy_addr]) {
1263 + phydev = sp->mii_bus->phy_map[phy_addr];
1264 + sp->phy = phy_addr;
1265 + break; /* break out with first one found */
1266 + }
1267 +
1268 + if (!phydev) {
1269 + printk (KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
1270 + return -1;
1271 + }
1272 +
1273 + /* now we are supposed to have a proper phydev, to attach to... */
1274 + BUG_ON(!phydev);
1275 + BUG_ON(phydev->attached_dev);
1276 +
1277 + phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, 0,
1278 + PHY_INTERFACE_MODE_MII);
1279 +
1280 + if (IS_ERR(phydev)) {
1281 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1282 + return PTR_ERR(phydev);
1283 + }
1284 +
1285 + /* mask with MAC supported features */
1286 + phydev->supported &= (SUPPORTED_10baseT_Half
1287 + | SUPPORTED_10baseT_Full
1288 + | SUPPORTED_100baseT_Half
1289 + | SUPPORTED_100baseT_Full
1290 + | SUPPORTED_Autoneg
1291 + /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
1292 + | SUPPORTED_MII
1293 + | SUPPORTED_TP);
1294 +
1295 + phydev->advertising = phydev->supported;
1296 +
1297 + sp->oldduplex = -1;
1298 + sp->phy_dev = phydev;
1299 +
1300 + printk(KERN_INFO "%s: attached PHY driver [%s] "
1301 + "(mii_bus:phy_addr=%s)\n",
1302 + dev->name, phydev->drv->name, dev_name(&phydev->dev));
1303 +
1304 + return 0;
1305 +}
1306 +
1307 --- /dev/null
1308 +++ b/drivers/net/ar231x.h
1309 @@ -0,0 +1,302 @@
1310 +/*
1311 + * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
1312 + *
1313 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
1314 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1315 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1316 + *
1317 + * Thanks to Atheros for providing hardware and documentation
1318 + * enabling me to write this driver.
1319 + *
1320 + * This program is free software; you can redistribute it and/or modify
1321 + * it under the terms of the GNU General Public License as published by
1322 + * the Free Software Foundation; either version 2 of the License, or
1323 + * (at your option) any later version.
1324 + */
1325 +
1326 +#ifndef _AR2313_H_
1327 +#define _AR2313_H_
1328 +
1329 +#include <generated/autoconf.h>
1330 +#include <linux/bitops.h>
1331 +#include <asm/bootinfo.h>
1332 +#include <ar231x_platform.h>
1333 +
1334 +/*
1335 + * probe link timer - 5 secs
1336 + */
1337 +#define LINK_TIMER (5*HZ)
1338 +
1339 +#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
1340 +#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
1341 +#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
1342 +
1343 +#define AR2313_TX_TIMEOUT (HZ/4)
1344 +
1345 +/*
1346 + * Rings
1347 + */
1348 +#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
1349 +#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
1350 +
1351 +#define AR2313_MBGET 2
1352 +#define AR2313_MBSET 3
1353 +#define AR2313_PCI_RECONFIG 4
1354 +#define AR2313_PCI_DUMP 5
1355 +#define AR2313_TEST_PANIC 6
1356 +#define AR2313_TEST_NULLPTR 7
1357 +#define AR2313_READ_DATA 8
1358 +#define AR2313_WRITE_DATA 9
1359 +#define AR2313_GET_VERSION 10
1360 +#define AR2313_TEST_HANG 11
1361 +#define AR2313_SYNC 12
1362 +
1363 +#define DMA_RX_ERR_CRC BIT(1)
1364 +#define DMA_RX_ERR_DRIB BIT(2)
1365 +#define DMA_RX_ERR_MII BIT(3)
1366 +#define DMA_RX_EV2 BIT(5)
1367 +#define DMA_RX_ERR_COL BIT(6)
1368 +#define DMA_RX_LONG BIT(7)
1369 +#define DMA_RX_LS BIT(8) /* last descriptor */
1370 +#define DMA_RX_FS BIT(9) /* first descriptor */
1371 +#define DMA_RX_MF BIT(10) /* multicast frame */
1372 +#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
1373 +#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
1374 +#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
1375 +#define DMA_RX_ERROR BIT(15) /* error summary */
1376 +#define DMA_RX_LEN_MASK 0x3fff0000
1377 +#define DMA_RX_LEN_SHIFT 16
1378 +#define DMA_RX_FILT BIT(30)
1379 +#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
1380 +
1381 +#define DMA_RX1_BSIZE_MASK 0x000007ff
1382 +#define DMA_RX1_BSIZE_SHIFT 0
1383 +#define DMA_RX1_CHAINED BIT(24)
1384 +#define DMA_RX1_RER BIT(25)
1385 +
1386 +#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
1387 +#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
1388 +#define DMA_TX_COL_MASK 0x78
1389 +#define DMA_TX_COL_SHIFT 3
1390 +#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
1391 +#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
1392 +#define DMA_TX_ERR_LATE BIT(9) /* late collision */
1393 +#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
1394 +#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
1395 +#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
1396 +#define DMA_TX_ERROR BIT(15) /* frame aborted */
1397 +#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
1398 +
1399 +#define DMA_TX1_BSIZE_MASK 0x000007ff
1400 +#define DMA_TX1_BSIZE_SHIFT 0
1401 +#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
1402 +#define DMA_TX1_TER BIT(25) /* transmit end of ring */
1403 +#define DMA_TX1_FS BIT(29) /* first segment */
1404 +#define DMA_TX1_LS BIT(30) /* last segment */
1405 +#define DMA_TX1_IC BIT(31) /* interrupt on completion */
1406 +
1407 +#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
1408 +
1409 +#define MAC_CONTROL_RE BIT(2) /* receive enable */
1410 +#define MAC_CONTROL_TE BIT(3) /* transmit enable */
1411 +#define MAC_CONTROL_DC BIT(5) /* Deferral check */
1412 +#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
1413 +#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
1414 +#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
1415 +#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
1416 +#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
1417 +#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
1418 +#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
1419 +#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
1420 +#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
1421 +#define MAC_CONTROL_PR BIT(18) /* promiscuous mode (valid frames only) */
1422 +#define MAC_CONTROL_PM BIT(19) /* pass multicast */
1423 +#define MAC_CONTROL_F BIT(20) /* full-duplex */
1424 +#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
1425 +#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
1426 +#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
1427 +#define MAC_CONTROL_RA BIT(31) /* receive all (valid and invalid frames) */
1428 +
1429 +#define MII_ADDR_BUSY BIT(0)
1430 +#define MII_ADDR_WRITE BIT(1)
1431 +#define MII_ADDR_REG_SHIFT 6
1432 +#define MII_ADDR_PHY_SHIFT 11
1433 +#define MII_DATA_SHIFT 0
1434 +
1435 +#define FLOW_CONTROL_FCE BIT(1)
1436 +
1437 +#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
1438 +#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
1439 +#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
1440 +#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
1441 +
1442 +#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
1443 +#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
1444 +#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
1445 +#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
1446 +#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
1447 +#define DMA_STATUS_RI BIT(6) /* receive interrupt */
1448 +#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
1449 +#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
1450 +#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
1451 +#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
1452 +#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
1453 +#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
1454 +#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
1455 +#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
1456 +#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
1457 +#define DMA_STATUS_EB_SHIFT 23 /* error bits */
1458 +
1459 +#define DMA_CONTROL_SR BIT(1) /* start receive */
1460 +#define DMA_CONTROL_ST BIT(13) /* start transmit */
1461 +#define DMA_CONTROL_SF BIT(21) /* store and forward */
1462 +
1463 +
1464 +typedef struct {
1465 + volatile unsigned int status; // OWN, Device control and status.
1466 + volatile unsigned int devcs; // pkt Control bits + Length
1467 + volatile unsigned int addr; // Current Address.
1468 + volatile unsigned int descr; // Next descriptor in chain.
1469 +} ar231x_descr_t;
1470 +
1471 +
1472 +
1473 +//
1474 +// New Combo structure for Both Eth0 AND eth1
1475 +//
1476 +typedef struct {
1477 + volatile unsigned int mac_control; /* 0x00 */
1478 + volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
1479 + volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
1480 + volatile unsigned int mii_addr; /* 0x14 */
1481 + volatile unsigned int mii_data; /* 0x18 */
1482 + volatile unsigned int flow_control; /* 0x1c */
1483 + volatile unsigned int vlan_tag; /* 0x20 */
1484 + volatile unsigned int pad[7]; /* 0x24 - 0x3c */
1485 + volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
1486 +
1487 +} ETHERNET_STRUCT;
1488 +
1489 +/********************************************************************
1490 + * Interrupt controller
1491 + ********************************************************************/
1492 +
1493 +typedef struct {
1494 + volatile unsigned int wdog_control; /* 0x08 */
1495 + volatile unsigned int wdog_timer; /* 0x0c */
1496 + volatile unsigned int misc_status; /* 0x10 */
1497 + volatile unsigned int misc_mask; /* 0x14 */
1498 + volatile unsigned int global_status; /* 0x18 */
1499 + volatile unsigned int reserved; /* 0x1c */
1500 + volatile unsigned int reset_control; /* 0x20 */
1501 +} INTERRUPT;
1502 +
1503 +/********************************************************************
1504 + * DMA controller
1505 + ********************************************************************/
1506 +typedef struct {
1507 + volatile unsigned int bus_mode; /* 0x00 (CSR0) */
1508 + volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
1509 + volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
1510 + volatile unsigned int rcv_base; /* 0x0c (CSR3) */
1511 + volatile unsigned int xmt_base; /* 0x10 (CSR4) */
1512 + volatile unsigned int status; /* 0x14 (CSR5) */
1513 + volatile unsigned int control; /* 0x18 (CSR6) */
1514 + volatile unsigned int intr_ena; /* 0x1c (CSR7) */
1515 + volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
1516 + volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
1517 + volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
1518 + volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
1519 +} DMA;
1520 +
1521 +/*
1522 + * Struct private for the Sibyte.
1523 + *
1524 + * Elements are grouped so variables used by the tx handling goes
1525 + * together, and will go into the same cache lines etc. in order to
1526 + * avoid cache line contention between the rx and tx handling on SMP.
1527 + *
1528 + * Frequently accessed variables are put at the beginning of the
1529 + * struct to help the compiler generate better/shorter code.
1530 + */
1531 +struct ar231x_private {
1532 + struct net_device *dev;
1533 + int version;
1534 + u32 mb[2];
1535 +
1536 + volatile ETHERNET_STRUCT *phy_regs;
1537 + volatile ETHERNET_STRUCT *eth_regs;
1538 + volatile DMA *dma_regs;
1539 + volatile u32 *int_regs;
1540 + struct ar231x_eth *cfg;
1541 +
1542 + spinlock_t lock; /* Serialise access to device */
1543 +
1544 + /*
1545 + * RX and TX descriptors, must be adjacent
1546 + */
1547 + ar231x_descr_t *rx_ring;
1548 + ar231x_descr_t *tx_ring;
1549 +
1550 +
1551 + struct sk_buff **rx_skb;
1552 + struct sk_buff **tx_skb;
1553 +
1554 + /*
1555 + * RX elements
1556 + */
1557 + u32 rx_skbprd;
1558 + u32 cur_rx;
1559 +
1560 + /*
1561 + * TX elements
1562 + */
1563 + u32 tx_prd;
1564 + u32 tx_csm;
1565 +
1566 + /*
1567 + * Misc elements
1568 + */
1569 + char name[48];
1570 + struct {
1571 + u32 address;
1572 + u32 length;
1573 + char *mapping;
1574 + } desc;
1575 +
1576 +
1577 + struct timer_list link_timer;
1578 + unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
1579 + unsigned short mac;
1580 + unsigned short link; /* 0 - link down, 1 - link up */
1581 + u16 phyData;
1582 +
1583 + struct tasklet_struct rx_tasklet;
1584 + int unloading;
1585 +
1586 + struct phy_device *phy_dev;
1587 + struct mii_bus *mii_bus;
1588 + int oldduplex;
1589 +};
1590 +
1591 +
1592 +/*
1593 + * Prototypes
1594 + */
1595 +static int ar231x_init(struct net_device *dev);
1596 +#ifdef TX_TIMEOUT
1597 +static void ar231x_tx_timeout(struct net_device *dev);
1598 +#endif
1599 +static int ar231x_restart(struct net_device *dev);
1600 +static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
1601 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
1602 +static int ar231x_open(struct net_device *dev);
1603 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
1604 +static int ar231x_close(struct net_device *dev);
1605 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr,
1606 + int cmd);
1607 +static void ar231x_init_cleanup(struct net_device *dev);
1608 +static int ar231x_setup_timer(struct net_device *dev);
1609 +static void ar231x_link_timer_fn(unsigned long data);
1610 +static void ar231x_check_link(struct net_device *dev);
1611 +#endif /* _AR2313_H_ */
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