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integrate the newer broadcom wl driver from us robotics
[openwrt.git] / target / linux / aruba-2.6 / patches / 000-aruba.patch
1 diff -Nur linux-2.6.16/arch/mips/aruba/Makefile linux-2.6.16-owrt/arch/mips/aruba/Makefile
2 --- linux-2.6.16/arch/mips/aruba/Makefile 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.16-owrt/arch/mips/aruba/Makefile 2006-03-20 14:25:10.000000000 +0100
4 @@ -0,0 +1,49 @@
5 +###############################################################################
6 +#
7 +# BRIEF MODULE DESCRIPTION
8 +# Makefile for IDT EB434 BSP
9 +#
10 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
11 +#
12 +# This program is free software; you can redistribute it and/or modify it
13 +# under the terms of the GNU General Public License as published by the
14 +# Free Software Foundation; either version 2 of the License, or (at your
15 +# option) any later version.
16 +#
17 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 +#
28 +# You should have received a copy of the GNU General Public License along
29 +# with this program; if not, write to the Free Software Foundation, Inc.,
30 +# 675 Mass Ave, Cambridge, MA 02139, USA.
31 +#
32 +#
33 +###############################################################################
34 +# May 2004 rkt, neb
35 +#
36 +# Initial Release
37 +#
38 +#
39 +#
40 +###############################################################################
41 +
42 +
43 +# .S.s:
44 +# $(CPP) $(CFLAGS) $< -o $*.s
45 +# .S.o:
46 +# $(CC) $(CFLAGS) -c $< -o $*.o
47 +
48 +obj-y := prom.o setup.o idtIRQ.o irq.o time.o flash_lock.o wdt_merlot.o
49 +obj-$(CONFIG_SERIAL_8250) += serial.o
50 +
51 +subdir-y += nvram
52 +obj-y += nvram/built-in.o
53 +
54 diff -Nur linux-2.6.16/arch/mips/aruba/nvram/Makefile linux-2.6.16-owrt/arch/mips/aruba/nvram/Makefile
55 --- linux-2.6.16/arch/mips/aruba/nvram/Makefile 1970-01-01 01:00:00.000000000 +0100
56 +++ linux-2.6.16-owrt/arch/mips/aruba/nvram/Makefile 2006-03-20 14:25:10.000000000 +0100
57 @@ -0,0 +1,46 @@
58 +###############################################################################
59 +#
60 +# BRIEF MODULE DESCRIPTION
61 +# Makefile for IDT EB434 nvram access routines
62 +#
63 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
64 +#
65 +# This program is free software; you can redistribute it and/or modify it
66 +# under the terms of the GNU General Public License as published by the
67 +# Free Software Foundation; either version 2 of the License, or (at your
68 +# option) any later version.
69 +#
70 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
71 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
72 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
73 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
74 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
75 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
76 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
77 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
80 +#
81 +# You should have received a copy of the GNU General Public License along
82 +# with this program; if not, write to the Free Software Foundation, Inc.,
83 +# 675 Mass Ave, Cambridge, MA 02139, USA.
84 +#
85 +#
86 +###############################################################################
87 +# May 2004 rkt, neb
88 +#
89 +# Initial Release
90 +#
91 +#
92 +#
93 +###############################################################################
94 +
95 +obj-y := nvram434.o
96 +obj-m := $(O_TARGET)
97 +
98 +
99 +
100 +
101 +
102 +
103 +
104 diff -Nur linux-2.6.16/arch/mips/aruba/nvram/nvram434.c linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.c
105 --- linux-2.6.16/arch/mips/aruba/nvram/nvram434.c 1970-01-01 01:00:00.000000000 +0100
106 +++ linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.c 2006-03-20 14:25:10.000000000 +0100
107 @@ -0,0 +1,392 @@
108 +/**************************************************************************
109 + *
110 + * BRIEF MODULE DESCRIPTION
111 + * nvram interface routines.
112 + *
113 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
114 + *
115 + * This program is free software; you can redistribute it and/or modify it
116 + * under the terms of the GNU General Public License as published by the
117 + * Free Software Foundation; either version 2 of the License, or (at your
118 + * option) any later version.
119 + *
120 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
121 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
122 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
123 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
124 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
125 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
126 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
127 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
128 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
129 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
130 + *
131 + * You should have received a copy of the GNU General Public License along
132 + * with this program; if not, write to the Free Software Foundation, Inc.,
133 + * 675 Mass Ave, Cambridge, MA 02139, USA.
134 + *
135 + *
136 + **************************************************************************
137 + * May 2004 rkt, neb
138 + *
139 + * Initial Release
140 + *
141 + *
142 + *
143 + **************************************************************************
144 + */
145 +
146 +#include <linux/ctype.h>
147 +#include <linux/string.h>
148 +
149 +//#include <asm/ds1553rtc.h>
150 +#include "nvram434.h"
151 +#define NVRAM_BASE 0xbfff8000
152 +
153 +extern void setenv (char *e, char *v, int rewrite);
154 +extern void unsetenv (char *e);
155 +extern void mapenv (int (*func)(char *, char *));
156 +extern char *getenv (char *s);
157 +extern void purgeenv(void);
158 +
159 +static void nvram_initenv(void);
160 +
161 +static unsigned char
162 +nvram_getbyte(int offs)
163 +{
164 + return(*((unsigned char*)(NVRAM_BASE + offs)));
165 +}
166 +
167 +static void
168 +nvram_setbyte(int offs, unsigned char val)
169 +{
170 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
171 +
172 + *nvramDataPointer = val;
173 +}
174 +
175 +/*
176 + * BigEndian!
177 + */
178 +static unsigned short
179 +nvram_getshort(int offs)
180 +{
181 + return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
182 +}
183 +
184 +static void
185 +nvram_setshort(int offs, unsigned short val)
186 +{
187 + nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
188 + nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
189 +}
190 +#if 0
191 +static unsigned int
192 +nvram_getint(int offs)
193 +{
194 + unsigned int val;
195 + val = nvram_getbyte(offs) << 24;
196 + val |= nvram_getbyte(offs + 1) << 16;
197 + val |= nvram_getbyte(offs + 2) << 8;
198 + val |= nvram_getbyte(offs + 3);
199 + return(val);
200 +}
201 +
202 +static void
203 +nvram_setint(int offs, unsigned int val)
204 +{
205 + nvram_setbyte(offs, val >> 24);
206 + nvram_setbyte(offs + 1, val >> 16);
207 + nvram_setbyte(offs + 2, val >> 8);
208 + nvram_setbyte(offs + 3, val);
209 +}
210 +#endif
211 +/*
212 + * calculate NVRAM checksum
213 + */
214 +static unsigned short
215 +nvram_calcsum(void)
216 +{
217 + unsigned short sum = NV_MAGIC;
218 + int i;
219 +
220 + for (i = ENV_BASE; i < ENV_TOP; i += 2)
221 + sum += nvram_getshort(i);
222 + return(sum);
223 +}
224 +
225 +/*
226 + * update the nvram checksum
227 + */
228 +static void
229 +nvram_updatesum (void)
230 +{
231 + nvram_setshort(NVOFF_CSUM, nvram_calcsum());
232 +}
233 +
234 +/*
235 + * test validity of nvram by checksumming it
236 + */
237 +static int
238 +nvram_isvalid(void)
239 +{
240 + static int is_valid;
241 +
242 + if (is_valid)
243 + return(1);
244 +
245 + if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
246 + printk("nvram_isvalid FAILED\n");
247 + //nvram_initenv();
248 + }
249 + is_valid = 1;
250 + return(1);
251 +}
252 +
253 +/* return nvram address of environment string */
254 +static int
255 +nvram_matchenv(char *s)
256 +{
257 + int envsize, envp, n, i, varsize;
258 + char *var;
259 +
260 + envsize = nvram_getshort(NVOFF_ENVSIZE);
261 +
262 + if (envsize > ENV_AVAIL)
263 + return(0); /* sanity */
264 +
265 + envp = ENV_BASE;
266 +
267 + if ((n = strlen (s)) > 255)
268 + return(0);
269 +
270 + while (envsize > 0) {
271 + varsize = nvram_getbyte(envp);
272 + if (varsize == 0 || (envp + varsize) > ENV_TOP)
273 + return(0); /* sanity */
274 + for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
275 + char c1 = nvram_getbyte(i);
276 + char c2 = *var;
277 + if (islower(c1))
278 + c1 = toupper(c1);
279 + if (islower(c2))
280 + c2 = toupper(c2);
281 + if (c1 != c2)
282 + break;
283 + }
284 + if (i > envp + n) { /* match so far */
285 + if (n == varsize - 1) /* match on boolean */
286 + return(envp);
287 + if (nvram_getbyte(i) == '=') /* exact match on variable */
288 + return(envp);
289 + }
290 + envsize -= varsize;
291 + envp += varsize;
292 + }
293 + return(0);
294 +}
295 +
296 +static void nvram_initenv(void)
297 +{
298 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
299 + nvram_setshort(NVOFF_ENVSIZE, 0);
300 +
301 + nvram_updatesum();
302 +}
303 +
304 +static void
305 +nvram_delenv(char *s)
306 +{
307 + int nenvp, envp, envsize, nbytes;
308 +
309 + envp = nvram_matchenv(s);
310 + if (envp == 0)
311 + return;
312 +
313 + nenvp = envp + nvram_getbyte(envp);
314 + envsize = nvram_getshort(NVOFF_ENVSIZE);
315 + nbytes = envsize - (nenvp - ENV_BASE);
316 + nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
317 + while (nbytes--) {
318 + nvram_setbyte(envp, nvram_getbyte(nenvp));
319 + envp++;
320 + nenvp++;
321 + }
322 + nvram_updatesum();
323 +}
324 +
325 +static int
326 +nvram_setenv(char *s, char *v)
327 +{
328 + int ns, nv, total;
329 + int envp;
330 +
331 + if (!nvram_isvalid())
332 + return(-1);
333 +
334 + nvram_delenv(s);
335 + ns = strlen(s);
336 + if (ns == 0)
337 + return (-1);
338 + if (v && *v) {
339 + nv = strlen(v);
340 + total = ns + nv + 2;
341 + }
342 + else {
343 + nv = 0;
344 + total = ns + 1;
345 + }
346 + if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
347 + return(-1);
348 +
349 + envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
350 +
351 + nvram_setbyte(envp, (unsigned char) total);
352 + envp++;
353 +
354 + while (ns--) {
355 + nvram_setbyte(envp, *s);
356 + envp++;
357 + s++;
358 + }
359 +
360 + if (nv) {
361 + nvram_setbyte(envp, '=');
362 + envp++;
363 + while (nv--) {
364 + nvram_setbyte(envp, *v);
365 + envp++;
366 + v++;
367 + }
368 + }
369 + nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
370 + nvram_updatesum();
371 + return 0;
372 +}
373 +
374 +static char *
375 +nvram_getenv(char *s)
376 +{
377 + static char buf[256]; /* FIXME: this cannot be static */
378 + int envp, ns, nbytes, i;
379 +
380 + if (!nvram_isvalid())
381 + return "INVALID NVRAM"; //((char *)0);
382 +
383 + envp = nvram_matchenv(s);
384 + if (envp == 0)
385 + return "NOT FOUND"; //((char *)0);
386 + ns = strlen(s);
387 + if (nvram_getbyte(envp) == ns + 1) /* boolean */
388 + buf[0] = '\0';
389 + else {
390 + nbytes = nvram_getbyte(envp) - (ns + 2);
391 + envp += ns + 2;
392 + for (i = 0; i < nbytes; i++)
393 + buf[i] = nvram_getbyte(envp++);
394 + buf[i] = '\0';
395 + }
396 + return(buf);
397 +}
398 +
399 +static void
400 +nvram_unsetenv(char *s)
401 +{
402 + if (!nvram_isvalid())
403 + return;
404 +
405 + nvram_delenv(s);
406 +}
407 +
408 +/*
409 + * apply func to each string in environment
410 + */
411 +static void
412 +nvram_mapenv(int (*func)(char *, char *))
413 +{
414 + int envsize, envp, n, i, seeneql;
415 + char name[256], value[256];
416 + char c, *s;
417 +
418 + if (!nvram_isvalid())
419 + return;
420 +
421 + envsize = nvram_getshort(NVOFF_ENVSIZE);
422 + envp = ENV_BASE;
423 +
424 + while (envsize > 0) {
425 + value[0] = '\0';
426 + seeneql = 0;
427 + s = name;
428 + n = nvram_getbyte(envp);
429 + for (i = envp + 1; i < envp + n; i++) {
430 + c = nvram_getbyte(i);
431 + if ((c == '=') && !seeneql) {
432 + *s = '\0';
433 + s = value;
434 + seeneql = 1;
435 + continue;
436 + }
437 + *s++ = c;
438 + }
439 + *s = '\0';
440 + (*func)(name, value);
441 + envsize -= n;
442 + envp += n;
443 + }
444 +}
445 +#if 0
446 +static unsigned int
447 +digit(char c)
448 +{
449 + if ('0' <= c && c <= '9')
450 + return (c - '0');
451 + if ('A' <= c && c <= 'Z')
452 + return (10 + c - 'A');
453 + if ('a' <= c && c <= 'z')
454 + return (10 + c - 'a');
455 + return (~0);
456 +}
457 +#endif
458 +/*
459 + * Wrappers to allow 'special' environment variables to get processed
460 + */
461 +void
462 +setenv(char *e, char *v, int rewrite)
463 +{
464 + if (nvram_getenv(e) && !rewrite)
465 + return;
466 +
467 + nvram_setenv(e, v);
468 +}
469 +
470 +char *
471 +getenv(char *e)
472 +{
473 + return(nvram_getenv(e));
474 +}
475 +
476 +void
477 +unsetenv(char *e)
478 +{
479 + nvram_unsetenv(e);
480 +}
481 +
482 +void
483 +purgeenv()
484 +{
485 + int i;
486 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
487 +
488 + for (i = ENV_BASE; i < ENV_TOP; i++)
489 + *nvramDataPointer++ = 0;
490 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
491 + nvram_setshort(NVOFF_ENVSIZE, 0);
492 + nvram_setshort(NVOFF_CSUM, NV_MAGIC);
493 +}
494 +
495 +void
496 +mapenv(int (*func)(char *, char *))
497 +{
498 + nvram_mapenv(func);
499 +}
500 diff -Nur linux-2.6.16/arch/mips/aruba/nvram/nvram434.h linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.h
501 --- linux-2.6.16/arch/mips/aruba/nvram/nvram434.h 1970-01-01 01:00:00.000000000 +0100
502 +++ linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.h 2006-03-20 14:25:10.000000000 +0100
503 @@ -0,0 +1,66 @@
504 +/**************************************************************************
505 + *
506 + * BRIEF MODULE DESCRIPTION
507 + * nvram definitions.
508 + *
509 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
510 + *
511 + * This program is free software; you can redistribute it and/or modify it
512 + * under the terms of the GNU General Public License as published by the
513 + * Free Software Foundation; either version 2 of the License, or (at your
514 + * option) any later version.
515 + *
516 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
517 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
518 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
519 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
520 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
521 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
522 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
523 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
524 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
525 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
526 + *
527 + * You should have received a copy of the GNU General Public License along
528 + * with this program; if not, write to the Free Software Foundation, Inc.,
529 + * 675 Mass Ave, Cambridge, MA 02139, USA.
530 + *
531 + *
532 + **************************************************************************
533 + * May 2004 rkt, neb
534 + *
535 + * Initial Release
536 + *
537 + *
538 + *
539 + **************************************************************************
540 + */
541 +
542 +
543 +#ifndef _NVRAM_
544 +#define _NVRAM_
545 +#define NVOFFSET 0 /* use all of NVRAM */
546 +
547 +/* Offsets to reserved locations */
548 + /* size description */
549 +#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */
550 +#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment checksum */
551 +#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' */
552 +#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte */
553 +#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address */
554 +#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table */
555 +
556 +#define NV_MAGIC 0xdeaf /* nvram magic number */
557 +#define NV_RESERVED 6 /* number of reserved bytes */
558 +
559 +#undef NVOFF_ETHADDR
560 +#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)
561 +
562 +/* number of bytes available for environment */
563 +#define ENV_BASE (NVOFFSET + NV_RESERVED)
564 +#define ENV_TOP 0x2000
565 +#define ENV_AVAIL (ENV_TOP - ENV_BASE)
566 +
567 +#endif /* _NVRAM_ */
568 +
569 +
570 diff -Nur linux-2.6.16/arch/mips/aruba/prom.c linux-2.6.16-owrt/arch/mips/aruba/prom.c
571 --- linux-2.6.16/arch/mips/aruba/prom.c 1970-01-01 01:00:00.000000000 +0100
572 +++ linux-2.6.16-owrt/arch/mips/aruba/prom.c 2006-03-20 14:25:10.000000000 +0100
573 @@ -0,0 +1,111 @@
574 +/**************************************************************************
575 + *
576 + * BRIEF MODULE DESCRIPTION
577 + * prom interface routines
578 + *
579 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
580 + *
581 + * This program is free software; you can redistribute it and/or modify it
582 + * under the terms of the GNU General Public License as published by the
583 + * Free Software Foundation; either version 2 of the License, or (at your
584 + * option) any later version.
585 + *
586 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
587 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
588 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
589 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
590 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
591 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
592 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
593 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
594 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
595 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
596 + *
597 + * You should have received a copy of the GNU General Public License along
598 + * with this program; if not, write to the Free Software Foundation, Inc.,
599 + * 675 Mass Ave, Cambridge, MA 02139, USA.
600 + *
601 + *
602 + **************************************************************************
603 + * May 2004 rkt, neb
604 + *
605 + * Initial Release
606 + *
607 + *
608 + *
609 + **************************************************************************
610 + */
611 +
612 +#include <linux/config.h>
613 +#include <linux/init.h>
614 +#include <linux/mm.h>
615 +#include <linux/module.h>
616 +#include <linux/string.h>
617 +#include <linux/console.h>
618 +#include <asm/bootinfo.h>
619 +#include <linux/bootmem.h>
620 +#include <linux/ioport.h>
621 +#include <linux/serial.h>
622 +#include <linux/serialP.h>
623 +#include <asm/serial.h>
624 +#include <linux/ioport.h>
625 +
626 +unsigned int idt_cpu_freq;
627 +EXPORT_SYMBOL(idt_cpu_freq);
628 +
629 +unsigned int arch_has_pci=0;
630 +
631 +/* Kernel Boot parameters */
632 +static unsigned char bootparm[] = "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2";
633 +
634 +extern unsigned long mips_machgroup;
635 +extern unsigned long mips_machtype;
636 +
637 +extern void setup_serial_port(void);
638 +extern char * getenv(char *e);
639 +
640 +/* IDT 79EB434 memory map -- we really should be auto sizing it */
641 +#define RAM_SIZE 32*1024*1024
642 +
643 +char *__init prom_getcmdline(void)
644 +{
645 + return &(arcs_cmdline[0]);
646 +}
647 +
648 +void __init prom_init(void)
649 +{
650 + char *boardname;
651 + sprintf(arcs_cmdline, "%s", bootparm);
652 +
653 + /* set our arch type */
654 + mips_machgroup = MACH_GROUP_ARUBA;
655 + mips_machtype = MACH_ARUBA_UNKNOWN;
656 +
657 + boardname=getenv("boardname");
658 +
659 + if (!strcmp(boardname,"Muscat")) {
660 + mips_machtype = MACH_ARUBA_AP70;
661 + idt_cpu_freq = 133000000;
662 + arch_has_pci=1;
663 + } else if (!strcmp(boardname,"Mataro")) {
664 + mips_machtype = MACH_ARUBA_AP65;
665 + idt_cpu_freq = 110000000;
666 + } else if (!strcmp(boardname,"Merlot")) {
667 + mips_machtype = MACH_ARUBA_AP60;
668 + idt_cpu_freq = 90000000;
669 + }
670 +
671 + /* turn on the console */
672 + setup_serial_port();
673 +
674 + /*
675 + * give all RAM to boot allocator,
676 + * except where the kernel was loaded
677 + */
678 + add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
679 +}
680 +
681 +void prom_free_prom_memory(void)
682 +{
683 + printk("stubbed prom_free_prom_memory()\n");
684 +}
685 diff -Nur linux-2.6.16/arch/mips/aruba/serial.c linux-2.6.16-owrt/arch/mips/aruba/serial.c
686 --- linux-2.6.16/arch/mips/aruba/serial.c 1970-01-01 01:00:00.000000000 +0100
687 +++ linux-2.6.16-owrt/arch/mips/aruba/serial.c 2006-03-20 14:25:10.000000000 +0100
688 @@ -0,0 +1,94 @@
689 +/**************************************************************************
690 + *
691 + * BRIEF MODULE DESCRIPTION
692 + * Serial port initialisation.
693 + *
694 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
695 + *
696 + * This program is free software; you can redistribute it and/or modify it
697 + * under the terms of the GNU General Public License as published by the
698 + * Free Software Foundation; either version 2 of the License, or (at your
699 + * option) any later version.
700 + *
701 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
702 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
703 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
704 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
705 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
706 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
707 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
708 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
709 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
710 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
711 + *
712 + * You should have received a copy of the GNU General Public License along
713 + * with this program; if not, write to the Free Software Foundation, Inc.,
714 + * 675 Mass Ave, Cambridge, MA 02139, USA.
715 + *
716 + *
717 + **************************************************************************
718 + * May 2004 rkt, neb
719 + *
720 + * Initial Release
721 + *
722 + *
723 + *
724 + **************************************************************************
725 + */
726 +
727 +
728 +#include <linux/config.h>
729 +#include <linux/init.h>
730 +#include <linux/sched.h>
731 +#include <linux/pci.h>
732 +#include <linux/interrupt.h>
733 +#include <linux/tty.h>
734 +#include <linux/serial.h>
735 +#include <linux/serial_core.h>
736 +
737 +#include <asm/time.h>
738 +#include <asm/cpu.h>
739 +#include <asm/bootinfo.h>
740 +#include <asm/irq.h>
741 +#include <asm/serial.h>
742 +
743 +#include <asm/idt-boards/rc32434/rc32434.h>
744 +
745 +extern int __init early_serial_setup(struct uart_port *port);
746 +
747 +#define BASE_BAUD (1843200 / 16)
748 +
749 +extern unsigned int idt_cpu_freq;
750 +
751 +extern int __init setup_serial_port(void)
752 +{
753 + static struct uart_port serial_req[2];
754 +
755 + memset(serial_req, 0, sizeof(serial_req));
756 + serial_req[0].type = PORT_16550A;
757 + serial_req[0].line = 0;
758 + serial_req[0].flags = STD_COM_FLAGS;
759 + serial_req[0].iotype = SERIAL_IO_MEM;
760 + serial_req[0].regshift = 2;
761 +
762 + switch (mips_machtype) {
763 + case MACH_ARUBA_AP70:
764 + serial_req[0].irq = 104;
765 + serial_req[0].mapbase = KSEG1ADDR(0x18058003);
766 + serial_req[0].membase = (char *) KSEG1ADDR(0x18058003);
767 + serial_req[0].uartclk = idt_cpu_freq;
768 + break;
769 + case MACH_ARUBA_AP65:
770 + case MACH_ARUBA_AP60:
771 + default:
772 + serial_req[0].irq = 12;
773 + serial_req[0].mapbase = KSEG1ADDR(0xbc000003);
774 + serial_req[0].membase = (char *) KSEG1ADDR(0xbc000003);
775 + serial_req[0].uartclk = idt_cpu_freq / 2;
776 + break;
777 + }
778 +
779 + early_serial_setup(&serial_req[0]);
780 +
781 + return(0);
782 +}
783 diff -Nur linux-2.6.16/arch/mips/aruba/setup.c linux-2.6.16-owrt/arch/mips/aruba/setup.c
784 --- linux-2.6.16/arch/mips/aruba/setup.c 1970-01-01 01:00:00.000000000 +0100
785 +++ linux-2.6.16-owrt/arch/mips/aruba/setup.c 2006-03-20 14:30:00.000000000 +0100
786 @@ -0,0 +1,125 @@
787 +/**************************************************************************
788 + *
789 + * BRIEF MODULE DESCRIPTION
790 + * setup routines for IDT EB434 boards
791 + *
792 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
793 + *
794 + * This program is free software; you can redistribute it and/or modify it
795 + * under the terms of the GNU General Public License as published by the
796 + * Free Software Foundation; either version 2 of the License, or (at your
797 + * option) any later version.
798 + *
799 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
800 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
801 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
802 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
803 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
804 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
805 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
806 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
807 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
808 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
809 + *
810 + * You should have received a copy of the GNU General Public License along
811 + * with this program; if not, write to the Free Software Foundation, Inc.,
812 + * 675 Mass Ave, Cambridge, MA 02139, USA.
813 + *
814 + *
815 + **************************************************************************
816 + * May 2004 rkt, neb
817 + *
818 + * Initial Release
819 + *
820 + *
821 + *
822 + **************************************************************************
823 + */
824 +
825 +#include <linux/init.h>
826 +#include <linux/mm.h>
827 +#include <linux/sched.h>
828 +#include <linux/irq.h>
829 +#include <asm/bootinfo.h>
830 +#include <asm/io.h>
831 +#include <linux/ioport.h>
832 +#include <asm/mipsregs.h>
833 +#include <asm/pgtable.h>
834 +#include <asm/reboot.h>
835 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
836 +#include <asm/idt-boards/rc32434/rc32434.h>
837 +#include <linux/pm.h>
838 +
839 +extern char *__init prom_getcmdline(void);
840 +
841 +extern void (*board_time_init) (void);
842 +extern void (*board_timer_setup) (struct irqaction * irq);
843 +extern void aruba_time_init(void);
844 +extern void aruba_timer_setup(struct irqaction *irq);
845 +extern void aruba_reset(void);
846 +
847 +#define epldMask ((volatile unsigned char *)0xB900000d)
848 +
849 +static void aruba_machine_restart(char *command)
850 +{
851 + switch (mips_machtype) {
852 + case MACH_ARUBA_AP70:
853 + *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
854 + break;
855 + case MACH_ARUBA_AP65:
856 + case MACH_ARUBA_AP60:
857 + default:
858 + /* Reset*/
859 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
860 + udelay(100);
861 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
862 + udelay(100);
863 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
864 + break;
865 + }
866 +}
867 +
868 +static void aruba_machine_halt(void)
869 +{
870 + for (;;) continue;
871 +}
872 +
873 +extern char * getenv(char *e);
874 +extern void unlock_ap60_70_flash(void);
875 +extern void wdt_merlot_disable(void);
876 +
877 +void __init plat_setup(void)
878 +{
879 + board_time_init = aruba_time_init;
880 +
881 + board_timer_setup = aruba_timer_setup;
882 +
883 + _machine_restart = aruba_machine_restart;
884 + _machine_halt = aruba_machine_halt;
885 + pm_power_off = aruba_machine_halt;
886 +
887 + set_io_port_base(KSEG1);
888 +
889 + /* Enable PCI interrupts in EPLD Mask register */
890 + *epldMask = 0x0;
891 + *(epldMask + 1) = 0x0;
892 +
893 + write_c0_wired(0);
894 + unlock_ap60_70_flash();
895 +
896 + printk("BOARD - %s\n",getenv("boardname"));
897 +
898 + wdt_merlot_disable();
899 +
900 + return 0;
901 +}
902 +
903 +int page_is_ram(unsigned long pagenr)
904 +{
905 + return 1;
906 +}
907 +
908 +const char *get_system_type(void)
909 +{
910 + return "MIPS IDT32434 - ARUBA";
911 +}
912 diff -Nur linux-2.6.16/arch/mips/aruba/time.c linux-2.6.16-owrt/arch/mips/aruba/time.c
913 --- linux-2.6.16/arch/mips/aruba/time.c 1970-01-01 01:00:00.000000000 +0100
914 +++ linux-2.6.16-owrt/arch/mips/aruba/time.c 2006-03-20 14:25:10.000000000 +0100
915 @@ -0,0 +1,108 @@
916 +/**************************************************************************
917 + *
918 + * BRIEF MODULE DESCRIPTION
919 + * timer routines for IDT EB434 boards
920 + *
921 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
922 + *
923 + * This program is free software; you can redistribute it and/or modify it
924 + * under the terms of the GNU General Public License as published by the
925 + * Free Software Foundation; either version 2 of the License, or (at your
926 + * option) any later version.
927 + *
928 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
929 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
930 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
931 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
932 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
933 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
934 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
935 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
936 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
937 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
938 + *
939 + * You should have received a copy of the GNU General Public License along
940 + * with this program; if not, write to the Free Software Foundation, Inc.,
941 + * 675 Mass Ave, Cambridge, MA 02139, USA.
942 + *
943 + *
944 + **************************************************************************
945 + * May 2004 rkt, neb
946 + *
947 + * Initial Release
948 + *
949 + *
950 + *
951 + **************************************************************************
952 + */
953 +
954 +#include <linux/config.h>
955 +#include <linux/init.h>
956 +#include <linux/kernel_stat.h>
957 +#include <linux/sched.h>
958 +#include <linux/spinlock.h>
959 +#include <linux/mc146818rtc.h>
960 +#include <linux/irq.h>
961 +#include <linux/timex.h>
962 +
963 +#include <linux/param.h>
964 +#include <asm/mipsregs.h>
965 +#include <asm/ptrace.h>
966 +#include <asm/time.h>
967 +#include <asm/hardirq.h>
968 +
969 +#include <asm/mipsregs.h>
970 +#include <asm/ptrace.h>
971 +#include <asm/debug.h>
972 +#include <asm/time.h>
973 +
974 +#include <asm/idt-boards/rc32434/rc32434.h>
975 +
976 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
977 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
978 +
979 +extern unsigned int idt_cpu_freq;
980 +
981 +static unsigned long __init cal_r4koff(void)
982 +{
983 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
984 + return (mips_hpt_frequency / HZ);
985 +}
986 +
987 +void __init aruba_time_init(void)
988 +{
989 + unsigned int est_freq, flags;
990 + local_irq_save(flags);
991 +
992 + printk("calculating r4koff... ");
993 + r4k_offset = cal_r4koff();
994 + printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
995 +
996 + est_freq = 2 * r4k_offset * HZ;
997 + est_freq += 5000; /* round */
998 + est_freq -= est_freq % 10000;
999 + printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
1000 + (est_freq % 1000000) * 100 / 1000000);
1001 + local_irq_restore(flags);
1002 +
1003 +}
1004 +
1005 +void __init aruba_timer_setup(struct irqaction *irq)
1006 +{
1007 + /* we are using the cpu counter for timer interrupts */
1008 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1009 +
1010 + /* to generate the first timer interrupt */
1011 + r4k_cur = (read_c0_count() + r4k_offset);
1012 + write_c0_compare(r4k_cur);
1013 +
1014 +}
1015 +
1016 +asmlinkage void aruba_timer_interrupt(int irq, struct pt_regs *regs)
1017 +{
1018 + irq_enter();
1019 + kstat_this_cpu.irqs[irq]++;
1020 +
1021 + timer_interrupt(irq, NULL, regs);
1022 + irq_exit();
1023 +}
1024 diff -Nur linux-2.6.16/arch/mips/aruba/wdt_merlot.c linux-2.6.16-owrt/arch/mips/aruba/wdt_merlot.c
1025 --- linux-2.6.16/arch/mips/aruba/wdt_merlot.c 1970-01-01 01:00:00.000000000 +0100
1026 +++ linux-2.6.16-owrt/arch/mips/aruba/wdt_merlot.c 2006-03-20 14:25:10.000000000 +0100
1027 @@ -0,0 +1,30 @@
1028 +#include <linux/config.h>
1029 +#include <linux/kernel.h>
1030 +#include <asm/bootinfo.h>
1031 +
1032 +void wdt_merlot_disable()
1033 +{
1034 + volatile __u32 *wdt_errcs;
1035 + volatile __u32 *wdt_wtc;
1036 + volatile __u32 *wdt_ctl;
1037 + volatile __u32 val;
1038 +
1039 + switch (mips_machtype) {
1040 + case MACH_ARUBA_AP70:
1041 + wdt_errcs = (__u32 *) 0xb8030030;
1042 + wdt_wtc = (__u32 *) 0xb803003c;
1043 + val = *wdt_errcs;
1044 + val &= ~0x201;
1045 + *wdt_errcs = val;
1046 + val = *wdt_wtc;
1047 + val &= ~0x1;
1048 + *wdt_wtc = val;
1049 + break;
1050 + case MACH_ARUBA_AP65:
1051 + case MACH_ARUBA_AP60:
1052 + default:
1053 + wdt_ctl = (__u32 *) 0xbc003008;
1054 + *wdt_ctl = 0;
1055 + break;
1056 + }
1057 +}
1058 diff -Nur linux-2.6.16/arch/mips/Kconfig linux-2.6.16-owrt/arch/mips/Kconfig
1059 --- linux-2.6.16/arch/mips/Kconfig 2006-03-20 06:53:29.000000000 +0100
1060 +++ linux-2.6.16-owrt/arch/mips/Kconfig 2006-03-20 14:25:10.000000000 +0100
1061 @@ -227,6 +227,17 @@
1062 either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
1063 a kernel for this platform.
1064
1065 +config MACH_ARUBA
1066 + bool "Support for the ARUBA product line"
1067 + select DMA_NONCOHERENT
1068 + select CPU_HAS_PREFETCH
1069 + select HW_HAS_PCI
1070 + select SWAP_IO_SPACE
1071 + select SYS_SUPPORTS_32BIT_KERNEL
1072 + select SYS_HAS_CPU_MIPS32_R1
1073 + select SYS_SUPPORTS_BIG_ENDIAN
1074 +
1075 +
1076 config MACH_JAZZ
1077 bool "Support for the Jazz family of machines"
1078 select ARC
1079 diff -Nur linux-2.6.16/arch/mips/Makefile linux-2.6.16-owrt/arch/mips/Makefile
1080 --- linux-2.6.16/arch/mips/Makefile 2006-03-20 06:53:29.000000000 +0100
1081 +++ linux-2.6.16-owrt/arch/mips/Makefile 2006-03-20 14:25:10.000000000 +0100
1082 @@ -279,6 +279,14 @@
1083 #
1084
1085 #
1086 +# Aruba
1087 +#
1088 +
1089 +core-$(CONFIG_MACH_ARUBA) += arch/mips/aruba/
1090 +cflags-$(CONFIG_MACH_ARUBA) += -Iinclude/asm-mips/aruba
1091 +load-$(CONFIG_MACH_ARUBA) += 0x80100000
1092 +
1093 +#
1094 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
1095 #
1096 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
1097 diff -Nur linux-2.6.16/arch/mips/mm/tlbex.c linux-2.6.16-owrt/arch/mips/mm/tlbex.c
1098 --- linux-2.6.16/arch/mips/mm/tlbex.c 2006-03-20 06:53:29.000000000 +0100
1099 +++ linux-2.6.16-owrt/arch/mips/mm/tlbex.c 2006-03-20 14:25:10.000000000 +0100
1100 @@ -852,7 +852,6 @@
1101
1102 case CPU_R10000:
1103 case CPU_R12000:
1104 - case CPU_4KC:
1105 case CPU_SB1:
1106 case CPU_SB1A:
1107 case CPU_4KSC:
1108 @@ -880,6 +879,7 @@
1109 tlbw(p);
1110 break;
1111
1112 + case CPU_4KC:
1113 case CPU_4KEC:
1114 case CPU_24K:
1115 case CPU_34K:
1116 diff -Nur linux-2.6.16/drivers/net/Kconfig linux-2.6.16-owrt/drivers/net/Kconfig
1117 --- linux-2.6.16/drivers/net/Kconfig 2006-03-20 06:53:29.000000000 +0100
1118 +++ linux-2.6.16-owrt/drivers/net/Kconfig 2006-03-20 14:25:10.000000000 +0100
1119 @@ -187,6 +187,13 @@
1120
1121 source "drivers/net/arm/Kconfig"
1122
1123 +config IDT_RC32434_ETH
1124 + tristate "IDT RC32434 Local Ethernet support"
1125 + depends on NET_ETHERNET
1126 + help
1127 + IDT RC32434 has one local ethernet port. Say Y here to enable it.
1128 + To compile this driver as a module, choose M here.
1129 +
1130 config MACE
1131 tristate "MACE (Power Mac ethernet) support"
1132 depends on NET_ETHERNET && PPC_PMAC && PPC32
1133 diff -Nur linux-2.6.16/drivers/net/Makefile linux-2.6.16-owrt/drivers/net/Makefile
1134 --- linux-2.6.16/drivers/net/Makefile 2006-03-20 06:53:29.000000000 +0100
1135 +++ linux-2.6.16-owrt/drivers/net/Makefile 2006-03-20 14:25:10.000000000 +0100
1136 @@ -38,6 +38,7 @@
1137
1138 obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
1139
1140 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
1141 obj-$(CONFIG_DGRS) += dgrs.o
1142 obj-$(CONFIG_VORTEX) += 3c59x.o
1143 obj-$(CONFIG_TYPHOON) += typhoon.o
1144 diff -Nur linux-2.6.16/drivers/net/natsemi.c linux-2.6.16-owrt/drivers/net/natsemi.c
1145 --- linux-2.6.16/drivers/net/natsemi.c 2006-03-20 06:53:29.000000000 +0100
1146 +++ linux-2.6.16-owrt/drivers/net/natsemi.c 2006-03-20 14:25:10.000000000 +0100
1147 @@ -771,6 +771,49 @@
1148 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
1149 static struct ethtool_ops ethtool_ops;
1150
1151 +#ifdef CONFIG_MACH_ARUBA
1152 +
1153 +#include <linux/ctype.h>
1154 +
1155 +#ifndef ERR
1156 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
1157 +#endif
1158 +
1159 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1160 +{
1161 + int i, j;
1162 + unsigned char result, value;
1163 +
1164 + for (i=0; i<6; i++) {
1165 + result = 0;
1166 + if (i != 5 && *(macstr+2) != ':') {
1167 + ERR("invalid mac address format: %d %c\n",
1168 + i, *(macstr+2));
1169 + return -EINVAL;
1170 + }
1171 + for (j=0; j<2; j++) {
1172 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1173 + toupper(*macstr)-'A'+10) < 16) {
1174 + result = result*16 + value;
1175 + macstr++;
1176 + }
1177 + else {
1178 + ERR("invalid mac address "
1179 + "character: %c\n", *macstr);
1180 + return -EINVAL;
1181 + }
1182 + }
1183 +
1184 + macstr++;
1185 + dev->dev_addr[i] = result;
1186 + }
1187 +
1188 + dev->dev_addr[5]++;
1189 + return 0;
1190 +}
1191 +
1192 +#endif
1193 +
1194 static inline void __iomem *ns_ioaddr(struct net_device *dev)
1195 {
1196 return (void __iomem *) dev->base_addr;
1197 @@ -859,6 +902,7 @@
1198 goto err_ioremap;
1199 }
1200
1201 +#ifndef CONFIG_MACH_ARUBA
1202 /* Work around the dropped serial bit. */
1203 prev_eedata = eeprom_read(ioaddr, 6);
1204 for (i = 0; i < 3; i++) {
1205 @@ -867,6 +911,19 @@
1206 dev->dev_addr[i*2+1] = eedata >> 7;
1207 prev_eedata = eedata;
1208 }
1209 +#else
1210 + {
1211 + char mac[32];
1212 + unsigned char def_mac[6] = {00, 0x0b, 0x86, 0xba, 0xdb, 0xad};
1213 + extern char *getenv(char *e);
1214 + memset(mac, 0, 32);
1215 + memcpy(mac, getenv("ethaddr"), 17);
1216 + if (parse_mac_addr(dev, mac)){
1217 + printk("%s: MAC address not found\n", __func__);
1218 + memcpy(dev->dev_addr, def_mac, 6);
1219 + }
1220 + }
1221 +#endif
1222
1223 dev->base_addr = (unsigned long __force) ioaddr;
1224 dev->irq = irq;
1225 diff -Nur linux-2.6.16/drivers/net/rc32434_eth.c linux-2.6.16-owrt/drivers/net/rc32434_eth.c
1226 --- linux-2.6.16/drivers/net/rc32434_eth.c 1970-01-01 01:00:00.000000000 +0100
1227 +++ linux-2.6.16-owrt/drivers/net/rc32434_eth.c 2006-03-20 14:25:10.000000000 +0100
1228 @@ -0,0 +1,1268 @@
1229 +/**************************************************************************
1230 + *
1231 + * BRIEF MODULE DESCRIPTION
1232 + * Driver for the IDT RC32434 on-chip ethernet controller.
1233 + *
1234 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1235 + *
1236 + * This program is free software; you can redistribute it and/or modify it
1237 + * under the terms of the GNU General Public License as published by the
1238 + * Free Software Foundation; either version 2 of the License, or (at your
1239 + * option) any later version.
1240 + *
1241 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1242 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1243 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1244 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1245 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1246 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1247 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1248 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1249 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1250 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1251 + *
1252 + * You should have received a copy of the GNU General Public License along
1253 + * with this program; if not, write to the Free Software Foundation, Inc.,
1254 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1255 + *
1256 + *
1257 + **************************************************************************
1258 + * May 2004 rkt, neb
1259 + *
1260 + * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
1261 + *
1262 + * Aug 2004 Sadik
1263 + *
1264 + * Added NAPI
1265 + *
1266 + **************************************************************************
1267 + */
1268 +
1269 +#include <linux/config.h>
1270 +#include <linux/module.h>
1271 +#include <linux/kernel.h>
1272 +#include <linux/moduleparam.h>
1273 +#include <linux/sched.h>
1274 +#include <linux/ctype.h>
1275 +#include <linux/types.h>
1276 +#include <linux/fcntl.h>
1277 +#include <linux/interrupt.h>
1278 +#include <linux/ptrace.h>
1279 +#include <linux/init.h>
1280 +#include <linux/ioport.h>
1281 +#include <linux/proc_fs.h>
1282 +#include <linux/in.h>
1283 +#include <linux/slab.h>
1284 +#include <linux/string.h>
1285 +#include <linux/delay.h>
1286 +#include <linux/netdevice.h>
1287 +#include <linux/etherdevice.h>
1288 +#include <linux/skbuff.h>
1289 +#include <linux/errno.h>
1290 +#include <asm/bootinfo.h>
1291 +#include <asm/system.h>
1292 +#include <asm/bitops.h>
1293 +#include <asm/pgtable.h>
1294 +#include <asm/segment.h>
1295 +#include <asm/io.h>
1296 +#include <asm/dma.h>
1297 +
1298 +#include "rc32434_eth.h"
1299 +
1300 +#define DRIVER_VERSION "(mar2904)"
1301 +
1302 +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
1303 +
1304 +
1305 +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
1306 + ((dev)->dev_addr[1]))
1307 +#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
1308 + ((dev)->dev_addr[3] << 16) | \
1309 + ((dev)->dev_addr[4] << 8) | \
1310 + ((dev)->dev_addr[5]))
1311 +
1312 +#define MII_CLOCK 1250000 /* no more than 2.5MHz */
1313 +static char mac0[18] = "08:00:06:05:40:01";
1314 +
1315 +MODULE_PARM(mac0, "c18");
1316 +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
1317 +
1318 +static struct rc32434_if_t {
1319 + char *name;
1320 + struct net_device *dev;
1321 + char* mac_str;
1322 + int weight;
1323 + u32 iobase;
1324 + u32 rxdmabase;
1325 + u32 txdmabase;
1326 + int rx_dma_irq;
1327 + int tx_dma_irq;
1328 + int rx_ovr_irq;
1329 + int tx_und_irq;
1330 +} rc32434_iflist[] =
1331 +{
1332 + {
1333 + "rc32434_eth0", NULL, mac0,
1334 + 64,
1335 + ETH0_PhysicalAddress,
1336 + ETH0_RX_DMA_ADDR,
1337 + ETH0_TX_DMA_ADDR,
1338 + ETH0_DMA_RX_IRQ,
1339 + ETH0_DMA_TX_IRQ,
1340 + ETH0_RX_OVR_IRQ,
1341 + ETH0_TX_UND_IRQ
1342 + }
1343 +};
1344 +
1345 +
1346 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1347 +{
1348 + int i, j;
1349 + unsigned char result, value;
1350 +
1351 + for (i=0; i<6; i++) {
1352 + result = 0;
1353 + if (i != 5 && *(macstr+2) != ':') {
1354 + ERR("invalid mac address format: %d %c\n",
1355 + i, *(macstr+2));
1356 + return -EINVAL;
1357 + }
1358 + for (j=0; j<2; j++) {
1359 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1360 + toupper(*macstr)-'A'+10) < 16) {
1361 + result = result*16 + value;
1362 + macstr++;
1363 + }
1364 + else {
1365 + ERR("invalid mac address "
1366 + "character: %c\n", *macstr);
1367 + return -EINVAL;
1368 + }
1369 + }
1370 +
1371 + macstr++;
1372 + dev->dev_addr[i] = result;
1373 + }
1374 +
1375 + return 0;
1376 +}
1377 +
1378 +
1379 +
1380 +static inline void rc32434_abort_tx(struct net_device *dev)
1381 +{
1382 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1383 + rc32434_abort_dma(dev, lp->tx_dma_regs);
1384 +
1385 +}
1386 +
1387 +static inline void rc32434_abort_rx(struct net_device *dev)
1388 +{
1389 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1390 + rc32434_abort_dma(dev, lp->rx_dma_regs);
1391 +
1392 +}
1393 +
1394 +static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td)
1395 +{
1396 + rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
1397 +}
1398 +
1399 +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1400 +{
1401 + rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1402 +}
1403 +
1404 +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
1405 +{
1406 + rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
1407 +}
1408 +
1409 +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1410 +{
1411 + rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1412 +}
1413 +
1414 +#ifdef RC32434_PROC_DEBUG
1415 +static int rc32434_read_proc(char *buf, char **start, off_t fpos,
1416 + int length, int *eof, void *data)
1417 +{
1418 + struct net_device *dev = (struct net_device *)data;
1419 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1420 + int len = 0;
1421 +
1422 + /* print out header */
1423 + len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
1424 + len += sprintf (buf + len,
1425 + "DMA halt count = %10d, DMA run count = %10d\n",
1426 + lp->dma_halt_cnt, lp->dma_run_cnt);
1427 +
1428 + if (fpos >= len) {
1429 + *start = buf;
1430 + *eof = 1;
1431 + return 0;
1432 + }
1433 + *start = buf + fpos;
1434 +
1435 + if ((len -= fpos) > length)
1436 + return length;
1437 + *eof = 1;
1438 +
1439 + return len;
1440 +
1441 +}
1442 +#endif
1443 +
1444 +
1445 +/*
1446 + * Restart the RC32434 ethernet controller.
1447 + */
1448 +static int rc32434_restart(struct net_device *dev)
1449 +{
1450 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1451 +
1452 + /*
1453 + * Disable interrupts
1454 + */
1455 + disable_irq(lp->rx_irq);
1456 + disable_irq(lp->tx_irq);
1457 +#ifdef RC32434_REVISION
1458 + disable_irq(lp->ovr_irq);
1459 +#endif
1460 + disable_irq(lp->und_irq);
1461 +
1462 + /* Mask F E bit in Tx DMA */
1463 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
1464 + /* Mask D H E bit in Rx DMA */
1465 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
1466 +
1467 + rc32434_init(dev);
1468 + rc32434_multicast_list(dev);
1469 +
1470 + enable_irq(lp->und_irq);
1471 +#ifdef RC32434_REVISION
1472 + enable_irq(lp->ovr_irq);
1473 +#endif
1474 + enable_irq(lp->tx_irq);
1475 + enable_irq(lp->rx_irq);
1476 +
1477 + return 0;
1478 +}
1479 +
1480 +int rc32434_init_module(void)
1481 +{
1482 +#ifdef CONFIG_MACH_ARUBA
1483 + if (mips_machtype != MACH_ARUBA_AP70)
1484 + return 1;
1485 +#endif
1486 +
1487 + printk(KERN_INFO DRIVER_NAME " \n");
1488 + return rc32434_probe(0);
1489 +}
1490 +
1491 +static int rc32434_probe(int port_num)
1492 +{
1493 + struct rc32434_if_t *bif = &rc32434_iflist[port_num];
1494 + struct rc32434_local *lp = NULL;
1495 + struct net_device *dev = NULL;
1496 + int i, retval,err;
1497 +
1498 + dev = alloc_etherdev(sizeof(struct rc32434_local));
1499 + if(!dev) {
1500 + ERR("rc32434_eth: alloc_etherdev failed\n");
1501 + return -1;
1502 + }
1503 +
1504 + SET_MODULE_OWNER(dev);
1505 + bif->dev = dev;
1506 +
1507 +#ifdef CONFIG_MACH_ARUBA
1508 + {
1509 + extern char * getenv(char *e);
1510 + memcpy(bif->mac_str, getenv("ethaddr"), 17);
1511 + }
1512 +#endif
1513 +
1514 + printk("mac: %s\n", bif->mac_str);
1515 + if ((retval = parse_mac_addr(dev, bif->mac_str))) {
1516 + ERR("MAC address parse failed\n");
1517 + free_netdev(dev);
1518 + return -1;
1519 + }
1520 +
1521 +
1522 + /* Initialize the device structure. */
1523 + if (dev->priv == NULL) {
1524 + lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
1525 + memset(lp, 0, sizeof(struct rc32434_local));
1526 + }
1527 + else {
1528 + lp = (struct rc32434_local *)dev->priv;
1529 + }
1530 +
1531 + lp->rx_irq = bif->rx_dma_irq;
1532 + lp->tx_irq = bif->tx_dma_irq;
1533 + lp->ovr_irq = bif->rx_ovr_irq;
1534 + lp->und_irq = bif->tx_und_irq;
1535 +
1536 + lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
1537 +
1538 + if (!lp->eth_regs) {
1539 + ERR("Can't remap eth registers\n");
1540 + retval = -ENXIO;
1541 + goto probe_err_out;
1542 + }
1543 +
1544 + lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
1545 +
1546 + if (!lp->rx_dma_regs) {
1547 + ERR("Can't remap Rx DMA registers\n");
1548 + retval = -ENXIO;
1549 + goto probe_err_out;
1550 + }
1551 + lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
1552 +
1553 + if (!lp->tx_dma_regs) {
1554 + ERR("Can't remap Tx DMA registers\n");
1555 + retval = -ENXIO;
1556 + goto probe_err_out;
1557 + }
1558 +
1559 +#ifdef RC32434_PROC_DEBUG
1560 + lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
1561 + rc32434_read_proc, dev);
1562 +#endif
1563 +
1564 + lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1565 + if (!lp->td_ring) {
1566 + ERR("Can't allocate descriptors\n");
1567 + retval = -ENOMEM;
1568 + goto probe_err_out;
1569 + }
1570 +
1571 + dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
1572 +
1573 + /* now convert TD_RING pointer to KSEG1 */
1574 + lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
1575 + lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
1576 +
1577 +
1578 + spin_lock_init(&lp->lock);
1579 +
1580 + dev->base_addr = bif->iobase;
1581 + /* just use the rx dma irq */
1582 + dev->irq = bif->rx_dma_irq;
1583 +
1584 + dev->priv = lp;
1585 +
1586 + dev->open = rc32434_open;
1587 + dev->stop = rc32434_close;
1588 + dev->hard_start_xmit = rc32434_send_packet;
1589 + dev->get_stats = rc32434_get_stats;
1590 + dev->set_multicast_list = &rc32434_multicast_list;
1591 + dev->tx_timeout = rc32434_tx_timeout;
1592 + dev->watchdog_timeo = RC32434_TX_TIMEOUT;
1593 +
1594 +#ifdef CONFIG_IDT_USE_NAPI
1595 + dev->poll = rc32434_poll;
1596 + dev->weight = bif->weight;
1597 + printk("Using NAPI with weight %d\n",dev->weight);
1598 +#else
1599 + lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1600 + tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
1601 +#endif
1602 + lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1603 + tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
1604 +
1605 + if ((err = register_netdev(dev))) {
1606 + printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
1607 + free_netdev(dev);
1608 + retval = -EINVAL;
1609 + goto probe_err_out;
1610 + }
1611 +
1612 + INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
1613 + for (i = 0; i < 6; i++) {
1614 + printk("%2.2x", dev->dev_addr[i]);
1615 + if (i<5)
1616 + printk(":");
1617 + }
1618 + printk("\n");
1619 +
1620 + return 0;
1621 +
1622 + probe_err_out:
1623 + rc32434_cleanup_module();
1624 + ERR(" failed. Returns %d\n", retval);
1625 + return retval;
1626 +
1627 +}
1628 +
1629 +
1630 +static void rc32434_cleanup_module(void)
1631 +{
1632 + int i;
1633 +
1634 + for (i = 0; rc32434_iflist[i].iobase; i++) {
1635 + struct rc32434_if_t * bif = &rc32434_iflist[i];
1636 + if (bif->dev != NULL) {
1637 + struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
1638 + if (lp != NULL) {
1639 + if (lp->eth_regs)
1640 + iounmap((void*)lp->eth_regs);
1641 + if (lp->rx_dma_regs)
1642 + iounmap((void*)lp->rx_dma_regs);
1643 + if (lp->tx_dma_regs)
1644 + iounmap((void*)lp->tx_dma_regs);
1645 + if (lp->td_ring)
1646 + kfree((void*)KSEG0ADDR(lp->td_ring));
1647 +
1648 +#ifdef RC32434_PROC_DEBUG
1649 + if (lp->ps) {
1650 + remove_proc_entry(bif->name, proc_net);
1651 + }
1652 +#endif
1653 + kfree(lp);
1654 + }
1655 +
1656 + unregister_netdev(bif->dev);
1657 + free_netdev(bif->dev);
1658 + kfree(bif->dev);
1659 + }
1660 + }
1661 +}
1662 +
1663 +
1664 +
1665 +static int rc32434_open(struct net_device *dev)
1666 +{
1667 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1668 +
1669 + /* Initialize */
1670 + if (rc32434_init(dev)) {
1671 + ERR("Error: cannot open the Ethernet device\n");
1672 + return -EAGAIN;
1673 + }
1674 +
1675 + /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
1676 + if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
1677 + SA_SHIRQ | SA_INTERRUPT,
1678 + "rc32434 ethernet Rx", dev)) {
1679 + ERR(": unable to get Rx DMA IRQ %d\n",
1680 + lp->rx_irq);
1681 + return -EAGAIN;
1682 + }
1683 + if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
1684 + SA_SHIRQ | SA_INTERRUPT,
1685 + "rc32434 ethernet Tx", dev)) {
1686 + ERR(": unable to get Tx DMA IRQ %d\n",
1687 + lp->tx_irq);
1688 + free_irq(lp->rx_irq, dev);
1689 + return -EAGAIN;
1690 + }
1691 +
1692 +#ifdef RC32434_REVISION
1693 + /* Install handler for overrun error. */
1694 + if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
1695 + SA_SHIRQ | SA_INTERRUPT,
1696 + "Ethernet Overflow", dev)) {
1697 + ERR(": unable to get OVR IRQ %d\n",
1698 + lp->ovr_irq);
1699 + free_irq(lp->rx_irq, dev);
1700 + free_irq(lp->tx_irq, dev);
1701 + return -EAGAIN;
1702 + }
1703 +#endif
1704 +
1705 + /* Install handler for underflow error. */
1706 + if (request_irq(lp->und_irq, &rc32434_und_interrupt,
1707 + SA_SHIRQ | SA_INTERRUPT,
1708 + "Ethernet Underflow", dev)) {
1709 + ERR(": unable to get UND IRQ %d\n",
1710 + lp->und_irq);
1711 + free_irq(lp->rx_irq, dev);
1712 + free_irq(lp->tx_irq, dev);
1713 +#ifdef RC32434_REVISION
1714 + free_irq(lp->ovr_irq, dev);
1715 +#endif
1716 + return -EAGAIN;
1717 + }
1718 +
1719 +
1720 + return 0;
1721 +}
1722 +
1723 +
1724 +
1725 +
1726 +static int rc32434_close(struct net_device *dev)
1727 +{
1728 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1729 + u32 tmp;
1730 +
1731 + /* Disable interrupts */
1732 + disable_irq(lp->rx_irq);
1733 + disable_irq(lp->tx_irq);
1734 +#ifdef RC32434_REVISION
1735 + disable_irq(lp->ovr_irq);
1736 +#endif
1737 + disable_irq(lp->und_irq);
1738 +
1739 + tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
1740 + tmp = tmp | DMASM_f_m | DMASM_e_m;
1741 + rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
1742 +
1743 + tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
1744 + tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
1745 + rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
1746 +
1747 + free_irq(lp->rx_irq, dev);
1748 + free_irq(lp->tx_irq, dev);
1749 +#ifdef RC32434_REVISION
1750 + free_irq(lp->ovr_irq, dev);
1751 +#endif
1752 + free_irq(lp->und_irq, dev);
1753 + return 0;
1754 +}
1755 +
1756 +
1757 +/* transmit packet */
1758 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
1759 +{
1760 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1761 + unsigned long flags;
1762 + u32 length;
1763 + DMAD_t td;
1764 +
1765 +
1766 + spin_lock_irqsave(&lp->lock, flags);
1767 +
1768 + td = &lp->td_ring[lp->tx_chain_tail];
1769 +
1770 + /* stop queue when full, drop pkts if queue already full */
1771 + if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
1772 + lp->tx_full = 1;
1773 +
1774 + if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
1775 + netif_stop_queue(dev);
1776 + }
1777 + else {
1778 + lp->stats.tx_dropped++;
1779 + dev_kfree_skb_any(skb);
1780 + spin_unlock_irqrestore(&lp->lock, flags);
1781 + return 1;
1782 + }
1783 + }
1784 +
1785 + lp->tx_count ++;
1786 +
1787 + lp->tx_skb[lp->tx_chain_tail] = skb;
1788 +
1789 + length = skb->len;
1790 +
1791 + /* Setup the transmit descriptor. */
1792 + td->ca = CPHYSADDR(skb->data);
1793 +
1794 + if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
1795 + if( lp->tx_chain_status == empty ) {
1796 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1797 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1798 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1799 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1800 + }
1801 + else {
1802 + td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */
1803 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1804 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1805 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1806 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1807 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1808 + lp->tx_chain_status = empty;
1809 + }
1810 + }
1811 + else {
1812 + if( lp->tx_chain_status == empty ) {
1813 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1814 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1815 + lp->tx_chain_status = filled;
1816 + }
1817 + else {
1818 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1819 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1820 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1821 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1822 + }
1823 + }
1824 +
1825 + dev->trans_start = jiffies;
1826 +
1827 + spin_unlock_irqrestore(&lp->lock, flags);
1828 +
1829 + return 0;
1830 +}
1831 +
1832 +
1833 +/* Ethernet MII-PHY Handler */
1834 +static void rc32434_mii_handler(unsigned long data)
1835 +{
1836 + struct net_device *dev = (struct net_device *)data;
1837 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1838 + unsigned long flags;
1839 + unsigned long duplex_status;
1840 + int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
1841 +
1842 + spin_lock_irqsave(&lp->lock, flags);
1843 +
1844 + /* Two ports are using the same MII, the difference is the PHY address */
1845 + rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
1846 + rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
1847 + rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
1848 + rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
1849 + while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
1850 +
1851 + ERR("irq:%x port_addr:%x RDD:%x\n",
1852 + lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
1853 + duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
1854 + if(duplex_status != lp->duplex_mode) {
1855 + ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
1856 + lp->duplex_mode = duplex_status;
1857 + rc32434_restart(dev);
1858 + }
1859 +
1860 + lp->mii_phy_timer.expires = jiffies + 10 * HZ;
1861 + add_timer(&lp->mii_phy_timer);
1862 +
1863 + spin_unlock_irqrestore(&lp->lock, flags);
1864 +
1865 +}
1866 +
1867 +#ifdef RC32434_REVISION
1868 +/* Ethernet Rx Overflow interrupt */
1869 +static irqreturn_t
1870 +rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1871 +{
1872 + struct net_device *dev = (struct net_device *)dev_id;
1873 + struct rc32434_local *lp;
1874 + unsigned int ovr;
1875 + irqreturn_t retval = IRQ_NONE;
1876 +
1877 + ASSERT(dev != NULL);
1878 +
1879 + lp = (struct rc32434_local *)dev->priv;
1880 + spin_lock(&lp->lock);
1881 + ovr = rc32434_readl(&lp->eth_regs->ethintfc);
1882 +
1883 + if(ovr & ETHINTFC_ovr_m) {
1884 + netif_stop_queue(dev);
1885 +
1886 + /* clear OVR bit */
1887 + rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
1888 +
1889 + /* Restart interface */
1890 + rc32434_restart(dev);
1891 + retval = IRQ_HANDLED;
1892 + }
1893 + spin_unlock(&lp->lock);
1894 +
1895 + return retval;
1896 +}
1897 +
1898 +#endif
1899 +
1900 +
1901 +/* Ethernet Tx Underflow interrupt */
1902 +static irqreturn_t
1903 +rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1904 +{
1905 + struct net_device *dev = (struct net_device *)dev_id;
1906 + struct rc32434_local *lp;
1907 + unsigned int und;
1908 + irqreturn_t retval = IRQ_NONE;
1909 +
1910 + ASSERT(dev != NULL);
1911 +
1912 + lp = (struct rc32434_local *)dev->priv;
1913 +
1914 + spin_lock(&lp->lock);
1915 +
1916 + und = rc32434_readl(&lp->eth_regs->ethintfc);
1917 +
1918 + if(und & ETHINTFC_und_m) {
1919 + netif_stop_queue(dev);
1920 +
1921 + rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
1922 +
1923 + /* Restart interface */
1924 + rc32434_restart(dev);
1925 + retval = IRQ_HANDLED;
1926 + }
1927 +
1928 + spin_unlock(&lp->lock);
1929 +
1930 + return retval;
1931 +}
1932 +
1933 +
1934 +/* Ethernet Rx DMA interrupt */
1935 +static irqreturn_t
1936 +rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1937 +{
1938 + struct net_device *dev = (struct net_device *)dev_id;
1939 + struct rc32434_local* lp;
1940 + volatile u32 dmas,dmasm;
1941 + irqreturn_t retval;
1942 +
1943 + ASSERT(dev != NULL);
1944 +
1945 + lp = (struct rc32434_local *)dev->priv;
1946 +
1947 + spin_lock(&lp->lock);
1948 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
1949 + if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
1950 + /* Mask D H E bit in Rx DMA */
1951 + dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
1952 + rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
1953 +#ifdef CONFIG_IDT_USE_NAPI
1954 + if(netif_rx_schedule_prep(dev))
1955 + __netif_rx_schedule(dev);
1956 +#else
1957 + tasklet_hi_schedule(lp->rx_tasklet);
1958 +#endif
1959 +
1960 + if (dmas & DMAS_e_m)
1961 + ERR(": DMA error\n");
1962 +
1963 + retval = IRQ_HANDLED;
1964 + }
1965 + else
1966 + retval = IRQ_NONE;
1967 +
1968 + spin_unlock(&lp->lock);
1969 + return retval;
1970 +}
1971 +
1972 +#ifdef CONFIG_IDT_USE_NAPI
1973 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
1974 +#else
1975 +static void rc32434_rx_tasklet(unsigned long rx_data_dev)
1976 +#endif
1977 +{
1978 + struct net_device *dev = (struct net_device *)rx_data_dev;
1979 + struct rc32434_local* lp = netdev_priv(dev);
1980 + volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done];
1981 + struct sk_buff *skb, *skb_new;
1982 + u8* pkt_buf;
1983 + u32 devcs, count, pkt_len, pktuncrc_len;
1984 + volatile u32 dmas;
1985 +#ifdef CONFIG_IDT_USE_NAPI
1986 + u32 received = 0;
1987 + int rx_work_limit = min(*budget,dev->quota);
1988 +#else
1989 + unsigned long flags;
1990 + spin_lock_irqsave(&lp->lock, flags);
1991 +#endif
1992 +
1993 + while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
1994 +#ifdef CONFIG_IDT_USE_NAPI
1995 + if(--rx_work_limit <0)
1996 + {
1997 + break;
1998 + }
1999 +#endif
2000 + /* init the var. used for the later operations within the while loop */
2001 + skb_new = NULL;
2002 + devcs = rd->devcs;
2003 + pkt_len = RCVPKT_LENGTH(devcs);
2004 + skb = lp->rx_skb[lp->rx_next_done];
2005 +
2006 + if (count < 64) {
2007 + lp->stats.rx_errors++;
2008 + lp->stats.rx_dropped++;
2009 + }
2010 + else if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) {
2011 + /* check that this is a whole packet */
2012 + /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
2013 + lp->stats.rx_errors++;
2014 + lp->stats.rx_dropped++;
2015 + }
2016 + else if ( (devcs & ETHRX_rok_m) ) {
2017 +
2018 + {
2019 + /* must be the (first and) last descriptor then */
2020 + pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
2021 +
2022 + pktuncrc_len = pkt_len - 4;
2023 + /* invalidate the cache */
2024 + dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
2025 +
2026 + /* Malloc up new buffer. */
2027 + skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
2028 +
2029 + if (skb_new != NULL){
2030 + /* Make room */
2031 + skb_put(skb, pktuncrc_len);
2032 +
2033 + skb->protocol = eth_type_trans(skb, dev);
2034 +
2035 + /* pass the packet to upper layers */
2036 +#ifdef CONFIG_IDT_USE_NAPI
2037 + netif_receive_skb(skb);
2038 +#else
2039 + netif_rx(skb);
2040 +#endif
2041 +
2042 + dev->last_rx = jiffies;
2043 + lp->stats.rx_packets++;
2044 + lp->stats.rx_bytes += pktuncrc_len;
2045 +
2046 + if (IS_RCV_MP(devcs))
2047 + lp->stats.multicast++;
2048 +
2049 + /* 16 bit align */
2050 + skb_reserve(skb_new, 2);
2051 +
2052 + skb_new->dev = dev;
2053 + lp->rx_skb[lp->rx_next_done] = skb_new;
2054 + }
2055 + else {
2056 + ERR("no memory, dropping rx packet.\n");
2057 + lp->stats.rx_errors++;
2058 + lp->stats.rx_dropped++;
2059 + }
2060 + }
2061 +
2062 + }
2063 + else {
2064 + /* This should only happen if we enable accepting broken packets */
2065 + lp->stats.rx_errors++;
2066 + lp->stats.rx_dropped++;
2067 +
2068 + /* add statistics counters */
2069 + if (IS_RCV_CRC_ERR(devcs)) {
2070 + DBG(2, "RX CRC error\n");
2071 + lp->stats.rx_crc_errors++;
2072 + }
2073 + else if (IS_RCV_LOR_ERR(devcs)) {
2074 + DBG(2, "RX LOR error\n");
2075 + lp->stats.rx_length_errors++;
2076 + }
2077 + else if (IS_RCV_LE_ERR(devcs)) {
2078 + DBG(2, "RX LE error\n");
2079 + lp->stats.rx_length_errors++;
2080 + }
2081 + else if (IS_RCV_OVR_ERR(devcs)) {
2082 + lp->stats.rx_over_errors++;
2083 + }
2084 + else if (IS_RCV_CV_ERR(devcs)) {
2085 + /* code violation */
2086 + DBG(2, "RX CV error\n");
2087 + lp->stats.rx_frame_errors++;
2088 + }
2089 + else if (IS_RCV_CES_ERR(devcs)) {
2090 + DBG(2, "RX Preamble error\n");
2091 + }
2092 + }
2093 +
2094 + rd->devcs = 0;
2095 +
2096 + /* restore descriptor's curr_addr */
2097 + if(skb_new)
2098 + rd->ca = CPHYSADDR(skb_new->data);
2099 + else
2100 + rd->ca = CPHYSADDR(skb->data);
2101 +
2102 + rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
2103 + lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m);
2104 +
2105 + lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
2106 + rd = &lp->rd_ring[lp->rx_next_done];
2107 + rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
2108 + }
2109 +#ifdef CONFIG_IDT_USE_NAPI
2110 + dev->quota -= received;
2111 + *budget =- received;
2112 + if(rx_work_limit < 0)
2113 + goto not_done;
2114 +#endif
2115 +
2116 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
2117 +
2118 + if(dmas & DMAS_h_m) {
2119 + rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
2120 +#ifdef RC32434_PROC_DEBUG
2121 + lp->dma_halt_cnt++;
2122 +#endif
2123 + rd->devcs = 0;
2124 + skb = lp->rx_skb[lp->rx_next_done];
2125 + rd->ca = CPHYSADDR(skb->data);
2126 + rc32434_chain_rx(lp,rd);
2127 + }
2128 +
2129 +#ifdef CONFIG_IDT_USE_NAPI
2130 + netif_rx_complete(dev);
2131 +#endif
2132 + /* Enable D H E bit in Rx DMA */
2133 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
2134 +#ifdef CONFIG_IDT_USE_NAPI
2135 + return 0;
2136 + not_done:
2137 + return 1;
2138 +#else
2139 + spin_unlock_irqrestore(&lp->lock, flags);
2140 + return;
2141 +#endif
2142 +
2143 +
2144 +}
2145 +
2146 +
2147 +
2148 +/* Ethernet Tx DMA interrupt */
2149 +static irqreturn_t
2150 +rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2151 +{
2152 + struct net_device *dev = (struct net_device *)dev_id;
2153 + struct rc32434_local *lp;
2154 + volatile u32 dmas,dmasm;
2155 + irqreturn_t retval;
2156 +
2157 + ASSERT(dev != NULL);
2158 +
2159 + lp = (struct rc32434_local *)dev->priv;
2160 +
2161 + spin_lock(&lp->lock);
2162 +
2163 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2164 +
2165 + if (dmas & (DMAS_f_m | DMAS_e_m)) {
2166 + dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
2167 + /* Mask F E bit in Tx DMA */
2168 + rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2169 +
2170 + tasklet_hi_schedule(lp->tx_tasklet);
2171 +
2172 + if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
2173 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
2174 + lp->tx_chain_status = empty;
2175 + lp->tx_chain_head = lp->tx_chain_tail;
2176 + dev->trans_start = jiffies;
2177 + }
2178 +
2179 + if (dmas & DMAS_e_m)
2180 + ERR(": DMA error\n");
2181 +
2182 + retval = IRQ_HANDLED;
2183 + }
2184 + else
2185 + retval = IRQ_NONE;
2186 +
2187 + spin_unlock(&lp->lock);
2188 +
2189 + return retval;
2190 +}
2191 +
2192 +
2193 +static void rc32434_tx_tasklet(unsigned long tx_data_dev)
2194 +{
2195 + struct net_device *dev = (struct net_device *)tx_data_dev;
2196 + struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
2197 + volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
2198 + u32 devcs;
2199 + unsigned long flags;
2200 + volatile u32 dmas;
2201 +
2202 + spin_lock_irqsave(&lp->lock, flags);
2203 +
2204 + /* process all desc that are done */
2205 + while(IS_DMA_FINISHED(td->control)) {
2206 + if(lp->tx_full == 1) {
2207 + netif_wake_queue(dev);
2208 + lp->tx_full = 0;
2209 + }
2210 +
2211 + devcs = lp->td_ring[lp->tx_next_done].devcs;
2212 + if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
2213 + lp->stats.tx_errors++;
2214 + lp->stats.tx_dropped++;
2215 +
2216 + /* should never happen */
2217 + DBG(1, __FUNCTION__ ": split tx ignored\n");
2218 + }
2219 + else if (IS_TX_TOK(devcs)) {
2220 + lp->stats.tx_packets++;
2221 + }
2222 + else {
2223 + lp->stats.tx_errors++;
2224 + lp->stats.tx_dropped++;
2225 +
2226 + /* underflow */
2227 + if (IS_TX_UND_ERR(devcs))
2228 + lp->stats.tx_fifo_errors++;
2229 +
2230 + /* oversized frame */
2231 + if (IS_TX_OF_ERR(devcs))
2232 + lp->stats.tx_aborted_errors++;
2233 +
2234 + /* excessive deferrals */
2235 + if (IS_TX_ED_ERR(devcs))
2236 + lp->stats.tx_carrier_errors++;
2237 +
2238 + /* collisions: medium busy */
2239 + if (IS_TX_EC_ERR(devcs))
2240 + lp->stats.collisions++;
2241 +
2242 + /* late collision */
2243 + if (IS_TX_LC_ERR(devcs))
2244 + lp->stats.tx_window_errors++;
2245 +
2246 + }
2247 +
2248 + /* We must always free the original skb */
2249 + if (lp->tx_skb[lp->tx_next_done] != NULL) {
2250 + dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
2251 + lp->tx_skb[lp->tx_next_done] = NULL;
2252 + }
2253 +
2254 + lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
2255 + lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
2256 + lp->td_ring[lp->tx_next_done].link = 0;
2257 + lp->td_ring[lp->tx_next_done].ca = 0;
2258 + lp->tx_count --;
2259 +
2260 + /* go on to next transmission */
2261 + lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
2262 + td = &lp->td_ring[lp->tx_next_done];
2263 +
2264 + }
2265 +
2266 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2267 + rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
2268 +
2269 + /* Enable F E bit in Tx DMA */
2270 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2271 + spin_unlock_irqrestore(&lp->lock, flags);
2272 +
2273 +}
2274 +
2275 +
2276 +static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
2277 +{
2278 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2279 + return &lp->stats;
2280 +}
2281 +
2282 +
2283 +/*
2284 + * Set or clear the multicast filter for this adaptor.
2285 + */
2286 +static void rc32434_multicast_list(struct net_device *dev)
2287 +{
2288 + /* listen to broadcasts always and to treat */
2289 + /* IFF bits independantly */
2290 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2291 + unsigned long flags;
2292 + u32 recognise = ETHARC_ab_m; /* always accept broadcasts */
2293 +
2294 + if (dev->flags & IFF_PROMISC) /* set promiscuous mode */
2295 + recognise |= ETHARC_pro_m;
2296 +
2297 + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
2298 + recognise |= ETHARC_am_m; /* all multicast & bcast */
2299 + else if (dev->mc_count > 0) {
2300 + DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
2301 + recognise |= ETHARC_am_m; /* for the time being */
2302 + }
2303 +
2304 + spin_lock_irqsave(&lp->lock, flags);
2305 + rc32434_writel(recognise, &lp->eth_regs->etharc);
2306 + spin_unlock_irqrestore(&lp->lock, flags);
2307 +}
2308 +
2309 +
2310 +static void rc32434_tx_timeout(struct net_device *dev)
2311 +{
2312 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2313 + unsigned long flags;
2314 +
2315 + spin_lock_irqsave(&lp->lock, flags);
2316 + rc32434_restart(dev);
2317 + spin_unlock_irqrestore(&lp->lock, flags);
2318 +
2319 +}
2320 +
2321 +
2322 +/*
2323 + * Initialize the RC32434 ethernet controller.
2324 + */
2325 +static int rc32434_init(struct net_device *dev)
2326 +{
2327 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2328 + int i, j;
2329 +
2330 + /* Disable DMA */
2331 + rc32434_abort_tx(dev);
2332 + rc32434_abort_rx(dev);
2333 +
2334 + /* reset ethernet logic */
2335 + rc32434_writel(0, &lp->eth_regs->ethintfc);
2336 + while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
2337 + dev->trans_start = jiffies;
2338 +
2339 + /* Enable Ethernet Interface */
2340 + rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
2341 +
2342 +#ifndef CONFIG_IDT_USE_NAPI
2343 + tasklet_disable(lp->rx_tasklet);
2344 +#endif
2345 + tasklet_disable(lp->tx_tasklet);
2346 +
2347 + /* Initialize the transmit Descriptors */
2348 + for (i = 0; i < RC32434_NUM_TDS; i++) {
2349 + lp->td_ring[i].control = DMAD_iof_m;
2350 + lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
2351 + lp->td_ring[i].ca = 0;
2352 + lp->td_ring[i].link = 0;
2353 + if (lp->tx_skb[i] != NULL) {
2354 + dev_kfree_skb_any(lp->tx_skb[i]);
2355 + lp->tx_skb[i] = NULL;
2356 + }
2357 + }
2358 + lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0;
2359 + lp-> tx_chain_status = empty;
2360 +
2361 + /*
2362 + * Initialize the receive descriptors so that they
2363 + * become a circular linked list, ie. let the last
2364 + * descriptor point to the first again.
2365 + */
2366 + for (i=0; i<RC32434_NUM_RDS; i++) {
2367 + struct sk_buff *skb = lp->rx_skb[i];
2368 +
2369 + if (lp->rx_skb[i] == NULL) {
2370 + skb = dev_alloc_skb(RC32434_RBSIZE + 2);
2371 + if (skb == NULL) {
2372 + ERR("No memory in the system\n");
2373 + for (j = 0; j < RC32434_NUM_RDS; j ++)
2374 + if (lp->rx_skb[j] != NULL)
2375 + dev_kfree_skb_any(lp->rx_skb[j]);
2376 +
2377 + return 1;
2378 + }
2379 + else {
2380 + skb->dev = dev;
2381 + skb_reserve(skb, 2);
2382 + lp->rx_skb[i] = skb;
2383 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2384 +
2385 + }
2386 + }
2387 + lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
2388 + lp->rd_ring[i].devcs = 0;
2389 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2390 + lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
2391 +
2392 + }
2393 + /* loop back */
2394 + lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
2395 + lp->rx_next_done = 0;
2396 +
2397 + lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
2398 + lp->rx_chain_head = 0;
2399 + lp->rx_chain_tail = 0;
2400 + lp->rx_chain_status = empty;
2401 +
2402 + rc32434_writel(0, &lp->rx_dma_regs->dmas);
2403 + /* Start Rx DMA */
2404 + rc32434_start_rx(lp, &lp->rd_ring[0]);
2405 +
2406 + /* Enable F E bit in Tx DMA */
2407 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2408 + /* Enable D H E bit in Rx DMA */
2409 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
2410 +
2411 + /* Accept only packets destined for this Ethernet device address */
2412 + rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
2413 +
2414 + /* Set all Ether station address registers to their initial values */
2415 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
2416 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
2417 +
2418 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
2419 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
2420 +
2421 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
2422 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
2423 +
2424 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
2425 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
2426 +
2427 +
2428 + /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
2429 + rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
2430 + //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode
2431 +
2432 + /* Back to back inter-packet-gap */
2433 + rc32434_writel(0x15, &lp->eth_regs->ethipgt);
2434 + /* Non - Back to back inter-packet-gap */
2435 + rc32434_writel(0x12, &lp->eth_regs->ethipgr);
2436 +
2437 + /* Management Clock Prescaler Divisor */
2438 + /* Clock independent setting */
2439 + rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
2440 + &lp->eth_regs->ethmcp);
2441 +
2442 + /* don't transmit until fifo contains 48b */
2443 + rc32434_writel(48, &lp->eth_regs->ethfifott);
2444 +
2445 + rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
2446 +
2447 +#ifndef CONFIG_IDT_USE_NAPI
2448 + tasklet_enable(lp->rx_tasklet);
2449 +#endif
2450 + tasklet_enable(lp->tx_tasklet);
2451 +
2452 + netif_start_queue(dev);
2453 +
2454 +
2455 + return 0;
2456 +
2457 +}
2458 +
2459 +
2460 +#ifndef MODULE
2461 +
2462 +static int __init rc32434_setup(char *options)
2463 +{
2464 + /* no options yet */
2465 + return 1;
2466 +}
2467 +
2468 +static int __init rc32434_setup_ethaddr0(char *options)
2469 +{
2470 + memcpy(mac0, options, 17);
2471 + mac0[17]= '\0';
2472 + return 1;
2473 +}
2474 +
2475 +__setup("rc32434eth=", rc32434_setup);
2476 +__setup("ethaddr0=", rc32434_setup_ethaddr0);
2477 +
2478 +
2479 +#endif /* MODULE */
2480 +
2481 +module_init(rc32434_init_module);
2482 +module_exit(rc32434_cleanup_module);
2483 +
2484 +
2485 +
2486 +
2487 +
2488 +
2489 +
2490 +
2491 +
2492 +
2493 +
2494 +
2495 +
2496 +
2497 diff -Nur linux-2.6.16/drivers/net/rc32434_eth.h linux-2.6.16-owrt/drivers/net/rc32434_eth.h
2498 --- linux-2.6.16/drivers/net/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
2499 +++ linux-2.6.16-owrt/drivers/net/rc32434_eth.h 2006-03-20 14:25:10.000000000 +0100
2500 @@ -0,0 +1,187 @@
2501 +/**************************************************************************
2502 + *
2503 + * BRIEF MODULE DESCRIPTION
2504 + * Definitions for IDT RC32434 on-chip ethernet controller.
2505 + *
2506 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2507 + *
2508 + * This program is free software; you can redistribute it and/or modify it
2509 + * under the terms of the GNU General Public License as published by the
2510 + * Free Software Foundation; either version 2 of the License, or (at your
2511 + * option) any later version.
2512 + *
2513 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2514 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2515 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2516 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2517 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2518 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2519 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2520 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2521 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2522 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2523 + *
2524 + * You should have received a copy of the GNU General Public License along
2525 + * with this program; if not, write to the Free Software Foundation, Inc.,
2526 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2527 + *
2528 + *
2529 + **************************************************************************
2530 + * May 2004 rkt, neb
2531 + *
2532 + * Initial Release
2533 + *
2534 + * Aug 2004
2535 + *
2536 + * Added NAPI
2537 + *
2538 + **************************************************************************
2539 + */
2540 +
2541 +
2542 +#include <asm/idt-boards/rc32434/rc32434.h>
2543 +#include <asm/idt-boards/rc32434/rc32434_dma_v.h>
2544 +#include <asm/idt-boards/rc32434/rc32434_eth_v.h>
2545 +
2546 +#define RC32434_DEBUG 2
2547 +//#define RC32434_PROC_DEBUG
2548 +#undef RC32434_DEBUG
2549 +
2550 +#ifdef RC32434_DEBUG
2551 +
2552 +/* use 0 for production, 1 for verification, >2 for debug */
2553 +static int rc32434_debug = RC32434_DEBUG;
2554 +#define ASSERT(expr) \
2555 + if(!(expr)) { \
2556 + printk( "Assertion failed! %s,%s,%s,line=%d\n", \
2557 + #expr,__FILE__,__FUNCTION__,__LINE__); }
2558 +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2559 +#else
2560 +#define ASSERT(expr) do {} while (0)
2561 +#define DBG(lvl, format, arg...) do {} while (0)
2562 +#endif
2563 +
2564 +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2565 +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
2566 +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
2567 +
2568 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
2569 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
2570 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
2571 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
2572 +
2573 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
2574 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
2575 +
2576 +/* the following must be powers of two */
2577 +#ifdef CONFIG_IDT_USE_NAPI
2578 +#define RC32434_NUM_RDS 64 /* number of receive descriptors */
2579 +#define RC32434_NUM_TDS 64 /* number of transmit descriptors */
2580 +#else
2581 +#define RC32434_NUM_RDS 128 /* number of receive descriptors */
2582 +#define RC32434_NUM_TDS 128 /* number of transmit descriptors */
2583 +#endif
2584 +
2585 +#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
2586 +#define RC32434_RDS_MASK (RC32434_NUM_RDS-1)
2587 +#define RC32434_TDS_MASK (RC32434_NUM_TDS-1)
2588 +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
2589 +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
2590 +
2591 +#define RC32434_TX_TIMEOUT HZ * 100
2592 +
2593 +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
2594 +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
2595 +
2596 +enum status { filled, empty};
2597 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
2598 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
2599 +
2600 +
2601 +/* Information that need to be kept for each board. */
2602 +struct rc32434_local {
2603 + ETH_t eth_regs;
2604 + DMA_Chan_t rx_dma_regs;
2605 + DMA_Chan_t tx_dma_regs;
2606 + volatile DMAD_t td_ring; /* transmit descriptor ring */
2607 + volatile DMAD_t rd_ring; /* receive descriptor ring */
2608 +
2609 + struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */
2610 + struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */
2611 +
2612 +#ifndef CONFIG_IDT_USE_NAPI
2613 + struct tasklet_struct * rx_tasklet;
2614 +#endif
2615 + struct tasklet_struct * tx_tasklet;
2616 +
2617 + int rx_next_done;
2618 + int rx_chain_head;
2619 + int rx_chain_tail;
2620 + enum status rx_chain_status;
2621 +
2622 + int tx_next_done;
2623 + int tx_chain_head;
2624 + int tx_chain_tail;
2625 + enum status tx_chain_status;
2626 + int tx_count;
2627 + int tx_full;
2628 +
2629 + struct timer_list mii_phy_timer;
2630 + unsigned long duplex_mode;
2631 +
2632 + int rx_irq;
2633 + int tx_irq;
2634 + int ovr_irq;
2635 + int und_irq;
2636 +
2637 + struct net_device_stats stats;
2638 + spinlock_t lock;
2639 +
2640 + /* debug /proc entry */
2641 + struct proc_dir_entry *ps;
2642 + int dma_halt_cnt; int dma_run_cnt;
2643 +};
2644 +
2645 +extern unsigned int idt_cpu_freq;
2646 +
2647 +/* Index to functions, as function prototypes. */
2648 +static int rc32434_open(struct net_device *dev);
2649 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
2650 +static void rc32434_mii_handler(unsigned long data);
2651 +static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2652 +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2653 +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2654 +#ifdef RC32434_REVISION
2655 +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2656 +#endif
2657 +static int rc32434_close(struct net_device *dev);
2658 +static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
2659 +static void rc32434_multicast_list(struct net_device *dev);
2660 +static int rc32434_init(struct net_device *dev);
2661 +static void rc32434_tx_timeout(struct net_device *dev);
2662 +
2663 +static void rc32434_tx_tasklet(unsigned long tx_data_dev);
2664 +#ifdef CONFIG_IDT_USE_NAPI
2665 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
2666 +#else
2667 +static void rc32434_rx_tasklet(unsigned long rx_data_dev);
2668 +#endif
2669 +static void rc32434_cleanup_module(void);
2670 +static int rc32434_probe(int port_num);
2671 +int rc32434_init_module(void);
2672 +
2673 +
2674 +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
2675 +{
2676 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
2677 + rc32434_writel(0x10, &ch->dmac);
2678 +
2679 + while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
2680 + dev->trans_start = jiffies;
2681 +
2682 + rc32434_writel(0, &ch->dmas);
2683 + }
2684 +
2685 + rc32434_writel(0, &ch->dmadptr);
2686 + rc32434_writel(0, &ch->dmandptr);
2687 +}
2688 diff -Nur linux-2.6.16/include/asm-mips/bootinfo.h linux-2.6.16-owrt/include/asm-mips/bootinfo.h
2689 --- linux-2.6.16/include/asm-mips/bootinfo.h 2006-03-20 06:53:29.000000000 +0100
2690 +++ linux-2.6.16-owrt/include/asm-mips/bootinfo.h 2006-03-20 14:25:10.000000000 +0100
2691 @@ -218,6 +218,17 @@
2692 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
2693 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
2694
2695 +
2696 +/*
2697 + * Valid machtype for group ARUBA
2698 + */
2699 +#define MACH_GROUP_ARUBA 23
2700 +#define MACH_ARUBA_UNKNOWN 0
2701 +#define MACH_ARUBA_AP60 1
2702 +#define MACH_ARUBA_AP65 2
2703 +#define MACH_ARUBA_AP70 3
2704 +#define MACH_ARUBA_AP40 4
2705 +
2706 #define CL_SIZE COMMAND_LINE_SIZE
2707
2708 const char *get_system_type(void);
2709 diff -Nur linux-2.6.16/include/asm-mips/cpu.h linux-2.6.16-owrt/include/asm-mips/cpu.h
2710 --- linux-2.6.16/include/asm-mips/cpu.h 2006-03-20 06:53:29.000000000 +0100
2711 +++ linux-2.6.16-owrt/include/asm-mips/cpu.h 2006-03-20 14:25:10.000000000 +0100
2712 @@ -53,6 +53,9 @@
2713 #define PRID_IMP_R12000 0x0e00
2714 #define PRID_IMP_R8000 0x1000
2715 #define PRID_IMP_PR4450 0x1200
2716 +#define PRID_IMP_RC32334 0x1800
2717 +#define PRID_IMP_RC32355 0x1900
2718 +#define PRID_IMP_RC32365 0x1900
2719 #define PRID_IMP_R4600 0x2000
2720 #define PRID_IMP_R4700 0x2100
2721 #define PRID_IMP_TX39 0x2200
2722 @@ -196,7 +199,8 @@
2723 #define CPU_34K 60
2724 #define CPU_PR4450 61
2725 #define CPU_SB1A 62
2726 -#define CPU_LAST 62
2727 +#define CPU_RC32300 63
2728 +#define CPU_LAST 63
2729
2730 /*
2731 * ISA Level encodings
2732 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32300.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h
2733 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32300.h 1970-01-01 01:00:00.000000000 +0100
2734 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h 2006-03-20 14:25:10.000000000 +0100
2735 @@ -0,0 +1,142 @@
2736 +/**************************************************************************
2737 + *
2738 + * BRIEF MODULE DESCRIPTION
2739 + * RC32300 helper routines
2740 + *
2741 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2742 + *
2743 + * This program is free software; you can redistribute it and/or modify it
2744 + * under the terms of the GNU General Public License as published by the
2745 + * Free Software Foundation; either version 2 of the License, or (at your
2746 + * option) any later version.
2747 + *
2748 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2749 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2750 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2751 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2752 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2753 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2754 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2755 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2756 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2757 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2758 + *
2759 + * You should have received a copy of the GNU General Public License along
2760 + * with this program; if not, write to the Free Software Foundation, Inc.,
2761 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2762 + *
2763 + *
2764 + **************************************************************************
2765 + * May 2004 P. Sadik.
2766 + *
2767 + * Initial Release
2768 + *
2769 + *
2770 + *
2771 + **************************************************************************
2772 + */
2773 +
2774 +#ifndef __IDT_RC32300_H__
2775 +#define __IDT_RC32300_H__
2776 +
2777 +#include <linux/delay.h>
2778 +#include <asm/io.h>
2779 +
2780 +
2781 +/* cpu pipeline flush */
2782 +static inline void rc32300_sync(void)
2783 +{
2784 + __asm__ volatile ("sync");
2785 +}
2786 +
2787 +static inline void rc32300_sync_udelay(int us)
2788 +{
2789 + __asm__ volatile ("sync");
2790 + udelay(us);
2791 +}
2792 +
2793 +static inline void rc32300_sync_delay(int ms)
2794 +{
2795 + __asm__ volatile ("sync");
2796 + mdelay(ms);
2797 +}
2798 +
2799 +/*
2800 + * Macros to access internal RC32300 registers. No byte
2801 + * swapping should be done when accessing the internal
2802 + * registers.
2803 + */
2804 +
2805 +static inline u8 rc32300_readb(unsigned long pa)
2806 +{
2807 + return *((volatile u8 *)KSEG1ADDR(pa));
2808 +}
2809 +static inline u16 rc32300_readw(unsigned long pa)
2810 +{
2811 + return *((volatile u16 *)KSEG1ADDR(pa));
2812 +}
2813 +static inline u32 rc32300_readl(unsigned long pa)
2814 +{
2815 + return *((volatile u32 *)KSEG1ADDR(pa));
2816 +}
2817 +static inline void rc32300_writeb(u8 val, unsigned long pa)
2818 +{
2819 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
2820 +}
2821 +static inline void rc32300_writew(u16 val, unsigned long pa)
2822 +{
2823 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
2824 +}
2825 +static inline void rc32300_writel(u32 val, unsigned long pa)
2826 +{
2827 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
2828 +}
2829 +
2830 +
2831 +#define local_readb __raw_readb
2832 +#define local_readw __raw_readw
2833 +#define local_readl __raw_readl
2834 +
2835 +#define local_writeb __raw_writeb
2836 +#define local_writew __raw_writew
2837 +#define local_writel __raw_writel
2838 +
2839 +
2840 +/*
2841 + * C access to CLZ and CLO instructions
2842 + * (count leading zeroes/ones).
2843 + */
2844 +static inline int rc32300_clz(unsigned long val)
2845 +{
2846 + int ret;
2847 + __asm__ volatile (
2848 + ".set\tnoreorder\n\t"
2849 + ".set\tnoat\n\t"
2850 + ".set\tmips32\n\t"
2851 + "clz\t%0,%1\n\t"
2852 + ".set\tmips0\n\t"
2853 + ".set\tat\n\t"
2854 + ".set\treorder"
2855 + : "=r" (ret)
2856 + : "r" (val));
2857 +
2858 + return ret;
2859 +}
2860 +static inline int rc32300_clo(unsigned long val)
2861 +{
2862 + int ret;
2863 + __asm__ volatile (
2864 + ".set\tnoreorder\n\t"
2865 + ".set\tnoat\n\t"
2866 + ".set\tmips32\n\t"
2867 + "clo\t%0,%1\n\t"
2868 + ".set\tmips0\n\t"
2869 + ".set\tat\n\t"
2870 + ".set\treorder"
2871 + : "=r" (ret)
2872 + : "r" (val));
2873 +
2874 + return ret;
2875 +}
2876 +
2877 +#endif // __IDT_RC32300_H__
2878 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h
2879 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32334.h 1970-01-01 01:00:00.000000000 +0100
2880 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h 2006-03-20 14:25:10.000000000 +0100
2881 @@ -0,0 +1,207 @@
2882 +/**************************************************************************
2883 + *
2884 + * BRIEF MODULE DESCRIPTION
2885 + * Definitions for IDT RC32334 CPU.
2886 + *
2887 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2888 + *
2889 + * This program is free software; you can redistribute it and/or modify it
2890 + * under the terms of the GNU General Public License as published by the
2891 + * Free Software Foundation; either version 2 of the License, or (at your
2892 + * option) any later version.
2893 + *
2894 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2895 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2896 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2897 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2898 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2899 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2900 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2901 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2902 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2903 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2904 + *
2905 + * You should have received a copy of the GNU General Public License along
2906 + * with this program; if not, write to the Free Software Foundation, Inc.,
2907 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2908 + *
2909 + *
2910 + **************************************************************************
2911 + * May 2004 P. Sadik.
2912 + *
2913 + * Initial Release
2914 + *
2915 + *
2916 + *
2917 + **************************************************************************
2918 + */
2919 +
2920 +
2921 +#ifndef __IDT_RC32334_H__
2922 +#define __IDT_RC32334_H__
2923 +
2924 +#include <linux/delay.h>
2925 +#include <asm/io.h>
2926 +
2927 +/* Base address of internal registers */
2928 +#define RC32334_REG_BASE 0x18000000
2929 +
2930 +/* CPU and IP Bus Control */
2931 +#define CPU_PORT_WIDTH 0xffffe200 // virtual!
2932 +#define CPU_BTA 0xffffe204 // virtual!
2933 +#define CPU_BUSERR_ADDR 0xffffe208 // virtual!
2934 +#define CPU_IP_BTA (RC32334_REG_BASE + 0x0000)
2935 +#define CPU_IP_ADDR_LATCH (RC32334_REG_BASE + 0x0004)
2936 +#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
2937 +#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
2938 +#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
2939 +#define CPU_IP_SYSID (RC32334_REG_BASE + 0x0018)
2940 +
2941 +/* Memory Controller */
2942 +#define MEM_BASE_BANK0 (RC32334_REG_BASE + 0x0080)
2943 +#define MEM_MASK_BANK0 (RC32334_REG_BASE + 0x0084)
2944 +#define MEM_CNTL_BANK0 (RC32334_REG_BASE + 0x0200)
2945 +#define MEM_BASE_BANK1 (RC32334_REG_BASE + 0x0088)
2946 +#define MEM_MASK_BANK1 (RC32334_REG_BASE + 0x008c)
2947 +#define MEM_CNTL_BANK1 (RC32334_REG_BASE + 0x0204)
2948 +#define MEM_CNTL_BANK2 (RC32334_REG_BASE + 0x0208)
2949 +#define MEM_CNTL_BANK3 (RC32334_REG_BASE + 0x020c)
2950 +#define MEM_CNTL_BANK4 (RC32334_REG_BASE + 0x0210)
2951 +#define MEM_CNTL_BANK5 (RC32334_REG_BASE + 0x0214)
2952 +
2953 +/* PCI Controller */
2954 +#define PCI_INTR_PEND (RC32334_REG_BASE + 0x05b0)
2955 +#define PCI_INTR_MASK (RC32334_REG_BASE + 0x05b4)
2956 +#define PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05b8)
2957 +#define CPU2PCI_INTR_PEND (RC32334_REG_BASE + 0x05c0)
2958 +#define CPU2PCI_INTR_MASK (RC32334_REG_BASE + 0x05c4)
2959 +#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
2960 +#define PCI2CPU_INTR_PEND (RC32334_REG_BASE + 0x05d0)
2961 +#define PCI2CPU_INTR_MASK (RC32334_REG_BASE + 0x05d4)
2962 +#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
2963 +#define PCI_MEM1_BASE (RC32334_REG_BASE + 0x20b0)
2964 +#define PCI_MEM2_BASE (RC32334_REG_BASE + 0x20b8)
2965 +#define PCI_MEM3_BASE (RC32334_REG_BASE + 0x20c0)
2966 +#define PCI_IO1_BASE (RC32334_REG_BASE + 0x20c8)
2967 +#define PCI_ARBITRATION (RC32334_REG_BASE + 0x20e0)
2968 +#define PCI_CPU_MEM1_BASE (RC32334_REG_BASE + 0x20e8)
2969 +#define PCI_CPU_IO_BASE (RC32334_REG_BASE + 0x2100)
2970 +#define PCI_CFG_CNTL (RC32334_REG_BASE + 0x2cf8)
2971 +#define PCI_CFG_DATA (RC32334_REG_BASE + 0x2cfc)
2972 +
2973 +/* Timers */
2974 +#define TIMER0_CNTL (RC32334_REG_BASE + 0x0700)
2975 +#define TIMER0_COUNT (RC32334_REG_BASE + 0x0704)
2976 +#define TIMER0_COMPARE (RC32334_REG_BASE + 0x0708)
2977 +#define TIMER_REG_OFFSET 0x10
2978 +
2979 +/* Programmable I/O */
2980 +#define PIO_DATA0 (RC32334_REG_BASE + 0x0600)
2981 +#define PIO_DATA1 (RC32334_REG_BASE + 0x0610)
2982 +
2983 +/*
2984 + * DMA
2985 + *
2986 + * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
2987 + *
2988 + * DMA0: 18001400
2989 + * DMA1: 18001440
2990 + * DMA2: 18001900
2991 + * DMA3: 18001940
2992 + * NB: dma number must be immediate value or variable.
2993 + * It MUST NOT be a function since it would get called twice!
2994 + */
2995 +#define DMA_IO(n) (((n)>1?0x500:0)+((n)&1?0x40:0))
2996 +
2997 +#define RC32300_IO_DMA(n) (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
2998 +#define RC32300_DMA_CONFREG(n) RC32300_IO_DMA(n)
2999 +#define RC32300_DMA_BASEREG(n) (RC32300_IO_DMA(n)+0x4)
3000 +
3001 +#define RC32300_DMA_CURRREG(n) (RC32300_IO_DMA(n)+0x8)
3002 +#define RC32300_DMA_STATREG(n) (RC32300_IO_DMA(n)+0x10)
3003 +#define RC32300_DMA_SRCREG(n) (RC32300_IO_DMA(n)+0x14)
3004 +#define RC32300_DMA_DSTREG(n) (RC32300_IO_DMA(n)+0x18)
3005 +#define RC32300_DMA_NEXTREG(n) (RC32300_IO_DMA(n)+0x1c)
3006 +
3007 +#define RC32300_DMA_IRQ(n) (GROUP7_IRQ_BASE+5*(n))
3008 +
3009 +/* Expansion Interrupt Controller */
3010 +#define IC_GROUP0_PEND (RC32334_REG_BASE + 0x0500)
3011 +#define IC_GROUP0_MASK (RC32334_REG_BASE + 0x0504)
3012 +#define IC_GROUP0_CLEAR (RC32334_REG_BASE + 0x0508)
3013 +#define IC_GROUP_OFFSET 0x10
3014 +
3015 +#define NUM_INTR_GROUPS 15
3016 +/*
3017 + * The IRQ mapping is as follows:
3018 + *
3019 + * IRQ Mapped To
3020 + * --- -------------------
3021 + * 0 SW0 (IP0) SW0 intr
3022 + * 1 SW1 (IP1) SW1 intr
3023 + * 2 Int0 (IP2) board-specific
3024 + * 3 Int1 (IP3) board-specific
3025 + * 4 Int2 (IP4) board-specific
3026 + * - Int3 (IP5) not used, mapped to IRQ's 8 and up
3027 + * 6 Int4 (IP6) board-specific
3028 + * 7 Int5 (IP7) CP0 Timer
3029 + *
3030 + * IRQ's 8 and up are all mapped to Int3 (IP5), which
3031 + * internally on the RC32334 is routed to the Expansion
3032 + * Interrupt Controller.
3033 + */
3034 +#define MIPS_CPU_TIMER_IRQ 7
3035 +
3036 +#define GROUP1_IRQ_BASE 8 // bus error
3037 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 1) // PIO active low
3038 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 12) // PIO active high
3039 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 8) // Timer Rollovers
3040 +#define GROUP5_IRQ_BASE (GROUP4_IRQ_BASE + 8) // UART0
3041 +#define GROUP6_IRQ_BASE (GROUP5_IRQ_BASE + 3) // UART1
3042 +#define GROUP7_IRQ_BASE (GROUP6_IRQ_BASE + 3) // DMA Ch0
3043 +#define GROUP8_IRQ_BASE (GROUP7_IRQ_BASE + 5) // DMA Ch1
3044 +#define GROUP9_IRQ_BASE (GROUP8_IRQ_BASE + 5) // DMA Ch2
3045 +#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5) // DMA Ch3
3046 +#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5) // PCI Ctlr errors
3047 +#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4) // PCI Satellite Mode
3048 +#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
3049 +#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4) // SPI
3050 +
3051 +#define RC32334_NR_IRQS (GROUP14_IRQ_BASE + 1)
3052 +
3053 +/* 16550 UARTs */
3054 +#ifdef __MIPSEB__
3055 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
3056 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
3057 +#else
3058 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
3059 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
3060 +#endif
3061 +
3062 +#define RC32300_UART0_IRQ GROUP5_IRQ_BASE
3063 +#define RC32300_UART1_IRQ GROUP6_IRQ_BASE
3064 +
3065 +#define IDT_CLOCK_MULT 2
3066 +
3067 +/* NVRAM */
3068 +#define NVRAM_BASE 0x12000000
3069 +#define NVRAM_ENVSIZE_OFF 4
3070 +#define NVRAM_ENVSTART_OFF 0x40
3071 +
3072 +/* LCD 4-digit display */
3073 +#define LCD_CLEAR 0x14000400
3074 +#define LCD_DIGIT0 0x1400000f
3075 +#define LCD_DIGIT1 0x14000008
3076 +#define LCD_DIGIT2 0x14000007
3077 +#define LCD_DIGIT3 0x14000003
3078 +
3079 +/* Interrupts routed on 79S334A board (see rc32334.h) */
3080 +#define RC32334_SCC8530_IRQ 2
3081 +#define RC32334_PCI_INTA_IRQ 3
3082 +#define RC32334_PCI_INTB_IRQ 4
3083 +#define RC32334_PCI_INTC_IRQ 6
3084 +#define RC32334_PCI_INTD_IRQ 7
3085 +
3086 +#define RAM_SIZE (32*1024*1024)
3087 +
3088 +#endif // __IDT_RC32334_H__
3089 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
3090 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 1970-01-01 01:00:00.000000000 +0100
3091 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 2006-03-20 14:25:10.000000000 +0100
3092 @@ -0,0 +1,206 @@
3093 +/**************************************************************************
3094 + *
3095 + * BRIEF MODULE DESCRIPTION
3096 + * DMA controller defines on IDT RC32355
3097 + *
3098 + * Copyright 2004 IDT Inc.
3099 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3100 + *
3101 + *
3102 + * This program is free software; you can redistribute it and/or modify it
3103 + * under the terms of the GNU General Public License as published by the
3104 + * Free Software Foundation; either version 2 of the License, or (at your
3105 + * option) any later version.
3106 + *
3107 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3108 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3109 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3110 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3111 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3112 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3113 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3114 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3115 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3116 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3117 + *
3118 + * You should have received a copy of the GNU General Public License along
3119 + * with this program; if not, write to the Free Software Foundation, Inc.,
3120 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3121 + *
3122 + *
3123 + * May 2004 rkt
3124 + * Initial Release
3125 + *
3126 + **************************************************************************
3127 + */
3128 +
3129 +#ifndef BANYAN_DMA_H
3130 +#define BANYAN_DMA_H
3131 +#include <asm/idt-boards/rc32300/rc32300.h>
3132 +
3133 +/*
3134 + * An image of one RC32355 dma channel registers
3135 + */
3136 +typedef struct {
3137 + u32 dmac;
3138 + u32 dmas;
3139 + u32 dmasm;
3140 + u32 dmadptr;
3141 + u32 dmandptr;
3142 +} rc32355_dma_ch_t;
3143 +
3144 +/*
3145 + * An image of all RC32355 dma channel registers
3146 + */
3147 +typedef struct {
3148 + rc32355_dma_ch_t ch[16];
3149 +} rc32355_dma_regs_t;
3150 +
3151 +
3152 +#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
3153 +
3154 +
3155 +/* DMAC register layout */
3156 +
3157 +#define DMAC_RUN 0x1 /* Halts processing when cleared */
3158 +#define DMAC_DM 0x2 /* Done Mask, ignore DMA events */
3159 +#define DMAC_MODE_MASK 0xC /* DMA operating mode */
3160 +
3161 +#define DMAC_MODE_AUTO 0x0 /* DMA Auto Request Mode */
3162 +#define DMAC_MODE_BURST 0x4 /* DMA Burst Request Mode */
3163 +#define DMAC_MODE_TFER 0x8 /* DMA Transfer Request Mode */
3164 +
3165 +/* DMAS and DMASM register layout */
3166 +
3167 +#define DMAS_F 0x01 /* Finished */
3168 +#define DMAS_D 0x02 /* Done */
3169 +#define DMAS_C 0x04 /* Chain */
3170 +#define DMAS_E 0x08 /* Error */
3171 +#define DMAS_H 0x10 /* Halt */
3172 +
3173 +/* Polling count for DMAS_H bit in DMAS register after halting DMA */
3174 +#define DMA_HALT_TIMEOUT 500
3175 +
3176 +
3177 +static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
3178 +{
3179 + int timeout=1;
3180 +
3181 + if (local_readl(&ch->dmac) & DMAC_RUN) {
3182 + local_writel(0, &ch->dmac);
3183 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
3184 + if (local_readl(&ch->dmas) & DMAS_H) {
3185 + local_writel(0, &ch->dmas);
3186 + break;
3187 + }
3188 + }
3189 + }
3190 +
3191 + return timeout ? 0 : 1;
3192 +}
3193 +
3194 +static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3195 +{
3196 + local_writel(0, &ch->dmandptr);
3197 + local_writel(dma_addr, &ch->dmadptr);
3198 +}
3199 +
3200 +static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3201 +{
3202 + local_writel(dma_addr, &ch->dmandptr);
3203 +}
3204 +
3205 +
3206 +/* The following can be used to describe DMA channels 0 to 15, and the */
3207 +/* sub device's needed to select them in the DMADESC_DS_MASK field */
3208 +
3209 +#define DMA_CHAN_ATM01 0 /* ATM interface 0,1 chan */
3210 +
3211 +#define DMA_CHAN_ATM0IN 0 /* ATM interface 0 input */
3212 +#define DMA_DEV_ATM0IN 0 /* ATM interface 0 input */
3213 +
3214 +#define DMA_CHAN_ATM1IN 0 /* ATM interface 1 input */
3215 +#define DMA_DEV_ATM1IN 1 /* ATM interface 1 input */
3216 +
3217 +#define DMA_CHAN_ATM0OUT 0 /* ATM interface 0 output */
3218 +#define DMA_DEV_ATM0OUT 2 /* ATM interface 0 output */
3219 +
3220 +#define DMA_CHAN_ATM1OUT 0 /* ATM interface 1 output */
3221 +#define DMA_DEV_ATM1OUT 3 /* ATM interface 1 output */
3222 +
3223 +/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
3224 +#define DMA_CHAN_ATMVCC(entry) ((entry)+1) /* ATM VC cache entry */
3225 +#define DMA_DEV_ATMVCC(entry) 0
3226 +
3227 +#define DMA_CHAN_MEMTOMEM 6 /* Memory to memory DMA */
3228 +#define DMA_DEV_MEMTOMEM 1 /* Memory to memory DMA */
3229 +
3230 +#define DMA_CHAN_ATMFMB0 7 /* ATM Frame Mode Buffer 0 */
3231 +#define DMA_DEV_ATMFMB0 1 /* ATM Frame Mode Buffer 0 */
3232 +
3233 +#define DMA_CHAN_ATMFMB1 8 /* ATM Frame Mode Buffer 1 */
3234 +#define DMA_DEV_ATMFMB1 1 /* ATM Frame Mode Buffer 1 */
3235 +
3236 +#define DMA_CHAN_ETHERIN 9 /* Ethernet input */
3237 +#define DMA_DEV_ETHERIN 0 /* Ethernet input */
3238 +
3239 +#define DMA_CHAN_ETHEROUT 10 /* Ethernet output */
3240 +#define DMA_DEV_ETHEROUT 0 /* Ethernet output */
3241 +
3242 +#define DMA_CHAN_TDMIN 11 /* TDM Bus input */
3243 +#define DMA_DEV_TDMIN 0 /* TDM Bus input */
3244 +
3245 +#define DMA_CHAN_TDMOUT 12 /* TDM Bus output */
3246 +#define DMA_DEV_TDMOUT 0 /* TDM Bus output */
3247 +
3248 +#define DMA_CHAN_USBIN 13 /* USB input */
3249 +#define DMA_DEV_USBIN 0 /* USB input */
3250 +
3251 +#define DMA_CHAN_USBOUT 14 /* USB output */
3252 +#define DMA_DEV_USBOUT 0 /* USB output */
3253 +
3254 +#define DMA_CHAN_EXTERN 15 /* External DMA */
3255 +#define DMA_DEV_EXTERN 0 /* External DMA */
3256 +
3257 +/*
3258 + * An RC32355 dma descriptor in system memory
3259 + */
3260 +typedef struct {
3261 + u32 cmdstat; /* control and status */
3262 + u32 curr_addr; /* current address of data */
3263 + u32 devcs; /* peripheral-specific control and status */
3264 + u32 link; /* link to next descriptor */
3265 +} rc32355_dma_desc_t;
3266 +
3267 +/* Values for the descriptor cmdstat word */
3268 +
3269 +#define DMADESC_F 0x80000000u /* Finished bit */
3270 +#define DMADESC_D 0x40000000u /* Done bit */
3271 +#define DMADESC_T 0x20000000u /* Terminated bit */
3272 +#define DMADESC_IOD 0x10000000u /* Interrupt On Done */
3273 +#define DMADESC_IOF 0x08000000u /* Interrupt On Finished */
3274 +#define DMADESC_COD 0x04000000u /* Chain On Done */
3275 +#define DMADESC_COF 0x02000000u /* Chain On Finished */
3276 +
3277 +#define DMADESC_DEVCMD_MASK 0x01C00000u /* Device Command mask */
3278 +#define DMADESC_DEVCMD_SHIFT 22 /* Device Command shift */
3279 +
3280 +#define DMADESC_DS_MASK 0x00300000u /* Device Select mask */
3281 +#define DMADESC_DS_SHIFT 20 /* Device Select shift */
3282 +
3283 +#define DMADESC_COUNT_MASK 0x0003FFFFu /* Byte Count mask */
3284 +#define DMADESC_COUNT_SHIFT 0 /* Byte Count shift */
3285 +
3286 +#define IS_DMA_FINISHED(X) ( ( (X) & DMADESC_F ) >> 31) /* F Bit */
3287 +#define IS_DMA_DONE(X) ( ( (X) & DMADESC_D ) >> 30) /* D Bit */
3288 +#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29) /* T Bit */
3289 +#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
3290 +
3291 +#define DMA_DEVCMD(devcmd) \
3292 + (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
3293 +#define DMA_DS(ds) \
3294 + (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
3295 +#define DMA_COUNT(count) \
3296 + ((count) & DMADESC_COUNT_MASK)
3297 +
3298 +#endif /* RC32355_DMA_H */
3299 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
3300 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 1970-01-01 01:00:00.000000000 +0100
3301 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 2006-03-20 14:25:10.000000000 +0100
3302 @@ -0,0 +1,442 @@
3303 +/**************************************************************************
3304 + *
3305 + * BRIEF MODULE DESCRIPTION
3306 + * Ethernet registers on IDT RC32355
3307 + *
3308 + * Copyright 2004 IDT Inc.
3309 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3310 + *
3311 + *
3312 + * This program is free software; you can redistribute it and/or modify it
3313 + * under the terms of the GNU General Public License as published by the
3314 + * Free Software Foundation; either version 2 of the License, or (at your
3315 + * option) any later version.
3316 + *
3317 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3318 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3319 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3320 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3321 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3322 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3323 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3324 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3325 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3326 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3327 + *
3328 + * You should have received a copy of the GNU General Public License along
3329 + * with this program; if not, write to the Free Software Foundation, Inc.,
3330 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3331 + *
3332 + *
3333 + * May 2004 rkt
3334 + * Initial Release
3335 + *
3336 + **************************************************************************
3337 + */
3338 +
3339 +
3340 +#ifndef RC32355_ETHER_H
3341 +#define RC32355_ETHER_H
3342 +
3343 +#include <asm/idt-boards/rc32300/rc32355_dma.h>
3344 +
3345 +/*
3346 + * A partial image of the RC32355 ethernet registers
3347 + */
3348 +typedef struct {
3349 + u32 ethintfc;
3350 + u32 ethfifott;
3351 + u32 etharc;
3352 + u32 ethhash0;
3353 + u32 ethhash1;
3354 + u32 ethfifost;
3355 + u32 ethfifos;
3356 + u32 ethodeops;
3357 + u32 ethis;
3358 + u32 ethos;
3359 + u32 ethmcp;
3360 + u32 _u1;
3361 + u32 ethid;
3362 + u32 _u2;
3363 + u32 _u3;
3364 + u32 _u4;
3365 + u32 ethod;
3366 + u32 _u5;
3367 + u32 _u6;
3368 + u32 _u7;
3369 + u32 ethodeop;
3370 + u32 _u8[43];
3371 + u32 ethsal0;
3372 + u32 ethsah0;
3373 + u32 ethsal1;
3374 + u32 ethsah1;
3375 + u32 ethsal2;
3376 + u32 ethsah2;
3377 + u32 ethsal3;
3378 + u32 ethsah3;
3379 + u32 ethrbc;
3380 + u32 ethrpc;
3381 + u32 ethrupc;
3382 + u32 ethrfc;
3383 + u32 ethtbc;
3384 + u32 ethgpf;
3385 + u32 _u9[50];
3386 + u32 ethmac1;
3387 + u32 ethmac2;
3388 + u32 ethipgt;
3389 + u32 ethipgr;
3390 + u32 ethclrt;
3391 + u32 ethmaxf;
3392 + u32 _u10;
3393 + u32 ethmtest;
3394 + u32 miimcfg;
3395 + u32 miimcmd;
3396 + u32 miimaddr;
3397 + u32 miimwtd;
3398 + u32 miimrdd;
3399 + u32 miimind;
3400 + u32 _u11;
3401 + u32 _u12;
3402 + u32 ethcfsa0;
3403 + u32 ethcfsa1;
3404 + u32 ethcfsa2;
3405 +} rc32355_eth_regs_t;
3406 +
3407 +#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
3408 +
3409 +#define ETH_INTFC (RC32355_ETH_BASE + 0x000) /* INTerFace Control */
3410 +#define ETH_FIFOTT (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold */
3411 +#define ETH_ARC (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl */
3412 +#define ETH_HASH0 (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
3413 +#define ETH_HASH1 (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
3414 +#define ETH_FIFOST (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
3415 +#define ETH_FIFOS (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
3416 +#define ETH_ODEOPS (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
3417 +#define ETH_IS (RC32355_ETH_BASE + 0x020) /* Input Status */
3418 +#define ETH_OS (RC32355_ETH_BASE + 0x024) /* Output Status */
3419 +#define ETH_MCP (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
3420 +#define ETH_ID (RC32355_ETH_BASE + 0x030) /* Input Data register */
3421 +#define ETH_OD (RC32355_ETH_BASE + 0x040) /* Output Data register */
3422 +#define ETH_ODEOP (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
3423 +
3424 +/* for n in { 0, 1, 2, 3 } */
3425 +#define ETH_SAL(n) (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
3426 +#define ETH_SAH(n) (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
3427 +
3428 +#define ETH_RBC (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
3429 +#define ETH_RPC (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
3430 +#define ETH_RUPC (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
3431 +#define ETH_RFC (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
3432 +#define ETH_TBC (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
3433 +#define ETH_GPF (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
3434 +#define ETH_MAC1 (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
3435 +#define ETH_MAC2 (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
3436 +#define ETH_IPGT (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
3437 +#define ETH_IPGR (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
3438 +#define ETH_CLRT (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
3439 +#define ETH_MAXF (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
3440 +#define ETH_MTEST (RC32355_ETH_BASE + 0x21C) /* MAC Test */
3441 +
3442 +#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
3443 +#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command */
3444 +#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
3445 +#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
3446 +#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
3447 +#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
3448 +
3449 +/* for n in { 0, 1, 2 } */
3450 +#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4)) /* Station Addr */
3451 +
3452 +
3453 +/*
3454 + * Register Interpretations follow
3455 + */
3456 +
3457 +/******************************************************************************
3458 + * ETHINTFC register
3459 + *****************************************************************************/
3460 +
3461 +#define ETHERINTFC_EN (1<<0)
3462 +#define ETHERINTFC_ITS (1<<1)
3463 +#define ETHERINTFC_RES (1<<2)
3464 +#define ETHERINTFC_RIP (1<<2)
3465 +#define ETHERINTFC_JAM (1<<3)
3466 +
3467 +/******************************************************************************
3468 + * ETHFIFOTT register
3469 + *****************************************************************************/
3470 +
3471 +#define ETHERFIFOTT_TTH(v) (((v)&0x3f)<<0)
3472 +
3473 +/******************************************************************************
3474 + * ETHARC register
3475 + *****************************************************************************/
3476 +
3477 +#define ETHERARC_PRO (1<<0)
3478 +#define ETHERARC_AM (1<<1)
3479 +#define ETHERARC_AFM (1<<2)
3480 +#define ETHERARC_AB (1<<3)
3481 +
3482 +/******************************************************************************
3483 + * ETHHASH registers
3484 + *****************************************************************************/
3485 +
3486 +#define ETHERHASH0(v) (((v)&0xffff)<<0)
3487 +#define ETHERHASH1(v) (((v)&0xffff)<<0)
3488 +
3489 +/******************************************************************************
3490 + * ETHSA registers
3491 + *****************************************************************************/
3492 +
3493 +#define ETHERSAL0(v) (((v)&0xffff)<<0)
3494 +#define ETHERSAL1(v) (((v)&0xffff)<<0)
3495 +#define ETHERSAL2(v) (((v)&0xffff)<<0)
3496 +#define ETHERSAL3(v) (((v)&0xffff)<<0)
3497 +#define ETHERSAH0(v) (((v)&0xff)<<0)
3498 +#define ETHERSAH1(v) (((v)&0xff)<<0)
3499 +#define ETHERSAH2(v) (((v)&0xff)<<0)
3500 +#define ETHERSAH3(v) (((v)&0xff)<<0)
3501 +
3502 +/******************************************************************************
3503 + * ETHFIFOST register
3504 + *****************************************************************************/
3505 +
3506 +#define ETHERFIFOST_IRTH(v) (((v)&0x3f)<<0)
3507 +#define ETHERFIFOST_ORTH(v) (((v)&0x3f)<<16)
3508 +
3509 +/******************************************************************************
3510 + * ETHFIFOS register
3511 + *****************************************************************************/
3512 +
3513 +#define ETHERFIFOS_IR (1<<0)
3514 +#define ETHERFIFOS_OR (1<<1)
3515 +#define ETHERFIFOS_OVR (1<<2)
3516 +#define ETHERFIFOS_UND (1<<3)
3517 +
3518 +/******************************************************************************
3519 + * DATA registers
3520 + *****************************************************************************/
3521 +
3522 +#define ETHERID(v) (((v)&0xffff)<<0)
3523 +#define ETHEROD(v) (((v)&0xffff)<<0)
3524 +
3525 +/******************************************************************************
3526 + * ETHODEOPS register
3527 + *****************************************************************************/
3528 +
3529 +#define ETHERODEOPS_SIZE(v) (((v)&0x3)<<0)
3530 +
3531 +/******************************************************************************
3532 + * ETHODEOP register
3533 + *****************************************************************************/
3534 +
3535 +#define ETHERODEOP(v) (((v)&0xffff)<<0)
3536 +
3537 +/******************************************************************************
3538 + * ETHIS register
3539 + *****************************************************************************/
3540 +
3541 +#define ETHERIS_EOP (1<<0)
3542 +#define ETHERIS_ROK (1<<2)
3543 +#define ETHERIS_FM (1<<3)
3544 +#define ETHERIS_MP (1<<4)
3545 +#define ETHERIS_BP (1<<5)
3546 +#define ETHERIS_VLT (1<<6)
3547 +#define ETHERIS_CF (1<<7)
3548 +#define ETHERIS_OVR (1<<8)
3549 +#define ETHERIS_CRC (1<<9)
3550 +#define ETHERIS_CV (1<<10)
3551 +#define ETHERIS_DB (1<<11)
3552 +#define ETHERIS_LE (1<<12)
3553 +#define ETHERIS_LOR (1<<13)
3554 +#define ETHERIS_SIZE(v) (((v)&0x3)<<14)
3555 +#define ETHERIS_LENGTH(v) (((v)&0xff)<<16)
3556 +
3557 +/******************************************************************************
3558 + * ETHOS register
3559 + *****************************************************************************/
3560 +
3561 +#define ETHEROS_T (1<<0)
3562 +#define ETHEROS_TOK (1<<6)
3563 +#define ETHEROS_MP (1<<7)
3564 +#define ETHEROS_BP (1<<8)
3565 +#define ETHEROS_UND (1<<9)
3566 +#define ETHEROS_OF (1<<10)
3567 +#define ETHEROS_ED (1<<11)
3568 +#define ETHEROS_EC (1<<12)
3569 +#define ETHEROS_LC (1<<13)
3570 +#define ETHEROS_TD (1<<14)
3571 +#define ETHEROS_CRC (1<<15)
3572 +#define ETHEROS_LE (1<<16)
3573 +#define ETHEROS_CC(v) (((v)&0xf)<<17)
3574 +#define ETHEROS_PFD (1<<21)
3575 +
3576 +/******************************************************************************
3577 + * Statistics registers
3578 + *****************************************************************************/
3579 +
3580 +#define ETHERRBC(v) (((v)&0xffff)<<0)
3581 +#define ETHERRPC(v) (((v)&0xffff)<<0)
3582 +#define ETHERRUPC(v) (((v)&0xffff)<<0)
3583 +#define ETHERRFC(v) (((v)&0xffff)<<0)
3584 +#define ETHERTBC(v) (((v)&0xffff)<<0)
3585 +
3586 +/******************************************************************************
3587 + * ETHGPF register
3588 + *****************************************************************************/
3589 +
3590 +#define ETHERGPF_PTV(v) (((v)&0xff)<<0)
3591 +
3592 +/******************************************************************************
3593 + * MAC registers
3594 + *****************************************************************************/
3595 +//ETHMAC1
3596 +#define ETHERMAC1_RE (1<<0)
3597 +#define ETHERMAC1_PAF (1<<1)
3598 +#define ETHERMAC1_RFC (1<<2)
3599 +#define ETHERMAC1_TFC (1<<3)
3600 +#define ETHERMAC1_LB (1<<4)
3601 +#define ETHERMAC1_MR (1<<15)
3602 +
3603 +//ETHMAC2
3604 +#define ETHERMAC2_FD (1<<0)
3605 +#define ETHERMAC2_FLC (1<<1)
3606 +#define ETHERMAC2_HFE (1<<2)
3607 +#define ETHERMAC2_DC (1<<3)
3608 +#define ETHERMAC2_CEN (1<<4)
3609 +#define ETHERMAC2_PE (1<<5)
3610 +#define ETHERMAC2_VPE (1<<6)
3611 +#define ETHERMAC2_APE (1<<7)
3612 +#define ETHERMAC2_PPE (1<<8)
3613 +#define ETHERMAC2_LPE (1<<9)
3614 +#define ETHERMAC2_NB (1<<12)
3615 +#define ETHERMAC2_BP (1<<13)
3616 +#define ETHERMAC2_ED (1<<14)
3617 +
3618 +//ETHIPGT
3619 +#define ETHERIPGT(v) (((v)&0x3f)<<0)
3620 +
3621 +//ETHIPGR
3622 +#define ETHERIPGR_IPGR1(v) (((v)&0x3f)<<0)
3623 +#define ETHERIPGR_IPGR2(v) (((v)&0x3f)<<8)
3624 +
3625 +//ETHCLRT
3626 +#define ETHERCLRT_MAXRET(v) (((v)&0x3f)<<0)
3627 +#define ETHERCLRT_COLWIN(v) (((v)&0x3f)<<8)
3628 +
3629 +//ETHMAXF
3630 +#define ETHERMAXF(v) (((v)&0x3f)<<0)
3631 +
3632 +//ETHMTEST
3633 +#define ETHERMTEST_TB (1<<2)
3634 +
3635 +//ETHMCP
3636 +#define ETHERMCP_DIV(v) (((v)&0xff)<<0)
3637 +
3638 +//MIIMCFG
3639 +#define ETHERMIIMCFG_CS(v) (((v)&0x3)<<2)
3640 +#define ETHERMIIMCFG_R (1<<15)
3641 +
3642 +//MIIMCMD
3643 +#define ETHERMIIMCMD_RD (1<<0)
3644 +#define ETHERMIIMCMD_SCN (1<<1)
3645 +
3646 +//MIIMADDR
3647 +#define ETHERMIIMADDR_REGADDR(v) (((v)&0x1f)<<0)
3648 +#define ETHERMIIMADDR_PHYADDR(v) (((v)&0x1f)<<8)
3649 +
3650 +//MIIMWTD
3651 +#define ETHERMIIMWTD(v) (((v)&0xff)<<0)
3652 +
3653 +//MIIMRDD
3654 +#define ETHERMIIMRDD(v) (((v)&0xff)<<0)
3655 +
3656 +//MIIMIND
3657 +#define ETHERMIIMIND_BSY (1<<0)
3658 +#define ETHERMIIMIND_SCN (1<<1)
3659 +#define ETHERMIIMIND_NV (1<<2)
3660 +
3661 +//DMA DEVCS IN
3662 +#define ETHERDMA_IN_LENGTH(v) (((v)&0xffff)<<16)
3663 +#define ETHERDMA_IN_CES (1<<14)
3664 +#define ETHERDMA_IN_LOR (1<<13)
3665 +#define ETHERDMA_IN_LE (1<<12)
3666 +#define ETHERDMA_IN_DB (1<<11)
3667 +#define ETHERDMA_IN_CV (1<<10)
3668 +#define ETHERDMA_IN_CRC (1<<9)
3669 +#define ETHERDMA_IN_OVR (1<<8)
3670 +#define ETHERDMA_IN_CF (1<<7)
3671 +#define ETHERDMA_IN_VLT (1<<6)
3672 +#define ETHERDMA_IN_BP (1<<5)
3673 +#define ETHERDMA_IN_MP (1<<4)
3674 +#define ETHERDMA_IN_FM (1<<3)
3675 +#define ETHERDMA_IN_ROK (1<<2)
3676 +#define ETHERDMA_IN_LD (1<<1)
3677 +#define ETHERDMA_IN_FD (1<<0)
3678 +
3679 +//DMA DEVCS OUT
3680 +#define ETHERDMA_OUT_CC(v) (((v)&0xf)<<17)
3681 +#define ETHERDMA_OUT_CNT 0x001e0000
3682 +#define ETHERDMA_OUT_SHFT 17
3683 +#define ETHERDMA_OUT_LE (1<<16)
3684 +
3685 +#define ETHERDMA_OUT_CRC (1<<15)
3686 +#define ETHERDMA_OUT_TD (1<<14)
3687 +#define ETHERDMA_OUT_LC (1<<13)
3688 +#define ETHERDMA_OUT_EC (1<<12)
3689 +#define ETHERDMA_OUT_ED (1<<11)
3690 +#define ETHERDMA_OUT_OF (1<<10)
3691 +#define ETHERDMA_OUT_UND (1<<9)
3692 +#define ETHERDMA_OUT_BP (1<<8)
3693 +#define ETHERDMA_OUT_MP (1<<7)
3694 +#define ETHERDMA_OUT_TOK (1<<6)
3695 +#define ETHERDMA_OUT_HEN (1<<5)
3696 +#define ETHERDMA_OUT_CEN (1<<4)
3697 +#define ETHERDMA_OUT_PEN (1<<3)
3698 +#define ETHERDMA_OUT_OEN (1<<2)
3699 +#define ETHERDMA_OUT_LD (1<<1)
3700 +#define ETHERDMA_OUT_FD (1<<0)
3701 +
3702 +#define RCV_ERRS \
3703 + (ETHERDMA_IN_OVR | ETHERDMA_IN_CRC | ETHERDMA_IN_CV | ETHERDMA_IN_LE)
3704 +#define TX_ERRS \
3705 + (ETHERDMA_OUT_LC | ETHERDMA_OUT_EC | ETHERDMA_OUT_ED | \
3706 + ETHERDMA_OUT_OF | ETHERDMA_OUT_UND)
3707 +
3708 +#define IS_RCV_ROK(X) (((X) & (1<<2)) >> 2) /* Receive Okay */
3709 +#define IS_RCV_FM(X) (((X) & (1<<3)) >> 3) /* Is Filter Match */
3710 +#define IS_RCV_MP(X) (((X) & (1<<4)) >> 4) /* Is it MP */
3711 +#define IS_RCV_BP(X) (((X) & (1<<5)) >> 5) /* Is it BP */
3712 +#define IS_RCV_VLT(X) (((X) & (1<<6)) >> 6) /* VLAN Tag Detect */
3713 +#define IS_RCV_CF(X) (((X) & (1<<7)) >> 7) /* Control Frame */
3714 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<8)) >> 8) /* Receive Overflow */
3715 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<9)) >> 9) /* CRC Error */
3716 +#define IS_RCV_CV_ERR(X) (((X) & (1<<10))>>10) /* Code Violation */
3717 +#define IS_RCV_DB_ERR(X) (((X) & (1<<11))>>11) /* Dribble Bits */
3718 +#define IS_RCV_LE_ERR(X) (((X) & (1<<12))>>12) /* Length error */
3719 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<13))>>13) /* Length Out of
3720 + Range */
3721 +#define IS_RCV_CES_ERR(X) (((X) & (1<<14))>>14) /* Preamble error */
3722 +#define RCVPKT_LENGTH(X) (((X) & 0xFFFF0000)>>16) /* Length of the
3723 + received packet */
3724 +
3725 +#define IS_TX_TOK(X) (((X) & (1<<6) ) >> 6 ) /* Transmit Okay */
3726 +#define IS_TX_MP(X) (((X) & (1<<7) ) >> 7 ) /* Multicast */
3727 +
3728 +#define IS_TX_BP(X) (((X) & (1<<8) ) >> 8 ) /* Broadcast */
3729 +#define IS_TX_UND_ERR(X) (((X) & (1<<9) ) >> 9 ) /* Transmit FIFO
3730 + Underflow */
3731 +#define IS_TX_OF_ERR(X) (((X) & (1<<10)) >>10 ) /* Oversized frame */
3732 +#define IS_TX_ED_ERR(X) (((X) & (1<<11)) >>11 ) /* Excessive
3733 + deferral */
3734 +#define IS_TX_EC_ERR(X) (((X) & (1<<12)) >>12 ) /* Excessive
3735 + collisions */
3736 +#define IS_TX_LC_ERR(X) (((X) & (1<<13)) >>13 ) /* Late Collision */
3737 +#define IS_TX_TD_ERR(X) (((X) & (1<<14)) >>14 ) /* Transmit deferred*/
3738 +#define IS_TX_CRC_ERR(X) (((X) & (1<<15)) >>15 ) /* CRC Error */
3739 +#define IS_TX_LE_ERR(X) (((X) & (1<<16)) >>16 ) /* Length Error */
3740 +
3741 +#define TX_COLLISION_COUNT(X) (((X) & 0x001E0000u)>>17) /* Collision Count */
3742 +
3743 +#endif /* RC32355_ETHER_H */
3744 +
3745 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h
3746 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355.h 1970-01-01 01:00:00.000000000 +0100
3747 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h 2006-03-20 14:25:10.000000000 +0100
3748 @@ -0,0 +1,177 @@
3749 +/**************************************************************************
3750 + *
3751 + * BRIEF MODULE DESCRIPTION
3752 + * Definitions for IDT RC32355 CPU.
3753 + *
3754 + * Copyright 2004 IDT Inc.
3755 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3756 + *
3757 + *
3758 + * This program is free software; you can redistribute it and/or modify it
3759 + * under the terms of the GNU General Public License as published by the
3760 + * Free Software Foundation; either version 2 of the License, or (at your
3761 + * option) any later version.
3762 + *
3763 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3764 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3765 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3766 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3767 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3768 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3769 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3770 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3771 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3772 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3773 + *
3774 + * You should have received a copy of the GNU General Public License along
3775 + * with this program; if not, write to the Free Software Foundation, Inc.,
3776 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3777 + *
3778 + *
3779 + * May 2004 rkt
3780 + * Initial Release
3781 + *
3782 + **************************************************************************
3783 + */
3784 +
3785 +
3786 +#ifndef _RC32355_H_
3787 +#define _RC32355_H_
3788 +
3789 +#include <linux/delay.h>
3790 +#include <asm/io.h>
3791 +
3792 +/* Base address of internal registers */
3793 +#define RC32355_REG_BASE 0x18000000
3794 +
3795 +/* System ID Registers */
3796 +#define CPU_SYSID (RC32355_REG_BASE + 0x00018)
3797 +#define CPU_BTADDR (RC32355_REG_BASE + 0x0001c)
3798 +#define CPU_REV (RC32355_REG_BASE + 0x0002c)
3799 +
3800 +/* Reset Controller */
3801 +#define RESET_CNTL (RC32355_REG_BASE + 0x08000)
3802 +
3803 +/* Device Controller */
3804 +#define DEV0_BASE (RC32355_REG_BASE + 0x10000)
3805 +#define DEV0_MASK (RC32355_REG_BASE + 0x10004)
3806 +#define DEV0_CNTL (RC32355_REG_BASE + 0x10008)
3807 +#define DEV0_TIMING (RC32355_REG_BASE + 0x1000c)
3808 +#define DEV_REG_OFFSET 0x10
3809 +
3810 +/* SDRAM Controller */
3811 +#define SDRAM0_BASE (RC32355_REG_BASE + 0x18000)
3812 +#define SDRAM0_MASK (RC32355_REG_BASE + 0x18004)
3813 +#define SDRAM1_BASE (RC32355_REG_BASE + 0x18008)
3814 +#define SDRAM1_MASK (RC32355_REG_BASE + 0x1800c)
3815 +#define SDRAM_CNTL (RC32355_REG_BASE + 0x18010)
3816 +
3817 +/* Bus Arbiter */
3818 +#define BUS_ARB_CNTL0 (RC32355_REG_BASE + 0x20000)
3819 +#define BUS_ARB_CNTL1 (RC32355_REG_BASE + 0x20004)
3820 +
3821 +/* Counters/Timers */
3822 +#define TIMER0_COUNT (RC32355_REG_BASE + 0x28000)
3823 +#define TIMER0_COMPARE (RC32355_REG_BASE + 0x28004)
3824 +#define TIMER0_CNTL (RC32355_REG_BASE + 0x28008)
3825 +#define TIMER_REG_OFFSET 0x0C
3826 +
3827 +/* System Integrity */
3828 +
3829 +/* Interrupt Controller */
3830 +#define IC_GROUP0_PEND (RC32355_REG_BASE + 0x30000)
3831 +#define IC_GROUP0_MASK (RC32355_REG_BASE + 0x30004)
3832 +#define IC_GROUP_OFFSET 0x08
3833 +
3834 +#define NUM_INTR_GROUPS 5
3835 +/*
3836 + * The IRQ mapping is as follows:
3837 + *
3838 + * IRQ Mapped To
3839 + * --- -------------------
3840 + * 0 SW0 (IP0) SW0 intr
3841 + * 1 SW1 (IP1) SW1 intr
3842 + * - Int0 (IP2) mapped to GROUP0_IRQ_BASE
3843 + * - Int1 (IP3) mapped to GROUP1_IRQ_BASE
3844 + * - Int2 (IP4) mapped to GROUP2_IRQ_BASE
3845 + * - Int3 (IP5) mapped to GROUP3_IRQ_BASE
3846 + * - Int4 (IP6) mapped to GROUP4_IRQ_BASE
3847 + * 7 Int5 (IP7) CP0 Timer
3848 + *
3849 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
3850 + * internally on the RC32355 is routed to the Expansion
3851 + * Interrupt Controller.
3852 + */
3853 +#define MIPS_CPU_TIMER_IRQ 7
3854 +
3855 +#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
3856 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) // DMA
3857 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) // ATM
3858 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) // TDM, Eth, USB, UARTs, I2C
3859 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) // GPIO
3860 +
3861 +#define RC32355_NR_IRQS (GROUP4_IRQ_BASE + 32)
3862 +
3863 +/* DMA - see rc32355_dma.h for full list of registers */
3864 +
3865 +#define RC32355_DMA_BASE (RC32355_REG_BASE + 0x38000)
3866 +#define DMA_CHAN_OFFSET 0x14
3867 +
3868 +/* GPIO Controller */
3869 +
3870 +/* TDM Bus */
3871 +
3872 +/* 16550 UARTs */
3873 +#ifdef __MIPSEB__
3874 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50003)
3875 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50023)
3876 +#else
3877 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50000)
3878 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50020)
3879 +#endif
3880 +
3881 +#define RC32300_UART0_IRQ (GROUP3_IRQ_BASE + 14)
3882 +#define RC32300_UART1_IRQ (GROUP3_IRQ_BASE + 17)
3883 +
3884 +/* ATM */
3885 +
3886 +/* Ethernet - see rc32355_eth.h for full list of registers */
3887 +
3888 +#define RC32355_ETH_BASE (RC32355_REG_BASE + 0x60000)
3889 +
3890 +
3891 +#define IDT_CLOCK_MULT 2
3892 +
3893 +/* Memory map of 79EB355 board */
3894 +
3895 +/* DRAM */
3896 +#define RAM_BASE 0x00000000
3897 +#define RAM_SIZE (32*1024*1024)
3898 +
3899 +/* SRAM (device 1) */
3900 +#define SRAM_BASE 0x02000000
3901 +#define SRAM_SIZE 0x00100000
3902 +
3903 +/* FLASH (device 2) */
3904 +#define FLASH_BASE 0x0C000000
3905 +#define FLASH_SIZE 0x00C00000
3906 +
3907 +/* ATM PHY (device 4) */
3908 +#define ATM_PHY_BASE 0x14000000
3909 +
3910 +/* TDM switch (device 3) */
3911 +#define TDM_BASE 0x1A000000
3912 +
3913 +/* LCD panel (device 3) */
3914 +#define LCD_BASE 0x1A002000
3915 +
3916 +/* RTC (DS1511W) (device 3) */
3917 +#define RTC_BASE 0x1A004000
3918 +
3919 +/* NVRAM (256 bytes internal to the DS1511 RTC) */
3920 +#define NVRAM_ADDR RTC_BASE + 0x10
3921 +#define NVRAM_DATA RTC_BASE + 0x13
3922 +#define NVRAM_ENVSIZE_OFF 4
3923 +#define NVRAM_ENVSTART_OFF 32
3924 +
3925 +#endif /* _RC32355_H_ */
3926 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_dma.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h
3927 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 1970-01-01 01:00:00.000000000 +0100
3928 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 2006-03-20 14:25:10.000000000 +0100
3929 @@ -0,0 +1,226 @@
3930 +/**************************************************************************
3931 + *
3932 + * BRIEF MODULE DESCRIPTION
3933 + * RC32365/336 DMA hardware abstraction.
3934 + *
3935 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
3936 + *
3937 + * This program is free software; you can redistribute it and/or modify it
3938 + * under the terms of the GNU General Public License as published by the
3939 + * Free Software Foundation; either version 2 of the License, or (at your
3940 + * option) any later version.
3941 + *
3942 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3943 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3944 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3945 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3946 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3947 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3948 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3949 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3950 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3951 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3952 + *
3953 + * You should have received a copy of the GNU General Public License along
3954 + * with this program; if not, write to the Free Software Foundation, Inc.,
3955 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3956 + *
3957 + *
3958 + **************************************************************************
3959 + * May 2004 P. Sadik.
3960 + *
3961 + * Initial Release
3962 + *
3963 + *
3964 + *
3965 + **************************************************************************
3966 + */
3967 +
3968 +#ifndef __IDT_RC32365_DMA_H__
3969 +#define __IDT_RC32365_DMA_H__
3970 +
3971 +enum
3972 +{
3973 + DMA0_PhysicalAddress = 0x18038000,
3974 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
3975 +
3976 + DMA0_VirtualAddress = 0xb8038000,
3977 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
3978 +} ;
3979 +
3980 +/*
3981 + * DMA descriptor (in physical memory).
3982 + */
3983 +
3984 +typedef struct DMAD_s
3985 +{
3986 + u32 control ; // Control. use DMAD_*
3987 + u32 ca ; // Current Address.
3988 + u32 devcs ; // Device control and status.
3989 + u32 link ; // Next descriptor in chain.
3990 +} volatile *DMAD_t ;
3991 +
3992 +enum
3993 +{
3994 + DMAD_size = sizeof (struct DMAD_s),
3995 + DMAD_count_b = 0, // in DMAD_t -> control
3996 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
3997 + DMAD_ds_b = 20, // in DMAD_t -> control
3998 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
3999 + DMAD_ds_extToMem0_v = 0,
4000 + DMAD_ds_memToExt0_v = 1,
4001 + DMAD_ds_extToMem1_v = 0,
4002 + DMAD_ds_memToExt1_v = 1,
4003 + DMAD_ds_ethRcv0_v = 0,
4004 + DMAD_ds_ethXmt0_v = 0,
4005 + DMAD_ds_ethRcv1_v = 0,
4006 + DMAD_ds_ethXmt2_v = 0,
4007 + DMAD_ds_memToFifo_v = 0,
4008 + DMAD_ds_fifoToMem_v = 0,
4009 + DMAD_ds_rng_de_v = 1,//randomNumberGenerator on LC/DE
4010 + DMAD_ds_pciToMem_v = 0,
4011 + DMAD_ds_memToPci_v = 0,
4012 + DMAD_ds_securityInput_v = 0,
4013 + DMAD_ds_securityOutput_v = 0,
4014 + DMAD_ds_rng_se_v = 0,//randomNumberGenerator on SE
4015 +
4016 + DMAD_devcmd_b = 22, // in DMAD_t -> control
4017 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
4018 + DMAD_devcmd_byte_v = 0, //memory-to-memory
4019 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
4020 + DMAD_devcmd_word_v = 2, //memory-to-memory
4021 + DMAD_devcmd_2words_v = 3, //memory-to-memory
4022 + DMAD_devcmd_4words_v = 4, //memory-to-memory
4023 + DMAD_devcmd_6words_v = 5, //memory-to-memory
4024 + DMAD_devcmd_8words_v = 6, //memory-to-memory
4025 + DMAD_devcmd_16words_v = 7, //memory-to-memory
4026 + DMAD_cof_b = 25, // chain on finished
4027 + DMAD_cof_m = 0x02000000, //
4028 + DMAD_cod_b = 26, // chain on done
4029 + DMAD_cod_m = 0x04000000, //
4030 + DMAD_iof_b = 27, // interrupt on finished
4031 + DMAD_iof_m = 0x08000000, //
4032 + DMAD_iod_b = 28, // interrupt on done
4033 + DMAD_iod_m = 0x10000000, //
4034 + DMAD_t_b = 29, // terminated
4035 + DMAD_t_m = 0x20000000, //
4036 + DMAD_d_b = 30, // done
4037 + DMAD_d_m = 0x40000000, //
4038 + DMAD_f_b = 31, // finished
4039 + DMAD_f_m = 0x80000000, //
4040 +} ;
4041 +
4042 +/*
4043 + * DMA register (within Internal Register Map).
4044 + */
4045 +
4046 +struct DMA_Chan_s
4047 +{
4048 + u32 dmac ; // Control.
4049 + u32 dmas ; // Status.
4050 + u32 dmasm ; // Mask.
4051 + u32 dmadptr ; // Descriptor pointer.
4052 + u32 dmandptr ; // Next descriptor pointer.
4053 +};
4054 +
4055 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
4056 +
4057 +//DMA_Channels use DMACH_count instead
4058 +
4059 +enum
4060 +{
4061 + DMAC_run_b = 0, //
4062 + DMAC_run_m = 0x00000001, //
4063 + DMAC_dm_b = 1, // done mask
4064 + DMAC_dm_m = 0x00000002, //
4065 + DMAC_mode_b = 2, //
4066 + DMAC_mode_m = 0x0000000c, //
4067 + DMAC_mode_auto_v = 0,
4068 + DMAC_mode_burst_v = 1,
4069 + DMAC_mode_transfer_v = 2, //usually used
4070 + DMAC_mode_reserved_v = 3,
4071 + DMAC_a_b = 4, //
4072 + DMAC_a_m = 0x00000010, //
4073 +
4074 + DMAS_f_b = 0, // finished (sticky)
4075 + DMAS_f_m = 0x00000001, //
4076 + DMAS_d_b = 1, // done (sticky)
4077 + DMAS_d_m = 0x00000002, //
4078 + DMAS_c_b = 2, // chain (sticky)
4079 + DMAS_c_m = 0x00000004, //
4080 + DMAS_e_b = 3, // error (sticky)
4081 + DMAS_e_m = 0x00000008, //
4082 + DMAS_h_b = 4, // halt (sticky)
4083 + DMAS_h_m = 0x00000010, //
4084 +
4085 + DMASM_f_b = 0, // finished (1=mask)
4086 + DMASM_f_m = 0x00000001, //
4087 + DMASM_d_b = 1, // done (1=mask)
4088 + DMASM_d_m = 0x00000002, //
4089 + DMASM_c_b = 2, // chain (1=mask)
4090 + DMASM_c_m = 0x00000004, //
4091 + DMASM_e_b = 3, // error (1=mask)
4092 + DMASM_e_m = 0x00000008, //
4093 + DMASM_h_b = 4, // halt (1=mask)
4094 + DMASM_h_m = 0x00000010, //
4095 +} ;
4096 +
4097 +/*
4098 + * DMA channel definitions
4099 + */
4100 +
4101 +enum
4102 +{
4103 + DMACH_ethRcv0 = 0,
4104 + DMACH_ethXmt0 = 1,
4105 + DMACH_ethRcv1 = 2,
4106 + DMACH_ethXmt2 = 3,
4107 + DMACH_pciToMem = 4,
4108 + DMACH_memToPci = 5,
4109 + DMACH_securityInput = 6,
4110 + DMACH_securityOutput = 7,
4111 + DMACH_rng = 8,
4112 +
4113 + DMACH_count //must be last
4114 +};
4115 +
4116 +
4117 +typedef struct DMAC_s
4118 +{
4119 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
4120 +} volatile *DMA_t ;
4121 +
4122 +
4123 +/*
4124 + * External DMA parameters
4125 +*/
4126 +
4127 +enum
4128 +{
4129 + DMADEVCMD_ts_b = 0, // ts field in devcmd
4130 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
4131 + DMADEVCMD_ts_byte_v = 0,
4132 + DMADEVCMD_ts_halfword_v = 1,
4133 + DMADEVCMD_ts_word_v = 2,
4134 + DMADEVCMD_ts_2word_v = 3,
4135 + DMADEVCMD_ts_4word_v = 4,
4136 + DMADEVCMD_ts_6word_v = 5,
4137 + DMADEVCMD_ts_8word_v = 6,
4138 + DMADEVCMD_ts_16word_v = 7
4139 +};
4140 +
4141 +
4142 +#if 1 // aws - Compatibility.
4143 +# define EXTDMA_ts_b DMADEVCMD_ts_b
4144 +# define EXTDMA_ts_m DMADEVCMD_ts_m
4145 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
4146 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
4147 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
4148 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
4149 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
4150 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
4151 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
4152 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
4153 +#endif // aws - Compatibility.
4154 +
4155 +#endif // __IDT_RC32365_DMA_H__
4156 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h
4157 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 1970-01-01 01:00:00.000000000 +0100
4158 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 2006-03-20 14:25:10.000000000 +0100
4159 @@ -0,0 +1,86 @@
4160 +/**************************************************************************
4161 + *
4162 + * BRIEF MODULE DESCRIPTION
4163 + * RC32365/336 DMA interface routines.
4164 + *
4165 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4166 + *
4167 + * This program is free software; you can redistribute it and/or modify it
4168 + * under the terms of the GNU General Public License as published by the
4169 + * Free Software Foundation; either version 2 of the License, or (at your
4170 + * option) any later version.
4171 + *
4172 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4173 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4174 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4175 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4176 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4177 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4178 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4179 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4180 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4181 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4182 + *
4183 + * You should have received a copy of the GNU General Public License along
4184 + * with this program; if not, write to the Free Software Foundation, Inc.,
4185 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4186 + *
4187 + *
4188 + **************************************************************************
4189 + * May 2004 P. Sadik.
4190 + *
4191 + * Initial Release
4192 + *
4193 + *
4194 + *
4195 + **************************************************************************
4196 + */
4197 +
4198 +#ifndef __IDT_RC32365_DMA_V_H__
4199 +#define __IDT_RC32365_DMA_V_H__
4200 +
4201 +
4202 +#include <asm/idt-boards/rc32300/rc32300.h>
4203 +#include <asm/idt-boards/rc32300/rc32365_dma.h>
4204 +#include <asm/idt-boards/rc32300/rc32365.h>
4205 +
4206 +#define DMA_CHAN_OFFSET 0x14
4207 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
4208 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
4209 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
4210 +
4211 +#define DMA_COUNT(count) \
4212 + ((count) & DMAD_count_m)
4213 +
4214 +#define DMA_HALT_TIMEOUT 500
4215 +
4216 +static inline int rc32365_halt_dma(DMA_Chan_t ch)
4217 +{
4218 + int timeout=1;
4219 + if (local_readl(&ch->dmac) & DMAC_run_m) {
4220 + local_writel(0, &ch->dmac);
4221 +
4222 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
4223 + if (local_readl(&ch->dmas) & DMAS_h_m) {
4224 + local_writel(0, &ch->dmas);
4225 + break;
4226 + }
4227 + }
4228 +
4229 + }
4230 +
4231 + return timeout ? 0 : 1;
4232 +}
4233 +
4234 +
4235 +static inline void rc32365_start_dma(DMA_Chan_t ch, u32 dma_addr)
4236 +{
4237 + local_writel(0, &ch->dmandptr);
4238 + local_writel(dma_addr, &ch->dmadptr);
4239 +}
4240 +
4241 +static inline void rc32365_chain_dma(DMA_Chan_t ch, u32 dma_addr)
4242 +{
4243 + local_writel(dma_addr, &ch->dmandptr);
4244 +}
4245 +#endif //__IDT_RC32365_DMA_V_H__
4246 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_eth.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h
4247 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 1970-01-01 01:00:00.000000000 +0100
4248 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 2006-03-20 14:25:10.000000000 +0100
4249 @@ -0,0 +1,344 @@
4250 +/**************************************************************************
4251 + *
4252 + * BRIEF MODULE DESCRIPTION
4253 + * RC32365/336 Ethernet hardware abstraction.
4254 + *
4255 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4256 + *
4257 + * This program is free software; you can redistribute it and/or modify it
4258 + * under the terms of the GNU General Public License as published by the
4259 + * Free Software Foundation; either version 2 of the License, or (at your
4260 + * option) any later version.
4261 + *
4262 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4263 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4264 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4265 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4266 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4267 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4268 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4269 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4270 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4271 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4272 + *
4273 + * You should have received a copy of the GNU General Public License along
4274 + * with this program; if not, write to the Free Software Foundation, Inc.,
4275 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4276 + *
4277 + *
4278 + **************************************************************************
4279 + * May 2004 P. Sadik.
4280 + *
4281 + * Initial Release
4282 + *
4283 + *
4284 + *
4285 + **************************************************************************
4286 + */
4287 +
4288 +#ifndef __IDT_RC32365_ETH_H__
4289 +#define __IDT_RC32365_ETH_H__
4290 +
4291 +enum
4292 +{
4293 + ETH0_PhysicalAddress = 0x18058000,
4294 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
4295 + ETH0_VirtualAddress = 0xb8058000,
4296 +
4297 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
4298 +
4299 + ETH1_PhysicalAddress = 0x18060000,
4300 + ETH1_VirtualAddress = 0xb8060000, // Default
4301 +} ;
4302 +
4303 +typedef struct
4304 +{
4305 + u32 ethintfc ;
4306 + u32 ethfifott ;
4307 + u32 etharc ;
4308 + u32 ethhash0 ;
4309 + u32 ethhash1 ;
4310 + u32 ethu0 [4] ; // Reserved.
4311 + u32 ethpfs ;
4312 + u32 ethmcp ;
4313 + u32 eth_u1 [10] ; // Reserved.
4314 + u32 ethspare ;
4315 + u32 eth_u2 [42] ; // Reserved.
4316 + u32 ethsal0 ;
4317 + u32 ethsah0 ;
4318 + u32 ethsal1 ;
4319 + u32 ethsah1 ;
4320 + u32 ethsal2 ;
4321 + u32 ethsah2 ;
4322 + u32 ethsal3 ;
4323 + u32 ethsah3 ;
4324 + u32 ethrbc ;
4325 + u32 ethrpc ;
4326 + u32 ethrupc ;
4327 + u32 ethrfc ;
4328 + u32 ethtbc ;
4329 + u32 ethgpf ;
4330 + u32 eth_u9 [50] ; // Reserved.
4331 + u32 ethmac1 ;
4332 + u32 ethmac2 ;
4333 + u32 ethipgt ;
4334 + u32 ethipgr ;
4335 + u32 ethclrt ;
4336 + u32 ethmaxf ;
4337 + u32 eth_u10 ; // Reserved.
4338 + u32 ethmtest ;
4339 + u32 miimcfg ;
4340 + u32 miimcmd ;
4341 + u32 miimaddr ;
4342 + u32 miimwtd ;
4343 + u32 miimrdd ;
4344 + u32 miimind ;
4345 + u32 eth_u11 ; // Reserved.
4346 + u32 eth_u12 ; // Reserved.
4347 + u32 ethcfsa0 ;
4348 + u32 ethcfsa1 ;
4349 + u32 ethcfsa2 ;
4350 +} volatile *ETH_t;
4351 +
4352 +enum
4353 +{
4354 + ETHINTFC_en_b = 0,
4355 + ETHINTFC_en_m = 0x00000001,
4356 + ETHINTFC_its_b = 1,
4357 + ETHINTFC_its_m = 0x00000002,
4358 + ETHINTFC_rip_b = 2,
4359 + ETHINTFC_rip_m = 0x00000004,
4360 + ETHINTFC_jam_b = 3,
4361 + ETHINTFC_jam_m = 0x00000008,
4362 + ETHINTFC_ovr_b = 4,
4363 + ETHINTFC_ovr_m = 0x00000010,
4364 + ETHINTFC_und_b = 5,
4365 + ETHINTFC_und_m = 0x00000020,
4366 +
4367 + ETHFIFOTT_tth_b = 0,
4368 + ETHFIFOTT_tth_m = 0x0000007f,
4369 +
4370 + ETHARC_pro_b = 0,
4371 + ETHARC_pro_m = 0x00000001,
4372 + ETHARC_am_b = 1,
4373 + ETHARC_am_m = 0x00000002,
4374 + ETHARC_afm_b = 2,
4375 + ETHARC_afm_m = 0x00000004,
4376 + ETHARC_ab_b = 3,
4377 + ETHARC_ab_m = 0x00000008,
4378 +
4379 + ETHSAL_byte5_b = 0,
4380 + ETHSAL_byte5_m = 0x000000ff,
4381 + ETHSAL_byte4_b = 8,
4382 + ETHSAL_byte4_m = 0x0000ff00,
4383 + ETHSAL_byte3_b = 16,
4384 + ETHSAL_byte3_m = 0x00ff0000,
4385 + ETHSAL_byte2_b = 24,
4386 + ETHSAL_byte2_m = 0xff000000,
4387 +
4388 + ETHSAH_byte1_b = 0,
4389 + ETHSAH_byte1_m = 0x000000ff,
4390 + ETHSAH_byte0_b = 8,
4391 + ETHSAH_byte0_m = 0x0000ff00,
4392 +
4393 + ETHGPF_ptv_b = 0,
4394 + ETHGPF_ptv_m = 0x0000ffff,
4395 +
4396 + ETHPFS_pfd_b = 0,
4397 + ETHPFS_pfd_m = 0x00000001,
4398 +
4399 + ETHCFSA0_cfsa4_b = 0,
4400 + ETHCFSA0_cfsa4_m = 0x000000ff,
4401 + ETHCFSA0_cfsa5_b = 8,
4402 + ETHCFSA0_cfsa5_m = 0x0000ff00,
4403 +
4404 + ETHCFSA1_cfsa2_b = 0,
4405 + ETHCFSA1_cfsa2_m = 0x000000ff,
4406 + ETHCFSA1_cfsa3_b = 8,
4407 + ETHCFSA1_cfsa3_m = 0x0000ff00,
4408 +
4409 + ETHCFSA2_cfsa0_b = 0,
4410 + ETHCFSA2_cfsa0_m = 0x000000ff,
4411 + ETHCFSA2_cfsa1_b = 8,
4412 + ETHCFSA2_cfsa1_m = 0x0000ff00,
4413 +
4414 + ETHMAC1_re_b = 0,
4415 + ETHMAC1_re_m = 0x00000001,
4416 + ETHMAC1_paf_b = 1,
4417 + ETHMAC1_paf_m = 0x00000002,
4418 + ETHMAC1_rfc_b = 2,
4419 + ETHMAC1_rfc_m = 0x00000004,
4420 + ETHMAC1_tfc_b = 3,
4421 + ETHMAC1_tfc_m = 0x00000008,
4422 + ETHMAC1_lb_b = 4,
4423 + ETHMAC1_lb_m = 0x00000010,
4424 + ETHMAC1_mr_b = 31,
4425 + ETHMAC1_mr_m = 0x80000000,
4426 +
4427 + ETHMAC2_fd_b = 0,
4428 + ETHMAC2_fd_m = 0x00000001,
4429 + ETHMAC2_flc_b = 1,
4430 + ETHMAC2_flc_m = 0x00000002,
4431 + ETHMAC2_hfe_b = 2,
4432 + ETHMAC2_hfe_m = 0x00000004,
4433 + ETHMAC2_dc_b = 3,
4434 + ETHMAC2_dc_m = 0x00000008,
4435 + ETHMAC2_cen_b = 4,
4436 + ETHMAC2_cen_m = 0x00000010,
4437 + ETHMAC2_pe_b = 5,
4438 + ETHMAC2_pe_m = 0x00000020,
4439 + ETHMAC2_vpe_b = 6,
4440 + ETHMAC2_vpe_m = 0x00000040,
4441 + ETHMAC2_ape_b = 7,
4442 + ETHMAC2_ape_m = 0x00000080,
4443 + ETHMAC2_ppe_b = 8,
4444 + ETHMAC2_ppe_m = 0x00000100,
4445 + ETHMAC2_lpe_b = 9,
4446 + ETHMAC2_lpe_m = 0x00000200,
4447 + ETHMAC2_nb_b = 12,
4448 + ETHMAC2_nb_m = 0x00001000,
4449 + ETHMAC2_bp_b = 13,
4450 + ETHMAC2_bp_m = 0x00002000,
4451 + ETHMAC2_ed_b = 14,
4452 + ETHMAC2_ed_m = 0x00004000,
4453 +
4454 + ETHIPGT_ipgt_b = 0,
4455 + ETHIPGT_ipgt_m = 0x0000007f,
4456 +
4457 + ETHIPGR_ipgr2_b = 0,
4458 + ETHIPGR_ipgr2_m = 0x0000007f,
4459 + ETHIPGR_ipgr1_b = 8,
4460 + ETHIPGR_ipgr1_m = 0x00007f00,
4461 +
4462 + ETHCLRT_maxret_b = 0,
4463 + ETHCLRT_maxret_m = 0x0000000f,
4464 + ETHCLRT_colwin_b = 8,
4465 + ETHCLRT_colwin_m = 0x00003f00,
4466 +
4467 + ETHMAXF_maxf_b = 0,
4468 + ETHMAXF_maxf_m = 0x0000ffff,
4469 +
4470 + ETHMTEST_tb_b = 2,
4471 + ETHMTEST_tb_m = 0x00000004,
4472 +
4473 + ETHMCP_div_b = 0,
4474 + ETHMCP_div_m = 0x000000ff,
4475 +
4476 + MIIMCFG_rsv_b = 0,
4477 + MIIMCFG_rsv_m = 0x0000000c,
4478 +
4479 + MIIMCMD_rd_b = 0,
4480 + MIIMCMD_rd_m = 0x00000001,
4481 + MIIMCMD_scn_b = 1,
4482 + MIIMCMD_scn_m = 0x00000002,
4483 +
4484 + MIIMADDR_regaddr_b = 0,
4485 + MIIMADDR_regaddr_m = 0x0000001f,
4486 + MIIMADDR_phyaddr_b = 8,
4487 + MIIMADDR_phyaddr_m = 0x00001f00,
4488 +
4489 + MIIMWTD_wdata_b = 0,
4490 + MIIMWTD_wdata_m = 0x0000ffff,
4491 +
4492 + MIIMRDD_rdata_b = 0,
4493 + MIIMRDD_rdata_m = 0x0000ffff,
4494 +
4495 + MIIMIND_bsy_b = 0,
4496 + MIIMIND_bsy_m = 0x00000001,
4497 + MIIMIND_scn_b = 1,
4498 + MIIMIND_scn_m = 0x00000002,
4499 + MIIMIND_nv_b = 2,
4500 + MIIMIND_nv_m = 0x00000004,
4501 +
4502 +} ;
4503 +
4504 +/*
4505 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
4506 + */
4507 +enum
4508 +{
4509 + ETHRX_fd_b = 0,
4510 + ETHRX_fd_m = 0x00000001,
4511 + ETHRX_ld_b = 1,
4512 + ETHRX_ld_m = 0x00000002,
4513 + ETHRX_rok_b = 2,
4514 + ETHRX_rok_m = 0x00000004,
4515 + ETHRX_fm_b = 3,
4516 + ETHRX_fm_m = 0x00000008,
4517 + ETHRX_mp_b = 4,
4518 + ETHRX_mp_m = 0x00000010,
4519 + ETHRX_bp_b = 5,
4520 + ETHRX_bp_m = 0x00000020,
4521 + ETHRX_vlt_b = 6,
4522 + ETHRX_vlt_m = 0x00000040,
4523 + ETHRX_cf_b = 7,
4524 + ETHRX_cf_m = 0x00000080,
4525 + ETHRX_ovr_b = 8,
4526 + ETHRX_ovr_m = 0x00000100,
4527 + ETHRX_crc_b = 9,
4528 + ETHRX_crc_m = 0x00000200,
4529 + ETHRX_cv_b = 10,
4530 + ETHRX_cv_m = 0x00000400,
4531 + ETHRX_db_b = 11,
4532 + ETHRX_db_m = 0x00000800,
4533 + ETHRX_le_b = 12,
4534 + ETHRX_le_m = 0x00001000,
4535 + ETHRX_lor_b = 13,
4536 + ETHRX_lor_m = 0x00002000,
4537 + ETHRX_ces_b = 14,
4538 + ETHRX_ces_m = 0x00004000,
4539 + ETHRX_length_b = 16,
4540 + ETHRX_length_m = 0xffff0000,
4541 +
4542 + ETHTX_fd_b = 0,
4543 + ETHTX_fd_m = 0x00000001,
4544 + ETHTX_ld_b = 1,
4545 + ETHTX_ld_m = 0x00000002,
4546 + ETHTX_oen_b = 2,
4547 + ETHTX_oen_m = 0x00000004,
4548 + ETHTX_pen_b = 3,
4549 + ETHTX_pen_m = 0x00000008,
4550 + ETHTX_cen_b = 4,
4551 + ETHTX_cen_m = 0x00000010,
4552 + ETHTX_hen_b = 5,
4553 + ETHTX_hen_m = 0x00000020,
4554 + ETHTX_tok_b = 6,
4555 + ETHTX_tok_m = 0x00000040,
4556 + ETHTX_mp_b = 7,
4557 + ETHTX_mp_m = 0x00000080,
4558 + ETHTX_bp_b = 8,
4559 + ETHTX_bp_m = 0x00000100,
4560 + ETHTX_und_b = 9,
4561 + ETHTX_und_m = 0x00000200,
4562 + ETHTX_of_b = 10,
4563 + ETHTX_of_m = 0x00000400,
4564 + ETHTX_ed_b = 11,
4565 + ETHTX_ed_m = 0x00000800,
4566 + ETHTX_ec_b = 12,
4567 + ETHTX_ec_m = 0x00001000,
4568 + ETHTX_lc_b = 13,
4569 + ETHTX_lc_m = 0x00002000,
4570 + ETHTX_td_b = 14,
4571 + ETHTX_td_m = 0x00004000,
4572 + ETHTX_crc_b = 15,
4573 + ETHTX_crc_m = 0x00008000,
4574 + ETHTX_le_b = 16,
4575 + ETHTX_le_m = 0x00010000,
4576 + ETHTX_cc_b = 17,
4577 + ETHTX_cc_m = 0x001E0000,
4578 +} ;
4579 +
4580 +enum
4581 +{
4582 + ETH0_IPABMC_PhysicalAddress = 0x18040010,
4583 + ETH0_IPABMC_VirtualAddress = 0xb8040000,
4584 + ETH1_IPABMC_PhysicalAddress = 0x18040018,
4585 + ETH1_IPABMC_VirtualAddress = 0xb8040018,
4586 +} ;
4587 +
4588 +typedef struct
4589 +{
4590 + u32 ipabmcrx ;
4591 + u32 ipabmctx ;
4592 +}volatile *IPABM_ETH_t;
4593 +#endif //__IDT_RC32365_ETH_H__
4594 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h
4595 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h 1970-01-01 01:00:00.000000000 +0100
4596 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h 2006-03-20 14:25:10.000000000 +0100
4597 @@ -0,0 +1,72 @@
4598 +/**************************************************************************
4599 + *
4600 + * BRIEF MODULE DESCRIPTION
4601 + * RC32365/336 Ethernet status checking.
4602 + *
4603 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4604 + *
4605 + * This program is free software; you can redistribute it and/or modify it
4606 + * under the terms of the GNU General Public License as published by the
4607 + * Free Software Foundation; either version 2 of the License, or (at your
4608 + * option) any later version.
4609 + *
4610 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4611 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4612 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4613 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4614 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4615 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4616 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4617 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4618 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4619 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4620 + *
4621 + * You should have received a copy of the GNU General Public License along
4622 + * with this program; if not, write to the Free Software Foundation, Inc.,
4623 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4624 + *
4625 + *
4626 + **************************************************************************
4627 + * May 2004 P. Sadik.
4628 + *
4629 + * Initial Release
4630 + *
4631 + *
4632 + *
4633 + **************************************************************************
4634 + */
4635 +
4636 +#ifndef __IDT_RC32365_ETH_V_H__
4637 +#define __IDT_RC32365_ETH_V_H__
4638 +#include <asm/idt-boards/rc32300/rc32365_eth.h>
4639 +
4640 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
4641 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
4642 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
4643 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
4644 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
4645 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
4646 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
4647 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
4648 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
4649 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
4650 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
4651 +
4652 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
4653 +
4654 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
4655 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
4656 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
4657 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
4658 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
4659 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
4660 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
4661 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
4662 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
4663 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
4664 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
4665 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
4666 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
4667 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
4668 +
4669 +#endif //__IDT_RC32365_ETH_V_H__
4670 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h
4671 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h 1970-01-01 01:00:00.000000000 +0100
4672 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h 2006-03-20 14:25:10.000000000 +0100
4673 @@ -0,0 +1,181 @@
4674 +/**************************************************************************
4675 + *
4676 + * BRIEF MODULE DESCRIPTION
4677 + * RC32365/336 GPIO hardware abstraction.
4678 + *
4679 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4680 + *
4681 + * This program is free software; you can redistribute it and/or modify it
4682 + * under the terms of the GNU General Public License as published by the
4683 + * Free Software Foundation; either version 2 of the License, or (at your
4684 + * option) any later version.
4685 + *
4686 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4687 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4688 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4689 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4690 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4691 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4692 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4693 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4694 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4695 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4696 + *
4697 + * You should have received a copy of the GNU General Public License along
4698 + * with this program; if not, write to the Free Software Foundation, Inc.,
4699 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4700 + *
4701 + *
4702 + **************************************************************************
4703 + * May 2004 P. Sadik.
4704 + *
4705 + * Initial Release
4706 + *
4707 + *
4708 + *
4709 + **************************************************************************
4710 + */
4711 +
4712 +#ifndef __IDT_RC32365_GPIO_H__
4713 +#define __IDT_RC32365_GPIO_H__
4714 +
4715 +enum
4716 +{
4717 + GPIO0_PhysicalAddress = 0x18048000,
4718 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
4719 +
4720 + GPIO0_VirtualAddress = 0xb8048000,
4721 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
4722 +} ;
4723 +
4724 +typedef struct
4725 +{
4726 + u32 gpiofunc; /* GPIO Function Register
4727 + * gpiofunc[x]==0 bit = gpio
4728 + * func[x]==1 bit = altfunc
4729 + */
4730 + u32 gpiocfg; /* GPIO Configuration Register
4731 + * gpiocfg[x]==0 bit = input
4732 + * gpiocfg[x]==1 bit = output
4733 + */
4734 + u32 gpiod; /* GPIO Data Register
4735 + * gpiod[x] read/write gpio pinX status
4736 + */
4737 + u32 gpioilevel; /* GPIO Interrupt Status Register
4738 + * interrupt level (see gpioistat)
4739 + */
4740 + u32 gpioistat; /* Gpio Interrupt Status Register
4741 + * istat[x] = (gpiod[x] == level[x])
4742 + * cleared in ISR (STICKY bits)
4743 + */
4744 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
4745 +} volatile * GPIO_t ;
4746 +
4747 +typedef enum
4748 +{
4749 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
4750 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
4751 + GPIO_input_v = 0, // gpiocfg use pin as input.
4752 + GPIO_output_v = 1, // gpiocfg use pin as output.
4753 + GPIO_pin0_b = 0,
4754 + GPIO_pin0_m = 0x00000001,
4755 + GPIO_pin1_b = 1,
4756 + GPIO_pin1_m = 0x00000002,
4757 + GPIO_pin2_b = 2,
4758 + GPIO_pin2_m = 0x00000004,
4759 + GPIO_pin3_b = 3,
4760 + GPIO_pin3_m = 0x00000008,
4761 + GPIO_pin4_b = 4,
4762 + GPIO_pin4_m = 0x00000010,
4763 + GPIO_pin5_b = 5,
4764 + GPIO_pin5_m = 0x00000020,
4765 + GPIO_pin6_b = 6,
4766 + GPIO_pin6_m = 0x00000040,
4767 + GPIO_pin7_b = 7,
4768 + GPIO_pin7_m = 0x00000080,
4769 + GPIO_pin8_b = 8,
4770 + GPIO_pin8_m = 0x00000100,
4771 + GPIO_pin9_b = 9,
4772 + GPIO_pin9_m = 0x00000200,
4773 + GPIO_pin10_b = 10,
4774 + GPIO_pin10_m = 0x00000400,
4775 + GPIO_pin11_b = 11,
4776 + GPIO_pin11_m = 0x00000800,
4777 + GPIO_pin12_b = 12,
4778 + GPIO_pin12_m = 0x00001000,
4779 + GPIO_pin13_b = 13,
4780 + GPIO_pin13_m = 0x00002000,
4781 + GPIO_pin14_b = 14,
4782 + GPIO_pin14_m = 0x00004000,
4783 + GPIO_pin15_b = 15,
4784 + GPIO_pin15_m = 0x00008000,
4785 +
4786 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
4787 +
4788 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
4789 + GPIO_u0sout_m = GPIO_pin0_m,
4790 + GPIO_u0sout_cfg_v = GPIO_output_v,
4791 +
4792 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
4793 + GPIO_u0sinp_m = GPIO_pin1_m,
4794 + GPIO_u0sinp_cfg_v = GPIO_input_v,
4795 +
4796 + GPIO_maddr22_b = GPIO_pin2_b, // M&P bus bit 22.
4797 + GPIO_maddr22_m = GPIO_pin2_m,
4798 + GPIO_maddr22_cfg_v = GPIO_output_v,
4799 +
4800 + GPIO_maddr23_b = GPIO_pin3_b, // M&P bus bit 23.
4801 + GPIO_maddr23_m = GPIO_pin3_m,
4802 + GPIO_maddr23_cfg_v = GPIO_output_v,
4803 +
4804 + GPIO_maddr24_b = GPIO_pin4_b, // M&P bus bit 24.
4805 + GPIO_maddr24_m = GPIO_pin4_m,
4806 + GPIO_maddr24_cfg_v = GPIO_output_v,
4807 +
4808 + GPIO_maddr25_b = GPIO_pin5_b, // M&P bus bit 25.
4809 + GPIO_maddr25_m = GPIO_pin5_m,
4810 + GPIO_maddr25_cfg_v = GPIO_output_v,
4811 +
4812 + GPIO_rngclk_b = GPIO_pin6_b, // reserved.
4813 + GPIO_rngclk_m = GPIO_pin6_m,
4814 + GPIO_rngclk_cfg_v = GPIO_input_v,
4815 +
4816 + GPIO_sdckenp_b = GPIO_pin7_b, // reserved.
4817 + GPIO_sdckenp_m = GPIO_pin7_m,
4818 + GPIO_sdckenp_cfg_v = GPIO_output_v,
4819 +
4820 + GPIO_cen1_b = GPIO_pin8_b, // reserved.
4821 + GPIO_cen1_m = GPIO_pin8_m,
4822 + GPIO_cen1_cfg_v = GPIO_output_v,
4823 +
4824 + GPIO_cen2_b = GPIO_pin9_b, // reserved.
4825 + GPIO_cen2_m = GPIO_pin9_m,
4826 + GPIO_cen2_cfg_v = GPIO_output_v,
4827 +
4828 + GPIO_regn_b = GPIO_pin10_b, // reserved.
4829 + GPIO_regn_m = GPIO_pin10_m,
4830 + GPIO_regn_cfg_v = GPIO_output_v,
4831 +
4832 + GPIO_iordn_b = GPIO_pin11_b, // reserved.
4833 + GPIO_iordn_m = GPIO_pin11_m,
4834 + GPIO_iordn_cfg_v = GPIO_output_v,
4835 +
4836 + GPIO_iowrn_b = GPIO_pin12_b, // reserved.
4837 + GPIO_iowrn_m = GPIO_pin12_m,
4838 + GPIO_iowrn_cfg_v = GPIO_output_v,
4839 +
4840 + GPIO_pcireqn2_b = GPIO_pin13_b, // PCI messaging int.
4841 + GPIO_pcireqn2_m = GPIO_pin13_m,
4842 + GPIO_pcireqn2_cfg_v = GPIO_input_v,
4843 +
4844 + GPIO_pcigntn2_b = GPIO_pin14_b, // PCI messaging int.
4845 + GPIO_pcigntn2_m = GPIO_pin14_m,
4846 + GPIO_pcigntn2_cfg_v = GPIO_output_v,
4847 +
4848 + GPIO_pcimuintn_b = GPIO_pin15_b, // PCI messaging int.
4849 + GPIO_pcimuintn_m = GPIO_pin15_m,
4850 + GPIO_pcimuintn_cfg_v= GPIO_output_v,
4851 +
4852 +} GPIO_DEFS_t;
4853 +
4854 +#endif //__IDT_RC32365_GPIO_H__
4855 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h
4856 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h 1970-01-01 01:00:00.000000000 +0100
4857 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h 2006-03-20 14:25:10.000000000 +0100
4858 @@ -0,0 +1,91 @@
4859 +/**************************************************************************
4860 + *
4861 + * BRIEF MODULE DESCRIPTION
4862 + * Routines to set/clear/toggle GPIO on RC32365
4863 + *
4864 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4865 + *
4866 + * This program is free software; you can redistribute it and/or modify it
4867 + * under the terms of the GNU General Public License as published by the
4868 + * Free Software Foundation; either version 2 of the License, or (at your
4869 + * option) any later version.
4870 + *
4871 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4872 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4873 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4874 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4875 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4876 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4877 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4878 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4879 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4880 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4881 + *
4882 + * You should have received a copy of the GNU General Public License along
4883 + * with this program; if not, write to the Free Software Foundation, Inc.,
4884 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4885 + *
4886 + *
4887 + **************************************************************************
4888 + * May 2004 P. Sadik.
4889 + *
4890 + * Initial Release
4891 + *
4892 + *
4893 + *
4894 + **************************************************************************
4895 + */
4896 +#ifndef __IDT_RC32365_GPIO_V_H__
4897 +#define __IDT_RC32365_GPIO_V_H__
4898 +
4899 +
4900 +#ifdef _LANGUAGE_ASSEMBLY
4901 +#define SET_GPIO(pin) \
4902 + lui t5,0xb804 ; \
4903 + ori t5,t5,0x8000 ; \
4904 + lw t4,8(t5) ; \
4905 + ori t4,t4,pin ; \
4906 + sw t4,8(t5) ;
4907 +
4908 +#define CLEAR_GPIO(pin) \
4909 + lui t5,0xb804 ; \
4910 + ori t5,t5,0x8000 ; \
4911 + lw t4,8(t5) ; \
4912 + lui t6,0xFFFF; \
4913 + ori t6,t6,0xFFFF; \
4914 + xori t6,t6,pin ; \
4915 + and t4,t6 ; \
4916 + sw t4,8(t5) ;
4917 +
4918 +#define TOGGLE_GPIO(pin) \
4919 + lui t5,0xb804 ; \
4920 + ori t5,t5,0x8000 ; \
4921 + lw t4,8(t5) ; \
4922 + xori t4,t4,pin ; \
4923 + sw t4,8(t5) ;
4924 +
4925 +#else // !_LANGUAGE_ASSEMBLY
4926 +#include <asm/rc32300/types.h>
4927 +#include <asm/rc32300/rc32365_gpio.h>
4928 +#include <asm/rc32300/rc32365.h>
4929 +
4930 +static inline void set_gpio(unsigned long pin)
4931 +{
4932 + idt_gpio->gpiod |= pin;
4933 +}
4934 +
4935 +static inline void clear_gpio(unsigned long pin)
4936 +{
4937 + idt_gpio->gpiod &= ~pin;
4938 +}
4939 +static inline void toggle_gpio(unsigned long pin)
4940 +{
4941 + idt_gpio->gpiod ^= pin;
4942 +}
4943 +#define SET_GPIO(pin) set_gpio(pin)
4944 +#define CLEAR_GPIO(pin) clear_gpio(pin)
4945 +#define TOGGLE_GPIO(pin) toggle_gpio(pin)
4946 +#endif // _LANGUAGE_ASSEMBLY
4947 +
4948 +#endif //__IDT_RC32365_GPIO_V_H__
4949 +
4950 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365.h
4951 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365.h 1970-01-01 01:00:00.000000000 +0100
4952 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365.h 2006-03-20 14:25:10.000000000 +0100
4953 @@ -0,0 +1,160 @@
4954 +/**************************************************************************
4955 + *
4956 + * BRIEF MODULE DESCRIPTION
4957 + * Definitions for IDT RC32365 CPU.
4958 + *
4959 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4960 + *
4961 + * This program is free software; you can redistribute it and/or modify it
4962 + * under the terms of the GNU General Public License as published by the
4963 + * Free Software Foundation; either version 2 of the License, or (at your
4964 + * option) any later version.
4965 + *
4966 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4967 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4968 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4969 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4970 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4971 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4972 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4973 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4974 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4975 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4976 + *
4977 + * You should have received a copy of the GNU General Public License along
4978 + * with this program; if not, write to the Free Software Foundation, Inc.,
4979 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4980 + *
4981 + *
4982 + **************************************************************************
4983 + * May 2004 P. Sadik.
4984 + *
4985 + * Initial Release
4986 + *
4987 + *
4988 + *
4989 + **************************************************************************
4990 + */
4991 +
4992 +#ifndef __IDT_RC32365_H__
4993 +#define __IDT_RC32365_H__
4994 +
4995 +extern unsigned int cedar_za;
4996 +
4997 +/* Base address of internal registers */
4998 +#define RC32365_REG_BASE 0x18000000
4999 +
5000 +/* System ID Registers */
5001 +#define CPU_SYSID (RC32365_REG_BASE + 0x00018)
5002 +#define CPU_DEVTYPE (RC32365_REG_BASE + 0x0001c)
5003 +
5004 +/* Reset Controller */
5005 +#define RESET_CNTL (RC32365_REG_BASE + 0x08000)
5006 +#define BOOT_VECTOR (RC32365_REG_BASE + 0x08004)
5007 +
5008 +/* Device Controller */
5009 +#define DEV0_BASE (RC32365_REG_BASE + 0x10000)
5010 +#define DEV0_MASK (RC32365_REG_BASE + 0x10004)
5011 +#define DEV0_CNTL (RC32365_REG_BASE + 0x10008)
5012 +#define DEV0_TIMING (RC32365_REG_BASE + 0x1000c)
5013 +#define DEV_REG_OFFSET 0x10
5014 +
5015 +/* SDRAM Controller */
5016 +#define SDRAM0_BASE (RC32365_REG_BASE + 0x18000)
5017 +#define SDRAM0_MASK (RC32365_REG_BASE + 0x18004)
5018 +#define SDRAM1_BASE (RC32365_REG_BASE + 0x18008)
5019 +#define SDRAM1_MASK (RC32365_REG_BASE + 0x1800c)
5020 +#define SDRAM_CNTL (RC32365_REG_BASE + 0x18010)
5021 +
5022 +/* Counters/Timers */
5023 +#define TIMER0_COUNT (RC32365_REG_BASE + 0x20000)
5024 +#define TIMER0_COMPARE (RC32365_REG_BASE + 0x20004)
5025 +#define TIMER0_CNTL (RC32365_REG_BASE + 0x20008)
5026 +#define TIMER0_SELECT (RC32365_REG_BASE + 0x2000c)
5027 +#define TIMER_REG_OFFSET 0x10
5028 +
5029 +/* System Integrity */
5030 +
5031 +/* Interrupt Controller */
5032 +#define IC_GROUP0_PEND (RC32365_REG_BASE + 0x30000)
5033 +#define IC_GROUP0_TEST (RC32365_REG_BASE + 0x30004)
5034 +#define IC_GROUP0_MASK (RC32365_REG_BASE + 0x30008)
5035 +#define IC_GROUP_OFFSET 0x0c
5036 +
5037 +#define NUM_INTR_GROUPS 5
5038 +/*
5039 + * The IRQ mapping is as follows:
5040 + *
5041 + * IRQ Mapped To
5042 + * --- -------------------
5043 + * 0 SW0 (IP0) SW0 intr
5044 + * 1 SW1 (IP1) SW1 intr
5045 + * - Int0 (IP2) mapped to GROUP0_IRQ_BASE
5046 + * - Int1 (IP3) mapped to GROUP1_IRQ_BASE
5047 + * - Int2 (IP4) mapped to GROUP2_IRQ_BASE
5048 + * - Int3 (IP5) mapped to GROUP3_IRQ_BASE
5049 + * - Int4 (IP6) mapped to GROUP4_IRQ_BASE
5050 + * 7 Int5 (IP7) CP0 Timer
5051 + *
5052 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
5053 + * internally on the RC32365 is routed to the Expansion
5054 + * Interrupt Controller.
5055 + */
5056 +#define MIPS_CPU_TIMER_IRQ 7
5057 +
5058 +#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
5059 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) // DMA
5060 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) // RNG, SEC
5061 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) // Eth, PCI, UARTs
5062 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) // GPIO
5063 +
5064 +#define RC32365_NR_IRQS (GROUP4_IRQ_BASE + 32)
5065 +
5066 +/* DMA - see rc32365_dma.h for full list of registers */
5067 +
5068 +#define RC32365_DMA_BASE (RC32365_REG_BASE + 0x38000)
5069 +#define DMA_CHAN_OFFSET 0x14
5070 +
5071 +/* GPIO Controller */
5072 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
5073 +
5074 +/* 16550 UARTs */
5075 +#ifdef __MIPSEB__
5076 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50003)
5077 +#else
5078 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50000)
5079 +#endif
5080 +#define RC32300_UART0_IRQ (GROUP3_IRQ_BASE + 0)
5081 +
5082 +/* Ethernet - see rc32365_eth.h for full list of registers */
5083 +
5084 +#define RC32365_ETH_BASE (RC32365_REG_BASE + 0x58000)
5085 +
5086 +#define IDT_CLOCK_MULT 2
5087 +
5088 +/* FLASH (device 1) */
5089 +#define FLASH_BASE 0x08000000
5090 +#define FLASH_SIZE 0x00800000
5091 +
5092 +/* LCD 4-digit display (device 2) */
5093 +#define LCD_DIGIT0 0x0C000003
5094 +#define LCD_DIGIT1 0x0C000002
5095 +#define LCD_DIGIT2 0x0C000001
5096 +#define LCD_DIGIT3 0x0C000000
5097 +
5098 +/* RTC (DS1553) (device 2) */
5099 +#define RTC_BASE 0x0c800000
5100 +/* NVRAM */
5101 +#define NVRAM_BASE RTC_BASE
5102 +#define NVRAM_ENVSIZE_OFF 4
5103 +#define NVRAM_ENVSTART_OFF 32
5104 +
5105 +/* Interrupts routed on 79EB365 board */
5106 +#define RC32365_PCI_INTA_IRQ (GROUP4_IRQ_BASE + 8)
5107 +#define RC32365_PCI_INTB_IRQ (GROUP4_IRQ_BASE + 9)
5108 +#define RC32365_PCI_INTC_IRQ (GROUP4_IRQ_BASE + 10)
5109 +#define RC32365_PCI_INTD_IRQ (GROUP4_IRQ_BASE + 11)
5110 +
5111 +#define RAM_SIZE (32 * 1024 * 1024)
5112 +
5113 +#endif //__IDT_RC32365_H__
5114 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_pci.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h
5115 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 1970-01-01 01:00:00.000000000 +0100
5116 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 2006-03-20 14:25:10.000000000 +0100
5117 @@ -0,0 +1,515 @@
5118 +/**************************************************************************
5119 + *
5120 + * BRIEF MODULE DESCRIPTION
5121 + * Datatype declaration for IDT 79EB365/336 PCI
5122 + *
5123 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5124 + *
5125 + * This program is free software; you can redistribute it and/or modify it
5126 + * under the terms of the GNU General Public License as published by the
5127 + * Free Software Foundation; either version 2 of the License, or (at your
5128 + * option) any later version.
5129 + *
5130 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5131 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5132 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5133 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5134 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5135 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5136 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5137 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5138 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5139 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5140 + *
5141 + * You should have received a copy of the GNU General Public License along
5142 + * with this program; if not, write to the Free Software Foundation, Inc.,
5143 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5144 + *
5145 + *
5146 + **************************************************************************
5147 + * May 2004 P. Sadik.
5148 + *
5149 + * Initial Release
5150 + *
5151 + *
5152 + *
5153 + **************************************************************************
5154 + */
5155 +
5156 +#ifndef __IDT_RC32365_PCI_H__
5157 +#define __IDT_RC32365_PCI_H__
5158 +
5159 +enum
5160 +{
5161 + PCI0_PhysicalAddress = 0x18068000,
5162 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
5163 +
5164 + PCI0_VirtualAddress = 0xb8068000,
5165 + PCI_VirtualAddress = PCI0_VirtualAddress,
5166 +} ;
5167 +
5168 +enum
5169 +{
5170 + PCI_LbaCount = 4, // Local base addresses.
5171 +} ;
5172 +
5173 +typedef struct
5174 +{
5175 + u32 a ; // Address.
5176 + u32 c ; // Control.
5177 + u32 m ; // mapping.
5178 +} PCI_Map_s ;
5179 +
5180 +typedef struct
5181 +{
5182 + u32 pcic ;
5183 + u32 pcis ;
5184 + u32 pcism ;
5185 + u32 pcicfga ;
5186 + u32 pcicfgd ;
5187 + PCI_Map_s pcilba [PCI_LbaCount] ;
5188 + u32 pcidac ;
5189 + u32 pcidas ;
5190 + u32 pcidasm ;
5191 + u32 pcidad ;
5192 + u32 pcidma8c ;
5193 + u32 pcidma9c ;
5194 + u32 pcitc ;
5195 +} volatile *PCI_t ;
5196 +
5197 +// PCI messaging unit.
5198 +enum
5199 +{
5200 + PCIM_Count = 2,
5201 +} ;
5202 +typedef struct
5203 +{
5204 + u32 pciim [PCIM_Count] ;
5205 + u32 pciom [PCIM_Count] ;
5206 + u32 pciid ;
5207 + u32 pciiic ;
5208 + u32 pciiim ;
5209 + u32 pciiod ;
5210 + u32 pciioic ;
5211 + u32 pciioim ;
5212 +} volatile *PCIM_t ;
5213 +
5214 +/*******************************************************************************
5215 + *
5216 + * PCI Control Register
5217 + *
5218 + ******************************************************************************/
5219 +enum
5220 +{
5221 + PCIC_en_b = 0,
5222 + PCIC_en_m = 0x00000001,
5223 + PCIC_tnr_b = 1,
5224 + PCIC_tnr_m = 0x00000002,
5225 + PCIC_sce_b = 2,
5226 + PCIC_sce_m = 0x00000004,
5227 + PCIC_ien_b = 3,
5228 + PCIC_ien_m = 0x00000008,
5229 + PCIC_aaa_b = 4,
5230 + PCIC_aaa_m = 0x00000010,
5231 + PCIC_eap_b = 5,
5232 + PCIC_eap_m = 0x00000020,
5233 + PCIC_pcim_b = 6,
5234 + PCIC_pcim_m = 0x000001c0,
5235 + PCIC_pcim_disabled_v = 0,
5236 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
5237 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
5238 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
5239 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
5240 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
5241 + PCIC_pcim_reserved6_v = 6,
5242 + PCIC_pcim_reserved7_v = 7,
5243 + PCIC_igm_b = 9,
5244 + PCIC_igm_m = 0x00000200,
5245 +} ;
5246 +
5247 +/*******************************************************************************
5248 + *
5249 + * PCI Status Register
5250 + *
5251 + ******************************************************************************/
5252 +enum {
5253 + PCIS_eed_b = 0,
5254 + PCIS_eed_m = 0x00000001,
5255 + PCIS_wr_b = 1,
5256 + PCIS_wr_m = 0x00000002,
5257 + PCIS_nmi_b = 2,
5258 + PCIS_nmi_m = 0x00000004,
5259 + PCIS_ii_b = 3,
5260 + PCIS_ii_m = 0x00000008,
5261 + PCIS_cwe_b = 4,
5262 + PCIS_cwe_m = 0x00000010,
5263 + PCIS_cre_b = 5,
5264 + PCIS_cre_m = 0x00000020,
5265 + PCIS_mdpe_b = 6,
5266 + PCIS_mdpe_m = 0x00000040,
5267 + PCIS_sta_b = 7,
5268 + PCIS_sta_m = 0x00000080,
5269 + PCIS_rta_b = 8,
5270 + PCIS_rta_m = 0x00000100,
5271 + PCIS_rma_b = 9,
5272 + PCIS_rma_m = 0x00000200,
5273 + PCIS_sse_b = 10,
5274 + PCIS_sse_m = 0x00000400,
5275 + PCIS_ose_b = 11,
5276 + PCIS_ose_m = 0x00000800,
5277 + PCIS_pe_b = 12,
5278 + PCIS_pe_m = 0x00001000,
5279 + PCIS_tae_b = 13,
5280 + PCIS_tae_m = 0x00002000,
5281 + PCIS_rle_b = 14,
5282 + PCIS_rle_m = 0x00004000,
5283 + PCIS_bme_b = 15,
5284 + PCIS_bme_m = 0x00008000,
5285 + PCIS_prd_b = 16,
5286 + PCIS_prd_m = 0x00010000,
5287 + PCIS_rip_b = 17,
5288 + PCIS_rip_m = 0x00020000,
5289 +} ;
5290 +
5291 +/*******************************************************************************
5292 + *
5293 + * PCI Status Mask Register
5294 + *
5295 + ******************************************************************************/
5296 +enum {
5297 + PCISM_eed_b = 0,
5298 + PCISM_eed_m = 0x00000001,
5299 + PCISM_wr_b = 1,
5300 + PCISM_wr_m = 0x00000002,
5301 + PCISM_nmi_b = 2,
5302 + PCISM_nmi_m = 0x00000004,
5303 + PCISM_ii_b = 3,
5304 + PCISM_ii_m = 0x00000008,
5305 + PCISM_cwe_b = 4,
5306 + PCISM_cwe_m = 0x00000010,
5307 + PCISM_cre_b = 5,
5308 + PCISM_cre_m = 0x00000020,
5309 + PCISM_mdpe_b = 6,
5310 + PCISM_mdpe_m = 0x00000040,
5311 + PCISM_sta_b = 7,
5312 + PCISM_sta_m = 0x00000080,
5313 + PCISM_rta_b = 8,
5314 + PCISM_rta_m = 0x00000100,
5315 + PCISM_rma_b = 9,
5316 + PCISM_rma_m = 0x00000200,
5317 + PCISM_sse_b = 10,
5318 + PCISM_sse_m = 0x00000400,
5319 + PCISM_ose_b = 11,
5320 + PCISM_ose_m = 0x00000800,
5321 + PCISM_pe_b = 12,
5322 + PCISM_pe_m = 0x00001000,
5323 + PCISM_tae_b = 13,
5324 + PCISM_tae_m = 0x00002000,
5325 + PCISM_rle_b = 14,
5326 + PCISM_rle_m = 0x00004000,
5327 + PCISM_bme_b = 15,
5328 + PCISM_bme_m = 0x00008000,
5329 + PCISM_prd_b = 16,
5330 + PCISM_prd_m = 0x00010000,
5331 + PCISM_rip_b = 17,
5332 + PCISM_rip_m = 0x00020000,
5333 +} ;
5334 +
5335 +/*******************************************************************************
5336 + *
5337 + * PCI Configuration Address Register
5338 + *
5339 + ******************************************************************************/
5340 +enum {
5341 + PCICFGA_reg_b = 2,
5342 + PCICFGA_reg_m = 0x000000fc,
5343 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
5344 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
5345 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
5346 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
5347 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
5348 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
5349 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
5350 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
5351 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
5352 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
5353 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
5354 + PCICFGA_reg_pba0m_v = 0x48>>2,
5355 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
5356 + PCICFGA_reg_pba1m_v = 0x50>>2,
5357 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
5358 + PCICFGA_reg_pba2m_v = 0x58>>2,
5359 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
5360 + PCICFGA_reg_pba3m_v = 0x60>>2,
5361 + PCICFGA_reg_pmgt_v = 0x64>>2,
5362 + PCICFGA_func_b = 8,
5363 + PCICFGA_func_m = 0x00000700,
5364 + PCICFGA_dev_b = 11,
5365 + PCICFGA_dev_m = 0x0000f800,
5366 + PCICFGA_dev_internal_v = 0,
5367 + PCICFGA_bus_b = 16,
5368 + PCICFGA_bus_m = 0x00ff0000,
5369 + PCICFGA_bus_type0_v = 0, //local bus
5370 + PCICFGA_en_b = 31, // read only
5371 + PCICFGA_en_m = 0x80000000,
5372 +} ;
5373 +
5374 +enum {
5375 + PCFGID_vendor_b = 0,
5376 + PCFGID_vendor_m = 0x0000ffff,
5377 + PCFGID_vendor_IDT_v = 0x111d,
5378 + PCFGID_device_b = 16,
5379 + PCFGID_device_m = 0xffff0000,
5380 + PCFGID_device_Acaciade_v = 0x0207,
5381 +
5382 + PCFG04_command_ioena_b = 1,
5383 + PCFG04_command_ioena_m = 0x00000001,
5384 + PCFG04_command_memena_b = 2,
5385 + PCFG04_command_memena_m = 0x00000002,
5386 + PCFG04_command_bmena_b = 3,
5387 + PCFG04_command_bmena_m = 0x00000004,
5388 + PCFG04_command_mwinv_b = 5,
5389 + PCFG04_command_mwinv_m = 0x00000010,
5390 + PCFG04_command_parena_b = 7,
5391 + PCFG04_command_parena_m = 0x00000040,
5392 + PCFG04_command_serrena_b = 9,
5393 + PCFG04_command_serrena_m = 0x00000100,
5394 + PCFG04_command_fastbbena_b = 10,
5395 + PCFG04_command_fastbbena_m = 0x00000200,
5396 + PCFG04_status_b = 16,
5397 + PCFG04_status_m = 0xffff0000,
5398 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
5399 + PCFG04_status_66MHz_m = 0x00200000,
5400 + PCFG04_status_fbb_b = 23,
5401 + PCFG04_status_fbb_m = 0x00800000,
5402 + PCFG04_status_mdpe_b = 24,
5403 + PCFG04_status_mdpe_m = 0x01000000,
5404 + PCFG04_status_dst_b = 25,
5405 + PCFG04_status_dst_m = 0x06000000,
5406 + PCFG04_status_sta_b = 27,
5407 + PCFG04_status_sta_m = 0x08000000,
5408 + PCFG04_status_rta_b = 28,
5409 + PCFG04_status_rta_m = 0x10000000,
5410 + PCFG04_status_rma_b = 29,
5411 + PCFG04_status_rma_m = 0x20000000,
5412 + PCFG04_status_sse_b = 30,
5413 + PCFG04_status_sse_m = 0x40000000,
5414 + PCFG04_status_pe_b = 31,
5415 + PCFG04_status_pe_m = 0x40000000,
5416 +
5417 + PCFG08_revId_b = 0,
5418 + PCFG08_revId_m = 0x000000ff,
5419 + PCFG08_classCode_b = 0,
5420 + PCFG08_classCode_m = 0xffffff00,
5421 + PCFG08_classCode_bridge_v = 06,
5422 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
5423 + PCFG0C_cacheline_b = 0,
5424 + PCFG0C_cacheline_m = 0x000000ff,
5425 + PCFG0C_masterLatency_b = 8,
5426 + PCFG0C_masterLatency_m = 0x0000ff00,
5427 + PCFG0C_headerType_b = 16,
5428 + PCFG0C_headerType_m = 0x00ff0000,
5429 + PCFG0C_bist_b = 24,
5430 + PCFG0C_bist_m = 0xff000000,
5431 +
5432 + PCIPBA_msi_b = 0,
5433 + PCIPBA_msi_m = 0x00000001,
5434 + PCIPBA_p_b = 3,
5435 + PCIPBA_p_m = 0x00000004,
5436 + PCIPBA_baddr_b = 8,
5437 + PCIPBA_baddr_m = 0xffffff00,
5438 +
5439 + PCFGSS_vendorId_b = 0,
5440 + PCFGSS_vendorId_m = 0x0000ffff,
5441 + PCFGSS_id_b = 16,
5442 + PCFGSS_id_m = 0xffff0000,
5443 +
5444 + PCFG3C_interruptLine_b = 0,
5445 + PCFG3C_interruptLine_m = 0x000000ff,
5446 + PCFG3C_interruptPin_b = 8,
5447 + PCFG3C_interruptPin_m = 0x0000ff00,
5448 + PCFG3C_minGrant_b = 16,
5449 + PCFG3C_minGrant_m = 0x00ff0000,
5450 + PCFG3C_maxLat_b = 24,
5451 + PCFG3C_maxLat_m = 0xff000000,
5452 +
5453 + PCIPBAC_msi_b = 0,
5454 + PCIPBAC_msi_m = 0x00000001,
5455 + PCIPBAC_p_b = 1,
5456 + PCIPBAC_p_m = 0x00000002,
5457 + PCIPBAC_size_b = 2,
5458 + PCIPBAC_size_m = 0x0000007c,
5459 + PCIPBAC_sb_b = 7,
5460 + PCIPBAC_sb_m = 0x00000080,
5461 + PCIPBAC_pp_b = 8,
5462 + PCIPBAC_pp_m = 0x00000100,
5463 + PCIPBAC_mr_b = 9,
5464 + PCIPBAC_mr_m = 0x00000600,
5465 + PCIPBAC_mr_read_v =0, //no prefetching
5466 + PCIPBAC_mr_readLine_v =1,
5467 + PCIPBAC_mr_readMult_v =2,
5468 + PCIPBAC_mrl_b = 11,
5469 + PCIPBAC_mrl_m = 0x00000800,
5470 + PCIPBAC_mrm_b = 12,
5471 + PCIPBAC_mrm_m = 0x00001000,
5472 + PCIPBAC_trp_b = 13,
5473 + PCIPBAC_trp_m = 0x00002000,
5474 +
5475 + PCFG40_trdyTimeout_b = 0,
5476 + PCFG40_trdyTimeout_m = 0x000000ff,
5477 + PCFG40_retryLim_b = 8,
5478 + PCFG40_retryLim_m = 0x0000ff00,
5479 +};
5480 +
5481 +/*******************************************************************************
5482 + *
5483 + * PCI Local Base Address [0|1|2|3] Register
5484 + *
5485 + ******************************************************************************/
5486 +enum {
5487 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
5488 + PCILBA_baddr_m = 0xffffff00,
5489 +} ;
5490 +/*******************************************************************************
5491 + *
5492 + * PCI Local Base Address Control Register
5493 + *
5494 + ******************************************************************************/
5495 +enum {
5496 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
5497 + PCILBAC_msi_m = 0x00000001,
5498 + PCILBAC_msi_mem_v = 0,
5499 + PCILBAC_msi_io_v = 1,
5500 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
5501 + PCILBAC_size_m = 0x0000007c,
5502 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
5503 + PCILBAC_sb_m = 0x00000080,
5504 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
5505 + PCILBAC_rt_m = 0x00000100,
5506 + PCILBAC_rt_noprefetch_v = 0, // mem read
5507 + PCILBAC_rt_prefetch_v = 1, // mem readline
5508 +} ;
5509 +
5510 +/*******************************************************************************
5511 + *
5512 + * PCI Local Base Address [0|1|2|3] Mapping Register
5513 + *
5514 + ******************************************************************************/
5515 +enum {
5516 + PCILBAM_maddr_b = 8,
5517 + PCILBAM_maddr_m = 0xffffff00,
5518 +} ;
5519 +
5520 +/*******************************************************************************
5521 + *
5522 + * PCI Decoupled Access Control Register
5523 + *
5524 + ******************************************************************************/
5525 +enum {
5526 + PCIDAC_den_b = 0,
5527 + PCIDAC_den_m = 0x00000001,
5528 +} ;
5529 +
5530 +/*******************************************************************************
5531 + *
5532 + * PCI Decoupled Access Status Register
5533 + *
5534 + ******************************************************************************/
5535 +enum {
5536 + PCIDAS_d_b = 0,
5537 + PCIDAS_d_m = 0x00000001,
5538 + PCIDAS_b_b = 1,
5539 + PCIDAS_b_m = 0x00000002,
5540 + PCIDAS_e_b = 2,
5541 + PCIDAS_e_m = 0x00000004,
5542 + PCIDAS_ofe_b = 3,
5543 + PCIDAS_ofe_m = 0x00000008,
5544 + PCIDAS_off_b = 4,
5545 + PCIDAS_off_m = 0x00000010,
5546 + PCIDAS_ife_b = 5,
5547 + PCIDAS_ife_m = 0x00000020,
5548 + PCIDAS_iff_b = 6,
5549 + PCIDAS_iff_m = 0x00000040,
5550 +} ;
5551 +
5552 +/*******************************************************************************
5553 + *
5554 + * PCI DMA Channel 8 Configuration Register
5555 + *
5556 + ******************************************************************************/
5557 +enum
5558 +{
5559 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
5560 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
5561 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
5562 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
5563 +} ;
5564 +
5565 +/*******************************************************************************
5566 + *
5567 + * PCI DMA Channel 9 Configuration Register
5568 + *
5569 + ******************************************************************************/
5570 +enum
5571 +{
5572 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
5573 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
5574 +} ;
5575 +
5576 +/*******************************************************************************
5577 + *
5578 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
5579 + *
5580 + ******************************************************************************/
5581 +enum {
5582 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
5583 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
5584 + // These are for reads (DMA channel 8)
5585 + PCIDMAD_devcmd_mr_v = 0, //memory read
5586 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
5587 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
5588 + PCIDMAD_devcmd_ior_v = 3, //I/O read
5589 + // These are for writes (DMA channel 9)
5590 + PCIDMAD_devcmd_mw_v = 0, //memory write
5591 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
5592 + PCIDMAD_devcmd_iow_v = 3, //I/O write
5593 +
5594 + // Swap byte field applies to both DMA channel 8 and 9
5595 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
5596 + PCIDMAD_sb_m = 0x01000000, // swap byte field
5597 +} ;
5598 +
5599 +
5600 +/*******************************************************************************
5601 + *
5602 + * PCI Target Control Register
5603 + *
5604 + ******************************************************************************/
5605 +enum
5606 +{
5607 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
5608 + PCITC_rtimer_m = 0x000000ff,
5609 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
5610 + PCITC_dtimer_m = 0x0000ff00,
5611 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
5612 + PCITC_rdr_m = 0x00040000,
5613 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
5614 + PCITC_ddt_m = 0x00080000,
5615 +} ;
5616 +/*******************************************************************************
5617 + *
5618 + * PCI messaging unit [applies to both inbound and outbound registers ]
5619 + *
5620 + ******************************************************************************/
5621 +enum
5622 +{
5623 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5624 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
5625 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5626 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
5627 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5628 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
5629 +};
5630 +
5631 +
5632 +#endif // __IDT_RC32365_PCI_H__
5633 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h
5634 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h 1970-01-01 01:00:00.000000000 +0100
5635 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h 2006-03-20 14:25:10.000000000 +0100
5636 @@ -0,0 +1,217 @@
5637 +/**************************************************************************
5638 + *
5639 + * BRIEF MODULE DESCRIPTION
5640 + * PCI header values for IDT 79EB365/336
5641 + *
5642 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5643 + *
5644 + * This program is free software; you can redistribute it and/or modify it
5645 + * under the terms of the GNU General Public License as published by the
5646 + * Free Software Foundation; either version 2 of the License, or (at your
5647 + * option) any later version.
5648 + *
5649 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5650 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5651 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5652 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5653 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5654 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5655 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5656 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5657 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5658 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5659 + *
5660 + * You should have received a copy of the GNU General Public License along
5661 + * with this program; if not, write to the Free Software Foundation, Inc.,
5662 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5663 + *
5664 + *
5665 + **************************************************************************
5666 + * May 2004 P. Sadik.
5667 + *
5668 + * Initial Release
5669 + *
5670 + *
5671 + *
5672 + **************************************************************************
5673 + */
5674 +
5675 +#ifndef __IDT_RC32365_PCI_V_H__
5676 +#define __IDT_RC32365_PCI_V_H__
5677 +
5678 +
5679 +#define PCI_MSG_VirtualAddress 0xB806C010
5680 +#define rc32365_pci ((volatile PCI_t) PCI0_VirtualAddress)
5681 +#define rc32365_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
5682 +
5683 +#define PCIM_SHFT 0x6
5684 +#define PCIM_BIT_LEN 0x7
5685 +#define PCIM_H_EA 0x3
5686 +#define PCIM_H_IA_FIX 0x4
5687 +#define PCIM_H_IA_RR 0x5
5688 +
5689 +#define PCI_ADDR_START 0x50000000
5690 +
5691 +#define CPUTOPCI_MEM_WIN 0x02000000
5692 +#define CPUTOPCI_IO_WIN 0x00100000
5693 +#define PCILBA_SIZE_SHFT 2
5694 +#define PCILBA_SIZE_MASK 0x1F
5695 +#define SIZE_256MB 0x1C
5696 +#define SIZE_128MB 0x1B
5697 +#define SIZE_64MB 0x1A
5698 +#define SIZE_32MB 0x19
5699 +#define SIZE_16MB 0x18
5700 +#define SIZE_4MB 0x16
5701 +#define SIZE_2MB 0x15
5702 +#define SIZE_1MB 0x14
5703 +#define CEDAR_CONFIG0_ADDR 0x80000000
5704 +#define CEDAR_CONFIG1_ADDR 0x80000004
5705 +#define CEDAR_CONFIG2_ADDR 0x80000008
5706 +#define CEDAR_CONFIG3_ADDR 0x8000000C
5707 +#define CEDAR_CONFIG4_ADDR 0x80000010
5708 +#define CEDAR_CONFIG5_ADDR 0x80000014
5709 +#define CEDAR_CONFIG6_ADDR 0x80000018
5710 +#define CEDAR_CONFIG7_ADDR 0x8000001C
5711 +#define CEDAR_CONFIG8_ADDR 0x80000020
5712 +#define CEDAR_CONFIG9_ADDR 0x80000024
5713 +#define CEDAR_CONFIG10_ADDR 0x80000028
5714 +#define CEDAR_CONFIG11_ADDR 0x8000002C
5715 +#define CEDAR_CONFIG12_ADDR 0x80000030
5716 +#define CEDAR_CONFIG13_ADDR 0x80000034
5717 +#define CEDAR_CONFIG14_ADDR 0x80000038
5718 +#define CEDAR_CONFIG15_ADDR 0x8000003C
5719 +#define CEDAR_CONFIG16_ADDR 0x80000040
5720 +#define CEDAR_CONFIG17_ADDR 0x80000044
5721 +#define CEDAR_CONFIG18_ADDR 0x80000048
5722 +#define CEDAR_CONFIG19_ADDR 0x8000004C
5723 +#define CEDAR_CONFIG20_ADDR 0x80000050
5724 +#define CEDAR_CONFIG21_ADDR 0x80000054
5725 +#define CEDAR_CONFIG22_ADDR 0x80000058
5726 +#define CEDAR_CONFIG23_ADDR 0x8000005C
5727 +#define CEDAR_CONFIG24_ADDR 0x80000060
5728 +#define CEDAR_CONFIG25_ADDR 0x80000064
5729 +#define CEDAR_CMD (PCFG04_command_ioena_m | \
5730 + PCFG04_command_memena_m | \
5731 + PCFG04_command_bmena_m | \
5732 + PCFG04_command_mwinv_m | \
5733 + PCFG04_command_parena_m | \
5734 + PCFG04_command_serrena_m )
5735 +
5736 +#define CEDAR_STAT (PCFG04_status_mdpe_m | \
5737 + PCFG04_status_sta_m | \
5738 + PCFG04_status_rta_m | \
5739 + PCFG04_status_rma_m | \
5740 + PCFG04_status_sse_m | \
5741 + PCFG04_status_pe_m)
5742 +
5743 +#define CEDAR_CNFG1 ((CEDAR_STAT << 16) | \
5744 + CEDAR_CMD)
5745 +
5746 +#define CEDAR_REVID 0
5747 +#define CEDAR_CLASS_CODE 0
5748 +#define CEDAR_CNFG2 ((CEDAR_CLASS_CODE << 8) | \
5749 + CEDAR_REVID)
5750 +
5751 +#define CEDAR_CACHE_LINE_SIZE 4
5752 +#define CEDAR_MASTER_LAT 0x3c
5753 +#define CEDAR_HEADER_TYPE 0
5754 +#define CEDAR_BIST 0
5755 +
5756 +#define CEDAR_CNFG3 ((CEDAR_BIST << 24) | \
5757 + (CEDAR_HEADER_TYPE << 16) | \
5758 + (CEDAR_MASTER_LAT << 8) | \
5759 + CEDAR_CACHE_LINE_SIZE)
5760 +
5761 +#define CEDAR_BAR0 0x00000008 /* 128 MB Memory */
5762 +#define CEDAR_BAR1 0x18800001 /* 1 MB IO */
5763 +#define CEDAR_BAR2 0x18000001 /* 2 MB IO window for Cedar
5764 + internal Registers */
5765 +#define CEDAR_BAR3 0x48000008 /* Spare 128 MB Memory */
5766 +
5767 +#define CEDAR_CNFG4 CEDAR_BAR0
5768 +#define CEDAR_CNFG5 CEDAR_BAR1
5769 +#define CEDAR_CNFG6 CEDAR_BAR2
5770 +#define CEDAR_CNFG7 CEDAR_BAR3
5771 +
5772 +#define CEDAR_SUBSYS_VENDOR_ID 0
5773 +#define CEDAR_SUBSYSTEM_ID 0
5774 +#define CEDAR_CNFG8 0
5775 +#define CEDAR_CNFG9 0
5776 +#define CEDAR_CNFG10 0
5777 +#define CEDAR_CNFG11 ((CEDAR_SUBSYS_VENDOR_ID << 16) | \
5778 + CEDAR_SUBSYSTEM_ID)
5779 +#define CEDAR_INT_LINE 1
5780 +#define CEDAR_INT_PIN 1
5781 +#define CEDAR_MIN_GNT 8
5782 +#define CEDAR_MAX_LAT 0x38
5783 +#define CEDAR_CNFG12 0
5784 +#define CEDAR_CNFG13 0
5785 +#define CEDAR_CNFG14 0
5786 +#define CEDAR_CNFG15 ((CEDAR_MAX_LAT << 24) | \
5787 + (CEDAR_MIN_GNT << 16) | \
5788 + (CEDAR_INT_PIN << 8) | \
5789 + CEDAR_INT_LINE)
5790 +#define CEDAR_RETRY_LIMIT 0x80
5791 +#define CEDAR_TRDY_LIMIT 0x80
5792 +#define CEDAR_CNFG16 ((CEDAR_RETRY_LIMIT << 8) | \
5793 + CEDAR_TRDY_LIMIT)
5794 +#define PCI_PBAxC_R 0x0
5795 +#define PCI_PBAxC_RL 0x1
5796 +#define PCI_PBAxC_RM 0x2
5797 +#define SIZE_SHFT 2
5798 +#ifdef __MIPSEB__
5799 +#define CEDAR_PBA0C (((1 & 0x3) << PCIPBAC_mr_b) | \
5800 + PCIPBAC_pp_m | \
5801 + PCIPBAC_sb_m | \
5802 + (SIZE_128MB << SIZE_SHFT) | \
5803 + PCIPBAC_p_m)
5804 +#else
5805 +
5806 +#define CEDAR_PBA0C (((1 & 0x3) << PCIPBAC_mr_b) | \
5807 + PCIPBAC_pp_m | \
5808 + (SIZE_128MB << SIZE_SHFT) | \
5809 + PCIPBAC_p_m)
5810 +#endif
5811 +#define CEDAR_CNFG17 CEDAR_PBA0C
5812 +#define CEDAR_PBA0M 0x0
5813 +#define CEDAR_CNFG18 CEDAR_PBA0M
5814 +
5815 +#ifdef __MIPSEB__
5816 +#define CEDAR_PBA1C ((SIZE_1MB << SIZE_SHFT) | \
5817 + PCIPBAC_sb_m | \
5818 + PCIPBAC_msi_m)
5819 +#else
5820 +#define CEDAR_PBA1C ((SIZE_1MB << SIZE_SHFT) | \
5821 + PCIPBAC_msi_m)
5822 +#endif
5823 +#define CEDAR_CNFG19 CEDAR_PBA1C
5824 +#define CEDAR_PBA1M 0x0
5825 +#define CEDAR_CNFG20 CEDAR_PBA1M
5826 +
5827 +#ifdef __MIPSEB__
5828 +#define CEDAR_PBA2C ((SIZE_2MB << SIZE_SHFT) | \
5829 + PCIPBAC_sb_m | \
5830 + PCIPBAC_msi_m)
5831 +#else
5832 +#define CEDAR_PBA2C ((SIZE_2MB << SIZE_SHFT) | \
5833 + PCIPBAC_msi_m)
5834 +#endif
5835 +
5836 +#define CEDAR_CNFG21 CEDAR_PBA2C
5837 +#define CEDAR_PBA2M 0x18000000
5838 +#define CEDAR_CNFG22 CEDAR_PBA2M
5839 +
5840 +#ifdef __MIPSEB__
5841 +#define CEDAR_PBA3C PCIPBAC_sb_m
5842 +#else
5843 +#define CEDAR_PBA3C 0
5844 +#endif
5845 +
5846 +#define CEDAR_CNFG23 CEDAR_PBA3C
5847 +#define CEDAR_PBA3M 0
5848 +#define CEDAR_CNFG24 CEDAR_PBA3M
5849 +
5850 +#define PCITC_DTIMER_VAL 8
5851 +#define PCITC_RTIMER_VAL 0x10
5852 +
5853 +#endif //__IDT_RC32365_PCI_V_H__
5854 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_dma.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h
5855 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 1970-01-01 01:00:00.000000000 +0100
5856 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 2006-03-20 14:25:10.000000000 +0100
5857 @@ -0,0 +1,205 @@
5858 +/**************************************************************************
5859 + *
5860 + * BRIEF MODULE DESCRIPTION
5861 + * DMA register definition
5862 + *
5863 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5864 + *
5865 + * This program is free software; you can redistribute it and/or modify it
5866 + * under the terms of the GNU General Public License as published by the
5867 + * Free Software Foundation; either version 2 of the License, or (at your
5868 + * option) any later version.
5869 + *
5870 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5871 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5872 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5873 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5874 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5875 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5876 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5877 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5878 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5879 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5880 + *
5881 + * You should have received a copy of the GNU General Public License along
5882 + * with this program; if not, write to the Free Software Foundation, Inc.,
5883 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5884 + *
5885 + *
5886 + **************************************************************************
5887 + * May 2004 rkt, neb
5888 + *
5889 + * Initial Release
5890 + *
5891 + *
5892 + *
5893 + **************************************************************************
5894 + */
5895 +
5896 +#ifndef __IDT_DMA_H__
5897 +#define __IDT_DMA_H__
5898 +
5899 +enum
5900 +{
5901 + DMA0_PhysicalAddress = 0x18040000,
5902 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
5903 +
5904 + DMA0_VirtualAddress = 0xb8040000,
5905 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
5906 +} ;
5907 +
5908 +/*
5909 + * DMA descriptor (in physical memory).
5910 + */
5911 +
5912 +typedef struct DMAD_s
5913 +{
5914 + u32 control ; // Control. use DMAD_*
5915 + u32 ca ; // Current Address.
5916 + u32 devcs ; // Device control and status.
5917 + u32 link ; // Next descriptor in chain.
5918 +} volatile *DMAD_t ;
5919 +
5920 +enum
5921 +{
5922 + DMAD_size = sizeof (struct DMAD_s),
5923 + DMAD_count_b = 0, // in DMAD_t -> control
5924 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
5925 + DMAD_ds_b = 20, // in DMAD_t -> control
5926 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
5927 + DMAD_ds_ethRcv0_v = 0,
5928 + DMAD_ds_ethXmt0_v = 0,
5929 + DMAD_ds_memToFifo_v = 0,
5930 + DMAD_ds_fifoToMem_v = 0,
5931 + DMAD_ds_pciToMem_v = 0,
5932 + DMAD_ds_memToPci_v = 0,
5933 +
5934 + DMAD_devcmd_b = 22, // in DMAD_t -> control
5935 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
5936 + DMAD_devcmd_byte_v = 0, //memory-to-memory
5937 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
5938 + DMAD_devcmd_word_v = 2, //memory-to-memory
5939 + DMAD_devcmd_2words_v = 3, //memory-to-memory
5940 + DMAD_devcmd_4words_v = 4, //memory-to-memory
5941 + DMAD_devcmd_6words_v = 5, //memory-to-memory
5942 + DMAD_devcmd_8words_v = 6, //memory-to-memory
5943 + DMAD_devcmd_16words_v = 7, //memory-to-memory
5944 + DMAD_cof_b = 25, // chain on finished
5945 + DMAD_cof_m = 0x02000000, //
5946 + DMAD_cod_b = 26, // chain on done
5947 + DMAD_cod_m = 0x04000000, //
5948 + DMAD_iof_b = 27, // interrupt on finished
5949 + DMAD_iof_m = 0x08000000, //
5950 + DMAD_iod_b = 28, // interrupt on done
5951 + DMAD_iod_m = 0x10000000, //
5952 + DMAD_t_b = 29, // terminated
5953 + DMAD_t_m = 0x20000000, //
5954 + DMAD_d_b = 30, // done
5955 + DMAD_d_m = 0x40000000, //
5956 + DMAD_f_b = 31, // finished
5957 + DMAD_f_m = 0x80000000, //
5958 +} ;
5959 +
5960 +/*
5961 + * DMA register (within Internal Register Map).
5962 + */
5963 +
5964 +struct DMA_Chan_s
5965 +{
5966 + u32 dmac ; // Control.
5967 + u32 dmas ; // Status.
5968 + u32 dmasm ; // Mask.
5969 + u32 dmadptr ; // Descriptor pointer.
5970 + u32 dmandptr ; // Next descriptor pointer.
5971 +};
5972 +
5973 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
5974 +
5975 +//DMA_Channels use DMACH_count instead
5976 +
5977 +enum
5978 +{
5979 + DMAC_run_b = 0, //
5980 + DMAC_run_m = 0x00000001, //
5981 + DMAC_dm_b = 1, // done mask
5982 + DMAC_dm_m = 0x00000002, //
5983 + DMAC_mode_b = 2, //
5984 + DMAC_mode_m = 0x0000000c, //
5985 + DMAC_mode_auto_v = 0,
5986 + DMAC_mode_burst_v = 1,
5987 + DMAC_mode_transfer_v = 2, //usually used
5988 + DMAC_mode_reserved_v = 3,
5989 + DMAC_a_b = 4, //
5990 + DMAC_a_m = 0x00000010, //
5991 +
5992 + DMAS_f_b = 0, // finished (sticky)
5993 + DMAS_f_m = 0x00000001, //
5994 + DMAS_d_b = 1, // done (sticky)
5995 + DMAS_d_m = 0x00000002, //
5996 + DMAS_c_b = 2, // chain (sticky)
5997 + DMAS_c_m = 0x00000004, //
5998 + DMAS_e_b = 3, // error (sticky)
5999 + DMAS_e_m = 0x00000008, //
6000 + DMAS_h_b = 4, // halt (sticky)
6001 + DMAS_h_m = 0x00000010, //
6002 +
6003 + DMASM_f_b = 0, // finished (1=mask)
6004 + DMASM_f_m = 0x00000001, //
6005 + DMASM_d_b = 1, // done (1=mask)
6006 + DMASM_d_m = 0x00000002, //
6007 + DMASM_c_b = 2, // chain (1=mask)
6008 + DMASM_c_m = 0x00000004, //
6009 + DMASM_e_b = 3, // error (1=mask)
6010 + DMASM_e_m = 0x00000008, //
6011 + DMASM_h_b = 4, // halt (1=mask)
6012 + DMASM_h_m = 0x00000010, //
6013 +} ;
6014 +
6015 +/*
6016 + * DMA channel definitions
6017 + */
6018 +
6019 +enum
6020 +{
6021 + DMACH_ethRcv0 = 0,
6022 + DMACH_ethXmt0 = 1,
6023 + DMACH_memToFifo = 2,
6024 + DMACH_fifoToMem = 3,
6025 + DMACH_pciToMem = 4,
6026 + DMACH_memToPci = 5,
6027 +
6028 + DMACH_count //must be last
6029 +};
6030 +
6031 +
6032 +typedef struct DMAC_s
6033 +{
6034 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
6035 +} volatile *DMA_t ;
6036 +
6037 +
6038 +/*
6039 + * External DMA parameters
6040 +*/
6041 +
6042 +enum
6043 +{
6044 + DMADEVCMD_ts_b = 0, // ts field in devcmd
6045 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
6046 + DMADEVCMD_ts_byte_v = 0,
6047 + DMADEVCMD_ts_halfword_v = 1,
6048 + DMADEVCMD_ts_word_v = 2,
6049 + DMADEVCMD_ts_2word_v = 3,
6050 + DMADEVCMD_ts_4word_v = 4,
6051 + DMADEVCMD_ts_6word_v = 5,
6052 + DMADEVCMD_ts_8word_v = 6,
6053 + DMADEVCMD_ts_16word_v = 7
6054 +};
6055 +
6056 +
6057 +#endif // __IDT_DMA_H__
6058 +
6059 +
6060 +
6061 +
6062 +
6063 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h
6064 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h 1970-01-01 01:00:00.000000000 +0100
6065 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h 2006-03-20 14:25:10.000000000 +0100
6066 @@ -0,0 +1,89 @@
6067 +/**************************************************************************
6068 + *
6069 + * BRIEF MODULE DESCRIPTION
6070 + * Definitions for DMA controller.
6071 + *
6072 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6073 + *
6074 + * This program is free software; you can redistribute it and/or modify it
6075 + * under the terms of the GNU General Public License as published by the
6076 + * Free Software Foundation; either version 2 of the License, or (at your
6077 + * option) any later version.
6078 + *
6079 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6080 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6081 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6082 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6083 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6084 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6085 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6086 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6087 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6088 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6089 + *
6090 + * You should have received a copy of the GNU General Public License along
6091 + * with this program; if not, write to the Free Software Foundation, Inc.,
6092 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6093 + *
6094 + *
6095 + **************************************************************************
6096 + * May 2004 rkt, neb.
6097 + *
6098 + * Initial Release
6099 + *
6100 + *
6101 + *
6102 + **************************************************************************
6103 + */
6104 +
6105 +#ifndef __IDT_DMA_V_H__
6106 +#define __IDT_DMA_V_H__
6107 +
6108 +#include <asm/idt-boards/rc32434/rc32434_dma.h>
6109 +#include <asm/idt-boards/rc32434/rc32434.h>
6110 +
6111 +#define DMA_CHAN_OFFSET 0x14
6112 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
6113 +#define DMA_COUNT(count) \
6114 + ((count) & DMAD_count_m)
6115 +
6116 +#define DMA_HALT_TIMEOUT 500
6117 +
6118 +
6119 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
6120 +{
6121 + int timeout=1;
6122 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
6123 + rc32434_writel(0, &ch->dmac);
6124 +
6125 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
6126 + if (rc32434_readl(&ch->dmas) & DMAS_h_m) {
6127 + rc32434_writel(0, &ch->dmas);
6128 + break;
6129 + }
6130 + }
6131 +
6132 + }
6133 +
6134 + return timeout ? 0 : 1;
6135 +}
6136 +
6137 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
6138 +{
6139 + rc32434_writel(0, &ch->dmandptr);
6140 + rc32434_writel(dma_addr, &ch->dmadptr);
6141 +}
6142 +
6143 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
6144 +{
6145 + rc32434_writel(dma_addr, &ch->dmandptr);
6146 +}
6147 +
6148 +#endif // __IDT_DMA_V_H__
6149 +
6150 +
6151 +
6152 +
6153 +
6154 +
6155 +
6156 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_eth.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h
6157 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
6158 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 2006-03-20 14:25:10.000000000 +0100
6159 @@ -0,0 +1,333 @@
6160 +/**************************************************************************
6161 + *
6162 + * BRIEF MODULE DESCRIPTION
6163 + * Ethernet register definition
6164 + *
6165 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6166 + *
6167 + * This program is free software; you can redistribute it and/or modify it
6168 + * under the terms of the GNU General Public License as published by the
6169 + * Free Software Foundation; either version 2 of the License, or (at your
6170 + * option) any later version.
6171 + *
6172 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6173 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6174 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6175 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6176 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6177 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6178 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6179 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6180 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6181 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6182 + *
6183 + * You should have received a copy of the GNU General Public License along
6184 + * with this program; if not, write to the Free Software Foundation, Inc.,
6185 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6186 + *
6187 + *
6188 + **************************************************************************
6189 + * May 2004 rkt, neb.
6190 + *
6191 + * Initial Release
6192 + *
6193 + *
6194 + *
6195 + **************************************************************************
6196 + */
6197 +
6198 +#ifndef __IDT_ETH_H__
6199 +#define __IDT_ETH_H__
6200 +
6201 +
6202 +enum
6203 +{
6204 + ETH0_PhysicalAddress = 0x18060000,
6205 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
6206 +
6207 + ETH0_VirtualAddress = 0xb8060000,
6208 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
6209 +} ;
6210 +
6211 +typedef struct
6212 +{
6213 + u32 ethintfc ;
6214 + u32 ethfifott ;
6215 + u32 etharc ;
6216 + u32 ethhash0 ;
6217 + u32 ethhash1 ;
6218 + u32 ethu0 [4] ; // Reserved.
6219 + u32 ethpfs ;
6220 + u32 ethmcp ;
6221 + u32 eth_u1 [10] ; // Reserved.
6222 + u32 ethspare ;
6223 + u32 eth_u2 [42] ; // Reserved.
6224 + u32 ethsal0 ;
6225 + u32 ethsah0 ;
6226 + u32 ethsal1 ;
6227 + u32 ethsah1 ;
6228 + u32 ethsal2 ;
6229 + u32 ethsah2 ;
6230 + u32 ethsal3 ;
6231 + u32 ethsah3 ;
6232 + u32 ethrbc ;
6233 + u32 ethrpc ;
6234 + u32 ethrupc ;
6235 + u32 ethrfc ;
6236 + u32 ethtbc ;
6237 + u32 ethgpf ;
6238 + u32 eth_u9 [50] ; // Reserved.
6239 + u32 ethmac1 ;
6240 + u32 ethmac2 ;
6241 + u32 ethipgt ;
6242 + u32 ethipgr ;
6243 + u32 ethclrt ;
6244 + u32 ethmaxf ;
6245 + u32 eth_u10 ; // Reserved.
6246 + u32 ethmtest ;
6247 + u32 miimcfg ;
6248 + u32 miimcmd ;
6249 + u32 miimaddr ;
6250 + u32 miimwtd ;
6251 + u32 miimrdd ;
6252 + u32 miimind ;
6253 + u32 eth_u11 ; // Reserved.
6254 + u32 eth_u12 ; // Reserved.
6255 + u32 ethcfsa0 ;
6256 + u32 ethcfsa1 ;
6257 + u32 ethcfsa2 ;
6258 +} volatile *ETH_t;
6259 +
6260 +enum
6261 +{
6262 + ETHINTFC_en_b = 0,
6263 + ETHINTFC_en_m = 0x00000001,
6264 + ETHINTFC_its_b = 1,
6265 + ETHINTFC_its_m = 0x00000002,
6266 + ETHINTFC_rip_b = 2,
6267 + ETHINTFC_rip_m = 0x00000004,
6268 + ETHINTFC_jam_b = 3,
6269 + ETHINTFC_jam_m = 0x00000008,
6270 + ETHINTFC_ovr_b = 4,
6271 + ETHINTFC_ovr_m = 0x00000010,
6272 + ETHINTFC_und_b = 5,
6273 + ETHINTFC_und_m = 0x00000020,
6274 +
6275 + ETHFIFOTT_tth_b = 0,
6276 + ETHFIFOTT_tth_m = 0x0000007f,
6277 +
6278 + ETHARC_pro_b = 0,
6279 + ETHARC_pro_m = 0x00000001,
6280 + ETHARC_am_b = 1,
6281 + ETHARC_am_m = 0x00000002,
6282 + ETHARC_afm_b = 2,
6283 + ETHARC_afm_m = 0x00000004,
6284 + ETHARC_ab_b = 3,
6285 + ETHARC_ab_m = 0x00000008,
6286 +
6287 + ETHSAL_byte5_b = 0,
6288 + ETHSAL_byte5_m = 0x000000ff,
6289 + ETHSAL_byte4_b = 8,
6290 + ETHSAL_byte4_m = 0x0000ff00,
6291 + ETHSAL_byte3_b = 16,
6292 + ETHSAL_byte3_m = 0x00ff0000,
6293 + ETHSAL_byte2_b = 24,
6294 + ETHSAL_byte2_m = 0xff000000,
6295 +
6296 + ETHSAH_byte1_b = 0,
6297 + ETHSAH_byte1_m = 0x000000ff,
6298 + ETHSAH_byte0_b = 8,
6299 + ETHSAH_byte0_m = 0x0000ff00,
6300 +
6301 + ETHGPF_ptv_b = 0,
6302 + ETHGPF_ptv_m = 0x0000ffff,
6303 +
6304 + ETHPFS_pfd_b = 0,
6305 + ETHPFS_pfd_m = 0x00000001,
6306 +
6307 + ETHCFSA0_cfsa4_b = 0,
6308 + ETHCFSA0_cfsa4_m = 0x000000ff,
6309 + ETHCFSA0_cfsa5_b = 8,
6310 + ETHCFSA0_cfsa5_m = 0x0000ff00,
6311 +
6312 + ETHCFSA1_cfsa2_b = 0,
6313 + ETHCFSA1_cfsa2_m = 0x000000ff,
6314 + ETHCFSA1_cfsa3_b = 8,
6315 + ETHCFSA1_cfsa3_m = 0x0000ff00,
6316 +
6317 + ETHCFSA2_cfsa0_b = 0,
6318 + ETHCFSA2_cfsa0_m = 0x000000ff,
6319 + ETHCFSA2_cfsa1_b = 8,
6320 + ETHCFSA2_cfsa1_m = 0x0000ff00,
6321 +
6322 + ETHMAC1_re_b = 0,
6323 + ETHMAC1_re_m = 0x00000001,
6324 + ETHMAC1_paf_b = 1,
6325 + ETHMAC1_paf_m = 0x00000002,
6326 + ETHMAC1_rfc_b = 2,
6327 + ETHMAC1_rfc_m = 0x00000004,
6328 + ETHMAC1_tfc_b = 3,
6329 + ETHMAC1_tfc_m = 0x00000008,
6330 + ETHMAC1_lb_b = 4,
6331 + ETHMAC1_lb_m = 0x00000010,
6332 + ETHMAC1_mr_b = 31,
6333 + ETHMAC1_mr_m = 0x80000000,
6334 +
6335 + ETHMAC2_fd_b = 0,
6336 + ETHMAC2_fd_m = 0x00000001,
6337 + ETHMAC2_flc_b = 1,
6338 + ETHMAC2_flc_m = 0x00000002,
6339 + ETHMAC2_hfe_b = 2,
6340 + ETHMAC2_hfe_m = 0x00000004,
6341 + ETHMAC2_dc_b = 3,
6342 + ETHMAC2_dc_m = 0x00000008,
6343 + ETHMAC2_cen_b = 4,
6344 + ETHMAC2_cen_m = 0x00000010,
6345 + ETHMAC2_pe_b = 5,
6346 + ETHMAC2_pe_m = 0x00000020,
6347 + ETHMAC2_vpe_b = 6,
6348 + ETHMAC2_vpe_m = 0x00000040,
6349 + ETHMAC2_ape_b = 7,
6350 + ETHMAC2_ape_m = 0x00000080,
6351 + ETHMAC2_ppe_b = 8,
6352 + ETHMAC2_ppe_m = 0x00000100,
6353 + ETHMAC2_lpe_b = 9,
6354 + ETHMAC2_lpe_m = 0x00000200,
6355 + ETHMAC2_nb_b = 12,
6356 + ETHMAC2_nb_m = 0x00001000,
6357 + ETHMAC2_bp_b = 13,
6358 + ETHMAC2_bp_m = 0x00002000,
6359 + ETHMAC2_ed_b = 14,
6360 + ETHMAC2_ed_m = 0x00004000,
6361 +
6362 + ETHIPGT_ipgt_b = 0,
6363 + ETHIPGT_ipgt_m = 0x0000007f,
6364 +
6365 + ETHIPGR_ipgr2_b = 0,
6366 + ETHIPGR_ipgr2_m = 0x0000007f,
6367 + ETHIPGR_ipgr1_b = 8,
6368 + ETHIPGR_ipgr1_m = 0x00007f00,
6369 +
6370 + ETHCLRT_maxret_b = 0,
6371 + ETHCLRT_maxret_m = 0x0000000f,
6372 + ETHCLRT_colwin_b = 8,
6373 + ETHCLRT_colwin_m = 0x00003f00,
6374 +
6375 + ETHMAXF_maxf_b = 0,
6376 + ETHMAXF_maxf_m = 0x0000ffff,
6377 +
6378 + ETHMTEST_tb_b = 2,
6379 + ETHMTEST_tb_m = 0x00000004,
6380 +
6381 + ETHMCP_div_b = 0,
6382 + ETHMCP_div_m = 0x000000ff,
6383 +
6384 + MIIMCFG_rsv_b = 0,
6385 + MIIMCFG_rsv_m = 0x0000000c,
6386 +
6387 + MIIMCMD_rd_b = 0,
6388 + MIIMCMD_rd_m = 0x00000001,
6389 + MIIMCMD_scn_b = 1,
6390 + MIIMCMD_scn_m = 0x00000002,
6391 +
6392 + MIIMADDR_regaddr_b = 0,
6393 + MIIMADDR_regaddr_m = 0x0000001f,
6394 + MIIMADDR_phyaddr_b = 8,
6395 + MIIMADDR_phyaddr_m = 0x00001f00,
6396 +
6397 + MIIMWTD_wdata_b = 0,
6398 + MIIMWTD_wdata_m = 0x0000ffff,
6399 +
6400 + MIIMRDD_rdata_b = 0,
6401 + MIIMRDD_rdata_m = 0x0000ffff,
6402 +
6403 + MIIMIND_bsy_b = 0,
6404 + MIIMIND_bsy_m = 0x00000001,
6405 + MIIMIND_scn_b = 1,
6406 + MIIMIND_scn_m = 0x00000002,
6407 + MIIMIND_nv_b = 2,
6408 + MIIMIND_nv_m = 0x00000004,
6409 +
6410 +} ;
6411 +
6412 +/*
6413 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
6414 + */
6415 +enum
6416 +{
6417 + ETHRX_fd_b = 0,
6418 + ETHRX_fd_m = 0x00000001,
6419 + ETHRX_ld_b = 1,
6420 + ETHRX_ld_m = 0x00000002,
6421 + ETHRX_rok_b = 2,
6422 + ETHRX_rok_m = 0x00000004,
6423 + ETHRX_fm_b = 3,
6424 + ETHRX_fm_m = 0x00000008,
6425 + ETHRX_mp_b = 4,
6426 + ETHRX_mp_m = 0x00000010,
6427 + ETHRX_bp_b = 5,
6428 + ETHRX_bp_m = 0x00000020,
6429 + ETHRX_vlt_b = 6,
6430 + ETHRX_vlt_m = 0x00000040,
6431 + ETHRX_cf_b = 7,
6432 + ETHRX_cf_m = 0x00000080,
6433 + ETHRX_ovr_b = 8,
6434 + ETHRX_ovr_m = 0x00000100,
6435 + ETHRX_crc_b = 9,
6436 + ETHRX_crc_m = 0x00000200,
6437 + ETHRX_cv_b = 10,
6438 + ETHRX_cv_m = 0x00000400,
6439 + ETHRX_db_b = 11,
6440 + ETHRX_db_m = 0x00000800,
6441 + ETHRX_le_b = 12,
6442 + ETHRX_le_m = 0x00001000,
6443 + ETHRX_lor_b = 13,
6444 + ETHRX_lor_m = 0x00002000,
6445 + ETHRX_ces_b = 14,
6446 + ETHRX_ces_m = 0x00004000,
6447 + ETHRX_length_b = 16,
6448 + ETHRX_length_m = 0xffff0000,
6449 +
6450 + ETHTX_fd_b = 0,
6451 + ETHTX_fd_m = 0x00000001,
6452 + ETHTX_ld_b = 1,
6453 + ETHTX_ld_m = 0x00000002,
6454 + ETHTX_oen_b = 2,
6455 + ETHTX_oen_m = 0x00000004,
6456 + ETHTX_pen_b = 3,
6457 + ETHTX_pen_m = 0x00000008,
6458 + ETHTX_cen_b = 4,
6459 + ETHTX_cen_m = 0x00000010,
6460 + ETHTX_hen_b = 5,
6461 + ETHTX_hen_m = 0x00000020,
6462 + ETHTX_tok_b = 6,
6463 + ETHTX_tok_m = 0x00000040,
6464 + ETHTX_mp_b = 7,
6465 + ETHTX_mp_m = 0x00000080,
6466 + ETHTX_bp_b = 8,
6467 + ETHTX_bp_m = 0x00000100,
6468 + ETHTX_und_b = 9,
6469 + ETHTX_und_m = 0x00000200,
6470 + ETHTX_of_b = 10,
6471 + ETHTX_of_m = 0x00000400,
6472 + ETHTX_ed_b = 11,
6473 + ETHTX_ed_m = 0x00000800,
6474 + ETHTX_ec_b = 12,
6475 + ETHTX_ec_m = 0x00001000,
6476 + ETHTX_lc_b = 13,
6477 + ETHTX_lc_m = 0x00002000,
6478 + ETHTX_td_b = 14,
6479 + ETHTX_td_m = 0x00004000,
6480 + ETHTX_crc_b = 15,
6481 + ETHTX_crc_m = 0x00008000,
6482 + ETHTX_le_b = 16,
6483 + ETHTX_le_m = 0x00010000,
6484 + ETHTX_cc_b = 17,
6485 + ETHTX_cc_m = 0x001E0000,
6486 +} ;
6487 +
6488 +#endif // __IDT_ETH_H__
6489 +
6490 +
6491 +
6492 +
6493 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h
6494 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h 1970-01-01 01:00:00.000000000 +0100
6495 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h 2006-03-20 14:25:10.000000000 +0100
6496 @@ -0,0 +1,77 @@
6497 +/**************************************************************************
6498 + *
6499 + * BRIEF MODULE DESCRIPTION
6500 + * Ethernet register definition
6501 + *
6502 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6503 + *
6504 + * This program is free software; you can redistribute it and/or modify it
6505 + * under the terms of the GNU General Public License as published by the
6506 + * Free Software Foundation; either version 2 of the License, or (at your
6507 + * option) any later version.
6508 + *
6509 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6510 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6511 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6512 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6513 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6514 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6515 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6516 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6517 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6518 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6519 + *
6520 + * You should have received a copy of the GNU General Public License along
6521 + * with this program; if not, write to the Free Software Foundation, Inc.,
6522 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6523 + *
6524 + *
6525 + **************************************************************************
6526 + * May 2004 rkt, neb.
6527 + *
6528 + * Initial Release
6529 + *
6530 + *
6531 + *
6532 + **************************************************************************
6533 + */
6534 +
6535 +#ifndef __IDT_ETH_V_H__
6536 +#define __IDT_ETH_V_H__
6537 +
6538 +#include <asm/idt-boards/rc32434/rc32434_eth.h>
6539 +
6540 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
6541 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
6542 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
6543 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
6544 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
6545 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
6546 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
6547 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
6548 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
6549 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
6550 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
6551 +
6552 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
6553 +
6554 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
6555 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
6556 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
6557 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
6558 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
6559 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
6560 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
6561 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
6562 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
6563 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
6564 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
6565 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
6566 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
6567 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
6568 +#endif // __IDT_ETH_V_H__
6569 +
6570 +
6571 +
6572 +
6573 +
6574 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h
6575 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h 1970-01-01 01:00:00.000000000 +0100
6576 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h 2006-03-20 14:25:10.000000000 +0100
6577 @@ -0,0 +1,167 @@
6578 +/**************************************************************************
6579 + *
6580 + * BRIEF MODULE DESCRIPTION
6581 + * GPIO register definition
6582 + *
6583 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6584 + *
6585 + * This program is free software; you can redistribute it and/or modify it
6586 + * under the terms of the GNU General Public License as published by the
6587 + * Free Software Foundation; either version 2 of the License, or (at your
6588 + * option) any later version.
6589 + *
6590 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6591 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6592 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6593 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6594 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6595 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6596 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6597 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6598 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6599 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6600 + *
6601 + * You should have received a copy of the GNU General Public License along
6602 + * with this program; if not, write to the Free Software Foundation, Inc.,
6603 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6604 + *
6605 + *
6606 + **************************************************************************
6607 + * May 2004 rkt, neb.
6608 + *
6609 + * Initial Release
6610 + *
6611 + *
6612 + *
6613 + **************************************************************************
6614 + */
6615 +
6616 +#ifndef __IDT_GPIO_H__
6617 +#define __IDT_GPIO_H__
6618 +
6619 +enum
6620 +{
6621 + GPIO0_PhysicalAddress = 0x18050000,
6622 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
6623 +
6624 + GPIO0_VirtualAddress = 0xb8050000,
6625 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
6626 +} ;
6627 +
6628 +typedef struct
6629 +{
6630 + u32 gpiofunc; /* GPIO Function Register
6631 + * gpiofunc[x]==0 bit = gpio
6632 + * func[x]==1 bit = altfunc
6633 + */
6634 + u32 gpiocfg; /* GPIO Configuration Register
6635 + * gpiocfg[x]==0 bit = input
6636 + * gpiocfg[x]==1 bit = output
6637 + */
6638 + u32 gpiod; /* GPIO Data Register
6639 + * gpiod[x] read/write gpio pinX status
6640 + */
6641 + u32 gpioilevel; /* GPIO Interrupt Status Register
6642 + * interrupt level (see gpioistat)
6643 + */
6644 + u32 gpioistat; /* Gpio Interrupt Status Register
6645 + * istat[x] = (gpiod[x] == level[x])
6646 + * cleared in ISR (STICKY bits)
6647 + */
6648 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
6649 +} volatile * GPIO_t ;
6650 +
6651 +typedef enum
6652 +{
6653 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
6654 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
6655 + GPIO_input_v = 0, // gpiocfg use pin as input.
6656 + GPIO_output_v = 1, // gpiocfg use pin as output.
6657 + GPIO_pin0_b = 0,
6658 + GPIO_pin0_m = 0x00000001,
6659 + GPIO_pin1_b = 1,
6660 + GPIO_pin1_m = 0x00000002,
6661 + GPIO_pin2_b = 2,
6662 + GPIO_pin2_m = 0x00000004,
6663 + GPIO_pin3_b = 3,
6664 + GPIO_pin3_m = 0x00000008,
6665 + GPIO_pin4_b = 4,
6666 + GPIO_pin4_m = 0x00000010,
6667 + GPIO_pin5_b = 5,
6668 + GPIO_pin5_m = 0x00000020,
6669 + GPIO_pin6_b = 6,
6670 + GPIO_pin6_m = 0x00000040,
6671 + GPIO_pin7_b = 7,
6672 + GPIO_pin7_m = 0x00000080,
6673 + GPIO_pin8_b = 8,
6674 + GPIO_pin8_m = 0x00000100,
6675 + GPIO_pin9_b = 9,
6676 + GPIO_pin9_m = 0x00000200,
6677 + GPIO_pin10_b = 10,
6678 + GPIO_pin10_m = 0x00000400,
6679 + GPIO_pin11_b = 11,
6680 + GPIO_pin11_m = 0x00000800,
6681 + GPIO_pin12_b = 12,
6682 + GPIO_pin12_m = 0x00001000,
6683 + GPIO_pin13_b = 13,
6684 + GPIO_pin13_m = 0x00002000,
6685 +
6686 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
6687 +
6688 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
6689 + GPIO_u0sout_m = GPIO_pin0_m,
6690 + GPIO_u0sout_cfg_v = GPIO_output_v,
6691 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
6692 + GPIO_u0sinp_m = GPIO_pin1_m,
6693 + GPIO_u0sinp_cfg_v = GPIO_input_v,
6694 + GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
6695 + GPIO_u0rtsn_m = GPIO_pin2_m,
6696 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
6697 + GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
6698 + GPIO_u0ctsn_m = GPIO_pin3_m,
6699 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
6700 +
6701 + GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
6702 + GPIO_maddr22_m = GPIO_pin4_m,
6703 + GPIO_maddr22_cfg_v = GPIO_output_v,
6704 +
6705 + GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
6706 + GPIO_maddr23_m = GPIO_pin5_m,
6707 + GPIO_maddr23_cfg_v = GPIO_output_v,
6708 +
6709 + GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
6710 + GPIO_maddr24_m = GPIO_pin6_m,
6711 + GPIO_maddr24_cfg_v = GPIO_output_v,
6712 +
6713 + GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
6714 + GPIO_maddr25_m = GPIO_pin7_m,
6715 + GPIO_maddr25_cfg_v = GPIO_output_v,
6716 +
6717 + GPIO_cpudmadebug_b = GPIO_pin8_b, // CPU or DMA debug pin
6718 + GPIO_cpudmadebug_m = GPIO_pin8_m,
6719 + GPIO_cpudmadebug_cfg_v = GPIO_output_v,
6720 +
6721 + GPIO_pcireq4_b = GPIO_pin9_b, // PCI Request 4
6722 + GPIO_pcireq4_m = GPIO_pin9_m,
6723 + GPIO_pcireq4_cfg_v = GPIO_input_v,
6724 +
6725 + GPIO_pcigrant4_b = GPIO_pin10_b, // PCI Grant 4
6726 + GPIO_pcigrant4_m = GPIO_pin10_m,
6727 + GPIO_pcigrant4_cfg_v = GPIO_output_v,
6728 +
6729 + GPIO_pcireq5_b = GPIO_pin11_b, // PCI Request 5
6730 + GPIO_pcireq5_m = GPIO_pin11_m,
6731 + GPIO_pcireq5_cfg_v = GPIO_input_v,
6732 +
6733 + GPIO_pcigrant5_b = GPIO_pin12_b, // PCI Grant 5
6734 + GPIO_pcigrant5_m = GPIO_pin12_m,
6735 + GPIO_pcigrant5_cfg_v = GPIO_output_v,
6736 +
6737 + GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
6738 + GPIO_pcimuintn_m = GPIO_pin13_m,
6739 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
6740 +
6741 +} GPIO_DEFS_t;
6742 +
6743 +#endif // __IDT_GPIO_H__
6744 +
6745 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434.h
6746 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434.h 1970-01-01 01:00:00.000000000 +0100
6747 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434.h 2006-03-20 14:25:10.000000000 +0100
6748 @@ -0,0 +1,199 @@
6749 + /**************************************************************************
6750 + *
6751 + * BRIEF MODULE DESCRIPTION
6752 + * Definitions for IDT RC32434 CPU
6753 + *
6754 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6755 + *
6756 + * This program is free software; you can redistribute it and/or modify it
6757 + * under the terms of the GNU General Public License as published by the
6758 + * Free Software Foundation; either version 2 of the License, or (at your
6759 + * option) any later version.
6760 + *
6761 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6762 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6763 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6764 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6765 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6766 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6767 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6768 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6769 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6770 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6771 + *
6772 + * You should have received a copy of the GNU General Public License along
6773 + * with this program; if not, write to the Free Software Foundation, Inc.,
6774 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6775 + *
6776 + *
6777 + **************************************************************************
6778 + * May 2004 rkt, neb.
6779 + *
6780 + * Initial Release
6781 + *
6782 + *
6783 + *
6784 + **************************************************************************
6785 + */
6786 +
6787 +#ifndef _RC32434_H_
6788 +#define _RC32434_H_
6789 +
6790 +#include <linux/config.h>
6791 +#include <linux/delay.h>
6792 +#include <asm/io.h>
6793 +#include <asm/idt-boards/rc32434/rc32434_timer.h>
6794 +
6795 +#define RC32434_REG_BASE 0x18000000
6796 +
6797 +
6798 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
6799 +#define idt_timer ((volatile TIM_t) TIM0_VirtualAddress)
6800 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
6801 +
6802 +#define IDT_CLOCK_MULT 2
6803 +#define MIPS_CPU_TIMER_IRQ 7
6804 +/* Interrupt Controller */
6805 +#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
6806 +#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
6807 +#define IC_GROUP_OFFSET 0x0C
6808 +#define RTC_BASE 0xBA001FF0
6809 +
6810 +#define NUM_INTR_GROUPS 5
6811 +/* 16550 UARTs */
6812 +
6813 +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
6814 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
6815 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
6816 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
6817 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
6818 +
6819 +#ifdef __MIPSEB__
6820 +
6821 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
6822 +#define EB434_UART1_BASE (0x19800003)
6823 +
6824 +#else
6825 +
6826 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
6827 +#define EB434_UART1_BASE (0x19800000)
6828 +
6829 +#endif
6830 +
6831 +#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
6832 +#define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
6833 +
6834 +#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
6835 +
6836 +/* cpu pipeline flush */
6837 +static inline void rc32434_sync(void)
6838 +{
6839 + __asm__ volatile ("sync");
6840 +}
6841 +
6842 +static inline void rc32434_sync_udelay(int us)
6843 +{
6844 + __asm__ volatile ("sync");
6845 + udelay(us);
6846 +}
6847 +
6848 +static inline void rc32434_sync_delay(int ms)
6849 +{
6850 + __asm__ volatile ("sync");
6851 + mdelay(ms);
6852 +}
6853 +
6854 +
6855 +
6856 +/*
6857 + * Macros to access internal RC32434 registers. No byte
6858 + * swapping should be done when accessing the internal
6859 + * registers.
6860 + */
6861 +
6862 +#define rc32434_readb __raw_readb
6863 +#define rc32434_readw __raw_readw
6864 +#define rc32434_readl __raw_readl
6865 +
6866 +#define rc32434_writeb __raw_writeb
6867 +#define rc32434_writew __raw_writew
6868 +#define rc32434_writel __raw_writel
6869 +
6870 +#if 0
6871 +static inline u8 rc32434_readb(unsigned long pa)
6872 +{
6873 + return *((volatile u8 *)KSEG1ADDR(pa));
6874 +}
6875 +static inline u16 rc32434_readw(unsigned long pa)
6876 +{
6877 + return *((volatile u16 *)KSEG1ADDR(pa));
6878 +}
6879 +static inline u32 rc32434_readl(unsigned long pa)
6880 +{
6881 + return *((volatile u32 *)KSEG1ADDR(pa));
6882 +}
6883 +static inline void rc32434_writeb(u8 val, unsigned long pa)
6884 +{
6885 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
6886 +}
6887 +static inline void rc32434_writew(u16 val, unsigned long pa)
6888 +{
6889 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
6890 +}
6891 +static inline void rc32434_writel(u32 val, unsigned long pa)
6892 +{
6893 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
6894 +}
6895 +
6896 +#endif
6897 +
6898 +
6899 +/*
6900 + * C access to CLZ and CLO instructions
6901 + * (count leading zeroes/ones).
6902 + */
6903 +static inline int rc32434_clz(unsigned long val)
6904 +{
6905 + int ret;
6906 + __asm__ volatile (
6907 + ".set\tnoreorder\n\t"
6908 + ".set\tnoat\n\t"
6909 + ".set\tmips32\n\t"
6910 + "clz\t%0,%1\n\t"
6911 + ".set\tmips0\n\t"
6912 + ".set\tat\n\t"
6913 + ".set\treorder"
6914 + : "=r" (ret)
6915 + : "r" (val));
6916 +
6917 + return ret;
6918 +}
6919 +static inline int rc32434_clo(unsigned long val)
6920 +{
6921 + int ret;
6922 + __asm__ volatile (
6923 + ".set\tnoreorder\n\t"
6924 + ".set\tnoat\n\t"
6925 + ".set\tmips32\n\t"
6926 + "clo\t%0,%1\n\t"
6927 + ".set\tmips0\n\t"
6928 + ".set\tat\n\t"
6929 + ".set\treorder"
6930 + : "=r" (ret)
6931 + : "r" (val));
6932 +
6933 + return ret;
6934 +}
6935 +#endif /* _RC32434_H_ */
6936 +
6937 +
6938 +
6939 +
6940 +
6941 +
6942 +
6943 +
6944 +
6945 +
6946 +
6947 +
6948 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_integ.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h
6949 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_integ.h 1970-01-01 01:00:00.000000000 +0100
6950 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h 2006-03-20 14:25:10.000000000 +0100
6951 @@ -0,0 +1,90 @@
6952 +/**************************************************************************
6953 + *
6954 + * BRIEF MODULE DESCRIPTION
6955 + * System Integrity register definition
6956 + *
6957 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6958 + *
6959 + * This program is free software; you can redistribute it and/or modify it
6960 + * under the terms of the GNU General Public License as published by the
6961 + * Free Software Foundation; either version 2 of the License, or (at your
6962 + * option) any later version.
6963 + *
6964 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6965 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6966 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6967 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6968 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6969 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6970 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6971 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6972 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6973 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6974 + *
6975 + * You should have received a copy of the GNU General Public License along
6976 + * with this program; if not, write to the Free Software Foundation, Inc.,
6977 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6978 + *
6979 + *
6980 + **************************************************************************
6981 + * May 2004 rkt, neb
6982 + *
6983 + * Initial Release
6984 + *
6985 + *
6986 + *
6987 + **************************************************************************
6988 + */
6989 +
6990 +#ifndef __IDT_INTEG_H__
6991 +#define __IDT_INTEG_H__
6992 +
6993 +enum
6994 +{
6995 + INTEG0_PhysicalAddress = 0x18030000,
6996 + INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default
6997 +
6998 + INTEG0_VirtualAddress = 0xB8030000,
6999 + INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default
7000 +} ;
7001 +
7002 +// if you are looking for CEA, try rst.h
7003 +typedef struct
7004 +{
7005 + u32 filler [0xc] ; // 0x30 bytes unused.
7006 + u32 errcs ; // sticky use ERRCS_
7007 + u32 wtcount ; // Watchdog timer count reg.
7008 + u32 wtcompare ; // Watchdog timer timeout value.
7009 + u32 wtc ; // Watchdog timer control. use WTC_
7010 +} volatile *INTEG_t ;
7011 +
7012 +enum
7013 +{
7014 + ERRCS_wto_b = 0, // In INTEG_t -> errcs
7015 + ERRCS_wto_m = 0x00000001,
7016 + ERRCS_wne_b = 1, // In INTEG_t -> errcs
7017 + ERRCS_wne_m = 0x00000002,
7018 + ERRCS_ucw_b = 2, // In INTEG_t -> errcs
7019 + ERRCS_ucw_m = 0x00000004,
7020 + ERRCS_ucr_b = 3, // In INTEG_t -> errcs
7021 + ERRCS_ucr_m = 0x00000008,
7022 + ERRCS_upw_b = 4, // In INTEG_t -> errcs
7023 + ERRCS_upw_m = 0x00000010,
7024 + ERRCS_upr_b = 5, // In INTEG_t -> errcs
7025 + ERRCS_upr_m = 0x00000020,
7026 + ERRCS_udw_b = 6, // In INTEG_t -> errcs
7027 + ERRCS_udw_m = 0x00000040,
7028 + ERRCS_udr_b = 7, // In INTEG_t -> errcs
7029 + ERRCS_udr_m = 0x00000080,
7030 + ERRCS_sae_b = 8, // In INTEG_t -> errcs
7031 + ERRCS_sae_m = 0x00000100,
7032 + ERRCS_wre_b = 9, // In INTEG_t -> errcs
7033 + ERRCS_wre_m = 0x00000200,
7034 +
7035 + WTC_en_b = 0, // In INTEG_t -> wtc
7036 + WTC_en_m = 0x00000001,
7037 + WTC_to_b = 1, // In INTEG_t -> wtc
7038 + WTC_to_m = 0x00000002,
7039 +} ;
7040 +
7041 +#endif // __IDT_INTEG_H__
7042 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_int.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h
7043 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_int.h 1970-01-01 01:00:00.000000000 +0100
7044 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h 2006-03-20 14:25:10.000000000 +0100
7045 @@ -0,0 +1,174 @@
7046 +/**************************************************************************
7047 + *
7048 + * BRIEF MODULE DESCRIPTION
7049 + * Interrupt Controller register definition.
7050 + *
7051 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7052 + *
7053 + * This program is free software; you can redistribute it and/or modify it
7054 + * under the terms of the GNU General Public License as published by the
7055 + * Free Software Foundation; either version 2 of the License, or (at your
7056 + * option) any later version.
7057 + *
7058 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7059 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7060 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7061 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7062 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7063 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7064 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7065 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7066 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7067 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7068 + *
7069 + * You should have received a copy of the GNU General Public License along
7070 + * with this program; if not, write to the Free Software Foundation, Inc.,
7071 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7072 + *
7073 + *
7074 + **************************************************************************
7075 + * May 2004 rkt, neb.
7076 + *
7077 + * Initial Release
7078 + *
7079 + *
7080 + *
7081 + **************************************************************************
7082 + */
7083 +
7084 +#ifndef __IDT_INT_H__
7085 +#define __IDT_INT_H__
7086 +
7087 +enum
7088 +{
7089 + INT0_PhysicalAddress = 0x18038000,
7090 + INT_PhysicalAddress = INT0_PhysicalAddress, // Default
7091 +
7092 + INT0_VirtualAddress = 0xB8038000,
7093 + INT_VirtualAddress = INT0_VirtualAddress, // Default
7094 +} ;
7095 +
7096 +struct INT_s
7097 +{
7098 + u32 ipend ; //Pending interrupts. use INT?_
7099 + u32 itest ; //Test bits. use INT?_
7100 + u32 imask ; //Interrupt disabled when set. use INT?_
7101 +} ;
7102 +
7103 +enum
7104 +{
7105 + IPEND2 = 0, // HW 2 interrupt to core. use INT2_
7106 + IPEND3 = 1, // HW 3 interrupt to core. use INT3_
7107 + IPEND4 = 2, // HW 4 interrupt to core. use INT4_
7108 + IPEND5 = 3, // HW 5 interrupt to core. use INT5_
7109 + IPEND6 = 4, // HW 6 interrupt to core. use INT6_
7110 +
7111 + IPEND_count, // must be last (used in loops)
7112 + IPEND_min = IPEND2 // min IPEND (used in loops)
7113 +};
7114 +
7115 +typedef struct INTC_s
7116 +{
7117 + struct INT_s i [IPEND_count] ;// use i[IPEND?] = INT?_
7118 + u32 nmips ; // use NMIPS_
7119 +} volatile *INT_t ;
7120 +
7121 +enum
7122 +{
7123 + INT2_timer0_b = 0,
7124 + INT2_timer0_m = 0x00000001,
7125 + INT2_timer1_b = 1,
7126 + INT2_timer1_m = 0x00000002,
7127 + INT2_timer2_b = 2,
7128 + INT2_timer2_m = 0x00000004,
7129 + INT2_refresh_b = 3,
7130 + INT2_refresh_m = 0x00000008,
7131 + INT2_watchdogTimeout_b = 4,
7132 + INT2_watchdogTimeout_m = 0x00000010,
7133 + INT2_undecodedCpuWrite_b = 5,
7134 + INT2_undecodedCpuWrite_m = 0x00000020,
7135 + INT2_undecodedCpuRead_b = 6,
7136 + INT2_undecodedCpuRead_m = 0x00000040,
7137 + INT2_undecodedPciWrite_b = 7,
7138 + INT2_undecodedPciWrite_m = 0x00000080,
7139 + INT2_undecodedPciRead_b = 8,
7140 + INT2_undecodedPciRead_m = 0x00000100,
7141 + INT2_undecodedDmaWrite_b = 9,
7142 + INT2_undecodedDmaWrite_m = 0x00000200,
7143 + INT2_undecodedDmaRead_b = 10,
7144 + INT2_undecodedDmaRead_m = 0x00000400,
7145 + INT2_ipBusSlaveAckError_b = 11,
7146 + INT2_ipBusSlaveAckError_m = 0x00000800,
7147 +
7148 + INT3_dmaChannel0_b = 0,
7149 + INT3_dmaChannel0_m = 0x00000001,
7150 + INT3_dmaChannel1_b = 1,
7151 + INT3_dmaChannel1_m = 0x00000002,
7152 + INT3_dmaChannel2_b = 2,
7153 + INT3_dmaChannel2_m = 0x00000004,
7154 + INT3_dmaChannel3_b = 3,
7155 + INT3_dmaChannel3_m = 0x00000008,
7156 + INT3_dmaChannel4_b = 4,
7157 + INT3_dmaChannel4_m = 0x00000010,
7158 + INT3_dmaChannel5_b = 5,
7159 + INT3_dmaChannel5_m = 0x00000020,
7160 +
7161 + INT5_uartGeneral0_b = 0,
7162 + INT5_uartGeneral0_m = 0x00000001,
7163 + INT5_uartTxrdy0_b = 1,
7164 + INT5_uartTxrdy0_m = 0x00000002,
7165 + INT5_uartRxrdy0_b = 2,
7166 + INT5_uartRxrdy0_m = 0x00000004,
7167 + INT5_pci_b = 3,
7168 + INT5_pci_m = 0x00000008,
7169 + INT5_pciDecoupled_b = 4,
7170 + INT5_pciDecoupled_m = 0x00000010,
7171 + INT5_spi_b = 5,
7172 + INT5_spi_m = 0x00000020,
7173 + INT5_deviceDecoupled_b = 6,
7174 + INT5_deviceDecoupled_m = 0x00000040,
7175 + INT5_eth0Ovr_b = 9,
7176 + INT5_eth0Ovr_m = 0x00000200,
7177 + INT5_eth0Und_b = 10,
7178 + INT5_eth0Und_m = 0x00000400,
7179 + INT5_eth0Pfd_b = 11,
7180 + INT5_eth0Pfd_m = 0x00000800,
7181 + INT5_nvram_b = 12,
7182 + INT5_nvram_m = 0x00001000,
7183 +
7184 + INT6_gpio0_b = 0,
7185 + INT6_gpio0_m = 0x00000001,
7186 + INT6_gpio1_b = 1,
7187 + INT6_gpio1_m = 0x00000002,
7188 + INT6_gpio2_b = 2,
7189 + INT6_gpio2_m = 0x00000004,
7190 + INT6_gpio3_b = 3,
7191 + INT6_gpio3_m = 0x00000008,
7192 + INT6_gpio4_b = 4,
7193 + INT6_gpio4_m = 0x00000010,
7194 + INT6_gpio5_b = 5,
7195 + INT6_gpio5_m = 0x00000020,
7196 + INT6_gpio6_b = 6,
7197 + INT6_gpio6_m = 0x00000040,
7198 + INT6_gpio7_b = 7,
7199 + INT6_gpio7_m = 0x00000080,
7200 + INT6_gpio8_b = 8,
7201 + INT6_gpio8_m = 0x00000100,
7202 + INT6_gpio9_b = 9,
7203 + INT6_gpio9_m = 0x00000200,
7204 + INT6_gpio10_b = 10,
7205 + INT6_gpio10_m = 0x00000400,
7206 + INT6_gpio11_b = 11,
7207 + INT6_gpio11_m = 0x00000800,
7208 + INT6_gpio12_b = 12,
7209 + INT6_gpio12_m = 0x00001000,
7210 + INT6_gpio13_b = 13,
7211 + INT6_gpio13_m = 0x00002000,
7212 +
7213 + NMIPS_gpio_b = 0,
7214 + NMIPS_gpio_m = 0x00000001,
7215 +} ;
7216 +
7217 +#endif // __IDT_INT_H__
7218 +
7219 +
7220 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h
7221 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h 1970-01-01 01:00:00.000000000 +0100
7222 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h 2006-03-20 14:25:10.000000000 +0100
7223 @@ -0,0 +1,111 @@
7224 +/**************************************************************************
7225 + *
7226 + * BRIEF MODULE DESCRIPTION
7227 + * IP Arbiter register definitions
7228 + *
7229 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7230 + *
7231 + * This program is free software; you can redistribute it and/or modify it
7232 + * under the terms of the GNU General Public License as published by the
7233 + * Free Software Foundation; either version 2 of the License, or (at your
7234 + * option) any later version.
7235 + *
7236 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7237 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7238 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7239 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7240 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7241 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7242 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7243 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7244 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7245 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7246 + *
7247 + * You should have received a copy of the GNU General Public License along
7248 + * with this program; if not, write to the Free Software Foundation, Inc.,
7249 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7250 + *
7251 + *
7252 + **************************************************************************
7253 + * May 2004 rkt,neb
7254 + *
7255 + * Initial Release
7256 + *
7257 + *
7258 + *
7259 + **************************************************************************
7260 + */
7261 +
7262 +#ifndef __IDT_IPARB_H__
7263 +#define __IDT_IPARB_H__
7264 +
7265 +enum
7266 +{
7267 + IPARB0_PhysicalAddress = 0x18048000,
7268 + IPARB_PhysicalAddress = IPARB0_PhysicalAddress, // Default
7269 +
7270 + IPARB0_VirtualAddress = 0xB8048000,
7271 + IPARB_VirtualAddress = IPARB0_VirtualAddress, // Default
7272 +} ;
7273 +
7274 +enum
7275 +{
7276 + IPABMXC_ethernet0Receive = 0,
7277 + IPABMXC_ethernet0Transmit = 1,
7278 + IPABMXC_memoryToHoldFifo = 2,
7279 + IPABMXC_holdFifoToMemory = 3,
7280 + IPABMXC_pciToMemory = 4,
7281 + IPABMXC_memoryToPci = 5,
7282 + IPABMXC_pciTarget = 6,
7283 + IPABMXC_pciTargetStart = 7,
7284 + IPABMXC_cpuToIpBus = 8,
7285 +
7286 + IPABMXC_Count, // Must be last in list !
7287 + IPABMXC_Min = IPABMXC_ethernet0Receive,
7288 +
7289 + IPAPXC_PriorityCount = 4, // 3-highest, 0-lowest.
7290 +} ;
7291 +
7292 +typedef struct
7293 +{
7294 + u32 ipapc [IPAPXC_PriorityCount] ; // ipapc[IPAPXC_] = IPAPC_
7295 + u32 ipabmc [IPABMXC_Count] ; // ipabmc[IPABMXC_] = IPABMC_
7296 + u32 ipac ; // use IPAC_
7297 + u32 ipaitcc; // use IPAITCC_
7298 + u32 ipaspare ;
7299 +} volatile * IPARB_t ;
7300 +
7301 +enum
7302 +{
7303 + IPAC_dp_b = 0,
7304 + IPAC_dp_m = 0x00000001,
7305 + IPAC_dep_b = 1,
7306 + IPAC_dep_m = 0x00000002,
7307 + IPAC_drm_b = 2,
7308 + IPAC_drm_m = 0x00000004,
7309 + IPAC_dwm_b = 3,
7310 + IPAC_dwm_m = 0x00000008,
7311 + IPAC_msk_b = 4,
7312 + IPAC_msk_m = 0x00000010,
7313 +
7314 + IPAPC_ptc_b = 0,
7315 + IPAPC_ptc_m = 0x00003fff,
7316 + IPAPC_mf_b = 14,
7317 + IPAPC_mf_m = 0x00004000,
7318 + IPAPC_cptc_b = 16,
7319 + IPAPC_cptc_m = 0x3fff0000,
7320 +
7321 + IPAITCC_itcc = 0,
7322 + IPAITCC_itcc, = 0x000001ff,
7323 +
7324 + IPABMC_mtc_b = 0,
7325 + IPABMC_mtc_m = 0x00000fff,
7326 + IPABMC_p_b = 12,
7327 + IPABMC_p_m = 0x00003000,
7328 + IPABMC_msk_b = 14,
7329 + IPABMC_msk_m = 0x00004000,
7330 + IPABMC_cmtc_b = 16,
7331 + IPABMC_cmtc_m = 0x0fff0000,
7332 +};
7333 +
7334 +#endif // __IDT_IPARB_H__
7335 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_pci.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h
7336 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 1970-01-01 01:00:00.000000000 +0100
7337 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 2006-03-20 14:25:10.000000000 +0100
7338 @@ -0,0 +1,695 @@
7339 +/**************************************************************************
7340 + *
7341 + * BRIEF MODULE DESCRIPTION
7342 + * PCI register definitio
7343 + *
7344 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7345 + *
7346 + * This program is free software; you can redistribute it and/or modify it
7347 + * under the terms of the GNU General Public License as published by the
7348 + * Free Software Foundation; either version 2 of the License, or (at your
7349 + * option) any later version.
7350 + *
7351 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7352 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7353 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7354 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7355 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7356 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7357 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7358 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7359 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7360 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7361 + *
7362 + * You should have received a copy of the GNU General Public License along
7363 + * with this program; if not, write to the Free Software Foundation, Inc.,
7364 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7365 + *
7366 + *
7367 + **************************************************************************
7368 + * May 2004 rkt, neb.
7369 + *
7370 + * Initial Release
7371 + *
7372 + *
7373 + *
7374 + **************************************************************************
7375 + */
7376 +
7377 +#ifndef __IDT_PCI_H__
7378 +#define __IDT_PCI_H__
7379 +
7380 +enum
7381 +{
7382 + PCI0_PhysicalAddress = 0x18080000,
7383 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
7384 +
7385 + PCI0_VirtualAddress = 0xB8080000,
7386 + PCI_VirtualAddress = PCI0_VirtualAddress,
7387 +} ;
7388 +
7389 +enum
7390 +{
7391 + PCI_LbaCount = 4, // Local base addresses.
7392 +} ;
7393 +
7394 +typedef struct
7395 +{
7396 + u32 a ; // Address.
7397 + u32 c ; // Control.
7398 + u32 m ; // mapping.
7399 +} PCI_Map_s ;
7400 +
7401 +typedef struct
7402 +{
7403 + u32 pcic ;
7404 + u32 pcis ;
7405 + u32 pcism ;
7406 + u32 pcicfga ;
7407 + u32 pcicfgd ;
7408 + PCI_Map_s pcilba [PCI_LbaCount] ;
7409 + u32 pcidac ;
7410 + u32 pcidas ;
7411 + u32 pcidasm ;
7412 + u32 pcidad ;
7413 + u32 pcidma8c ;
7414 + u32 pcidma9c ;
7415 + u32 pcitc ;
7416 +} volatile *PCI_t ;
7417 +
7418 +// PCI messaging unit.
7419 +enum
7420 +{
7421 + PCIM_Count = 2,
7422 +} ;
7423 +typedef struct
7424 +{
7425 + u32 pciim [PCIM_Count] ;
7426 + u32 pciom [PCIM_Count] ;
7427 + u32 pciid ;
7428 + u32 pciiic ;
7429 + u32 pciiim ;
7430 + u32 pciiod ;
7431 + u32 pciioic ;
7432 + u32 pciioim ;
7433 +} volatile *PCIM_t ;
7434 +
7435 +/*******************************************************************************
7436 + *
7437 + * PCI Control Register
7438 + *
7439 + ******************************************************************************/
7440 +enum
7441 +{
7442 + PCIC_en_b = 0,
7443 + PCIC_en_m = 0x00000001,
7444 + PCIC_tnr_b = 1,
7445 + PCIC_tnr_m = 0x00000002,
7446 + PCIC_sce_b = 2,
7447 + PCIC_sce_m = 0x00000004,
7448 + PCIC_ien_b = 3,
7449 + PCIC_ien_m = 0x00000008,
7450 + PCIC_aaa_b = 4,
7451 + PCIC_aaa_m = 0x00000010,
7452 + PCIC_eap_b = 5,
7453 + PCIC_eap_m = 0x00000020,
7454 + PCIC_pcim_b = 6,
7455 + PCIC_pcim_m = 0x000001c0,
7456 + PCIC_pcim_disabled_v = 0,
7457 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
7458 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
7459 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
7460 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
7461 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
7462 + PCIC_pcim_reserved6_v = 6,
7463 + PCIC_pcim_reserved7_v = 7,
7464 + PCIC_igm_b = 9,
7465 + PCIC_igm_m = 0x00000200,
7466 +} ;
7467 +
7468 +/*******************************************************************************
7469 + *
7470 + * PCI Status Register
7471 + *
7472 + ******************************************************************************/
7473 +enum {
7474 + PCIS_eed_b = 0,
7475 + PCIS_eed_m = 0x00000001,
7476 + PCIS_wr_b = 1,
7477 + PCIS_wr_m = 0x00000002,
7478 + PCIS_nmi_b = 2,
7479 + PCIS_nmi_m = 0x00000004,
7480 + PCIS_ii_b = 3,
7481 + PCIS_ii_m = 0x00000008,
7482 + PCIS_cwe_b = 4,
7483 + PCIS_cwe_m = 0x00000010,
7484 + PCIS_cre_b = 5,
7485 + PCIS_cre_m = 0x00000020,
7486 + PCIS_mdpe_b = 6,
7487 + PCIS_mdpe_m = 0x00000040,
7488 + PCIS_sta_b = 7,
7489 + PCIS_sta_m = 0x00000080,
7490 + PCIS_rta_b = 8,
7491 + PCIS_rta_m = 0x00000100,
7492 + PCIS_rma_b = 9,
7493 + PCIS_rma_m = 0x00000200,
7494 + PCIS_sse_b = 10,
7495 + PCIS_sse_m = 0x00000400,
7496 + PCIS_ose_b = 11,
7497 + PCIS_ose_m = 0x00000800,
7498 + PCIS_pe_b = 12,
7499 + PCIS_pe_m = 0x00001000,
7500 + PCIS_tae_b = 13,
7501 + PCIS_tae_m = 0x00002000,
7502 + PCIS_rle_b = 14,
7503 + PCIS_rle_m = 0x00004000,
7504 + PCIS_bme_b = 15,
7505 + PCIS_bme_m = 0x00008000,
7506 + PCIS_prd_b = 16,
7507 + PCIS_prd_m = 0x00010000,
7508 + PCIS_rip_b = 17,
7509 + PCIS_rip_m = 0x00020000,
7510 +} ;
7511 +
7512 +/*******************************************************************************
7513 + *
7514 + * PCI Status Mask Register
7515 + *
7516 + ******************************************************************************/
7517 +enum {
7518 + PCISM_eed_b = 0,
7519 + PCISM_eed_m = 0x00000001,
7520 + PCISM_wr_b = 1,
7521 + PCISM_wr_m = 0x00000002,
7522 + PCISM_nmi_b = 2,
7523 + PCISM_nmi_m = 0x00000004,
7524 + PCISM_ii_b = 3,
7525 + PCISM_ii_m = 0x00000008,
7526 + PCISM_cwe_b = 4,
7527 + PCISM_cwe_m = 0x00000010,
7528 + PCISM_cre_b = 5,
7529 + PCISM_cre_m = 0x00000020,
7530 + PCISM_mdpe_b = 6,
7531 + PCISM_mdpe_m = 0x00000040,
7532 + PCISM_sta_b = 7,
7533 + PCISM_sta_m = 0x00000080,
7534 + PCISM_rta_b = 8,
7535 + PCISM_rta_m = 0x00000100,
7536 + PCISM_rma_b = 9,
7537 + PCISM_rma_m = 0x00000200,
7538 + PCISM_sse_b = 10,
7539 + PCISM_sse_m = 0x00000400,
7540 + PCISM_ose_b = 11,
7541 + PCISM_ose_m = 0x00000800,
7542 + PCISM_pe_b = 12,
7543 + PCISM_pe_m = 0x00001000,
7544 + PCISM_tae_b = 13,
7545 + PCISM_tae_m = 0x00002000,
7546 + PCISM_rle_b = 14,
7547 + PCISM_rle_m = 0x00004000,
7548 + PCISM_bme_b = 15,
7549 + PCISM_bme_m = 0x00008000,
7550 + PCISM_prd_b = 16,
7551 + PCISM_prd_m = 0x00010000,
7552 + PCISM_rip_b = 17,
7553 + PCISM_rip_m = 0x00020000,
7554 +} ;
7555 +
7556 +/*******************************************************************************
7557 + *
7558 + * PCI Configuration Address Register
7559 + *
7560 + ******************************************************************************/
7561 +enum {
7562 + PCICFGA_reg_b = 2,
7563 + PCICFGA_reg_m = 0x000000fc,
7564 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
7565 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
7566 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
7567 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
7568 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
7569 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
7570 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
7571 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
7572 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
7573 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
7574 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
7575 + PCICFGA_reg_pba0m_v = 0x48>>2,
7576 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
7577 + PCICFGA_reg_pba1m_v = 0x50>>2,
7578 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
7579 + PCICFGA_reg_pba2m_v = 0x58>>2,
7580 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
7581 + PCICFGA_reg_pba3m_v = 0x60>>2,
7582 + PCICFGA_reg_pmgt_v = 0x64>>2,
7583 + PCICFGA_func_b = 8,
7584 + PCICFGA_func_m = 0x00000700,
7585 + PCICFGA_dev_b = 11,
7586 + PCICFGA_dev_m = 0x0000f800,
7587 + PCICFGA_dev_internal_v = 0,
7588 + PCICFGA_bus_b = 16,
7589 + PCICFGA_bus_m = 0x00ff0000,
7590 + PCICFGA_bus_type0_v = 0, //local bus
7591 + PCICFGA_en_b = 31, // read only
7592 + PCICFGA_en_m = 0x80000000,
7593 +} ;
7594 +
7595 +enum {
7596 + PCFGID_vendor_b = 0,
7597 + PCFGID_vendor_m = 0x0000ffff,
7598 + PCFGID_vendor_IDT_v = 0x111d,
7599 + PCFGID_device_b = 16,
7600 + PCFGID_device_m = 0xffff0000,
7601 + PCFGID_device_Korinade_v = 0x0214,
7602 +
7603 + PCFG04_command_ioena_b = 1,
7604 + PCFG04_command_ioena_m = 0x00000001,
7605 + PCFG04_command_memena_b = 2,
7606 + PCFG04_command_memena_m = 0x00000002,
7607 + PCFG04_command_bmena_b = 3,
7608 + PCFG04_command_bmena_m = 0x00000004,
7609 + PCFG04_command_mwinv_b = 5,
7610 + PCFG04_command_mwinv_m = 0x00000010,
7611 + PCFG04_command_parena_b = 7,
7612 + PCFG04_command_parena_m = 0x00000040,
7613 + PCFG04_command_serrena_b = 9,
7614 + PCFG04_command_serrena_m = 0x00000100,
7615 + PCFG04_command_fastbbena_b = 10,
7616 + PCFG04_command_fastbbena_m = 0x00000200,
7617 + PCFG04_status_b = 16,
7618 + PCFG04_status_m = 0xffff0000,
7619 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
7620 + PCFG04_status_66MHz_m = 0x00200000,
7621 + PCFG04_status_fbb_b = 23,
7622 + PCFG04_status_fbb_m = 0x00800000,
7623 + PCFG04_status_mdpe_b = 24,
7624 + PCFG04_status_mdpe_m = 0x01000000,
7625 + PCFG04_status_dst_b = 25,
7626 + PCFG04_status_dst_m = 0x06000000,
7627 + PCFG04_status_sta_b = 27,
7628 + PCFG04_status_sta_m = 0x08000000,
7629 + PCFG04_status_rta_b = 28,
7630 + PCFG04_status_rta_m = 0x10000000,
7631 + PCFG04_status_rma_b = 29,
7632 + PCFG04_status_rma_m = 0x20000000,
7633 + PCFG04_status_sse_b = 30,
7634 + PCFG04_status_sse_m = 0x40000000,
7635 + PCFG04_status_pe_b = 31,
7636 + PCFG04_status_pe_m = 0x40000000,
7637 +
7638 + PCFG08_revId_b = 0,
7639 + PCFG08_revId_m = 0x000000ff,
7640 + PCFG08_classCode_b = 0,
7641 + PCFG08_classCode_m = 0xffffff00,
7642 + PCFG08_classCode_bridge_v = 06,
7643 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
7644 + PCFG0C_cacheline_b = 0,
7645 + PCFG0C_cacheline_m = 0x000000ff,
7646 + PCFG0C_masterLatency_b = 8,
7647 + PCFG0C_masterLatency_m = 0x0000ff00,
7648 + PCFG0C_headerType_b = 16,
7649 + PCFG0C_headerType_m = 0x00ff0000,
7650 + PCFG0C_bist_b = 24,
7651 + PCFG0C_bist_m = 0xff000000,
7652 +
7653 + PCIPBA_msi_b = 0,
7654 + PCIPBA_msi_m = 0x00000001,
7655 + PCIPBA_p_b = 3,
7656 + PCIPBA_p_m = 0x00000004,
7657 + PCIPBA_baddr_b = 8,
7658 + PCIPBA_baddr_m = 0xffffff00,
7659 +
7660 + PCFGSS_vendorId_b = 0,
7661 + PCFGSS_vendorId_m = 0x0000ffff,
7662 + PCFGSS_id_b = 16,
7663 + PCFGSS_id_m = 0xffff0000,
7664 +
7665 + PCFG3C_interruptLine_b = 0,
7666 + PCFG3C_interruptLine_m = 0x000000ff,
7667 + PCFG3C_interruptPin_b = 8,
7668 + PCFG3C_interruptPin_m = 0x0000ff00,
7669 + PCFG3C_minGrant_b = 16,
7670 + PCFG3C_minGrant_m = 0x00ff0000,
7671 + PCFG3C_maxLat_b = 24,
7672 + PCFG3C_maxLat_m = 0xff000000,
7673 +
7674 + PCIPBAC_msi_b = 0,
7675 + PCIPBAC_msi_m = 0x00000001,
7676 + PCIPBAC_p_b = 1,
7677 + PCIPBAC_p_m = 0x00000002,
7678 + PCIPBAC_size_b = 2,
7679 + PCIPBAC_size_m = 0x0000007c,
7680 + PCIPBAC_sb_b = 7,
7681 + PCIPBAC_sb_m = 0x00000080,
7682 + PCIPBAC_pp_b = 8,
7683 + PCIPBAC_pp_m = 0x00000100,
7684 + PCIPBAC_mr_b = 9,
7685 + PCIPBAC_mr_m = 0x00000600,
7686 + PCIPBAC_mr_read_v =0, //no prefetching
7687 + PCIPBAC_mr_readLine_v =1,
7688 + PCIPBAC_mr_readMult_v =2,
7689 + PCIPBAC_mrl_b = 11,
7690 + PCIPBAC_mrl_m = 0x00000800,
7691 + PCIPBAC_mrm_b = 12,
7692 + PCIPBAC_mrm_m = 0x00001000,
7693 + PCIPBAC_trp_b = 13,
7694 + PCIPBAC_trp_m = 0x00002000,
7695 +
7696 + PCFG40_trdyTimeout_b = 0,
7697 + PCFG40_trdyTimeout_m = 0x000000ff,
7698 + PCFG40_retryLim_b = 8,
7699 + PCFG40_retryLim_m = 0x0000ff00,
7700 +};
7701 +
7702 +/*******************************************************************************
7703 + *
7704 + * PCI Local Base Address [0|1|2|3] Register
7705 + *
7706 + ******************************************************************************/
7707 +enum {
7708 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
7709 + PCILBA_baddr_m = 0xffffff00,
7710 +} ;
7711 +/*******************************************************************************
7712 + *
7713 + * PCI Local Base Address Control Register
7714 + *
7715 + ******************************************************************************/
7716 +enum {
7717 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
7718 + PCILBAC_msi_m = 0x00000001,
7719 + PCILBAC_msi_mem_v = 0,
7720 + PCILBAC_msi_io_v = 1,
7721 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
7722 + PCILBAC_size_m = 0x0000007c,
7723 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
7724 + PCILBAC_sb_m = 0x00000080,
7725 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
7726 + PCILBAC_rt_m = 0x00000100,
7727 + PCILBAC_rt_noprefetch_v = 0, // mem read
7728 + PCILBAC_rt_prefetch_v = 1, // mem readline
7729 +} ;
7730 +
7731 +/*******************************************************************************
7732 + *
7733 + * PCI Local Base Address [0|1|2|3] Mapping Register
7734 + *
7735 + ******************************************************************************/
7736 +enum {
7737 + PCILBAM_maddr_b = 8,
7738 + PCILBAM_maddr_m = 0xffffff00,
7739 +} ;
7740 +
7741 +/*******************************************************************************
7742 + *
7743 + * PCI Decoupled Access Control Register
7744 + *
7745 + ******************************************************************************/
7746 +enum {
7747 + PCIDAC_den_b = 0,
7748 + PCIDAC_den_m = 0x00000001,
7749 +} ;
7750 +
7751 +/*******************************************************************************
7752 + *
7753 + * PCI Decoupled Access Status Register
7754 + *
7755 + ******************************************************************************/
7756 +enum {
7757 + PCIDAS_d_b = 0,
7758 + PCIDAS_d_m = 0x00000001,
7759 + PCIDAS_b_b = 1,
7760 + PCIDAS_b_m = 0x00000002,
7761 + PCIDAS_e_b = 2,
7762 + PCIDAS_e_m = 0x00000004,
7763 + PCIDAS_ofe_b = 3,
7764 + PCIDAS_ofe_m = 0x00000008,
7765 + PCIDAS_off_b = 4,
7766 + PCIDAS_off_m = 0x00000010,
7767 + PCIDAS_ife_b = 5,
7768 + PCIDAS_ife_m = 0x00000020,
7769 + PCIDAS_iff_b = 6,
7770 + PCIDAS_iff_m = 0x00000040,
7771 +} ;
7772 +
7773 +/*******************************************************************************
7774 + *
7775 + * PCI DMA Channel 8 Configuration Register
7776 + *
7777 + ******************************************************************************/
7778 +enum
7779 +{
7780 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
7781 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
7782 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
7783 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
7784 +} ;
7785 +
7786 +/*******************************************************************************
7787 + *
7788 + * PCI DMA Channel 9 Configuration Register
7789 + *
7790 + ******************************************************************************/
7791 +enum
7792 +{
7793 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
7794 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
7795 +} ;
7796 +
7797 +/*******************************************************************************
7798 + *
7799 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
7800 + *
7801 + ******************************************************************************/
7802 +enum {
7803 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
7804 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
7805 + // These are for reads (DMA channel 8)
7806 + PCIDMAD_devcmd_mr_v = 0, //memory read
7807 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
7808 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
7809 + PCIDMAD_devcmd_ior_v = 3, //I/O read
7810 + // These are for writes (DMA channel 9)
7811 + PCIDMAD_devcmd_mw_v = 0, //memory write
7812 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
7813 + PCIDMAD_devcmd_iow_v = 3, //I/O write
7814 +
7815 + // Swap byte field applies to both DMA channel 8 and 9
7816 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
7817 + PCIDMAD_sb_m = 0x01000000, // swap byte field
7818 +} ;
7819 +
7820 +
7821 +/*******************************************************************************
7822 + *
7823 + * PCI Target Control Register
7824 + *
7825 + ******************************************************************************/
7826 +enum
7827 +{
7828 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
7829 + PCITC_rtimer_m = 0x000000ff,
7830 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
7831 + PCITC_dtimer_m = 0x0000ff00,
7832 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
7833 + PCITC_rdr_m = 0x00040000,
7834 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
7835 + PCITC_ddt_m = 0x00080000,
7836 +} ;
7837 +/*******************************************************************************
7838 + *
7839 + * PCI messaging unit [applies to both inbound and outbound registers ]
7840 + *
7841 + ******************************************************************************/
7842 +enum
7843 +{
7844 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7845 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
7846 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7847 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
7848 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7849 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
7850 +};
7851 +
7852 +
7853 +
7854 +
7855 +
7856 +
7857 +#define PCI_MSG_VirtualAddress 0xB8088010
7858 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
7859 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
7860 +
7861 +#define PCIM_SHFT 0x6
7862 +#define PCIM_BIT_LEN 0x7
7863 +#define PCIM_H_EA 0x3
7864 +#define PCIM_H_IA_FIX 0x4
7865 +#define PCIM_H_IA_RR 0x5
7866 +#if 0
7867 +#define PCI_ADDR_START 0x13000000
7868 +#endif
7869 +
7870 +#define PCI_ADDR_START 0x50000000
7871 +
7872 +#define CPUTOPCI_MEM_WIN 0x02000000
7873 +#define CPUTOPCI_IO_WIN 0x00100000
7874 +#define PCILBA_SIZE_SHFT 2
7875 +#define PCILBA_SIZE_MASK 0x1F
7876 +#define SIZE_256MB 0x1C
7877 +#define SIZE_128MB 0x1B
7878 +#define SIZE_64MB 0x1A
7879 +#define SIZE_32MB 0x19
7880 +#define SIZE_16MB 0x18
7881 +#define SIZE_4MB 0x16
7882 +#define SIZE_2MB 0x15
7883 +#define SIZE_1MB 0x14
7884 +#define KORINA_CONFIG0_ADDR 0x80000000
7885 +#define KORINA_CONFIG1_ADDR 0x80000004
7886 +#define KORINA_CONFIG2_ADDR 0x80000008
7887 +#define KORINA_CONFIG3_ADDR 0x8000000C
7888 +#define KORINA_CONFIG4_ADDR 0x80000010
7889 +#define KORINA_CONFIG5_ADDR 0x80000014
7890 +#define KORINA_CONFIG6_ADDR 0x80000018
7891 +#define KORINA_CONFIG7_ADDR 0x8000001C
7892 +#define KORINA_CONFIG8_ADDR 0x80000020
7893 +#define KORINA_CONFIG9_ADDR 0x80000024
7894 +#define KORINA_CONFIG10_ADDR 0x80000028
7895 +#define KORINA_CONFIG11_ADDR 0x8000002C
7896 +#define KORINA_CONFIG12_ADDR 0x80000030
7897 +#define KORINA_CONFIG13_ADDR 0x80000034
7898 +#define KORINA_CONFIG14_ADDR 0x80000038
7899 +#define KORINA_CONFIG15_ADDR 0x8000003C
7900 +#define KORINA_CONFIG16_ADDR 0x80000040
7901 +#define KORINA_CONFIG17_ADDR 0x80000044
7902 +#define KORINA_CONFIG18_ADDR 0x80000048
7903 +#define KORINA_CONFIG19_ADDR 0x8000004C
7904 +#define KORINA_CONFIG20_ADDR 0x80000050
7905 +#define KORINA_CONFIG21_ADDR 0x80000054
7906 +#define KORINA_CONFIG22_ADDR 0x80000058
7907 +#define KORINA_CONFIG23_ADDR 0x8000005C
7908 +#define KORINA_CONFIG24_ADDR 0x80000060
7909 +#define KORINA_CONFIG25_ADDR 0x80000064
7910 +#define KORINA_CMD (PCFG04_command_ioena_m | \
7911 + PCFG04_command_memena_m | \
7912 + PCFG04_command_bmena_m | \
7913 + PCFG04_command_mwinv_m | \
7914 + PCFG04_command_parena_m | \
7915 + PCFG04_command_serrena_m )
7916 +
7917 +#define KORINA_STAT (PCFG04_status_mdpe_m | \
7918 + PCFG04_status_sta_m | \
7919 + PCFG04_status_rta_m | \
7920 + PCFG04_status_rma_m | \
7921 + PCFG04_status_sse_m | \
7922 + PCFG04_status_pe_m)
7923 +
7924 +#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
7925 +
7926 +#define KORINA_REVID 0
7927 +#define KORINA_CLASS_CODE 0
7928 +#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
7929 + KORINA_REVID)
7930 +
7931 +#define KORINA_CACHE_LINE_SIZE 4
7932 +#define KORINA_MASTER_LAT 0x3c
7933 +#define KORINA_HEADER_TYPE 0
7934 +#define KORINA_BIST 0
7935 +
7936 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
7937 + (KORINA_HEADER_TYPE<<16) | \
7938 + (KORINA_MASTER_LAT<<8) | \
7939 + KORINA_CACHE_LINE_SIZE )
7940 +
7941 +#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
7942 +#define KORINA_BAR1 0x18800001 /* 1 MB IO */
7943 +#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
7944 + internal Registers */
7945 +#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
7946 +
7947 +#define KORINA_CNFG4 KORINA_BAR0
7948 +#define KORINA_CNFG5 KORINA_BAR1
7949 +#define KORINA_CNFG6 KORINA_BAR2
7950 +#define KORINA_CNFG7 KORINA_BAR3
7951 +
7952 +#define KORINA_SUBSYS_VENDOR_ID 0x011d
7953 +#define KORINA_SUBSYSTEM_ID 0x0214
7954 +#define KORINA_CNFG8 0
7955 +#define KORINA_CNFG9 0
7956 +#define KORINA_CNFG10 0
7957 +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
7958 + KORINA_SUBSYSTEM_ID)
7959 +#define KORINA_INT_LINE 1
7960 +#define KORINA_INT_PIN 1
7961 +#define KORINA_MIN_GNT 8
7962 +#define KORINA_MAX_LAT 0x38
7963 +#define KORINA_CNFG12 0
7964 +#define KORINA_CNFG13 0
7965 +#define KORINA_CNFG14 0
7966 +#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
7967 + (KORINA_MIN_GNT<<16) | \
7968 + (KORINA_INT_PIN<<8) | \
7969 + KORINA_INT_LINE)
7970 +#define KORINA_RETRY_LIMIT 0x80
7971 +#define KORINA_TRDY_LIMIT 0x80
7972 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
7973 + KORINA_TRDY_LIMIT)
7974 +#define PCI_PBAxC_R 0x0
7975 +#define PCI_PBAxC_RL 0x1
7976 +#define PCI_PBAxC_RM 0x2
7977 +#define SIZE_SHFT 2
7978 +
7979 +#if defined(__MIPSEB__)
7980 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
7981 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
7982 + PCIPBAC_pp_m | \
7983 + (SIZE_128MB<<SIZE_SHFT) | \
7984 + PCIPBAC_p_m)
7985 +#else
7986 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
7987 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
7988 + PCIPBAC_pp_m | \
7989 + (SIZE_128MB<<SIZE_SHFT) | \
7990 + PCIPBAC_p_m)
7991 +#endif
7992 +#define KORINA_CNFG17 KORINA_PBA0C
7993 +#define KORINA_PBA0M 0x0
7994 +#define KORINA_CNFG18 KORINA_PBA0M
7995 +
7996 +#if defined(__MIPSEB__)
7997 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
7998 + PCIPBAC_msi_m)
7999 +#else
8000 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
8001 + PCIPBAC_msi_m)
8002 +#endif
8003 +#define KORINA_CNFG19 KORINA_PBA1C
8004 +#define KORINA_PBA1M 0x0
8005 +#define KORINA_CNFG20 KORINA_PBA1M
8006 +
8007 +#if defined(__MIPSEB__)
8008 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
8009 + PCIPBAC_msi_m)
8010 +#else
8011 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
8012 + PCIPBAC_msi_m)
8013 +#endif
8014 +#define KORINA_CNFG21 KORINA_PBA2C
8015 +#define KORINA_PBA2M 0x18000000
8016 +#define KORINA_CNFG22 KORINA_PBA2M
8017 +#define KORINA_PBA3C 0
8018 +#define KORINA_CNFG23 KORINA_PBA3C
8019 +#define KORINA_PBA3M 0
8020 +#define KORINA_CNFG24 KORINA_PBA3M
8021 +
8022 +
8023 +
8024 +#define PCITC_DTIMER_VAL 8
8025 +#define PCITC_RTIMER_VAL 0x10
8026 +
8027 +
8028 +
8029 +
8030 +#endif // __IDT_PCI_H__
8031 +
8032 +
8033 +
8034 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_rst.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h
8035 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 1970-01-01 01:00:00.000000000 +0100
8036 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 2006-03-20 14:25:10.000000000 +0100
8037 @@ -0,0 +1,119 @@
8038 +/**************************************************************************
8039 + *
8040 + * BRIEF MODULE DESCRIPTION
8041 + * Reset register definitions.
8042 + *
8043 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8044 + *
8045 + * This program is free software; you can redistribute it and/or modify it
8046 + * under the terms of the GNU General Public License as published by the
8047 + * Free Software Foundation; either version 2 of the License, or (at your
8048 + * option) any later version.
8049 + *
8050 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8051 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8052 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8053 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8054 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8055 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8056 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8057 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8058 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8059 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8060 + *
8061 + * You should have received a copy of the GNU General Public License along
8062 + * with this program; if not, write to the Free Software Foundation, Inc.,
8063 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8064 + *
8065 + *
8066 + **************************************************************************
8067 + * May 2004 rkt, neb.
8068 + *
8069 + * Initial Release
8070 + *
8071 + *
8072 + *
8073 + **************************************************************************
8074 + */
8075 +
8076 +#ifndef __IDT_RST_H__
8077 +#define __IDT_RST_H__
8078 +
8079 +enum
8080 +{
8081 + RST0_PhysicalAddress = 0x18000000,
8082 + RST_PhysicalAddress = RST0_PhysicalAddress, // Default
8083 +
8084 + RST0_VirtualAddress = 0xb8000000,
8085 + RST_VirtualAddress = RST0_VirtualAddress, // Default
8086 +} ;
8087 +
8088 +typedef struct RST_s
8089 +{
8090 + u32 filler [0x0006] ;
8091 + u32 sysid ;
8092 + u32 filler2 [0x2000-8] ; // Pad out to offset 0x8000
8093 + u32 reset ;
8094 + u32 bcv ;
8095 + u32 cea ;
8096 +} volatile * RST_t ;
8097 +
8098 +enum
8099 +{
8100 + SYSID_rev_b = 0,
8101 + SYSID_rev_m = 0x000000ff,
8102 + SYSID_imp_b = 8,
8103 + SYSID_imp_m = 0x000fff00,
8104 + SYSID_vendor_b = 8,
8105 + SYSID_vendor_m = 0xfff00000,
8106 +
8107 + BCV_pll_b = 0,
8108 + BCV_pll_m = 0x0000000f,
8109 + BCV_pll_PLLBypass_v = 0x0, // PCLK=1*CLK.
8110 + BCV_pll_Mul3_v = 0x1, // PCLK=3*CLK.
8111 + BCV_pll_Mul4_v = 0x2, // PCLK=4*CLK.
8112 + BCV_pll_SlowMul5_v = 0x3, // PCLK=5*CLK.
8113 + BCV_pll_Mul5_v = 0x4, // PCLK=5*CLK.
8114 + BCV_pll_SlowMul6_v = 0x5, // PCLK=6*CLK.
8115 + BCV_pll_Mul6_v = 0x6, // PCLK=6*CLK.
8116 + BCV_pll_Mul8_v = 0x7, // PCLK=8*CLK.
8117 + BCV_pll_Mul10_v = 0x8, // PCLK=10*CLK.
8118 + BCV_pll_Res9_v = 0x9,
8119 + BCV_pll_Res10_v = 0xa,
8120 + BCV_pll_Res11_v = 0xb,
8121 + BCV_pll_Res12_v = 0xc,
8122 + BCV_pll_Res13_v = 0xd,
8123 + BCV_pll_Res14_v = 0xe,
8124 + BCV_pll_Res15_v = 0xf,
8125 + BCV_clkDiv_b = 4,
8126 + BCV_clkDiv_m = 0x00000030,
8127 + BCV_clkDiv_Div1_v = 0x0,
8128 + BCV_clkDiv_Div2_v = 0x1,
8129 + BCV_clkDiv_Div4_v = 0x2,
8130 + BCV_clkDiv_Res3_v = 0x3,
8131 + BCV_bigEndian_b = 6,
8132 + BCV_bigEndian_m = 0x00000040,
8133 + BCV_resetFast_b = 7,
8134 + BCV_resetFast_m = 0x00000080,
8135 + BCV_pciMode_b = 8,
8136 + BCV_pciMode_m = 0x00000700,
8137 + BCV_pciMode_disabled_v = 0, // PCI is disabled.
8138 + BCV_pciMode_tnr_v = 1, // satellite Target Not Ready.
8139 + BCV_pciMode_suspended_v = 2, // satellite with suspended CPU.
8140 + BCV_pciMode_external_v = 3, // host, external arbiter.
8141 + BCV_pciMode_fixed_v = 4, // host, fixed priority arbiter.
8142 + BCV_pciMode_roundRobin_v= 5, // host, round robin arbiter.
8143 + BCV_pciMode_res6_v = 6,
8144 + BCV_pciMode_res7_v = 7,
8145 + BCV_watchDisable_b = 11,
8146 + BCV_watchDisable_m = 0x00000800,
8147 + BCV_res12_b = 12,
8148 + BCV_res12_m = 0x00001000,
8149 + BCV_res13_b = 13,
8150 + BCV_res13_m = 0x00002000,
8151 + BCV_res14_b = 14,
8152 + BCV_res14_m = 0x00004000,
8153 + BCV_res15_b = 15,
8154 + BCV_res15_m = 0x00008000,
8155 +} ;
8156 +#endif // __IDT_RST_H__
8157 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_spi.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h
8158 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 1970-01-01 01:00:00.000000000 +0100
8159 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 2006-03-20 14:25:10.000000000 +0100
8160 @@ -0,0 +1,120 @@
8161 +/**************************************************************************
8162 + *
8163 + * BRIEF MODULE DESCRIPTION
8164 + * Serial Peripheral Interface register definitions.
8165 + *
8166 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8167 + *
8168 + * This program is free software; you can redistribute it and/or modify it
8169 + * under the terms of the GNU General Public License as published by the
8170 + * Free Software Foundation; either version 2 of the License, or (at your
8171 + * option) any later version.
8172 + *
8173 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8174 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8175 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8176 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8177 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8178 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8179 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8180 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8181 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8182 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8183 + *
8184 + * You should have received a copy of the GNU General Public License along
8185 + * with this program; if not, write to the Free Software Foundation, Inc.,
8186 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8187 + *
8188 + *
8189 + **************************************************************************
8190 + * May 2004 rkt, neb.
8191 + *
8192 + * Initial Release
8193 + *
8194 + *
8195 + *
8196 + **************************************************************************
8197 + */
8198 +
8199 +#ifndef __IDT_SPI_H__
8200 +#define __IDT_SPI_H__
8201 +
8202 +enum
8203 +{
8204 + SPI0_PhysicalAddress = 0x18070000,
8205 + SPI_PhysicalAddress = SPI0_PhysicalAddress,
8206 +
8207 + SPI0_VirtualAddress = 0xB8070000,
8208 + SPI_VirtualAddress = SPI0_VirtualAddress,
8209 +} ;
8210 +
8211 +typedef struct
8212 +{
8213 + u32 spcp ; // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
8214 + u32 spc ; // spi control reg use SPC_
8215 + u32 sps ; // spi status reg use SPS_
8216 + u32 spd ; // spi data reg use SPD_
8217 + u32 siofunc ; // serial IO function use SIOFUNC_
8218 + u32 siocfg ; // serial IO config use SIOCFG_
8219 + u32 siod; // serial IO data use SIOD_
8220 +} volatile *SPI_t ;
8221 +
8222 +enum
8223 +{
8224 + SPCP_div_b = 0,
8225 + SPCP_div_m = 0x000000ff,
8226 + SPC_spr_b = 0,
8227 + SPC_spr_m = 0x00000003,
8228 + SPC_spr_div2_v = 0,
8229 + SPC_spr_div4_v = 1,
8230 + SPC_spr_div16_v = 2,
8231 + SPC_spr_div32_v = 3,
8232 + SPC_cpha_b = 2,
8233 + SPC_cpha_m = 0x00000004,
8234 + SPC_cpol_b = 3,
8235 + SPC_cpol_m = 0x00000008,
8236 + SPC_mstr_b = 4,
8237 + SPC_mstr_m = 0x00000010,
8238 + SPC_spe_b = 6,
8239 + SPC_spe_m = 0x00000040,
8240 + SPC_spie_b = 7,
8241 + SPC_spie_m = 0x00000080,
8242 +
8243 + SPS_modf_b = 4,
8244 + SPS_modf_m = 0x00000010,
8245 + SPS_wcol_b = 6,
8246 + SPS_wcol_m = 0x00000040,
8247 + SPS_spif_b = 7,
8248 + SPS_spif_m = 0x00000070,
8249 +
8250 + SPD_data_b = 0,
8251 + SPD_data_m = 0x000000ff,
8252 +
8253 + SIOFUNC_sdo_b = 0,
8254 + SIOFUNC_sdo_m = 0x00000001,
8255 + SIOFUNC_sdi_b = 1,
8256 + SIOFUNC_sdi_m = 0x00000002,
8257 + SIOFUNC_sck_b = 2,
8258 + SIOFUNC_sck_m = 0x00000004,
8259 + SIOFUNC_pci_b = 3,
8260 + SIOFUNC_pci_m = 0x00000008,
8261 +
8262 + SIOCFG_sdo_b = 0,
8263 + SIOCFG_sdo_m = 0x00000001,
8264 + SIOCFG_sdi_b = 1,
8265 + SIOCFG_sdi_m = 0x00000002,
8266 + SIOCFG_sck_b = 2,
8267 + SIOCFG_sck_m = 0x00000004,
8268 + SIOCFG_pci_b = 3,
8269 + SIOCFG_pci_m = 0x00000008,
8270 +
8271 + SIOD_sdo_b = 0,
8272 + SIOD_sdo_m = 0x00000001,
8273 + SIOD_sdi_b = 1,
8274 + SIOD_sdi_m = 0x00000002,
8275 + SIOD_sck_b = 2,
8276 + SIOD_sck_m = 0x00000004,
8277 + SIOD_pci_b = 3,
8278 + SIOD_pci_m = 0x00000008,
8279 +} ;
8280 +#endif // __IDT_SPI_H__
8281 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_timer.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h
8282 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_timer.h 1970-01-01 01:00:00.000000000 +0100
8283 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h 2006-03-20 14:25:10.000000000 +0100
8284 @@ -0,0 +1,91 @@
8285 +/**************************************************************************
8286 + *
8287 + * BRIEF MODULE DESCRIPTION
8288 + * Definitions for timer registers
8289 + *
8290 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8291 + *
8292 + * This program is free software; you can redistribute it and/or modify it
8293 + * under the terms of the GNU General Public License as published by the
8294 + * Free Software Foundation; either version 2 of the License, or (at your
8295 + * option) any later version.
8296 + *
8297 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8298 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8299 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8300 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8301 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8302 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8303 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8304 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8305 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8306 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8307 + *
8308 + * You should have received a copy of the GNU General Public License along
8309 + * with this program; if not, write to the Free Software Foundation, Inc.,
8310 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8311 + *
8312 + *
8313 + **************************************************************************
8314 + * May 2004 rkt,neb.
8315 + *
8316 + * Initial Release
8317 + *
8318 + *
8319 + *
8320 + **************************************************************************
8321 + */
8322 +
8323 +#ifndef __IDT_TIM_H__
8324 +#define __IDT_TIM_H__
8325 +
8326 +enum
8327 +{
8328 + TIM0_PhysicalAddress = 0x18028000,
8329 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
8330 +
8331 + TIM0_VirtualAddress = 0xb8028000,
8332 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
8333 +} ;
8334 +
8335 +enum
8336 +{
8337 + TIM_Count = 3,
8338 +} ;
8339 +
8340 +struct TIM_CNTR_s
8341 +{
8342 + u32 count ;
8343 + u32 compare ;
8344 + u32 ctc ; //use CTC_
8345 +} ;
8346 +
8347 +typedef struct TIM_s
8348 +{
8349 + struct TIM_CNTR_s tim [TIM_Count] ;
8350 + u32 rcount ; //use RCOUNT_
8351 + u32 rcompare ; //use RCOMPARE_
8352 + u32 rtc ; //use RTC_
8353 +} volatile * TIM_t ;
8354 +
8355 +enum
8356 +{
8357 + CTC_en_b = 0,
8358 + CTC_en_m = 0x00000001,
8359 + CTC_to_b = 1,
8360 + CTC_to_m = 0x00000002,
8361 +
8362 + RCOUNT_count_b = 0,
8363 + RCOUNT_count_m = 0x0000ffff,
8364 + RCOMPARE_compare_b = 0,
8365 + RCOMPARE_compare_m = 0x0000ffff,
8366 + RTC_ce_b = 0,
8367 + RTC_ce_m = 0x00000001,
8368 + RTC_to_b = 1,
8369 + RTC_to_m = 0x00000002,
8370 + RTC_rqe_b = 2,
8371 + RTC_rqe_m = 0x00000004,
8372 +
8373 +} ;
8374 +#endif // __IDT_TIM_H__
8375 +
8376 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_uart.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h
8377 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_uart.h 1970-01-01 01:00:00.000000000 +0100
8378 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h 2006-03-20 14:25:10.000000000 +0100
8379 @@ -0,0 +1,189 @@
8380 +/**************************************************************************
8381 + *
8382 + * BRIEF MODULE DESCRIPTION
8383 + * UART register definitions
8384 + *
8385 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8386 + *
8387 + * This program is free software; you can redistribute it and/or modify it
8388 + * under the terms of the GNU General Public License as published by the
8389 + * Free Software Foundation; either version 2 of the License, or (at your
8390 + * option) any later version.
8391 + *
8392 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8393 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8394 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8395 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8396 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8397 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8398 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8399 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8400 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8401 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8402 + *
8403 + * You should have received a copy of the GNU General Public License along
8404 + * with this program; if not, write to the Free Software Foundation, Inc.,
8405 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8406 + *
8407 + *
8408 + **************************************************************************
8409 + * May 2004 rkt, neb.
8410 + *
8411 + * Initial Release
8412 + *
8413 + *
8414 + *
8415 + **************************************************************************
8416 + */
8417 +
8418 +#ifndef __IDT_UART_H__
8419 +#define __IDT_UART_H__
8420 +
8421 +enum
8422 +{
8423 + UART0_PhysicalAddress = 0x1c000000,
8424 + UART_PhysicalAddress = UART0_PhysicalAddress, // Default
8425 +
8426 + UART0_VirtualAddress = 0xbc000000,
8427 + UART_VirtualAddress = UART0_VirtualAddress, // Default
8428 +} ;
8429 +
8430 +/*
8431 + * Register definitions are in bytes so we can handle endian problems.
8432 + */
8433 +
8434 +typedef struct UART_s
8435 +{
8436 + union
8437 + {
8438 + u32 const uartrb ; // 0x00 - DLAB=0, read.
8439 + u32 uartth ; // 0x00 - DLAB=0, write.
8440 + u32 uartdll ; // 0x00 - DLAB=1, read/write.
8441 + } ;
8442 +
8443 + union
8444 + {
8445 + u32 uartie ; // 0x04 - DLAB=0, read/write.
8446 + u32 uartdlh ; // 0x04 - DLAB=1, read/write.
8447 + } ;
8448 + union
8449 + {
8450 + u32 const uartii ; // 0x08 - DLAB=0, read.
8451 + u32 uartfc ; // 0x08 - DLAB=0, write.
8452 + } ;
8453 +
8454 + u32 uartlc ; // 0x0c
8455 + u32 uartmc ; // 0x10
8456 + u32 uartls ; // 0x14
8457 + u32 uartms ; // 0x18
8458 + u32 uarts ; // 0x1c
8459 +} volatile *UART_t ;
8460 +
8461 +// Reset registers.
8462 +typedef u32 volatile *UARTRR_t ;
8463 +
8464 +enum
8465 +{
8466 + UARTIE_rda_b = 0,
8467 + UARTIE_rda_m = 0x00000001,
8468 + UARTIE_the_b = 1,
8469 + UARTIE_the_m = 0x00000002,
8470 + UARTIE_rls_b = 2,
8471 + UARTIE_rls_m = 0x00000004,
8472 + UARTIE_ems_b = 3,
8473 + UARTIE_ems_m = 0x00000008,
8474 +
8475 + UARTII_pi_b = 0,
8476 + UARTII_pi_m = 0x00000001,
8477 + UARTII_iid_b = 1,
8478 + UARTII_iid_m = 0x0000000e,
8479 + UARTII_iid_ms_v = 0, // Modem stat-CTS,DSR,RI or DCD.
8480 + UARTII_iid_thre_v = 1, // Trans. Holding Reg. empty.
8481 + UARTII_iid_rda_v = 2, // Receive data available
8482 + UARTII_iid_rls_v = 3, // Overrun, parity, etc, error.
8483 + UARTII_iid_res4_v = 4, // reserved.
8484 + UARTII_iid_res5_v = 5, // reserved.
8485 + UARTII_iid_cto_v = 6, // Character timeout.
8486 + UARTII_iid_res7_v = 7, // reserved.
8487 +
8488 + UARTFC_en_b = 0,
8489 + UARTFC_en_m = 0x00000001,
8490 + UARTFC_rr_b = 1,
8491 + UARTFC_rr_m = 0x00000002,
8492 + UARTFC_tr_b = 2,
8493 + UARTFC_tr_m = 0x00000004,
8494 + UARTFC_dms_b = 3,
8495 + UARTFC_dms_m = 0x00000008,
8496 + UARTFC_rt_b = 6,
8497 + UARTFC_rt_m = 0x000000c0,
8498 + UARTFC_rt_1Byte_v = 0,
8499 + UARTFC_rt_4Byte_v = 1,
8500 + UARTFC_rt_8Byte_v = 2,
8501 + UARTFC_rt_14Byte_v = 3,
8502 +
8503 + UARTLC_wls_b = 0,
8504 + UARTLC_wls_m = 0x00000003,
8505 + UARTLC_wls_5Bits_v = 0,
8506 + UARTLC_wls_6Bits_v = 1,
8507 + UARTLC_wls_7Bits_v = 2,
8508 + UARTLC_wls_8Bits_v = 3,
8509 + UARTLC_stb_b = 2,
8510 + UARTLC_stb_m = 0x00000004,
8511 + UARTLC_pen_b = 3,
8512 + UARTLC_pen_m = 0x00000008,
8513 + UARTLC_eps_b = 4,
8514 + UARTLC_eps_m = 0x00000010,
8515 + UARTLC_sp_b = 5,
8516 + UARTLC_sp_m = 0x00000020,
8517 + UARTLC_sb_b = 6,
8518 + UARTLC_sb_m = 0x00000040,
8519 + UARTLC_dlab_b = 7,
8520 + UARTLC_dlab_m = 0x00000080,
8521 +
8522 + UARTMC_dtr_b = 0,
8523 + UARTMC_dtr_m = 0x00000001,
8524 + UARTMC_rts_b = 1,
8525 + UARTMC_rts_m = 0x00000002,
8526 + UARTMC_o1_b = 2,
8527 + UARTMC_o1_m = 0x00000004,
8528 + UARTMC_o2_b = 3,
8529 + UARTMC_o2_m = 0x00000008,
8530 + UARTMC_lp_b = 4,
8531 + UARTMC_lp_m = 0x00000010,
8532 +
8533 + UARTLS_dr_b = 0,
8534 + UARTLS_dr_m = 0x00000001,
8535 + UARTLS_oe_b = 1,
8536 + UARTLS_oe_m = 0x00000002,
8537 + UARTLS_pe_b = 2,
8538 + UARTLS_pe_m = 0x00000004,
8539 + UARTLS_fe_b = 3,
8540 + UARTLS_fe_m = 0x00000008,
8541 + UARTLS_bi_b = 4,
8542 + UARTLS_bi_m = 0x00000010,
8543 + UARTLS_thr_b = 5,
8544 + UARTLS_thr_m = 0x00000020,
8545 + UARTLS_te_b = 6,
8546 + UARTLS_te_m = 0x00000040,
8547 + UARTLS_rfe_b = 7,
8548 + UARTLS_rfe_m = 0x00000080,
8549 +
8550 + UARTMS_dcts_b = 0,
8551 + UARTMS_dcts_m = 0x00000001,
8552 + UARTMS_ddsr_b = 1,
8553 + UARTMS_ddsr_m = 0x00000002,
8554 + UARTMS_teri_b = 2,
8555 + UARTMS_teri_m = 0x00000004,
8556 + UARTMS_ddcd_b = 3,
8557 + UARTMS_ddcd_m = 0x00000008,
8558 + UARTMS_cts_b = 4,
8559 + UARTMS_cts_m = 0x00000010,
8560 + UARTMS_dsr_b = 5,
8561 + UARTMS_dsr_m = 0x00000020,
8562 + UARTMS_ri_b = 6,
8563 + UARTMS_ri_m = 0x00000040,
8564 + UARTMS_dcd_b = 7,
8565 + UARTMS_dcd_m = 0x00000080,
8566 +} ;
8567 +
8568 +#endif // __IDT_UART_H__
8569 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_dma.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h
8570 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 1970-01-01 01:00:00.000000000 +0100
8571 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 2006-03-20 14:25:10.000000000 +0100
8572 @@ -0,0 +1,231 @@
8573 +/**************************************************************************
8574 + *
8575 + * BRIEF MODULE DESCRIPTION
8576 + * Register definitions for IDT RC32438 DMA.
8577 + *
8578 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8579 + *
8580 + * This program is free software; you can redistribute it and/or modify it
8581 + * under the terms of the GNU General Public License as published by the
8582 + * Free Software Foundation; either version 2 of the License, or (at your
8583 + * option) any later version.
8584 + *
8585 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8586 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8587 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8588 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8589 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8590 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8591 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8592 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8593 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8594 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8595 + *
8596 + * You should have received a copy of the GNU General Public License along
8597 + * with this program; if not, write to the Free Software Foundation, Inc.,
8598 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8599 + *
8600 + *
8601 + **************************************************************************
8602 + * May 2004 P. Sadik.
8603 + *
8604 + * Initial Release
8605 + *
8606 + *
8607 + *
8608 + **************************************************************************
8609 + */
8610 +#ifndef __IDT_RC32438_DMA_H__
8611 +#define __IDT_RC32438_DMA_H__
8612 +enum
8613 +{
8614 + DMA0_PhysicalAddress = 0x18040000,
8615 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
8616 +
8617 + DMA0_VirtualAddress = 0xb8040000,
8618 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
8619 +} ;
8620 +
8621 +/*
8622 + * DMA descriptor (in physical memory).
8623 + */
8624 +
8625 +typedef struct DMAD_s
8626 +{
8627 + u32 control ; // Control. use DMAD_*
8628 + u32 ca ; // Current Address.
8629 + u32 devcs ; // Device control and status.
8630 + u32 link ; // Next descriptor in chain.
8631 +} volatile *DMAD_t ;
8632 +
8633 +enum
8634 +{
8635 + DMAD_size = sizeof (struct DMAD_s),
8636 + DMAD_count_b = 0, // in DMAD_t -> control
8637 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
8638 + DMAD_ds_b = 20, // in DMAD_t -> control
8639 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
8640 + DMAD_ds_extToMem0_v = 0,
8641 + DMAD_ds_memToExt0_v = 1,
8642 + DMAD_ds_extToMem1_v = 0,
8643 + DMAD_ds_memToExt1_v = 1,
8644 + DMAD_ds_ethRcv0_v = 0,
8645 + DMAD_ds_ethXmt0_v = 0,
8646 + DMAD_ds_ethRcv1_v = 0,
8647 + DMAD_ds_ethXmt2_v = 0,
8648 + DMAD_ds_memToFifo_v = 0,
8649 + DMAD_ds_fifoToMem_v = 0,
8650 + DMAD_ds_rng_de_v = 1,//randomNumberGenerator on LC/DE
8651 + DMAD_ds_pciToMem_v = 0,
8652 + DMAD_ds_memToPci_v = 0,
8653 + DMAD_ds_securityInput_v = 0,
8654 + DMAD_ds_securityOutput_v = 0,
8655 + DMAD_ds_rng_se_v = 0,//randomNumberGenerator on SE
8656 +
8657 + DMAD_devcmd_b = 22, // in DMAD_t -> control
8658 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
8659 + DMAD_devcmd_byte_v = 0, //memory-to-memory
8660 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
8661 + DMAD_devcmd_word_v = 2, //memory-to-memory
8662 + DMAD_devcmd_2words_v = 3, //memory-to-memory
8663 + DMAD_devcmd_4words_v = 4, //memory-to-memory
8664 + DMAD_devcmd_6words_v = 5, //memory-to-memory
8665 + DMAD_devcmd_8words_v = 6, //memory-to-memory
8666 + DMAD_devcmd_16words_v = 7, //memory-to-memory
8667 + DMAD_cof_b = 25, // chain on finished
8668 + DMAD_cof_m = 0x02000000, //
8669 + DMAD_cod_b = 26, // chain on done
8670 + DMAD_cod_m = 0x04000000, //
8671 + DMAD_iof_b = 27, // interrupt on finished
8672 + DMAD_iof_m = 0x08000000, //
8673 + DMAD_iod_b = 28, // interrupt on done
8674 + DMAD_iod_m = 0x10000000, //
8675 + DMAD_t_b = 29, // terminated
8676 + DMAD_t_m = 0x20000000, //
8677 + DMAD_d_b = 30, // done
8678 + DMAD_d_m = 0x40000000, //
8679 + DMAD_f_b = 31, // finished
8680 + DMAD_f_m = 0x80000000, //
8681 +} ;
8682 +
8683 +/*
8684 + * DMA register (within Internal Register Map).
8685 + */
8686 +
8687 +struct DMA_Chan_s
8688 +{
8689 + u32 dmac ; // Control.
8690 + u32 dmas ; // Status.
8691 + u32 dmasm ; // Mask.
8692 + u32 dmadptr ; // Descriptor pointer.
8693 + u32 dmandptr ; // Next descriptor pointer.
8694 +};
8695 +
8696 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
8697 +
8698 +//DMA_Channels use DMACH_count instead
8699 +
8700 +enum
8701 +{
8702 + DMAC_run_b = 0, //
8703 + DMAC_run_m = 0x00000001, //
8704 + DMAC_dm_b = 1, // done mask
8705 + DMAC_dm_m = 0x00000002, //
8706 + DMAC_mode_b = 2, //
8707 + DMAC_mode_m = 0x0000000c, //
8708 + DMAC_mode_auto_v = 0,
8709 + DMAC_mode_burst_v = 1,
8710 + DMAC_mode_transfer_v = 2, //usually used
8711 + DMAC_mode_reserved_v = 3,
8712 + DMAC_a_b = 4, //
8713 + DMAC_a_m = 0x00000010, //
8714 +
8715 + DMAS_f_b = 0, // finished (sticky)
8716 + DMAS_f_m = 0x00000001, //
8717 + DMAS_d_b = 1, // done (sticky)
8718 + DMAS_d_m = 0x00000002, //
8719 + DMAS_c_b = 2, // chain (sticky)
8720 + DMAS_c_m = 0x00000004, //
8721 + DMAS_e_b = 3, // error (sticky)
8722 + DMAS_e_m = 0x00000008, //
8723 + DMAS_h_b = 4, // halt (sticky)
8724 + DMAS_h_m = 0x00000010, //
8725 +
8726 + DMASM_f_b = 0, // finished (1=mask)
8727 + DMASM_f_m = 0x00000001, //
8728 + DMASM_d_b = 1, // done (1=mask)
8729 + DMASM_d_m = 0x00000002, //
8730 + DMASM_c_b = 2, // chain (1=mask)
8731 + DMASM_c_m = 0x00000004, //
8732 + DMASM_e_b = 3, // error (1=mask)
8733 + DMASM_e_m = 0x00000008, //
8734 + DMASM_h_b = 4, // halt (1=mask)
8735 + DMASM_h_m = 0x00000010, //
8736 +} ;
8737 +
8738 +/*
8739 + * DMA channel definitions
8740 + */
8741 +
8742 +enum
8743 +{
8744 + DMACH_extToMem0 = 0,
8745 + DMACH_memToExt0 = 0,
8746 + DMACH_extToMem1 = 1,
8747 + DMACH_memToExt1 = 1,
8748 + DMACH_ethRcv0 = 2,
8749 + DMACH_ethXmt0 = 3,
8750 + DMACH_ethRcv1 = 4,
8751 + DMACH_ethXmt2 = 5,
8752 + DMACH_memToFifo = 6,
8753 + DMACH_fifoToMem = 7,
8754 + DMACH_rng_de = 7,//randomNumberGenerator on LC/DE
8755 + DMACH_pciToMem = 8,
8756 + DMACH_memToPci = 9,
8757 + DMACH_securityInput = 10,
8758 + DMACH_securityOutput = 11,
8759 + DMACH_rng_se = 12, //randomNumberGenerator on SE
8760 +
8761 + DMACH_count //must be last
8762 +};
8763 +
8764 +
8765 +typedef struct DMAC_s
8766 +{
8767 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
8768 +} volatile *DMA_t ;
8769 +
8770 +
8771 +/*
8772 + * External DMA parameters
8773 +*/
8774 +
8775 +enum
8776 +{
8777 + DMADEVCMD_ts_b = 0, // ts field in devcmd
8778 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
8779 + DMADEVCMD_ts_byte_v = 0,
8780 + DMADEVCMD_ts_halfword_v = 1,
8781 + DMADEVCMD_ts_word_v = 2,
8782 + DMADEVCMD_ts_2word_v = 3,
8783 + DMADEVCMD_ts_4word_v = 4,
8784 + DMADEVCMD_ts_6word_v = 5,
8785 + DMADEVCMD_ts_8word_v = 6,
8786 + DMADEVCMD_ts_16word_v = 7
8787 +};
8788 +
8789 +
8790 +#if 1 // aws - Compatibility.
8791 +# define EXTDMA_ts_b DMADEVCMD_ts_b
8792 +# define EXTDMA_ts_m DMADEVCMD_ts_m
8793 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
8794 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
8795 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
8796 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
8797 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
8798 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
8799 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
8800 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
8801 +#endif // aws - Compatibility.
8802 +
8803 +#endif //__IDT_RC32438_DMA_H__
8804 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h
8805 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h 1970-01-01 01:00:00.000000000 +0100
8806 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h 2006-03-20 14:25:10.000000000 +0100
8807 @@ -0,0 +1,82 @@
8808 +/**************************************************************************
8809 + *
8810 + * BRIEF MODULE DESCRIPTION
8811 + * DMA operations for IDT RC32438.
8812 + *
8813 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8814 + *
8815 + * This program is free software; you can redistribute it and/or modify it
8816 + * under the terms of the GNU General Public License as published by the
8817 + * Free Software Foundation; either version 2 of the License, or (at your
8818 + * option) any later version.
8819 + *
8820 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8821 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8822 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8823 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8824 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8825 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8826 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8827 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8828 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8829 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8830 + *
8831 + * You should have received a copy of the GNU General Public License along
8832 + * with this program; if not, write to the Free Software Foundation, Inc.,
8833 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8834 + *
8835 + *
8836 + **************************************************************************
8837 + * May 2004 P. Sadik.
8838 + *
8839 + * Initial Release
8840 + *
8841 + *
8842 + *
8843 + **************************************************************************
8844 + */
8845 +
8846 +#ifndef __IDT_RC32438_DMA_V_H__
8847 +#define __IDT_RC32438_DMA_V_H__
8848 +#include <asm/idt-boards/rc32438/rc32438_dma.h>
8849 +
8850 +#define DMA_CHAN_OFFSET 0x14
8851 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
8852 +#define DMA_COUNT(count) \
8853 + ((count) & DMAD_count_m)
8854 +
8855 +#define DMA_HALT_TIMEOUT 500
8856 +
8857 +
8858 +static inline int rc32438_halt_dma(DMA_Chan_t ch)
8859 +{
8860 + int timeout=1;
8861 + if (rc32438_readl(&ch->dmac) & DMAC_run_m) {
8862 + rc32438_writel(0, &ch->dmac);
8863 +
8864 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
8865 + if (rc32438_readl(&ch->dmas) & DMAS_h_m) {
8866 + rc32438_writel(0, &ch->dmas);
8867 + break;
8868 + }
8869 + }
8870 +
8871 + }
8872 +
8873 + return timeout ? 0 : 1;
8874 +}
8875 +
8876 +
8877 +
8878 +
8879 +static inline void rc32438_start_dma(DMA_Chan_t ch, u32 dma_addr)
8880 +{
8881 + rc32438_writel(0, &ch->dmandptr);
8882 + rc32438_writel(dma_addr, &ch->dmadptr);
8883 +}
8884 +
8885 +static inline void rc32438_chain_dma(DMA_Chan_t ch, u32 dma_addr)
8886 +{
8887 + rc32438_writel(dma_addr, &ch->dmandptr);
8888 +}
8889 +#endif //__IDT_RC32438_DMA_V_H__
8890 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_eth.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h
8891 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 1970-01-01 01:00:00.000000000 +0100
8892 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 2006-03-20 14:25:10.000000000 +0100
8893 @@ -0,0 +1,328 @@
8894 +/**************************************************************************
8895 + *
8896 + * BRIEF MODULE DESCRIPTION
8897 + * Definitions for IDT EB438 ethernet
8898 + *
8899 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8900 + *
8901 + * This program is free software; you can redistribute it and/or modify it
8902 + * under the terms of the GNU General Public License as published by the
8903 + * Free Software Foundation; either version 2 of the License, or (at your
8904 + * option) any later version.
8905 + *
8906 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8907 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8908 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8909 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8910 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8911 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8912 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8913 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8914 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8915 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8916 + *
8917 + * You should have received a copy of the GNU General Public License along
8918 + * with this program; if not, write to the Free Software Foundation, Inc.,
8919 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8920 + *
8921 + *
8922 + **************************************************************************
8923 + * May 2004 P. Sadik.
8924 + *
8925 + * Initial Release
8926 + *
8927 + *
8928 + *
8929 + **************************************************************************
8930 + */
8931 +
8932 +#ifndef __IDT_RC32438_ETH_H__
8933 +#define __IDT_RC32438_ETH_H__
8934 +enum
8935 +{
8936 + ETH0_PhysicalAddress = 0x18058000,
8937 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
8938 +
8939 + ETH0_VirtualAddress = 0xb8058000,
8940 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
8941 + ETH1_PhysicalAddress = 0x18060000,
8942 + ETH1_VirtualAddress = 0xb8060000, // Default
8943 +} ;
8944 +
8945 +typedef struct
8946 +{
8947 + u32 ethintfc ;
8948 + u32 ethfifott ;
8949 + u32 etharc ;
8950 + u32 ethhash0 ;
8951 + u32 ethhash1 ;
8952 + u32 ethu0 [4] ; // Reserved.
8953 + u32 ethpfs ;
8954 + u32 ethmcp ;
8955 + u32 eth_u1 [10] ; // Reserved.
8956 + u32 ethspare ;
8957 + u32 eth_u2 [42] ; // Reserved.
8958 + u32 ethsal0 ;
8959 + u32 ethsah0 ;
8960 + u32 ethsal1 ;
8961 + u32 ethsah1 ;
8962 + u32 ethsal2 ;
8963 + u32 ethsah2 ;
8964 + u32 ethsal3 ;
8965 + u32 ethsah3 ;
8966 + u32 ethrbc ;
8967 + u32 ethrpc ;
8968 + u32 ethrupc ;
8969 + u32 ethrfc ;
8970 + u32 ethtbc ;
8971 + u32 ethgpf ;
8972 + u32 eth_u9 [50] ; // Reserved.
8973 + u32 ethmac1 ;
8974 + u32 ethmac2 ;
8975 + u32 ethipgt ;
8976 + u32 ethipgr ;
8977 + u32 ethclrt ;
8978 + u32 ethmaxf ;
8979 + u32 eth_u10 ; // Reserved.
8980 + u32 ethmtest ;
8981 + u32 miimcfg ;
8982 + u32 miimcmd ;
8983 + u32 miimaddr ;
8984 + u32 miimwtd ;
8985 + u32 miimrdd ;
8986 + u32 miimind ;
8987 + u32 eth_u11 ; // Reserved.
8988 + u32 eth_u12 ; // Reserved.
8989 + u32 ethcfsa0 ;
8990 + u32 ethcfsa1 ;
8991 + u32 ethcfsa2 ;
8992 +} volatile *ETH_t;
8993 +
8994 +enum
8995 +{
8996 + ETHINTFC_en_b = 0,
8997 + ETHINTFC_en_m = 0x00000001,
8998 + ETHINTFC_its_b = 1,
8999 + ETHINTFC_its_m = 0x00000002,
9000 + ETHINTFC_rip_b = 2,
9001 + ETHINTFC_rip_m = 0x00000004,
9002 + ETHINTFC_jam_b = 3,
9003 + ETHINTFC_jam_m = 0x00000008,
9004 + ETHINTFC_ovr_b = 4,
9005 + ETHINTFC_ovr_m = 0x00000010,
9006 + ETHINTFC_und_b = 5,
9007 + ETHINTFC_und_m = 0x00000020,
9008 +
9009 + ETHFIFOTT_tth_b = 0,
9010 + ETHFIFOTT_tth_m = 0x0000007f,
9011 +
9012 + ETHARC_pro_b = 0,
9013 + ETHARC_pro_m = 0x00000001,
9014 + ETHARC_am_b = 1,
9015 + ETHARC_am_m = 0x00000002,
9016 + ETHARC_afm_b = 2,
9017 + ETHARC_afm_m = 0x00000004,
9018 + ETHARC_ab_b = 3,
9019 + ETHARC_ab_m = 0x00000008,
9020 +
9021 + ETHSAL_byte5_b = 0,
9022 + ETHSAL_byte5_m = 0x000000ff,
9023 + ETHSAL_byte4_b = 8,
9024 + ETHSAL_byte4_m = 0x0000ff00,
9025 + ETHSAL_byte3_b = 16,
9026 + ETHSAL_byte3_m = 0x00ff0000,
9027 + ETHSAL_byte2_b = 24,
9028 + ETHSAL_byte2_m = 0xff000000,
9029 +
9030 + ETHSAH_byte1_b = 0,
9031 + ETHSAH_byte1_m = 0x000000ff,
9032 + ETHSAH_byte0_b = 8,
9033 + ETHSAH_byte0_m = 0x0000ff00,
9034 +
9035 + ETHGPF_ptv_b = 0,
9036 + ETHGPF_ptv_m = 0x0000ffff,
9037 +
9038 + ETHPFS_pfd_b = 0,
9039 + ETHPFS_pfd_m = 0x00000001,
9040 +
9041 + ETHCFSA0_cfsa4_b = 0,
9042 + ETHCFSA0_cfsa4_m = 0x000000ff,
9043 + ETHCFSA0_cfsa5_b = 8,
9044 + ETHCFSA0_cfsa5_m = 0x0000ff00,
9045 +
9046 + ETHCFSA1_cfsa2_b = 0,
9047 + ETHCFSA1_cfsa2_m = 0x000000ff,
9048 + ETHCFSA1_cfsa3_b = 8,
9049 + ETHCFSA1_cfsa3_m = 0x0000ff00,
9050 +
9051 + ETHCFSA2_cfsa0_b = 0,
9052 + ETHCFSA2_cfsa0_m = 0x000000ff,
9053 + ETHCFSA2_cfsa1_b = 8,
9054 + ETHCFSA2_cfsa1_m = 0x0000ff00,
9055 +
9056 + ETHMAC1_re_b = 0,
9057 + ETHMAC1_re_m = 0x00000001,
9058 + ETHMAC1_paf_b = 1,
9059 + ETHMAC1_paf_m = 0x00000002,
9060 + ETHMAC1_rfc_b = 2,
9061 + ETHMAC1_rfc_m = 0x00000004,
9062 + ETHMAC1_tfc_b = 3,
9063 + ETHMAC1_tfc_m = 0x00000008,
9064 + ETHMAC1_lb_b = 4,
9065 + ETHMAC1_lb_m = 0x00000010,
9066 + ETHMAC1_mr_b = 31,
9067 + ETHMAC1_mr_m = 0x80000000,
9068 +
9069 + ETHMAC2_fd_b = 0,
9070 + ETHMAC2_fd_m = 0x00000001,
9071 + ETHMAC2_flc_b = 1,
9072 + ETHMAC2_flc_m = 0x00000002,
9073 + ETHMAC2_hfe_b = 2,
9074 + ETHMAC2_hfe_m = 0x00000004,
9075 + ETHMAC2_dc_b = 3,
9076 + ETHMAC2_dc_m = 0x00000008,
9077 + ETHMAC2_cen_b = 4,
9078 + ETHMAC2_cen_m = 0x00000010,
9079 + ETHMAC2_pe_b = 5,
9080 + ETHMAC2_pe_m = 0x00000020,
9081 + ETHMAC2_vpe_b = 6,
9082 + ETHMAC2_vpe_m = 0x00000040,
9083 + ETHMAC2_ape_b = 7,
9084 + ETHMAC2_ape_m = 0x00000080,
9085 + ETHMAC2_ppe_b = 8,
9086 + ETHMAC2_ppe_m = 0x00000100,
9087 + ETHMAC2_lpe_b = 9,
9088 + ETHMAC2_lpe_m = 0x00000200,
9089 + ETHMAC2_nb_b = 12,
9090 + ETHMAC2_nb_m = 0x00001000,
9091 + ETHMAC2_bp_b = 13,
9092 + ETHMAC2_bp_m = 0x00002000,
9093 + ETHMAC2_ed_b = 14,
9094 + ETHMAC2_ed_m = 0x00004000,
9095 +
9096 + ETHIPGT_ipgt_b = 0,
9097 + ETHIPGT_ipgt_m = 0x0000007f,
9098 +
9099 + ETHIPGR_ipgr2_b = 0,
9100 + ETHIPGR_ipgr2_m = 0x0000007f,
9101 + ETHIPGR_ipgr1_b = 8,
9102 + ETHIPGR_ipgr1_m = 0x00007f00,
9103 +
9104 + ETHCLRT_maxret_b = 0,
9105 + ETHCLRT_maxret_m = 0x0000000f,
9106 + ETHCLRT_colwin_b = 8,
9107 + ETHCLRT_colwin_m = 0x00003f00,
9108 +
9109 + ETHMAXF_maxf_b = 0,
9110 + ETHMAXF_maxf_m = 0x0000ffff,
9111 +
9112 + ETHMTEST_tb_b = 2,
9113 + ETHMTEST_tb_m = 0x00000004,
9114 +
9115 + ETHMCP_div_b = 0,
9116 + ETHMCP_div_m = 0x000000ff,
9117 +
9118 + MIIMCFG_rsv_b = 0,
9119 + MIIMCFG_rsv_m = 0x0000000c,
9120 +
9121 + MIIMCMD_rd_b = 0,
9122 + MIIMCMD_rd_m = 0x00000001,
9123 + MIIMCMD_scn_b = 1,
9124 + MIIMCMD_scn_m = 0x00000002,
9125 +
9126 + MIIMADDR_regaddr_b = 0,
9127 + MIIMADDR_regaddr_m = 0x0000001f,
9128 + MIIMADDR_phyaddr_b = 8,
9129 + MIIMADDR_phyaddr_m = 0x00001f00,
9130 +
9131 + MIIMWTD_wdata_b = 0,
9132 + MIIMWTD_wdata_m = 0x0000ffff,
9133 +
9134 + MIIMRDD_rdata_b = 0,
9135 + MIIMRDD_rdata_m = 0x0000ffff,
9136 +
9137 + MIIMIND_bsy_b = 0,
9138 + MIIMIND_bsy_m = 0x00000001,
9139 + MIIMIND_scn_b = 1,
9140 + MIIMIND_scn_m = 0x00000002,
9141 + MIIMIND_nv_b = 2,
9142 + MIIMIND_nv_m = 0x00000004,
9143 +
9144 +} ;
9145 +
9146 +/*
9147 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
9148 + */
9149 +enum
9150 +{
9151 + ETHRX_fd_b = 0,
9152 + ETHRX_fd_m = 0x00000001,
9153 + ETHRX_ld_b = 1,
9154 + ETHRX_ld_m = 0x00000002,
9155 + ETHRX_rok_b = 2,
9156 + ETHRX_rok_m = 0x00000004,
9157 + ETHRX_fm_b = 3,
9158 + ETHRX_fm_m = 0x00000008,
9159 + ETHRX_mp_b = 4,
9160 + ETHRX_mp_m = 0x00000010,
9161 + ETHRX_bp_b = 5,
9162 + ETHRX_bp_m = 0x00000020,
9163 + ETHRX_vlt_b = 6,
9164 + ETHRX_vlt_m = 0x00000040,
9165 + ETHRX_cf_b = 7,
9166 + ETHRX_cf_m = 0x00000080,
9167 + ETHRX_ovr_b = 8,
9168 + ETHRX_ovr_m = 0x00000100,
9169 + ETHRX_crc_b = 9,
9170 + ETHRX_crc_m = 0x00000200,
9171 + ETHRX_cv_b = 10,
9172 + ETHRX_cv_m = 0x00000400,
9173 + ETHRX_db_b = 11,
9174 + ETHRX_db_m = 0x00000800,
9175 + ETHRX_le_b = 12,
9176 + ETHRX_le_m = 0x00001000,
9177 + ETHRX_lor_b = 13,
9178 + ETHRX_lor_m = 0x00002000,
9179 + ETHRX_ces_b = 14,
9180 + ETHRX_ces_m = 0x00004000,
9181 + ETHRX_length_b = 16,
9182 + ETHRX_length_m = 0xffff0000,
9183 +
9184 + ETHTX_fd_b = 0,
9185 + ETHTX_fd_m = 0x00000001,
9186 + ETHTX_ld_b = 1,
9187 + ETHTX_ld_m = 0x00000002,
9188 + ETHTX_oen_b = 2,
9189 + ETHTX_oen_m = 0x00000004,
9190 + ETHTX_pen_b = 3,
9191 + ETHTX_pen_m = 0x00000008,
9192 + ETHTX_cen_b = 4,
9193 + ETHTX_cen_m = 0x00000010,
9194 + ETHTX_hen_b = 5,
9195 + ETHTX_hen_m = 0x00000020,
9196 + ETHTX_tok_b = 6,
9197 + ETHTX_tok_m = 0x00000040,
9198 + ETHTX_mp_b = 7,
9199 + ETHTX_mp_m = 0x00000080,
9200 + ETHTX_bp_b = 8,
9201 + ETHTX_bp_m = 0x00000100,
9202 + ETHTX_und_b = 9,
9203 + ETHTX_und_m = 0x00000200,
9204 + ETHTX_of_b = 10,
9205 + ETHTX_of_m = 0x00000400,
9206 + ETHTX_ed_b = 11,
9207 + ETHTX_ed_m = 0x00000800,
9208 + ETHTX_ec_b = 12,
9209 + ETHTX_ec_m = 0x00001000,
9210 + ETHTX_lc_b = 13,
9211 + ETHTX_lc_m = 0x00002000,
9212 + ETHTX_td_b = 14,
9213 + ETHTX_td_m = 0x00004000,
9214 + ETHTX_crc_b = 15,
9215 + ETHTX_crc_m = 0x00008000,
9216 + ETHTX_le_b = 16,
9217 + ETHTX_le_m = 0x00010000,
9218 + ETHTX_cc_b = 17,
9219 + ETHTX_cc_m = 0x001E0000,
9220 +} ;
9221 +#endif //__IDT_RC32438_ETH_H__
9222 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h
9223 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h 1970-01-01 01:00:00.000000000 +0100
9224 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h 2006-03-20 14:25:10.000000000 +0100
9225 @@ -0,0 +1,72 @@
9226 +/**************************************************************************
9227 + *
9228 + * BRIEF MODULE DESCRIPTION
9229 + * macros for IDT EB438 ethernet
9230 + *
9231 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9232 + *
9233 + * This program is free software; you can redistribute it and/or modify it
9234 + * under the terms of the GNU General Public License as published by the
9235 + * Free Software Foundation; either version 2 of the License, or (at your
9236 + * option) any later version.
9237 + *
9238 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9239 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9240 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9241 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9242 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9243 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9244 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9245 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9246 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9247 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9248 + *
9249 + * You should have received a copy of the GNU General Public License along
9250 + * with this program; if not, write to the Free Software Foundation, Inc.,
9251 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9252 + *
9253 + *
9254 + **************************************************************************
9255 + * May 2004 P. Sadik.
9256 + *
9257 + * Initial Release
9258 + *
9259 + *
9260 + *
9261 + **************************************************************************
9262 + */
9263 +
9264 +#ifndef __IDT_RC32438_ETH_V_H__
9265 +#define __IDT_RC32438_ETH_V_H__
9266 +#include <asm/idt-boards/rc32438/rc32438_eth.h>
9267 +
9268 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
9269 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
9270 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
9271 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
9272 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
9273 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
9274 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
9275 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
9276 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
9277 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
9278 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
9279 +
9280 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
9281 +
9282 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
9283 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
9284 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
9285 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
9286 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
9287 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
9288 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
9289 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
9290 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
9291 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
9292 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
9293 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
9294 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
9295 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
9296 +
9297 +#endif //__IDT_RC32438_ETH_V_H__
9298 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h
9299 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h 1970-01-01 01:00:00.000000000 +0100
9300 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h 2006-03-20 14:25:10.000000000 +0100
9301 @@ -0,0 +1,257 @@
9302 +/**************************************************************************
9303 + *
9304 + * BRIEF MODULE DESCRIPTION
9305 + * Definitions for IDT RC32438 GPIO.
9306 + *
9307 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9308 + *
9309 + * This program is free software; you can redistribute it and/or modify it
9310 + * under the terms of the GNU General Public License as published by the
9311 + * Free Software Foundation; either version 2 of the License, or (at your
9312 + * option) any later version.
9313 + *
9314 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9315 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9316 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9317 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9318 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9319 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9320 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9321 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9322 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9323 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9324 + *
9325 + * You should have received a copy of the GNU General Public License along
9326 + * with this program; if not, write to the Free Software Foundation, Inc.,
9327 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9328 + *
9329 + *
9330 + **************************************************************************
9331 + * May 2004 P. Sadik.
9332 + *
9333 + * Initial Release
9334 + *
9335 + *
9336 + *
9337 + **************************************************************************
9338 + */
9339 +#ifndef __IDT_RC32438_GPIO_H__
9340 +#define __IDT_RC32438_GPIO_H__
9341 +enum
9342 +{
9343 + GPIO0_PhysicalAddress = 0x18048000,
9344 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
9345 +
9346 + GPIO0_VirtualAddress = 0xb8048000,
9347 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
9348 +} ;
9349 +
9350 +typedef struct
9351 +{
9352 + u32 gpiofunc; /* GPIO Function Register
9353 + * gpiofunc[x]==0 bit = gpio
9354 + * func[x]==1 bit = altfunc
9355 + */
9356 + u32 gpiocfg; /* GPIO Configuration Register
9357 + * gpiocfg[x]==0 bit = input
9358 + * gpiocfg[x]==1 bit = output
9359 + */
9360 + u32 gpiod; /* GPIO Data Register
9361 + * gpiod[x] read/write gpio pinX status
9362 + */
9363 + u32 gpioilevel; /* GPIO Interrupt Status Register
9364 + * interrupt level (see gpioistat)
9365 + */
9366 + u32 gpioistat; /* Gpio Interrupt Status Register
9367 + * istat[x] = (gpiod[x] == level[x])
9368 + * cleared in ISR (STICKY bits)
9369 + */
9370 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
9371 +} volatile * GPIO_t ;
9372 +
9373 +typedef enum
9374 +{
9375 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
9376 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
9377 + GPIO_input_v = 0, // gpiocfg use pin as input.
9378 + GPIO_output_v = 1, // gpiocfg use pin as output.
9379 + GPIO_pin0_b = 0,
9380 + GPIO_pin0_m = 0x00000001,
9381 + GPIO_pin1_b = 1,
9382 + GPIO_pin1_m = 0x00000002,
9383 + GPIO_pin2_b = 2,
9384 + GPIO_pin2_m = 0x00000004,
9385 + GPIO_pin3_b = 3,
9386 + GPIO_pin3_m = 0x00000008,
9387 + GPIO_pin4_b = 4,
9388 + GPIO_pin4_m = 0x00000010,
9389 + GPIO_pin5_b = 5,
9390 + GPIO_pin5_m = 0x00000020,
9391 + GPIO_pin6_b = 6,
9392 + GPIO_pin6_m = 0x00000040,
9393 + GPIO_pin7_b = 7,
9394 + GPIO_pin7_m = 0x00000080,
9395 + GPIO_pin8_b = 8,
9396 + GPIO_pin8_m = 0x00000100,
9397 + GPIO_pin9_b = 9,
9398 + GPIO_pin9_m = 0x00000200,
9399 + GPIO_pin10_b = 10,
9400 + GPIO_pin10_m = 0x00000400,
9401 + GPIO_pin11_b = 11,
9402 + GPIO_pin11_m = 0x00000800,
9403 + GPIO_pin12_b = 12,
9404 + GPIO_pin12_m = 0x00001000,
9405 + GPIO_pin13_b = 13,
9406 + GPIO_pin13_m = 0x00002000,
9407 + GPIO_pin14_b = 14,
9408 + GPIO_pin14_m = 0x00004000,
9409 + GPIO_pin15_b = 15,
9410 + GPIO_pin15_m = 0x00008000,
9411 + GPIO_pin16_b = 16,
9412 + GPIO_pin16_m = 0x00010000,
9413 + GPIO_pin17_b = 17,
9414 + GPIO_pin17_m = 0x00020000,
9415 + GPIO_pin18_b = 18,
9416 + GPIO_pin18_m = 0x00040000,
9417 + GPIO_pin19_b = 19,
9418 + GPIO_pin19_m = 0x00080000,
9419 + GPIO_pin20_b = 20,
9420 + GPIO_pin20_m = 0x00100000,
9421 + GPIO_pin21_b = 21,
9422 + GPIO_pin21_m = 0x00200000,
9423 + GPIO_pin22_b = 22,
9424 + GPIO_pin22_m = 0x00400000,
9425 + GPIO_pin23_b = 23,
9426 + GPIO_pin23_m = 0x00800000,
9427 + GPIO_pin24_b = 24,
9428 + GPIO_pin24_m = 0x01000000,
9429 + GPIO_pin25_b = 25,
9430 + GPIO_pin25_m = 0x02000000,
9431 + GPIO_pin26_b = 26,
9432 + GPIO_pin26_m = 0x04000000,
9433 + GPIO_pin27_b = 27,
9434 + GPIO_pin27_m = 0x08000000,
9435 + GPIO_pin28_b = 28,
9436 + GPIO_pin28_m = 0x10000000,
9437 + GPIO_pin29_b = 29,
9438 + GPIO_pin29_m = 0x20000000,
9439 + GPIO_pin30_b = 30,
9440 + GPIO_pin30_m = 0x40000000,
9441 + GPIO_pin31_b = 31,
9442 + GPIO_pin31_m = 0x80000000,
9443 +
9444 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
9445 +
9446 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
9447 + GPIO_u0sout_m = GPIO_pin0_m,
9448 + GPIO_u0sout_cfg_v = GPIO_output_v,
9449 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
9450 + GPIO_u0sinp_m = GPIO_pin1_m,
9451 + GPIO_u0sinp_cfg_v = GPIO_input_v,
9452 + GPIO_u0rin_b = GPIO_pin2_b, // UART 0 ring indic.
9453 + GPIO_u0rin_m = GPIO_pin2_m,
9454 + GPIO_u0rin_cfg_v = GPIO_input_v,
9455 + GPIO_u0dcdn_b = GPIO_pin3_b, // UART 0 data carr.det.
9456 + GPIO_u0dcdn_m = GPIO_pin3_m,
9457 + GPIO_u0dcdn_cfg_v = GPIO_input_v,
9458 + GPIO_u0dtrn_b = GPIO_pin4_b, // UART 0 data term rdy.
9459 + GPIO_u0dtrn_m = GPIO_pin4_m,
9460 + GPIO_u0dtrn_cfg_v = GPIO_output_v,
9461 + GPIO_u0dsrn_b = GPIO_pin5_b, // UART 0 data set rdy.
9462 + GPIO_u0dsrn_m = GPIO_pin5_m,
9463 + GPIO_u0dsrn_cfg_v = GPIO_input_v,
9464 + GPIO_u0rtsn_b = GPIO_pin6_b, // UART 0 req. to send.
9465 + GPIO_u0rtsn_m = GPIO_pin6_m,
9466 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
9467 + GPIO_u0ctsn_b = GPIO_pin7_b, // UART 0 clear to send.
9468 + GPIO_u0ctsn_m = GPIO_pin7_m,
9469 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
9470 +
9471 + GPIO_u1sout_b = GPIO_pin8_b, // UART 1 serial out.
9472 + GPIO_u1sout_m = GPIO_pin8_m,
9473 + GPIO_u1sout_cfg_v = GPIO_output_v,
9474 + GPIO_u1sinp_b = GPIO_pin9_b, // UART 1 serial in.
9475 + GPIO_u1sinp_m = GPIO_pin9_m,
9476 + GPIO_u1sinp_cfg_v = GPIO_input_v,
9477 + GPIO_u1dtrn_b = GPIO_pin10_b, // UART 1 data term rdy.
9478 + GPIO_u1dtrn_m = GPIO_pin10_m,
9479 + GPIO_u1dtrn_cfg_v = GPIO_output_v,
9480 + GPIO_u1dsrn_b = GPIO_pin11_b, // UART 1 data set rdy.
9481 + GPIO_u1dsrn_m = GPIO_pin11_m,
9482 + GPIO_u1dsrn_cfg_v = GPIO_input_v,
9483 + GPIO_u1rtsn_b = GPIO_pin12_b, // UART 1 req. to send.
9484 + GPIO_u1rtsn_m = GPIO_pin12_m,
9485 + GPIO_u1rtsn_cfg_v = GPIO_output_v,
9486 + GPIO_u1ctsn_b = GPIO_pin13_b, // UART 1 clear to send.
9487 + GPIO_u1ctsn_m = GPIO_pin13_m,
9488 + GPIO_u1ctsn_cfg_v = GPIO_input_v,
9489 +
9490 + GPIO_dmareqn0_b = GPIO_pin14_b, // Ext. DMA 0 request
9491 + GPIO_dmareqn0_m = GPIO_pin14_m,
9492 + GPIO_dmareqn0_cfg_v = GPIO_input_v,
9493 +
9494 + GPIO_dmareqn1_b = GPIO_pin15_b, // Ext. DMA 1 request
9495 + GPIO_dmareqn1_m = GPIO_pin15_m,
9496 + GPIO_dmareqn1_cfg_v = GPIO_input_v,
9497 +
9498 + GPIO_dmadonen0_b = GPIO_pin16_b, // Ext. DMA 0 done
9499 + GPIO_dmadonen0_m = GPIO_pin16_m,
9500 + GPIO_dmadonen0_cfg_v = GPIO_input_v,
9501 +
9502 + GPIO_dmadonen1_b = GPIO_pin17_b, // Ext. DMA 1 done
9503 + GPIO_dmadonen1_m = GPIO_pin17_m,
9504 + GPIO_dmadonen1_cfg_v = GPIO_input_v,
9505 +
9506 + GPIO_dmafinn0_b = GPIO_pin18_b, // Ext. DMA 0 finished
9507 + GPIO_dmafinn0_m = GPIO_pin18_m,
9508 + GPIO_dmafinn0_cfg_v = GPIO_output_v,
9509 +
9510 + GPIO_dmafinn1_b = GPIO_pin19_b, // Ext. DMA 1 finished
9511 + GPIO_dmafinn1_m = GPIO_pin19_m,
9512 + GPIO_dmafinn1_cfg_v = GPIO_output_v,
9513 +
9514 + GPIO_maddr22_b = GPIO_pin20_b, // M&P bus bit 22.
9515 + GPIO_maddr22_m = GPIO_pin20_m,
9516 + GPIO_maddr22_cfg_v = GPIO_output_v,
9517 +
9518 + GPIO_maddr23_b = GPIO_pin21_b, // M&P bus bit 23.
9519 + GPIO_maddr23_m = GPIO_pin21_m,
9520 + GPIO_maddr23_cfg_v = GPIO_output_v,
9521 +
9522 + GPIO_maddr24_b = GPIO_pin22_b, // M&P bus bit 24.
9523 + GPIO_maddr24_m = GPIO_pin22_m,
9524 + GPIO_maddr24_cfg_v = GPIO_output_v,
9525 +
9526 + GPIO_maddr25_b = GPIO_pin23_b, // M&P bus bit 25.
9527 + GPIO_maddr25_m = GPIO_pin23_m,
9528 + GPIO_maddr25_cfg_v = GPIO_output_v,
9529 +
9530 + GPIO_afspare6_b = GPIO_pin24_b, // reserved.
9531 + GPIO_afspare6_m = GPIO_pin24_m,
9532 + GPIO_afspare6_cfg_v = GPIO_input_v,
9533 + GPIO_afspare5_b = GPIO_pin25_b, // reserved.
9534 + GPIO_afspare5_m = GPIO_pin25_m,
9535 + GPIO_afspare5_cfg_v = GPIO_input_v,
9536 + GPIO_afspare4_b = GPIO_pin26_b, // reserved.
9537 + GPIO_afspare4_m = GPIO_pin26_m,
9538 + GPIO_afspare4_cfg_v = GPIO_input_v,
9539 + GPIO_afspare3_b = GPIO_pin27_b, // reserved.
9540 + GPIO_afspare3_m = GPIO_pin27_m,
9541 + GPIO_afspare3_cfg_v = GPIO_input_v,
9542 + GPIO_afspare2_b = GPIO_pin28_b, // reserved.
9543 + GPIO_afspare2_m = GPIO_pin28_m,
9544 + GPIO_afspare2_cfg_v = GPIO_input_v,
9545 + GPIO_afspare1_b = GPIO_pin29_b, // reserved.
9546 + GPIO_afspare1_m = GPIO_pin29_m,
9547 + GPIO_afspare1_cfg_v = GPIO_input_v,
9548 +
9549 + GPIO_pcimuintn_b = GPIO_pin30_b, // PCI messaging int.
9550 + GPIO_pcimuintn_m = GPIO_pin30_m,
9551 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
9552 +
9553 + GPIO_rngclk_b = GPIO_pin31_b, // RNG external clock
9554 + GPIO_rngclk_m = GPIO_pin31_m,
9555 + GPIO_rncclk_cfg_v = GPIO_input_v,
9556 +} GPIO_DEFS_t;
9557 +
9558 +#endif //__IDT_RC32438_GPIO_H__
9559 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438.h
9560 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438.h 1970-01-01 01:00:00.000000000 +0100
9561 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438.h 2006-03-20 14:25:10.000000000 +0100
9562 @@ -0,0 +1,152 @@
9563 +/**************************************************************************
9564 + *
9565 + * BRIEF MODULE DESCRIPTION
9566 + * Definitions for IDT RC32438 CPU.
9567 + *
9568 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9569 + *
9570 + * This program is free software; you can redistribute it and/or modify it
9571 + * under the terms of the GNU General Public License as published by the
9572 + * Free Software Foundation; either version 2 of the License, or (at your
9573 + * option) any later version.
9574 + *
9575 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9576 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9577 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9578 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9579 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9580 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9581 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9582 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9583 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9584 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9585 + *
9586 + * You should have received a copy of the GNU General Public License along
9587 + * with this program; if not, write to the Free Software Foundation, Inc.,
9588 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9589 + *
9590 + *
9591 + **************************************************************************
9592 + * May 2004 P. Sadik.
9593 + *
9594 + * Initial Release
9595 + *
9596 + *
9597 + *
9598 + **************************************************************************
9599 + */
9600 +
9601 +#ifndef __IDT_RC32438_H__
9602 +#define __IDT_RC32438_H__
9603 +#include <linux/config.h>
9604 +#include <linux/delay.h>
9605 +#include <asm/io.h>
9606 +#include <asm/idt-boards/rc32438/rc32438_timer.h>
9607 +
9608 +#define RC32438_REG_BASE 0x18000000
9609 +
9610 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
9611 +#define idttimer ((volatile TIM_t) TIM0_VirtualAddress)
9612 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
9613 +
9614 +#define IDT_CLOCK_MULT 2
9615 +#define MIPS_CPU_TIMER_IRQ 7
9616 +/* Interrupt Controller */
9617 +#define IC_GROUP0_PEND (RC32438_REG_BASE + 0x38000)
9618 +#define IC_GROUP0_MASK (RC32438_REG_BASE + 0x38008)
9619 +#define IC_GROUP_OFFSET 0x0C
9620 +#define RTC_BASE 0xAC0801FF0
9621 +
9622 +#define NUM_INTR_GROUPS 5
9623 +/* 16550 UARTs */
9624 +
9625 +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
9626 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
9627 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
9628 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
9629 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
9630 +
9631 +#ifdef __MIPSEB__
9632 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50003)
9633 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50023)
9634 +#else
9635 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50000)
9636 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50020)
9637 +#endif
9638 +
9639 +#define RC32438_UART0_IRQ GROUP3_IRQ_BASE + 0
9640 +#define RC32438_UART1_IRQ GROUP3_IRQ_BASE + 3
9641 +
9642 +#define RC32438_NR_IRQS (GROUP4_IRQ_BASE + 32)
9643 +
9644 +
9645 +
9646 +/* cpu pipeline flush */
9647 +static inline void rc32438_sync(void)
9648 +{
9649 + __asm__ volatile ("sync");
9650 +}
9651 +
9652 +static inline void rc32438_sync_udelay(int us)
9653 +{
9654 + __asm__ volatile ("sync");
9655 + udelay(us);
9656 +}
9657 +
9658 +static inline void rc32438_sync_delay(int ms)
9659 +{
9660 + __asm__ volatile ("sync");
9661 + mdelay(ms);
9662 +}
9663 +
9664 +/*
9665 + * Macros to access internal RC32438 registers. No byte
9666 + * swapping should be done when accessing the internal
9667 + * registers.
9668 + */
9669 +
9670 +#define rc32438_readb __raw_readb
9671 +#define rc32438_readw __raw_readw
9672 +#define rc32438_readl __raw_readl
9673 +
9674 +#define rc32438_writeb __raw_writeb
9675 +#define rc32438_writew __raw_writew
9676 +#define rc32438_writel __raw_writel
9677 +
9678 +/*
9679 + * C access to CLZ and CLO instructions
9680 + * (count leading zeroes/ones).
9681 + */
9682 +static inline int rc32438_clz(unsigned long val)
9683 +{
9684 + int ret;
9685 + __asm__ volatile (
9686 + ".set\tnoreorder\n\t"
9687 + ".set\tnoat\n\t"
9688 + ".set\tmips32\n\t"
9689 + "clz\t%0,%1\n\t"
9690 + ".set\tmips0\n\t"
9691 + ".set\tat\n\t"
9692 + ".set\treorder"
9693 + : "=r" (ret)
9694 + : "r" (val));
9695 +
9696 + return ret;
9697 +}
9698 +static inline int rc32438_clo(unsigned long val)
9699 +{
9700 + int ret;
9701 + __asm__ volatile (
9702 + ".set\tnoreorder\n\t"
9703 + ".set\tnoat\n\t"
9704 + ".set\tmips32\n\t"
9705 + "clo\t%0,%1\n\t"
9706 + ".set\tmips0\n\t"
9707 + ".set\tat\n\t"
9708 + ".set\treorder"
9709 + : "=r" (ret)
9710 + : "r" (val));
9711 +
9712 + return ret;
9713 +}
9714 +#endif //__IDT_RC32438_H__
9715 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_pci.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h
9716 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 1970-01-01 01:00:00.000000000 +0100
9717 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 2006-03-20 14:25:10.000000000 +0100
9718 @@ -0,0 +1,510 @@
9719 +/**************************************************************************
9720 + *
9721 + * BRIEF MODULE DESCRIPTION
9722 + * Definitions for IDT RC32438 PCI.
9723 + *
9724 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9725 + *
9726 + * This program is free software; you can redistribute it and/or modify it
9727 + * under the terms of the GNU General Public License as published by the
9728 + * Free Software Foundation; either version 2 of the License, or (at your
9729 + * option) any later version.
9730 + *
9731 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9732 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9733 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9734 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9735 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9736 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9737 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9738 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9739 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9740 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9741 + *
9742 + * You should have received a copy of the GNU General Public License along
9743 + * with this program; if not, write to the Free Software Foundation, Inc.,
9744 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9745 + *
9746 + *
9747 + **************************************************************************
9748 + * May 2004 P. Sadik
9749 + *
9750 + * Initial Release
9751 + *
9752 + *
9753 + *
9754 + **************************************************************************
9755 + */
9756 +
9757 +enum
9758 +{
9759 + PCI0_PhysicalAddress = 0x18080000,
9760 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
9761 +
9762 + PCI0_VirtualAddress = 0xb8080000,
9763 + PCI_VirtualAddress = PCI0_VirtualAddress,
9764 +} ;
9765 +
9766 +enum
9767 +{
9768 + PCI_LbaCount = 4, // Local base addresses.
9769 +} ;
9770 +
9771 +typedef struct
9772 +{
9773 + u32 a ; // Address.
9774 + u32 c ; // Control.
9775 + u32 m ; // mapping.
9776 +} PCI_Map_s ;
9777 +
9778 +typedef struct
9779 +{
9780 + u32 pcic ;
9781 + u32 pcis ;
9782 + u32 pcism ;
9783 + u32 pcicfga ;
9784 + u32 pcicfgd ;
9785 + PCI_Map_s pcilba [PCI_LbaCount] ;
9786 + u32 pcidac ;
9787 + u32 pcidas ;
9788 + u32 pcidasm ;
9789 + u32 pcidad ;
9790 + u32 pcidma8c ;
9791 + u32 pcidma9c ;
9792 + u32 pcitc ;
9793 +} volatile *PCI_t ;
9794 +
9795 +// PCI messaging unit.
9796 +enum
9797 +{
9798 + PCIM_Count = 2,
9799 +} ;
9800 +typedef struct
9801 +{
9802 + u32 pciim [PCIM_Count] ;
9803 + u32 pciom [PCIM_Count] ;
9804 + u32 pciid ;
9805 + u32 pciiic ;
9806 + u32 pciiim ;
9807 + u32 pciiod ;
9808 + u32 pciioic ;
9809 + u32 pciioim ;
9810 +} volatile *PCIM_t ;
9811 +
9812 +/*******************************************************************************
9813 + *
9814 + * PCI Control Register
9815 + *
9816 + ******************************************************************************/
9817 +enum
9818 +{
9819 + PCIC_en_b = 0,
9820 + PCIC_en_m = 0x00000001,
9821 + PCIC_tnr_b = 1,
9822 + PCIC_tnr_m = 0x00000002,
9823 + PCIC_sce_b = 2,
9824 + PCIC_sce_m = 0x00000004,
9825 + PCIC_ien_b = 3,
9826 + PCIC_ien_m = 0x00000008,
9827 + PCIC_aaa_b = 4,
9828 + PCIC_aaa_m = 0x00000010,
9829 + PCIC_eap_b = 5,
9830 + PCIC_eap_m = 0x00000020,
9831 + PCIC_pcim_b = 6,
9832 + PCIC_pcim_m = 0x000001c0,
9833 + PCIC_pcim_disabled_v = 0,
9834 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
9835 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
9836 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
9837 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
9838 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
9839 + PCIC_pcim_reserved6_v = 6,
9840 + PCIC_pcim_reserved7_v = 7,
9841 + PCIC_igm_b = 9,
9842 + PCIC_igm_m = 0x00000200,
9843 +} ;
9844 +
9845 +/*******************************************************************************
9846 + *
9847 + * PCI Status Register
9848 + *
9849 + ******************************************************************************/
9850 +enum {
9851 + PCIS_eed_b = 0,
9852 + PCIS_eed_m = 0x00000001,
9853 + PCIS_wr_b = 1,
9854 + PCIS_wr_m = 0x00000002,
9855 + PCIS_nmi_b = 2,
9856 + PCIS_nmi_m = 0x00000004,
9857 + PCIS_ii_b = 3,
9858 + PCIS_ii_m = 0x00000008,
9859 + PCIS_cwe_b = 4,
9860 + PCIS_cwe_m = 0x00000010,
9861 + PCIS_cre_b = 5,
9862 + PCIS_cre_m = 0x00000020,
9863 + PCIS_mdpe_b = 6,
9864 + PCIS_mdpe_m = 0x00000040,
9865 + PCIS_sta_b = 7,
9866 + PCIS_sta_m = 0x00000080,
9867 + PCIS_rta_b = 8,
9868 + PCIS_rta_m = 0x00000100,
9869 + PCIS_rma_b = 9,
9870 + PCIS_rma_m = 0x00000200,
9871 + PCIS_sse_b = 10,
9872 + PCIS_sse_m = 0x00000400,
9873 + PCIS_ose_b = 11,
9874 + PCIS_ose_m = 0x00000800,
9875 + PCIS_pe_b = 12,
9876 + PCIS_pe_m = 0x00001000,
9877 + PCIS_tae_b = 13,
9878 + PCIS_tae_m = 0x00002000,
9879 + PCIS_rle_b = 14,
9880 + PCIS_rle_m = 0x00004000,
9881 + PCIS_bme_b = 15,
9882 + PCIS_bme_m = 0x00008000,
9883 + PCIS_prd_b = 16,
9884 + PCIS_prd_m = 0x00010000,
9885 + PCIS_rip_b = 17,
9886 + PCIS_rip_m = 0x00020000,
9887 +} ;
9888 +
9889 +/*******************************************************************************
9890 + *
9891 + * PCI Status Mask Register
9892 + *
9893 + ******************************************************************************/
9894 +enum {
9895 + PCISM_eed_b = 0,
9896 + PCISM_eed_m = 0x00000001,
9897 + PCISM_wr_b = 1,
9898 + PCISM_wr_m = 0x00000002,
9899 + PCISM_nmi_b = 2,
9900 + PCISM_nmi_m = 0x00000004,
9901 + PCISM_ii_b = 3,
9902 + PCISM_ii_m = 0x00000008,
9903 + PCISM_cwe_b = 4,
9904 + PCISM_cwe_m = 0x00000010,
9905 + PCISM_cre_b = 5,
9906 + PCISM_cre_m = 0x00000020,
9907 + PCISM_mdpe_b = 6,
9908 + PCISM_mdpe_m = 0x00000040,
9909 + PCISM_sta_b = 7,
9910 + PCISM_sta_m = 0x00000080,
9911 + PCISM_rta_b = 8,
9912 + PCISM_rta_m = 0x00000100,
9913 + PCISM_rma_b = 9,
9914 + PCISM_rma_m = 0x00000200,
9915 + PCISM_sse_b = 10,
9916 + PCISM_sse_m = 0x00000400,
9917 + PCISM_ose_b = 11,
9918 + PCISM_ose_m = 0x00000800,
9919 + PCISM_pe_b = 12,
9920 + PCISM_pe_m = 0x00001000,
9921 + PCISM_tae_b = 13,
9922 + PCISM_tae_m = 0x00002000,
9923 + PCISM_rle_b = 14,
9924 + PCISM_rle_m = 0x00004000,
9925 + PCISM_bme_b = 15,
9926 + PCISM_bme_m = 0x00008000,
9927 + PCISM_prd_b = 16,
9928 + PCISM_prd_m = 0x00010000,
9929 + PCISM_rip_b = 17,
9930 + PCISM_rip_m = 0x00020000,
9931 +} ;
9932 +
9933 +/*******************************************************************************
9934 + *
9935 + * PCI Configuration Address Register
9936 + *
9937 + ******************************************************************************/
9938 +enum {
9939 + PCICFGA_reg_b = 2,
9940 + PCICFGA_reg_m = 0x000000fc,
9941 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
9942 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
9943 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
9944 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
9945 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
9946 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
9947 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
9948 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
9949 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
9950 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
9951 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
9952 + PCICFGA_reg_pba0m_v = 0x48>>2,
9953 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
9954 + PCICFGA_reg_pba1m_v = 0x50>>2,
9955 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
9956 + PCICFGA_reg_pba2m_v = 0x58>>2,
9957 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
9958 + PCICFGA_reg_pba3m_v = 0x60>>2,
9959 + PCICFGA_reg_pmgt_v = 0x64>>2,
9960 + PCICFGA_func_b = 8,
9961 + PCICFGA_func_m = 0x00000700,
9962 + PCICFGA_dev_b = 11,
9963 + PCICFGA_dev_m = 0x0000f800,
9964 + PCICFGA_dev_internal_v = 0,
9965 + PCICFGA_bus_b = 16,
9966 + PCICFGA_bus_m = 0x00ff0000,
9967 + PCICFGA_bus_type0_v = 0, //local bus
9968 + PCICFGA_en_b = 31, // read only
9969 + PCICFGA_en_m = 0x80000000,
9970 +} ;
9971 +
9972 +enum {
9973 + PCFGID_vendor_b = 0,
9974 + PCFGID_vendor_m = 0x0000ffff,
9975 + PCFGID_vendor_IDT_v = 0x111d,
9976 + PCFGID_device_b = 16,
9977 + PCFGID_device_m = 0xffff0000,
9978 + PCFGID_device_Acaciade_v = 0x0207,
9979 +
9980 + PCFG04_command_ioena_b = 1,
9981 + PCFG04_command_ioena_m = 0x00000001,
9982 + PCFG04_command_memena_b = 2,
9983 + PCFG04_command_memena_m = 0x00000002,
9984 + PCFG04_command_bmena_b = 3,
9985 + PCFG04_command_bmena_m = 0x00000004,
9986 + PCFG04_command_mwinv_b = 5,
9987 + PCFG04_command_mwinv_m = 0x00000010,
9988 + PCFG04_command_parena_b = 7,
9989 + PCFG04_command_parena_m = 0x00000040,
9990 + PCFG04_command_serrena_b = 9,
9991 + PCFG04_command_serrena_m = 0x00000100,
9992 + PCFG04_command_fastbbena_b = 10,
9993 + PCFG04_command_fastbbena_m = 0x00000200,
9994 + PCFG04_status_b = 16,
9995 + PCFG04_status_m = 0xffff0000,
9996 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
9997 + PCFG04_status_66MHz_m = 0x00200000,
9998 + PCFG04_status_fbb_b = 23,
9999 + PCFG04_status_fbb_m = 0x00800000,
10000 + PCFG04_status_mdpe_b = 24,
10001 + PCFG04_status_mdpe_m = 0x01000000,
10002 + PCFG04_status_dst_b = 25,
10003 + PCFG04_status_dst_m = 0x06000000,
10004 + PCFG04_status_sta_b = 27,
10005 + PCFG04_status_sta_m = 0x08000000,
10006 + PCFG04_status_rta_b = 28,
10007 + PCFG04_status_rta_m = 0x10000000,
10008 + PCFG04_status_rma_b = 29,
10009 + PCFG04_status_rma_m = 0x20000000,
10010 + PCFG04_status_sse_b = 30,
10011 + PCFG04_status_sse_m = 0x40000000,
10012 + PCFG04_status_pe_b = 31,
10013 + PCFG04_status_pe_m = 0x40000000,
10014 +
10015 + PCFG08_revId_b = 0,
10016 + PCFG08_revId_m = 0x000000ff,
10017 + PCFG08_classCode_b = 0,
10018 + PCFG08_classCode_m = 0xffffff00,
10019 + PCFG08_classCode_bridge_v = 06,
10020 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
10021 + PCFG0C_cacheline_b = 0,
10022 + PCFG0C_cacheline_m = 0x000000ff,
10023 + PCFG0C_masterLatency_b = 8,
10024 + PCFG0C_masterLatency_m = 0x0000ff00,
10025 + PCFG0C_headerType_b = 16,
10026 + PCFG0C_headerType_m = 0x00ff0000,
10027 + PCFG0C_bist_b = 24,
10028 + PCFG0C_bist_m = 0xff000000,
10029 +
10030 + PCIPBA_msi_b = 0,
10031 + PCIPBA_msi_m = 0x00000001,
10032 + PCIPBA_p_b = 3,
10033 + PCIPBA_p_m = 0x00000004,
10034 + PCIPBA_baddr_b = 8,
10035 + PCIPBA_baddr_m = 0xffffff00,
10036 +
10037 + PCFGSS_vendorId_b = 0,
10038 + PCFGSS_vendorId_m = 0x0000ffff,
10039 + PCFGSS_id_b = 16,
10040 + PCFGSS_id_m = 0xffff0000,
10041 +
10042 + PCFG3C_interruptLine_b = 0,
10043 + PCFG3C_interruptLine_m = 0x000000ff,
10044 + PCFG3C_interruptPin_b = 8,
10045 + PCFG3C_interruptPin_m = 0x0000ff00,
10046 + PCFG3C_minGrant_b = 16,
10047 + PCFG3C_minGrant_m = 0x00ff0000,
10048 + PCFG3C_maxLat_b = 24,
10049 + PCFG3C_maxLat_m = 0xff000000,
10050 +
10051 + PCIPBAC_msi_b = 0,
10052 + PCIPBAC_msi_m = 0x00000001,
10053 + PCIPBAC_p_b = 1,
10054 + PCIPBAC_p_m = 0x00000002,
10055 + PCIPBAC_size_b = 2,
10056 + PCIPBAC_size_m = 0x0000007c,
10057 + PCIPBAC_sb_b = 7,
10058 + PCIPBAC_sb_m = 0x00000080,
10059 + PCIPBAC_pp_b = 8,
10060 + PCIPBAC_pp_m = 0x00000100,
10061 + PCIPBAC_mr_b = 9,
10062 + PCIPBAC_mr_m = 0x00000600,
10063 + PCIPBAC_mr_read_v =0, //no prefetching
10064 + PCIPBAC_mr_readLine_v =1,
10065 + PCIPBAC_mr_readMult_v =2,
10066 + PCIPBAC_mrl_b = 11,
10067 + PCIPBAC_mrl_m = 0x00000800,
10068 + PCIPBAC_mrm_b = 12,
10069 + PCIPBAC_mrm_m = 0x00001000,
10070 + PCIPBAC_trp_b = 13,
10071 + PCIPBAC_trp_m = 0x00002000,
10072 +
10073 + PCFG40_trdyTimeout_b = 0,
10074 + PCFG40_trdyTimeout_m = 0x000000ff,
10075 + PCFG40_retryLim_b = 8,
10076 + PCFG40_retryLim_m = 0x0000ff00,
10077 +};
10078 +
10079 +/*******************************************************************************
10080 + *
10081 + * PCI Local Base Address [0|1|2|3] Register
10082 + *
10083 + ******************************************************************************/
10084 +enum {
10085 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
10086 + PCILBA_baddr_m = 0xffffff00,
10087 +} ;
10088 +/*******************************************************************************
10089 + *
10090 + * PCI Local Base Address Control Register
10091 + *
10092 + ******************************************************************************/
10093 +enum {
10094 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
10095 + PCILBAC_msi_m = 0x00000001,
10096 + PCILBAC_msi_mem_v = 0,
10097 + PCILBAC_msi_io_v = 1,
10098 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
10099 + PCILBAC_size_m = 0x0000007c,
10100 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
10101 + PCILBAC_sb_m = 0x00000080,
10102 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
10103 + PCILBAC_rt_m = 0x00000100,
10104 + PCILBAC_rt_noprefetch_v = 0, // mem read
10105 + PCILBAC_rt_prefetch_v = 1, // mem readline
10106 +} ;
10107 +
10108 +/*******************************************************************************
10109 + *
10110 + * PCI Local Base Address [0|1|2|3] Mapping Register
10111 + *
10112 + ******************************************************************************/
10113 +enum {
10114 + PCILBAM_maddr_b = 8,
10115 + PCILBAM_maddr_m = 0xffffff00,
10116 +} ;
10117 +
10118 +/*******************************************************************************
10119 + *
10120 + * PCI Decoupled Access Control Register
10121 + *
10122 + ******************************************************************************/
10123 +enum {
10124 + PCIDAC_den_b = 0,
10125 + PCIDAC_den_m = 0x00000001,
10126 +} ;
10127 +
10128 +/*******************************************************************************
10129 + *
10130 + * PCI Decoupled Access Status Register
10131 + *
10132 + ******************************************************************************/
10133 +enum {
10134 + PCIDAS_d_b = 0,
10135 + PCIDAS_d_m = 0x00000001,
10136 + PCIDAS_b_b = 1,
10137 + PCIDAS_b_m = 0x00000002,
10138 + PCIDAS_e_b = 2,
10139 + PCIDAS_e_m = 0x00000004,
10140 + PCIDAS_ofe_b = 3,
10141 + PCIDAS_ofe_m = 0x00000008,
10142 + PCIDAS_off_b = 4,
10143 + PCIDAS_off_m = 0x00000010,
10144 + PCIDAS_ife_b = 5,
10145 + PCIDAS_ife_m = 0x00000020,
10146 + PCIDAS_iff_b = 6,
10147 + PCIDAS_iff_m = 0x00000040,
10148 +} ;
10149 +
10150 +/*******************************************************************************
10151 + *
10152 + * PCI DMA Channel 8 Configuration Register
10153 + *
10154 + ******************************************************************************/
10155 +enum
10156 +{
10157 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
10158 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
10159 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
10160 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
10161 +} ;
10162 +
10163 +/*******************************************************************************
10164 + *
10165 + * PCI DMA Channel 9 Configuration Register
10166 + *
10167 + ******************************************************************************/
10168 +enum
10169 +{
10170 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
10171 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
10172 +} ;
10173 +
10174 +/*******************************************************************************
10175 + *
10176 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
10177 + *
10178 + ******************************************************************************/
10179 +enum {
10180 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
10181 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
10182 + // These are for reads (DMA channel 8)
10183 + PCIDMAD_devcmd_mr_v = 0, //memory read
10184 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
10185 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
10186 + PCIDMAD_devcmd_ior_v = 3, //I/O read
10187 + // These are for writes (DMA channel 9)
10188 + PCIDMAD_devcmd_mw_v = 0, //memory write
10189 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
10190 + PCIDMAD_devcmd_iow_v = 3, //I/O write
10191 +
10192 + // Swap byte field applies to both DMA channel 8 and 9
10193 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
10194 + PCIDMAD_sb_m = 0x01000000, // swap byte field
10195 +} ;
10196 +
10197 +
10198 +/*******************************************************************************
10199 + *
10200 + * PCI Target Control Register
10201 + *
10202 + ******************************************************************************/
10203 +enum
10204 +{
10205 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
10206 + PCITC_rtimer_m = 0x000000ff,
10207 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
10208 + PCITC_dtimer_m = 0x0000ff00,
10209 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
10210 + PCITC_rdr_m = 0x00040000,
10211 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
10212 + PCITC_ddt_m = 0x00080000,
10213 +} ;
10214 +/*******************************************************************************
10215 + *
10216 + * PCI messaging unit [applies to both inbound and outbound registers ]
10217 + *
10218 + ******************************************************************************/
10219 +enum
10220 +{
10221 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10222 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
10223 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10224 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
10225 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10226 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
10227 +};
10228 +
10229 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h
10230 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h 1970-01-01 01:00:00.000000000 +0100
10231 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h 2006-03-20 14:25:10.000000000 +0100
10232 @@ -0,0 +1,190 @@
10233 +/**************************************************************************
10234 + *
10235 + * BRIEF MODULE DESCRIPTION
10236 + * Definitions for IDT RC32438 PCI setup.
10237 + *
10238 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
10239 + *
10240 + * This program is free software; you can redistribute it and/or modify it
10241 + * under the terms of the GNU General Public License as published by the
10242 + * Free Software Foundation; either version 2 of the License, or (at your
10243 + * option) any later version.
10244 + *
10245 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10246 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
10247 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10248 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
10249 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10250 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
10251 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10252 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10253 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10254 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10255 + *
10256 + * You should have received a copy of the GNU General Public License along
10257 + * with this program; if not, write to the Free Software Foundation, Inc.,
10258 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10259 + *
10260 + *
10261 + **************************************************************************
10262 + * May 2004 P. Sadik
10263 + *
10264 + * Initial Release
10265 + *
10266 + *
10267 + *
10268 + **************************************************************************
10269 + */
10270 +
10271 +#define PCI_MSG_VirtualAddress 0xB8088010
10272 +#define rc32438_pci ((volatile PCI_t) PCI0_VirtualAddress)
10273 +#define rc32438_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
10274 +
10275 +#define PCIM_SHFT 0x6
10276 +#define PCIM_BIT_LEN 0x7
10277 +#define PCIM_H_EA 0x3
10278 +#define PCIM_H_IA_FIX 0x4
10279 +#define PCIM_H_IA_RR 0x5
10280 +
10281 +#define PCI_ADDR_START 0x50000000
10282 +
10283 +#define CPUTOPCI_MEM_WIN 0x02000000
10284 +#define CPUTOPCI_IO_WIN 0x00100000
10285 +#define PCILBA_SIZE_SHFT 2
10286 +#define PCILBA_SIZE_MASK 0x1F
10287 +#define SIZE_256MB 0x1C
10288 +#define SIZE_128MB 0x1B
10289 +#define SIZE_64MB 0x1A
10290 +#define SIZE_32MB 0x19
10291 +#define SIZE_16MB 0x18
10292 +#define SIZE_4MB 0x16
10293 +#define SIZE_2MB 0x15
10294 +#define SIZE_1MB 0x14
10295 +#define ACACIA_CONFIG0_ADDR 0x80000000
10296 +#define ACACIA_CONFIG1_ADDR 0x80000004
10297 +#define ACACIA_CONFIG2_ADDR 0x80000008
10298 +#define ACACIA_CONFIG3_ADDR 0x8000000C
10299 +#define ACACIA_CONFIG4_ADDR 0x80000010
10300 +#define ACACIA_CONFIG5_ADDR 0x80000014
10301 +#define ACACIA_CONFIG6_ADDR 0x80000018
10302 +#define ACACIA_CONFIG7_ADDR 0x8000001C
10303 +#define ACACIA_CONFIG8_ADDR 0x80000020
10304 +#define ACACIA_CONFIG9_ADDR 0x80000024
10305 +#define ACACIA_CONFIG10_ADDR 0x80000028
10306 +#define ACACIA_CONFIG11_ADDR 0x8000002C
10307 +#define ACACIA_CONFIG12_ADDR 0x80000030
10308 +#define ACACIA_CONFIG13_ADDR 0x80000034
10309 +#define ACACIA_CONFIG14_ADDR 0x80000038
10310 +#define ACACIA_CONFIG15_ADDR 0x8000003C
10311 +#define ACACIA_CONFIG16_ADDR 0x80000040
10312 +#define ACACIA_CONFIG17_ADDR 0x80000044
10313 +#define ACACIA_CONFIG18_ADDR 0x80000048
10314 +#define ACACIA_CONFIG19_ADDR 0x8000004C
10315 +#define ACACIA_CONFIG20_ADDR 0x80000050
10316 +#define ACACIA_CONFIG21_ADDR 0x80000054
10317 +#define ACACIA_CONFIG22_ADDR 0x80000058
10318 +#define ACACIA_CONFIG23_ADDR 0x8000005C
10319 +#define ACACIA_CONFIG24_ADDR 0x80000060
10320 +#define ACACIA_CONFIG25_ADDR 0x80000064
10321 +#define ACACIA_CMD (PCFG04_command_ioena_m | \
10322 + PCFG04_command_memena_m | \
10323 + PCFG04_command_bmena_m | \
10324 + PCFG04_command_mwinv_m | \
10325 + PCFG04_command_parena_m | \
10326 + PCFG04_command_serrena_m )
10327 +
10328 +#define ACACIA_STAT (PCFG04_status_mdpe_m | \
10329 + PCFG04_status_sta_m | \
10330 + PCFG04_status_rta_m | \
10331 + PCFG04_status_rma_m | \
10332 + PCFG04_status_sse_m | \
10333 + PCFG04_status_pe_m)
10334 +
10335 +#define ACACIA_CNFG1 ((ACACIA_STAT<<16)|ACACIA_CMD)
10336 +
10337 +#define ACACIA_REVID 0
10338 +#define ACACIA_CLASS_CODE 0
10339 +#define ACACIA_CNFG2 ((ACACIA_CLASS_CODE<<8) | \
10340 + ACACIA_REVID)
10341 +
10342 +#define ACACIA_CACHE_LINE_SIZE 4
10343 +#define ACACIA_MASTER_LAT 0x3c
10344 +#define ACACIA_HEADER_TYPE 0
10345 +#define ACACIA_BIST 0
10346 +
10347 +#define ACACIA_CNFG3 ((ACACIA_BIST << 24) | \
10348 + (ACACIA_HEADER_TYPE<<16) | \
10349 + (ACACIA_MASTER_LAT<<8) | \
10350 + ACACIA_CACHE_LINE_SIZE )
10351 +
10352 +#define ACACIA_BAR0 0x00000008 /* 128 MB Memory */
10353 +#define ACACIA_BAR1 0x18800001 /* 1 MB IO */
10354 +#define ACACIA_BAR2 0x18000001 /* 2 MB IO window for Acacia
10355 + internal Registers */
10356 +#define ACACIA_BAR3 0x48000008 /* Spare 128 MB Memory */
10357 +
10358 +#define ACACIA_CNFG4 ACACIA_BAR0
10359 +#define ACACIA_CNFG5 ACACIA_BAR1
10360 +#define ACACIA_CNFG6 ACACIA_BAR2
10361 +#define ACACIA_CNFG7 ACACIA_BAR3
10362 +
10363 +#define ACACIA_SUBSYS_VENDOR_ID 0
10364 +#define ACACIA_SUBSYSTEM_ID 0
10365 +#define ACACIA_CNFG8 0
10366 +#define ACACIA_CNFG9 0
10367 +#define ACACIA_CNFG10 0
10368 +#define ACACIA_CNFG11 ((ACACIA_SUBSYS_VENDOR_ID<<16) | \
10369 + ACACIA_SUBSYSTEM_ID)
10370 +#define ACACIA_INT_LINE 1
10371 +#define ACACIA_INT_PIN 1
10372 +#define ACACIA_MIN_GNT 8
10373 +#define ACACIA_MAX_LAT 0x38
10374 +#define ACACIA_CNFG12 0
10375 +#define ACACIA_CNFG13 0
10376 +#define ACACIA_CNFG14 0
10377 +#define ACACIA_CNFG15 ((ACACIA_MAX_LAT<<24) | \
10378 + (ACACIA_MIN_GNT<<16) | \
10379 + (ACACIA_INT_PIN<<8) | \
10380 + ACACIA_INT_LINE)
10381 +#define ACACIA_RETRY_LIMIT 0x80
10382 +#define ACACIA_TRDY_LIMIT 0x80
10383 +#define ACACIA_CNFG16 ((ACACIA_RETRY_LIMIT<<8) | \
10384 + ACACIA_TRDY_LIMIT)
10385 +#define PCI_PBAxC_R 0x0
10386 +#define PCI_PBAxC_RL 0x1
10387 +#define PCI_PBAxC_RM 0x2
10388 +#define SIZE_SHFT 2
10389 +
10390 +#define ACACIA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
10391 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
10392 + PCIPBAC_pp_m | \
10393 + (SIZE_128MB<<SIZE_SHFT) | \
10394 + PCIPBAC_p_m)
10395 +
10396 +#define ACACIA_CNFG17 ACACIA_PBA0C
10397 +#define ACACIA_PBA0M 0x0
10398 +#define ACACIA_CNFG18 ACACIA_PBA0M
10399 +
10400 +#define ACACIA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
10401 + PCIPBAC_msi_m)
10402 +
10403 +#define ACACIA_CNFG19 ACACIA_PBA1C
10404 +#define ACACIA_PBA1M 0x0
10405 +#define ACACIA_CNFG20 ACACIA_PBA1M
10406 +
10407 +#define ACACIA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
10408 + PCIPBAC_msi_m)
10409 +
10410 +#define ACACIA_CNFG21 ACACIA_PBA2C
10411 +#define ACACIA_PBA2M 0x18000000
10412 +#define ACACIA_CNFG22 ACACIA_PBA2M
10413 +#define ACACIA_PBA3C 0
10414 +#define ACACIA_CNFG23 ACACIA_PBA3C
10415 +#define ACACIA_PBA3M 0
10416 +#define ACACIA_CNFG24 ACACIA_PBA3M
10417 +
10418 +
10419 +
10420 +#define PCITC_DTIMER_VAL 8
10421 +#define PCITC_RTIMER_VAL 0x10
10422 +
10423 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_timer.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h
10424 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_timer.h 1970-01-01 01:00:00.000000000 +0100
10425 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h 2006-03-20 14:25:10.000000000 +0100
10426 @@ -0,0 +1,91 @@
10427 +/**************************************************************************
10428 + *
10429 + * BRIEF MODULE DESCRIPTION
10430 + * Timer register definition IDT RC32438 CPU.
10431 + *
10432 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
10433 + *
10434 + * This program is free software; you can redistribute it and/or modify it
10435 + * under the terms of the GNU General Public License as published by the
10436 + * Free Software Foundation; either version 2 of the License, or (at your
10437 + * option) any later version.
10438 + *
10439 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10440 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
10441 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10442 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
10443 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10444 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
10445 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10446 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10447 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10448 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10449 + *
10450 + * You should have received a copy of the GNU General Public License along
10451 + * with this program; if not, write to the Free Software Foundation, Inc.,
10452 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10453 + *
10454 + *
10455 + **************************************************************************
10456 + * May 2004 P. Sadik.
10457 + *
10458 + * Initial Release
10459 + *
10460 + *
10461 + *
10462 + **************************************************************************
10463 + */
10464 +
10465 +#ifndef __IDT_RC32438_TIM_H__
10466 +#define __IDT_RC32438_TIM_H__
10467 +
10468 +enum
10469 +{
10470 + TIM0_PhysicalAddress = 0x18028000,
10471 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
10472 +
10473 + TIM0_VirtualAddress = 0xb8028000,
10474 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
10475 +} ;
10476 +
10477 +enum
10478 +{
10479 + TIM_Count = 3,
10480 +} ;
10481 +
10482 +struct TIM_CNTR_s
10483 +{
10484 + u32 count ;
10485 + u32 compare ;
10486 + u32 ctc ; //use CTC_
10487 +} ;
10488 +
10489 +typedef struct TIM_s
10490 +{
10491 + struct TIM_CNTR_s tim [TIM_Count] ;
10492 + u32 rcount ; //use RCOUNT_
10493 + u32 rcompare ; //use RCOMPARE_
10494 + u32 rtc ; //use RTC_
10495 +} volatile * TIM_t ;
10496 +
10497 +enum
10498 +{
10499 + CTC_en_b = 0,
10500 + CTC_en_m = 0x00000001,
10501 + CTC_to_b = 1,
10502 + CTC_to_m = 0x00000002,
10503 +
10504 + RCOUNT_count_b = 0,
10505 + RCOUNT_count_m = 0x0000ffff,
10506 + RCOMPARE_compare_b = 0,
10507 + RCOMPARE_compare_m = 0x0000ffff,
10508 + RTC_ce_b = 0,
10509 + RTC_ce_m = 0x00000001,
10510 + RTC_to_b = 1,
10511 + RTC_to_m = 0x00000002,
10512 + RTC_rqe_b = 2,
10513 + RTC_rqe_m = 0x00000004,
10514 +
10515 +} ;
10516 +#endif //__IDT_RC32438_TIM_H__
10517 +
10518 diff -Nur linux-2.6.16/include/asm-mips/mach-generic/irq.h linux-2.6.16-owrt/include/asm-mips/mach-generic/irq.h
10519 --- linux-2.6.16/include/asm-mips/mach-generic/irq.h 2006-03-20 06:53:29.000000000 +0100
10520 +++ linux-2.6.16-owrt/include/asm-mips/mach-generic/irq.h 2006-03-20 14:25:10.000000000 +0100
10521 @@ -8,6 +8,6 @@
10522 #ifndef __ASM_MACH_GENERIC_IRQ_H
10523 #define __ASM_MACH_GENERIC_IRQ_H
10524
10525 -#define NR_IRQS 128
10526 +#define NR_IRQS 256
10527
10528 #endif /* __ASM_MACH_GENERIC_IRQ_H */
10529 diff -Nur linux-2.6.16/include/linux/init.h linux-2.6.16-owrt/include/linux/init.h
10530 --- linux-2.6.16/include/linux/init.h 2006-03-20 06:53:29.000000000 +0100
10531 +++ linux-2.6.16-owrt/include/linux/init.h 2006-03-20 14:25:10.000000000 +0100
10532 @@ -86,6 +86,8 @@
10533 static initcall_t __initcall_##fn __attribute_used__ \
10534 __attribute__((__section__(".initcall" level ".init"))) = fn
10535
10536 +#define early_initcall(fn) __define_initcall(".early1",fn)
10537 +
10538 #define core_initcall(fn) __define_initcall("1",fn)
10539 #define postcore_initcall(fn) __define_initcall("2",fn)
10540 #define arch_initcall(fn) __define_initcall("3",fn)
10541 diff -Nur linux-2.6.16/include/linux/kernel.h linux-2.6.16-owrt/include/linux/kernel.h
10542 --- linux-2.6.16/include/linux/kernel.h 2006-03-20 06:53:29.000000000 +0100
10543 +++ linux-2.6.16-owrt/include/linux/kernel.h 2006-03-20 14:25:10.000000000 +0100
10544 @@ -324,6 +324,7 @@
10545 };
10546
10547 /* Force a compilation error if condition is true */
10548 +extern void BUILD_BUG(void);
10549 #define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
10550
10551 /* Trap pasters of __FUNCTION__ at compile-time */
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