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make a image for netgear, loader need to be ELF
[openwrt.git] / target / linux / linux-2.6 / patches / brcm / 001-bcm947xx.patch
1 diff -Nur linux-2.6.12.5/arch/mips/Kconfig linux-2.6.12.5-brcm/arch/mips/Kconfig
2 --- linux-2.6.12.5/arch/mips/Kconfig 2005-08-15 02:20:18.000000000 +0200
3 +++ linux-2.6.12.5-brcm/arch/mips/Kconfig 2005-08-28 16:21:04.700803432 +0200
4 @@ -40,6 +40,15 @@
5 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
6 Olivetti M700-10 workstations.
7
8 +config BCM947XX
9 + bool "Support for BCM947xx based boards"
10 + select DMA_NONCOHERENT
11 + select HW_HAS_PCI
12 + select IRQ_CPU
13 + select CPU_LITTLE_ENDIAN
14 + help
15 + Support for BCM947xx based boards
16 +
17 config ACER_PICA_61
18 bool "Support for Acer PICA 1 chipset (EXPERIMENTAL)"
19 depends on MACH_JAZZ && EXPERIMENTAL
20 @@ -974,7 +983,7 @@
21
22 config CPU_LITTLE_ENDIAN
23 bool "Generate little endian code"
24 - default y if ACER_PICA_61 || CASIO_E55 || DDB5074 || DDB5476 || DDB5477 || MACH_DECSTATION || IBM_WORKPAD || LASAT || MIPS_COBALT || MIPS_ITE8172 || MIPS_IVR || SOC_AU1X00 || NEC_OSPREY || OLIVETTI_M700 || SNI_RM200_PCI || VICTOR_MPC30X || ZAO_CAPCELLA
25 + default y if ACER_PICA_61 || CASIO_E55 || DDB5074 || DDB5476 || DDB5477 || MACH_DECSTATION || IBM_WORKPAD || LASAT || MIPS_COBALT || MIPS_ITE8172 || MIPS_IVR || SOC_AU1X00 || NEC_OSPREY || OLIVETTI_M700 || SNI_RM200_PCI || VICTOR_MPC30X || ZAO_CAPCELLA || BCM47XX
26 default n if MIPS_EV64120 || MIPS_EV96100 || MOMENCO_OCELOT || MOMENCO_OCELOT_G || SGI_IP22 || SGI_IP27 || SGI_IP32 || TOSHIBA_JMR3927
27 help
28 Some MIPS machines can be configured for either little or big endian
29 diff -Nur linux-2.6.12.5/arch/mips/Makefile linux-2.6.12.5-brcm/arch/mips/Makefile
30 --- linux-2.6.12.5/arch/mips/Makefile 2005-08-15 02:20:18.000000000 +0200
31 +++ linux-2.6.12.5-brcm/arch/mips/Makefile 2005-08-28 16:39:59.077334424 +0200
32 @@ -79,7 +79,7 @@
33 cflags-y += -I $(TOPDIR)/include/asm/gcc
34 cflags-y += -G 0 -mno-abicalls -fno-pic -pipe
35 cflags-y += $(call cc-option, -finline-limit=100000)
36 -LDFLAGS_vmlinux += -G 0 -static -n
37 +LDFLAGS_vmlinux += -G 0 -static -n -nostdlib
38 MODFLAGS += -mlong-calls
39
40 cflags-$(CONFIG_SB1XXX_CORELIS) += -mno-sched-prolog -fno-omit-frame-pointer
41 @@ -167,9 +167,10 @@
42 $(call set_gccflags,r4600,mips3,r4600,mips3,mips2) \
43 -Wa,--trap
44
45 -cflags-$(CONFIG_CPU_MIPS32) += \
46 - $(call set_gccflags,mips32,mips32,r4600,mips3,mips2) \
47 - -Wa,--trap
48 +#cflags-$(CONFIG_CPU_MIPS32) += \
49 +# $(call set_gccflags,mips32,mips32,r4600,mips3,mips2) \
50 +# -Wa,--trap
51 +cflags-$(CONFIG_CPU_MIPS32) += -mips2 -Wa,--trap
52
53 cflags-$(CONFIG_CPU_MIPS64) += \
54 $(call set_gccflags,mips64,mips64,r4600,mips3,mips2) \
55 @@ -618,6 +619,14 @@
56 load-$(CONFIG_SIBYTE_SWARM) := 0xffffffff80100000
57
58 #
59 +# Broadcom BCM47XX boards
60 +#
61 +core-$(CONFIG_BCM947XX) += arch/mips/bcm947xx/ arch/mips/bcm947xx/broadcom/
62 +cflags-$(CONFIG_BCM947XX) += -Iarch/mips/bcm947xx/include
63 +load-$(CONFIG_BCM947XX) := 0xffffffff80001000
64 +
65 +
66 +#
67 # SNI RM200 PCI
68 #
69 core-$(CONFIG_SNI_RM200_PCI) += arch/mips/sni/
70 @@ -729,6 +738,7 @@
71 archclean:
72 @$(MAKE) $(clean)=arch/mips/boot
73 @$(MAKE) $(clean)=arch/mips/lasat
74 + @$(MAKE) -C arch/mips/bcm47xx/compressed clean
75
76 # Generate <asm/offset.h
77 #
78 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/Makefile linux-2.6.12.5-brcm/arch/mips/bcm947xx/Makefile
79 --- linux-2.6.12.5/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
80 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/Makefile 2005-08-28 11:12:20.406862800 +0200
81 @@ -0,0 +1,6 @@
82 +#
83 +# Makefile for the BCM47xx specific kernel interface routines
84 +# under Linux.
85 +#
86 +
87 +obj-y := irq.o int-handler.o prom.o setup.o time.o
88 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/broadcom/Makefile linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/Makefile
89 --- linux-2.6.12.5/arch/mips/bcm947xx/broadcom/Makefile 1970-01-01 01:00:00.000000000 +0100
90 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/Makefile 2005-08-28 11:12:20.407862648 +0200
91 @@ -0,0 +1,6 @@
92 +#
93 +# Makefile for the BCM47xx specific kernel interface routines
94 +# under Linux.
95 +#
96 +
97 +obj-y := sbutils.o linux_osl.o bcmsrom.o bcmutils.o sbmips.o sbpci.o hnddma.o
98 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/broadcom/bcmsrom.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/bcmsrom.c
99 --- linux-2.6.12.5/arch/mips/bcm947xx/broadcom/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
100 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/bcmsrom.c 2005-08-28 11:12:20.408862496 +0200
101 @@ -0,0 +1,685 @@
102 +/*
103 + * Misc useful routines to access NIC SROM
104 + *
105 + * Copyright 2001-2003, Broadcom Corporation
106 + * All Rights Reserved.
107 + *
108 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
109 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
110 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
111 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
112 + * $Id: bcmsrom.c,v 1.1 2005/02/28 13:33:32 jolt Exp $
113 + */
114 +
115 +#include <typedefs.h>
116 +#include <osl.h>
117 +#include <bcmutils.h>
118 +#include <bcmsrom.h>
119 +#include <bcmdevs.h>
120 +#include <bcmendian.h>
121 +#include <sbpcmcia.h>
122 +#include <pcicfg.h>
123 +
124 +#include <proto/ethernet.h> /* for sprom content groking */
125 +
126 +#define VARS_MAX 4096 /* should be reduced */
127 +
128 +static int initvars_srom_pci(void *curmap, char **vars, int *count);
129 +static int initvars_cis_pcmcia(void *osh, char **vars, int *count);
130 +static int sprom_cmd_pcmcia(void *osh, uint8 cmd);
131 +static int sprom_read_pcmcia(void *osh, uint16 addr, uint16 *data);
132 +static int sprom_write_pcmcia(void *osh, uint16 addr, uint16 data);
133 +static int sprom_read_pci(uint16 *sprom, uint byteoff, uint16 *buf, uint nbytes, bool check_crc);
134 +
135 +/*
136 + * Initialize the vars from the right source for this platform.
137 + * Return 0 on success, nonzero on error.
138 + */
139 +int
140 +srom_var_init(uint bus, void *curmap, void *osh, char **vars, int *count)
141 +{
142 + if (vars == NULL)
143 + return (0);
144 +
145 + switch (bus) {
146 + case SB_BUS:
147 + /* These two could be asserts ... */
148 + *vars = NULL;
149 + *count = 0;
150 + return(0);
151 +
152 + case PCI_BUS:
153 + ASSERT(curmap); /* can not be NULL */
154 + return(initvars_srom_pci(curmap, vars, count));
155 +
156 + case PCMCIA_BUS:
157 + return(initvars_cis_pcmcia(osh, vars, count));
158 +
159 +
160 + default:
161 + ASSERT(0);
162 + }
163 + return (-1);
164 +}
165 +
166 +
167 +/* support only 16-bit word read from srom */
168 +int
169 +srom_read(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf)
170 +{
171 + void *srom;
172 + uint i, off, nw;
173 +
174 + /* check input - 16-bit access only */
175 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
176 + return 1;
177 +
178 + if (bus == PCI_BUS) {
179 + if (!curmap)
180 + return 1;
181 + srom = (void *)((uint)curmap + PCI_BAR0_SPROM_OFFSET);
182 + if (sprom_read_pci(srom, byteoff, buf, nbytes, FALSE))
183 + return 1;
184 + } else if (bus == PCMCIA_BUS) {
185 + off = byteoff / 2;
186 + nw = nbytes / 2;
187 + for (i = 0; i < nw; i++) {
188 + if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
189 + return 1;
190 + }
191 + } else {
192 + return 1;
193 + }
194 +
195 + return 0;
196 +}
197 +
198 +/* support only 16-bit word write into srom */
199 +int
200 +srom_write(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf)
201 +{
202 + uint16 *srom;
203 + uint i, off, nw, crc_range;
204 + uint16 image[SPROM_SIZE], *p;
205 + uint8 crc;
206 + volatile uint32 val32;
207 +
208 + /* check input - 16-bit access only */
209 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
210 + return 1;
211 +
212 + crc_range = ((bus == PCMCIA_BUS) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
213 +
214 + /* if changes made inside crc cover range */
215 + if (byteoff < crc_range) {
216 + nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
217 + /* read data including entire first 64 words from srom */
218 + if (srom_read(bus, curmap, osh, 0, nw * 2, image))
219 + return 1;
220 + /* make changes */
221 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
222 + /* calculate crc */
223 + htol16_buf(image, crc_range);
224 + crc = ~crc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
225 + ltoh16_buf(image, crc_range);
226 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
227 + p = image;
228 + off = 0;
229 + } else {
230 + p = buf;
231 + off = byteoff / 2;
232 + nw = nbytes / 2;
233 + }
234 +
235 + if (bus == PCI_BUS) {
236 + srom = (uint16*)((uint)curmap + PCI_BAR0_SPROM_OFFSET);
237 + /* enable writes to the SPROM */
238 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
239 + val32 |= SPROM_WRITEEN;
240 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
241 + bcm_mdelay(500);
242 + /* write srom */
243 + for (i = 0; i < nw; i++) {
244 + W_REG(&srom[off + i], p[i]);
245 + bcm_mdelay(20);
246 + }
247 + /* disable writes to the SPROM */
248 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
249 + } else if (bus == PCMCIA_BUS) {
250 + /* enable writes to the SPROM */
251 + if (sprom_cmd_pcmcia(osh, SROM_WEN))
252 + return 1;
253 + bcm_mdelay(500);
254 + /* write srom */
255 + for (i = 0; i < nw; i++) {
256 + sprom_write_pcmcia(osh, (uint16)(off + i), p[i]);
257 + bcm_mdelay(20);
258 + }
259 + /* disable writes to the SPROM */
260 + if (sprom_cmd_pcmcia(osh, SROM_WDS))
261 + return 1;
262 + } else {
263 + return 1;
264 + }
265 +
266 + bcm_mdelay(500);
267 + return 0;
268 +}
269 +
270 +
271 +int
272 +srom_parsecis(uint8 *cis, char **vars, int *count)
273 +{
274 + char eabuf[32];
275 + char *vp, *base;
276 + uint8 tup, tlen, sromrev = 1;
277 + int i, j;
278 + uint varsize;
279 + bool ag_init = FALSE;
280 + uint16 w;
281 +
282 + ASSERT(vars);
283 + ASSERT(count);
284 +
285 + base = vp = MALLOC(VARS_MAX);
286 + ASSERT(vp);
287 +
288 + i = 0;
289 + do {
290 + tup = cis[i++];
291 + tlen = cis[i++];
292 +
293 + switch (tup) {
294 + case CISTPL_MANFID:
295 + vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
296 + vp++;
297 + vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
298 + vp++;
299 + break;
300 +
301 + case CISTPL_FUNCE:
302 + if (cis[i] == LAN_NID) {
303 + ASSERT(cis[i + 1] == ETHER_ADDR_LEN);
304 + bcm_ether_ntoa((uchar*)&cis[i + 2], eabuf);
305 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
306 + vp++;
307 + }
308 + break;
309 +
310 + case CISTPL_CFTABLE:
311 + vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
312 + vp++;
313 + break;
314 +
315 + case CISTPL_BRCM_HNBU:
316 + switch (cis[i]) {
317 + case HNBU_CHIPID:
318 + vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) + cis[i + 1]);
319 + vp++;
320 + vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) + cis[i + 3]);
321 + vp++;
322 + if (tlen == 7) {
323 + vp += sprintf(vp, "chiprev=%d", (cis[i + 6] << 8) + cis[i + 5]);
324 + vp++;
325 + }
326 + break;
327 +
328 + case HNBU_BOARDREV:
329 + vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
330 + vp++;
331 + break;
332 +
333 + case HNBU_AA:
334 + vp += sprintf(vp, "aa0=%d", cis[i + 1]);
335 + vp++;
336 + break;
337 +
338 + case HNBU_AG:
339 + vp += sprintf(vp, "ag0=%d", cis[i + 1]);
340 + vp++;
341 + ag_init = TRUE;
342 + break;
343 +
344 + case HNBU_CC:
345 + vp += sprintf(vp, "cc=%d", cis[i + 1]);
346 + vp++;
347 + break;
348 +
349 + case HNBU_PAPARMS:
350 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + tlen - 1]);
351 + vp++;
352 + if (tlen == 9) {
353 + /* New version */
354 + for (j = 0; j < 3; j++) {
355 + vp += sprintf(vp, "pa0b%d=%d", j,
356 + (cis[i + (j * 2) + 2] << 8) + cis[i + (j * 2) + 1]);
357 + vp++;
358 + }
359 + vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
360 + vp++;
361 + }
362 + break;
363 +
364 + case HNBU_OEM:
365 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
366 + cis[i + 1], cis[i + 2], cis[i + 3], cis[i + 4],
367 + cis[i + 5], cis[i + 6], cis[i + 7], cis[i + 8]);
368 + vp++;
369 + break;
370 + case HNBU_BOARDFLAGS:
371 + w = (cis[i + 2] << 8) + cis[i + 1];
372 + if (w == 0xffff) w = 0;
373 + vp += sprintf(vp, "boardflags=%d", w);
374 + vp++;
375 + break;
376 + case HNBU_LED:
377 + if (cis[i + 1] != 0xff) {
378 + vp += sprintf(vp, "wl0gpio0=%d", cis[i + 1]);
379 + vp++;
380 + }
381 + if (cis[i + 2] != 0xff) {
382 + vp += sprintf(vp, "wl0gpio1=%d", cis[i + 2]);
383 + vp++;
384 + }
385 + if (cis[i + 3] != 0xff) {
386 + vp += sprintf(vp, "wl0gpio2=%d", cis[i + 3]);
387 + vp++;
388 + }
389 + if (cis[i + 4] != 0xff) {
390 + vp += sprintf(vp, "wl0gpio3=%d", cis[i + 4]);
391 + vp++;
392 + }
393 + break;
394 + }
395 + break;
396 +
397 + }
398 + i += tlen;
399 + } while (tup != 0xff);
400 +
401 + /* Set the srom version */
402 + vp += sprintf(vp, "sromrev=%d", sromrev);
403 + vp++;
404 +
405 + /* For now just set boardflags2 to zero */
406 + vp += sprintf(vp, "boardflags2=0");
407 + vp++;
408 +
409 + /* if there is no antenna gain field, set default */
410 + if (ag_init == FALSE) {
411 + vp += sprintf(vp, "ag0=%d", 0xff);
412 + vp++;
413 + }
414 +
415 + /* final nullbyte terminator */
416 + *vp++ = '\0';
417 + varsize = (uint)vp - (uint)base;
418 +
419 + ASSERT(varsize < VARS_MAX);
420 +
421 + if (varsize == VARS_MAX) {
422 + *vars = base;
423 + } else {
424 + vp = MALLOC(varsize);
425 + ASSERT(vp);
426 + bcopy(base, vp, varsize);
427 + MFREE(base, VARS_MAX);
428 + *vars = vp;
429 + }
430 + *count = varsize;
431 +
432 + return (0);
433 +}
434 +
435 +
436 +/* set PCMCIA sprom command register */
437 +static int
438 +sprom_cmd_pcmcia(void *osh, uint8 cmd)
439 +{
440 + uint8 status;
441 + uint wait_cnt = 1000;
442 +
443 + /* write sprom command register */
444 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
445 +
446 + /* wait status */
447 + while (wait_cnt--) {
448 + OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
449 + if (status & SROM_DONE)
450 + return 0;
451 + }
452 + return 1;
453 +}
454 +
455 +/* read a word from the PCMCIA srom */
456 +static int
457 +sprom_read_pcmcia(void *osh, uint16 addr, uint16 *data)
458 +{
459 + uint8 addr_l, addr_h, data_l, data_h;
460 +
461 + addr_l = (uint8)((addr * 2) & 0xff);
462 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
463 +
464 + /* set address */
465 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
466 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
467 +
468 + /* do read */
469 + if (sprom_cmd_pcmcia(osh, SROM_READ))
470 + return 1;
471 +
472 + /* read data */
473 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
474 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
475 +
476 + *data = (data_h << 8) | data_l;
477 + return 0;
478 +}
479 +
480 +/* write a word to the PCMCIA srom */
481 +static int
482 +sprom_write_pcmcia(void *osh, uint16 addr, uint16 data)
483 +{
484 + uint8 addr_l, addr_h, data_l, data_h;
485 +
486 + addr_l = (uint8)((addr * 2) & 0xff);
487 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
488 + data_l = (uint8)(data & 0xff);
489 + data_h = (uint8)((data >> 8) & 0xff);
490 +
491 + /* set address */
492 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
493 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
494 +
495 + /* write data */
496 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
497 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
498 +
499 + /* do write */
500 + return sprom_cmd_pcmcia(osh, SROM_WRITE);
501 +}
502 +
503 +/*
504 + * Read in and validate sprom.
505 + * Return 0 on success, nonzero on error.
506 + */
507 +static int
508 +sprom_read_pci(uint16 *sprom, uint byteoff, uint16 *buf, uint nbytes, bool check_crc)
509 +{
510 + int off, nw;
511 + uint8 chk8;
512 + int i;
513 +
514 + off = byteoff / 2;
515 + nw = ROUNDUP(nbytes, 2) / 2;
516 +
517 + /* read the sprom */
518 + for (i = 0; i < nw; i++)
519 + buf[i] = R_REG(&sprom[off + i]);
520 +
521 + if (check_crc) {
522 + /* fixup the endianness so crc8 will pass */
523 + htol16_buf(buf, nw * 2);
524 + if ((chk8 = crc8((uchar*)buf, nbytes, CRC8_INIT_VALUE)) != CRC8_GOOD_VALUE)
525 + return (1);
526 + /* now correct the endianness of the byte array */
527 + ltoh16_buf(buf, nw * 2);
528 + }
529 +
530 + return (0);
531 +}
532 +
533 +/*
534 + * Initialize nonvolatile variable table from sprom.
535 + * Return 0 on success, nonzero on error.
536 + */
537 +
538 +static int
539 +initvars_srom_pci(void *curmap, char **vars, int *count)
540 +{
541 + uint16 w, b[64];
542 + uint8 sromrev;
543 + struct ether_addr ea;
544 + char eabuf[32];
545 + int c, woff, i;
546 + char *vp, *base;
547 +
548 + if (sprom_read_pci((void *)((uint)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof (b), TRUE))
549 + return (-1);
550 +
551 + /* top word of sprom contains version and crc8 */
552 + sromrev = b[63] & 0xff;
553 + if ((sromrev != 1) && (sromrev != 2)) {
554 + return (-2);
555 + }
556 +
557 + ASSERT(vars);
558 + ASSERT(count);
559 +
560 + base = vp = MALLOC(VARS_MAX);
561 + ASSERT(vp);
562 +
563 + vp += sprintf(vp, "sromrev=%d", sromrev);
564 + vp++;
565 +
566 + if (sromrev >= 2) {
567 + /* New section takes over the 4th hardware function space */
568 +
569 + /* Word 28 is boardflags2 */
570 + vp += sprintf(vp, "boardflags2=%d", b[28]);
571 + vp++;
572 +
573 + /* Word 29 is max power 11a high/low */
574 + w = b[29];
575 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
576 + vp++;
577 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
578 + vp++;
579 +
580 + /* Words 30-32 set the 11alow pa settings,
581 + * 33-35 are the 11ahigh ones.
582 + */
583 + for (i = 0; i < 3; i++) {
584 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
585 + vp++;
586 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
587 + vp++;
588 + }
589 + w = b[59];
590 + if (w == 0)
591 + vp += sprintf(vp, "ccode=");
592 + else
593 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
594 + vp++;
595 +
596 + }
597 +
598 + /* parameter section of sprom starts at byte offset 72 */
599 + woff = 72/2;
600 +
601 + /* first 6 bytes are il0macaddr */
602 + ea.octet[0] = (b[woff] >> 8) & 0xff;
603 + ea.octet[1] = b[woff] & 0xff;
604 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
605 + ea.octet[3] = b[woff+1] & 0xff;
606 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
607 + ea.octet[5] = b[woff+2] & 0xff;
608 + woff += ETHER_ADDR_LEN/2 ;
609 + bcm_ether_ntoa((uchar*)&ea, eabuf);
610 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
611 + vp++;
612 +
613 + /* next 6 bytes are et0macaddr */
614 + ea.octet[0] = (b[woff] >> 8) & 0xff;
615 + ea.octet[1] = b[woff] & 0xff;
616 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
617 + ea.octet[3] = b[woff+1] & 0xff;
618 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
619 + ea.octet[5] = b[woff+2] & 0xff;
620 + woff += ETHER_ADDR_LEN/2 ;
621 + bcm_ether_ntoa((uchar*)&ea, eabuf);
622 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
623 + vp++;
624 +
625 + /* next 6 bytes are et1macaddr */
626 + ea.octet[0] = (b[woff] >> 8) & 0xff;
627 + ea.octet[1] = b[woff] & 0xff;
628 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
629 + ea.octet[3] = b[woff+1] & 0xff;
630 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
631 + ea.octet[5] = b[woff+2] & 0xff;
632 + woff += ETHER_ADDR_LEN/2 ;
633 + bcm_ether_ntoa((uchar*)&ea, eabuf);
634 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
635 + vp++;
636 +
637 + /*
638 + * Enet phy settings one or two singles or a dual
639 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
640 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
641 + * Bit 14 : Mdio for enet0
642 + * Bit 15 : Mdio for enet1
643 + */
644 + w = b[woff];
645 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
646 + vp++;
647 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
648 + vp++;
649 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
650 + vp++;
651 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
652 + vp++;
653 +
654 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
655 + w = b[46];
656 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
657 + vp++;
658 +
659 + if (sromrev > 1)
660 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
661 + else
662 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
663 + vp++;
664 +
665 + vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
666 + vp++;
667 +
668 + vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
669 + vp++;
670 +
671 + /* Words 47-49 set the (wl) pa settings */
672 + woff = 47;
673 +
674 + for (i = 0; i < 3; i++) {
675 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
676 + vp++;
677 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
678 + vp++;
679 + }
680 +
681 + /*
682 + * Words 50-51 set the customer-configured wl led behavior.
683 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
684 + * LED behavior values defined in wlioctl.h .
685 + */
686 + w = b[50];
687 + if ((w != 0) && (w != 0xffff)) {
688 + /* gpio0 */
689 + vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
690 + vp++;
691 +
692 + /* gpio1 */
693 + vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
694 + vp++;
695 + }
696 + w = b[51];
697 + if ((w != 0) && (w != 0xffff)) {
698 + /* gpio2 */
699 + vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
700 + vp++;
701 +
702 + /* gpio3 */
703 + vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
704 + vp++;
705 + }
706 +
707 + /* Word 52 is max power 0/1 */
708 + w = b[52];
709 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
710 + vp++;
711 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
712 + vp++;
713 +
714 + /* Word 56 is idle tssi target 0/1 */
715 + w = b[56];
716 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
717 + vp++;
718 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
719 + vp++;
720 +
721 + /* Word 57 is boardflags, if not programmed make it zero */
722 + w = b[57];
723 + if (w == 0xffff) w = 0;
724 + vp += sprintf(vp, "boardflags=%d", w);
725 + vp++;
726 +
727 + /* Word 58 is antenna gain 0/1 */
728 + w = b[58];
729 + vp += sprintf(vp, "ag0=%d", w & 0xff);
730 + vp++;
731 +
732 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
733 + vp++;
734 +
735 + if (sromrev == 1) {
736 + /* set the oem string */
737 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
738 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
739 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
740 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
741 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
742 + vp++;
743 + }
744 +
745 + /* final nullbyte terminator */
746 + *vp++ = '\0';
747 +
748 + c = vp - base;
749 + ASSERT(c <= VARS_MAX);
750 +
751 + if (c == VARS_MAX) {
752 + *vars = base;
753 + } else {
754 + vp = MALLOC(c);
755 + ASSERT(vp);
756 + bcopy(base, vp, c);
757 + MFREE(base, VARS_MAX);
758 + *vars = vp;
759 + }
760 + *count = c;
761 +
762 + return (0);
763 +}
764 +
765 +/*
766 + * Read the cis and call parsecis to initialize the vars.
767 + * Return 0 on success, nonzero on error.
768 + */
769 +static int
770 +initvars_cis_pcmcia(void *osh, char **vars, int *count)
771 +{
772 + uint8 *cis = NULL;
773 + int rc;
774 +
775 + if ((cis = MALLOC(CIS_SIZE)) == NULL)
776 + return (-1);
777 +
778 + OSL_PCMCIA_READ_ATTR(osh, 0, cis, CIS_SIZE);
779 +
780 + rc = srom_parsecis(cis, vars, count);
781 +
782 + MFREE(cis, CIS_SIZE);
783 +
784 + return (rc);
785 +}
786 +
787 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/broadcom/bcmutils.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/bcmutils.c
788 --- linux-2.6.12.5/arch/mips/bcm947xx/broadcom/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
789 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/bcmutils.c 2005-08-28 11:12:20.428859456 +0200
790 @@ -0,0 +1,691 @@
791 +/*
792 + * Misc useful OS-independent routines.
793 + *
794 + * Copyright 2001-2003, Broadcom Corporation
795 + * All Rights Reserved.
796 + *
797 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
798 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
799 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
800 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
801 + * $Id: bcmutils.c,v 1.1 2005/02/28 13:33:32 jolt Exp $
802 + */
803 +
804 +#include <typedefs.h>
805 +#include <osl.h>
806 +#include <bcmutils.h>
807 +#include <bcmendian.h>
808 +#include <bcmnvram.h>
809 +
810 +unsigned char bcm_ctype[] = {
811 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
812 + _BCM_C,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C,_BCM_C, /* 8-15 */
813 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
814 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
815 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
816 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
817 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
818 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
819 + _BCM_P,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U, /* 64-71 */
820 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
821 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
822 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
823 + _BCM_P,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L, /* 96-103 */
824 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
825 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
826 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
827 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
828 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
829 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 160-175 */
830 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 176-191 */
831 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 192-207 */
832 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_L, /* 208-223 */
833 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 224-239 */
834 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L /* 240-255 */
835 +};
836 +
837 +uchar
838 +bcm_toupper(uchar c)
839 +{
840 + if (bcm_islower(c))
841 + c -= 'a'-'A';
842 + return (c);
843 +}
844 +
845 +ulong
846 +bcm_strtoul(char *cp, char **endp, uint base)
847 +{
848 + ulong result, value;
849 + bool minus;
850 +
851 + minus = FALSE;
852 +
853 + while (bcm_isspace(*cp))
854 + cp++;
855 +
856 + if (cp[0] == '+')
857 + cp++;
858 + else if (cp[0] == '-') {
859 + minus = TRUE;
860 + cp++;
861 + }
862 +
863 + if (base == 0) {
864 + if (cp[0] == '0') {
865 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
866 + base = 16;
867 + cp = &cp[2];
868 + } else {
869 + base = 8;
870 + cp = &cp[1];
871 + }
872 + } else
873 + base = 10;
874 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
875 + cp = &cp[2];
876 + }
877 +
878 + result = 0;
879 +
880 + while (bcm_isxdigit(*cp) &&
881 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
882 + result = result*base + value;
883 + cp++;
884 + }
885 +
886 + if (minus)
887 + result = (ulong)(result * -1);
888 +
889 + if (endp)
890 + *endp = (char *)cp;
891 +
892 + return (result);
893 +}
894 +
895 +uint
896 +bcm_atoi(char *s)
897 +{
898 + uint n;
899 +
900 + n = 0;
901 +
902 + while (bcm_isdigit(*s))
903 + n = (n * 10) + *s++ - '0';
904 + return (n);
905 +}
906 +
907 +void
908 +deadbeef(char *p, uint len)
909 +{
910 + static uchar meat[] = { 0xde, 0xad, 0xbe, 0xef };
911 +
912 + while (len-- > 0) {
913 + *p = meat[((uint)p) & 3];
914 + p++;
915 + }
916 +}
917 +
918 +/* pretty hex print a contiguous buffer */
919 +void
920 +prhex(char *msg, uchar *buf, uint nbytes)
921 +{
922 + char line[256];
923 + char* p;
924 + uint i;
925 +
926 + if (msg && (msg[0] != '\0'))
927 + printf("%s: ", msg);
928 +
929 + p = line;
930 + for (i = 0; i < nbytes; i++) {
931 + if (i % 16 == 0) {
932 + p += sprintf(p, "%04d: ", i); /* line prefix */
933 + }
934 + p += sprintf(p, "%02x ", buf[i]);
935 + if (i % 16 == 15) {
936 + printf("%s\n", line); /* flush line */
937 + p = line;
938 + }
939 + }
940 +
941 + /* flush last partial line */
942 + if (p != line)
943 + printf("%s\n", line);
944 +}
945 +
946 +/* pretty hex print a pkt buffer chain */
947 +void
948 +prpkt(char *msg, void *drv, void *p0)
949 +{
950 + void *p;
951 +
952 + if (msg && (msg[0] != '\0'))
953 + printf("%s: ", msg);
954 +
955 + for (p = p0; p; p = PKTNEXT(drv, p))
956 + prhex(NULL, PKTDATA(drv, p), PKTLEN(drv, p));
957 +}
958 +
959 +/* copy a pkt buffer chain into a buffer */
960 +uint
961 +pktcopy(void *drv, void *p, uint offset, int len, uchar *buf)
962 +{
963 + uint n, ret = 0;
964 +
965 + if (len < 0)
966 + len = 4096; /* "infinite" */
967 +
968 + /* skip 'offset' bytes */
969 + for (; p && offset; p = PKTNEXT(drv, p)) {
970 + if (offset < (uint)PKTLEN(drv, p))
971 + break;
972 + offset -= PKTLEN(drv, p);
973 + }
974 +
975 + if (!p)
976 + return 0;
977 +
978 + /* copy the data */
979 + for (; p && len; p = PKTNEXT(drv, p)) {
980 + n = MIN((uint)PKTLEN(drv, p) - offset, (uint)len);
981 + bcopy(PKTDATA(drv, p) + offset, buf, n);
982 + buf += n;
983 + len -= n;
984 + ret += n;
985 + offset = 0;
986 + }
987 +
988 + return ret;
989 +}
990 +
991 +/* return total length of buffer chain */
992 +uint
993 +pkttotlen(void *drv, void *p)
994 +{
995 + uint total;
996 +
997 + total = 0;
998 + for (; p; p = PKTNEXT(drv, p))
999 + total += PKTLEN(drv, p);
1000 + return (total);
1001 +}
1002 +
1003 +
1004 +uchar*
1005 +bcm_ether_ntoa(char *ea, char *buf)
1006 +{
1007 + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
1008 + (uchar)ea[0]&0xff, (uchar)ea[1]&0xff, (uchar)ea[2]&0xff,
1009 + (uchar)ea[3]&0xff, (uchar)ea[4]&0xff, (uchar)ea[5]&0xff);
1010 + return (buf);
1011 +}
1012 +
1013 +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
1014 +int
1015 +bcm_ether_atoe(char *p, char *ea)
1016 +{
1017 + int i = 0;
1018 +
1019 + for (;;) {
1020 + ea[i++] = (char) bcm_strtoul(p, &p, 16);
1021 + if (!*p++ || i == 6)
1022 + break;
1023 + }
1024 +
1025 + return (i == 6);
1026 +}
1027 +
1028 +/*
1029 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
1030 + * triples, returning a pointer to the substring whose first element
1031 + * matches tag. Stop parsing when we see an element whose ID is greater
1032 + * than the target key.
1033 + */
1034 +bcm_tlv_t *
1035 +bcm_parse_ordered_tlvs(void *buf, int buflen, uint key)
1036 +{
1037 + bcm_tlv_t *elt;
1038 + int totlen;
1039 +
1040 + elt = (bcm_tlv_t*)buf;
1041 + totlen = buflen;
1042 +
1043 + /* find tagged parameter */
1044 + while (totlen >= 2) {
1045 + uint id = elt->id;
1046 + int len = elt->len;
1047 +
1048 + /* Punt if we start seeing IDs > than target key */
1049 + if (id > key)
1050 + return(NULL);
1051 +
1052 + /* validate remaining totlen */
1053 + if ((id == key) && (totlen >= (len + 2)))
1054 + return (elt);
1055 +
1056 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
1057 + totlen -= (len + 2);
1058 + }
1059 + return NULL;
1060 +}
1061 +
1062 +
1063 +/*
1064 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
1065 + * triples, returning a pointer to the substring whose first element
1066 + * matches tag
1067 + */
1068 +bcm_tlv_t *
1069 +bcm_parse_tlvs(void *buf, int buflen, uint key)
1070 +{
1071 + bcm_tlv_t *elt;
1072 + int totlen;
1073 +
1074 + elt = (bcm_tlv_t*)buf;
1075 + totlen = buflen;
1076 +
1077 + /* find tagged parameter */
1078 + while (totlen >= 2) {
1079 + int len = elt->len;
1080 +
1081 + /* validate remaining totlen */
1082 + if ((elt->id == key) && (totlen >= (len + 2)))
1083 + return (elt);
1084 +
1085 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
1086 + totlen -= (len + 2);
1087 + }
1088 +
1089 + return NULL;
1090 +}
1091 +
1092 +void
1093 +pktqinit(struct pktq *q, int maxlen)
1094 +{
1095 + q->head = q->tail = NULL;
1096 + q->maxlen = maxlen;
1097 + q->len = 0;
1098 +}
1099 +
1100 +void
1101 +pktenq(struct pktq *q, void *p, bool lifo)
1102 +{
1103 + ASSERT(PKTLINK(p) == NULL);
1104 +
1105 + PKTSETLINK(p, NULL);
1106 +
1107 + if (q->tail == NULL) {
1108 + ASSERT(q->head == NULL);
1109 + q->head = q->tail = p;
1110 + }
1111 + else {
1112 + ASSERT(q->head);
1113 + ASSERT(PKTLINK(q->tail) == NULL);
1114 + if (lifo) {
1115 + PKTSETLINK(p, q->head);
1116 + q->head = p;
1117 + } else {
1118 + PKTSETLINK(q->tail, p);
1119 + q->tail = p;
1120 + }
1121 + }
1122 + q->len++;
1123 +}
1124 +
1125 +void*
1126 +pktdeq(struct pktq *q)
1127 +{
1128 + void *p;
1129 +
1130 + if ((p = q->head)) {
1131 + ASSERT(q->tail);
1132 + q->head = PKTLINK(p);
1133 + PKTSETLINK(p, NULL);
1134 + q->len--;
1135 + if (q->head == NULL)
1136 + q->tail = NULL;
1137 + }
1138 + else {
1139 + ASSERT(q->tail == NULL);
1140 + }
1141 +
1142 + return (p);
1143 +}
1144 +
1145 +/*******************************************************************************
1146 + * crc8
1147 + *
1148 + * Computes a crc8 over the input data using the polynomial:
1149 + *
1150 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
1151 + *
1152 + * The caller provides the initial value (either CRC8_INIT_VALUE
1153 + * or the previous returned value) to allow for processing of
1154 + * discontiguous blocks of data. When generating the CRC the
1155 + * caller is responsible for complementing the final return value
1156 + * and inserting it into the byte stream. When checking, a final
1157 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
1158 + *
1159 + * Reference: Dallas Semiconductor Application Note 27
1160 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
1161 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
1162 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
1163 + *
1164 + ******************************************************************************/
1165 +
1166 +static uint8 crc8_table[256] = {
1167 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
1168 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
1169 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
1170 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
1171 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
1172 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
1173 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
1174 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
1175 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
1176 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
1177 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
1178 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
1179 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
1180 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
1181 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
1182 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
1183 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
1184 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
1185 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
1186 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
1187 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
1188 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
1189 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
1190 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
1191 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
1192 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
1193 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
1194 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
1195 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
1196 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
1197 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
1198 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
1199 +};
1200 +
1201 +/*
1202 + * Search the name=value vars for a specific one and return its value.
1203 + * Returns NULL if not found.
1204 + */
1205 +char*
1206 +getvar(char *vars, char *name)
1207 +{
1208 + char *s;
1209 + int len;
1210 +
1211 + len = strlen(name);
1212 +
1213 + /* first look in vars[] */
1214 + for (s = vars; s && *s; ) {
1215 + if ((bcmp(s, name, len) == 0) && (s[len] == '='))
1216 + return (&s[len+1]);
1217 +
1218 + while (*s++)
1219 + ;
1220 + }
1221 +
1222 + /* then query nvram */
1223 + return (nvram_get(name));
1224 +}
1225 +
1226 +/*
1227 + * Search the vars for a specific one and return its value as
1228 + * an integer. Returns 0 if not found.
1229 + */
1230 +int
1231 +getintvar(char *vars, char *name)
1232 +{
1233 + char *val;
1234 +
1235 + if ((val = getvar(vars, name)) == NULL)
1236 + return (0);
1237 +
1238 + return (bcm_strtoul(val, NULL, 0));
1239 +}
1240 +
1241 +void
1242 +bcm_mdelay(uint ms)
1243 +{
1244 + uint i;
1245 +
1246 + for (i = 0; i < ms; i++) {
1247 + OSL_DELAY(1000);
1248 + }
1249 +}
1250 +
1251 +#define CRC_INNER_LOOP(n, c, x) \
1252 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
1253 +
1254 +uint8
1255 +crc8(
1256 + uint8 *pdata, /* pointer to array of data to process */
1257 + uint nbytes, /* number of input data bytes to process */
1258 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
1259 +)
1260 +{
1261 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
1262 + * to avoid the undefined and unnecessary (uint8 >> 8) operation. */
1263 + while (nbytes-- > 0)
1264 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
1265 +
1266 + return crc;
1267 +}
1268 +
1269 +/*******************************************************************************
1270 + * crc16
1271 + *
1272 + * Computes a crc16 over the input data using the polynomial:
1273 + *
1274 + * x^16 + x^12 +x^5 + 1
1275 + *
1276 + * The caller provides the initial value (either CRC16_INIT_VALUE
1277 + * or the previous returned value) to allow for processing of
1278 + * discontiguous blocks of data. When generating the CRC the
1279 + * caller is responsible for complementing the final return value
1280 + * and inserting it into the byte stream. When checking, a final
1281 + * return value of CRC16_GOOD_VALUE indicates a valid CRC.
1282 + *
1283 + * Reference: Dallas Semiconductor Application Note 27
1284 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
1285 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
1286 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
1287 + *
1288 + ******************************************************************************/
1289 +
1290 +static uint16 crc16_table[256] = {
1291 + 0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF,
1292 + 0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7,
1293 + 0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E,
1294 + 0x9CC9, 0x8D40, 0xBFDB, 0xAE52, 0xDAED, 0xCB64, 0xF9FF, 0xE876,
1295 + 0x2102, 0x308B, 0x0210, 0x1399, 0x6726, 0x76AF, 0x4434, 0x55BD,
1296 + 0xAD4A, 0xBCC3, 0x8E58, 0x9FD1, 0xEB6E, 0xFAE7, 0xC87C, 0xD9F5,
1297 + 0x3183, 0x200A, 0x1291, 0x0318, 0x77A7, 0x662E, 0x54B5, 0x453C,
1298 + 0xBDCB, 0xAC42, 0x9ED9, 0x8F50, 0xFBEF, 0xEA66, 0xD8FD, 0xC974,
1299 + 0x4204, 0x538D, 0x6116, 0x709F, 0x0420, 0x15A9, 0x2732, 0x36BB,
1300 + 0xCE4C, 0xDFC5, 0xED5E, 0xFCD7, 0x8868, 0x99E1, 0xAB7A, 0xBAF3,
1301 + 0x5285, 0x430C, 0x7197, 0x601E, 0x14A1, 0x0528, 0x37B3, 0x263A,
1302 + 0xDECD, 0xCF44, 0xFDDF, 0xEC56, 0x98E9, 0x8960, 0xBBFB, 0xAA72,
1303 + 0x6306, 0x728F, 0x4014, 0x519D, 0x2522, 0x34AB, 0x0630, 0x17B9,
1304 + 0xEF4E, 0xFEC7, 0xCC5C, 0xDDD5, 0xA96A, 0xB8E3, 0x8A78, 0x9BF1,
1305 + 0x7387, 0x620E, 0x5095, 0x411C, 0x35A3, 0x242A, 0x16B1, 0x0738,
1306 + 0xFFCF, 0xEE46, 0xDCDD, 0xCD54, 0xB9EB, 0xA862, 0x9AF9, 0x8B70,
1307 + 0x8408, 0x9581, 0xA71A, 0xB693, 0xC22C, 0xD3A5, 0xE13E, 0xF0B7,
1308 + 0x0840, 0x19C9, 0x2B52, 0x3ADB, 0x4E64, 0x5FED, 0x6D76, 0x7CFF,
1309 + 0x9489, 0x8500, 0xB79B, 0xA612, 0xD2AD, 0xC324, 0xF1BF, 0xE036,
1310 + 0x18C1, 0x0948, 0x3BD3, 0x2A5A, 0x5EE5, 0x4F6C, 0x7DF7, 0x6C7E,
1311 + 0xA50A, 0xB483, 0x8618, 0x9791, 0xE32E, 0xF2A7, 0xC03C, 0xD1B5,
1312 + 0x2942, 0x38CB, 0x0A50, 0x1BD9, 0x6F66, 0x7EEF, 0x4C74, 0x5DFD,
1313 + 0xB58B, 0xA402, 0x9699, 0x8710, 0xF3AF, 0xE226, 0xD0BD, 0xC134,
1314 + 0x39C3, 0x284A, 0x1AD1, 0x0B58, 0x7FE7, 0x6E6E, 0x5CF5, 0x4D7C,
1315 + 0xC60C, 0xD785, 0xE51E, 0xF497, 0x8028, 0x91A1, 0xA33A, 0xB2B3,
1316 + 0x4A44, 0x5BCD, 0x6956, 0x78DF, 0x0C60, 0x1DE9, 0x2F72, 0x3EFB,
1317 + 0xD68D, 0xC704, 0xF59F, 0xE416, 0x90A9, 0x8120, 0xB3BB, 0xA232,
1318 + 0x5AC5, 0x4B4C, 0x79D7, 0x685E, 0x1CE1, 0x0D68, 0x3FF3, 0x2E7A,
1319 + 0xE70E, 0xF687, 0xC41C, 0xD595, 0xA12A, 0xB0A3, 0x8238, 0x93B1,
1320 + 0x6B46, 0x7ACF, 0x4854, 0x59DD, 0x2D62, 0x3CEB, 0x0E70, 0x1FF9,
1321 + 0xF78F, 0xE606, 0xD49D, 0xC514, 0xB1AB, 0xA022, 0x92B9, 0x8330,
1322 + 0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78
1323 +};
1324 +
1325 +uint16
1326 +crc16(
1327 + uint8 *pdata, /* pointer to array of data to process */
1328 + uint nbytes, /* number of input data bytes to process */
1329 + uint16 crc /* either CRC16_INIT_VALUE or previous return value */
1330 +)
1331 +{
1332 + while (nbytes-- > 0)
1333 + CRC_INNER_LOOP(16, crc, *pdata++);
1334 + return crc;
1335 +}
1336 +
1337 +static uint32 crc32_table[256] = {
1338 + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
1339 + 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
1340 + 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
1341 + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
1342 + 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
1343 + 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
1344 + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
1345 + 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
1346 + 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
1347 + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
1348 + 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
1349 + 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
1350 + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
1351 + 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
1352 + 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
1353 + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
1354 + 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
1355 + 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
1356 + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
1357 + 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
1358 + 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
1359 + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
1360 + 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
1361 + 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
1362 + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
1363 + 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
1364 + 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
1365 + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
1366 + 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
1367 + 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
1368 + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
1369 + 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
1370 + 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
1371 + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
1372 + 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
1373 + 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
1374 + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
1375 + 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
1376 + 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
1377 + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
1378 + 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
1379 + 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
1380 + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
1381 + 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
1382 + 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
1383 + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
1384 + 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
1385 + 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
1386 + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
1387 + 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
1388 + 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
1389 + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
1390 + 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
1391 + 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
1392 + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
1393 + 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
1394 + 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
1395 + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
1396 + 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
1397 + 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
1398 + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
1399 + 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
1400 + 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
1401 + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
1402 +};
1403 +
1404 +uint32
1405 +crc32(
1406 + uint8 *pdata, /* pointer to array of data to process */
1407 + uint nbytes, /* number of input data bytes to process */
1408 + uint32 crc /* either CRC32_INIT_VALUE or previous return value */
1409 +)
1410 +{
1411 + uint8 *pend;
1412 +#ifdef __mips__
1413 + uint8 tmp[4];
1414 + ulong *tptr = (ulong *)tmp;
1415 +
1416 + /* in case the beginning of the buffer isn't aligned */
1417 + pend = (uint8 *)((uint)(pdata + 3) & 0xfffffffc);
1418 + nbytes -= (pend - pdata);
1419 + while (pdata < pend)
1420 + CRC_INNER_LOOP(32, crc, *pdata++);
1421 +
1422 + /* handle bulk of data as 32-bit words */
1423 + pend = pdata + (nbytes & 0xfffffffc);
1424 + while (pdata < pend) {
1425 + *tptr = *((ulong *)pdata)++;
1426 + CRC_INNER_LOOP(32, crc, tmp[0]);
1427 + CRC_INNER_LOOP(32, crc, tmp[1]);
1428 + CRC_INNER_LOOP(32, crc, tmp[2]);
1429 + CRC_INNER_LOOP(32, crc, tmp[3]);
1430 + }
1431 +
1432 + /* 1-3 bytes at end of buffer */
1433 + pend = pdata + (nbytes & 0x03);
1434 + while (pdata < pend)
1435 + CRC_INNER_LOOP(32, crc, *pdata++);
1436 +#else
1437 + pend = pdata + nbytes;
1438 + while (pdata < pend)
1439 + CRC_INNER_LOOP(32, crc, *pdata++);
1440 +#endif
1441 +
1442 + return crc;
1443 +}
1444 +
1445 +#ifdef notdef
1446 +#define CLEN 1499
1447 +#define CBUFSIZ (CLEN+4)
1448 +#define CNBUFS 5
1449 +
1450 +void testcrc32(void)
1451 +{
1452 + uint j,k,l;
1453 + uint8 *buf;
1454 + uint len[CNBUFS];
1455 + uint32 crcr;
1456 + uint32 crc32tv[CNBUFS] =
1457 + {0xd2cb1faa, 0xd385c8fa, 0xf5b4f3f3, 0x55789e20, 0x00343110};
1458 +
1459 + ASSERT((buf = MALLOC(CBUFSIZ*CNBUFS)) != NULL);
1460 +
1461 + /* step through all possible alignments */
1462 + for (l=0;l<=4;l++) {
1463 + for (j=0; j<CNBUFS; j++) {
1464 + len[j] = CLEN;
1465 + for (k=0; k<len[j]; k++)
1466 + *(buf + j*CBUFSIZ + (k+l)) = (j+k) & 0xff;
1467 + }
1468 +
1469 + for (j=0; j<CNBUFS; j++) {
1470 + crcr = crc32(buf + j*CBUFSIZ + l, len[j], CRC32_INIT_VALUE);
1471 + ASSERT(crcr == crc32tv[j]);
1472 + }
1473 + }
1474 +
1475 + MFREE(buf, CBUFSIZ*CNBUFS);
1476 + return;
1477 +}
1478 +#endif
1479 +
1480 +
1481 +
1482 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/broadcom/hnddma.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/hnddma.c
1483 --- linux-2.6.12.5/arch/mips/bcm947xx/broadcom/hnddma.c 1970-01-01 01:00:00.000000000 +0100
1484 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/hnddma.c 2005-08-28 11:12:20.430859152 +0200
1485 @@ -0,0 +1,763 @@
1486 +/*
1487 + * Generic Broadcom Home Networking Division (HND) DMA module.
1488 + * This supports the following chips: BCM42xx, 44xx, 47xx .
1489 + *
1490 + * Copyright 2001-2003, Broadcom Corporation
1491 + * All Rights Reserved.
1492 + *
1493 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1494 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1495 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1496 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1497 + *
1498 + * $Id: hnddma.c,v 1.1 2005/02/28 13:33:32 jolt Exp $
1499 + */
1500 +
1501 +#include <typedefs.h>
1502 +#include <osl.h>
1503 +#include <bcmendian.h>
1504 +#include <bcmutils.h>
1505 +
1506 +struct dma_info; /* forward declaration */
1507 +#define di_t struct dma_info
1508 +#include <hnddma.h>
1509 +
1510 +/* debug/trace */
1511 +#define DMA_ERROR(args)
1512 +#define DMA_TRACE(args)
1513 +
1514 +/* default dma message level(if input msg_level pointer is null in dma_attach()) */
1515 +static uint dma_msg_level = 0;
1516 +
1517 +#define MAXNAMEL 8
1518 +#define MAXDD (DMAMAXRINGSZ / sizeof (dmadd_t))
1519 +
1520 +/* dma engine software state */
1521 +typedef struct dma_info {
1522 + hnddma_t hnddma; /* exported structure */
1523 + uint *msg_level; /* message level pointer */
1524 +
1525 + char name[MAXNAMEL]; /* callers name for diag msgs */
1526 + void *drv; /* driver handle */
1527 + void *dev; /* device handle */
1528 + dmaregs_t *regs; /* dma engine registers */
1529 +
1530 + dmadd_t *txd; /* pointer to chip-specific tx descriptor ring */
1531 + uint txin; /* index of next descriptor to reclaim */
1532 + uint txout; /* index of next descriptor to post */
1533 + uint txavail; /* # free tx descriptors */
1534 + void *txp[MAXDD]; /* parallel array of pointers to packets */
1535 + ulong txdpa; /* physical address of descriptor ring */
1536 + uint txdalign; /* #bytes added to alloc'd mem to align txd */
1537 +
1538 + dmadd_t *rxd; /* pointer to chip-specific rx descriptor ring */
1539 + uint rxin; /* index of next descriptor to reclaim */
1540 + uint rxout; /* index of next descriptor to post */
1541 + void *rxp[MAXDD]; /* parallel array of pointers to packets */
1542 + ulong rxdpa; /* physical address of descriptor ring */
1543 + uint rxdalign; /* #bytes added to alloc'd mem to align rxd */
1544 +
1545 + /* tunables */
1546 + uint ntxd; /* # tx descriptors */
1547 + uint nrxd; /* # rx descriptors */
1548 + uint rxbufsize; /* rx buffer size in bytes */
1549 + uint nrxpost; /* # rx buffers to keep posted */
1550 + uint rxoffset; /* rxcontrol offset */
1551 + uint ddoffset; /* add to get dma address of descriptor ring */
1552 + uint dataoffset; /* add to get dma address of data buffer */
1553 +} dma_info_t;
1554 +
1555 +/* descriptor bumping macros */
1556 +#define NEXTTXD(i) ((i + 1) & (di->ntxd - 1))
1557 +#define PREVTXD(i) ((i - 1) & (di->ntxd - 1))
1558 +#define NEXTRXD(i) ((i + 1) & (di->nrxd - 1))
1559 +#define NTXDACTIVE(h, t) ((t - h) & (di->ntxd - 1))
1560 +#define NRXDACTIVE(h, t) ((t - h) & (di->nrxd - 1))
1561 +
1562 +/* macros to convert between byte offsets and indexes */
1563 +#define B2I(bytes) ((bytes) / sizeof (dmadd_t))
1564 +#define I2B(index) ((index) * sizeof (dmadd_t))
1565 +
1566 +void*
1567 +dma_attach(void *drv, void *dev, char *name, dmaregs_t *regs, uint ntxd, uint nrxd,
1568 + uint rxbufsize, uint nrxpost, uint rxoffset, uint ddoffset, uint dataoffset, uint *msg_level)
1569 +{
1570 + dma_info_t *di;
1571 + void *va;
1572 +
1573 + ASSERT(ntxd <= MAXDD);
1574 + ASSERT(nrxd <= MAXDD);
1575 +
1576 + /* allocate private info structure */
1577 + if ((di = MALLOC(sizeof (dma_info_t))) == NULL)
1578 + return (NULL);
1579 + bzero((char*)di, sizeof (dma_info_t));
1580 +
1581 + /* set message level */
1582 + di->msg_level = msg_level ? msg_level : &dma_msg_level;
1583 +
1584 + DMA_TRACE(("%s: dma_attach: drv 0x%x dev 0x%x regs 0x%x ntxd %d nrxd %d rxbufsize %d nrxpost %d rxoffset %d ddoffset 0x%x dataoffset 0x%x\n", name, (uint)drv, (uint)dev, (uint)regs, ntxd, nrxd, rxbufsize, nrxpost, rxoffset, ddoffset, dataoffset));
1585 +
1586 + /* make a private copy of our callers name */
1587 + strncpy(di->name, name, MAXNAMEL);
1588 + di->name[MAXNAMEL-1] = '\0';
1589 +
1590 + di->drv = drv;
1591 + di->dev = dev;
1592 + di->regs = regs;
1593 +
1594 + /* allocate transmit descriptor ring */
1595 + if (ntxd) {
1596 + if ((va = DMA_ALLOC_CONSISTENT(dev, (DMAMAXRINGSZ + DMARINGALIGN), &di->txdpa)) == NULL)
1597 + goto fail;
1598 + di->txd = (dmadd_t*) ROUNDUP(va, DMARINGALIGN);
1599 + di->txdalign = ((uint)di->txd - (uint)va);
1600 + di->txdpa = di->txdpa + di->txdalign;
1601 + ASSERT(ISALIGNED(di->txd, DMARINGALIGN));
1602 + }
1603 +
1604 + /* allocate receive descriptor ring */
1605 + if (nrxd) {
1606 + if ((va = DMA_ALLOC_CONSISTENT(dev, (DMAMAXRINGSZ + DMARINGALIGN), &di->rxdpa)) == NULL)
1607 + goto fail;
1608 + di->rxd = (dmadd_t*) ROUNDUP(va, DMARINGALIGN);
1609 + di->rxdalign = ((uint)di->rxd - (uint)va);
1610 + di->rxdpa = di->rxdpa + di->rxdalign;
1611 + ASSERT(ISALIGNED(di->rxd, DMARINGALIGN));
1612 + }
1613 +
1614 + /* save tunables */
1615 + di->ntxd = ntxd;
1616 + di->nrxd = nrxd;
1617 + di->rxbufsize = rxbufsize;
1618 + di->nrxpost = nrxpost;
1619 + di->rxoffset = rxoffset;
1620 + di->ddoffset = ddoffset;
1621 + di->dataoffset = dataoffset;
1622 +
1623 + return ((void*)di);
1624 +
1625 +fail:
1626 + dma_detach((void*)di);
1627 + return (NULL);
1628 +}
1629 +
1630 +/* may be called with core in reset */
1631 +void
1632 +dma_detach(dma_info_t *di)
1633 +{
1634 + if (di == NULL)
1635 + return;
1636 +
1637 + DMA_TRACE(("%s: dma_detach\n", di->name));
1638 +
1639 + /* shouldn't be here if descriptors are unreclaimed */
1640 + ASSERT(di->txin == di->txout);
1641 + ASSERT(di->rxin == di->rxout);
1642 +
1643 + /* free dma descriptor rings */
1644 + if (di->txd)
1645 + DMA_FREE_CONSISTENT(di->dev, (void *)((uint)di->txd - di->txdalign), (DMAMAXRINGSZ + DMARINGALIGN), di->txdpa);
1646 + if (di->rxd)
1647 + DMA_FREE_CONSISTENT(di->dev, (void *)((uint)di->rxd - di->rxdalign), (DMAMAXRINGSZ + DMARINGALIGN), di->rxdpa);
1648 +
1649 + /* free our private info structure */
1650 + MFREE((void*)di, sizeof (dma_info_t));
1651 +}
1652 +
1653 +
1654 +void
1655 +dma_txreset(dma_info_t *di)
1656 +{
1657 + uint32 status;
1658 +
1659 + DMA_TRACE(("%s: dma_txreset\n", di->name));
1660 +
1661 + /* suspend tx DMA first */
1662 + W_REG(&di->regs->xmtcontrol, XC_SE);
1663 + SPINWAIT((status = (R_REG(&di->regs->xmtstatus) & XS_XS_MASK)) != XS_XS_DISABLED &&
1664 + status != XS_XS_IDLE &&
1665 + status != XS_XS_STOPPED,
1666 + 10000);
1667 +
1668 + W_REG(&di->regs->xmtcontrol, 0);
1669 + SPINWAIT((status = (R_REG(&di->regs->xmtstatus) & XS_XS_MASK)) != XS_XS_DISABLED,
1670 + 10000);
1671 +
1672 + if (status != XS_XS_DISABLED) {
1673 + DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
1674 + }
1675 +
1676 + /* wait for the last transaction to complete */
1677 + OSL_DELAY(300);
1678 +}
1679 +
1680 +void
1681 +dma_rxreset(dma_info_t *di)
1682 +{
1683 + uint32 status;
1684 +
1685 + DMA_TRACE(("%s: dma_rxreset\n", di->name));
1686 +
1687 + W_REG(&di->regs->rcvcontrol, 0);
1688 + SPINWAIT((status = (R_REG(&di->regs->rcvstatus) & RS_RS_MASK)) != RS_RS_DISABLED,
1689 + 10000);
1690 +
1691 + if (status != RS_RS_DISABLED) {
1692 + DMA_ERROR(("%s: dma_rxreset: dma cannot be stopped\n", di->name));
1693 + }
1694 +}
1695 +
1696 +void
1697 +dma_txinit(dma_info_t *di)
1698 +{
1699 + DMA_TRACE(("%s: dma_txinit\n", di->name));
1700 +
1701 + di->txin = di->txout = 0;
1702 + di->txavail = di->ntxd - 1;
1703 +
1704 + /* clear tx descriptor ring */
1705 + BZERO_SM((void*)di->txd, (di->ntxd * sizeof (dmadd_t)));
1706 +
1707 + W_REG(&di->regs->xmtcontrol, XC_XE);
1708 + W_REG(&di->regs->xmtaddr, (di->txdpa + di->ddoffset));
1709 +}
1710 +
1711 +bool
1712 +dma_txenabled(dma_info_t *di)
1713 +{
1714 + uint32 xc;
1715 +
1716 + /* If the chip is dead, it is not enabled :-) */
1717 + xc = R_REG(&di->regs->xmtcontrol);
1718 + return ((xc != 0xffffffff) && (xc & XC_XE));
1719 +}
1720 +
1721 +void
1722 +dma_txsuspend(dma_info_t *di)
1723 +{
1724 + DMA_TRACE(("%s: dma_txsuspend\n", di->name));
1725 + OR_REG(&di->regs->xmtcontrol, XC_SE);
1726 +}
1727 +
1728 +void
1729 +dma_txresume(dma_info_t *di)
1730 +{
1731 + DMA_TRACE(("%s: dma_txresume\n", di->name));
1732 + AND_REG(&di->regs->xmtcontrol, ~XC_SE);
1733 +}
1734 +
1735 +bool
1736 +dma_txsuspended(dma_info_t *di)
1737 +{
1738 + uint32 xc;
1739 + uint32 xs;
1740 +
1741 + xc = R_REG(&di->regs->xmtcontrol);
1742 + if (xc & XC_SE) {
1743 + xs = R_REG(&di->regs->xmtstatus);
1744 + return ((xs & XS_XS_MASK) == XS_XS_IDLE);
1745 + }
1746 + return 0;
1747 +}
1748 +
1749 +bool
1750 +dma_txstopped(dma_info_t *di)
1751 +{
1752 + return ((R_REG(&di->regs->xmtstatus) & XS_XS_MASK) == XS_XS_STOPPED);
1753 +}
1754 +
1755 +bool
1756 +dma_rxstopped(dma_info_t *di)
1757 +{
1758 + return ((R_REG(&di->regs->rcvstatus) & RS_RS_MASK) == RS_RS_STOPPED);
1759 +}
1760 +
1761 +void
1762 +dma_fifoloopbackenable(dma_info_t *di)
1763 +{
1764 + DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
1765 + OR_REG(&di->regs->xmtcontrol, XC_LE);
1766 +}
1767 +
1768 +void
1769 +dma_rxinit(dma_info_t *di)
1770 +{
1771 + DMA_TRACE(("%s: dma_rxinit\n", di->name));
1772 +
1773 + di->rxin = di->rxout = 0;
1774 +
1775 + /* clear rx descriptor ring */
1776 + BZERO_SM((void*)di->rxd, (di->nrxd * sizeof (dmadd_t)));
1777 +
1778 + dma_rxenable(di);
1779 + W_REG(&di->regs->rcvaddr, (di->rxdpa + di->ddoffset));
1780 +}
1781 +
1782 +void
1783 +dma_rxenable(dma_info_t *di)
1784 +{
1785 + DMA_TRACE(("%s: dma_rxenable\n", di->name));
1786 + W_REG(&di->regs->rcvcontrol, ((di->rxoffset << RC_RO_SHIFT) | RC_RE));
1787 +}
1788 +
1789 +bool
1790 +dma_rxenabled(dma_info_t *di)
1791 +{
1792 + uint32 rc;
1793 +
1794 + rc = R_REG(&di->regs->rcvcontrol);
1795 + return ((rc != 0xffffffff) && (rc & RC_RE));
1796 +}
1797 +
1798 +/*
1799 + * The BCM47XX family supports full 32bit dma engine buffer addressing so
1800 + * dma buffers can cross 4 Kbyte page boundaries.
1801 + */
1802 +int
1803 +dma_txfast(dma_info_t *di, void *p0, uint32 coreflags)
1804 +{
1805 + void *p, *next;
1806 + uchar *data;
1807 + uint len;
1808 + uint txout;
1809 + uint32 ctrl;
1810 + uint32 pa;
1811 +
1812 + DMA_TRACE(("%s: dma_txfast\n", di->name));
1813 +
1814 + txout = di->txout;
1815 + ctrl = 0;
1816 +
1817 + /*
1818 + * Walk the chain of packet buffers
1819 + * allocating and initializing transmit descriptor entries.
1820 + */
1821 + for (p = p0; p; p = next) {
1822 + data = PKTDATA(di->drv, p);
1823 + len = PKTLEN(di->drv, p);
1824 + next = PKTNEXT(di->drv, p);
1825 +
1826 + /* return nonzero if out of tx descriptors */
1827 + if (NEXTTXD(txout) == di->txin)
1828 + goto outoftxd;
1829 +
1830 + if (len == 0)
1831 + continue;
1832 +
1833 + /* get physical address of buffer start */
1834 + pa = (uint32) DMA_MAP(di->dev, data, len, DMA_TX, p);
1835 +
1836 + /* build the descriptor control value */
1837 + ctrl = len & CTRL_BC_MASK;
1838 +
1839 + ctrl |= coreflags;
1840 +
1841 + if (p == p0)
1842 + ctrl |= CTRL_SOF;
1843 + if (next == NULL)
1844 + ctrl |= (CTRL_IOC | CTRL_EOF);
1845 + if (txout == (di->ntxd - 1))
1846 + ctrl |= CTRL_EOT;
1847 +
1848 + /* init the tx descriptor */
1849 + W_SM(&di->txd[txout].ctrl, BUS_SWAP32(ctrl));
1850 + W_SM(&di->txd[txout].addr, BUS_SWAP32(pa + di->dataoffset));
1851 +
1852 + ASSERT(di->txp[txout] == NULL);
1853 +
1854 + txout = NEXTTXD(txout);
1855 + }
1856 +
1857 + /* if last txd eof not set, fix it */
1858 + if (!(ctrl & CTRL_EOF))
1859 + W_SM(&di->txd[PREVTXD(txout)].ctrl, BUS_SWAP32(ctrl | CTRL_IOC | CTRL_EOF));
1860 +
1861 + /* save the packet */
1862 + di->txp[PREVTXD(txout)] = p0;
1863 +
1864 + /* bump the tx descriptor index */
1865 + di->txout = txout;
1866 +
1867 + /* kick the chip */
1868 + W_REG(&di->regs->xmtptr, I2B(txout));
1869 +
1870 + /* tx flow control */
1871 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
1872 +
1873 + return (0);
1874 +
1875 +outoftxd:
1876 + DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
1877 + PKTFREE(di->drv, p0, TRUE);
1878 + di->txavail = 0;
1879 + di->hnddma.txnobuf++;
1880 + return (-1);
1881 +}
1882 +
1883 +#define PAGESZ 4096
1884 +#define PAGEBASE(x) ((uint)(x) & ~4095)
1885 +
1886 +/*
1887 + * Just like above except go through the extra effort of splitting
1888 + * buffers that cross 4Kbyte boundaries into multiple tx descriptors.
1889 + */
1890 +int
1891 +dma_tx(dma_info_t *di, void *p0, uint32 coreflags)
1892 +{
1893 + void *p, *next;
1894 + uchar *data;
1895 + uint plen, len;
1896 + uchar *page, *start, *end;
1897 + uint txout;
1898 + uint32 ctrl;
1899 + uint32 pa;
1900 +
1901 + DMA_TRACE(("%s: dma_tx\n", di->name));
1902 +
1903 + txout = di->txout;
1904 + ctrl = 0;
1905 +
1906 + /*
1907 + * Walk the chain of packet buffers
1908 + * splitting those that cross 4 Kbyte boundaries
1909 + * allocating and initializing transmit descriptor entries.
1910 + */
1911 + for (p = p0; p; p = next) {
1912 + data = PKTDATA(di->drv, p);
1913 + plen = PKTLEN(di->drv, p);
1914 + next = PKTNEXT(di->drv, p);
1915 +
1916 + if (plen == 0)
1917 + continue;
1918 +
1919 + for (page = (uchar*)PAGEBASE(data);
1920 + page <= (uchar*)PAGEBASE(data + plen - 1);
1921 + page += PAGESZ) {
1922 +
1923 + /* return nonzero if out of tx descriptors */
1924 + if (NEXTTXD(txout) == di->txin)
1925 + goto outoftxd;
1926 +
1927 + start = (page == (uchar*)PAGEBASE(data))? data: page;
1928 + end = (page == (uchar*)PAGEBASE(data + plen))?
1929 + (data + plen): (page + PAGESZ);
1930 + len = end - start;
1931 +
1932 + /* build the descriptor control value */
1933 + ctrl = len & CTRL_BC_MASK;
1934 +
1935 + ctrl |= coreflags;
1936 +
1937 + if ((p == p0) && (start == data))
1938 + ctrl |= CTRL_SOF;
1939 + if ((next == NULL) && (end == (data + plen)))
1940 + ctrl |= (CTRL_IOC | CTRL_EOF);
1941 + if (txout == (di->ntxd - 1))
1942 + ctrl |= CTRL_EOT;
1943 +
1944 + /* get physical address of buffer start */
1945 + pa = (uint32) DMA_MAP(di->dev, start, len, DMA_TX, p);
1946 +
1947 + /* init the tx descriptor */
1948 + W_SM(&di->txd[txout].ctrl, BUS_SWAP32(ctrl));
1949 + W_SM(&di->txd[txout].addr, BUS_SWAP32(pa + di->dataoffset));
1950 +
1951 + ASSERT(di->txp[txout] == NULL);
1952 +
1953 + txout = NEXTTXD(txout);
1954 + }
1955 + }
1956 +
1957 + /* if last txd eof not set, fix it */
1958 + if (!(ctrl & CTRL_EOF))
1959 + W_SM(&di->txd[PREVTXD(txout)].ctrl, BUS_SWAP32(ctrl | CTRL_IOC | CTRL_EOF));
1960 +
1961 + /* save the packet */
1962 + di->txp[PREVTXD(txout)] = p0;
1963 +
1964 + /* bump the tx descriptor index */
1965 + di->txout = txout;
1966 +
1967 + /* kick the chip */
1968 + W_REG(&di->regs->xmtptr, I2B(txout));
1969 +
1970 + /* tx flow control */
1971 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
1972 +
1973 + return (0);
1974 +
1975 +outoftxd:
1976 + DMA_ERROR(("%s: dma_tx: out of txds\n", di->name));
1977 + PKTFREE(di->drv, p0, TRUE);
1978 + di->txavail = 0;
1979 + di->hnddma.txnobuf++;
1980 + return (-1);
1981 +}
1982 +
1983 +/* returns a pointer to the next frame received, or NULL if there are no more */
1984 +void*
1985 +dma_rx(dma_info_t *di)
1986 +{
1987 + void *p;
1988 + uint len;
1989 + int skiplen = 0;
1990 +
1991 + while ((p = dma_getnextrxp(di, FALSE))) {
1992 + /* skip giant packets which span multiple rx descriptors */
1993 + if (skiplen > 0) {
1994 + skiplen -= di->rxbufsize;
1995 + if (skiplen < 0)
1996 + skiplen = 0;
1997 + PKTFREE(di->drv, p, FALSE);
1998 + continue;
1999 + }
2000 +
2001 + len = ltoh16(*(uint16*)(PKTDATA(di->drv, p)));
2002 + DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
2003 +
2004 + /* bad frame length check */
2005 + if (len > (di->rxbufsize - di->rxoffset)) {
2006 + DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n", di->name, len));
2007 + if (len > 0)
2008 + skiplen = len - (di->rxbufsize - di->rxoffset);
2009 + PKTFREE(di->drv, p, FALSE);
2010 + di->hnddma.rxgiants++;
2011 + continue;
2012 + }
2013 +
2014 + /* set actual length */
2015 + PKTSETLEN(di->drv, p, (di->rxoffset + len));
2016 +
2017 + break;
2018 + }
2019 +
2020 + return (p);
2021 +}
2022 +
2023 +/* post receive buffers */
2024 +void
2025 +dma_rxfill(dma_info_t *di)
2026 +{
2027 + void *p;
2028 + uint rxin, rxout;
2029 + uint ctrl;
2030 + uint n;
2031 + uint i;
2032 + uint32 pa;
2033 + uint rxbufsize;
2034 +
2035 + /*
2036 + * Determine how many receive buffers we're lacking
2037 + * from the full complement, allocate, initialize,
2038 + * and post them, then update the chip rx lastdscr.
2039 + */
2040 +
2041 + rxin = di->rxin;
2042 + rxout = di->rxout;
2043 + rxbufsize = di->rxbufsize;
2044 +
2045 + n = di->nrxpost - NRXDACTIVE(rxin, rxout);
2046 +
2047 + DMA_TRACE(("%s: dma_rxfill: post %d\n", di->name, n));
2048 +
2049 + for (i = 0; i < n; i++) {
2050 + if ((p = PKTGET(di->drv, rxbufsize, FALSE)) == NULL) {
2051 + DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n", di->name));
2052 + di->hnddma.rxnobuf++;
2053 + break;
2054 + }
2055 +
2056 + *(uint32*)(OSL_UNCACHED(PKTDATA(di->drv, p))) = 0;
2057 +
2058 + pa = (uint32) DMA_MAP(di->dev, PKTDATA(di->drv, p), rxbufsize, DMA_RX, p);
2059 + ASSERT(ISALIGNED(pa, 4));
2060 +
2061 + /* save the free packet pointer */
2062 + ASSERT(di->rxp[rxout] == NULL);
2063 + di->rxp[rxout] = p;
2064 +
2065 + /* prep the descriptor control value */
2066 + ctrl = rxbufsize;
2067 + if (rxout == (di->nrxd - 1))
2068 + ctrl |= CTRL_EOT;
2069 +
2070 + /* init the rx descriptor */
2071 + W_SM(&di->rxd[rxout].ctrl, BUS_SWAP32(ctrl));
2072 + W_SM(&di->rxd[rxout].addr, BUS_SWAP32(pa + di->dataoffset));
2073 +
2074 + rxout = NEXTRXD(rxout);
2075 + }
2076 +
2077 + di->rxout = rxout;
2078 +
2079 + /* update the chip lastdscr pointer */
2080 + W_REG(&di->regs->rcvptr, I2B(rxout));
2081 +}
2082 +
2083 +void
2084 +dma_txreclaim(dma_info_t *di, bool forceall)
2085 +{
2086 + void *p;
2087 +
2088 + DMA_TRACE(("%s: dma_txreclaim %s\n", di->name, forceall ? "all" : ""));
2089 +
2090 + while ((p = dma_getnexttxp(di, forceall)))
2091 + PKTFREE(di->drv, p, TRUE);
2092 +}
2093 +
2094 +/*
2095 + * Reclaim next completed txd (txds if using chained buffers) and
2096 + * return associated packet.
2097 + * If 'force' is true, reclaim txd(s) and return associated packet
2098 + * regardless of the value of the hardware "curr" pointer.
2099 + */
2100 +void*
2101 +dma_getnexttxp(dma_info_t *di, bool forceall)
2102 +{
2103 + uint start, end, i;
2104 + void *txp;
2105 +
2106 + DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
2107 +
2108 + txp = NULL;
2109 +
2110 + start = di->txin;
2111 + if (forceall)
2112 + end = di->txout;
2113 + else
2114 + end = B2I(R_REG(&di->regs->xmtstatus) & XS_CD_MASK);
2115 +
2116 + if ((start == 0) && (end > di->txout))
2117 + goto bogus;
2118 +
2119 + for (i = start; i != end && !txp; i = NEXTTXD(i)) {
2120 + DMA_UNMAP(di->dev, (BUS_SWAP32(R_SM(&di->txd[i].addr)) - di->dataoffset),
2121 + (BUS_SWAP32(R_SM(&di->txd[i].ctrl)) & CTRL_BC_MASK), DMA_TX, di->txp[i]);
2122 + W_SM(&di->txd[i].addr, 0xdeadbeef);
2123 + txp = di->txp[i];
2124 + di->txp[i] = NULL;
2125 + }
2126 +
2127 + di->txin = i;
2128 +
2129 + /* tx flow control */
2130 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
2131 +
2132 + return (txp);
2133 +
2134 +bogus:
2135 +/*
2136 + DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
2137 + start, end, di->txout, forceall));
2138 +*/
2139 + return (NULL);
2140 +}
2141 +
2142 +void
2143 +dma_rxreclaim(dma_info_t *di)
2144 +{
2145 + void *p;
2146 +
2147 + DMA_TRACE(("%s: dma_rxreclaim\n", di->name));
2148 +
2149 + while ((p = dma_getnextrxp(di, TRUE)))
2150 + PKTFREE(di->drv, p, FALSE);
2151 +}
2152 +
2153 +void *
2154 +dma_getnextrxp(dma_info_t *di, bool forceall)
2155 +{
2156 + uint i;
2157 + void *rxp;
2158 +
2159 + /* if forcing, dma engine must be disabled */
2160 + ASSERT(!forceall || !dma_rxenabled(di));
2161 +
2162 + i = di->rxin;
2163 +
2164 + /* return if no packets posted */
2165 + if (i == di->rxout)
2166 + return (NULL);
2167 +
2168 + /* ignore curr if forceall */
2169 + if (!forceall && (i == B2I(R_REG(&di->regs->rcvstatus) & RS_CD_MASK)))
2170 + return (NULL);
2171 +
2172 + /* get the packet pointer that corresponds to the rx descriptor */
2173 + rxp = di->rxp[i];
2174 + ASSERT(rxp);
2175 + di->rxp[i] = NULL;
2176 +
2177 + /* clear this packet from the descriptor ring */
2178 + DMA_UNMAP(di->dev, (BUS_SWAP32(R_SM(&di->rxd[i].addr)) - di->dataoffset),
2179 + di->rxbufsize, DMA_RX, rxp);
2180 + W_SM(&di->rxd[i].addr, 0xdeadbeef);
2181 +
2182 + di->rxin = NEXTRXD(i);
2183 +
2184 + return (rxp);
2185 +}
2186 +
2187 +char*
2188 +dma_dumptx(dma_info_t *di, char *buf)
2189 +{
2190 + buf += sprintf(buf, "txd 0x%lx txdpa 0x%lx txp 0x%lx txin %d txout %d txavail %d\n",
2191 + (ulong)di->txd, di->txdpa, (ulong)di->txp, di->txin, di->txout, di->txavail);
2192 + buf += sprintf(buf, "xmtcontrol 0x%x xmtaddr 0x%x xmtptr 0x%x xmtstatus 0x%x\n",
2193 + R_REG(&di->regs->xmtcontrol),
2194 + R_REG(&di->regs->xmtaddr),
2195 + R_REG(&di->regs->xmtptr),
2196 + R_REG(&di->regs->xmtstatus));
2197 + return (buf);
2198 +}
2199 +
2200 +char*
2201 +dma_dumprx(dma_info_t *di, char *buf)
2202 +{
2203 + buf += sprintf(buf, "rxd 0x%lx rxdpa 0x%lx rxp 0x%lx rxin %d rxout %d\n",
2204 + (ulong)di->rxd, di->rxdpa, (ulong)di->rxp, di->rxin, di->rxout);
2205 + buf += sprintf(buf, "rcvcontrol 0x%x rcvaddr 0x%x rcvptr 0x%x rcvstatus 0x%x\n",
2206 + R_REG(&di->regs->rcvcontrol),
2207 + R_REG(&di->regs->rcvaddr),
2208 + R_REG(&di->regs->rcvptr),
2209 + R_REG(&di->regs->rcvstatus));
2210 + return (buf);
2211 +}
2212 +
2213 +char*
2214 +dma_dump(dma_info_t *di, char *buf)
2215 +{
2216 + buf = dma_dumptx(di, buf);
2217 + buf = dma_dumprx(di, buf);
2218 + return (buf);
2219 +}
2220 +
2221 +uint
2222 +dma_getvar(dma_info_t *di, char *name)
2223 +{
2224 + if (!strcmp(name, "&txavail"))
2225 + return ((uint) &di->txavail);
2226 + else {
2227 + ASSERT(0);
2228 + }
2229 + return (0);
2230 +}
2231 +
2232 +void
2233 +dma_txblock(dma_info_t *di)
2234 +{
2235 + di->txavail = 0;
2236 +}
2237 +
2238 +void
2239 +dma_txunblock(dma_info_t *di)
2240 +{
2241 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
2242 +}
2243 +
2244 +uint
2245 +dma_txactive(dma_info_t *di)
2246 +{
2247 + return (NTXDACTIVE(di->txin, di->txout));
2248 +}
2249 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/broadcom/linux_osl.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/linux_osl.c
2250 --- linux-2.6.12.5/arch/mips/bcm947xx/broadcom/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
2251 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/linux_osl.c 2005-08-28 11:12:20.476852160 +0200
2252 @@ -0,0 +1,420 @@
2253 +/*
2254 + * Linux OS Independent Layer
2255 + *
2256 + * Copyright 2001-2003, Broadcom Corporation
2257 + * All Rights Reserved.
2258 + *
2259 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2260 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2261 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2262 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2263 + *
2264 + * $Id: linux_osl.c,v 1.2 2005/02/28 13:34:25 jolt Exp $
2265 + */
2266 +
2267 +#define LINUX_OSL
2268 +
2269 +#include <typedefs.h>
2270 +#include <bcmendian.h>
2271 +#include <linuxver.h>
2272 +#include <linux_osl.h>
2273 +#include <bcmutils.h>
2274 +#include <linux/delay.h>
2275 +#ifdef mips
2276 +#include <asm/paccess.h>
2277 +#endif
2278 +#include <pcicfg.h>
2279 +
2280 +#define PCI_CFG_RETRY 10
2281 +
2282 +void*
2283 +osl_pktget(void *drv, uint len, bool send)
2284 +{
2285 + struct sk_buff *skb;
2286 +
2287 + if ((skb = dev_alloc_skb(len)) == NULL)
2288 + return (NULL);
2289 +
2290 + skb_put(skb, len);
2291 +
2292 + /* ensure the cookie field is cleared */
2293 + PKTSETCOOKIE(skb, NULL);
2294 +
2295 + return ((void*) skb);
2296 +}
2297 +
2298 +void
2299 +osl_pktfree(void *p)
2300 +{
2301 + struct sk_buff *skb, *nskb;
2302 +
2303 + skb = (struct sk_buff*) p;
2304 +
2305 + /* perversion: we use skb->next to chain multi-skb packets */
2306 + while (skb) {
2307 + nskb = skb->next;
2308 + skb->next = NULL;
2309 + if (skb->destructor) {
2310 + /* cannot kfree_skb() on hard IRQ (net/core/skbuff.c) if destructor exists */
2311 + dev_kfree_skb_any(skb);
2312 + } else {
2313 + /* can free immediately (even in_irq()) if destructor does not exist */
2314 + dev_kfree_skb(skb);
2315 + }
2316 + skb = nskb;
2317 + }
2318 +}
2319 +
2320 +uint32
2321 +osl_pci_read_config(void *loc, uint offset, uint size)
2322 +{
2323 + struct pci_dev *pdev;
2324 + uint val;
2325 + uint retry=PCI_CFG_RETRY;
2326 +
2327 + /* only 4byte access supported */
2328 + ASSERT(size == 4);
2329 +
2330 + pdev = (struct pci_dev*)loc;
2331 + do {
2332 + pci_read_config_dword(pdev, offset, &val);
2333 + if (val != 0xffffffff)
2334 + break;
2335 + } while (retry--);
2336 +
2337 +
2338 + return (val);
2339 +}
2340 +
2341 +void
2342 +osl_pci_write_config(void *loc, uint offset, uint size, uint val)
2343 +{
2344 + struct pci_dev *pdev;
2345 + uint retry=PCI_CFG_RETRY;
2346 +
2347 + /* only 4byte access supported */
2348 + ASSERT(size == 4);
2349 +
2350 + pdev = (struct pci_dev*)loc;
2351 +
2352 + do {
2353 + pci_write_config_dword(pdev, offset, val);
2354 + if (offset!=PCI_BAR0_WIN)
2355 + break;
2356 + if (osl_pci_read_config(loc,offset,size) == val)
2357 + break;
2358 + } while (retry--);
2359 +
2360 +}
2361 +
2362 +void
2363 +osl_pcmcia_read_attr(void *osh, uint offset, void *buf, int size)
2364 +{
2365 + ASSERT(0);
2366 +}
2367 +
2368 +void
2369 +osl_pcmcia_write_attr(void *osh, uint offset, void *buf, int size)
2370 +{
2371 + ASSERT(0);
2372 +}
2373 +
2374 +void
2375 +osl_assert(char *exp, char *file, int line)
2376 +{
2377 + char tempbuf[255];
2378 +
2379 + sprintf(tempbuf, "assertion \"%s\" failed: file \"%s\", line %d\n", exp, file, line);
2380 + panic(tempbuf);
2381 +}
2382 +
2383 +/*
2384 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
2385 + */
2386 +#ifdef BINOSL
2387 +
2388 +int
2389 +osl_printf(const char *format, ...)
2390 +{
2391 + va_list args;
2392 + char buf[1024];
2393 + int len;
2394 +
2395 + /* sprintf into a local buffer because there *is* no "vprintk()".. */
2396 + va_start(args, format);
2397 + len = vsprintf(buf, format, args);
2398 + va_end(args);
2399 +
2400 + if (len > sizeof (buf)) {
2401 + printk("osl_printf: buffer overrun\n");
2402 + return (0);
2403 + }
2404 +
2405 + return (printk(buf));
2406 +}
2407 +
2408 +int
2409 +osl_sprintf(char *buf, const char *format, ...)
2410 +{
2411 + va_list args;
2412 + int rc;
2413 +
2414 + va_start(args, format);
2415 + rc = vsprintf(buf, format, args);
2416 + va_end(args);
2417 + return (rc);
2418 +}
2419 +
2420 +int
2421 +osl_strcmp(const char *s1, const char *s2)
2422 +{
2423 + return (strcmp(s1, s2));
2424 +}
2425 +
2426 +int
2427 +osl_strncmp(const char *s1, const char *s2, uint n)
2428 +{
2429 + return (strncmp(s1, s2, n));
2430 +}
2431 +
2432 +int
2433 +osl_strlen(char *s)
2434 +{
2435 + return (strlen(s));
2436 +}
2437 +
2438 +char*
2439 +osl_strcpy(char *d, const char *s)
2440 +{
2441 + return (strcpy(d, s));
2442 +}
2443 +
2444 +char*
2445 +osl_strncpy(char *d, const char *s, uint n)
2446 +{
2447 + return (strncpy(d, s, n));
2448 +}
2449 +
2450 +void
2451 +bcopy(const void *src, void *dst, int len)
2452 +{
2453 + memcpy(dst, src, len);
2454 +}
2455 +
2456 +int
2457 +bcmp(const void *b1, const void *b2, int len)
2458 +{
2459 + return (memcmp(b1, b2, len));
2460 +}
2461 +
2462 +void
2463 +bzero(void *b, int len)
2464 +{
2465 + memset(b, '\0', len);
2466 +}
2467 +
2468 +void*
2469 +osl_malloc(uint size)
2470 +{
2471 + return (kmalloc(size, GFP_ATOMIC));
2472 +}
2473 +
2474 +void
2475 +osl_mfree(void *addr, uint size)
2476 +{
2477 + kfree(addr);
2478 +}
2479 +
2480 +uint32
2481 +osl_readl(volatile uint32 *r)
2482 +{
2483 + return (readl(r));
2484 +}
2485 +
2486 +uint16
2487 +osl_readw(volatile uint16 *r)
2488 +{
2489 + return (readw(r));
2490 +}
2491 +
2492 +uint8
2493 +osl_readb(volatile uint8 *r)
2494 +{
2495 + return (readb(r));
2496 +}
2497 +
2498 +void
2499 +osl_writel(uint32 v, volatile uint32 *r)
2500 +{
2501 + writel(v, r);
2502 +}
2503 +
2504 +void
2505 +osl_writew(uint16 v, volatile uint16 *r)
2506 +{
2507 + writew(v, r);
2508 +}
2509 +
2510 +void
2511 +osl_writeb(uint8 v, volatile uint8 *r)
2512 +{
2513 + writeb(v, r);
2514 +}
2515 +
2516 +void *
2517 +osl_uncached(void *va)
2518 +{
2519 +#ifdef mips
2520 + return ((void*)KSEG1ADDR(va));
2521 +#else
2522 + return ((void*)va);
2523 +#endif
2524 +}
2525 +
2526 +uint
2527 +osl_getcycles(void)
2528 +{
2529 + uint cycles;
2530 +
2531 +#if defined(mips)
2532 + cycles = read_c0_count() * 2;
2533 +#elif defined(__i386__)
2534 + rdtscl(cycles);
2535 +#else
2536 + cycles = 0;
2537 +#endif
2538 + return cycles;
2539 +}
2540 +
2541 +void *
2542 +osl_reg_map(uint32 pa, uint size)
2543 +{
2544 + return (ioremap_nocache((unsigned long)pa, (unsigned long)size));
2545 +}
2546 +
2547 +void
2548 +osl_reg_unmap(void *va)
2549 +{
2550 + iounmap(va);
2551 +}
2552 +
2553 +int
2554 +osl_busprobe(uint32 *val, uint32 addr)
2555 +{
2556 +#ifdef mips
2557 + return get_dbe(*val, (uint32*)addr);
2558 +#else
2559 + *val = readl(addr);
2560 + return 0;
2561 +#endif
2562 +}
2563 +
2564 +void*
2565 +osl_dma_alloc_consistent(void *dev, uint size, ulong *pap)
2566 +{
2567 + return (pci_alloc_consistent((struct pci_dev*)dev, size, (dma_addr_t*)pap));
2568 +}
2569 +
2570 +void
2571 +osl_dma_free_consistent(void *dev, void *va, uint size, ulong pa)
2572 +{
2573 + pci_free_consistent((struct pci_dev*)dev, size, va, (dma_addr_t)pa);
2574 +}
2575 +
2576 +uint
2577 +osl_dma_map(void *dev, void *va, uint size, int direction)
2578 +{
2579 + int dir;
2580 +
2581 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
2582 + return (pci_map_single(dev, va, size, dir));
2583 +}
2584 +
2585 +void
2586 +osl_dma_unmap(void *dev, uint pa, uint size, int direction)
2587 +{
2588 + int dir;
2589 +
2590 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
2591 + pci_unmap_single(dev, (uint32)pa, size, dir);
2592 +}
2593 +
2594 +void
2595 +osl_delay(uint usec)
2596 +{
2597 + udelay(usec);
2598 +}
2599 +
2600 +uchar*
2601 +osl_pktdata(void *drv, void *skb)
2602 +{
2603 + return (((struct sk_buff*)skb)->data);
2604 +}
2605 +
2606 +uint
2607 +osl_pktlen(void *drv, void *skb)
2608 +{
2609 + return (((struct sk_buff*)skb)->len);
2610 +}
2611 +
2612 +void*
2613 +osl_pktnext(void *drv, void *skb)
2614 +{
2615 + return (((struct sk_buff*)skb)->next);
2616 +}
2617 +
2618 +void
2619 +osl_pktsetnext(void *skb, void *x)
2620 +{
2621 + ((struct sk_buff*)skb)->next = (struct sk_buff*)x;
2622 +}
2623 +
2624 +void
2625 +osl_pktsetlen(void *drv, void *skb, uint len)
2626 +{
2627 + __skb_trim((struct sk_buff*)skb, len);
2628 +}
2629 +
2630 +uchar*
2631 +osl_pktpush(void *drv, void *skb, int bytes)
2632 +{
2633 + return (skb_push((struct sk_buff*)skb, bytes));
2634 +}
2635 +
2636 +uchar*
2637 +osl_pktpull(void *drv, void *skb, int bytes)
2638 +{
2639 + return (skb_pull((struct sk_buff*)skb, bytes));
2640 +}
2641 +
2642 +void*
2643 +osl_pktdup(void *drv, void *skb)
2644 +{
2645 + return (skb_clone((struct sk_buff*)skb, GFP_ATOMIC));
2646 +}
2647 +
2648 +void*
2649 +osl_pktcookie(void *skb)
2650 +{
2651 + return ((void*)((struct sk_buff*)skb)->csum);
2652 +}
2653 +
2654 +void
2655 +osl_pktsetcookie(void *skb, void *x)
2656 +{
2657 + ((struct sk_buff*)skb)->csum = (uint)x;
2658 +}
2659 +
2660 +void*
2661 +osl_pktlink(void *skb)
2662 +{
2663 + return (((struct sk_buff*)skb)->prev);
2664 +}
2665 +
2666 +void
2667 +osl_pktsetlink(void *skb, void *x)
2668 +{
2669 + ((struct sk_buff*)skb)->prev = (struct sk_buff*)x;
2670 +}
2671 +
2672 +#endif
2673 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/broadcom/sbmips.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/sbmips.c
2674 --- linux-2.6.12.5/arch/mips/bcm947xx/broadcom/sbmips.c 1970-01-01 01:00:00.000000000 +0100
2675 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/sbmips.c 2005-08-28 11:12:20.478851856 +0200
2676 @@ -0,0 +1,950 @@
2677 +/*
2678 + * BCM47XX Sonics SiliconBackplane MIPS core routines
2679 + *
2680 + * Copyright 2001-2003, Broadcom Corporation
2681 + * All Rights Reserved.
2682 + *
2683 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2684 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2685 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2686 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2687 + *
2688 + * $Id: sbmips.c,v 1.1 2005/02/28 13:33:32 jolt Exp $
2689 + */
2690 +
2691 +#include <typedefs.h>
2692 +#include <osl.h>
2693 +#include <sbutils.h>
2694 +#include <bcmdevs.h>
2695 +#include <bcmnvram.h>
2696 +#include <bcmutils.h>
2697 +#include <hndmips.h>
2698 +#include <sbconfig.h>
2699 +#include <sbextif.h>
2700 +#include <sbchipc.h>
2701 +#include <sbmemc.h>
2702 +
2703 +/*
2704 + * Memory segments (32bit kernel mode addresses)
2705 + */
2706 +#undef KUSEG
2707 +#undef KSEG0
2708 +#undef KSEG1
2709 +#undef KSEG2
2710 +#undef KSEG3
2711 +#define KUSEG 0x00000000
2712 +#define KSEG0 0x80000000
2713 +#define KSEG1 0xa0000000
2714 +#define KSEG2 0xc0000000
2715 +#define KSEG3 0xe0000000
2716 +
2717 +/*
2718 + * Map an address to a certain kernel segment
2719 + */
2720 +#undef KSEG0ADDR
2721 +#undef KSEG1ADDR
2722 +#undef KSEG2ADDR
2723 +#undef KSEG3ADDR
2724 +#define KSEG0ADDR(a) (((a) & 0x1fffffff) | KSEG0)
2725 +#define KSEG1ADDR(a) (((a) & 0x1fffffff) | KSEG1)
2726 +#define KSEG2ADDR(a) (((a) & 0x1fffffff) | KSEG2)
2727 +#define KSEG3ADDR(a) (((a) & 0x1fffffff) | KSEG3)
2728 +
2729 +/*
2730 + * The following macros are especially useful for __asm__
2731 + * inline assembler.
2732 + */
2733 +#ifndef __STR
2734 +#define __STR(x) #x
2735 +#endif
2736 +#ifndef STR
2737 +#define STR(x) __STR(x)
2738 +#endif
2739 +
2740 +/* *********************************************************************
2741 + * CP0 Registers
2742 + ********************************************************************* */
2743 +
2744 +#define C0_INX 0 /* CP0: TLB Index */
2745 +#define C0_RAND 1 /* CP0: TLB Random */
2746 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
2747 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
2748 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
2749 +#define C0_CTEXT 4 /* CP0: Context */
2750 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
2751 +#define C0_WIRED 6 /* CP0: TLB Wired */
2752 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
2753 +#define C0_COUNT 9 /* CP0: Count */
2754 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
2755 +#define C0_COMPARE 11 /* CP0: Compare */
2756 +#define C0_SR 12 /* CP0: Processor Status */
2757 +#define C0_STATUS C0_SR /* CP0: Processor Status */
2758 +#define C0_CAUSE 13 /* CP0: Exception Cause */
2759 +#define C0_EPC 14 /* CP0: Exception PC */
2760 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
2761 +#define C0_CONFIG 16 /* CP0: Config */
2762 +#define C0_LLADDR 17 /* CP0: LLAddr */
2763 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
2764 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
2765 +#define C0_XCTEXT 20 /* CP0: XContext */
2766 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
2767 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
2768 +#define C0_ECC 26 /* CP0: ECC */
2769 +#define C0_CACHEERR 27 /* CP0: CacheErr */
2770 +#define C0_TAGLO 28 /* CP0: TagLo */
2771 +#define C0_TAGHI 29 /* CP0: TagHi */
2772 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
2773 +
2774 +/*
2775 + * Macros to access the system control coprocessor
2776 + */
2777 +
2778 +#define MFC0(source, sel) \
2779 +({ \
2780 + int __res; \
2781 + __asm__ __volatile__( \
2782 + ".set\tnoreorder\n\t" \
2783 + ".set\tnoat\n\t" \
2784 + ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
2785 + "move\t%0,$1\n\t" \
2786 + ".set\tat\n\t" \
2787 + ".set\treorder" \
2788 + :"=r" (__res) \
2789 + : \
2790 + :"$1"); \
2791 + __res; \
2792 +})
2793 +
2794 +#define MTC0(source, sel, value) \
2795 +do { \
2796 + __asm__ __volatile__( \
2797 + ".set\tnoreorder\n\t" \
2798 + ".set\tnoat\n\t" \
2799 + "move\t$1,%z0\n\t" \
2800 + ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
2801 + ".set\tat\n\t" \
2802 + ".set\treorder" \
2803 + : \
2804 + :"Jr" (value) \
2805 + :"$1"); \
2806 +} while (0)
2807 +
2808 +/*
2809 + * R4x00 interrupt enable / cause bits
2810 + */
2811 +#undef IE_SW0
2812 +#undef IE_SW1
2813 +#undef IE_IRQ0
2814 +#undef IE_IRQ1
2815 +#undef IE_IRQ2
2816 +#undef IE_IRQ3
2817 +#undef IE_IRQ4
2818 +#undef IE_IRQ5
2819 +#define IE_SW0 (1<< 8)
2820 +#define IE_SW1 (1<< 9)
2821 +#define IE_IRQ0 (1<<10)
2822 +#define IE_IRQ1 (1<<11)
2823 +#define IE_IRQ2 (1<<12)
2824 +#define IE_IRQ3 (1<<13)
2825 +#define IE_IRQ4 (1<<14)
2826 +#define IE_IRQ5 (1<<15)
2827 +
2828 +/*
2829 + * Bitfields in the R4xx0 cp0 status register
2830 + */
2831 +#define ST0_IE 0x00000001
2832 +#define ST0_EXL 0x00000002
2833 +#define ST0_ERL 0x00000004
2834 +#define ST0_KSU 0x00000018
2835 +# define KSU_USER 0x00000010
2836 +# define KSU_SUPERVISOR 0x00000008
2837 +# define KSU_KERNEL 0x00000000
2838 +#define ST0_UX 0x00000020
2839 +#define ST0_SX 0x00000040
2840 +#define ST0_KX 0x00000080
2841 +#define ST0_DE 0x00010000
2842 +#define ST0_CE 0x00020000
2843 +
2844 +/*
2845 + * Status register bits available in all MIPS CPUs.
2846 + */
2847 +#define ST0_IM 0x0000ff00
2848 +#define ST0_CH 0x00040000
2849 +#define ST0_SR 0x00100000
2850 +#define ST0_TS 0x00200000
2851 +#define ST0_BEV 0x00400000
2852 +#define ST0_RE 0x02000000
2853 +#define ST0_FR 0x04000000
2854 +#define ST0_CU 0xf0000000
2855 +#define ST0_CU0 0x10000000
2856 +#define ST0_CU1 0x20000000
2857 +#define ST0_CU2 0x40000000
2858 +#define ST0_CU3 0x80000000
2859 +#define ST0_XX 0x80000000 /* MIPS IV naming */
2860 +
2861 +/*
2862 + * Cache Operations
2863 + */
2864 +
2865 +#ifndef Fill_I
2866 +#define Fill_I 0x14
2867 +#endif
2868 +
2869 +#define cache_unroll(base,op) \
2870 + __asm__ __volatile__(" \
2871 + .set noreorder; \
2872 + .set mips3; \
2873 + cache %1, (%0); \
2874 + .set mips0; \
2875 + .set reorder" \
2876 + : \
2877 + : "r" (base), \
2878 + "i" (op));
2879 +
2880 +/*
2881 + * These are the UART port assignments, expressed as offsets from the base
2882 + * register. These assignments should hold for any serial port based on
2883 + * a 8250, 16450, or 16550(A).
2884 + */
2885 +
2886 +#define UART_MCR 4 /* Out: Modem Control Register */
2887 +#define UART_MSR 6 /* In: Modem Status Register */
2888 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
2889 +
2890 +/*
2891 + * Returns TRUE if an external UART exists at the given base
2892 + * register.
2893 + */
2894 +static bool
2895 +serial_exists(uint8 *regs)
2896 +{
2897 + uint8 save_mcr, status1;
2898 +
2899 + save_mcr = R_REG(&regs[UART_MCR]);
2900 + W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
2901 + status1 = R_REG(&regs[UART_MSR]) & 0xf0;
2902 + W_REG(&regs[UART_MCR], save_mcr);
2903 +
2904 + return (status1 == 0x90);
2905 +}
2906 +
2907 +/*
2908 + * Initializes UART access. The callback function will be called once
2909 + * per found UART.
2910 +*/
2911 +void
2912 +sb_serial_init(void *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
2913 +{
2914 + void *regs;
2915 + ulong base;
2916 + uint irq;
2917 + int i, n;
2918 +
2919 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
2920 + extifregs_t *eir = (extifregs_t *) regs;
2921 + sbconfig_t *sb;
2922 +
2923 + /* Determine external UART register base */
2924 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
2925 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
2926 +
2927 + /* Determine IRQ */
2928 + irq = sb_irq(sbh);
2929 +
2930 + /* Disable GPIO interrupt initially */
2931 + W_REG(&eir->gpiointpolarity, 0);
2932 + W_REG(&eir->gpiointmask, 0);
2933 +
2934 + /* Search for external UARTs */
2935 + n = 2;
2936 + for (i = 0; i < 2; i++) {
2937 + regs = (void *) REG_MAP(base + (i * 8), 8);
2938 + if (serial_exists(regs)) {
2939 + /* Set GPIO 1 to be the external UART IRQ */
2940 + W_REG(&eir->gpiointmask, 2);
2941 + if (add)
2942 + add(regs, irq, 13500000, 0);
2943 + }
2944 + }
2945 +
2946 + /* Add internal UART if enabled */
2947 + if (R_REG(&eir->corecontrol) & CC_UE)
2948 + if (add)
2949 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
2950 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
2951 + chipcregs_t *cc = (chipcregs_t *) regs;
2952 + uint32 rev, cap, pll, baud_base, div;
2953 +
2954 + /* Determine core revision and capabilities */
2955 + rev = sb_corerev(sbh);
2956 + cap = R_REG(&cc->capabilities);
2957 + pll = cap & CAP_PLL_MASK;
2958 +
2959 + /* Determine IRQ */
2960 + irq = sb_irq(sbh);
2961 +
2962 + if (pll == PLL_TYPE1) {
2963 + /* PLL clock */
2964 + baud_base = sb_clock_rate(pll,
2965 + R_REG(&cc->clockcontrol_n),
2966 + R_REG(&cc->clockcontrol_m2));
2967 + div = 1;
2968 + } else if (rev >= 3) {
2969 + /* Internal backplane clock */
2970 + baud_base = sb_clock_rate(pll,
2971 + R_REG(&cc->clockcontrol_n),
2972 + R_REG(&cc->clockcontrol_sb));
2973 + div = 2; /* Minimum divisor */
2974 + W_REG(&cc->uart_clkdiv, div);
2975 + } else {
2976 + /* Fixed internal backplane clock */
2977 + baud_base = 88000000;
2978 + div = 48;
2979 + }
2980 +
2981 + /* Clock source depends on strapping if UartClkOverride is unset */
2982 + if ((rev > 0) && ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
2983 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
2984 + /* Internal divided backplane clock */
2985 + baud_base /= div;
2986 + } else {
2987 + /* Assume external clock of 1.8432 MHz */
2988 + baud_base = 1843200;
2989 + }
2990 + }
2991 +
2992 + /* Add internal UARTs */
2993 + n = cap & CAP_UARTS_MASK;
2994 + for (i = 0; i < n; i++) {
2995 + /* Register offset changed after revision 0 */
2996 + if (rev)
2997 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
2998 + else
2999 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
3000 +
3001 + if (add)
3002 + add(regs, irq, baud_base, 0);
3003 + }
3004 + }
3005 +}
3006 +
3007 +/* Returns the SB interrupt flag of the current core. */
3008 +uint32
3009 +sb_flag(void *sbh)
3010 +{
3011 + void *regs;
3012 + sbconfig_t *sb;
3013 +
3014 + regs = sb_coreregs(sbh);
3015 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
3016 +
3017 + return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
3018 +}
3019 +
3020 +static const uint32 sbips_int_mask[] = {
3021 + 0,
3022 + SBIPS_INT1_MASK,
3023 + SBIPS_INT2_MASK,
3024 + SBIPS_INT3_MASK,
3025 + SBIPS_INT4_MASK
3026 +};
3027 +
3028 +static const uint32 sbips_int_shift[] = {
3029 + 0,
3030 + 0,
3031 + SBIPS_INT2_SHIFT,
3032 + SBIPS_INT3_SHIFT,
3033 + SBIPS_INT4_SHIFT
3034 +};
3035 +
3036 +/*
3037 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
3038 + * 0 is returned.
3039 + */
3040 +uint
3041 +sb_irq(void *sbh)
3042 +{
3043 + uint idx;
3044 + void *regs;
3045 + sbconfig_t *sb;
3046 + uint32 flag, sbipsflag;
3047 + uint irq = 0;
3048 +
3049 + flag = sb_flag(sbh);
3050 +
3051 + idx = sb_coreidx(sbh);
3052 +
3053 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
3054 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
3055 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
3056 +
3057 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
3058 + sbipsflag = R_REG(&sb->sbipsflag);
3059 + for (irq = 1; irq <= 4; irq++) {
3060 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
3061 + break;
3062 + }
3063 + if (irq == 5)
3064 + irq = 0;
3065 + }
3066 +
3067 + sb_setcoreidx(sbh, idx);
3068 +
3069 + return irq;
3070 +}
3071 +
3072 +/* Clears the specified MIPS IRQ. */
3073 +static void
3074 +sb_clearirq(void *sbh, uint irq)
3075 +{
3076 + void *regs;
3077 + sbconfig_t *sb;
3078 +
3079 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
3080 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
3081 + ASSERT(regs);
3082 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
3083 +
3084 + if (irq == 0)
3085 + W_REG(&sb->sbintvec, 0);
3086 + else
3087 + OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
3088 +}
3089 +
3090 +/*
3091 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
3092 + * IRQ 0 may be assigned more than once.
3093 + */
3094 +static void
3095 +sb_setirq(void *sbh, uint irq, uint coreid, uint coreunit)
3096 +{
3097 + void *regs;
3098 + sbconfig_t *sb;
3099 + uint32 flag;
3100 +
3101 + regs = sb_setcore(sbh, coreid, coreunit);
3102 + ASSERT(regs);
3103 + flag = sb_flag(sbh);
3104 +
3105 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
3106 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
3107 + ASSERT(regs);
3108 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
3109 +
3110 + if (irq == 0)
3111 + OR_REG(&sb->sbintvec, 1 << flag);
3112 + else {
3113 + flag <<= sbips_int_shift[irq];
3114 + ASSERT(!(flag & ~sbips_int_mask[irq]));
3115 + flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
3116 + W_REG(&sb->sbipsflag, flag);
3117 + }
3118 +}
3119 +
3120 +/*
3121 + * Initializes clocks and interrupts. SB and NVRAM access must be
3122 + * initialized prior to calling.
3123 + */
3124 +void
3125 +sb_mips_init(void *sbh)
3126 +{
3127 + ulong hz, ns, tmp;
3128 + extifregs_t *eir;
3129 + chipcregs_t *cc;
3130 + char *value;
3131 + uint irq;
3132 +
3133 + /* Figure out current SB clock speed */
3134 + if ((hz = sb_clock(sbh)) == 0)
3135 + hz = 100000000;
3136 + ns = 1000000000 / hz;
3137 +
3138 + /* Setup external interface timing */
3139 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
3140 + /* Initialize extif so we can get to the LEDs and external UART */
3141 + W_REG(&eir->prog_config, CF_EN);
3142 +
3143 + /* Set timing for the flash */
3144 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
3145 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
3146 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
3147 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
3148 +
3149 + /* Set programmable interface timing for external uart */
3150 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
3151 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
3152 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
3153 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
3154 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
3155 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
3156 + /* Set timing for the flash */
3157 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
3158 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
3159 + tmp |= CEIL(120, ns); /* W0 = 120nS */
3160 + W_REG(&cc->parallelflashwaitcnt, tmp);
3161 +
3162 + W_REG(&cc->cs01memwaitcnt, tmp);
3163 + }
3164 +
3165 + /* Chip specific initialization */
3166 + switch (sb_chip(sbh)) {
3167 + case BCM4710_DEVICE_ID:
3168 + /* Clear interrupt map */
3169 + for (irq = 0; irq <= 4; irq++)
3170 + sb_clearirq(sbh, irq);
3171 + sb_setirq(sbh, 0, SB_CODEC, 0);
3172 + sb_setirq(sbh, 0, SB_EXTIF, 0);
3173 + sb_setirq(sbh, 2, SB_ENET, 1);
3174 + sb_setirq(sbh, 3, SB_ILINE20, 0);
3175 + sb_setirq(sbh, 4, SB_PCI, 0);
3176 + ASSERT(eir);
3177 + value = nvram_get("et0phyaddr");
3178 + if (value && !strcmp(value, "31")) {
3179 + /* Enable internal UART */
3180 + W_REG(&eir->corecontrol, CC_UE);
3181 + /* Give USB its own interrupt */
3182 + sb_setirq(sbh, 1, SB_USB, 0);
3183 + } else {
3184 + /* Disable internal UART */
3185 + W_REG(&eir->corecontrol, 0);
3186 + /* Give Ethernet its own interrupt */
3187 + sb_setirq(sbh, 1, SB_ENET, 0);
3188 + sb_setirq(sbh, 0, SB_USB, 0);
3189 + }
3190 + break;
3191 + case BCM4310_DEVICE_ID:
3192 + MTC0(C0_BROADCOM, 0, MFC0(C0_BROADCOM, 0) & ~(1 << 22));
3193 + break;
3194 + }
3195 +}
3196 +
3197 +uint32
3198 +sb_mips_clock(void *sbh)
3199 +{
3200 + extifregs_t *eir;
3201 + chipcregs_t *cc;
3202 + uint32 n, m;
3203 + uint idx;
3204 + uint32 pll_type, rate = 0;
3205 +
3206 + /* get index of the current core */
3207 + idx = sb_coreidx(sbh);
3208 + pll_type = PLL_TYPE1;
3209 +
3210 + /* switch to extif or chipc core */
3211 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
3212 + n = R_REG(&eir->clockcontrol_n);
3213 + m = R_REG(&eir->clockcontrol_sb);
3214 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
3215 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
3216 + n = R_REG(&cc->clockcontrol_n);
3217 + if ((pll_type == PLL_TYPE2) || (pll_type == PLL_TYPE4))
3218 + m = R_REG(&cc->clockcontrol_mips);
3219 + else if (pll_type == PLL_TYPE3) {
3220 + rate = 200000000;
3221 + goto out;
3222 + } else
3223 + m = R_REG(&cc->clockcontrol_sb);
3224 + } else
3225 + goto out;
3226 +
3227 + /* calculate rate */
3228 + rate = sb_clock_rate(pll_type, n, m);
3229 +
3230 +out:
3231 + /* switch back to previous core */
3232 + sb_setcoreidx(sbh, idx);
3233 +
3234 + return rate;
3235 +}
3236 +
3237 +static void
3238 +icache_probe(int *size, int *lsize)
3239 +{
3240 + uint32 config1;
3241 + uint sets, ways;
3242 +
3243 + config1 = MFC0(C0_CONFIG, 1);
3244 +
3245 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
3246 + if ((*lsize = ((config1 >> 19) & 7)))
3247 + *lsize = 2 << *lsize;
3248 + sets = 64 << ((config1 >> 22) & 7);
3249 + ways = 1 + ((config1 >> 16) & 7);
3250 + *size = *lsize * sets * ways;
3251 +}
3252 +
3253 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
3254 +
3255 +static void
3256 +handler(void)
3257 +{
3258 + /* Step 11 */
3259 + __asm__ (
3260 + ".set\tmips32\n\t"
3261 + "ssnop\n\t"
3262 + "ssnop\n\t"
3263 + /* Disable interrupts */
3264 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
3265 + "mfc0 $15, $12\n\t"
3266 + "and $15, $15, -31746\n\t"
3267 + "mtc0 $15, $12\n\t"
3268 + "eret\n\t"
3269 + "nop\n\t"
3270 + "nop\n\t"
3271 + ".set\tmips0"
3272 + );
3273 +}
3274 +
3275 +/* The following MUST come right after handler() */
3276 +static void
3277 +afterhandler(void)
3278 +{
3279 +}
3280 +
3281 +/*
3282 + * Set the MIPS, backplane and PCI clocks as closely as possible.
3283 + */
3284 +bool
3285 +sb_mips_setclock(void *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
3286 +{
3287 + extifregs_t *eir = NULL;
3288 + chipcregs_t *cc = NULL;
3289 + mipsregs_t *mipsr = NULL;
3290 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci;
3291 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, new_ratio;
3292 + uint32 pll_type, sync_mode;
3293 + uint idx, i;
3294 + struct {
3295 + uint32 mipsclock;
3296 + uint16 n;
3297 + uint32 sb;
3298 + uint32 pci33;
3299 + uint32 pci25;
3300 + } type1_table[] = {
3301 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /* 96.000 32.000 24.000 */
3302 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
3303 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
3304 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
3305 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
3306 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
3307 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
3308 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
3309 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
3310 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
3311 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
3312 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
3313 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
3314 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
3315 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
3316 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
3317 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
3318 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
3319 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
3320 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
3321 + };
3322 + typedef struct {
3323 + uint32 mipsclock;
3324 + uint32 sbclock;
3325 + uint16 n;
3326 + uint32 sb;
3327 + uint32 pci33;
3328 + uint32 m2;
3329 + uint32 m3;
3330 + uint32 ratio;
3331 + uint32 ratio_parm;
3332 + } n4m_table_t;
3333 +
3334 + n4m_table_t type2_table[] = {
3335 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 0x94, 0x012a0115 },
3336 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 0x21, 0x0aaa0555 },
3337 + { 200000000, 100000000, 0x0303, 0x01000000, 0x01000600, 0x01000000, 0x05000000, 0x21, 0x0aaa0555 },
3338 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
3339 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
3340 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
3341 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 0x94, 0x012a0115 },
3342 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
3343 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 0x21, 0x0aaa0555 },
3344 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
3345 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 0x94, 0x012a0115 },
3346 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 0x94, 0x012a0115 },
3347 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 0x21, 0x0aaa0555 },
3348 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 0x94, 0x012a0115 },
3349 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 0x21, 0x0aaa0555 },
3350 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 0x94, 0x012a0115 },
3351 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 0x21, 0x0aaa0555 }
3352 + };
3353 +
3354 + n4m_table_t type4_table[] = {
3355 + { 192000000, 96000000, 0x0702, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 0x21, 0x0aaa0555 },
3356 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 0x21, 0x0aaa0555 },
3357 + { 216000000, 108000000, 0x0211, 0x11020005, 0x11030303, 0x11020005, 0x04000005, 0x21, 0x0aaa0555 },
3358 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x11030305, 0x04000005, 0x94, 0x012a00a9 },
3359 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 0x21, 0x0aaa0555 },
3360 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 0x21, 0x0aaa0555 },
3361 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 0x21, 0x0aaa0555 },
3362 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 0x21, 0x0aaa0555 },
3363 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 0x73, 0x254a14a9 },
3364 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 0x73, 0x254a14a9 },
3365 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 0x73, 0x254a14a9 },
3366 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 0x52, 0x02520129 }
3367 + };
3368 + uint icache_size, ic_lsize;
3369 + ulong start, end, dst;
3370 + bool ret = FALSE;
3371 +
3372 + /* get index of the current core */
3373 + idx = sb_coreidx(sbh);
3374 +
3375 + /* switch to extif or chipc core */
3376 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
3377 + pll_type = PLL_TYPE1;
3378 + clockcontrol_n = &eir->clockcontrol_n;
3379 + clockcontrol_sb = &eir->clockcontrol_sb;
3380 + clockcontrol_pci = &eir->clockcontrol_pci;
3381 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
3382 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
3383 + clockcontrol_n = &cc->clockcontrol_n;
3384 + clockcontrol_sb = &cc->clockcontrol_sb;
3385 + clockcontrol_pci = &cc->clockcontrol_pci;
3386 + } else
3387 + goto done;
3388 +
3389 + /* Store the current clock register values */
3390 + orig_n = R_REG(clockcontrol_n);
3391 + orig_sb = R_REG(clockcontrol_sb);
3392 + orig_pci = R_REG(clockcontrol_pci);
3393 +
3394 + if (pll_type == PLL_TYPE1) {
3395 + /* Keep the current PCI clock if not specified */
3396 + if (pciclock == 0) {
3397 + pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
3398 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
3399 + }
3400 +
3401 + /* Search for the closest MIPS clock less than or equal to a preferred value */
3402 + for (i = 0; i < ARRAYSIZE(type1_table); i++) {
3403 + ASSERT(type1_table[i].mipsclock ==
3404 + sb_clock_rate(pll_type, type1_table[i].n, type1_table[i].sb));
3405 + if (type1_table[i].mipsclock > mipsclock)
3406 + break;
3407 + }
3408 + if (i == 0) {
3409 + ret = FALSE;
3410 + goto done;
3411 + } else {
3412 + ret = TRUE;
3413 + i--;
3414 + }
3415 + ASSERT(type1_table[i].mipsclock <= mipsclock);
3416 +
3417 + /* No PLL change */
3418 + if ((orig_n == type1_table[i].n) &&
3419 + (orig_sb == type1_table[i].sb) &&
3420 + (orig_pci == type1_table[i].pci33))
3421 + goto done;
3422 +
3423 + /* Set the PLL controls */
3424 + W_REG(clockcontrol_n, type1_table[i].n);
3425 + W_REG(clockcontrol_sb, type1_table[i].sb);
3426 + if (pciclock == 25000000)
3427 + W_REG(clockcontrol_pci, type1_table[i].pci25);
3428 + else
3429 + W_REG(clockcontrol_pci, type1_table[i].pci33);
3430 +
3431 + /* Reset */
3432 + sb_watchdog(sbh, 1);
3433 + while (1);
3434 + } else if ((pll_type == PLL_TYPE2) || (pll_type == PLL_TYPE4)) {
3435 + n4m_table_t *table = (pll_type == PLL_TYPE2) ? type2_table : type4_table;
3436 + uint tabsz = (pll_type == PLL_TYPE2) ? ARRAYSIZE(type2_table) : ARRAYSIZE(type4_table);
3437 +
3438 + ASSERT(cc);
3439 +
3440 + /* Store the current clock register values */
3441 + orig_m2 = R_REG(&cc->clockcontrol_m2);
3442 + orig_mips = R_REG(&cc->clockcontrol_mips);
3443 + orig_ratio_parm = 0;
3444 +
3445 + /* Look up current ratio */
3446 + for (i = 0; i < tabsz; i++) {
3447 + if ((orig_n == table[i].n) &&
3448 + (orig_sb == table[i].sb) &&
3449 + (orig_pci == table[i].pci33) &&
3450 + (orig_m2 == table[i].m2) &&
3451 + (orig_mips == table[i].m3)) {
3452 + orig_ratio_parm = table[i].ratio_parm;
3453 + break;
3454 + }
3455 + }
3456 +
3457 + /* Search for the closest MIPS clock greater or equal to a preferred value */
3458 + for (i = 0; i < tabsz; i++) {
3459 + ASSERT(table[i].mipsclock ==
3460 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
3461 + if ((mipsclock <= table[i].mipsclock) &&
3462 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
3463 + break;
3464 + }
3465 + if (i == tabsz) {
3466 + ret = FALSE;
3467 + goto done;
3468 + } else {
3469 + ret = TRUE;
3470 + }
3471 +
3472 + /* No PLL change */
3473 + if ((orig_n == table[i].n) &&
3474 + (orig_sb == table[i].sb) &&
3475 + (orig_pci == table[i].pci33) &&
3476 + (orig_m2 == table[i].m2) &&
3477 + (orig_mips == table[i].m3))
3478 + goto done;
3479 +
3480 + /* Set the PLL controls */
3481 + W_REG(clockcontrol_n, table[i].n);
3482 + W_REG(clockcontrol_sb, table[i].sb);
3483 + W_REG(clockcontrol_pci, table[i].pci33);
3484 + W_REG(&cc->clockcontrol_m2, table[i].m2);
3485 + W_REG(&cc->clockcontrol_mips, table[i].m3);
3486 +
3487 + /* No ratio change */
3488 + if (orig_ratio_parm == table[i].ratio_parm)
3489 + goto end_fill;
3490 +
3491 + new_ratio = table[i].ratio_parm;
3492 +
3493 + icache_probe(&icache_size, &ic_lsize);
3494 +
3495 + /* Preload the code into the cache */
3496 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
3497 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
3498 + while (start < end) {
3499 + cache_unroll(start, Fill_I);
3500 + start += ic_lsize;
3501 + }
3502 +
3503 + /* Copy the handler */
3504 + start = (ulong) &handler;
3505 + end = (ulong) &afterhandler;
3506 + dst = KSEG1ADDR(0x180);
3507 + for (i = 0; i < (end - start); i += 4)
3508 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
3509 +
3510 + /* Preload handler into the cache one line at a time */
3511 + for (i = 0; i < (end - start); i += 4)
3512 + cache_unroll(dst + i, Fill_I);
3513 +
3514 + /* Clear BEV bit */
3515 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
3516 +
3517 + /* Enable interrupts */
3518 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
3519 +
3520 + /* Enable MIPS timer interrupt */
3521 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
3522 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
3523 + ASSERT(mipsr);
3524 + W_REG(&mipsr->intmask, 1);
3525 +
3526 + start_fill:
3527 + /* step 1, set clock ratios */
3528 + MTC0(C0_BROADCOM, 3, new_ratio);
3529 + MTC0(C0_BROADCOM, 1, 8);
3530 +
3531 + /* step 2: program timer intr */
3532 + W_REG(&mipsr->timer, 100);
3533 + (void) R_REG(&mipsr->timer);
3534 +
3535 + /* step 3, switch to async */
3536 + sync_mode = MFC0(C0_BROADCOM, 4);
3537 + MTC0(C0_BROADCOM, 4, 1 << 22);
3538 +
3539 + /* step 4, set cfg active */
3540 + MTC0(C0_BROADCOM, 2, 0x9);
3541 +
3542 +
3543 + /* steps 5 & 6 */
3544 + __asm__ __volatile__ (
3545 + ".set\tmips3\n\t"
3546 + "wait\n\t"
3547 + ".set\tmips0"
3548 + );
3549 +
3550 + /* step 7, clear cfg_active */
3551 + MTC0(C0_BROADCOM, 2, 0);
3552 +
3553 + /* Additional Step: set back to orig sync mode */
3554 + MTC0(C0_BROADCOM, 4, sync_mode);
3555 +
3556 + /* step 8, fake soft reset */
3557 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
3558 +
3559 + end_fill:
3560 + /* step 9 set watchdog timer */
3561 + sb_watchdog(sbh, 20);
3562 + (void) R_REG(&cc->chipid);
3563 +
3564 + /* step 11 */
3565 + __asm__ __volatile__ (
3566 + ".set\tmips3\n\t"
3567 + "sync\n\t"
3568 + "wait\n\t"
3569 + ".set\tmips0"
3570 + );
3571 + while (1);
3572 + }
3573 +
3574 +done:
3575 + /* switch back to previous core */
3576 + sb_setcoreidx(sbh, idx);
3577 +
3578 + return ret;
3579 +}
3580 +
3581 +
3582 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
3583 +uint32
3584 +sb_memc_get_ncdl(void *sbh)
3585 +{
3586 + sbmemcregs_t *memc;
3587 + uint32 ret = 0;
3588 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
3589 + uint idx, rev;
3590 +
3591 + idx = sb_coreidx(sbh);
3592 +
3593 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
3594 + if (memc == 0)
3595 + goto out;
3596 +
3597 + rev = sb_corerev(sbh);
3598 +
3599 + config = R_REG(&memc->config);
3600 + wr = R_REG(&memc->wrncdlcor);
3601 + rd = R_REG(&memc->rdncdlcor);
3602 + misc = R_REG(&memc->miscdlyctl);
3603 + dqsg = R_REG(&memc->dqsgatencdl);
3604 +
3605 + rd &= MEMC_RDNCDLCOR_RD_MASK;
3606 + wr &= MEMC_WRNCDLCOR_WR_MASK;
3607 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
3608 +
3609 + if (config & MEMC_CONFIG_DDR) {
3610 + ret = (wr << 16) | (rd << 8) | dqsg;
3611 + } else {
3612 + if (rev > 0)
3613 + cd = rd;
3614 + else
3615 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
3616 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
3617 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
3618 + ret = (sm << 16) | (sd << 8) | cd;
3619 + }
3620 +
3621 +out:
3622 + /* switch back to previous core */
3623 + sb_setcoreidx(sbh, idx);
3624 +
3625 + return ret;
3626 +}
3627 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/broadcom/sbpci.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/sbpci.c
3628 --- linux-2.6.12.5/arch/mips/bcm947xx/broadcom/sbpci.c 1970-01-01 01:00:00.000000000 +0100
3629 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/sbpci.c 2005-08-28 11:12:20.479851704 +0200
3630 @@ -0,0 +1,530 @@
3631 +/*
3632 + * Low-Level PCI and SB support for BCM47xx
3633 + *
3634 + * Copyright 2001-2003, Broadcom Corporation
3635 + * All Rights Reserved.
3636 + *
3637 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3638 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3639 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3640 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3641 + *
3642 + * $Id: sbpci.c,v 1.2 2005/02/28 13:34:25 jolt Exp $
3643 + */
3644 +
3645 +#include <typedefs.h>
3646 +#include <pcicfg.h>
3647 +#include <bcmdevs.h>
3648 +#include <sbconfig.h>
3649 +#include <sbpci.h>
3650 +#include <osl.h>
3651 +#include <bcmendian.h>
3652 +#include <bcmutils.h>
3653 +#include <sbutils.h>
3654 +#include <bcmnvram.h>
3655 +#include <hndmips.h>
3656 +
3657 +/* Can free sbpci_init() memory after boot */
3658 +#ifndef linux
3659 +#define __init
3660 +#endif
3661 +
3662 +/* Emulated configuration space */
3663 +static pci_config_regs sb_config_regs[SB_MAXCORES];
3664 +
3665 +/* Banned cores */
3666 +static uint16 pci_ban[32] = { 0 };
3667 +static uint pci_banned = 0;
3668 +
3669 +/* CardBus mode */
3670 +static bool cardbus = FALSE;
3671 +
3672 +/*
3673 + * Functions for accessing external PCI configuration space
3674 + */
3675 +
3676 +/* Assume one-hot slot wiring */
3677 +#define PCI_SLOT_MAX 16
3678 +
3679 +static uint32
3680 +config_cmd(void *sbh, uint bus, uint dev, uint func, uint off)
3681 +{
3682 + uint coreidx;
3683 + sbpciregs_t *regs;
3684 + uint32 addr = 0;
3685 +
3686 + /* CardBusMode supports only one device */
3687 + if (cardbus && dev > 1)
3688 + return 0;
3689 +
3690 + coreidx = sb_coreidx(sbh);
3691 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
3692 +
3693 + /* Type 0 transaction */
3694 + if (bus == 1) {
3695 + /* Skip unwired slots */
3696 + if (dev < PCI_SLOT_MAX) {
3697 + /* Slide the PCI window to the appropriate slot */
3698 + W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
3699 + addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
3700 + (func << 8) | (off & ~3);
3701 + }
3702 + }
3703 +
3704 + /* Type 1 transaction */
3705 + else {
3706 + W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
3707 + addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
3708 + }
3709 +
3710 + sb_setcoreidx(sbh, coreidx);
3711 +
3712 + return addr;
3713 +}
3714 +
3715 +static int
3716 +extpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
3717 +{
3718 + uint32 addr, *reg = NULL, val;
3719 + int ret = 0;
3720 +
3721 + if (!(addr = config_cmd(sbh, bus, dev, func, off)) ||
3722 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
3723 + BUSPROBE(val, reg))
3724 + val = 0xffffffff;
3725 +
3726 + val >>= 8 * (off & 3);
3727 + if (len == 4)
3728 + *((uint32 *) buf) = val;
3729 + else if (len == 2)
3730 + *((uint16 *) buf) = (uint16) val;
3731 + else if (len == 1)
3732 + *((uint8 *) buf) = (uint8) val;
3733 + else
3734 + ret = -1;
3735 +
3736 + if (reg)
3737 + REG_UNMAP(reg);
3738 +
3739 + return ret;
3740 +}
3741 +
3742 +static int
3743 +extpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
3744 +{
3745 + uint32 addr, *reg = NULL, val;
3746 + int ret = 0;
3747 +
3748 + if (!(addr = config_cmd(sbh, bus, dev, func, off)) ||
3749 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
3750 + BUSPROBE(val, reg))
3751 + goto done;
3752 +
3753 + if (len == 4)
3754 + val = *((uint32 *) buf);
3755 + else if (len == 2) {
3756 + val &= ~(0xffff << (8 * (off & 3)));
3757 + val |= *((uint16 *) buf) << (8 * (off & 3));
3758 + } else if (len == 1) {
3759 + val &= ~(0xff << (8 * (off & 3)));
3760 + val |= *((uint8 *) buf) << (8 * (off & 3));
3761 + } else
3762 + ret = -1;
3763 +
3764 + W_REG(reg, val);
3765 +
3766 + done:
3767 + if (reg)
3768 + REG_UNMAP(reg);
3769 +
3770 + return ret;
3771 +}
3772 +
3773 +/*
3774 + * Functions for accessing translated SB configuration space
3775 + */
3776 +
3777 +static int
3778 +sb_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
3779 +{
3780 + pci_config_regs *cfg;
3781 +
3782 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
3783 + return -1;
3784 + cfg = &sb_config_regs[dev];
3785 +
3786 + ASSERT(ISALIGNED(off, len));
3787 + ASSERT(ISALIGNED(buf, len));
3788 +
3789 + if (len == 4)
3790 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
3791 + else if (len == 2)
3792 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
3793 + else if (len == 1)
3794 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
3795 + else
3796 + return -1;
3797 +
3798 + return 0;
3799 +}
3800 +
3801 +static int
3802 +sb_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
3803 +{
3804 + uint coreidx, n;
3805 + void *regs;
3806 + sbconfig_t *sb;
3807 + pci_config_regs *cfg;
3808 +
3809 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
3810 + return -1;
3811 + cfg = &sb_config_regs[dev];
3812 +
3813 + ASSERT(ISALIGNED(off, len));
3814 + ASSERT(ISALIGNED(buf, len));
3815 +
3816 + /* Emulate BAR sizing */
3817 + if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
3818 + len == 4 && *((uint32 *) buf) == ~0) {
3819 + coreidx = sb_coreidx(sbh);
3820 + if ((regs = sb_setcoreidx(sbh, dev))) {
3821 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
3822 + /* Highest numbered address match register */
3823 + n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
3824 + if (off == OFFSETOF(pci_config_regs, base[0]))
3825 + cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
3826 + /*else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
3827 + cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
3828 + else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
3829 + cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
3830 + else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
3831 + cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);*/
3832 + }
3833 + sb_setcoreidx(sbh, coreidx);
3834 + return 0;
3835 + }
3836 +
3837 + if (len == 4)
3838 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
3839 + else if (len == 2)
3840 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
3841 + else if (len == 1)
3842 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
3843 + else
3844 + return -1;
3845 +
3846 + return 0;
3847 +}
3848 +
3849 +int
3850 +sbpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
3851 +{
3852 + if (bus == 0)
3853 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
3854 + else
3855 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
3856 +}
3857 +
3858 +int
3859 +sbpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
3860 +{
3861 + if (bus == 0)
3862 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
3863 + else
3864 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
3865 +}
3866 +
3867 +void
3868 +sbpci_ban(uint16 core)
3869 +{
3870 + if (pci_banned < ARRAYSIZE(pci_ban))
3871 + pci_ban[pci_banned++] = core;
3872 +}
3873 +
3874 +int __init
3875 +sbpci_init(void *sbh)
3876 +{
3877 + uint chip, chiprev, chippkg, coreidx, host, i;
3878 + sbpciregs_t *pci;
3879 + sbconfig_t *sb;
3880 + pci_config_regs *cfg;
3881 + void *regs;
3882 + char varname[8];
3883 + uint wlidx = 0;
3884 + uint16 vendor, core;
3885 + uint8 class, subclass, progif;
3886 + uint32 val;
3887 + uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
3888 + uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
3889 +
3890 + chip = sb_chip(sbh);
3891 + chiprev = sb_chiprev(sbh);
3892 + chippkg = sb_chippkg(sbh);
3893 + coreidx = sb_coreidx(sbh);
3894 +
3895 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0)))
3896 + return -1;
3897 + sb_core_reset(sbh, 0);
3898 +
3899 + if (((chip == BCM4310_DEVICE_ID) && (chiprev == 0)) ||
3900 + ((chip == BCM4712_DEVICE_ID) && (chippkg == BCM4712SMALL_PKG_ID)))
3901 + host = 0;
3902 + else
3903 + host = !BUSPROBE(val, &pci->control);
3904 +
3905 + if (!host) {
3906 + /* Disable PCI interrupts in client mode */
3907 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
3908 + W_REG(&sb->sbintvec, 0);
3909 +
3910 + /* Disable the PCI bridge in client mode */
3911 + sbpci_ban(SB_PCI);
3912 + printf("PCI: Disabled\n");
3913 + } else {
3914 + /* Reset the external PCI bus and enable the clock */
3915 + W_REG(&pci->control, 0x5); /* enable the tristate drivers */
3916 + W_REG(&pci->control, 0xd); /* enable the PCI clock */
3917 + OSL_DELAY(100); /* delay 100 us */
3918 + W_REG(&pci->control, 0xf); /* deassert PCI reset */
3919 + W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
3920 + OSL_DELAY(1); /* delay 1 us */
3921 +
3922 + /* Enable CardBusMode */
3923 + cardbus = nvram_match("cardbus", "1");
3924 + if (cardbus) {
3925 + printf("PCI: Enabling CardBus\n");
3926 + /* GPIO 1 resets the CardBus device on bcm94710ap */
3927 + sb_gpioout(sbh, 1, 1);
3928 + sb_gpioouten(sbh, 1, 1);
3929 + W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
3930 + }
3931 +
3932 + /* 64 MB I/O access window */
3933 + W_REG(&pci->sbtopci0, SBTOPCI_IO);
3934 + /* 64 MB configuration access window */
3935 + W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
3936 + /* 1 GB memory access window */
3937 + W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
3938 +
3939 + /* Enable PCI bridge BAR0 prefetch and burst */
3940 + val = 6;
3941 + sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
3942 +
3943 + /* Enable PCI interrupts */
3944 + W_REG(&pci->intmask, PCI_INTA);
3945 + }
3946 +
3947 + /* Scan the SB bus */
3948 + bzero(sb_config_regs, sizeof(sb_config_regs));
3949 + for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
3950 + cfg->vendor = 0xffff;
3951 + if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
3952 + continue;
3953 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
3954 +
3955 + /* Read ID register and parse vendor and core */
3956 + val = R_REG(&sb->sbidhigh);
3957 + vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
3958 + core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
3959 + progif = 0;
3960 +
3961 + /* Check if this core is banned */
3962 + for (i = 0; i < pci_banned; i++)
3963 + if (core == pci_ban[i])
3964 + break;
3965 + if (i < pci_banned)
3966 + continue;
3967 +
3968 + /* Known vendor translations */
3969 + switch (vendor) {
3970 + case SB_VEND_BCM:
3971 + vendor = VENDOR_BROADCOM;
3972 + break;
3973 + }
3974 +
3975 + /* Determine class based on known core codes */
3976 + switch (core) {
3977 + case SB_ILINE20:
3978 + class = PCI_CLASS_NET;
3979 + subclass = PCI_NET_ETHER;
3980 + core = BCM47XX_ILINE_ID;
3981 + break;
3982 + case SB_ILINE100:
3983 + class = PCI_CLASS_NET;
3984 + subclass = PCI_NET_ETHER;
3985 + core = BCM4610_ILINE_ID;
3986 + break;
3987 + case SB_ENET:
3988 + class = PCI_CLASS_NET;
3989 + subclass = PCI_NET_ETHER;
3990 + core = BCM47XX_ENET_ID;
3991 + break;
3992 + case SB_SDRAM:
3993 + case SB_MEMC:
3994 + class = PCI_CLASS_MEMORY;
3995 + subclass = PCI_MEMORY_RAM;
3996 + break;
3997 + case SB_PCI:
3998 + class = PCI_CLASS_BRIDGE;
3999 + subclass = PCI_BRIDGE_PCI;
4000 + //break;
4001 + case SB_MIPS:
4002 + case SB_MIPS33:
4003 + class = PCI_CLASS_CPU;
4004 + subclass = PCI_CPU_MIPS;
4005 + break;
4006 + case SB_CODEC:
4007 + class = PCI_CLASS_COMM;
4008 + subclass = PCI_COMM_MODEM;
4009 + core = BCM47XX_V90_ID;
4010 + break;
4011 + case SB_USB:
4012 + class = PCI_CLASS_SERIAL;
4013 + subclass = PCI_SERIAL_USB;
4014 + progif = 0x10; /* OHCI */
4015 + core = BCM47XX_USB_ID;
4016 + break;
4017 + case SB_USB11H:
4018 + class = PCI_CLASS_SERIAL;
4019 + subclass = PCI_SERIAL_USB;
4020 + progif = 0x10; /* OHCI */
4021 + core = BCM47XX_USBH_ID;
4022 + break;
4023 + case SB_USB11D:
4024 + class = PCI_CLASS_SERIAL;
4025 + subclass = PCI_SERIAL_USB;
4026 + core = BCM47XX_USBD_ID;
4027 + break;
4028 + case SB_IPSEC:
4029 + class = PCI_CLASS_CRYPT;
4030 + subclass = PCI_CRYPT_NETWORK;
4031 + core = BCM47XX_IPSEC_ID;
4032 + break;
4033 + case SB_EXTIF:
4034 + case SB_CC:
4035 + class = PCI_CLASS_MEMORY;
4036 + subclass = PCI_MEMORY_FLASH;
4037 + break;
4038 + case SB_D11:
4039 + class = PCI_CLASS_NET;
4040 + subclass = PCI_NET_OTHER;
4041 + /* Let an nvram variable override this */
4042 + sprintf(varname, "wl%did", wlidx);
4043 + wlidx++;
4044 + if ((core = getintvar(NULL, varname)) == 0) {
4045 + if (chip == BCM4712_DEVICE_ID) {
4046 + if (chippkg == BCM4712SMALL_PKG_ID)
4047 + core = BCM4306_D11G_ID;
4048 + else
4049 + core = BCM4306_D11DUAL_ID;
4050 + } else {
4051 + /* 4310 */
4052 + core = BCM4310_D11B_ID;
4053 + }
4054 + }
4055 + break;
4056 +
4057 + default:
4058 + class = subclass = progif = 0xff;
4059 + break;
4060 + }
4061 +
4062 + /* Supported translations */
4063 + cfg->vendor = htol16(vendor);
4064 + cfg->device = htol16(core);
4065 + cfg->rev_id = chiprev;
4066 + cfg->prog_if = progif;
4067 + cfg->sub_class = subclass;
4068 + cfg->base_class = class;
4069 + cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
4070 + cfg->base[1] = 0/*htol32(sb_base(R_REG(&sb->sbadmatch1)))*/;
4071 + cfg->base[2] = 0/*htol32(sb_base(R_REG(&sb->sbadmatch2)))*/;
4072 + cfg->base[3] = 0/*htol32(sb_base(R_REG(&sb->sbadmatch3)))*/;
4073 + cfg->base[4] = 0;
4074 + cfg->base[5] = 0;
4075 + if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
4076 + cfg->header_type = PCI_HEADER_BRIDGE;
4077 + else
4078 + cfg->header_type = PCI_HEADER_NORMAL;
4079 + /* Save core interrupt flag */
4080 + cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
4081 + /* Default to MIPS shared interrupt 0 */
4082 + cfg->int_line = 0;
4083 + /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
4084 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
4085 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
4086 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
4087 + val = R_REG(&sb->sbipsflag);
4088 + for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
4089 + if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
4090 + break;
4091 + }
4092 + if (cfg->int_line > 4)
4093 + cfg->int_line = 0;
4094 + }
4095 + /* Emulated core */
4096 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
4097 + }
4098 +
4099 + sb_setcoreidx(sbh, coreidx);
4100 + return 0;
4101 +}
4102 +
4103 +void
4104 +sbpci_check(void *sbh)
4105 +{
4106 + uint coreidx;
4107 + sbpciregs_t *pci;
4108 + uint32 sbtopci1;
4109 + uint32 buf[64], *ptr, i;
4110 + ulong pa;
4111 + volatile uint j;
4112 +
4113 + coreidx = sb_coreidx(sbh);
4114 + pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
4115 +
4116 + /* Clear the test array */
4117 + pa = (ulong) DMA_MAP(NULL, buf, sizeof(buf), DMA_RX, NULL);
4118 + ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
4119 + memset(ptr, 0, sizeof(buf));
4120 +
4121 + /* Point PCI window 1 to memory */
4122 + sbtopci1 = R_REG(&pci->sbtopci1);
4123 + W_REG(&pci->sbtopci1, SBTOPCI_MEM | (pa & SBTOPCI1_MASK));
4124 +
4125 + /* Fill the test array via PCI window 1 */
4126 + ptr = (uint32 *) REG_MAP(SB_PCI_CFG + (pa & ~SBTOPCI1_MASK), sizeof(buf));
4127 + for (i = 0; i < ARRAYSIZE(buf); i++) {
4128 + for (j = 0; j < 2; j++);
4129 + W_REG(&ptr[i], i);
4130 + }
4131 + REG_UNMAP(ptr);
4132 +
4133 + /* Restore PCI window 1 */
4134 + W_REG(&pci->sbtopci1, sbtopci1);
4135 +
4136 + /* Check the test array */
4137 + DMA_UNMAP(NULL, pa, sizeof(buf), DMA_RX, NULL);
4138 + ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
4139 + for (i = 0; i < ARRAYSIZE(buf); i++) {
4140 + if (ptr[i] != i)
4141 + break;
4142 + }
4143 +
4144 + /* Change the clock if the test fails */
4145 + if (i < ARRAYSIZE(buf)) {
4146 + uint32 req, cur;
4147 +
4148 + cur = sb_clock(sbh);
4149 + printf("PCI: Test failed at %d MHz\n", (cur + 500000) / 1000000);
4150 + for (req = 104000000; req < 176000000; req += 4000000) {
4151 + printf("PCI: Resetting to %d MHz\n", (req + 500000) / 1000000);
4152 + /* This will only reset if the clocks are valid and have changed */
4153 + sb_mips_setclock(sbh, req, 0, 0);
4154 + }
4155 + /* Should not reach here */
4156 + ASSERT(0);
4157 + }
4158 +
4159 + sb_setcoreidx(sbh, coreidx);
4160 +}
4161 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/broadcom/sbutils.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/sbutils.c
4162 --- linux-2.6.12.5/arch/mips/bcm947xx/broadcom/sbutils.c 1970-01-01 01:00:00.000000000 +0100
4163 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/sbutils.c 2005-08-28 11:12:20.482851248 +0200
4164 @@ -0,0 +1,1895 @@
4165 +/*
4166 + * Misc utility routines for accessing chip-specific features
4167 + * of the SiliconBackplane-based Broadcom chips.
4168 + *
4169 + * Copyright 2001-2003, Broadcom Corporation
4170 + * All Rights Reserved.
4171 + *
4172 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4173 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4174 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4175 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4176 + *
4177 + * $Id: sbutils.c,v 1.1 2005/02/28 13:33:32 jolt Exp $
4178 + */
4179 +
4180 +#include <typedefs.h>
4181 +#include <osl.h>
4182 +#include <bcmutils.h>
4183 +#include <bcmdevs.h>
4184 +#include <sbconfig.h>
4185 +#include <sbchipc.h>
4186 +#include <sbpci.h>
4187 +#include <pcicfg.h>
4188 +#include <sbpcmcia.h>
4189 +#include <sbextif.h>
4190 +#include <sbutils.h>
4191 +#include <bcmsrom.h>
4192 +
4193 +/* debug/trace */
4194 +#define SB_ERROR(args)
4195 +
4196 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
4197 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
4198 +
4199 +/* misc sb info needed by some of the routines */
4200 +typedef struct sb_info {
4201 + uint chip; /* chip number */
4202 + uint chiprev; /* chip revision */
4203 + uint chippkg; /* chip package option */
4204 + uint boardtype; /* board type */
4205 + uint boardvendor; /* board vendor id */
4206 + uint bus; /* what bus type we are going through */
4207 +
4208 + void *osh; /* osl os handle */
4209 + void *sdh; /* bcmsdh handle */
4210 +
4211 + void *curmap; /* current regs va */
4212 + void *regs[SB_MAXCORES]; /* other regs va */
4213 +
4214 + uint curidx; /* current core index */
4215 + uint dev_coreid; /* the core provides driver functions */
4216 + uint pciidx; /* pci core index */
4217 + uint pcirev; /* pci core rev */
4218 +
4219 + uint pcmciaidx; /* pcmcia core index */
4220 + uint pcmciarev; /* pcmcia core rev */
4221 + bool memseg; /* flag to toggle MEM_SEG register */
4222 +
4223 + uint ccrev; /* chipc core rev */
4224 +
4225 + uint gpioidx; /* gpio control core index */
4226 + uint gpioid; /* gpio control coretype */
4227 +
4228 + uint numcores; /* # discovered cores */
4229 + uint coreid[SB_MAXCORES]; /* id of each core */
4230 +
4231 + void *intr_arg; /* interrupt callback function arg */
4232 + sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
4233 + sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
4234 +} sb_info_t;
4235 +
4236 +/* local prototypes */
4237 +static void* sb_doattach(sb_info_t *si, uint devid, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
4238 +static void sb_scan(sb_info_t *si);
4239 +static uint sb_corereg(void *sbh, uint coreidx, uint regoff, uint mask, uint val);
4240 +static uint _sb_coreidx(void *sbh);
4241 +static uint sb_findcoreidx(void *sbh, uint coreid, uint coreunit);
4242 +static uint sb_pcidev2chip(uint pcidev);
4243 +static uint sb_chip2numcores(uint chip);
4244 +
4245 +#define SB_INFO(sbh) (sb_info_t*)sbh
4246 +#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
4247 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) \
4248 + && ISALIGNED((x), SB_CORE_SIZE))
4249 +#define GOODREGS(regs) (regs && ISALIGNED(regs, SB_CORE_SIZE))
4250 +#define REGS2SB(va) (sbconfig_t*) ((uint)(va) + SBCONFIGOFF)
4251 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
4252 +#define BADIDX (SB_MAXCORES+1)
4253 +
4254 +#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
4255 +#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
4256 +#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
4257 +#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
4258 +
4259 +/*
4260 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
4261 + * after core switching to avoid invalid register accesss inside ISR.
4262 + */
4263 +#define INTR_OFF(si, intr_val) \
4264 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
4265 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
4266 +#define INTR_RESTORE(si, intr_val) \
4267 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
4268 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
4269 +
4270 +/* power control defines */
4271 +#define PLL_DELAY 150 /* 150us pll on delay */
4272 +#define FREF_DELAY 15 /* 15us fref change delay */
4273 +#define LPOMINFREQ 25000 /* low power oscillator min */
4274 +#define LPOMAXFREQ 43000 /* low power oscillator max */
4275 +#define XTALMINFREQ 19800000 /* 20mhz - 1% */
4276 +#define XTALMAXFREQ 20200000 /* 20mhz + 1% */
4277 +#define PCIMINFREQ 25000000 /* 25mhz */
4278 +#define PCIMAXFREQ 34000000 /* 33mhz + fudge */
4279 +
4280 +#define SCC_LOW2FAST_LIMIT 5000 /* turn on fast clock time, in unit of ms */
4281 +
4282 +
4283 +static uint32
4284 +sb_read_sbreg(void *sbh, volatile uint32 *sbr)
4285 +{
4286 + sb_info_t *si;
4287 + uint8 tmp;
4288 + uint32 val, intr_val = 0;
4289 +
4290 + si = SB_INFO(sbh);
4291 +
4292 + /*
4293 + * compact flash only has 11 bits address, while we needs 12 bits address.
4294 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
4295 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
4296 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
4297 + */
4298 + if(si->memseg) {
4299 + INTR_OFF(si, intr_val);
4300 + tmp = 1;
4301 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
4302 + (uint32)sbr &= ~(1 << 11); /* mask out bit 11*/
4303 + }
4304 +
4305 + val = R_REG(sbr);
4306 +
4307 + if(si->memseg) {
4308 + tmp = 0;
4309 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
4310 + INTR_RESTORE(si, intr_val);
4311 + }
4312 +
4313 + return (val);
4314 +}
4315 +
4316 +static void
4317 +sb_write_sbreg(void *sbh, volatile uint32 *sbr, uint32 v)
4318 +{
4319 + sb_info_t *si;
4320 + uint8 tmp;
4321 + volatile uint32 dummy;
4322 + uint32 intr_val = 0;
4323 +
4324 + si = SB_INFO(sbh);
4325 +
4326 + /*
4327 + * compact flash only has 11 bits address, while we needs 12 bits address.
4328 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
4329 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
4330 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
4331 + */
4332 + if(si->memseg) {
4333 + INTR_OFF(si, intr_val);
4334 + tmp = 1;
4335 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
4336 + (uint32)sbr &= ~(1 << 11); /* mask out bit 11 */
4337 + }
4338 +
4339 + if ((si->bus == PCMCIA_BUS) || (si->bus == PCI_BUS)) {
4340 +#ifdef IL_BIGENDIAN
4341 + dummy = R_REG(sbr);
4342 + W_REG((volatile uint16 *)((uint32)sbr + 2), (uint16)((v >> 16) & 0xffff));
4343 + dummy = R_REG(sbr);
4344 + W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
4345 +#else
4346 + dummy = R_REG(sbr);
4347 + W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
4348 + dummy = R_REG(sbr);
4349 + W_REG((volatile uint16 *)((uint32)sbr + 2), (uint16)((v >> 16) & 0xffff));
4350 +#endif
4351 + } else
4352 + W_REG(sbr, v);
4353 +
4354 + if(si->memseg) {
4355 + tmp = 0;
4356 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
4357 + INTR_RESTORE(si, intr_val);
4358 + }
4359 +}
4360 +
4361 +/*
4362 + * Allocate a sb handle.
4363 + * devid - pci device id (used to determine chip#)
4364 + * osh - opaque OS handle
4365 + * regs - virtual address of initial core registers
4366 + * bustype - pci/pcmcia/sb/sdio/etc
4367 + * vars - pointer to a pointer area for "environment" variables
4368 + * varsz - pointer to int to return the size of the vars
4369 + */
4370 +void*
4371 +sb_attach(uint devid, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz)
4372 +{
4373 + sb_info_t *si;
4374 +
4375 + /* alloc sb_info_t */
4376 + if ((si = MALLOC(sizeof (sb_info_t))) == NULL) {
4377 + SB_ERROR(("sb_attach: malloc failed!\n"));
4378 + return (NULL);
4379 + }
4380 +
4381 + return (sb_doattach(si, devid, osh, regs, bustype, sdh, vars, varsz));
4382 +}
4383 +
4384 +/* global kernel resource */
4385 +static sb_info_t ksi;
4386 +
4387 +/* generic kernel variant of sb_attach() */
4388 +void*
4389 +sb_kattach()
4390 +{
4391 + uint32 *regs;
4392 + char *unused;
4393 + int varsz;
4394 +
4395 + if (ksi.curmap == NULL) {
4396 + uint32 cid;
4397 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
4398 + cid = R_REG((uint32 *)regs);
4399 + if ((cid == 0x08104712) || (cid == 0x08114712)) {
4400 + uint32 *scc, val;
4401 +
4402 + scc = (uint32 *)((uint32)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
4403 + val = R_REG(scc);
4404 + SB_ERROR((" initial scc = 0x%x\n", val));
4405 + val |= SCC_SS_XTAL;
4406 + W_REG(scc, val);
4407 + }
4408 +
4409 + sb_doattach(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
4410 + SB_BUS, NULL, &unused, &varsz);
4411 + }
4412 +
4413 + return &ksi;
4414 +}
4415 +
4416 +static void*
4417 +sb_doattach(sb_info_t *si, uint devid, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz)
4418 +{
4419 + uint origidx;
4420 + chipcregs_t *cc;
4421 + uint32 w;
4422 +
4423 + ASSERT(GOODREGS(regs));
4424 +
4425 + bzero((uchar*)si, sizeof (sb_info_t));
4426 +
4427 + si->pciidx = si->gpioidx = BADIDX;
4428 +
4429 + si->osh = osh;
4430 + si->curmap = regs;
4431 + si->sdh = sdh;
4432 +
4433 + /* 4317A0 PCMCIA is no longer supported */
4434 + if ((bustype == PCMCIA_BUS) && (R_REG((uint32 *)regs) == 0x04104317))
4435 + return NULL;
4436 +
4437 + /* check to see if we are a sb core mimic'ing a pci core */
4438 + if (bustype == PCI_BUS) {
4439 + if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
4440 + bustype = SB_BUS;
4441 + else
4442 + bustype = PCI_BUS;
4443 + }
4444 +
4445 + si->bus = bustype;
4446 +
4447 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
4448 + if (si->bus == PCI_BUS)
4449 + sb_pwrctl_xtal((void*)si, XTAL|PLL, ON);
4450 +
4451 + /* clear any previous epidiag-induced target abort */
4452 + sb_taclear((void*)si);
4453 +
4454 + /* initialize current core index value */
4455 + si->curidx = _sb_coreidx((void*)si);
4456 +
4457 + /* keep and reuse the initial register mapping */
4458 + origidx = si->curidx;
4459 + if (si->bus == SB_BUS)
4460 + si->regs[origidx] = regs;
4461 +
4462 + /* initialize the vars */
4463 + if (srom_var_init(si->bus, si->curmap, osh, vars, varsz)) {
4464 + SB_ERROR(("sb_attach: srom_var_init failed\n"));
4465 + goto bad;
4466 + }
4467 +
4468 + if (si->bus == PCMCIA_BUS) {
4469 + w = getintvar(*vars, "regwindowsz");
4470 + si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
4471 + }
4472 +
4473 + /* is core-0 a chipcommon core? */
4474 + si->numcores = 1;
4475 + cc = (chipcregs_t*) sb_setcoreidx((void*)si, 0);
4476 + if (sb_coreid((void*)si) != SB_CC)
4477 + cc = NULL;
4478 +
4479 + /* determine chip id and rev */
4480 + if (cc) {
4481 + /* chip common core found! */
4482 + si->chip = R_REG(&cc->chipid) & CID_ID_MASK;
4483 + si->chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
4484 + si->chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
4485 + } else {
4486 + /* without chip common core, get devid for PCMCIA */
4487 + if (si->bus == PCMCIA_BUS)
4488 + devid = getintvar(*vars, "devid");
4489 +
4490 + /* no chip common core -- must convert device id to chip id */
4491 + if ((si->chip = sb_pcidev2chip(devid)) == 0) {
4492 + SB_ERROR(("sb_attach: unrecognized device id 0x%04x\n", devid));
4493 + goto bad;
4494 + }
4495 +
4496 + /*
4497 + * The chip revision number is hardwired into all
4498 + * of the pci function config rev fields and is
4499 + * independent from the individual core revision numbers.
4500 + * For example, the "A0" silicon of each chip is chip rev 0.
4501 + * For PCMCIA we get it from the CIS instead.
4502 + */
4503 + if (si->bus == PCMCIA_BUS) {
4504 + ASSERT(vars);
4505 + si->chiprev = getintvar(*vars, "chiprev");
4506 + } else if (si->bus == PCI_BUS) {
4507 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
4508 + si->chiprev = w & 0xff;
4509 + } else
4510 + si->chiprev = 0;
4511 + }
4512 +
4513 + /* get chipcommon rev */
4514 + si->ccrev = cc? sb_corerev((void*)si) : 0;
4515 +
4516 + /* determine numcores */
4517 + if ((si->ccrev == 4) || (si->ccrev >= 6))
4518 + si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
4519 + else
4520 + si->numcores = sb_chip2numcores(si->chip);
4521 +
4522 + /* return to original core */
4523 + sb_setcoreidx((void*)si, origidx);
4524 +
4525 + /* sanity checks */
4526 + ASSERT(si->chip);
4527 + /* 4704A1 is chiprev 8 :-( */
4528 + ASSERT((si->chiprev < 8) ||
4529 + ((si->chip == BCM4704_DEVICE_ID) && ((si->chiprev == 8))));
4530 +
4531 + /* scan for cores */
4532 + sb_scan(si);
4533 +
4534 + /* pci core is required */
4535 + if (!GOODIDX(si->pciidx)) {
4536 + SB_ERROR(("sb_attach: pci core not found\n"));
4537 + goto bad;
4538 + }
4539 +
4540 + /* gpio control core is required */
4541 + if (!GOODIDX(si->gpioidx)) {
4542 + SB_ERROR(("sb_attach: gpio control core not found\n"));
4543 + goto bad;
4544 + }
4545 +
4546 + /* get boardtype and boardrev */
4547 + switch (si->bus) {
4548 + case PCI_BUS:
4549 + /* do a pci config read to get subsystem id and subvendor id */
4550 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
4551 + si->boardvendor = w & 0xffff;
4552 + si->boardtype = (w >> 16) & 0xffff;
4553 + break;
4554 +
4555 + case PCMCIA_BUS:
4556 + case SDIO_BUS:
4557 + si->boardvendor = getintvar(*vars, "manfid");
4558 + si->boardtype = getintvar(*vars, "prodid");
4559 + break;
4560 +
4561 + case SB_BUS:
4562 + si->boardvendor = VENDOR_BROADCOM;
4563 + si->boardtype = 0xffff;
4564 + break;
4565 + }
4566 +
4567 + if (si->boardtype == 0) {
4568 + SB_ERROR(("sb_attach: unknown board type\n"));
4569 + ASSERT(si->boardtype);
4570 + }
4571 +
4572 + return ((void*)si);
4573 +
4574 +bad:
4575 + MFREE(si, sizeof (sb_info_t));
4576 + return (NULL);
4577 +}
4578 +
4579 +uint
4580 +sb_coreid(void *sbh)
4581 +{
4582 + sb_info_t *si;
4583 + sbconfig_t *sb;
4584 +
4585 + si = SB_INFO(sbh);
4586 + sb = REGS2SB(si->curmap);
4587 +
4588 + return ((R_SBREG(sbh, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
4589 +}
4590 +
4591 +uint
4592 +sb_coreidx(void *sbh)
4593 +{
4594 + sb_info_t *si;
4595 +
4596 + si = SB_INFO(sbh);
4597 + return (si->curidx);
4598 +}
4599 +
4600 +/* return current index of core */
4601 +static uint
4602 +_sb_coreidx(void *sbh)
4603 +{
4604 + sb_info_t *si;
4605 + sbconfig_t *sb;
4606 + uint32 sbaddr = 0;
4607 +
4608 + si = SB_INFO(sbh);
4609 + ASSERT(si);
4610 +
4611 + switch (si->bus) {
4612 + case SB_BUS:
4613 + sb = REGS2SB(si->curmap);
4614 + sbaddr = sb_base(R_SBREG(sbh, &sb->sbadmatch0));
4615 + break;
4616 +
4617 + case PCI_BUS:
4618 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
4619 + break;
4620 +
4621 + case PCMCIA_BUS: {
4622 + uint8 tmp;
4623 +
4624 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
4625 + sbaddr = (uint)tmp << 12;
4626 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
4627 + sbaddr |= (uint)tmp << 16;
4628 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
4629 + sbaddr |= (uint)tmp << 24;
4630 + break;
4631 + }
4632 + default:
4633 + ASSERT(0);
4634 + }
4635 +
4636 + ASSERT(GOODCOREADDR(sbaddr));
4637 + return ((sbaddr - SB_ENUM_BASE)/SB_CORE_SIZE);
4638 +}
4639 +
4640 +uint
4641 +sb_corevendor(void *sbh)
4642 +{
4643 + sb_info_t *si;
4644 + sbconfig_t *sb;
4645 +
4646 + si = SB_INFO(sbh);
4647 + sb = REGS2SB(si->curmap);
4648 +
4649 + return ((R_SBREG(sbh, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
4650 +}
4651 +
4652 +uint
4653 +sb_corerev(void *sbh)
4654 +{
4655 + sb_info_t *si;
4656 + sbconfig_t *sb;
4657 +
4658 + si = SB_INFO(sbh);
4659 + sb = REGS2SB(si->curmap);
4660 +
4661 + return (R_SBREG(sbh, &(sb)->sbidhigh) & SBIDH_RC_MASK);
4662 +}
4663 +
4664 +#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
4665 +
4666 +/* set/clear sbtmstatelow core-specific flags */
4667 +uint32
4668 +sb_coreflags(void *sbh, uint32 mask, uint32 val)
4669 +{
4670 + sb_info_t *si;
4671 + sbconfig_t *sb;
4672 + uint32 w;
4673 +
4674 + si = SB_INFO(sbh);
4675 + sb = REGS2SB(si->curmap);
4676 +
4677 + ASSERT((val & ~mask) == 0);
4678 + ASSERT((mask & ~SBTML_ALLOW) == 0);
4679 +
4680 + /* mask and set */
4681 + if (mask || val) {
4682 + w = (R_SBREG(sbh, &sb->sbtmstatelow) & ~mask) | val;
4683 + W_SBREG(sbh, &sb->sbtmstatelow, w);
4684 + }
4685 +
4686 + /* return the new value */
4687 + return (R_SBREG(sbh, &sb->sbtmstatelow) & SBTML_ALLOW);
4688 +}
4689 +
4690 +/* set/clear sbtmstatehigh core-specific flags */
4691 +uint32
4692 +sb_coreflagshi(void *sbh, uint32 mask, uint32 val)
4693 +{
4694 + sb_info_t *si;
4695 + sbconfig_t *sb;
4696 + uint32 w;
4697 +
4698 + si = SB_INFO(sbh);
4699 + sb = REGS2SB(si->curmap);
4700 +
4701 + ASSERT((val & ~mask) == 0);
4702 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
4703 +
4704 + /* mask and set */
4705 + if (mask || val) {
4706 + w = (R_SBREG(sbh, &sb->sbtmstatehigh) & ~mask) | val;
4707 + W_SBREG(sbh, &sb->sbtmstatehigh, w);
4708 + }
4709 +
4710 + /* return the new value */
4711 + return (R_SBREG(sbh, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
4712 +}
4713 +
4714 +bool
4715 +sb_iscoreup(void *sbh)
4716 +{
4717 + sb_info_t *si;
4718 + sbconfig_t *sb;
4719 +
4720 + si = SB_INFO(sbh);
4721 + sb = REGS2SB(si->curmap);
4722 +
4723 + return ((R_SBREG(sbh, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK);
4724 +}
4725 +
4726 +/*
4727 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
4728 + * switch back to the original core, and return the new value.
4729 + */
4730 +static uint
4731 +sb_corereg(void *sbh, uint coreidx, uint regoff, uint mask, uint val)
4732 +{
4733 + sb_info_t *si;
4734 + uint origidx;
4735 + uint32 *r;
4736 + uint w;
4737 + uint intr_val = 0;
4738 +
4739 + ASSERT(GOODIDX(coreidx));
4740 + ASSERT(regoff < SB_CORE_SIZE);
4741 + ASSERT((val & ~mask) == 0);
4742 +
4743 + si = SB_INFO(sbh);
4744 +
4745 + /* save current core index */
4746 + origidx = sb_coreidx(sbh);
4747 +
4748 + /* switch core */
4749 + INTR_OFF(si, intr_val);
4750 + r = (uint32*) ((uint) sb_setcoreidx(sbh, coreidx) + regoff);
4751 +
4752 + /* mask and set */
4753 + if (mask || val) {
4754 + if (regoff >= SBCONFIGOFF) {
4755 + w = (R_SBREG(sbh, r) & ~mask) | val;
4756 + W_SBREG(sbh, r, w);
4757 + } else {
4758 + w = (R_REG(r) & ~mask) | val;
4759 + W_REG(r, w);
4760 + }
4761 + }
4762 +
4763 + /* readback */
4764 + w = R_SBREG(sbh, r);
4765 +
4766 + /* restore core index */
4767 + if (origidx != coreidx)
4768 + sb_setcoreidx(sbh, origidx);
4769 +
4770 + INTR_RESTORE(si, intr_val);
4771 + return (w);
4772 +}
4773 +
4774 +/* scan the sb enumerated space to identify all cores */
4775 +static void
4776 +sb_scan(sb_info_t *si)
4777 +{
4778 + void *sbh;
4779 + uint origidx;
4780 + uint i;
4781 +
4782 + sbh = (void*) si;
4783 +
4784 + /* numcores should already be set */
4785 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
4786 +
4787 + /* save current core index */
4788 + origidx = sb_coreidx(sbh);
4789 +
4790 + si->pciidx = si->gpioidx = BADIDX;
4791 +
4792 + for (i = 0; i < si->numcores; i++) {
4793 + sb_setcoreidx(sbh, i);
4794 + si->coreid[i] = sb_coreid(sbh);
4795 +
4796 + if (si->coreid[i] == SB_CC)
4797 + si->ccrev = sb_corerev(sbh);
4798 +
4799 + else if (si->coreid[i] == SB_PCI) {
4800 + si->pciidx = i;
4801 + si->pcirev = sb_corerev(sbh);
4802 +
4803 + }else if (si->coreid[i] == SB_PCMCIA){
4804 + si->pcmciaidx = i;
4805 + si->pcmciarev = sb_corerev(sbh);
4806 + }
4807 + }
4808 +
4809 + /*
4810 + * Find the gpio "controlling core" type and index.
4811 + * Precedence:
4812 + * - if there's a chip common core - use that
4813 + * - else if there's a pci core (rev >= 2) - use that
4814 + * - else there had better be an extif core (4710 only)
4815 + */
4816 + if (GOODIDX(sb_findcoreidx(sbh, SB_CC, 0))) {
4817 + si->gpioidx = sb_findcoreidx(sbh, SB_CC, 0);
4818 + si->gpioid = SB_CC;
4819 + } else if (GOODIDX(si->pciidx) && (si->pcirev >= 2)) {
4820 + si->gpioidx = si->pciidx;
4821 + si->gpioid = SB_PCI;
4822 + } else if (sb_findcoreidx(sbh, SB_EXTIF, 0)) {
4823 + si->gpioidx = sb_findcoreidx(sbh, SB_EXTIF, 0);
4824 + si->gpioid = SB_EXTIF;
4825 + }
4826 +
4827 + /* return to original core index */
4828 + sb_setcoreidx(sbh, origidx);
4829 +}
4830 +
4831 +/* may be called with core in reset */
4832 +void
4833 +sb_detach(void *sbh)
4834 +{
4835 + sb_info_t *si;
4836 + uint idx;
4837 +
4838 + si = SB_INFO(sbh);
4839 +
4840 + if (si == NULL)
4841 + return;
4842 +
4843 + if (si->bus == SB_BUS)
4844 + for (idx = 0; idx < SB_MAXCORES; idx++)
4845 + if (si->regs[idx]) {
4846 + REG_UNMAP(si->regs[idx]);
4847 + si->regs[idx] = NULL;
4848 + }
4849 +
4850 + MFREE(si, sizeof (sb_info_t));
4851 +}
4852 +
4853 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
4854 +static uint
4855 +sb_pcidev2chip(uint pcidev)
4856 +{
4857 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
4858 + return (BCM4710_DEVICE_ID);
4859 + if ((pcidev >= BCM4610_DEVICE_ID) && (pcidev <= BCM4610_USB_ID))
4860 + return (BCM4610_DEVICE_ID);
4861 + if ((pcidev >= BCM4402_DEVICE_ID) && (pcidev <= BCM4402_V90_ID))
4862 + return (BCM4402_DEVICE_ID);
4863 + if ((pcidev >= BCM4307_V90_ID) && (pcidev <= BCM4307_D11B_ID))
4864 + return (BCM4307_DEVICE_ID);
4865 + if (pcidev == BCM4301_DEVICE_ID)
4866 + return (BCM4301_DEVICE_ID);
4867 +
4868 + return (0);
4869 +}
4870 +
4871 +/* convert chip number to number of i/o cores */
4872 +static uint
4873 +sb_chip2numcores(uint chip)
4874 +{
4875 + if (chip == 0x4710)
4876 + return (9);
4877 + if (chip == 0x4610)
4878 + return (9);
4879 + if (chip == 0x4402)
4880 + return (3);
4881 + if ((chip == 0x4307) || (chip == 0x4301))
4882 + return (5);
4883 + if (chip == 0x4310)
4884 + return (8);
4885 + if (chip == 0x4306) /* < 4306c0 */
4886 + return (6);
4887 + if (chip == 0x4704)
4888 + return (9);
4889 + if (chip == 0x5365)
4890 + return (7);
4891 +
4892 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
4893 + ASSERT(0);
4894 + return (1);
4895 +}
4896 +
4897 +/* return index of coreid or BADIDX if not found */
4898 +static uint
4899 +sb_findcoreidx(void *sbh, uint coreid, uint coreunit)
4900 +{
4901 + sb_info_t *si;
4902 + uint found;
4903 + uint i;
4904 +
4905 + si = SB_INFO(sbh);
4906 + found = 0;
4907 +
4908 + for (i = 0; i < si->numcores; i++)
4909 + if (si->coreid[i] == coreid) {
4910 + if (found == coreunit)
4911 + return (i);
4912 + found++;
4913 + }
4914 +
4915 + return (BADIDX);
4916 +}
4917 +
4918 +/* change logical "focus" to the indiciated core */
4919 +void*
4920 +sb_setcoreidx(void *sbh, uint coreidx)
4921 +{
4922 + sb_info_t *si;
4923 + uint32 sbaddr;
4924 + uint8 tmp;
4925 +
4926 + si = SB_INFO(sbh);
4927 +
4928 + if (coreidx >= si->numcores)
4929 + return (NULL);
4930 +
4931 + /*
4932 + * If the user has provided an interrupt mask enabled function,
4933 + * then assert interrupts are disabled before switching the core.
4934 + */
4935 + ASSERT((si->imf == NULL) || !(*si->imf)(si->imfarg));
4936 +
4937 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
4938 +
4939 + switch (si->bus) {
4940 + case SB_BUS:
4941 + /* map new one */
4942 + if (!si->regs[coreidx]) {
4943 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
4944 + ASSERT(GOODREGS(si->regs[coreidx]));
4945 + }
4946 + si->curmap = si->regs[coreidx];
4947 + break;
4948 +
4949 + case PCI_BUS:
4950 + /* point bar0 window */
4951 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
4952 + break;
4953 +
4954 + case PCMCIA_BUS:
4955 + tmp = (sbaddr >> 12) & 0x0f;
4956 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
4957 + tmp = (sbaddr >> 16) & 0xff;
4958 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
4959 + tmp = (sbaddr >> 24) & 0xff;
4960 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
4961 + break;
4962 + }
4963 +
4964 + si->curidx = coreidx;
4965 +
4966 + return (si->curmap);
4967 +}
4968 +
4969 +/* change logical "focus" to the indicated core */
4970 +void*
4971 +sb_setcore(void *sbh, uint coreid, uint coreunit)
4972 +{
4973 + sb_info_t *si;
4974 + uint idx;
4975 +
4976 + si = SB_INFO(sbh);
4977 +
4978 + idx = sb_findcoreidx(sbh, coreid, coreunit);
4979 + if (!GOODIDX(idx))
4980 + return (NULL);
4981 +
4982 + return (sb_setcoreidx(sbh, idx));
4983 +}
4984 +
4985 +/* return chip number */
4986 +uint
4987 +sb_chip(void *sbh)
4988 +{
4989 + sb_info_t *si;
4990 +
4991 + si = SB_INFO(sbh);
4992 + return (si->chip);
4993 +}
4994 +
4995 +/* return chip revision number */
4996 +uint
4997 +sb_chiprev(void *sbh)
4998 +{
4999 + sb_info_t *si;
5000 +
5001 + si = SB_INFO(sbh);
5002 + return (si->chiprev);
5003 +}
5004 +
5005 +/* return chip package option */
5006 +uint
5007 +sb_chippkg(void *sbh)
5008 +{
5009 + sb_info_t *si;
5010 +
5011 + si = SB_INFO(sbh);
5012 + return (si->chippkg);
5013 +}
5014 +
5015 +/* return board vendor id */
5016 +uint
5017 +sb_boardvendor(void *sbh)
5018 +{
5019 + sb_info_t *si;
5020 +
5021 + si = SB_INFO(sbh);
5022 + return (si->boardvendor);
5023 +}
5024 +
5025 +/* return boardtype */
5026 +uint
5027 +sb_boardtype(void *sbh)
5028 +{
5029 + sb_info_t *si;
5030 + char *var;
5031 +
5032 + si = SB_INFO(sbh);
5033 +
5034 + if (si->bus == SB_BUS && si->boardtype == 0xffff) {
5035 + /* boardtype format is a hex string */
5036 + si->boardtype = getintvar(NULL, "boardtype");
5037 +
5038 + /* backward compatibility for older boardtype string format */
5039 + if ((si->boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
5040 + if (!strcmp(var, "bcm94710dev"))
5041 + si->boardtype = BCM94710D_BOARD;
5042 + else if (!strcmp(var, "bcm94710ap"))
5043 + si->boardtype = BCM94710AP_BOARD;
5044 + else if (!strcmp(var, "bcm94310u"))
5045 + si->boardtype = BCM94310U_BOARD;
5046 + else if (!strcmp(var, "bu4711"))
5047 + si->boardtype = BU4711_BOARD;
5048 + else if (!strcmp(var, "bu4710"))
5049 + si->boardtype = BU4710_BOARD;
5050 + else if (!strcmp(var, "bcm94702mn"))
5051 + si->boardtype = BCM94702MN_BOARD;
5052 + else if (!strcmp(var, "bcm94710r1"))
5053 + si->boardtype = BCM94710R1_BOARD;
5054 + else if (!strcmp(var, "bcm94710r4"))
5055 + si->boardtype = BCM94710R4_BOARD;
5056 + else if (!strcmp(var, "bcm94702cpci"))
5057 + si->boardtype = BCM94702CPCI_BOARD;
5058 + else if (!strcmp(var, "bcm95380_rr"))
5059 + si->boardtype = BCM95380RR_BOARD;
5060 + }
5061 + }
5062 +
5063 + return (si->boardtype);
5064 +}
5065 +
5066 +/* return board bus style */
5067 +uint
5068 +sb_boardstyle(void *sbh)
5069 +{
5070 + sb_info_t *si;
5071 + uint16 w;
5072 +
5073 + si = SB_INFO(sbh);
5074 +
5075 + if (si->bus == PCMCIA_BUS)
5076 + return (BOARDSTYLE_PCMCIA);
5077 +
5078 + if (si->bus == SB_BUS)
5079 + return (BOARDSTYLE_SOC);
5080 +
5081 + /* bus is PCI */
5082 +
5083 + if (OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_CIS, sizeof (uint32)) != 0)
5084 + return (BOARDSTYLE_CARDBUS);
5085 +
5086 + if ((srom_read(si->bus, si->curmap, si->osh, (SPROM_SIZE - 1) * 2, 2, &w) == 0) &&
5087 + (w == 0x0313))
5088 + return (BOARDSTYLE_CARDBUS);
5089 +
5090 + return (BOARDSTYLE_PCI);
5091 +}
5092 +
5093 +/* return boolean if sbh device is in pci hostmode or client mode */
5094 +uint
5095 +sb_bus(void *sbh)
5096 +{
5097 + sb_info_t *si;
5098 +
5099 + si = SB_INFO(sbh);
5100 + return (si->bus);
5101 +}
5102 +
5103 +/* return list of found cores */
5104 +uint
5105 +sb_corelist(void *sbh, uint coreid[])
5106 +{
5107 + sb_info_t *si;
5108 +
5109 + si = SB_INFO(sbh);
5110 +
5111 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof (uint)));
5112 + return (si->numcores);
5113 +}
5114 +
5115 +/* return current register mapping */
5116 +void *
5117 +sb_coreregs(void *sbh)
5118 +{
5119 + sb_info_t *si;
5120 +
5121 + si = SB_INFO(sbh);
5122 + ASSERT(GOODREGS(si->curmap));
5123 +
5124 + return (si->curmap);
5125 +}
5126 +
5127 +/* Check if a target abort has happened and clear it */
5128 +bool
5129 +sb_taclear(void *sbh)
5130 +{
5131 + sb_info_t *si;
5132 + bool rc = FALSE;
5133 + sbconfig_t *sb;
5134 +
5135 + si = SB_INFO(sbh);
5136 + sb = REGS2SB(si->curmap);
5137 +
5138 + if (si->bus == PCI_BUS) {
5139 + uint32 stcmd;
5140 +
5141 + stcmd = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_CMD, sizeof(stcmd));
5142 + rc = (stcmd & 0x08000000) != 0;
5143 +
5144 + if (rc) {
5145 + /* Target abort bit is set, clear it */
5146 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_CFG_CMD, sizeof(stcmd), stcmd);
5147 + }
5148 + } else if (si->bus == PCMCIA_BUS) {
5149 + rc = FALSE;
5150 + }
5151 + else if (si->bus == SDIO_BUS) {
5152 + /* due to 4317 A0 HW bug, sdio core wedged on target abort,
5153 + just clear SBSErr bit blindly */
5154 + if (0x0 != R_SBREG(sbh, &sb->sbtmerrlog)) {
5155 + SB_ERROR(("SDIO target abort, clean it"));
5156 + W_SBREG(sbh, &sb->sbtmstatehigh, 0);
5157 + }
5158 + rc = FALSE;
5159 + }
5160 +
5161 + return (rc);
5162 +}
5163 +
5164 +/* do buffered registers update */
5165 +void
5166 +sb_commit(void *sbh)
5167 +{
5168 + sb_info_t *si;
5169 + sbpciregs_t *pciregs;
5170 + uint origidx;
5171 + uint intr_val = 0;
5172 +
5173 + si = SB_INFO(sbh);
5174 +
5175 + origidx = si->curidx;
5176 + ASSERT(GOODIDX(origidx));
5177 +
5178 + INTR_OFF(si, intr_val);
5179 + /* switch over to pci core */
5180 + pciregs = (sbpciregs_t*) sb_setcore(sbh, SB_PCI, 0);
5181 +
5182 + /* do the buffer registers update */
5183 + W_REG(&pciregs->bcastaddr, SB_COMMIT);
5184 + W_REG(&pciregs->bcastdata, 0x0);
5185 +
5186 + /* restore core index */
5187 + sb_setcoreidx(sbh, origidx);
5188 + INTR_RESTORE(si, intr_val);
5189 +}
5190 +
5191 +/* reset and re-enable a core */
5192 +void
5193 +sb_core_reset(void *sbh, uint32 bits)
5194 +{
5195 + sb_info_t *si;
5196 + sbconfig_t *sb;
5197 + volatile uint32 dummy;
5198 +
5199 + si = SB_INFO(sbh);
5200 + ASSERT(GOODREGS(si->curmap));
5201 + sb = REGS2SB(si->curmap);
5202 +
5203 + /*
5204 + * Must do the disable sequence first to work for arbitrary current core state.
5205 + */
5206 + sb_core_disable(sbh, bits);
5207 +
5208 + /*
5209 + * Now do the initialization sequence.
5210 + */
5211 +
5212 + /* set reset while enabling the clock and forcing them on throughout the core */
5213 + W_SBREG(sbh, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits));
5214 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
5215 +
5216 + if (sb_coreid(sbh) == SB_ILINE100) {
5217 + bcm_mdelay(50);
5218 + } else {
5219 + OSL_DELAY(1);
5220 + }
5221 +
5222 + if (R_SBREG(sbh, &sb->sbtmstatehigh) & SBTMH_SERR) {
5223 + W_SBREG(sbh, &sb->sbtmstatehigh, 0);
5224 + }
5225 + if ((dummy = R_SBREG(sbh, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
5226 + AND_SBREG(sbh, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
5227 + }
5228 +
5229 + /* clear reset and allow it to propagate throughout the core */
5230 + W_SBREG(sbh, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
5231 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
5232 + OSL_DELAY(1);
5233 +
5234 + /* leave clock enabled */
5235 + W_SBREG(sbh, &sb->sbtmstatelow, (SBTML_CLK | bits));
5236 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
5237 + OSL_DELAY(1);
5238 +}
5239 +
5240 +void
5241 +sb_core_tofixup(void *sbh)
5242 +{
5243 + sb_info_t *si;
5244 + sbconfig_t *sb;
5245 +
5246 + si = SB_INFO(sbh);
5247 +
5248 + if (si->pcirev >= 5)
5249 + return;
5250 +
5251 + ASSERT(GOODREGS(si->curmap));
5252 + sb = REGS2SB(si->curmap);
5253 +
5254 + if (si->bus == SB_BUS) {
5255 + SET_SBREG(sbh, &sb->sbimconfiglow,
5256 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
5257 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
5258 + } else {
5259 + if (sb_coreid(sbh) == SB_PCI) {
5260 + SET_SBREG(sbh, &sb->sbimconfiglow,
5261 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
5262 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
5263 + } else {
5264 + SET_SBREG(sbh, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
5265 + }
5266 + }
5267 +
5268 + sb_commit(sbh);
5269 +}
5270 +
5271 +void
5272 +sb_core_disable(void *sbh, uint32 bits)
5273 +{
5274 + sb_info_t *si;
5275 + volatile uint32 dummy;
5276 + sbconfig_t *sb;
5277 +
5278 + si = SB_INFO(sbh);
5279 +
5280 + ASSERT(GOODREGS(si->curmap));
5281 + sb = REGS2SB(si->curmap);
5282 +
5283 + /* must return if core is already in reset */
5284 + if (R_SBREG(sbh, &sb->sbtmstatelow) & SBTML_RESET)
5285 + return;
5286 +
5287 + /* put into reset and return if clocks are not enabled */
5288 + if ((R_SBREG(sbh, &sb->sbtmstatelow) & SBTML_CLK) == 0)
5289 + goto disable;
5290 +
5291 + /* set the reject bit */
5292 + W_SBREG(sbh, &sb->sbtmstatelow, (SBTML_CLK | SBTML_REJ));
5293 +
5294 + /* spin until reject is set */
5295 + while ((R_SBREG(sbh, &sb->sbtmstatelow) & SBTML_REJ) == 0)
5296 + OSL_DELAY(1);
5297 +
5298 + /* spin until sbtmstatehigh.busy is clear */
5299 + while (R_SBREG(sbh, &sb->sbtmstatehigh) & SBTMH_BUSY)
5300 + OSL_DELAY(1);
5301 +
5302 + /* set reset and reject while enabling the clocks */
5303 + W_SBREG(sbh, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET));
5304 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
5305 + OSL_DELAY(10);
5306 +
5307 + disable:
5308 + /* leave reset and reject asserted */
5309 + W_SBREG(sbh, &sb->sbtmstatelow, (bits | SBTML_REJ | SBTML_RESET));
5310 + OSL_DELAY(1);
5311 +}
5312 +
5313 +void
5314 +sb_watchdog(void *sbh, uint ticks)
5315 +{
5316 + sb_info_t *si = SB_INFO(sbh);
5317 +
5318 + /* instant NMI */
5319 + switch (si->gpioid) {
5320 + case SB_CC:
5321 + sb_corereg(sbh, si->gpioidx, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
5322 + break;
5323 + case SB_EXTIF:
5324 + sb_corereg(sbh, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
5325 + break;
5326 + }
5327 +}
5328 +
5329 +/* initialize the pcmcia core */
5330 +void
5331 +sb_pcmcia_init(void *sbh)
5332 +{
5333 + sb_info_t *si;
5334 + uint8 cor;
5335 +
5336 + si = SB_INFO(sbh);
5337 +
5338 + /* enable d11 mac interrupts */
5339 + if (si->chip == BCM4301_DEVICE_ID) {
5340 + /* Have to use FCR2 in 4301 */
5341 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
5342 + cor |= COR_IRQEN | COR_FUNEN;
5343 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
5344 + } else {
5345 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
5346 + cor |= COR_IRQEN | COR_FUNEN;
5347 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
5348 + }
5349 +
5350 +}
5351 +
5352 +
5353 +/*
5354 + * Configure the pci core for pci client (NIC) action
5355 + * and get appropriate dma offset value.
5356 + * coremask is the bitvec of cores by index to be enabled.
5357 + */
5358 +void
5359 +sb_pci_setup(void *sbh, uint32 *dmaoffset, uint coremask)
5360 +{
5361 + sb_info_t *si;
5362 + sbconfig_t *sb;
5363 + sbpciregs_t *pciregs;
5364 + uint32 sbflag;
5365 + uint32 w;
5366 + uint idx;
5367 +
5368 + si = SB_INFO(sbh);
5369 +
5370 + if (dmaoffset)
5371 + *dmaoffset = 0;
5372 +
5373 + /* if not pci bus, we're done */
5374 + if (si->bus != PCI_BUS)
5375 + return;
5376 +
5377 + ASSERT(si->pciidx);
5378 +
5379 + /* get current core index */
5380 + idx = si->curidx;
5381 +
5382 + /* we interrupt on this backplane flag number */
5383 + ASSERT(GOODREGS(si->curmap));
5384 + sb = REGS2SB(si->curmap);
5385 + sbflag = R_SBREG(sbh, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
5386 +
5387 + /* switch over to pci core */
5388 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->pciidx);
5389 + sb = REGS2SB(pciregs);
5390 +
5391 + /*
5392 + * Enable sb->pci interrupts. Assume
5393 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
5394 + */
5395 + if (si->pcirev < 6) {
5396 + /* set sbintvec bit for our flag number */
5397 + OR_SBREG(sbh, &sb->sbintvec, (1 << sbflag));
5398 + } else {
5399 + /* pci config write to set this core bit in PCIIntMask */
5400 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
5401 + w |= (coremask << PCI_SBIM_SHIFT);
5402 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
5403 + }
5404 +
5405 + /* enable prefetch and bursts for sonics-to-pci translation 2 */
5406 + OR_REG(&pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
5407 +
5408 + if (si->pcirev < 5) {
5409 + SET_SBREG(sbh, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
5410 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
5411 + sb_commit(sbh);
5412 + }
5413 +
5414 + /* switch back to previous core */
5415 + sb_setcoreidx(sbh, idx);
5416 +
5417 + /* use large sb pci dma window */
5418 + if (dmaoffset)
5419 + *dmaoffset = SB_PCI_DMA;
5420 +}
5421 +
5422 +uint32
5423 +sb_base(uint32 admatch)
5424 +{
5425 + uint32 base;
5426 + uint type;
5427 +
5428 + type = admatch & SBAM_TYPE_MASK;
5429 + ASSERT(type < 3);
5430 +
5431 + base = 0;
5432 +
5433 + if (type == 0) {
5434 + base = admatch & SBAM_BASE0_MASK;
5435 + } else if (type == 1) {
5436 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
5437 + base = admatch & SBAM_BASE1_MASK;
5438 + } else if (type == 2) {
5439 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
5440 + base = admatch & SBAM_BASE2_MASK;
5441 + }
5442 +
5443 + return (base);
5444 +}
5445 +
5446 +uint32
5447 +sb_size(uint32 admatch)
5448 +{
5449 + uint32 size;
5450 + uint type;
5451 +
5452 + type = admatch & SBAM_TYPE_MASK;
5453 + ASSERT(type < 3);
5454 +
5455 + size = 0;
5456 +
5457 + if (type == 0) {
5458 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
5459 + } else if (type == 1) {
5460 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
5461 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
5462 + } else if (type == 2) {
5463 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
5464 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
5465 + }
5466 +
5467 + return (size);
5468 +}
5469 +
5470 +/* return the core-type instantiation # of the current core */
5471 +uint
5472 +sb_coreunit(void *sbh)
5473 +{
5474 + sb_info_t *si;
5475 + uint idx;
5476 + uint coreid;
5477 + uint coreunit;
5478 + uint i;
5479 +
5480 + si = SB_INFO(sbh);
5481 + coreunit = 0;
5482 +
5483 + idx = si->curidx;
5484 +
5485 + ASSERT(GOODREGS(si->curmap));
5486 + coreid = sb_coreid(sbh);
5487 +
5488 + /* count the cores of our type */
5489 + for (i = 0; i < idx; i++)
5490 + if (si->coreid[i] == coreid)
5491 + coreunit++;
5492 +
5493 + return (coreunit);
5494 +}
5495 +
5496 +static INLINE uint32
5497 +factor6(uint32 x)
5498 +{
5499 + switch (x) {
5500 + case CC_F6_2: return 2;
5501 + case CC_F6_3: return 3;
5502 + case CC_F6_4: return 4;
5503 + case CC_F6_5: return 5;
5504 + case CC_F6_6: return 6;
5505 + case CC_F6_7: return 7;
5506 + default: return 0;
5507 + }
5508 +}
5509 +
5510 +/* calculate the speed the SB would run at given a set of clockcontrol values */
5511 +uint32
5512 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
5513 +{
5514 + uint32 n1, n2, clock, m1, m2, m3, mc;
5515 +
5516 + n1 = n & CN_N1_MASK;
5517 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
5518 +
5519 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE4)) {
5520 + n1 = factor6(n1);
5521 + n2 += CC_F5_BIAS;
5522 + } else if (pll_type == PLL_TYPE2) {
5523 + n1 += CC_T2_BIAS;
5524 + n2 += CC_T2_BIAS;
5525 + ASSERT((n1 >= 2) && (n1 <= 7));
5526 + ASSERT((n2 >= 5) && (n2 <= 23));
5527 + } else if (pll_type == PLL_TYPE3) {
5528 + return (100000000);
5529 + } else
5530 + ASSERT((pll_type >= PLL_TYPE1) && (pll_type <= PLL_TYPE4));
5531 +
5532 + clock = CC_CLOCK_BASE * n1 * n2;
5533 +
5534 + if (clock == 0)
5535 + return 0;
5536 +
5537 + m1 = m & CC_M1_MASK;
5538 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
5539 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
5540 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
5541 +
5542 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE4)) {
5543 + m1 = factor6(m1);
5544 + if (pll_type == PLL_TYPE1)
5545 + m2 += CC_F5_BIAS;
5546 + else
5547 + m2 = factor6(m2);
5548 + m3 = factor6(m3);
5549 +
5550 + switch (mc) {
5551 + case CC_MC_BYPASS: return (clock);
5552 + case CC_MC_M1: return (clock / m1);
5553 + case CC_MC_M1M2: return (clock / (m1 * m2));
5554 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
5555 + case CC_MC_M1M3: return (clock / (m1 * m3));
5556 + default: return (0);
5557 + }
5558 + } else {
5559 + ASSERT(pll_type == PLL_TYPE2);
5560 +
5561 + m1 += CC_T2_BIAS;
5562 + m2 += CC_T2M2_BIAS;
5563 + m3 += CC_T2_BIAS;
5564 + ASSERT((m1 >= 2) && (m1 <= 7));
5565 + ASSERT((m2 >= 3) && (m2 <= 10));
5566 + ASSERT((m3 >= 2) && (m3 <= 7));
5567 +
5568 + if ((mc & CC_T2MC_M1BYP) == 0)
5569 + clock /= m1;
5570 + if ((mc & CC_T2MC_M2BYP) == 0)
5571 + clock /= m2;
5572 + if ((mc & CC_T2MC_M3BYP) == 0)
5573 + clock /= m3;
5574 +
5575 + return(clock);
5576 + }
5577 +}
5578 +
5579 +/* returns the current speed the SB is running at */
5580 +uint32
5581 +sb_clock(void *sbh)
5582 +{
5583 + sb_info_t *si;
5584 + extifregs_t *eir;
5585 + chipcregs_t *cc;
5586 + uint32 n, m;
5587 + uint idx;
5588 + uint32 pll_type, rate;
5589 + uint intr_val = 0;
5590 +
5591 + si = SB_INFO(sbh);
5592 + idx = si->curidx;
5593 + pll_type = PLL_TYPE1;
5594 +
5595 + INTR_OFF(si, intr_val);
5596 +
5597 + /* switch to extif or chipc core */
5598 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
5599 + n = R_REG(&eir->clockcontrol_n);
5600 + m = R_REG(&eir->clockcontrol_sb);
5601 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
5602 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
5603 + n = R_REG(&cc->clockcontrol_n);
5604 + m = R_REG(&cc->clockcontrol_sb);
5605 + } else {
5606 + INTR_RESTORE(si, intr_val);
5607 + return 0;
5608 + }
5609 +
5610 + /* calculate rate */
5611 + rate = sb_clock_rate(pll_type, n, m);
5612 +
5613 + /* switch back to previous core */
5614 + sb_setcoreidx(sbh, idx);
5615 +
5616 + INTR_RESTORE(si, intr_val);
5617 +
5618 + return rate;
5619 +}
5620 +
5621 +/* change logical "focus" to the gpio core for optimized access */
5622 +void*
5623 +sb_gpiosetcore(void *sbh)
5624 +{
5625 + sb_info_t *si;
5626 +
5627 + si = SB_INFO(sbh);
5628 +
5629 + return (sb_setcoreidx(sbh, si->gpioidx));
5630 +}
5631 +
5632 +/* mask&set gpiocontrol bits */
5633 +uint32
5634 +sb_gpiocontrol(void *sbh, uint32 mask, uint32 val)
5635 +{
5636 + sb_info_t *si;
5637 + uint regoff;
5638 +
5639 + si = SB_INFO(sbh);
5640 + regoff = 0;
5641 +
5642 + switch (si->gpioid) {
5643 + case SB_CC:
5644 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
5645 + break;
5646 +
5647 + case SB_PCI:
5648 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
5649 + break;
5650 +
5651 + case SB_EXTIF:
5652 + return (0);
5653 + }
5654 +
5655 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
5656 +}
5657 +
5658 +/* mask&set gpio output enable bits */
5659 +uint32
5660 +sb_gpioouten(void *sbh, uint32 mask, uint32 val)
5661 +{
5662 + sb_info_t *si;
5663 + uint regoff;
5664 +
5665 + si = SB_INFO(sbh);
5666 + regoff = 0;
5667 +
5668 + switch (si->gpioid) {
5669 + case SB_CC:
5670 + regoff = OFFSETOF(chipcregs_t, gpioouten);
5671 + break;
5672 +
5673 + case SB_PCI:
5674 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
5675 + break;
5676 +
5677 + case SB_EXTIF:
5678 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
5679 + break;
5680 + }
5681 +
5682 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
5683 +}
5684 +
5685 +/* mask&set gpio output bits */
5686 +uint32
5687 +sb_gpioout(void *sbh, uint32 mask, uint32 val)
5688 +{
5689 + sb_info_t *si;
5690 + uint regoff;
5691 +
5692 + si = SB_INFO(sbh);
5693 + regoff = 0;
5694 +
5695 + switch (si->gpioid) {
5696 + case SB_CC:
5697 + regoff = OFFSETOF(chipcregs_t, gpioout);
5698 + break;
5699 +
5700 + case SB_PCI:
5701 + regoff = OFFSETOF(sbpciregs_t, gpioout);
5702 + break;
5703 +
5704 + case SB_EXTIF:
5705 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
5706 + break;
5707 + }
5708 +
5709 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
5710 +}
5711 +
5712 +/* return the current gpioin register value */
5713 +uint32
5714 +sb_gpioin(void *sbh)
5715 +{
5716 + sb_info_t *si;
5717 + uint regoff;
5718 +
5719 + si = SB_INFO(sbh);
5720 + regoff = 0;
5721 +
5722 + switch (si->gpioid) {
5723 + case SB_CC:
5724 + regoff = OFFSETOF(chipcregs_t, gpioin);
5725 + break;
5726 +
5727 + case SB_PCI:
5728 + regoff = OFFSETOF(sbpciregs_t, gpioin);
5729 + break;
5730 +
5731 + case SB_EXTIF:
5732 + regoff = OFFSETOF(extifregs_t, gpioin);
5733 + break;
5734 + }
5735 +
5736 + return (sb_corereg(sbh, si->gpioidx, regoff, 0, 0));
5737 +}
5738 +
5739 +/* mask&set gpio interrupt polarity bits */
5740 +uint32
5741 +sb_gpiointpolarity(void *sbh, uint32 mask, uint32 val)
5742 +{
5743 + sb_info_t *si;
5744 + uint regoff;
5745 +
5746 + si = SB_INFO(sbh);
5747 + regoff = 0;
5748 +
5749 + switch (si->gpioid) {
5750 + case SB_CC:
5751 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
5752 + break;
5753 +
5754 + case SB_PCI:
5755 + /* pci gpio implementation does not support interrupt polarity */
5756 + ASSERT(0);
5757 + break;
5758 +
5759 + case SB_EXTIF:
5760 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
5761 + break;
5762 + }
5763 +
5764 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
5765 +}
5766 +
5767 +/* mask&set gpio interrupt mask bits */
5768 +uint32
5769 +sb_gpiointmask(void *sbh, uint32 mask, uint32 val)
5770 +{
5771 + sb_info_t *si;
5772 + uint regoff;
5773 +
5774 + si = SB_INFO(sbh);
5775 + regoff = 0;
5776 +
5777 + switch (si->gpioid) {
5778 + case SB_CC:
5779 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
5780 + break;
5781 +
5782 + case SB_PCI:
5783 + /* pci gpio implementation does not support interrupt mask */
5784 + ASSERT(0);
5785 + break;
5786 +
5787 + case SB_EXTIF:
5788 + regoff = OFFSETOF(extifregs_t, gpiointmask);
5789 + break;
5790 + }
5791 +
5792 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
5793 +}
5794 +
5795 +
5796 +/*
5797 + * Return the slowclock min or max frequency.
5798 + * Three sources of SLOW CLOCK:
5799 + * 1. On Chip LPO - 32khz or 160khz
5800 + * 2. On Chip Xtal OSC - 20mhz/4*(divider+1)
5801 + * 3. External PCI clock - 66mhz/4*(divider+1)
5802 + */
5803 +static uint
5804 +slowfreq(void *sbh, bool max)
5805 +{
5806 + sb_info_t *si;
5807 + chipcregs_t *cc;
5808 + uint32 v;
5809 + uint div;
5810 +
5811 + si = SB_INFO(sbh);
5812 +
5813 + ASSERT(sb_coreid(sbh) == SB_CC);
5814 +
5815 + cc = (chipcregs_t*) sb_setcoreidx(sbh, si->curidx);
5816 +
5817 + /* shouldn't be here unless we've established the chip has dynamic power control */
5818 + ASSERT(R_REG(&cc->capabilities) & CAP_PWR_CTL);
5819 +
5820 + if (si->ccrev < 6) {
5821 + v = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
5822 +
5823 + if (v & PCI_CFG_GPIO_SCS)
5824 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
5825 + else
5826 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
5827 + } else {
5828 + v = R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK;
5829 + div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHF) + 1);
5830 + if (v == SCC_SS_LPO)
5831 + return (max? LPOMAXFREQ : LPOMINFREQ);
5832 + else if (v == SCC_SS_XTAL)
5833 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
5834 + else if (v == SCC_SS_PCI)
5835 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
5836 + else
5837 + ASSERT(0);
5838 + }
5839 + return (0);
5840 +}
5841 +
5842 +/* initialize power control delay registers */
5843 +void
5844 +sb_pwrctl_init(void *sbh)
5845 +{
5846 + sb_info_t *si;
5847 + uint origidx;
5848 + chipcregs_t *cc;
5849 + uint slowmaxfreq;
5850 + uint pll_on_delay, fref_sel_delay;
5851 +
5852 + si = SB_INFO(sbh);
5853 +
5854 + if (si->bus == SB_BUS)
5855 + return;
5856 +
5857 + origidx = si->curidx;
5858 +
5859 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
5860 + return;
5861 +
5862 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5863 + goto done;
5864 +
5865 + slowmaxfreq = slowfreq(sbh, TRUE);
5866 + pll_on_delay = ((slowmaxfreq * PLL_DELAY) + 999999) / 1000000;
5867 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
5868 +
5869 + W_REG(&cc->pll_on_delay, pll_on_delay);
5870 + W_REG(&cc->fref_sel_delay, fref_sel_delay);
5871 +
5872 + /* 4317pc does not work with SlowClock less than 5Mhz */
5873 + if (si->bus == PCMCIA_BUS)
5874 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, (0 << SCC_CD_SHF));
5875 +
5876 +done:
5877 + sb_setcoreidx(sbh, origidx);
5878 +}
5879 +
5880 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
5881 +uint16
5882 +sb_pwrctl_fast_pwrup_delay(void *sbh)
5883 +{
5884 + sb_info_t *si;
5885 + uint origidx;
5886 + chipcregs_t *cc;
5887 + uint slowminfreq;
5888 + uint16 fpdelay;
5889 + uint intr_val = 0;
5890 +
5891 + si = SB_INFO(sbh);
5892 + fpdelay = 0;
5893 + origidx = si->curidx;
5894 +
5895 + if (si->bus == SB_BUS)
5896 + goto done;
5897 +
5898 + INTR_OFF(si, intr_val);
5899 +
5900 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
5901 + goto done;
5902 +
5903 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5904 + goto done;
5905 +
5906 + slowminfreq = slowfreq(sbh, FALSE);
5907 + fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + (slowminfreq - 1)) / slowminfreq;
5908 +
5909 +done:
5910 + sb_setcoreidx(sbh, origidx);
5911 + INTR_RESTORE(si, intr_val);
5912 + return (fpdelay);
5913 +}
5914 +
5915 +/* turn primary xtal and/or pll off/on */
5916 +int
5917 +sb_pwrctl_xtal(void *sbh, uint what, bool on)
5918 +{
5919 + sb_info_t *si;
5920 + uint32 in, out, outen;
5921 +
5922 + si = SB_INFO(sbh);
5923 +
5924 +
5925 + if (si->bus == PCMCIA_BUS) {
5926 + return (0);
5927 + }
5928 +
5929 + if (si->bus != PCI_BUS)
5930 + return (-1);
5931 +
5932 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof (uint32));
5933 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
5934 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32));
5935 +
5936 + /*
5937 + * We can't actually read the state of the PLLPD so we infer it
5938 + * by the value of XTAL_PU which *is* readable via gpioin.
5939 + */
5940 + if (on && (in & PCI_CFG_GPIO_XTAL))
5941 + return (0);
5942 +
5943 + if (what & XTAL)
5944 + outen |= PCI_CFG_GPIO_XTAL;
5945 + if (what & PLL)
5946 + outen |= PCI_CFG_GPIO_PLL;
5947 +
5948 + if (on) {
5949 + /* turn primary xtal on */
5950 + if (what & XTAL) {
5951 + out |= PCI_CFG_GPIO_XTAL;
5952 + if (what & PLL)
5953 + out |= PCI_CFG_GPIO_PLL;
5954 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5955 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
5956 + OSL_DELAY(200);
5957 + }
5958 +
5959 + /* turn pll on */
5960 + if (what & PLL) {
5961 + out &= ~PCI_CFG_GPIO_PLL;
5962 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5963 + OSL_DELAY(2000);
5964 + }
5965 + } else {
5966 + if (what & XTAL)
5967 + out &= ~PCI_CFG_GPIO_XTAL;
5968 + if (what & PLL)
5969 + out |= PCI_CFG_GPIO_PLL;
5970 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5971 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
5972 + }
5973 +
5974 + return (0);
5975 +}
5976 +
5977 +/* set dynamic power control mode (forceslow, forcefast, dynamic) */
5978 +/* returns true if ignore pll off is set and false if it is not */
5979 +bool
5980 +sb_pwrctl_clk(void *sbh, uint mode)
5981 +{
5982 + sb_info_t *si;
5983 + uint origidx;
5984 + chipcregs_t *cc;
5985 + uint32 scc;
5986 + bool forcefastclk=FALSE;
5987 + uint intr_val = 0;
5988 +
5989 + si = SB_INFO(sbh);
5990 +
5991 + /* chipcommon cores prior to rev6 don't support slowclkcontrol */
5992 + if (si->ccrev < 6)
5993 + return (FALSE);
5994 +
5995 + INTR_OFF(si, intr_val);
5996 +
5997 + origidx = si->curidx;
5998 +
5999 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
6000 + ASSERT(cc != NULL);
6001 +
6002 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
6003 + goto done;
6004 +
6005 + switch (mode) {
6006 + case CLK_FAST: /* force fast (pll) clock */
6007 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
6008 + sb_pwrctl_xtal(sbh, XTAL, ON);
6009 +
6010 + SET_REG(&cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
6011 + break;
6012 +
6013 + case CLK_SLOW: /* force slow clock */
6014 + if ((si->bus == SDIO_BUS) || (si->bus == PCMCIA_BUS))
6015 + return (-1);
6016 +
6017 + if (si->ccrev >= 6)
6018 + OR_REG(&cc->slow_clk_ctl, SCC_FS);
6019 + break;
6020 +
6021 + case CLK_DYNAMIC: /* enable dynamic power control */
6022 + scc = R_REG(&cc->slow_clk_ctl);
6023 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
6024 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
6025 + scc |= SCC_XC;
6026 + W_REG(&cc->slow_clk_ctl, scc);
6027 +
6028 + /* for dynamic control, we have to release our xtal_pu "force on" */
6029 + if (scc & SCC_XC)
6030 + sb_pwrctl_xtal(sbh, XTAL, OFF);
6031 + break;
6032 + }
6033 +
6034 + /* Is the h/w forcing the use of the fast clk */
6035 + forcefastclk = (bool)((R_REG(&cc->slow_clk_ctl) & SCC_IP) == SCC_IP);
6036 +
6037 +done:
6038 + sb_setcoreidx(sbh, origidx);
6039 + INTR_RESTORE(si, intr_val);
6040 + return (forcefastclk);
6041 +}
6042 +
6043 +/* register driver interrupt disabling and restoring callback functions */
6044 +void
6045 +sb_register_intr_callback(void *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intr_arg)
6046 +{
6047 + sb_info_t *si;
6048 +
6049 + si = SB_INFO(sbh);
6050 + si->intr_arg = intr_arg;
6051 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
6052 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
6053 + /* save current core id. when this function called, the current core
6054 + * must be the core which provides driver functions(il, et, wl, etc.)
6055 + */
6056 + si->dev_coreid = si->coreid[si->curidx];
6057 +}
6058 +
6059 +
6060 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/bcm4710.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcm4710.h
6061 --- linux-2.6.12.5/arch/mips/bcm947xx/include/bcm4710.h 1970-01-01 01:00:00.000000000 +0100
6062 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcm4710.h 2005-08-28 11:12:20.430859152 +0200
6063 @@ -0,0 +1,90 @@
6064 +/*
6065 + * BCM4710 address space map and definitions
6066 + * Think twice before adding to this file, this is not the kitchen sink
6067 + * These definitions are not guaranteed for all 47xx chips, only the 4710
6068 + *
6069 + * Copyright 2001-2003, Broadcom Corporation
6070 + * All Rights Reserved.
6071 + *
6072 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6073 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6074 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6075 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6076 + * $Id$
6077 + */
6078 +
6079 +#ifndef _bcm4710_h_
6080 +#define _bcm4710_h_
6081 +
6082 +/* Address map */
6083 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
6084 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
6085 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
6086 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
6087 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
6088 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
6089 +
6090 +/* Core register space */
6091 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
6092 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
6093 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
6094 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
6095 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
6096 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
6097 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
6098 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
6099 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
6100 +
6101 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
6102 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
6103 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
6104 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
6105 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
6106 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
6107 +
6108 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
6109 +
6110 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
6111 +
6112 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
6113 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
6114 +
6115 +#define SBFLAG_PCI 0
6116 +#define SBFLAG_ENET0 1
6117 +#define SBFLAG_ILINE20 2
6118 +#define SBFLAG_CODEC 3
6119 +#define SBFLAG_USB 4
6120 +#define SBFLAG_EXTIF 5
6121 +#define SBFLAG_ENET1 6
6122 +
6123 +#ifdef CONFIG_HWSIM
6124 +#define BCM4710_TRACE(trval) do { *((int *)0xa0000f18) = (trval); } while (0)
6125 +#else
6126 +#define BCM4710_TRACE(trval)
6127 +#endif
6128 +
6129 +
6130 +/* BCM94702 CPCI -ExtIF used for LocalBus devs */
6131 +
6132 +#define BCM94702_CPCI_RESET_ADDR BCM4710_EXTIF
6133 +#define BCM94702_CPCI_BOARDID_ADDR (BCM4710_EXTIF | 0x4000)
6134 +#define BCM94702_CPCI_DOC_ADDR (BCM4710_EXTIF | 0x6000)
6135 +#define BCM94702_DOC_ADDR BCM94702_CPCI_DOC_ADDR
6136 +#define BCM94702_CPCI_LED_ADDR (BCM4710_EXTIF | 0xc000)
6137 +#define BCM94702_CPCI_NVRAM_ADDR (BCM4710_EXTIF | 0xe000)
6138 +#define BCM94702_CPCI_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
6139 +#define BCM94702_CPCI_TOD_REG_BASE (BCM94702_CPCI_NVRAM_ADDR | 0x1ff0)
6140 +
6141 +#define LED_REG(x) \
6142 + (*(volatile unsigned char *) (KSEG1ADDR(BCM94702_CPCI_LED_ADDR) + (x)))
6143 +
6144 +/*
6145 + * Reset function implemented in PLD. Read or write should trigger hard reset
6146 + */
6147 +#define SYS_HARD_RESET() \
6148 + { for (;;) \
6149 + *( (volatile unsigned char *)\
6150 + KSEG1ADDR(BCM94702_CPCI_RESET_ADDR) ) = 0x80; \
6151 + }
6152 +
6153 +#endif /* _bcm4710_h_ */
6154 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/bcmdevs.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmdevs.h
6155 --- linux-2.6.12.5/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
6156 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmdevs.h 2005-08-28 11:12:20.431859000 +0200
6157 @@ -0,0 +1,238 @@
6158 +/*
6159 + * Broadcom device-specific manifest constants.
6160 + *
6161 + * $Id$
6162 + * Copyright 2001-2003, Broadcom Corporation
6163 + * All Rights Reserved.
6164 + *
6165 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6166 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6167 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6168 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6169 + */
6170 +
6171 +#ifndef _BCMDEVS_H
6172 +#define _BCMDEVS_H
6173 +
6174 +
6175 +/* Known PCI vendor Id's */
6176 +#define VENDOR_EPIGRAM 0xfeda
6177 +#define VENDOR_BROADCOM 0x14e4
6178 +#define VENDOR_3COM 0x10b7
6179 +#define VENDOR_NETGEAR 0x1385
6180 +#define VENDOR_DIAMOND 0x1092
6181 +#define VENDOR_DELL 0x1028
6182 +#define VENDOR_HP 0x0e11
6183 +#define VENDOR_APPLE 0x106b
6184 +
6185 +/* PCI Device Id's */
6186 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
6187 +#define BCM4211_DEVICE_ID 0x4211
6188 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
6189 +#define BCM4231_DEVICE_ID 0x4231
6190 +
6191 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
6192 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
6193 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
6194 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
6195 +
6196 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
6197 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
6198 +
6199 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
6200 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
6201 +
6202 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
6203 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
6204 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
6205 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
6206 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
6207 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
6208 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
6209 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
6210 +
6211 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
6212 +
6213 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
6214 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
6215 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
6216 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
6217 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
6218 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
6219 +
6220 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
6221 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
6222 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
6223 +
6224 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
6225 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
6226 +
6227 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
6228 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
6229 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
6230 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
6231 +
6232 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
6233 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
6234 +#define BCM4306_D11G_ID2 0x4325
6235 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
6236 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
6237 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
6238 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
6239 +
6240 +#define BCM4309_PKG_ID 1 /* 4309 package id */
6241 +
6242 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
6243 +#define BCM4303_PKG_ID 2 /* 4303 package id */
6244 +
6245 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
6246 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
6247 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
6248 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
6249 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
6250 +
6251 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
6252 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
6253 +
6254 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
6255 +
6256 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
6257 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
6258 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
6259 +
6260 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
6261 +
6262 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
6263 +
6264 +
6265 +/* PCMCIA vendor Id's */
6266 +
6267 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
6268 +
6269 +/* SDIO vendor Id's */
6270 +#define VENDOR_BROADCOM_SDIO 0x00BF
6271 +
6272 +
6273 +/* boardflags */
6274 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
6275 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
6276 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
6277 +#define BFL_ENETSPI 0x0010 /* This board has ephy roboswitch spi */
6278 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
6279 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
6280 +#define BFL_ENETVLAN 0x0100 /* This board can do vlan */
6281 +
6282 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
6283 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
6284 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
6285 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
6286 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
6287 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
6288 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
6289 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
6290 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
6291 +
6292 +/* Bus types */
6293 +#define SB_BUS 0 /* Silicon Backplane */
6294 +#define PCI_BUS 1 /* PCI target */
6295 +#define PCMCIA_BUS 2 /* PCMCIA target */
6296 +#define SDIO_BUS 3 /* SDIO target */
6297 +
6298 +/* Reference Board Types */
6299 +
6300 +#define BU4710_BOARD 0x0400
6301 +#define VSIM4710_BOARD 0x0401
6302 +#define QT4710_BOARD 0x0402
6303 +
6304 +#define BU4610_BOARD 0x0403
6305 +#define VSIM4610_BOARD 0x0404
6306 +
6307 +#define BU4307_BOARD 0x0405
6308 +#define BCM94301CB_BOARD 0x0406
6309 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
6310 +#define BCM94301MP_BOARD 0x0407
6311 +#define BCM94307MP_BOARD 0x0408
6312 +#define BCMAP4307_BOARD 0x0409
6313 +
6314 +#define BU4309_BOARD 0x040a
6315 +#define BCM94309CB_BOARD 0x040b
6316 +#define BCM94309MP_BOARD 0x040c
6317 +#define BCM4309AP_BOARD 0x040d
6318 +
6319 +#define BCM94302MP_BOARD 0x040e
6320 +
6321 +#define VSIM4310_BOARD 0x040f
6322 +#define BU4711_BOARD 0x0410
6323 +#define BCM94310U_BOARD 0x0411
6324 +#define BCM94310AP_BOARD 0x0412
6325 +#define BCM94310MP_BOARD 0x0414
6326 +
6327 +#define BU4306_BOARD 0x0416
6328 +#define BCM94306CB_BOARD 0x0417
6329 +#define BCM94306MP_BOARD 0x0418
6330 +
6331 +#define BCM94710D_BOARD 0x041a
6332 +#define BCM94710R1_BOARD 0x041b
6333 +#define BCM94710R4_BOARD 0x041c
6334 +#define BCM94710AP_BOARD 0x041d
6335 +
6336 +
6337 +#define BU2050_BOARD 0x041f
6338 +
6339 +
6340 +#define BCM94309G_BOARD 0x0421
6341 +
6342 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
6343 +
6344 +#define BU4704_BOARD 0x0423
6345 +#define BU4702_BOARD 0x0424
6346 +
6347 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
6348 +
6349 +#define BU4317_BOARD 0x0426
6350 +
6351 +
6352 +#define BCM94702MN_BOARD 0x0428
6353 +
6354 +/* BCM4702 1U CompactPCI Board */
6355 +#define BCM94702CPCI_BOARD 0x0429
6356 +
6357 +/* BCM4702 with BCM95380 VLAN Router */
6358 +#define BCM95380RR_BOARD 0x042a
6359 +
6360 +/* cb4306 with SiGe PA */
6361 +#define BCM94306CBSG_BOARD 0x042b
6362 +
6363 +/* mp4301 with 2050 radio */
6364 +#define BCM94301MPL_BOARD 0x042c
6365 +
6366 +/* cb4306 with SiGe PA */
6367 +#define PCSG94306_BOARD 0x042d
6368 +
6369 +/* bu4704 with sdram */
6370 +#define BU4704SD_BOARD 0x042e
6371 +
6372 +/* Dual 11a/11g Router */
6373 +#define BCM94704AGR_BOARD 0x042f
6374 +
6375 +/* 11a-only minipci */
6376 +#define BCM94308MP_BOARD 0x0430
6377 +
6378 +
6379 +
6380 +/* BCM94317 boards */
6381 +#define BCM94317CB_BOARD 0x0440
6382 +#define BCM94317MP_BOARD 0x0441
6383 +#define BCM94317PCMCIA_BOARD 0x0442
6384 +#define BCM94317SDIO_BOARD 0x0443
6385 +
6386 +#define BU4712_BOARD 0x0444
6387 +
6388 +/* BCM4712 boards */
6389 +#define BCM94712AGR_BOARD 0x0445
6390 +#define BCM94712AP_BOARD 0x0446
6391 +
6392 +/* BCM4702 boards */
6393 +#define CT4702AP_BOARD 0x0447
6394 +
6395 +#endif /* _BCMDEVS_H */
6396 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/bcmendian.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmendian.h
6397 --- linux-2.6.12.5/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
6398 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmendian.h 2005-08-28 11:12:20.431859000 +0200
6399 @@ -0,0 +1,125 @@
6400 +/*******************************************************************************
6401 + * $Id$
6402 + * Copyright 2001-2003, Broadcom Corporation
6403 + * All Rights Reserved.
6404 + *
6405 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6406 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6407 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6408 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6409 + * local version of endian.h - byte order defines
6410 + ******************************************************************************/
6411 +
6412 +#ifndef _BCMENDIAN_H_
6413 +#define _BCMENDIAN_H_
6414 +
6415 +#include <typedefs.h>
6416 +
6417 +/* Byte swap a 16 bit value */
6418 +#define BCMSWAP16(val) \
6419 + ((uint16)( \
6420 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
6421 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
6422 +
6423 +/* Byte swap a 32 bit value */
6424 +#define BCMSWAP32(val) \
6425 + ((uint32)( \
6426 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
6427 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
6428 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
6429 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
6430 +
6431 +static INLINE uint16
6432 +bcmswap16(uint16 val)
6433 +{
6434 + return BCMSWAP16(val);
6435 +}
6436 +
6437 +static INLINE uint32
6438 +bcmswap32(uint32 val)
6439 +{
6440 + return BCMSWAP32(val);
6441 +}
6442 +
6443 +/* buf - start of buffer of shorts to swap */
6444 +/* len - byte length of buffer */
6445 +static INLINE void
6446 +bcmswap16_buf(uint16 *buf, uint len)
6447 +{
6448 + len = len/2;
6449 +
6450 + while(len--){
6451 + *buf = bcmswap16(*buf);
6452 + buf++;
6453 + }
6454 +}
6455 +
6456 +#ifndef hton16
6457 +#ifndef IL_BIGENDIAN
6458 +#define HTON16(i) BCMSWAP16(i)
6459 +#define hton16(i) bcmswap16(i)
6460 +#define hton32(i) bcmswap32(i)
6461 +#define ntoh16(i) bcmswap16(i)
6462 +#define ntoh32(i) bcmswap32(i)
6463 +#define ltoh16(i) (i)
6464 +#define ltoh32(i) (i)
6465 +#define htol16(i) (i)
6466 +#define htol32(i) (i)
6467 +#else
6468 +#define HTON16(i) (i)
6469 +#define hton16(i) (i)
6470 +#define hton32(i) (i)
6471 +#define ntoh16(i) (i)
6472 +#define ntoh32(i) (i)
6473 +#define ltoh16(i) bcmswap16(i)
6474 +#define ltoh32(i) bcmswap32(i)
6475 +#define htol16(i) bcmswap16(i)
6476 +#define htol32(i) bcmswap32(i)
6477 +#endif
6478 +#endif
6479 +
6480 +#ifndef IL_BIGENDIAN
6481 +#define ltoh16_buf(buf, i)
6482 +#define htol16_buf(buf, i)
6483 +#else
6484 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
6485 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
6486 +#endif
6487 +
6488 +/*
6489 +* load 16-bit value from unaligned little endian byte array.
6490 +*/
6491 +static INLINE uint16
6492 +ltoh16_ua(uint8 *bytes)
6493 +{
6494 + return (bytes[1]<<8)+bytes[0];
6495 +}
6496 +
6497 +/*
6498 +* load 32-bit value from unaligned little endian byte array.
6499 +*/
6500 +static INLINE uint32
6501 +ltoh32_ua(uint8 *bytes)
6502 +{
6503 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
6504 +}
6505 +
6506 +/*
6507 +* load 16-bit value from unaligned big(network) endian byte array.
6508 +*/
6509 +static INLINE uint16
6510 +ntoh16_ua(uint8 *bytes)
6511 +{
6512 + return (bytes[0]<<8)+bytes[1];
6513 +}
6514 +
6515 +/*
6516 +* load 32-bit value from unaligned big(network) endian byte array.
6517 +*/
6518 +static INLINE uint32
6519 +ntoh32_ua(uint8 *bytes)
6520 +{
6521 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
6522 +}
6523 +
6524 +#endif /* _BCMENDIAN_H_ */
6525 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/bcmenet47xx.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmenet47xx.h
6526 --- linux-2.6.12.5/arch/mips/bcm947xx/include/bcmenet47xx.h 1970-01-01 01:00:00.000000000 +0100
6527 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmenet47xx.h 2005-08-28 11:12:20.432858848 +0200
6528 @@ -0,0 +1,229 @@
6529 +/*
6530 + * Hardware-specific definitions for
6531 + * Broadcom BCM47XX 10/100 Mbps Ethernet cores.
6532 + *
6533 + * Copyright 2001-2003, Broadcom Corporation
6534 + * All Rights Reserved.
6535 + *
6536 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6537 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6538 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6539 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6540 + * $Id$
6541 + */
6542 +
6543 +#ifndef _bcmenet_47xx_h_
6544 +#define _bcmenet_47xx_h_
6545 +
6546 +#include <bcmdevs.h>
6547 +#include <hnddma.h>
6548 +
6549 +#define BCMENET_NFILTERS 64 /* # ethernet address filter entries */
6550 +#define BCMENET_MCHASHBASE 0x200 /* multicast hash filter base address */
6551 +#define BCMENET_MCHASHSIZE 256 /* multicast hash filter size in bytes */
6552 +#define BCMENET_MAX_DMA 4096 /* chip has 12 bits of DMA addressing */
6553 +
6554 +/* power management event wakeup pattern constants */
6555 +#define BCMENET_NPMP 4 /* chip supports 4 wakeup patterns */
6556 +#define BCMENET_PMPBASE 0x400 /* wakeup pattern base address */
6557 +#define BCMENET_PMPSIZE 0x80 /* 128bytes each pattern */
6558 +#define BCMENET_PMMBASE 0x600 /* wakeup mask base address */
6559 +#define BCMENET_PMMSIZE 0x10 /* 128bits each mask */
6560 +
6561 +/* cpp contortions to concatenate w/arg prescan */
6562 +#ifndef PAD
6563 +#define _PADLINE(line) pad ## line
6564 +#define _XSTR(line) _PADLINE(line)
6565 +#define PAD _XSTR(__LINE__)
6566 +#endif /* PAD */
6567 +
6568 +/* sometimes you just need the enet mib definitions */
6569 +#include <bcmenetmib.h>
6570 +
6571 +/*
6572 + * Host Interface Registers
6573 + */
6574 +typedef volatile struct _bcmenettregs {
6575 + /* Device and Power Control */
6576 + uint32 devcontrol;
6577 + uint32 PAD[2];
6578 + uint32 biststatus;
6579 + uint32 wakeuplength;
6580 + uint32 PAD[3];
6581 +
6582 + /* Interrupt Control */
6583 + uint32 intstatus;
6584 + uint32 intmask;
6585 + uint32 gptimer;
6586 + uint32 PAD[23];
6587 +
6588 + /* Ethernet MAC Address Filtering Control */
6589 + uint32 PAD[2];
6590 + uint32 enetftaddr;
6591 + uint32 enetftdata;
6592 + uint32 PAD[2];
6593 +
6594 + /* Ethernet MAC Control */
6595 + uint32 emactxmaxburstlen;
6596 + uint32 emacrxmaxburstlen;
6597 + uint32 emaccontrol;
6598 + uint32 emacflowcontrol;
6599 +
6600 + uint32 PAD[20];
6601 +
6602 + /* DMA Lazy Interrupt Control */
6603 + uint32 intrecvlazy;
6604 + uint32 PAD[63];
6605 +
6606 + /* DMA engine */
6607 + dmaregs_t dmaregs;
6608 + dmafifo_t dmafifo;
6609 + uint32 PAD[116];
6610 +
6611 + /* EMAC Registers */
6612 + uint32 rxconfig;
6613 + uint32 rxmaxlength;
6614 + uint32 txmaxlength;
6615 + uint32 PAD;
6616 + uint32 mdiocontrol;
6617 + uint32 mdiodata;
6618 + uint32 emacintmask;
6619 + uint32 emacintstatus;
6620 + uint32 camdatalo;
6621 + uint32 camdatahi;
6622 + uint32 camcontrol;
6623 + uint32 enetcontrol;
6624 + uint32 txcontrol;
6625 + uint32 txwatermark;
6626 + uint32 mibcontrol;
6627 + uint32 PAD[49];
6628 +
6629 + /* EMAC MIB counters */
6630 + bcmenetmib_t mib;
6631 +
6632 + uint32 PAD[585];
6633 +
6634 + /* Sonics SiliconBackplane config registers */
6635 + sbconfig_t sbconfig;
6636 +} bcmenetregs_t;
6637 +
6638 +/* device control */
6639 +#define DC_PM ((uint32)1 << 7) /* pattern filtering enable */
6640 +#define DC_IP ((uint32)1 << 10) /* internal ephy present (rev >= 1) */
6641 +#define DC_ER ((uint32)1 << 15) /* ephy reset */
6642 +#define DC_MP ((uint32)1 << 16) /* mii phy mode enable */
6643 +#define DC_CO ((uint32)1 << 17) /* mii phy mode: enable clocks */
6644 +#define DC_PA_MASK 0x7c0000 /* mii phy mode: mdc/mdio phy address */
6645 +#define DC_PA_SHIFT 18
6646 +
6647 +/* wakeup length */
6648 +#define WL_P0_MASK 0x7f /* pattern 0 */
6649 +#define WL_D0 ((uint32)1 << 7)
6650 +#define WL_P1_MASK 0x7f00 /* pattern 1 */
6651 +#define WL_P1_SHIFT 8
6652 +#define WL_D1 ((uint32)1 << 15)
6653 +#define WL_P2_MASK 0x7f0000 /* pattern 2 */
6654 +#define WL_P2_SHIFT 16
6655 +#define WL_D2 ((uint32)1 << 23)
6656 +#define WL_P3_MASK 0x7f000000 /* pattern 3 */
6657 +#define WL_P3_SHIFT 24
6658 +#define WL_D3 ((uint32)1 << 31)
6659 +
6660 +/* intstatus and intmask */
6661 +#define I_PME ((uint32)1 << 6) /* power management event */
6662 +#define I_TO ((uint32)1 << 7) /* general purpose timeout */
6663 +#define I_PC ((uint32)1 << 10) /* descriptor error */
6664 +#define I_PD ((uint32)1 << 11) /* data error */
6665 +#define I_DE ((uint32)1 << 12) /* descriptor protocol error */
6666 +#define I_RU ((uint32)1 << 13) /* receive descriptor underflow */
6667 +#define I_RO ((uint32)1 << 14) /* receive fifo overflow */
6668 +#define I_XU ((uint32)1 << 15) /* transmit fifo underflow */
6669 +#define I_RI ((uint32)1 << 16) /* receive interrupt */
6670 +#define I_XI ((uint32)1 << 24) /* transmit interrupt */
6671 +#define I_EM ((uint32)1 << 26) /* emac interrupt */
6672 +#define I_MW ((uint32)1 << 27) /* mii write */
6673 +#define I_MR ((uint32)1 << 28) /* mii read */
6674 +
6675 +/* emaccontrol */
6676 +#define EMC_CG ((uint32)1 << 0) /* crc32 generation enable */
6677 +#define EMC_EP ((uint32)1 << 2) /* onchip ephy: powerdown (rev >= 1) */
6678 +#define EMC_ED ((uint32)1 << 3) /* onchip ephy: energy detected (rev >= 1) */
6679 +#define EMC_LC_MASK 0xe0 /* onchip ephy: led control (rev >= 1) */
6680 +#define EMC_LC_SHIFT 5
6681 +
6682 +/* emacflowcontrol */
6683 +#define EMF_RFH_MASK 0xff /* rx fifo hi water mark */
6684 +#define EMF_PG ((uint32)1 << 15) /* enable pause frame generation */
6685 +
6686 +/* interrupt receive lazy */
6687 +#define IRL_TO_MASK 0x00ffffff /* timeout */
6688 +#define IRL_FC_MASK 0xff000000 /* frame count */
6689 +#define IRL_FC_SHIFT 24 /* frame count */
6690 +
6691 +/* emac receive config */
6692 +#define ERC_DB ((uint32)1 << 0) /* disable broadcast */
6693 +#define ERC_AM ((uint32)1 << 1) /* accept all multicast */
6694 +#define ERC_RDT ((uint32)1 << 2) /* receive disable while transmitting */
6695 +#define ERC_PE ((uint32)1 << 3) /* promiscuous enable */
6696 +#define ERC_LE ((uint32)1 << 4) /* loopback enable */
6697 +#define ERC_FE ((uint32)1 << 5) /* enable flow control */
6698 +#define ERC_UF ((uint32)1 << 6) /* accept unicast flow control frame */
6699 +#define ERC_RF ((uint32)1 << 7) /* reject filter */
6700 +
6701 +/* emac mdio control */
6702 +#define MC_MF_MASK 0x7f /* mdc frequency */
6703 +#define MC_PE ((uint32)1 << 7) /* mii preamble enable */
6704 +
6705 +/* emac mdio data */
6706 +#define MD_DATA_MASK 0xffff /* r/w data */
6707 +#define MD_TA_MASK 0x30000 /* turnaround value */
6708 +#define MD_TA_SHIFT 16
6709 +#define MD_TA_VALID (2 << MD_TA_SHIFT) /* valid ta */
6710 +#define MD_RA_MASK 0x7c0000 /* register address */
6711 +#define MD_RA_SHIFT 18
6712 +#define MD_PMD_MASK 0xf800000 /* physical media device */
6713 +#define MD_PMD_SHIFT 23
6714 +#define MD_OP_MASK 0x30000000 /* opcode */
6715 +#define MD_OP_SHIFT 28
6716 +#define MD_OP_WRITE (1 << MD_OP_SHIFT) /* write op */
6717 +#define MD_OP_READ (2 << MD_OP_SHIFT) /* read op */
6718 +#define MD_SB_MASK 0xc0000000 /* start bits */
6719 +#define MD_SB_SHIFT 30
6720 +#define MD_SB_START (0x1 << MD_SB_SHIFT) /* start of frame */
6721 +
6722 +/* emac intstatus and intmask */
6723 +#define EI_MII ((uint32)1 << 0) /* mii mdio interrupt */
6724 +#define EI_MIB ((uint32)1 << 1) /* mib interrupt */
6725 +#define EI_FLOW ((uint32)1 << 2) /* flow control interrupt */
6726 +
6727 +/* emac cam data high */
6728 +#define CD_V ((uint32)1 << 16) /* valid bit */
6729 +
6730 +/* emac cam control */
6731 +#define CC_CE ((uint32)1 << 0) /* cam enable */
6732 +#define CC_MS ((uint32)1 << 1) /* mask select */
6733 +#define CC_RD ((uint32)1 << 2) /* read */
6734 +#define CC_WR ((uint32)1 << 3) /* write */
6735 +#define CC_INDEX_MASK 0x3f0000 /* index */
6736 +#define CC_INDEX_SHIFT 16
6737 +#define CC_CB ((uint32)1 << 31) /* cam busy */
6738 +
6739 +/* emac ethernet control */
6740 +#define EC_EE ((uint32)1 << 0) /* emac enable */
6741 +#define EC_ED ((uint32)1 << 1) /* emac disable */
6742 +#define EC_ES ((uint32)1 << 2) /* emac soft reset */
6743 +#define EC_EP ((uint32)1 << 3) /* external phy select */
6744 +
6745 +/* emac transmit control */
6746 +#define EXC_FD ((uint32)1 << 0) /* full duplex */
6747 +#define EXC_FM ((uint32)1 << 1) /* flowmode */
6748 +#define EXC_SB ((uint32)1 << 2) /* single backoff enable */
6749 +#define EXC_SS ((uint32)1 << 3) /* small slottime */
6750 +
6751 +/* emac mib control */
6752 +#define EMC_RZ ((uint32)1 << 0) /* autoclear on read */
6753 +
6754 +/* sometimes you just need the enet rxheader definitions */
6755 +#include <bcmenetrxh.h>
6756 +
6757 +#endif /* _bcmenet_47xx_h_ */
6758 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/bcmenetmib.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmenetmib.h
6759 --- linux-2.6.12.5/arch/mips/bcm947xx/include/bcmenetmib.h 1970-01-01 01:00:00.000000000 +0100
6760 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmenetmib.h 2005-08-28 11:12:20.432858848 +0200
6761 @@ -0,0 +1,81 @@
6762 +/*
6763 + * Hardware-specific MIB definition for
6764 + * Broadcom Home Networking Division
6765 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
6766 + *
6767 + * Copyright 2001-2003, Broadcom Corporation
6768 + * All Rights Reserved.
6769 + *
6770 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6771 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6772 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6773 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6774 + * $Id$
6775 + */
6776 +
6777 +#ifndef _bcmenetmib_h_
6778 +#define _bcmenetmib_h_
6779 +
6780 +/* cpp contortions to concatenate w/arg prescan */
6781 +#ifndef PAD
6782 +#define _PADLINE(line) pad ## line
6783 +#define _XSTR(line) _PADLINE(line)
6784 +#define PAD _XSTR(__LINE__)
6785 +#endif /* PAD */
6786 +
6787 +/*
6788 + * EMAC MIB Registers
6789 + */
6790 +typedef volatile struct {
6791 + uint32 tx_good_octets;
6792 + uint32 tx_good_pkts;
6793 + uint32 tx_octets;
6794 + uint32 tx_pkts;
6795 + uint32 tx_broadcast_pkts;
6796 + uint32 tx_multicast_pkts;
6797 + uint32 tx_len_64;
6798 + uint32 tx_len_65_to_127;
6799 + uint32 tx_len_128_to_255;
6800 + uint32 tx_len_256_to_511;
6801 + uint32 tx_len_512_to_1023;
6802 + uint32 tx_len_1024_to_max;
6803 + uint32 tx_jabber_pkts;
6804 + uint32 tx_oversize_pkts;
6805 + uint32 tx_fragment_pkts;
6806 + uint32 tx_underruns;
6807 + uint32 tx_total_cols;
6808 + uint32 tx_single_cols;
6809 + uint32 tx_multiple_cols;
6810 + uint32 tx_excessive_cols;
6811 + uint32 tx_late_cols;
6812 + uint32 tx_defered;
6813 + uint32 tx_carrier_lost;
6814 + uint32 tx_pause_pkts;
6815 + uint32 PAD[8];
6816 +
6817 + uint32 rx_good_octets;
6818 + uint32 rx_good_pkts;
6819 + uint32 rx_octets;
6820 + uint32 rx_pkts;
6821 + uint32 rx_broadcast_pkts;
6822 + uint32 rx_multicast_pkts;
6823 + uint32 rx_len_64;
6824 + uint32 rx_len_65_to_127;
6825 + uint32 rx_len_128_to_255;
6826 + uint32 rx_len_256_to_511;
6827 + uint32 rx_len_512_to_1023;
6828 + uint32 rx_len_1024_to_max;
6829 + uint32 rx_jabber_pkts;
6830 + uint32 rx_oversize_pkts;
6831 + uint32 rx_fragment_pkts;
6832 + uint32 rx_missed_pkts;
6833 + uint32 rx_crc_align_errs;
6834 + uint32 rx_undersize;
6835 + uint32 rx_crc_errs;
6836 + uint32 rx_align_errs;
6837 + uint32 rx_symbol_errs;
6838 + uint32 rx_pause_pkts;
6839 + uint32 rx_nonpause_pkts;
6840 +} bcmenetmib_t;
6841 +
6842 +#endif /* _bcmenetmib_h_ */
6843 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/bcmenetrxh.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmenetrxh.h
6844 --- linux-2.6.12.5/arch/mips/bcm947xx/include/bcmenetrxh.h 1970-01-01 01:00:00.000000000 +0100
6845 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmenetrxh.h 2005-08-28 11:12:20.433858696 +0200
6846 @@ -0,0 +1,43 @@
6847 +/*
6848 + * Hardware-specific Receive Data Header for the
6849 + * Broadcom Home Networking Division
6850 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
6851 + *
6852 + * Copyright 2001-2003, Broadcom Corporation
6853 + * All Rights Reserved.
6854 + *
6855 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6856 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6857 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6858 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6859 + * $Id$
6860 + */
6861 +
6862 +#ifndef _bcmenetrxh_h_
6863 +#define _bcmenetrxh_h_
6864 +
6865 +/*
6866 + * The Ethernet MAC core returns an 8-byte Receive Frame Data Header
6867 + * with every frame consisting of
6868 + * 16bits of frame length, followed by
6869 + * 16bits of EMAC rx descriptor info, followed by 32bits of undefined.
6870 + */
6871 +typedef volatile struct {
6872 + uint16 len;
6873 + uint16 flags;
6874 + uint16 pad[12];
6875 +} bcmenetrxh_t;
6876 +
6877 +#define RXHDR_LEN 28
6878 +
6879 +#define RXF_L ((uint16)1 << 11) /* last buffer in a frame */
6880 +#define RXF_MISS ((uint16)1 << 7) /* received due to promisc mode */
6881 +#define RXF_BRDCAST ((uint16)1 << 6) /* dest is broadcast address */
6882 +#define RXF_MULT ((uint16)1 << 5) /* dest is multicast address */
6883 +#define RXF_LG ((uint16)1 << 4) /* frame length > rxmaxlength */
6884 +#define RXF_NO ((uint16)1 << 3) /* odd number of nibbles */
6885 +#define RXF_RXER ((uint16)1 << 2) /* receive symbol error */
6886 +#define RXF_CRC ((uint16)1 << 1) /* crc error */
6887 +#define RXF_OV ((uint16)1 << 0) /* fifo overflow */
6888 +
6889 +#endif /* _bcmenetrxh_h_ */
6890 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/bcmnvram.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmnvram.h
6891 --- linux-2.6.12.5/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
6892 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmnvram.h 2005-08-28 11:12:20.433858696 +0200
6893 @@ -0,0 +1,131 @@
6894 +/*
6895 + * NVRAM variable manipulation
6896 + *
6897 + * $Copyright Open Broadcom Corporation$
6898 + *
6899 + * $Id: bcmnvram.h,v 1.1.1.1 2004/01/21 03:50:44 gigis Exp $
6900 + */
6901 +
6902 +#ifndef _bcmnvram_h_
6903 +#define _bcmnvram_h_
6904 +
6905 +#ifndef _LANGUAGE_ASSEMBLY
6906 +
6907 +#include <typedefs.h>
6908 +
6909 +struct nvram_header {
6910 + uint32 magic;
6911 + uint32 len;
6912 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:27 init, mem. test 28, 29-31 reserved */
6913 + uint32 config_refresh; /* 0:15 config, 16:31 refresh */
6914 + uint32 config_ncdl; /* ncdl values for memc */
6915 +};
6916 +
6917 +struct nvram_tuple {
6918 + char *name;
6919 + char *value;
6920 + struct nvram_tuple *next;
6921 +};
6922 +
6923 +/*
6924 + * Initialize NVRAM access. May be unnecessary or undefined on certain
6925 + * platforms.
6926 + */
6927 +extern int nvram_init(void *sbh);
6928 +
6929 +/*
6930 + * Disable NVRAM access. May be unnecessary or undefined on certain
6931 + * platforms.
6932 + */
6933 +extern void nvram_exit(void);
6934 +
6935 +/*
6936 + * Get the value of an NVRAM variable. The pointer returned may be
6937 + * invalid after a set.
6938 + * @param name name of variable to get
6939 + * @return value of variable or NULL if undefined
6940 + */
6941 +extern char * nvram_get(const char *name);
6942 +
6943 +/*
6944 + * Get the value of an NVRAM variable.
6945 + * @param name name of variable to get
6946 + * @return value of variable or NUL if undefined
6947 + */
6948 +#define nvram_safe_get(name) (nvram_get(name) ? : "")
6949 +
6950 +/*
6951 + * Match an NVRAM variable.
6952 + * @param name name of variable to match
6953 + * @param match value to compare against value of variable
6954 + * @return TRUE if variable is defined and its value is string equal
6955 + * to match or FALSE otherwise
6956 + */
6957 +static INLINE int
6958 +nvram_match(char *name, char *match) {
6959 + const char *value = nvram_get(name);
6960 + return (value && !strcmp(value, match));
6961 +}
6962 +
6963 +/*
6964 + * Inversely match an NVRAM variable.
6965 + * @param name name of variable to match
6966 + * @param match value to compare against value of variable
6967 + * @return TRUE if variable is defined and its value is not string
6968 + * equal to invmatch or FALSE otherwise
6969 + */
6970 +static INLINE int
6971 +nvram_invmatch(char *name, char *invmatch) {
6972 + const char *value = nvram_get(name);
6973 + return (value && strcmp(value, invmatch));
6974 +}
6975 +
6976 +/*
6977 + * Set the value of an NVRAM variable. The name and value strings are
6978 + * copied into private storage. Pointers to previously set values
6979 + * may become invalid. The new value may be immediately
6980 + * retrieved but will not be permanently stored until a commit.
6981 + * @param name name of variable to set
6982 + * @param value value of variable
6983 + * @return 0 on success and errno on failure
6984 + */
6985 +extern int nvram_set(const char *name, const char *value);
6986 +
6987 +/*
6988 + * Unset an NVRAM variable. Pointers to previously set values
6989 + * remain valid until a set.
6990 + * @param name name of variable to unset
6991 + * @return 0 on success and errno on failure
6992 + * NOTE: use nvram_commit to commit this change to flash.
6993 + */
6994 +extern int nvram_unset(const char *name);
6995 +
6996 +/*
6997 + * Commit NVRAM variables to permanent storage. All pointers to values
6998 + * may be invalid after a commit.
6999 + * NVRAM values are undefined after a commit.
7000 + * @return 0 on success and errno on failure
7001 + */
7002 +extern int nvram_commit(void);
7003 +
7004 +/*
7005 + * Get all NVRAM variables (format name=value\0 ... \0\0).
7006 + * @param buf buffer to store variables
7007 + * @param count size of buffer in bytes
7008 + * @return 0 on success and errno on failure
7009 + */
7010 +extern int nvram_getall(char *buf, int count);
7011 +
7012 +extern int kernel_write(unsigned char *buffer, int offset, int length);
7013 +
7014 +#endif /* _LANGUAGE_ASSEMBLY */
7015 +
7016 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
7017 +#define NVRAM_VERSION 1
7018 +#define NVRAM_HEADER_SIZE 20
7019 +#define NVRAM_LOC_GAP 0x100000
7020 +#define NVRAM_SPACE 0x2000
7021 +#define NVRAM_FIRST_LOC (0xbfd00000 - NVRAM_SPACE)
7022 +#define NVRAM_LAST_LOC (0xc0000000 - NVRAM_SPACE)
7023 +
7024 +#endif /* _bcmnvram_h_ */
7025 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/bcmsrom.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmsrom.h
7026 --- linux-2.6.12.5/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
7027 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmsrom.h 2005-08-28 11:12:20.433858696 +0200
7028 @@ -0,0 +1,24 @@
7029 +/*
7030 + * Misc useful routines to access NIC srom
7031 + *
7032 + * Copyright 2001-2003, Broadcom Corporation
7033 + * All Rights Reserved.
7034 + *
7035 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7036 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7037 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7038 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7039 + *
7040 + * $Id$
7041 + */
7042 +
7043 +#ifndef _bcmsrom_h_
7044 +#define _bcmsrom_h_
7045 +
7046 +extern int srom_var_init(uint bus, void *curmap, void *osh, char **vars, int *count);
7047 +
7048 +extern int srom_read(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf);
7049 +extern int srom_write(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf);
7050 +extern int srom_parsecis(uint8 *cis, char **vars, int *count);
7051 +
7052 +#endif /* _bcmsrom_h_ */
7053 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/bcmutils.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmutils.h
7054 --- linux-2.6.12.5/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
7055 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmutils.h 2005-08-28 11:12:20.435858392 +0200
7056 @@ -0,0 +1,136 @@
7057 +/*
7058 + * Misc useful os-independent macros and functions.
7059 + *
7060 + * Copyright 2001-2003, Broadcom Corporation
7061 + * All Rights Reserved.
7062 + *
7063 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7064 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7065 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7066 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7067 + * $Id$
7068 + */
7069 +
7070 +#ifndef _bcmutils_h_
7071 +#define _bcmutils_h_
7072 +
7073 +#ifndef MIN
7074 +#define MIN(a, b) (((a)<(b))?(a):(b))
7075 +#endif
7076 +
7077 +#ifndef MAX
7078 +#define MAX(a, b) (((a)>(b))?(a):(b))
7079 +#endif
7080 +
7081 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
7082 +#define ROUNDUP(x, y) ((((ulong)(x)+((y)-1))/(y))*(y))
7083 +#define ISALIGNED(a, x) (((uint)(a) & ((x)-1)) == 0)
7084 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
7085 +#define OFFSETOF(type, member) ((uint) &((type *)0)->member)
7086 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
7087 +
7088 +/* bit map related macros */
7089 +#ifndef setbit
7090 +#define NBBY 8 /* 8 bits per byte */
7091 +#define setbit(a,i) ((a)[(i)/NBBY] |= 1<<((i)%NBBY))
7092 +#define clrbit(a,i) ((a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
7093 +#define isset(a,i) ((a)[(i)/NBBY] & (1<<((i)%NBBY)))
7094 +#define isclr(a,i) (((a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
7095 +#endif
7096 +
7097 +#define NBITS(type) (sizeof (type) * 8)
7098 +
7099 +#define _BCM_U 0x01 /* upper */
7100 +#define _BCM_L 0x02 /* lower */
7101 +#define _BCM_D 0x04 /* digit */
7102 +#define _BCM_C 0x08 /* cntrl */
7103 +#define _BCM_P 0x10 /* punct */
7104 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
7105 +#define _BCM_X 0x40 /* hex digit */
7106 +#define _BCM_SP 0x80 /* hard space (0x20) */
7107 +
7108 +extern unsigned char bcm_ctype[];
7109 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
7110 +
7111 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
7112 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
7113 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
7114 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
7115 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
7116 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
7117 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
7118 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
7119 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
7120 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
7121 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
7122 +
7123 +/*
7124 + * Spin at most 'us' microseconds while 'exp' is true.
7125 + * Caller should explicitly test 'exp' when this completes
7126 + * and take appropriate error action if 'exp' is still true.
7127 + */
7128 +#define SPINWAIT(exp, us) { \
7129 + uint countdown = (us) + 9; \
7130 + while ((exp) && (countdown >= 10)) {\
7131 + OSL_DELAY(10); \
7132 + countdown -= 10; \
7133 + } \
7134 +}
7135 +
7136 +/* generic osl packet queue */
7137 +struct pktq {
7138 + void *head;
7139 + void *tail;
7140 + uint len;
7141 + uint maxlen;
7142 +};
7143 +#define DEFAULT_QLEN 128
7144 +
7145 +#define pktq_len(q) ((q)->len)
7146 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
7147 +#define pktq_head(q) ((q)->head)
7148 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
7149 +
7150 +/* crc defines */
7151 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
7152 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
7153 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
7154 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
7155 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
7156 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
7157 +
7158 +/* tag_ID/length/value_buffer tuple */
7159 +typedef struct bcm_tlv {
7160 + uint8 id;
7161 + uint8 len;
7162 + uint8 data[1];
7163 +} bcm_tlv_t;
7164 +
7165 +/* externs */
7166 +extern uint bcm_atoi(char *s);
7167 +extern uchar bcm_toupper(uchar c);
7168 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
7169 +extern void deadbeef(char *p, uint len);
7170 +extern void prhex(char *msg, uchar *buf, uint len);
7171 +extern void prpkt(char *msg, void *drv, void *p0);
7172 +extern uint pktcopy(void *drv, void *p, uint offset, int len, uchar *buf);
7173 +extern uint pkttotlen(void *drv, void *);
7174 +extern uchar *bcm_ether_ntoa(char *ea, char *buf);
7175 +extern int bcm_ether_atoe(char *p, char *ea);
7176 +extern void bcm_mdelay(uint ms);
7177 +extern char *getvar(char *vars, char *name);
7178 +extern int getintvar(char *vars, char *name);
7179 +
7180 +extern uint8 crc8(uint8 *p, uint nbytes, uint8 crc);
7181 +extern uint16 crc16(uint8 *p, uint nbytes, uint16 crc);
7182 +extern uint32 crc32(uint8 *p, uint nbytes, uint32 crc);
7183 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
7184 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
7185 +extern void pktqinit(struct pktq *q, int maxlen);
7186 +extern void pktenq(struct pktq *q, void *p, bool lifo);
7187 +extern void *pktdeq(struct pktq *q);
7188 +
7189 +#define bcmlog(fmt, a1, a2)
7190 +#define bcmdumplog(buf, size) *buf = '\0'
7191 +
7192 +#endif /* _bcmutils_h_ */
7193 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/bitfuncs.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bitfuncs.h
7194 --- linux-2.6.12.5/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
7195 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bitfuncs.h 2005-08-28 11:12:20.435858392 +0200
7196 @@ -0,0 +1,85 @@
7197 +/*
7198 + * bit manipulation utility functions
7199 + *
7200 + * Copyright 2001-2003, Broadcom Corporation
7201 + * All Rights Reserved.
7202 + *
7203 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7204 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7205 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7206 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7207 + * $Id$
7208 + */
7209 +
7210 +#ifndef _BITFUNCS_H
7211 +#define _BITFUNCS_H
7212 +
7213 +#include <typedefs.h>
7214 +
7215 +/* local prototypes */
7216 +static INLINE uint32 find_msbit(uint32 x);
7217 +
7218 +
7219 +/*
7220 + * find_msbit: returns index of most significant set bit in x, with index
7221 + * range defined as 0-31. NOTE: returns zero if input is zero.
7222 + */
7223 +
7224 +#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
7225 +
7226 +/*
7227 + * Implementation for Pentium processors and gcc. Note that this
7228 + * instruction is actually very slow on some processors (e.g., family 5,
7229 + * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
7230 + * implementation instead.
7231 + */
7232 +static INLINE uint32 find_msbit(uint32 x)
7233 +{
7234 + uint msbit;
7235 + __asm__("bsrl %1,%0"
7236 + :"=r" (msbit)
7237 + :"r" (x));
7238 + return msbit;
7239 +}
7240 +
7241 +#else
7242 +
7243 +/*
7244 + * Generic Implementation
7245 + */
7246 +
7247 +#define DB_POW_MASK16 0xffff0000
7248 +#define DB_POW_MASK8 0x0000ff00
7249 +#define DB_POW_MASK4 0x000000f0
7250 +#define DB_POW_MASK2 0x0000000c
7251 +#define DB_POW_MASK1 0x00000002
7252 +
7253 +static INLINE uint32 find_msbit(uint32 x)
7254 +{
7255 + uint32 temp_x = x;
7256 + uint msbit = 0;
7257 + if (temp_x & DB_POW_MASK16) {
7258 + temp_x >>= 16;
7259 + msbit = 16;
7260 + }
7261 + if (temp_x & DB_POW_MASK8) {
7262 + temp_x >>= 8;
7263 + msbit += 8;
7264 + }
7265 + if (temp_x & DB_POW_MASK4) {
7266 + temp_x >>= 4;
7267 + msbit += 4;
7268 + }
7269 + if (temp_x & DB_POW_MASK2) {
7270 + temp_x >>= 2;
7271 + msbit += 2;
7272 + }
7273 + if (temp_x & DB_POW_MASK1) {
7274 + msbit += 1;
7275 + }
7276 + return(msbit);
7277 +}
7278 +
7279 +#endif
7280 +
7281 +#endif /* _BITFUNCS_H */
7282 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/epivers.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/epivers.h
7283 --- linux-2.6.12.5/arch/mips/bcm947xx/include/epivers.h 1970-01-01 01:00:00.000000000 +0100
7284 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/epivers.h 2005-08-28 11:12:20.435858392 +0200
7285 @@ -0,0 +1,69 @@
7286 +/*
7287 + * Copyright 2001-2003, Broadcom Corporation
7288 + * All Rights Reserved.
7289 + *
7290 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7291 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7292 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7293 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7294 + *
7295 + * $Id$
7296 + *
7297 +*/
7298 +
7299 +#ifndef _epivers_h_
7300 +#define _epivers_h_
7301 +
7302 +#ifdef linux
7303 +#include <linux/config.h>
7304 +#endif
7305 +
7306 +/* Vendor Name, ASCII, 32 chars max */
7307 +#ifdef COMPANYNAME
7308 +#define HPNA_VENDOR COMPANYNAME
7309 +#else
7310 +#define HPNA_VENDOR "Broadcom Corporation"
7311 +#endif
7312 +
7313 +/* Driver Date, ASCII, 32 chars max */
7314 +#define HPNA_DRV_BUILD_DATE __DATE__
7315 +
7316 +/* Hardware Manufacture Date, ASCII, 32 chars max */
7317 +#define HPNA_HW_MFG_DATE "Not Specified"
7318 +
7319 +/* See documentation for Device Type values, 32 values max */
7320 +#ifndef HPNA_DEV_TYPE
7321 +
7322 +#if defined(CONFIG_BRCM_VJ)
7323 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
7324 +
7325 +#elif defined(CONFIG_BCRM_93725)
7326 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
7327 +
7328 +#else
7329 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
7330 +
7331 +#endif
7332 +
7333 +#endif /* !HPNA_DEV_TYPE */
7334 +
7335 +
7336 +#define EPI_MAJOR_VERSION 1
7337 +
7338 +#define EPI_MINOR_VERSION 1
7339 +
7340 +#define EPI_RC_NUMBER 2
7341 +
7342 +#define EPI_INCREMENTAL_NUMBER 0
7343 +
7344 +#define EPI_BUILD_NUMBER 0
7345 +
7346 +#define EPI_VERSION 1,1,2,0
7347 +
7348 +#define EPI_VERSION_NUM 0x01010200
7349 +
7350 +/* Driver Version String, ASCII, 32 chars max */
7351 +#define EPI_VERSION_STR "1.1.2.0"
7352 +#define EPI_ROUTER_VERSION_STR "1.1.2.0"
7353 +
7354 +#endif /* _epivers_h_ */
7355 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/epivers.h.in linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/epivers.h.in
7356 --- linux-2.6.12.5/arch/mips/bcm947xx/include/epivers.h.in 1970-01-01 01:00:00.000000000 +0100
7357 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/epivers.h.in 2005-08-28 11:12:20.436858240 +0200
7358 @@ -0,0 +1,69 @@
7359 +/*
7360 + * Copyright 2001-2003, Broadcom Corporation
7361 + * All Rights Reserved.
7362 + *
7363 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7364 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7365 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7366 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7367 + *
7368 + * $Id$
7369 + *
7370 +*/
7371 +
7372 +#ifndef _epivers_h_
7373 +#define _epivers_h_
7374 +
7375 +#ifdef linux
7376 +#include <linux/config.h>
7377 +#endif
7378 +
7379 +/* Vendor Name, ASCII, 32 chars max */
7380 +#ifdef COMPANYNAME
7381 +#define HPNA_VENDOR COMPANYNAME
7382 +#else
7383 +#define HPNA_VENDOR "Broadcom Corporation"
7384 +#endif
7385 +
7386 +/* Driver Date, ASCII, 32 chars max */
7387 +#define HPNA_DRV_BUILD_DATE __DATE__
7388 +
7389 +/* Hardware Manufacture Date, ASCII, 32 chars max */
7390 +#define HPNA_HW_MFG_DATE "Not Specified"
7391 +
7392 +/* See documentation for Device Type values, 32 values max */
7393 +#ifndef HPNA_DEV_TYPE
7394 +
7395 +#if defined(CONFIG_BRCM_VJ)
7396 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
7397 +
7398 +#elif defined(CONFIG_BCRM_93725)
7399 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
7400 +
7401 +#else
7402 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
7403 +
7404 +#endif
7405 +
7406 +#endif /* !HPNA_DEV_TYPE */
7407 +
7408 +
7409 +#define EPI_MAJOR_VERSION @EPI_MAJOR_VERSION@
7410 +
7411 +#define EPI_MINOR_VERSION @EPI_MINOR_VERSION@
7412 +
7413 +#define EPI_RC_NUMBER @EPI_RC_NUMBER@
7414 +
7415 +#define EPI_INCREMENTAL_NUMBER @EPI_INCREMENTAL_NUMBER@
7416 +
7417 +#define EPI_BUILD_NUMBER @EPI_BUILD_NUMBER@
7418 +
7419 +#define EPI_VERSION @EPI_VERSION@
7420 +
7421 +#define EPI_VERSION_NUM @EPI_VERSION_NUM@
7422 +
7423 +/* Driver Version String, ASCII, 32 chars max */
7424 +#define EPI_VERSION_STR "@EPI_VERSION_STR@"
7425 +#define EPI_ROUTER_VERSION_STR "@EPI_ROUTER_VERSION_STR@"
7426 +
7427 +#endif /* _epivers_h_ */
7428 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/etsockio.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/etsockio.h
7429 --- linux-2.6.12.5/arch/mips/bcm947xx/include/etsockio.h 1970-01-01 01:00:00.000000000 +0100
7430 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/etsockio.h 2005-08-28 11:12:20.436858240 +0200
7431 @@ -0,0 +1,60 @@
7432 +/*
7433 + * Driver-specific socket ioctls
7434 + * used by BSD, Linux, and PSOS
7435 + * Broadcom BCM44XX 10/100Mbps Ethernet Device Driver
7436 + *
7437 + * Copyright 2001-2003, Broadcom Corporation
7438 + * All Rights Reserved.
7439 + *
7440 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7441 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7442 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7443 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7444 + *
7445 + * $Id$
7446 + */
7447 +
7448 +#ifndef _etsockio_h_
7449 +#define _etsockio_h_
7450 +
7451 +/* THESE MUST BE CONTIGUOUS AND CONSISTENT WITH VALUES IN ETC.H */
7452 +
7453 +
7454 +#if defined(linux)
7455 +#define SIOCSETCUP (SIOCDEVPRIVATE + 0)
7456 +#define SIOCSETCDOWN (SIOCDEVPRIVATE + 1)
7457 +#define SIOCSETCLOOP (SIOCDEVPRIVATE + 2)
7458 +#define SIOCGETCDUMP (SIOCDEVPRIVATE + 3)
7459 +#define SIOCSETCSETMSGLEVEL (SIOCDEVPRIVATE + 4)
7460 +#define SIOCSETCPROMISC (SIOCDEVPRIVATE + 5)
7461 +#define SIOCSETCTXDOWN (SIOCDEVPRIVATE + 6) /* obsolete */
7462 +#define SIOCSETCSPEED (SIOCDEVPRIVATE + 7)
7463 +#define SIOCTXGEN (SIOCDEVPRIVATE + 8)
7464 +#define SIOCGETCPHYRD (SIOCDEVPRIVATE + 9)
7465 +#define SIOCSETCPHYWR (SIOCDEVPRIVATE + 10)
7466 +#define SIOCPERF (SIOCDEVPRIVATE + 11)
7467 +#define SIOCPERFDMA (SIOCDEVPRIVATE + 12)
7468 +
7469 +#else /* !linux */
7470 +
7471 +#define SIOCSETCUP _IOWR('e', 130 + 0, struct ifreq)
7472 +#define SIOCSETCDOWN _IOWR('e', 130 + 1, struct ifreq)
7473 +#define SIOCSETCLOOP _IOWR('e', 130 + 2, struct ifreq)
7474 +#define SIOCGETCDUMP _IOWR('e', 130 + 3, struct ifreq)
7475 +#define SIOCSETCSETMSGLEVEL _IOWR('e', 130 + 4, struct ifreq)
7476 +#define SIOCSETCPROMISC _IOWR('e', 130 + 5, struct ifreq)
7477 +#define SIOCSETCTXDOWN _IOWR('e', 130 + 6, struct ifreq) /* obsolete */
7478 +#define SIOCSETCSPEED _IOWR('e', 130 + 7, struct ifreq)
7479 +#define SIOCTXGEN _IOWR('e', 130 + 8, struct ifreq)
7480 +
7481 +#endif
7482 +
7483 +/* arg to SIOCTXGEN */
7484 +struct txg {
7485 + uint32 num; /* number of frames to send */
7486 + uint32 delay; /* delay in microseconds between sending each */
7487 + uint32 size; /* size of ether frame to send */
7488 + uchar buf[1514]; /* starting ether frame data */
7489 +};
7490 +
7491 +#endif
7492 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/flash.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/flash.h
7493 --- linux-2.6.12.5/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
7494 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/flash.h 2005-08-28 11:12:20.437858088 +0200
7495 @@ -0,0 +1,184 @@
7496 +/*
7497 + * flash.h: Common definitions for flash access.
7498 + *
7499 + * Copyright 2001-2003, Broadcom Corporation
7500 + * All Rights Reserved.
7501 + *
7502 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7503 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7504 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7505 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7506 + *
7507 + * $Id$
7508 + */
7509 +
7510 +/* Types of flashes we know about */
7511 +typedef enum _flash_type {OLD, BSC, SCS, AMD, SST} flash_type_t;
7512 +
7513 +/* Commands to write/erase the flases */
7514 +typedef struct _flash_cmds{
7515 + flash_type_t type;
7516 + bool need_unlock;
7517 + uint16 pre_erase;
7518 + uint16 erase_block;
7519 + uint16 erase_chip;
7520 + uint16 write_word;
7521 + uint16 write_buf;
7522 + uint16 clear_csr;
7523 + uint16 read_csr;
7524 + uint16 read_id;
7525 + uint16 confirm;
7526 + uint16 read_array;
7527 +} flash_cmds_t;
7528 +
7529 +#define UNLOCK_CMD_WORDS 2
7530 +
7531 +typedef struct _unlock_cmd {
7532 + uint addr[UNLOCK_CMD_WORDS];
7533 + uint16 cmd[UNLOCK_CMD_WORDS];
7534 +} unlock_cmd_t;
7535 +
7536 +/* Flash descriptors */
7537 +typedef struct _flash_desc {
7538 + uint16 mfgid; /* Manufacturer Id */
7539 + uint16 devid; /* Device Id */
7540 + uint size; /* Total size in bytes */
7541 + uint width; /* Device width in bytes */
7542 + flash_type_t type; /* Device type old, S, J */
7543 + uint bsize; /* Block size */
7544 + uint nb; /* Number of blocks */
7545 + uint ff; /* First full block */
7546 + uint lf; /* Last full block */
7547 + uint nsub; /* Number of subblocks */
7548 + uint *subblocks; /* Offsets for subblocks */
7549 + char *desc; /* Description */
7550 +} flash_desc_t;
7551 +
7552 +
7553 +#ifdef DECLARE_FLASHES
7554 +
7555 +flash_cmds_t flash_cmds[] = {
7556 +/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
7557 + { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
7558 + { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
7559 + { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
7560 + { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
7561 + { 0 }
7562 +};
7563 +
7564 +unlock_cmd_t unlock_cmd_amd = {
7565 +#ifdef MIPSEB
7566 +/* addr: */ { 0x0aa8, 0x0556},
7567 +#else
7568 +/* addr: */ { 0x0aaa, 0x0554},
7569 +#endif
7570 +/* data: */ { 0xaa, 0x55}
7571 +};
7572 +
7573 +unlock_cmd_t unlock_cmd_sst = {
7574 +#ifdef MIPSEB
7575 +/* addr: */ { 0xaaa8, 0x5556},
7576 +#else
7577 +/* addr: */ { 0xaaaa, 0x5554},
7578 +#endif
7579 +/* data: */ { 0xaa, 0x55}
7580 +};
7581 +
7582 +#define AMD_CMD 0xaaa
7583 +#define SST_CMD 0xaaaa
7584 +
7585 +/* intel unlock block cmds */
7586 +#define INTEL_UNLOCK1 0x60
7587 +#define INTEL_UNLOCK2 0xD0
7588 +
7589 +/* Just eight blocks of 8KB byte each */
7590 +
7591 +uint blk8x8k[] = { 0x00000000,
7592 + 0x00002000,
7593 + 0x00004000,
7594 + 0x00006000,
7595 + 0x00008000,
7596 + 0x0000a000,
7597 + 0x0000c000,
7598 + 0x0000e000,
7599 + 0x00010000
7600 +};
7601 +
7602 +/* Funky AMD arrangement for 29xx800's */
7603 +uint amd800[] = { 0x00000000, /* 16KB */
7604 + 0x00004000, /* 32KB */
7605 + 0x0000c000, /* 8KB */
7606 + 0x0000e000, /* 8KB */
7607 + 0x00010000, /* 8KB */
7608 + 0x00012000, /* 8KB */
7609 + 0x00014000, /* 32KB */
7610 + 0x0001c000, /* 16KB */
7611 + 0x00020000
7612 +};
7613 +
7614 +/* AMD arrangement for 29xx160's */
7615 +uint amd4112[] = { 0x00000000, /* 32KB */
7616 + 0x00008000, /* 8KB */
7617 + 0x0000a000, /* 8KB */
7618 + 0x0000c000, /* 16KB */
7619 + 0x00010000
7620 +};
7621 +uint amd2114[] = { 0x00000000, /* 16KB */
7622 + 0x00004000, /* 8KB */
7623 + 0x00006000, /* 8KB */
7624 + 0x00008000, /* 32KB */
7625 + 0x00010000
7626 +};
7627 +
7628 +
7629 +
7630 +flash_desc_t flashes[] = {
7631 + { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
7632 + { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
7633 + { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
7634 + { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
7635 + { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
7636 + { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
7637 + { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
7638 + { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
7639 + { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
7640 + { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
7641 + { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
7642 + { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
7643 + { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
7644 + { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
7645 + { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
7646 + { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
7647 + { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
7648 + { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
7649 + { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
7650 + { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
7651 + { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
7652 + { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
7653 + { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
7654 + { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
7655 + { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
7656 + { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
7657 + { 0x0001, 0x2201, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
7658 + { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
7659 + { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
7660 + { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
7661 + { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
7662 + { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
7663 + { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
7664 + { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
7665 + { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
7666 + { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
7667 + { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
7668 + { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
7669 + { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
7670 + { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
7671 +};
7672 +
7673 +#else
7674 +
7675 +extern flash_cmds_t flash_cmds[];
7676 +extern unlock_cmd_t unlock_cmd;
7677 +extern flash_desc_t flashes[];
7678 +
7679 +#endif
7680 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/flashutl.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/flashutl.h
7681 --- linux-2.6.12.5/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
7682 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/flashutl.h 2005-08-28 11:12:20.437858088 +0200
7683 @@ -0,0 +1,34 @@
7684 +/*
7685 + * BCM47XX FLASH driver interface
7686 + *
7687 + * Copyright 2001-2003, Broadcom Corporation
7688 + * All Rights Reserved.
7689 + *
7690 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7691 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7692 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7693 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7694 + * $Id$
7695 + */
7696 +
7697 +#ifndef _flashutl_h_
7698 +#define _flashutl_h_
7699 +
7700 +#define FLASH_BASE 0xbfc00000 /* BCM4710 */
7701 +
7702 +int flash_init(void* base_addr, char *flash_str);
7703 +int flash_erase(void);
7704 +int flash_eraseblk(unsigned long off);
7705 +int flash_write(unsigned long off, uint16 *src, uint nbytes);
7706 +unsigned long flash_block_base(unsigned long off);
7707 +unsigned long flash_block_lim(unsigned long off);
7708 +int FlashWriteRange(unsigned short* dst, unsigned short* src, unsigned int numbytes);
7709 +
7710 +void nvWrite(unsigned short *data, unsigned int len);
7711 +
7712 +/* Global vars */
7713 +extern char* flashutl_base;
7714 +extern flash_desc_t* flashutl_desc;
7715 +extern flash_cmds_t* flashutl_cmd;
7716 +
7717 +#endif /* _flashutl_h_ */
7718 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/hnddma.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/hnddma.h
7719 --- linux-2.6.12.5/arch/mips/bcm947xx/include/hnddma.h 1970-01-01 01:00:00.000000000 +0100
7720 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/hnddma.h 2005-08-28 11:12:20.438857936 +0200
7721 @@ -0,0 +1,181 @@
7722 +/*
7723 + * Generic Broadcom Home Networking Division (HND) DMA engine definitions.
7724 + * This supports the following chips: BCM42xx, 44xx, 47xx .
7725 + *
7726 + * $Id$
7727 + * Copyright 2001-2003, Broadcom Corporation
7728 + * All Rights Reserved.
7729 + *
7730 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7731 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7732 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7733 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7734 + */
7735 +
7736 +#ifndef _hnddma_h_
7737 +#define _hnddma_h_
7738 +
7739 +/*
7740 + * Each DMA processor consists of a transmit channel and a receive channel.
7741 + */
7742 +typedef volatile struct {
7743 + /* transmit channel */
7744 + uint32 xmtcontrol; /* enable, et al */
7745 + uint32 xmtaddr; /* descriptor ring base address (4K aligned) */
7746 + uint32 xmtptr; /* last descriptor posted to chip */
7747 + uint32 xmtstatus; /* current active descriptor, et al */
7748 +
7749 + /* receive channel */
7750 + uint32 rcvcontrol; /* enable, et al */
7751 + uint32 rcvaddr; /* descriptor ring base address (4K aligned) */
7752 + uint32 rcvptr; /* last descriptor posted to chip */
7753 + uint32 rcvstatus; /* current active descriptor, et al */
7754 +} dmaregs_t;
7755 +
7756 +typedef volatile struct {
7757 + /* diag access */
7758 + uint32 fifoaddr; /* diag address */
7759 + uint32 fifodatalow; /* low 32bits of data */
7760 + uint32 fifodatahigh; /* high 32bits of data */
7761 + uint32 pad; /* reserved */
7762 +} dmafifo_t;
7763 +
7764 +/* transmit channel control */
7765 +#define XC_XE ((uint32)1 << 0) /* transmit enable */
7766 +#define XC_SE ((uint32)1 << 1) /* transmit suspend request */
7767 +#define XC_LE ((uint32)1 << 2) /* loopback enable */
7768 +#define XC_FL ((uint32)1 << 4) /* flush request */
7769 +
7770 +/* transmit descriptor table pointer */
7771 +#define XP_LD_MASK 0xfff /* last valid descriptor */
7772 +
7773 +/* transmit channel status */
7774 +#define XS_CD_MASK 0x0fff /* current descriptor pointer */
7775 +#define XS_XS_MASK 0xf000 /* transmit state */
7776 +#define XS_XS_SHIFT 12
7777 +#define XS_XS_DISABLED 0x0000 /* disabled */
7778 +#define XS_XS_ACTIVE 0x1000 /* active */
7779 +#define XS_XS_IDLE 0x2000 /* idle wait */
7780 +#define XS_XS_STOPPED 0x3000 /* stopped */
7781 +#define XS_XS_SUSP 0x4000 /* suspend pending */
7782 +#define XS_XE_MASK 0xf0000 /* transmit errors */
7783 +#define XS_XE_SHIFT 16
7784 +#define XS_XE_NOERR 0x00000 /* no error */
7785 +#define XS_XE_DPE 0x10000 /* descriptor protocol error */
7786 +#define XS_XE_DFU 0x20000 /* data fifo underrun */
7787 +#define XS_XE_BEBR 0x30000 /* bus error on buffer read */
7788 +#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
7789 +#define XS_FL ((uint32)1 << 20) /* flushed */
7790 +
7791 +/* receive channel control */
7792 +#define RC_RE ((uint32)1 << 0) /* receive enable */
7793 +#define RC_RO_MASK 0xfe /* receive frame offset */
7794 +#define RC_RO_SHIFT 1
7795 +#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
7796 +
7797 +/* receive descriptor table pointer */
7798 +#define RP_LD_MASK 0xfff /* last valid descriptor */
7799 +
7800 +/* receive channel status */
7801 +#define RS_CD_MASK 0x0fff /* current descriptor pointer */
7802 +#define RS_RS_MASK 0xf000 /* receive state */
7803 +#define RS_RS_SHIFT 12
7804 +#define RS_RS_DISABLED 0x0000 /* disabled */
7805 +#define RS_RS_ACTIVE 0x1000 /* active */
7806 +#define RS_RS_IDLE 0x2000 /* idle wait */
7807 +#define RS_RS_STOPPED 0x3000 /* reserved */
7808 +#define RS_RE_MASK 0xf0000 /* receive errors */
7809 +#define RS_RE_SHIFT 16
7810 +#define RS_RE_NOERR 0x00000 /* no error */
7811 +#define RS_RE_DPE 0x10000 /* descriptor protocol error */
7812 +#define RS_RE_DFO 0x20000 /* data fifo overflow */
7813 +#define RS_RE_BEBW 0x30000 /* bus error on buffer write */
7814 +#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
7815 +
7816 +/* fifoaddr */
7817 +#define FA_OFF_MASK 0xffff /* offset */
7818 +#define FA_SEL_MASK 0xf0000 /* select */
7819 +#define FA_SEL_SHIFT 16
7820 +#define FA_SEL_XDD 0x00000 /* transmit dma data */
7821 +#define FA_SEL_XDP 0x10000 /* transmit dma pointers */
7822 +#define FA_SEL_RDD 0x40000 /* receive dma data */
7823 +#define FA_SEL_RDP 0x50000 /* receive dma pointers */
7824 +#define FA_SEL_XFD 0x80000 /* transmit fifo data */
7825 +#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
7826 +#define FA_SEL_RFD 0xc0000 /* receive fifo data */
7827 +#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
7828 +
7829 +/*
7830 + * DMA Descriptor
7831 + * Descriptors are only read by the hardware, never written back.
7832 + */
7833 +typedef volatile struct {
7834 + uint32 ctrl; /* misc control bits & bufcount */
7835 + uint32 addr; /* data buffer address */
7836 +} dmadd_t;
7837 +
7838 +/*
7839 + * Each descriptor ring must be 4096byte aligned
7840 + * and fit within a single 4096byte page.
7841 + */
7842 +#define DMAMAXRINGSZ 4096
7843 +#define DMARINGALIGN 4096
7844 +
7845 +/* control flags */
7846 +#define CTRL_BC_MASK 0x1fff /* buffer byte count */
7847 +#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
7848 +#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
7849 +#define CTRL_EOF ((uint32)1 << 30) /* end of frame */
7850 +#define CTRL_SOF ((uint32)1 << 31) /* start of frame */
7851 +
7852 +/* control flags in the range [27:20] are core-specific and not defined here */
7853 +#define CTRL_CORE_MASK 0x0ff00000
7854 +
7855 +/* export structure */
7856 +typedef volatile struct {
7857 + /* rx error counters */
7858 + uint rxgiants; /* rx giant frames */
7859 + uint rxnobuf; /* rx out of dma descriptors */
7860 + /* tx error counters */
7861 + uint txnobuf; /* tx out of dma descriptors */
7862 +} hnddma_t;
7863 +
7864 +#ifndef di_t
7865 +#define di_t void
7866 +#endif
7867 +
7868 +/* externs */
7869 +extern void *dma_attach(void *drv, void *dev, char *name, dmaregs_t *dmaregs,
7870 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset,
7871 + uint ddoffset, uint dataoffset, uint *msg_level);
7872 +extern void dma_detach(di_t *di);
7873 +extern void dma_txreset(di_t *di);
7874 +extern void dma_rxreset(di_t *di);
7875 +extern void dma_txinit(di_t *di);
7876 +extern bool dma_txenabled(di_t *di);
7877 +extern void dma_rxinit(di_t *di);
7878 +extern void dma_rxenable(di_t *di);
7879 +extern bool dma_rxenabled(di_t *di);
7880 +extern void dma_txsuspend(di_t *di);
7881 +extern void dma_txresume(di_t *di);
7882 +extern bool dma_txsuspended(di_t *di);
7883 +extern bool dma_txstopped(di_t *di);
7884 +extern bool dma_rxstopped(di_t *di);
7885 +extern int dma_txfast(di_t *di, void *p, uint32 coreflags);
7886 +extern int dma_tx(di_t *di, void *p, uint32 coreflags);
7887 +extern void dma_fifoloopbackenable(di_t *di);
7888 +extern void *dma_rx(di_t *di);
7889 +extern void dma_rxfill(di_t *di);
7890 +extern void dma_txreclaim(di_t *di, bool forceall);
7891 +extern void dma_rxreclaim(di_t *di);
7892 +extern char *dma_dump(di_t *di, char *buf);
7893 +extern char *dma_dumptx(di_t *di, char *buf);
7894 +extern char *dma_dumprx(di_t *di, char *buf);
7895 +extern uint dma_getvar(di_t *di, char *name);
7896 +extern void *dma_getnexttxp(di_t *di, bool forceall);
7897 +extern void *dma_getnextrxp(di_t *di, bool forceall);
7898 +extern void dma_txblock(di_t *di);
7899 +extern void dma_txunblock(di_t *di);
7900 +extern uint dma_txactive(di_t *di);
7901 +
7902 +#endif /* _hnddma_h_ */
7903 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/hndmips.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/hndmips.h
7904 --- linux-2.6.12.5/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
7905 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/hndmips.h 2005-08-28 11:12:20.439857784 +0200
7906 @@ -0,0 +1,16 @@
7907 +/*
7908 + * Alternate include file for HND sbmips.h since CFE also ships with
7909 + * a sbmips.h.
7910 + *
7911 + * Copyright 2001-2003, Broadcom Corporation
7912 + * All Rights Reserved.
7913 + *
7914 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7915 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7916 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7917 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7918 + *
7919 + * $Id$
7920 + */
7921 +
7922 +#include "sbmips.h"
7923 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/linux_osl.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/linux_osl.h
7924 --- linux-2.6.12.5/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
7925 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/linux_osl.h 2005-08-28 11:12:20.440857632 +0200
7926 @@ -0,0 +1,313 @@
7927 +/*
7928 + * Linux OS Independent Layer
7929 + *
7930 + * Copyright 2001-2003, Broadcom Corporation
7931 + * All Rights Reserved.
7932 + *
7933 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7934 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7935 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7936 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7937 + *
7938 + * $Id$
7939 + */
7940 +
7941 +#ifndef _linux_osl_h_
7942 +#define _linux_osl_h_
7943 +
7944 +#include <typedefs.h>
7945 +
7946 +/* use current 2.4.x calling conventions */
7947 +#include <linuxver.h>
7948 +
7949 +/* assert and panic */
7950 +#define ASSERT(exp) do {} while (0)
7951 +
7952 +/* PCMCIA attribute space access macros */
7953 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
7954 + osl_pcmcia_read_attr((osh), (offset), (buf), (size))
7955 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
7956 + osl_pcmcia_write_attr((osh), (offset), (buf), (size))
7957 +extern void osl_pcmcia_read_attr(void *osh, uint offset, void *buf, int size);
7958 +extern void osl_pcmcia_write_attr(void *osh, uint offset, void *buf, int size);
7959 +
7960 +/* PCI configuration space access macros */
7961 +#define OSL_PCI_READ_CONFIG(loc, offset, size) \
7962 + osl_pci_read_config((loc), (offset), (size))
7963 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
7964 + osl_pci_write_config((loc), (offset), (size), (val))
7965 +extern uint32 osl_pci_read_config(void *loc, uint size, uint offset);
7966 +extern void osl_pci_write_config(void *loc, uint offset, uint size, uint val);
7967 +
7968 +/* OSL initialization */
7969 +#define osl_init() do {} while (0)
7970 +
7971 +/* host/bus architecture-specific byte swap */
7972 +#define BUS_SWAP32(v) (v)
7973 +
7974 +/*
7975 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
7976 + * Macros expand to calls to functions defined in linux_osl.c .
7977 + */
7978 +#ifndef BINOSL
7979 +
7980 +/* string library, kernel mode */
7981 +#define printf(fmt, args...) printk(fmt, ## args)
7982 +#include <linux/kernel.h>
7983 +#include <linux/string.h>
7984 +
7985 +/* register access macros */
7986 +#define R_REG(r) ({ \
7987 + __typeof(*(r)) __osl_v; \
7988 + switch (sizeof(*(r))) { \
7989 + case sizeof(uint8): __osl_v = readb((volatile uint8*)(r)); break; \
7990 + case sizeof(uint16): __osl_v = readw((volatile uint16*)(r)); break; \
7991 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
7992 + } \
7993 + __osl_v; \
7994 +})
7995 +#define W_REG(r, v) do { \
7996 + switch (sizeof(*(r))) { \
7997 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
7998 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
7999 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
8000 + } \
8001 +} while (0)
8002 +
8003 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
8004 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
8005 +
8006 +/* bcopy, bcmp, and bzero */
8007 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
8008 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
8009 +#define bzero(b, len) memset((b), '\0', (len))
8010 +
8011 +/* general purpose memory allocation */
8012 +#define MALLOC(size) kmalloc((size), GFP_ATOMIC)
8013 +#define MFREE(addr, size) kfree((addr))
8014 +
8015 +/* uncached virtual address */
8016 +#ifdef mips
8017 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
8018 +#include <asm/addrspace.h>
8019 +#else
8020 +#define OSL_UNCACHED(va) (va)
8021 +#endif
8022 +
8023 +/* get processor cycle count */
8024 +#if defined(mips)
8025 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
8026 +#elif defined(__i386__)
8027 +#define OSL_GETCYCLES(x) rdtscl((x))
8028 +#else
8029 +#define OSL_GETCYCLES(x) ((x) = 0)
8030 +#endif
8031 +
8032 +/* dereference an address that may cause a bus exception */
8033 +#ifdef mips
8034 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
8035 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
8036 +#else
8037 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
8038 +#include <asm/paccess.h>
8039 +#endif
8040 +#else
8041 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
8042 +#endif
8043 +
8044 +/* map/unmap physical to virtual I/O */
8045 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
8046 +#define REG_UNMAP(va) iounmap((void *)(va))
8047 +
8048 +/* allocate/free shared (dma-able) consistent (uncached) memory */
8049 +#define DMA_ALLOC_CONSISTENT(dev, size, pap) \
8050 + pci_alloc_consistent((dev), (size), (dma_addr_t*)(pap))
8051 +#define DMA_FREE_CONSISTENT(dev, va, size, pa) \
8052 + pci_free_consistent((dev), (size), (va), (dma_addr_t)(pa))
8053 +
8054 +/* map/unmap direction */
8055 +#define DMA_TX PCI_DMA_TODEVICE
8056 +#define DMA_RX PCI_DMA_FROMDEVICE
8057 +
8058 +/* map/unmap shared (dma-able) memory */
8059 +#define DMA_MAP(dev, va, size, direction, p) \
8060 + pci_map_single((dev), (va), (size), (direction))
8061 +#define DMA_UNMAP(dev, pa, size, direction, p) \
8062 + pci_unmap_single((dev), (dma_addr_t)(pa), (size), (direction))
8063 +
8064 +/* microsecond delay */
8065 +#define OSL_DELAY(usec) udelay(usec)
8066 +#include <linux/delay.h>
8067 +#define OSL_SLEEP(usec) set_current_state(TASK_INTERRUPTIBLE); \
8068 + schedule_timeout((usec*HZ)/1000000);
8069 +#define OSL_IN_INTERRUPT() in_interrupt()
8070 +
8071 +/* shared (dma-able) memory access macros */
8072 +#define R_SM(r) *(r)
8073 +#define W_SM(r, v) (*(r) = (v))
8074 +#define BZERO_SM(r, len) memset((r), '\0', (len))
8075 +
8076 +/* packet primitives */
8077 +#define PKTGET(drv, len, send) osl_pktget((drv), (len), (send))
8078 +#define PKTFREE(drv, skb, send) osl_pktfree((skb))
8079 +#define PKTDATA(drv, skb) (((struct sk_buff*)(skb))->data)
8080 +#define PKTLEN(drv, skb) (((struct sk_buff*)(skb))->len)
8081 +#define PKTHEADROOM(drv, skb) (PKTDATA(drv,skb)-(((struct sk_buff*)(skb))->head))
8082 +#define PKTTAILROOM(drv, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
8083 +#define PKTNEXT(drv, skb) (((struct sk_buff*)(skb))->next)
8084 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
8085 +#define PKTSETLEN(drv, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
8086 +#define PKTPUSH(drv, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
8087 +#define PKTPULL(drv, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
8088 +#define PKTDUP(drv, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
8089 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
8090 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
8091 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
8092 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
8093 +extern void *osl_pktget(void *drv, uint len, bool send);
8094 +extern void osl_pktfree(void *skb);
8095 +
8096 +#else /* BINOSL */
8097 +
8098 +/* string library */
8099 +#ifndef LINUX_OSL
8100 +#undef printf
8101 +#define printf(fmt, args...) osl_printf((fmt), ## args)
8102 +#undef sprintf
8103 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
8104 +#undef strcmp
8105 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
8106 +#undef strncmp
8107 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
8108 +#undef strlen
8109 +#define strlen(s) osl_strlen((s))
8110 +#undef strcpy
8111 +#define strcpy(d, s) osl_strcpy((d), (s))
8112 +#undef strncpy
8113 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
8114 +#endif
8115 +extern int osl_printf(const char *format, ...);
8116 +extern int osl_sprintf(char *buf, const char *format, ...);
8117 +extern int osl_strcmp(const char *s1, const char *s2);
8118 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
8119 +extern int osl_strlen(char *s);
8120 +extern char* osl_strcpy(char *d, const char *s);
8121 +extern char* osl_strncpy(char *d, const char *s, uint n);
8122 +
8123 +/* register access macros */
8124 +#define R_REG(r) ({ \
8125 + __typeof(*(r)) __osl_v; \
8126 + switch (sizeof(*(r))) { \
8127 + case sizeof(uint8): __osl_v = osl_readb((volatile uint8*)(r)); break; \
8128 + case sizeof(uint16): __osl_v = osl_readw((volatile uint16*)(r)); break; \
8129 + case sizeof(uint32): __osl_v = osl_readl((volatile uint32*)(r)); break; \
8130 + } \
8131 + __osl_v; \
8132 +})
8133 +#define W_REG(r, v) do { \
8134 + switch (sizeof(*(r))) { \
8135 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
8136 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
8137 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
8138 + } \
8139 +} while (0)
8140 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
8141 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
8142 +extern uint8 osl_readb(volatile uint8 *r);
8143 +extern uint16 osl_readw(volatile uint16 *r);
8144 +extern uint32 osl_readl(volatile uint32 *r);
8145 +extern void osl_writeb(uint8 v, volatile uint8 *r);
8146 +extern void osl_writew(uint16 v, volatile uint16 *r);
8147 +extern void osl_writel(uint32 v, volatile uint32 *r);
8148 +
8149 +/* bcopy, bcmp, and bzero */
8150 +extern void bcopy(const void *src, void *dst, int len);
8151 +extern int bcmp(const void *b1, const void *b2, int len);
8152 +extern void bzero(void *b, int len);
8153 +
8154 +/* general purpose memory allocation */
8155 +#define MALLOC(size) osl_malloc((size))
8156 +#define MFREE(addr, size) osl_mfree((char*)(addr), (size))
8157 +extern void *osl_malloc(uint size);
8158 +extern void osl_mfree(void *addr, uint size);
8159 +
8160 +/* uncached virtual address */
8161 +#define OSL_UNCACHED(va) osl_uncached((va))
8162 +extern void *osl_uncached(void *va);
8163 +
8164 +/* get processor cycle count */
8165 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
8166 +extern uint osl_getcycles(void);
8167 +
8168 +/* dereference an address that may target abort */
8169 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
8170 +extern int osl_busprobe(uint32 *val, uint32 addr);
8171 +
8172 +/* map/unmap physical to virtual */
8173 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
8174 +#define REG_UNMAP(va) osl_reg_unmap((va))
8175 +extern void *osl_reg_map(uint32 pa, uint size);
8176 +extern void osl_reg_unmap(void *va);
8177 +
8178 +/* allocate/free shared (dma-able) consistent (uncached) memory */
8179 +#define DMA_ALLOC_CONSISTENT(dev, size, pap) \
8180 + osl_dma_alloc_consistent((dev), (size), (pap))
8181 +#define DMA_FREE_CONSISTENT(dev, va, size, pa) \
8182 + osl_dma_free_consistent((dev), (void*)(va), (size), (pa))
8183 +extern void *osl_dma_alloc_consistent(void *dev, uint size, ulong *pap);
8184 +extern void osl_dma_free_consistent(void *dev, void *va, uint size, ulong pa);
8185 +
8186 +/* map/unmap direction */
8187 +#define DMA_TX 1
8188 +#define DMA_RX 2
8189 +
8190 +/* map/unmap shared (dma-able) memory */
8191 +#define DMA_MAP(dev, va, size, direction, p) \
8192 + osl_dma_map((dev), (va), (size), (direction))
8193 +#define DMA_UNMAP(dev, pa, size, direction, p) \
8194 + osl_dma_unmap((dev), (pa), (size), (direction))
8195 +extern uint osl_dma_map(void *dev, void *va, uint size, int direction);
8196 +extern void osl_dma_unmap(void *dev, uint pa, uint size, int direction);
8197 +
8198 +/* microsecond delay */
8199 +#define OSL_DELAY(usec) osl_delay((usec))
8200 +extern void osl_delay(uint usec);
8201 +
8202 +/* shared (dma-able) memory access macros */
8203 +#define R_SM(r) *(r)
8204 +#define W_SM(r, v) (*(r) = (v))
8205 +#define BZERO_SM(r, len) bzero((r), (len))
8206 +
8207 +/* packet primitives */
8208 +#define PKTGET(drv, len, send) osl_pktget((drv), (len), (send))
8209 +#define PKTFREE(drv, skb, send) osl_pktfree((skb))
8210 +#define PKTDATA(drv, skb) osl_pktdata((drv), (skb))
8211 +#define PKTLEN(drv, skb) osl_pktlen((drv), (skb))
8212 +#define PKTNEXT(drv, skb) osl_pktnext((drv), (skb))
8213 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
8214 +#define PKTSETLEN(drv, skb, len) osl_pktsetlen((drv), (skb), (len))
8215 +#define PKTPUSH(drv, skb, bytes) osl_pktpush((drv), (skb), (bytes))
8216 +#define PKTPULL(drv, skb, bytes) osl_pktpull((drv), (skb), (bytes))
8217 +#define PKTDUP(drv, skb) osl_pktdup((drv), (skb))
8218 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
8219 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
8220 +#define PKTLINK(skb) osl_pktlink((skb))
8221 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
8222 +extern void *osl_pktget(void *drv, uint len, bool send);
8223 +extern void osl_pktfree(void *skb);
8224 +extern uchar *osl_pktdata(void *drv, void *skb);
8225 +extern uint osl_pktlen(void *drv, void *skb);
8226 +extern void *osl_pktnext(void *drv, void *skb);
8227 +extern void osl_pktsetnext(void *skb, void *x);
8228 +extern void osl_pktsetlen(void *drv, void *skb, uint len);
8229 +extern uchar *osl_pktpush(void *drv, void *skb, int bytes);
8230 +extern uchar *osl_pktpull(void *drv, void *skb, int bytes);
8231 +extern void *osl_pktdup(void *drv, void *skb);
8232 +extern void *osl_pktcookie(void *skb);
8233 +extern void osl_pktsetcookie(void *skb, void *x);
8234 +extern void *osl_pktlink(void *skb);
8235 +extern void osl_pktsetlink(void *skb, void *x);
8236 +
8237 +#endif /* BINOSL */
8238 +
8239 +#endif /* _linux_osl_h_ */
8240 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/linuxver.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/linuxver.h
8241 --- linux-2.6.12.5/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
8242 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/linuxver.h 2005-08-28 11:12:20.441857480 +0200
8243 @@ -0,0 +1,326 @@
8244 +/*
8245 + * Linux-specific abstractions to gain some independence from linux kernel versions.
8246 + * Pave over some 2.2 versus 2.4 kernel differences.
8247 + *
8248 + * Copyright 2001-2003, Broadcom Corporation
8249 + * All Rights Reserved.
8250 + *
8251 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8252 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8253 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8254 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8255 + * $Id$
8256 + */
8257 +
8258 +#ifndef _linuxver_h_
8259 +#define _linuxver_h_
8260 +
8261 +#include <linux/config.h>
8262 +#include <linux/version.h>
8263 +
8264 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
8265 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
8266 +#ifdef __UNDEF_NO_VERSION__
8267 +#undef __NO_VERSION__
8268 +#else
8269 +#define __NO_VERSION__
8270 +#endif
8271 +#endif
8272 +
8273 +#if defined(MODULE) && defined(MODVERSIONS)
8274 +#include <linux/modversions.h>
8275 +#endif
8276 +
8277 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
8278 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
8279 +#include <linux/malloc.h>
8280 +#else
8281 +#include <linux/slab.h>
8282 +#endif
8283 +
8284 +#include <linux/types.h>
8285 +#include <linux/init.h>
8286 +#include <linux/module.h>
8287 +#include <linux/mm.h>
8288 +#include <linux/string.h>
8289 +#include <linux/pci.h>
8290 +#include <linux/interrupt.h>
8291 +#include <linux/netdevice.h>
8292 +#include <asm/io.h>
8293 +
8294 +#ifndef __exit
8295 +#define __exit
8296 +#endif
8297 +#ifndef __devexit
8298 +#define __devexit
8299 +#endif
8300 +#ifndef __devinit
8301 +#define __devinit __init
8302 +#endif
8303 +#ifndef __devinitdata
8304 +#define __devinitdata
8305 +#endif
8306 +#ifndef __devexit_p
8307 +#define __devexit_p(x) x
8308 +#endif
8309 +
8310 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
8311 +
8312 +#define pci_get_drvdata(dev) (dev)->sysdata
8313 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
8314 +
8315 +/*
8316 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
8317 + */
8318 +
8319 +struct pci_device_id {
8320 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
8321 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
8322 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
8323 + unsigned long driver_data; /* Data private to the driver */
8324 +};
8325 +
8326 +struct pci_driver {
8327 + struct list_head node;
8328 + char *name;
8329 + const struct pci_device_id *id_table; /* NULL if wants all devices */
8330 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
8331 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
8332 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
8333 + void (*resume)(struct pci_dev *dev); /* Device woken up */
8334 +};
8335 +
8336 +#define MODULE_DEVICE_TABLE(type, name)
8337 +#define PCI_ANY_ID (~0)
8338 +
8339 +/* compatpci.c */
8340 +#define pci_module_init pci_register_driver
8341 +extern int pci_register_driver(struct pci_driver *drv);
8342 +extern void pci_unregister_driver(struct pci_driver *drv);
8343 +
8344 +#endif /* PCI registration */
8345 +
8346 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
8347 +#ifdef MODULE
8348 +#define module_init(x) int init_module(void) { return x(); }
8349 +#define module_exit(x) void cleanup_module(void) { x(); }
8350 +#else
8351 +#define module_init(x) __initcall(x);
8352 +#define module_exit(x) __exitcall(x);
8353 +#endif
8354 +#endif
8355 +
8356 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
8357 +#define list_for_each(pos, head) \
8358 + for (pos = (head)->next; pos != (head); pos = pos->next)
8359 +#endif
8360 +
8361 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
8362 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
8363 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
8364 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
8365 +#endif
8366 +
8367 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
8368 +#define pci_enable_device(dev) do { } while (0)
8369 +#endif
8370 +
8371 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
8372 +#define net_device device
8373 +#endif
8374 +
8375 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
8376 +
8377 +/*
8378 + * DMA mapping
8379 + *
8380 + * See linux/Documentation/DMA-mapping.txt
8381 + */
8382 +
8383 +#ifndef PCI_DMA_TODEVICE
8384 +#define PCI_DMA_TODEVICE 1
8385 +#define PCI_DMA_FROMDEVICE 2
8386 +#endif
8387 +
8388 +typedef u32 dma_addr_t;
8389 +
8390 +/* Pure 2^n version of get_order */
8391 +static inline int get_order(unsigned long size)
8392 +{
8393 + int order;
8394 +
8395 + size = (size-1) >> (PAGE_SHIFT-1);
8396 + order = -1;
8397 + do {
8398 + size >>= 1;
8399 + order++;
8400 + } while (size);
8401 + return order;
8402 +}
8403 +
8404 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
8405 + dma_addr_t *dma_handle)
8406 +{
8407 + void *ret;
8408 + int gfp = GFP_ATOMIC | GFP_DMA;
8409 +
8410 + ret = (void *)__get_free_pages(gfp, get_order(size));
8411 +
8412 + if (ret != NULL) {
8413 + memset(ret, 0, size);
8414 + *dma_handle = virt_to_bus(ret);
8415 + }
8416 + return ret;
8417 +}
8418 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
8419 + void *vaddr, dma_addr_t dma_handle)
8420 +{
8421 + free_pages((unsigned long)vaddr, get_order(size));
8422 +}
8423 +#ifdef ILSIM
8424 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
8425 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
8426 +#else
8427 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
8428 +#define pci_unmap_single(cookie, address, size, dir)
8429 +#endif
8430 +
8431 +#endif /* DMA mapping */
8432 +
8433 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
8434 +
8435 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
8436 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
8437 +
8438 +/* pcmcia-cs provides its own netdevice compatibility layer */
8439 +#ifndef _COMPAT_NETDEVICE_H
8440 +
8441 +/*
8442 + * SoftNet
8443 + *
8444 + * For pre-softnet kernels we need to tell the upper layer not to
8445 + * re-enter start_xmit() while we are in there. However softnet
8446 + * guarantees not to enter while we are in there so there is no need
8447 + * to do the netif_stop_queue() dance unless the transmit queue really
8448 + * gets stuck. This should also improve performance according to tests
8449 + * done by Aman Singla.
8450 + */
8451 +
8452 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
8453 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
8454 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
8455 +
8456 +static inline void netif_start_queue(struct net_device *dev)
8457 +{
8458 + dev->tbusy = 0;
8459 + dev->interrupt = 0;
8460 + dev->start = 1;
8461 +}
8462 +
8463 +#define netif_queue_stopped(dev) (dev)->tbusy
8464 +#define netif_running(dev) (dev)->start
8465 +
8466 +#endif /* _COMPAT_NETDEVICE_H */
8467 +
8468 +#define netif_device_attach(dev) netif_start_queue(dev)
8469 +#define netif_device_detach(dev) netif_stop_queue(dev)
8470 +
8471 +/* 2.4.x renamed bottom halves to tasklets */
8472 +#define tasklet_struct tq_struct
8473 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
8474 +{
8475 + queue_task(tasklet, &tq_immediate);
8476 + mark_bh(IMMEDIATE_BH);
8477 +}
8478 +
8479 +static inline void tasklet_init(struct tasklet_struct *tasklet,
8480 + void (*func)(unsigned long),
8481 + unsigned long data)
8482 +{
8483 + tasklet->next = NULL;
8484 + tasklet->sync = 0;
8485 + tasklet->routine = (void (*)(void *))func;
8486 + tasklet->data = (void *)data;
8487 +}
8488 +#define tasklet_kill(tasklet) {do{} while(0);}
8489 +
8490 +/* 2.4.x introduced del_timer_sync() */
8491 +#define del_timer_sync(timer) del_timer(timer)
8492 +
8493 +#else
8494 +
8495 +#define netif_down(dev)
8496 +
8497 +#endif /* SoftNet */
8498 +
8499 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
8500 +
8501 +/*
8502 + * Emit code to initialise a tq_struct's routine and data pointers
8503 + */
8504 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
8505 + do { \
8506 + (_tq)->routine = _routine; \
8507 + (_tq)->data = _data; \
8508 + } while (0)
8509 +
8510 +/*
8511 + * Emit code to initialise all of a tq_struct
8512 + */
8513 +#define INIT_TQUEUE(_tq, _routine, _data) \
8514 + do { \
8515 + INIT_LIST_HEAD(&(_tq)->list); \
8516 + (_tq)->sync = 0; \
8517 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
8518 + } while (0)
8519 +
8520 +#endif
8521 +
8522 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
8523 +
8524 +/* Power management related routines */
8525 +
8526 +static inline int
8527 +pci_save_state(struct pci_dev *dev, u32 *buffer)
8528 +{
8529 + int i;
8530 + if (buffer) {
8531 + for (i = 0; i < 16; i++)
8532 + pci_read_config_dword(dev, i * 4,&buffer[i]);
8533 + }
8534 + return 0;
8535 +}
8536 +
8537 +static inline int
8538 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
8539 +{
8540 + int i;
8541 +
8542 + if (buffer) {
8543 + for (i = 0; i < 16; i++)
8544 + pci_write_config_dword(dev,i * 4, buffer[i]);
8545 + }
8546 + /*
8547 + * otherwise, write the context information we know from bootup.
8548 + * This works around a problem where warm-booting from Windows
8549 + * combined with a D3(hot)->D0 transition causes PCI config
8550 + * header data to be forgotten.
8551 + */
8552 + else {
8553 + for (i = 0; i < 6; i ++)
8554 + pci_write_config_dword(dev,
8555 + PCI_BASE_ADDRESS_0 + (i * 4),
8556 + pci_resource_start(dev, i));
8557 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
8558 + }
8559 + return 0;
8560 +}
8561 +
8562 +#endif /* PCI power management */
8563 +
8564 +/* Old cp0 access macros deprecated in 2.4.19 */
8565 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
8566 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
8567 +#endif
8568 +
8569 +#endif /* _linuxver_h_ */
8570 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/nvports.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/nvports.h
8571 --- linux-2.6.12.5/arch/mips/bcm947xx/include/nvports.h 1970-01-01 01:00:00.000000000 +0100
8572 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/nvports.h 2005-08-28 11:12:20.441857480 +0200
8573 @@ -0,0 +1,62 @@
8574 +/*
8575 + * Broadcom Home Gateway Reference Design
8576 + * Ports Web Page Configuration Support Routines
8577 + *
8578 + * Copyright 2001-2003, Broadcom Corporation
8579 + * All Rights Reserved.
8580 + *
8581 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8582 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8583 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8584 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8585 + * $Id$
8586 + */
8587 +
8588 +#ifndef _nvports_h_
8589 +#define _nvports_h_
8590 +
8591 +#define uint32 unsigned long
8592 +#define uint16 unsigned short
8593 +#define uint unsigned int
8594 +#define uint8 unsigned char
8595 +#define uint64 unsigned long long
8596 +
8597 +enum FORCE_PORT {
8598 + FORCE_OFF,
8599 + FORCE_10H,
8600 + FORCE_10F,
8601 + FORCE_100H,
8602 + FORCE_100F,
8603 + FORCE_DOWN,
8604 + POWER_OFF
8605 +};
8606 +
8607 +typedef struct _PORT_ATTRIBS
8608 +{
8609 + uint autoneg;
8610 + uint force;
8611 + uint native;
8612 +} PORT_ATTRIBS;
8613 +
8614 +extern uint
8615 +nvExistsPortAttrib(char *attrib, uint portno);
8616 +
8617 +extern int
8618 +nvExistsAnyForcePortAttrib(uint portno);
8619 +
8620 +extern void
8621 +nvSetPortAttrib(char *attrib, uint portno);
8622 +
8623 +extern void
8624 +nvUnsetPortAttrib(char *attrib, uint portno);
8625 +
8626 +extern void
8627 +nvUnsetAllForcePortAttrib(uint portno);
8628 +
8629 +extern PORT_ATTRIBS
8630 +nvGetSwitchPortAttribs(uint portno);
8631 +
8632 +#endif /* _nvports_h_ */
8633 +
8634 +
8635 +
8636 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/osl.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/osl.h
8637 --- linux-2.6.12.5/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
8638 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/osl.h 2005-08-28 11:12:20.441857480 +0200
8639 @@ -0,0 +1,38 @@
8640 +/*
8641 + * OS Independent Layer
8642 + *
8643 + * Copyright 2001-2003, Broadcom Corporation
8644 + * All Rights Reserved.
8645 + *
8646 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8647 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8648 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8649 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8650 + * $Id$
8651 + */
8652 +
8653 +#ifndef _osl_h_
8654 +#define _osl_h_
8655 +
8656 +#ifdef V2_HAL
8657 +#include <v2hal_osl.h>
8658 +#elif defined(linux)
8659 +#include <linux_osl.h>
8660 +#elif PMON
8661 +#include <pmon_osl.h>
8662 +#elif defined(NDIS)
8663 +#include <ndis_osl.h>
8664 +#elif defined(_CFE_)
8665 +#include <cfe_osl.h>
8666 +#elif defined(MACOS9)
8667 +#include <macos9_osl.h>
8668 +#elif defined(MACOSX)
8669 +#include <macosx_osl.h>
8670 +#else
8671 +#error "Unsupported OSL requested"
8672 +#endif
8673 +
8674 +/* handy */
8675 +#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
8676 +
8677 +#endif /* _osl_h_ */
8678 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/pcicfg.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/pcicfg.h
8679 --- linux-2.6.12.5/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
8680 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/pcicfg.h 2005-08-28 11:12:20.442857328 +0200
8681 @@ -0,0 +1,362 @@
8682 +/*
8683 + * pcicfg.h: PCI configuration constants and structures.
8684 + *
8685 + * Copyright 2001-2003, Broadcom Corporation
8686 + * All Rights Reserved.
8687 + *
8688 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8689 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8690 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8691 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8692 + *
8693 + * $Id$
8694 + */
8695 +
8696 +#ifndef _h_pci_
8697 +#define _h_pci_
8698 +
8699 +/* The following inside ifndef's so we don't collide with NTDDK.H */
8700 +#ifndef PCI_MAX_BUS
8701 +#define PCI_MAX_BUS 0x100
8702 +#endif
8703 +#ifndef PCI_MAX_DEVICES
8704 +#define PCI_MAX_DEVICES 0x20
8705 +#endif
8706 +#ifndef PCI_MAX_FUNCTION
8707 +#define PCI_MAX_FUNCTION 0x8
8708 +#endif
8709 +
8710 +#ifndef PCI_INVALID_VENDORID
8711 +#define PCI_INVALID_VENDORID 0xffff
8712 +#endif
8713 +#ifndef PCI_INVALID_DEVICEID
8714 +#define PCI_INVALID_DEVICEID 0xffff
8715 +#endif
8716 +
8717 +
8718 +/* Convert between bus-slot-function-register and config addresses */
8719 +
8720 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
8721 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
8722 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
8723 +#define PCICFG_OFF_SHIFT 0 /* Bus shift */
8724 +
8725 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
8726 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
8727 +#define PCICFG_FUN_MASK 7 /* Function mask */
8728 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
8729 +
8730 +#define PCI_CONFIG_ADDR(b, s, f, o) \
8731 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
8732 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
8733 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
8734 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
8735 +
8736 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
8737 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
8738 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
8739 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
8740 +
8741 +
8742 +/* The actual config space */
8743 +
8744 +#define PCI_BAR_MAX 6
8745 +
8746 +#define PCI_ROM_BAR 8
8747 +
8748 +#define PCR_RSVDA_MAX 2
8749 +
8750 +typedef struct _pci_config_regs {
8751 + unsigned short vendor;
8752 + unsigned short device;
8753 + unsigned short command;
8754 + unsigned short status;
8755 + unsigned char rev_id;
8756 + unsigned char prog_if;
8757 + unsigned char sub_class;
8758 + unsigned char base_class;
8759 + unsigned char cache_line_size;
8760 + unsigned char latency_timer;
8761 + unsigned char header_type;
8762 + unsigned char bist;
8763 + unsigned long base[PCI_BAR_MAX];
8764 + unsigned long cardbus_cis;
8765 + unsigned short subsys_vendor;
8766 + unsigned short subsys_id;
8767 + unsigned long baserom;
8768 + unsigned long rsvd_a[PCR_RSVDA_MAX];
8769 + unsigned char int_line;
8770 + unsigned char int_pin;
8771 + unsigned char min_gnt;
8772 + unsigned char max_lat;
8773 + unsigned char dev_dep[192];
8774 +} pci_config_regs;
8775 +
8776 +#define SZPCR (sizeof (pci_config_regs))
8777 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
8778 +
8779 +/* A structure for the config registers is nice, but in most
8780 + * systems the config space is not memory mapped, so we need
8781 + * filed offsetts. :-(
8782 + */
8783 +#define PCI_CFG_VID 0
8784 +#define PCI_CFG_DID 2
8785 +#define PCI_CFG_CMD 4
8786 +#define PCI_CFG_STAT 6
8787 +#define PCI_CFG_REV 8
8788 +#define PCI_CFG_PROGIF 9
8789 +#define PCI_CFG_SUBCL 0xa
8790 +#define PCI_CFG_BASECL 0xb
8791 +#define PCI_CFG_CLSZ 0xc
8792 +#define PCI_CFG_LATTIM 0xd
8793 +#define PCI_CFG_HDR 0xe
8794 +#define PCI_CFG_BIST 0xf
8795 +#define PCI_CFG_BAR0 0x10
8796 +#define PCI_CFG_BAR1 0x14
8797 +#define PCI_CFG_BAR2 0x18
8798 +#define PCI_CFG_BAR3 0x1c
8799 +#define PCI_CFG_BAR4 0x20
8800 +#define PCI_CFG_BAR5 0x24
8801 +#define PCI_CFG_CIS 0x28
8802 +#define PCI_CFG_SVID 0x2c
8803 +#define PCI_CFG_SSID 0x2e
8804 +#define PCI_CFG_ROMBAR 0x30
8805 +#define PCI_CFG_INT 0x3c
8806 +#define PCI_CFG_PIN 0x3d
8807 +#define PCI_CFG_MINGNT 0x3e
8808 +#define PCI_CFG_MAXLAT 0x3f
8809 +
8810 +/* Classes and subclasses */
8811 +
8812 +typedef enum {
8813 + PCI_CLASS_OLD = 0,
8814 + PCI_CLASS_DASDI,
8815 + PCI_CLASS_NET,
8816 + PCI_CLASS_DISPLAY,
8817 + PCI_CLASS_MMEDIA,
8818 + PCI_CLASS_MEMORY,
8819 + PCI_CLASS_BRIDGE,
8820 + PCI_CLASS_COMM,
8821 + PCI_CLASS_BASE,
8822 + PCI_CLASS_INPUT,
8823 + PCI_CLASS_DOCK,
8824 + PCI_CLASS_CPU,
8825 + PCI_CLASS_SERIAL,
8826 + PCI_CLASS_INTELLIGENT = 0xe,
8827 + PCI_CLASS_SATELLITE,
8828 + PCI_CLASS_CRYPT,
8829 + PCI_CLASS_DSP,
8830 + PCI_CLASS_MAX
8831 +} pci_classes;
8832 +
8833 +typedef enum {
8834 + PCI_DASDI_SCSI,
8835 + PCI_DASDI_IDE,
8836 + PCI_DASDI_FLOPPY,
8837 + PCI_DASDI_IPI,
8838 + PCI_DASDI_RAID,
8839 + PCI_DASDI_OTHER = 0x80
8840 +} pci_dasdi_subclasses;
8841 +
8842 +typedef enum {
8843 + PCI_NET_ETHER,
8844 + PCI_NET_TOKEN,
8845 + PCI_NET_FDDI,
8846 + PCI_NET_ATM,
8847 + PCI_NET_OTHER = 0x80
8848 +} pci_net_subclasses;
8849 +
8850 +typedef enum {
8851 + PCI_DISPLAY_VGA,
8852 + PCI_DISPLAY_XGA,
8853 + PCI_DISPLAY_3D,
8854 + PCI_DISPLAY_OTHER = 0x80
8855 +} pci_display_subclasses;
8856 +
8857 +typedef enum {
8858 + PCI_MMEDIA_VIDEO,
8859 + PCI_MMEDIA_AUDIO,
8860 + PCI_MMEDIA_PHONE,
8861 + PCI_MEDIA_OTHER = 0x80
8862 +} pci_mmedia_subclasses;
8863 +
8864 +typedef enum {
8865 + PCI_MEMORY_RAM,
8866 + PCI_MEMORY_FLASH,
8867 + PCI_MEMORY_OTHER = 0x80
8868 +} pci_memory_subclasses;
8869 +
8870 +typedef enum {
8871 + PCI_BRIDGE_HOST,
8872 + PCI_BRIDGE_ISA,
8873 + PCI_BRIDGE_EISA,
8874 + PCI_BRIDGE_MC,
8875 + PCI_BRIDGE_PCI,
8876 + PCI_BRIDGE_PCMCIA,
8877 + PCI_BRIDGE_NUBUS,
8878 + PCI_BRIDGE_CARDBUS,
8879 + PCI_BRIDGE_RACEWAY,
8880 + PCI_BRIDGE_OTHER = 0x80
8881 +} pci_bridge_subclasses;
8882 +
8883 +typedef enum {
8884 + PCI_COMM_UART,
8885 + PCI_COMM_PARALLEL,
8886 + PCI_COMM_MULTIUART,
8887 + PCI_COMM_MODEM,
8888 + PCI_COMM_OTHER = 0x80
8889 +} pci_comm_subclasses;
8890 +
8891 +typedef enum {
8892 + PCI_BASE_PIC,
8893 + PCI_BASE_DMA,
8894 + PCI_BASE_TIMER,
8895 + PCI_BASE_RTC,
8896 + PCI_BASE_PCI_HOTPLUG,
8897 + PCI_BASE_OTHER = 0x80
8898 +} pci_base_subclasses;
8899 +
8900 +typedef enum {
8901 + PCI_INPUT_KBD,
8902 + PCI_INPUT_PEN,
8903 + PCI_INPUT_MOUSE,
8904 + PCI_INPUT_SCANNER,
8905 + PCI_INPUT_GAMEPORT,
8906 + PCI_INPUT_OTHER = 0x80
8907 +} pci_input_subclasses;
8908 +
8909 +typedef enum {
8910 + PCI_DOCK_GENERIC,
8911 + PCI_DOCK_OTHER = 0x80
8912 +} pci_dock_subclasses;
8913 +
8914 +typedef enum {
8915 + PCI_CPU_386,
8916 + PCI_CPU_486,
8917 + PCI_CPU_PENTIUM,
8918 + PCI_CPU_ALPHA = 0x10,
8919 + PCI_CPU_POWERPC = 0x20,
8920 + PCI_CPU_MIPS = 0x30,
8921 + PCI_CPU_COPROC = 0x40,
8922 + PCI_CPU_OTHER = 0x80
8923 +} pci_cpu_subclasses;
8924 +
8925 +typedef enum {
8926 + PCI_SERIAL_IEEE1394,
8927 + PCI_SERIAL_ACCESS,
8928 + PCI_SERIAL_SSA,
8929 + PCI_SERIAL_USB,
8930 + PCI_SERIAL_FIBER,
8931 + PCI_SERIAL_SMBUS,
8932 + PCI_SERIAL_OTHER = 0x80
8933 +} pci_serial_subclasses;
8934 +
8935 +typedef enum {
8936 + PCI_INTELLIGENT_I2O,
8937 +} pci_intelligent_subclasses;
8938 +
8939 +typedef enum {
8940 + PCI_SATELLITE_TV,
8941 + PCI_SATELLITE_AUDIO,
8942 + PCI_SATELLITE_VOICE,
8943 + PCI_SATELLITE_DATA,
8944 + PCI_SATELLITE_OTHER = 0x80
8945 +} pci_satellite_subclasses;
8946 +
8947 +typedef enum {
8948 + PCI_CRYPT_NETWORK,
8949 + PCI_CRYPT_ENTERTAINMENT,
8950 + PCI_CRYPT_OTHER = 0x80
8951 +} pci_crypt_subclasses;
8952 +
8953 +typedef enum {
8954 + PCI_DSP_DPIO,
8955 + PCI_DSP_OTHER = 0x80
8956 +} pci_dsp_subclasses;
8957 +
8958 +/* Header types */
8959 +typedef enum {
8960 + PCI_HEADER_NORMAL,
8961 + PCI_HEADER_BRIDGE,
8962 + PCI_HEADER_CARDBUS
8963 +} pci_header_types;
8964 +
8965 +
8966 +/* Overlay for a PCI-to-PCI bridge */
8967 +
8968 +#define PPB_RSVDA_MAX 2
8969 +#define PPB_RSVDD_MAX 8
8970 +
8971 +typedef struct _ppb_config_regs {
8972 + unsigned short vendor;
8973 + unsigned short device;
8974 + unsigned short command;
8975 + unsigned short status;
8976 + unsigned char rev_id;
8977 + unsigned char prog_if;
8978 + unsigned char sub_class;
8979 + unsigned char base_class;
8980 + unsigned char cache_line_size;
8981 + unsigned char latency_timer;
8982 + unsigned char header_type;
8983 + unsigned char bist;
8984 + unsigned long rsvd_a[PPB_RSVDA_MAX];
8985 + unsigned char prim_bus;
8986 + unsigned char sec_bus;
8987 + unsigned char sub_bus;
8988 + unsigned char sec_lat;
8989 + unsigned char io_base;
8990 + unsigned char io_lim;
8991 + unsigned short sec_status;
8992 + unsigned short mem_base;
8993 + unsigned short mem_lim;
8994 + unsigned short pf_mem_base;
8995 + unsigned short pf_mem_lim;
8996 + unsigned long pf_mem_base_hi;
8997 + unsigned long pf_mem_lim_hi;
8998 + unsigned short io_base_hi;
8999 + unsigned short io_lim_hi;
9000 + unsigned short subsys_vendor;
9001 + unsigned short subsys_id;
9002 + unsigned long rsvd_b;
9003 + unsigned char rsvd_c;
9004 + unsigned char int_pin;
9005 + unsigned short bridge_ctrl;
9006 + unsigned char chip_ctrl;
9007 + unsigned char diag_ctrl;
9008 + unsigned short arb_ctrl;
9009 + unsigned long rsvd_d[PPB_RSVDD_MAX];
9010 + unsigned char dev_dep[192];
9011 +} ppb_config_regs;
9012 +
9013 +/* Eveything below is BRCM HND proprietary */
9014 +
9015 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
9016 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
9017 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
9018 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
9019 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
9020 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
9021 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
9022 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
9023 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
9024 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
9025 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
9026 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
9027 +
9028 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
9029 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
9030 +
9031 +/* PCI_INT_MASK */
9032 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
9033 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
9034 +
9035 +/* PCI_SPROM_CONTROL */
9036 +#define SPROM_BLANK 0x04 /* indicating a blank sprom */
9037 +#define SPROM_WRITEEN 0x10 /* sprom write enable */
9038 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
9039 +
9040 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
9041 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
9042 +
9043 +#endif
9044 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/proto/802.11.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/proto/802.11.h
9045 --- linux-2.6.12.5/arch/mips/bcm947xx/include/proto/802.11.h 1970-01-01 01:00:00.000000000 +0100
9046 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/proto/802.11.h 2005-08-28 11:12:20.450856112 +0200
9047 @@ -0,0 +1,679 @@
9048 +/*
9049 + * Copyright 2001-2003, Broadcom Corporation
9050 + * All Rights Reserved.
9051 + *
9052 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9053 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9054 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9055 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9056 + *
9057 + * Fundamental types and constants relating to 802.11
9058 + *
9059 + * $Id$
9060 + */
9061 +
9062 +#ifndef _802_11_H_
9063 +#define _802_11_H_
9064 +
9065 +#ifndef _TYPEDEFS_H_
9066 +#include <typedefs.h>
9067 +#endif
9068 +
9069 +#ifndef _NET_ETHERNET_H_
9070 +#include <proto/ethernet.h>
9071 +#endif
9072 +
9073 +/* enable structure packing */
9074 +#if !defined(__GNUC__)
9075 +#pragma pack(1)
9076 +#endif
9077 +
9078 +/* some platforms require stronger medicine */
9079 +#if defined(__GNUC__)
9080 +#define PACKED __attribute__((packed))
9081 +#else
9082 +#define PACKED
9083 +#endif
9084 +
9085 +
9086 +#define DOT11_TU_TO_US 1024 /* 802.11 Time Unit is 1024 microseconds */
9087 +
9088 +/* Generic 802.11 frame constants */
9089 +#define DOT11_A3_HDR_LEN 24
9090 +#define DOT11_A4_HDR_LEN 30
9091 +#define DOT11_MAC_HDR_LEN DOT11_A3_HDR_LEN
9092 +#define DOT11_FCS_LEN 4
9093 +#define DOT11_ICV_LEN 4
9094 +#define DOT11_ICV_AES_LEN 8
9095 +
9096 +
9097 +#define DOT11_KEY_INDEX_SHIFT 6
9098 +#define DOT11_IV_LEN 4
9099 +#define DOT11_IV_TKIP_LEN 8
9100 +#define DOT11_IV_AES_OCB_LEN 4
9101 +#define DOT11_IV_AES_CCM_LEN 8
9102 +
9103 +#define DOT11_MAX_MPDU_BODY_LEN 2312
9104 +#define DOT11_MAX_MPDU_LEN 2346 /* body len + A4 hdr + FCS */
9105 +#define DOT11_MAX_SSID_LEN 32
9106 +
9107 +/* dot11RTSThreshold */
9108 +#define DOT11_DEFAULT_RTS_LEN 2347
9109 +#define DOT11_MAX_RTS_LEN 2347
9110 +
9111 +/* dot11FragmentationThreshold */
9112 +#define DOT11_MIN_FRAG_LEN 256
9113 +#define DOT11_MAX_FRAG_LEN 2346 /* Max frag is also limited by aMPDUMaxLength of the attached PHY */
9114 +#define DOT11_DEFAULT_FRAG_LEN 2346
9115 +
9116 +/* dot11BeaconPeriod */
9117 +#define DOT11_MIN_BEACON_PERIOD 1
9118 +#define DOT11_MAX_BEACON_PERIOD 0xFFFF
9119 +
9120 +/* dot11DTIMPeriod */
9121 +#define DOT11_MIN_DTIM_PERIOD 1
9122 +#define DOT11_MAX_DTIM_PERIOD 0xFF
9123 +
9124 +/* 802.2 LLC/SNAP header used by 802.11 per 802.1H */
9125 +#define DOT11_LLC_SNAP_HDR_LEN 8
9126 +#define DOT11_OUI_LEN 3
9127 +struct dot11_llc_snap_header {
9128 + uint8 dsap; /* always 0xAA */
9129 + uint8 ssap; /* always 0xAA */
9130 + uint8 ctl; /* always 0x03 */
9131 + uint8 oui[DOT11_OUI_LEN]; /* RFC1042: 0x00 0x00 0x00
9132 + Bridge-Tunnel: 0x00 0x00 0xF8 */
9133 + uint16 type; /* ethertype */
9134 +} PACKED;
9135 +
9136 +/* RFC1042 header used by 802.11 per 802.1H */
9137 +#define RFC1042_HDR_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN)
9138 +
9139 +/* Generic 802.11 MAC header */
9140 +/*
9141 + * N.B.: This struct reflects the full 4 address 802.11 MAC header.
9142 + * The fields are defined such that the shorter 1, 2, and 3
9143 + * address headers just use the first k fields.
9144 + */
9145 +struct dot11_header {
9146 + uint16 fc; /* frame control */
9147 + uint16 durid; /* duration/ID */
9148 + struct ether_addr a1; /* address 1 */
9149 + struct ether_addr a2; /* address 2 */
9150 + struct ether_addr a3; /* address 3 */
9151 + uint16 seq; /* sequence control */
9152 + struct ether_addr a4; /* address 4 */
9153 +} PACKED;
9154 +
9155 +/* Control frames */
9156 +
9157 +struct dot11_rts_frame {
9158 + uint16 fc; /* frame control */
9159 + uint16 durid; /* duration/ID */
9160 + struct ether_addr ra; /* receiver address */
9161 + struct ether_addr ta; /* transmitter address */
9162 +} PACKED;
9163 +#define DOT11_RTS_LEN 16
9164 +
9165 +struct dot11_cts_frame {
9166 + uint16 fc; /* frame control */
9167 + uint16 durid; /* duration/ID */
9168 + struct ether_addr ra; /* receiver address */
9169 +} PACKED;
9170 +#define DOT11_CTS_LEN 10
9171 +
9172 +struct dot11_ack_frame {
9173 + uint16 fc; /* frame control */
9174 + uint16 durid; /* duration/ID */
9175 + struct ether_addr ra; /* receiver address */
9176 +} PACKED;
9177 +#define DOT11_ACK_LEN 10
9178 +
9179 +struct dot11_ps_poll_frame {
9180 + uint16 fc; /* frame control */
9181 + uint16 durid; /* AID */
9182 + struct ether_addr bssid; /* receiver address, STA in AP */
9183 + struct ether_addr ta; /* transmitter address */
9184 +} PACKED;
9185 +#define DOT11_PS_POLL_LEN 16
9186 +
9187 +struct dot11_cf_end_frame {
9188 + uint16 fc; /* frame control */
9189 + uint16 durid; /* duration/ID */
9190 + struct ether_addr ra; /* receiver address */
9191 + struct ether_addr bssid; /* transmitter address, STA in AP */
9192 +} PACKED;
9193 +#define DOT11_CS_END_LEN 16
9194 +
9195 +/* Management frame header */
9196 +struct dot11_management_header {
9197 + uint16 fc; /* frame control */
9198 + uint16 durid; /* duration/ID */
9199 + struct ether_addr da; /* receiver address */
9200 + struct ether_addr sa; /* transmitter address */
9201 + struct ether_addr bssid; /* BSS ID */
9202 + uint16 seq; /* sequence control */
9203 +} PACKED;
9204 +#define DOT11_MGMT_HDR_LEN 24
9205 +
9206 +/* Management frame payloads */
9207 +
9208 +struct dot11_bcn_prb {
9209 + uint32 timestamp[2];
9210 + uint16 beacon_interval;
9211 + uint16 capability;
9212 +} PACKED;
9213 +#define DOT11_BCN_PRB_LEN 12
9214 +
9215 +struct dot11_auth {
9216 + uint16 alg; /* algorithm */
9217 + uint16 seq; /* sequence control */
9218 + uint16 status; /* status code */
9219 +} PACKED;
9220 +#define DOT11_AUTH_FIXED_LEN 6 /* length of auth frame without challenge info elt */
9221 +
9222 +struct dot11_assoc_req {
9223 + uint16 capability; /* capability information */
9224 + uint16 listen; /* listen interval */
9225 +} PACKED;
9226 +
9227 +struct dot11_assoc_resp {
9228 + uint16 capability; /* capability information */
9229 + uint16 status; /* status code */
9230 + uint16 aid; /* association ID */
9231 +} PACKED;
9232 +
9233 +struct dot11_action_measure {
9234 + uint8 category;
9235 + uint8 action;
9236 + uint8 token;
9237 + uint8 data[1];
9238 +} PACKED;
9239 +#define DOT11_ACTION_MEASURE_LEN 3
9240 +
9241 +/**************
9242 + 802.11h related definitions.
9243 +**************/
9244 +typedef struct {
9245 + uint8 id;
9246 + uint8 len;
9247 + uint8 power;
9248 +} dot11_power_cnst_t;
9249 +
9250 +typedef struct {
9251 + uint8 min;
9252 + uint8 max;
9253 +} dot11_power_cap_t;
9254 +
9255 +typedef struct {
9256 + uint8 id;
9257 + uint8 len;
9258 + uint8 tx_pwr;
9259 + uint8 margin;
9260 +} dot11_tpc_rep_t;
9261 +#define DOT11_MNG_IE_TPC_REPORT_LEN 2 /* length of IE data, not including 2 byte header */
9262 +
9263 +typedef struct {
9264 + uint8 id;
9265 + uint8 len;
9266 + uint8 first_channel;
9267 + uint8 num_channels;
9268 +} dot11_supp_channels_t;
9269 +
9270 +struct dot11_channel_switch {
9271 + uint8 id;
9272 + uint8 len;
9273 + uint8 mode;
9274 + uint8 channel;
9275 + uint8 count;
9276 +} PACKED;
9277 +typedef struct dot11_channel_switch dot11_channel_switch_t;
9278 +
9279 +/* 802.11h Measurement Request/Report IEs */
9280 +/* Measurement Type field */
9281 +#define DOT11_MEASURE_TYPE_BASIC 0
9282 +#define DOT11_MEASURE_TYPE_CCA 1
9283 +#define DOT11_MEASURE_TYPE_RPI 2
9284 +
9285 +/* Measurement Mode field */
9286 +
9287 +/* Measurement Request Modes */
9288 +#define DOT11_MEASURE_MODE_ENABLE (1<<1)
9289 +#define DOT11_MEASURE_MODE_REQUEST (1<<2)
9290 +#define DOT11_MEASURE_MODE_REPORT (1<<3)
9291 +/* Measurement Report Modes */
9292 +#define DOT11_MEASURE_MODE_LATE (1<<0)
9293 +#define DOT11_MEASURE_MODE_INCAPABLE (1<<1)
9294 +#define DOT11_MEASURE_MODE_REFUSED (1<<2)
9295 +/* Basic Measurement Map bits */
9296 +#define DOT11_MEASURE_BASIC_MAP_BSS ((uint8)(1<<0))
9297 +#define DOT11_MEASURE_BASIC_MAP_OFDM ((uint8)(1<<1))
9298 +#define DOT11_MEASURE_BASIC_MAP_UKNOWN ((uint8)(1<<2))
9299 +#define DOT11_MEASURE_BASIC_MAP_RADAR ((uint8)(1<<3))
9300 +#define DOT11_MEASURE_BASIC_MAP_UNMEAS ((uint8)(1<<4))
9301 +
9302 +typedef struct {
9303 + uint8 id;
9304 + uint8 len;
9305 + uint8 token;
9306 + uint8 mode;
9307 + uint8 type;
9308 + uint8 channel;
9309 + uint8 start_time[8];
9310 + uint16 duration;
9311 +} dot11_meas_req_t;
9312 +#define DOT11_MNG_IE_MREQ_LEN 14
9313 +/* length of Measure Request IE data not including variable len */
9314 +#define DOT11_MNG_IE_MREQ_FIXED_LEN 3
9315 +
9316 +struct dot11_meas_rep {
9317 + uint8 id;
9318 + uint8 len;
9319 + uint8 token;
9320 + uint8 mode;
9321 + uint8 type;
9322 + union
9323 + {
9324 + struct {
9325 + uint8 channel;
9326 + uint8 start_time[8];
9327 + uint16 duration;
9328 + uint8 map;
9329 + } PACKED basic;
9330 + uint8 data[1];
9331 + } PACKED rep;
9332 +} PACKED;
9333 +typedef struct dot11_meas_rep dot11_meas_rep_t;
9334 +
9335 +/* length of Measure Report IE data not including variable len */
9336 +#define DOT11_MNG_IE_MREP_FIXED_LEN 3
9337 +
9338 +struct dot11_meas_rep_basic {
9339 + uint8 channel;
9340 + uint8 start_time[8];
9341 + uint16 duration;
9342 + uint8 map;
9343 +} PACKED;
9344 +typedef struct dot11_meas_rep_basic dot11_meas_rep_basic_t;
9345 +#define DOT11_MEASURE_BASIC_REP_LEN 12
9346 +
9347 +struct dot11_quiet {
9348 + uint8 id;
9349 + uint8 len;
9350 + uint8 count; /* TBTTs until beacon interval in quiet starts */
9351 + uint8 period; /* Beacon intervals between periodic quiet periods ? */
9352 + uint16 duration;/* Length of quiet period, in TU's */
9353 + uint16 offset; /* TU's offset from TBTT in Count field */
9354 +} PACKED;
9355 +typedef struct dot11_quiet dot11_quiet_t;
9356 +
9357 +typedef struct {
9358 + uint8 channel;
9359 + uint8 map;
9360 +} chan_map_tuple_t;
9361 +
9362 +typedef struct {
9363 + uint8 id;
9364 + uint8 len;
9365 + uint8 eaddr[ETHER_ADDR_LEN];
9366 + uint8 interval;
9367 + chan_map_tuple_t map[1];
9368 +} dot11_ibss_dfs_t;
9369 +
9370 +
9371 +/* Macro to take a pointer to a beacon or probe response
9372 + * header and return the char* pointer to the SSID info element
9373 + */
9374 +#define BCN_PRB_SSID(hdr) ((char*)(hdr) + DOT11_MGMT_HDR_LEN + DOT11_BCN_PRB_LEN)
9375 +
9376 +/* Authentication frame payload constants */
9377 +#define DOT11_OPEN_SYSTEM 0
9378 +#define DOT11_SHARED_KEY 1
9379 +#define DOT11_CHALLENGE_LEN 128
9380 +
9381 +/* Frame control macros */
9382 +#define FC_PVER_MASK 0x3
9383 +#define FC_PVER_SHIFT 0
9384 +#define FC_TYPE_MASK 0xC
9385 +#define FC_TYPE_SHIFT 2
9386 +#define FC_SUBTYPE_MASK 0xF0
9387 +#define FC_SUBTYPE_SHIFT 4
9388 +#define FC_TODS 0x100
9389 +#define FC_TODS_SHIFT 8
9390 +#define FC_FROMDS 0x200
9391 +#define FC_FROMDS_SHIFT 9
9392 +#define FC_MOREFRAG 0x400
9393 +#define FC_MOREFRAG_SHIFT 10
9394 +#define FC_RETRY 0x800
9395 +#define FC_RETRY_SHIFT 11
9396 +#define FC_PM 0x1000
9397 +#define FC_PM_SHIFT 12
9398 +#define FC_MOREDATA 0x2000
9399 +#define FC_MOREDATA_SHIFT 13
9400 +#define FC_WEP 0x4000
9401 +#define FC_WEP_SHIFT 14
9402 +#define FC_ORDER 0x8000
9403 +#define FC_ORDER_SHIFT 15
9404 +
9405 +/* sequence control macros */
9406 +#define SEQNUM_SHIFT 4
9407 +#define FRAGNUM_MASK 0xF
9408 +
9409 +/* Frame Control type/subtype defs */
9410 +
9411 +/* FC Types */
9412 +#define FC_TYPE_MNG 0
9413 +#define FC_TYPE_CTL 1
9414 +#define FC_TYPE_DATA 2
9415 +
9416 +/* Management Subtypes */
9417 +#define FC_SUBTYPE_ASSOC_REQ 0
9418 +#define FC_SUBTYPE_ASSOC_RESP 1
9419 +#define FC_SUBTYPE_REASSOC_REQ 2
9420 +#define FC_SUBTYPE_REASSOC_RESP 3
9421 +#define FC_SUBTYPE_PROBE_REQ 4
9422 +#define FC_SUBTYPE_PROBE_RESP 5
9423 +#define FC_SUBTYPE_BEACON 8
9424 +#define FC_SUBTYPE_ATIM 9
9425 +#define FC_SUBTYPE_DISASSOC 10
9426 +#define FC_SUBTYPE_AUTH 11
9427 +#define FC_SUBTYPE_DEAUTH 12
9428 +#define FC_SUBTYPE_ACTION 13
9429 +
9430 +/* Control Subtypes */
9431 +#define FC_SUBTYPE_PS_POLL 10
9432 +#define FC_SUBTYPE_RTS 11
9433 +#define FC_SUBTYPE_CTS 12
9434 +#define FC_SUBTYPE_ACK 13
9435 +#define FC_SUBTYPE_CF_END 14
9436 +#define FC_SUBTYPE_CF_END_ACK 15
9437 +
9438 +/* Data Subtypes */
9439 +#define FC_SUBTYPE_DATA 0
9440 +#define FC_SUBTYPE_DATA_CF_ACK 1
9441 +#define FC_SUBTYPE_DATA_CF_POLL 2
9442 +#define FC_SUBTYPE_DATA_CF_ACK_POLL 3
9443 +#define FC_SUBTYPE_NULL 4
9444 +#define FC_SUBTYPE_CF_ACK 5
9445 +#define FC_SUBTYPE_CF_POLL 6
9446 +#define FC_SUBTYPE_CF_ACK_POLL 7
9447 +
9448 +/* type-subtype combos */
9449 +#define FC_KIND_MASK (FC_TYPE_MASK | FC_SUBTYPE_MASK)
9450 +
9451 +#define FC_KIND(t, s) (((t) << FC_TYPE_SHIFT) | ((s) << FC_SUBTYPE_SHIFT))
9452 +
9453 +#define FC_ASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_REQ)
9454 +#define FC_ASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_RESP)
9455 +#define FC_REASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_REQ)
9456 +#define FC_REASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_RESP)
9457 +#define FC_PROBE_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_REQ)
9458 +#define FC_PROBE_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_RESP)
9459 +#define FC_BEACON FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_BEACON)
9460 +#define FC_DISASSOC FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DISASSOC)
9461 +#define FC_AUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_AUTH)
9462 +#define FC_DEAUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DEAUTH)
9463 +#define FC_ACTION FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ACTION)
9464 +
9465 +#define FC_PS_POLL FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_PS_POLL)
9466 +#define FC_RTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_RTS)
9467 +#define FC_CTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CTS)
9468 +#define FC_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_ACK)
9469 +#define FC_CF_END FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END)
9470 +#define FC_CF_END_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END_ACK)
9471 +
9472 +#define FC_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA)
9473 +#define FC_NULL_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_NULL)
9474 +#define FC_DATA_CF_ACK FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA_CF_ACK)
9475 +
9476 +/* Management Frames */
9477 +
9478 +/* Management Frame Constants */
9479 +
9480 +/* Fixed fields */
9481 +#define DOT11_MNG_AUTH_ALGO_LEN 2
9482 +#define DOT11_MNG_AUTH_SEQ_LEN 2
9483 +#define DOT11_MNG_BEACON_INT_LEN 2
9484 +#define DOT11_MNG_CAP_LEN 2
9485 +#define DOT11_MNG_AP_ADDR_LEN 6
9486 +#define DOT11_MNG_LISTEN_INT_LEN 2
9487 +#define DOT11_MNG_REASON_LEN 2
9488 +#define DOT11_MNG_AID_LEN 2
9489 +#define DOT11_MNG_STATUS_LEN 2
9490 +#define DOT11_MNG_TIMESTAMP_LEN 8
9491 +
9492 +/* DUR/ID field in assoc resp is 0xc000 | AID */
9493 +#define DOT11_AID_MASK 0x3fff
9494 +
9495 +/* Reason Codes */
9496 +#define DOT11_RC_RESERVED 0
9497 +#define DOT11_RC_UNSPECIFIED 1 /* Unspecified reason */
9498 +#define DOT11_RC_AUTH_INVAL 2 /* Previous authentication no longer valid */
9499 +#define DOT11_RC_DEAUTH_LEAVING 3 /* Deauthenticated because sending station is
9500 + leaving (or has left) IBSS or ESS */
9501 +#define DOT11_RC_INACTIVITY 4 /* Disassociated due to inactivity */
9502 +#define DOT11_RC_BUSY 5 /* Disassociated because AP is unable to handle
9503 + all currently associated stations */
9504 +#define DOT11_RC_INVAL_CLASS_2 6 /* Class 2 frame received from
9505 + nonauthenticated station */
9506 +#define DOT11_RC_INVAL_CLASS_3 7 /* Class 3 frame received from
9507 + nonassociated station */
9508 +#define DOT11_RC_DISASSOC_LEAVING 8 /* Disassociated because sending station is
9509 + leaving (or has left) BSS */
9510 +#define DOT11_RC_NOT_AUTH 9 /* Station requesting (re)association is
9511 + not authenticated with responding station */
9512 +#define DOT11_RC_MAX 23 /* Reason codes > 23 are reserved */
9513 +
9514 +/* Status Codes */
9515 +#define DOT11_STATUS_SUCCESS 0 /* Successful */
9516 +#define DOT11_STATUS_FAILURE 1 /* Unspecified failure */
9517 +#define DOT11_STATUS_CAP_MISMATCH 10 /* Cannot support all requested capabilities
9518 + in the Capability Information field */
9519 +#define DOT11_STATUS_REASSOC_FAIL 11 /* Reassociation denied due to inability to
9520 + confirm that association exists */
9521 +#define DOT11_STATUS_ASSOC_FAIL 12 /* Association denied due to reason outside
9522 + the scope of this standard */
9523 +#define DOT11_STATUS_AUTH_MISMATCH 13 /* Responding station does not support the
9524 + specified authentication algorithm */
9525 +#define DOT11_STATUS_AUTH_SEQ 14 /* Received an Authentication frame with
9526 + authentication transaction sequence number
9527 + out of expected sequence */
9528 +#define DOT11_STATUS_AUTH_CHALLENGE_FAIL 15 /* Authentication rejected because of challenge failure */
9529 +#define DOT11_STATUS_AUTH_TIMEOUT 16 /* Authentication rejected due to timeout waiting
9530 + for next frame in sequence */
9531 +#define DOT11_STATUS_ASSOC_BUSY_FAIL 17 /* Association denied because AP is unable to
9532 + handle additional associated stations */
9533 +#define DOT11_STATUS_ASSOC_RATE_MISMATCH 18 /* Association denied due to requesting station
9534 + not supporting all of the data rates in the
9535 + BSSBasicRateSet parameter */
9536 +#define DOT11_STATUS_ASSOC_SHORT_REQUIRED 19 /* Association denied due to requesting station
9537 + not supporting the Short Preamble option */
9538 +#define DOT11_STATUS_ASSOC_PBCC_REQUIRED 20 /* Association denied due to requesting station
9539 + not supporting the PBCC Modulation option */
9540 +#define DOT11_STATUS_ASSOC_AGILITY_REQUIRED 21 /* Association denied due to requesting station
9541 + not supporting the Channel Agility option */
9542 +#define DOT11_STATUS_ASSOC_SPECTRUM_REQUIRED 22 /* Association denied because Spectrum Management
9543 + capability is required. */
9544 +#define DOT11_STATUS_ASSOC_BAD_POWER_CAP 23 /* Association denied because the info in the
9545 + Power Cap element is unacceptable. */
9546 +#define DOT11_STATUS_ASSOC_BAD_SUP_CHANNELS 24 /* Association denied because the info in the
9547 + Supported Channel element is unacceptable */
9548 +#define DOT11_STATUS_ASSOC_SHORTSLOT_REQUIRED 25 /* Association denied due to requesting station
9549 + not supporting the Short Slot Time option */
9550 +#define DOT11_STATUS_ASSOC_ERPBCC_REQUIRED 26 /* Association denied due to requesting station
9551 + not supporting the ER-PBCC Modulation option */
9552 +#define DOT11_STATUS_ASSOC_DSSOFDM_REQUIRED 27 /* Association denied due to requesting station
9553 + not supporting the DSS-OFDM option */
9554 +
9555 +/* Info Elts, length of INFORMATION portion of Info Elts */
9556 +#define DOT11_MNG_DS_PARAM_LEN 1
9557 +#define DOT11_MNG_IBSS_PARAM_LEN 2
9558 +
9559 +/* TIM Info element has 3 bytes fixed info in INFORMATION field,
9560 + * followed by 1 to 251 bytes of Partial Virtual Bitmap */
9561 +#define DOT11_MNG_TIM_FIXED_LEN 3
9562 +#define DOT11_MNG_TIM_DTIM_COUNT 0
9563 +#define DOT11_MNG_TIM_DTIM_PERIOD 1
9564 +#define DOT11_MNG_TIM_BITMAP_CTL 2
9565 +#define DOT11_MNG_TIM_PVB 3
9566 +
9567 +/* TLV defines */
9568 +#define TLV_TAG_OFF 0
9569 +#define TLV_LEN_OFF 1
9570 +#define TLV_HDR_LEN 2
9571 +#define TLV_BODY_OFF 2
9572 +
9573 +/* Management Frame Information Element IDs */
9574 +#define DOT11_MNG_SSID_ID 0
9575 +#define DOT11_MNG_RATES_ID 1
9576 +#define DOT11_MNG_FH_PARMS_ID 2
9577 +#define DOT11_MNG_DS_PARMS_ID 3
9578 +#define DOT11_MNG_CF_PARMS_ID 4
9579 +#define DOT11_MNG_TIM_ID 5
9580 +#define DOT11_MNG_IBSS_PARMS_ID 6
9581 +#define DOT11_MNG_COUNTRY_ID 7
9582 +#define DOT11_MNG_HOPPING_PARMS_ID 8
9583 +#define DOT11_MNG_HOPPING_TABLE_ID 9
9584 +#define DOT11_MNG_REQUEST_ID 10
9585 +#define DOT11_MNG_CHALLENGE_ID 16
9586 +#define DOT11_MNG_PWR_CONSTRAINT_ID 32 /* 11H PowerConstraint */
9587 +#define DOT11_MNG_PWR_CAP_ID 33 /* 11H PowerCapability */
9588 +#define DOT11_MNG_TPC_REQUEST_ID 34 /* 11H TPC Request */
9589 +#define DOT11_MNG_TPC_REPORT_ID 35 /* 11H TPC Report */
9590 +#define DOT11_MNG_SUPP_CHANNELS_ID 36 /* 11H Supported Channels */
9591 +#define DOT11_MNG_CHANNEL_SWITCH_ID 37 /* 11H ChannelSwitch Announcement*/
9592 +#define DOT11_MNG_MEASURE_REQUEST_ID 38 /* 11H MeasurementRequest */
9593 +#define DOT11_MNG_MEASURE_REPORT_ID 39 /* 11H MeasurementReport */
9594 +#define DOT11_MNG_QUIET_ID 40 /* 11H Quiet */
9595 +#define DOT11_MNG_IBSS_DFS_ID 41 /* 11H IBSS_DFS */
9596 +#define DOT11_MNG_ERP_ID 42
9597 +#define DOT11_MNG_NONERP_ID 47
9598 +#define DOT11_MNG_EXT_RATES_ID 50
9599 +#define DOT11_MNG_WPA_ID 221
9600 +#define DOT11_MNG_PROPR_ID 221
9601 +
9602 +/* ERP info element bit values */
9603 +#define DOT11_MNG_ERP_LEN 1 /* ERP is currently 1 byte long */
9604 +#define DOT11_MNG_NONERP_PRESENT 0x01 /* NonERP (802.11b) STAs are present in the BSS */
9605 +#define DOT11_MNG_USE_PROTECTION 0x02 /* Use protection mechanisms for ERP-OFDM frames */
9606 +#define DOT11_MNG_BARKER_PREAMBLE 0x04 /* Short Preambles: 0 == allowed, 1 == not allowed */
9607 +
9608 +/* Capability Information Field */
9609 +#define DOT11_CAP_ESS 0x0001
9610 +#define DOT11_CAP_IBSS 0x0002
9611 +#define DOT11_CAP_POLLABLE 0x0004
9612 +#define DOT11_CAP_POLL_RQ 0x0008
9613 +#define DOT11_CAP_PRIVACY 0x0010
9614 +#define DOT11_CAP_SHORT 0x0020
9615 +#define DOT11_CAP_PBCC 0x0040
9616 +#define DOT11_CAP_AGILITY 0x0080
9617 +#define DOT11_CAP_SPECTRUM 0x0100
9618 +#define DOT11_CAP_SHORTSLOT 0x0400
9619 +#define DOT11_CAP_CCK_OFDM 0x2000
9620 +
9621 +/* Action Frame Constants */
9622 +#define DOT11_ACTION_CAT_ERR_MASK 0x10
9623 +#define DOT11_ACTION_CAT_SPECT_MNG 0x00
9624 +
9625 +#define DOT11_ACTION_ID_M_REQ 0
9626 +#define DOT11_ACTION_ID_M_REP 1
9627 +#define DOT11_ACTION_ID_TPC_REQ 2
9628 +#define DOT11_ACTION_ID_TPC_REP 3
9629 +#define DOT11_ACTION_ID_CHANNEL_SWITCH 4
9630 +
9631 +/* MLME Enumerations */
9632 +#define DOT11_BSSTYPE_INFRASTRUCTURE 0
9633 +#define DOT11_BSSTYPE_INDEPENDENT 1
9634 +#define DOT11_BSSTYPE_ANY 2
9635 +#define DOT11_SCANTYPE_ACTIVE 0
9636 +#define DOT11_SCANTYPE_PASSIVE 1
9637 +
9638 +/* 802.11 A PHY constants */
9639 +#define APHY_SLOT_TIME 9
9640 +#define APHY_SIFS_TIME 16
9641 +#define APHY_DIFS_TIME (APHY_SIFS_TIME + (2 * APHY_SLOT_TIME))
9642 +#define APHY_PREAMBLE_TIME 16
9643 +#define APHY_SIGNAL_TIME 4
9644 +#define APHY_SYMBOL_TIME 4
9645 +#define APHY_SERVICE_NBITS 16
9646 +#define APHY_TAIL_NBITS 6
9647 +#define APHY_CWMIN 15
9648 +
9649 +/* 802.11 B PHY constants */
9650 +#define BPHY_SLOT_TIME 20
9651 +#define BPHY_SIFS_TIME 10
9652 +#define BPHY_DIFS_TIME 50
9653 +#define BPHY_PLCP_TIME 192
9654 +#define BPHY_PLCP_SHORT_TIME 96
9655 +#define BPHY_CWMIN 31
9656 +
9657 +/* 802.11 G constants */
9658 +#define DOT11_OFDM_SIGNAL_EXTENSION 6
9659 +
9660 +#define PHY_CWMAX 1023
9661 +
9662 +#define DOT11_MAXNUMFRAGS 16 /* max # fragments per MSDU */
9663 +
9664 +/* dot11Counters Table - 802.11 spec., Annex D */
9665 +typedef struct d11cnt {
9666 + uint32 txfrag; /* dot11TransmittedFragmentCount */
9667 + uint32 txmulti; /* dot11MulticastTransmittedFrameCount */
9668 + uint32 txfail; /* dot11FailedCount */
9669 + uint32 txretry; /* dot11RetryCount */
9670 + uint32 txretrie; /* dot11MultipleRetryCount */
9671 + uint32 rxdup; /* dot11FrameduplicateCount */
9672 + uint32 txrts; /* dot11RTSSuccessCount */
9673 + uint32 txnocts; /* dot11RTSFailureCount */
9674 + uint32 txnoack; /* dot11ACKFailureCount */
9675 + uint32 rxfrag; /* dot11ReceivedFragmentCount */
9676 + uint32 rxmulti; /* dot11MulticastReceivedFrameCount */
9677 + uint32 rxcrc; /* dot11FCSErrorCount */
9678 + uint32 txfrmsnt; /* dot11TransmittedFrameCount */
9679 + uint32 rxundec; /* dot11WEPUndecryptableCount */
9680 +} d11cnt_t;
9681 +
9682 +/* BRCM OUI */
9683 +#define BRCM_OUI "\x00\x10\x18"
9684 +
9685 +/* WPA definitions */
9686 +#define WPA_VERSION 1
9687 +#define WPA_OUI "\x00\x50\xF2"
9688 +
9689 +#define WPA_OUI_LEN 3
9690 +
9691 +/* WPA authentication modes */
9692 +#define WPA_AUTH_NONE 0 /* None */
9693 +#define WPA_AUTH_UNSPECIFIED 1 /* Unspecified authentication over 802.1X: default for WPA */
9694 +#define WPA_AUTH_PSK 2 /* Pre-shared Key over 802.1X */
9695 +#define WPA_AUTH_DISABLED 255 /* Legacy (i.e., non-WPA) */
9696 +
9697 +#define IS_WPA_AUTH(auth) ((auth) == WPA_AUTH_NONE || \
9698 + (auth) == WPA_AUTH_UNSPECIFIED || \
9699 + (auth) == WPA_AUTH_PSK)
9700 +
9701 +
9702 +/* Key related defines */
9703 +#define DOT11_MAX_KEY_SIZE 32 /* max size of any key */
9704 +#define DOT11_MAX_IV_SIZE 16 /* max size of any IV */
9705 +#define DOT11_EXT_IV_FLAG (1<<5) /* flag to indicate IV is > 4 bytes */
9706 +
9707 +#define WEP1_KEY_SIZE 5 /* max size of any WEP key */
9708 +#define WEP1_KEY_HEX_SIZE 10 /* size of WEP key in hex. */
9709 +#define WEP128_KEY_SIZE 13 /* max size of any WEP key */
9710 +#define WEP128_KEY_HEX_SIZE 26 /* size of WEP key in hex. */
9711 +#define TKIP_MIC_SIZE 8 /* size of TKIP MIC */
9712 +#define TKIP_EOM_SIZE 7 /* max size of TKIP EOM */
9713 +#define TKIP_EOM_FLAG 0x5a /* TKIP EOM flag byte */
9714 +#define TKIP_KEY_SIZE 32 /* size of any TKIP key */
9715 +#define TKIP_MIC_AUTH_TX 16 /* offset to Authenticator MIC TX key */
9716 +#define TKIP_MIC_AUTH_RX 24 /* offset to Authenticator MIC RX key */
9717 +#define TKIP_MIC_SUP_RX 16 /* offset to Supplicant MIC RX key */
9718 +#define TKIP_MIC_SUP_TX 24 /* offset to Supplicant MIC TX key */
9719 +#define AES_KEY_SIZE 16 /* size of AES key */
9720 +
9721 +#undef PACKED
9722 +#if !defined(__GNUC__)
9723 +#pragma pack()
9724 +#endif
9725 +
9726 +#endif /* _802_11_H_ */
9727 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/proto/ethernet.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/proto/ethernet.h
9728 --- linux-2.6.12.5/arch/mips/bcm947xx/include/proto/ethernet.h 1970-01-01 01:00:00.000000000 +0100
9729 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/proto/ethernet.h 2005-08-28 11:12:20.450856112 +0200
9730 @@ -0,0 +1,145 @@
9731 +/*******************************************************************************
9732 + * $Id$
9733 + * Copyright 2001-2003, Broadcom Corporation
9734 + * All Rights Reserved.
9735 + *
9736 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9737 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9738 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9739 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9740 + * From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
9741 + ******************************************************************************/
9742 +
9743 +#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
9744 +#define _NET_ETHERNET_H_
9745 +
9746 +#ifndef _TYPEDEFS_H_
9747 +#include "typedefs.h"
9748 +#endif
9749 +
9750 +#if defined(__GNUC__)
9751 +#define PACKED __attribute__((packed))
9752 +#else
9753 +#define PACKED
9754 +#endif
9755 +
9756 +/*
9757 + * The number of bytes in an ethernet (MAC) address.
9758 + */
9759 +#define ETHER_ADDR_LEN 6
9760 +
9761 +/*
9762 + * The number of bytes in the type field.
9763 + */
9764 +#define ETHER_TYPE_LEN 2
9765 +
9766 +/*
9767 + * The number of bytes in the trailing CRC field.
9768 + */
9769 +#define ETHER_CRC_LEN 4
9770 +
9771 +/*
9772 + * The length of the combined header.
9773 + */
9774 +#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN)
9775 +
9776 +/*
9777 + * The minimum packet length.
9778 + */
9779 +#define ETHER_MIN_LEN 64
9780 +
9781 +/*
9782 + * The minimum packet user data length.
9783 + */
9784 +#define ETHER_MIN_DATA 46
9785 +
9786 +/*
9787 + * The maximum packet length.
9788 + */
9789 +#define ETHER_MAX_LEN 1518
9790 +
9791 +/*
9792 + * The maximum packet user data length.
9793 + */
9794 +#define ETHER_MAX_DATA 1500
9795 +
9796 +/*
9797 + * Used to uniquely identify a 802.1q VLAN-tagged header.
9798 + */
9799 +#define VLAN_TAG 0x8100
9800 +
9801 +/*
9802 + * Located after dest & src address in ether header.
9803 + */
9804 +#define VLAN_FIELDS_OFFSET (ETHER_ADDR_LEN * 2)
9805 +
9806 +/*
9807 + * 4 bytes of vlan field info.
9808 + */
9809 +#define VLAN_FIELDS_SIZE 4
9810 +
9811 +/* location of pri bits in 16-bit vlan fields */
9812 +#define VLAN_PRI_SHIFT 13
9813 +
9814 +/* 3 bits of priority */
9815 +#define VLAN_PRI_MASK 7
9816 +
9817 +/* 802.1X ethertype */
9818 +#define ETHER_TYPE_802_1X 0x888e
9819 +
9820 +/*
9821 + * A macro to validate a length with
9822 + */
9823 +#define ETHER_IS_VALID_LEN(foo) \
9824 + ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
9825 +
9826 +
9827 +#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
9828 +/*
9829 + * Structure of a 10Mb/s Ethernet header.
9830 + */
9831 +struct ether_header {
9832 + uint8 ether_dhost[ETHER_ADDR_LEN];
9833 + uint8 ether_shost[ETHER_ADDR_LEN];
9834 + uint16 ether_type;
9835 +} PACKED ;
9836 +
9837 +/*
9838 + * Structure of a 48-bit Ethernet address.
9839 + */
9840 +struct ether_addr {
9841 + uint8 octet[ETHER_ADDR_LEN];
9842 +} PACKED ;
9843 +#endif
9844 +
9845 +/*
9846 + * Takes a pointer, returns true if a 48-bit multicast address
9847 + * (including broadcast, since it is all ones)
9848 + */
9849 +#define ETHER_ISMULTI(ea) (((uint8 *)(ea))[0] & 1)
9850 +
9851 +/*
9852 + * Takes a pointer, returns true if a 48-bit broadcast (all ones)
9853 + */
9854 +#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
9855 + ((uint8 *)(ea))[1] & \
9856 + ((uint8 *)(ea))[2] & \
9857 + ((uint8 *)(ea))[3] & \
9858 + ((uint8 *)(ea))[4] & \
9859 + ((uint8 *)(ea))[5]) == 0xff)
9860 +
9861 +static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
9862 +
9863 +/*
9864 + * Takes a pointer, returns true if a 48-bit null address (all zeros)
9865 + */
9866 +#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
9867 + ((uint8 *)(ea))[1] | \
9868 + ((uint8 *)(ea))[2] | \
9869 + ((uint8 *)(ea))[3] | \
9870 + ((uint8 *)(ea))[4] | \
9871 + ((uint8 *)(ea))[5]) == 0)
9872 +
9873 +#undef PACKED
9874 +
9875 +#endif /* _NET_ETHERNET_H_ */
9876 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/rts/crc.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/rts/crc.h
9877 --- linux-2.6.12.5/arch/mips/bcm947xx/include/rts/crc.h 1970-01-01 01:00:00.000000000 +0100
9878 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/rts/crc.h 2005-08-28 11:12:20.451855960 +0200
9879 @@ -0,0 +1,69 @@
9880 +/*******************************************************************************
9881 + * $Id$
9882 + * Copyright 2001-2003, Broadcom Corporation
9883 + * All Rights Reserved.
9884 + *
9885 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9886 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9887 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9888 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9889 + * crc.h - a function to compute crc for iLine10 headers
9890 + ******************************************************************************/
9891 +
9892 +#ifndef _RTS_CRC_H_
9893 +#define _RTS_CRC_H_ 1
9894 +
9895 +#include "typedefs.h"
9896 +
9897 +#ifdef __cplusplus
9898 +extern "C" {
9899 +#endif
9900 +
9901 +
9902 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
9903 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
9904 +#define HCS_GOOD_VALUE 0x39 /* Good final header checksum value */
9905 +
9906 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
9907 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
9908 +
9909 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
9910 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
9911 +
9912 +void hcs(uint8 *, uint);
9913 +uint8 crc8(uint8 *, uint, uint8);
9914 +uint16 crc16(uint8 *, uint, uint16);
9915 +uint32 crc32(uint8 *, uint, uint32);
9916 +
9917 +/* macros for common usage */
9918 +
9919 +#define APPEND_CRC8(pbytes, nbytes) \
9920 +do { \
9921 + uint8 tmp = crc8(pbytes, nbytes, CRC8_INIT_VALUE) ^ 0xff; \
9922 + (pbytes)[(nbytes)] = tmp; \
9923 + (nbytes) += 1; \
9924 +} while (0)
9925 +
9926 +#define APPEND_CRC16(pbytes, nbytes) \
9927 +do { \
9928 + uint16 tmp = crc16(pbytes, nbytes, CRC16_INIT_VALUE) ^ 0xffff; \
9929 + (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
9930 + (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
9931 + (nbytes) += 2; \
9932 +} while (0)
9933 +
9934 +#define APPEND_CRC32(pbytes, nbytes) \
9935 +do { \
9936 + uint32 tmp = crc32(pbytes, nbytes, CRC32_INIT_VALUE) ^ 0xffffffff; \
9937 + (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
9938 + (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
9939 + (pbytes)[(nbytes) + 2] = (tmp >> 16) & 0xff; \
9940 + (pbytes)[(nbytes) + 3] = (tmp >> 24) & 0xff; \
9941 + (nbytes) += 4; \
9942 +} while (0)
9943 +
9944 +#ifdef __cplusplus
9945 +}
9946 +#endif
9947 +
9948 +#endif /* _RTS_CRC_H_ */
9949 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/s5.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/s5.h
9950 --- linux-2.6.12.5/arch/mips/bcm947xx/include/s5.h 1970-01-01 01:00:00.000000000 +0100
9951 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/s5.h 2005-08-28 11:12:20.451855960 +0200
9952 @@ -0,0 +1,103 @@
9953 +#ifndef _S5_H_
9954 +#define _S5_H_
9955 +/*
9956 + * Copyright 2003, Broadcom Corporation
9957 + * All Rights Reserved.
9958 + *
9959 + * Broadcom Sentry5 (S5) BCM5365, 53xx, BCM58xx SOC Internal Core
9960 + * and MIPS3301 (R4K) System Address Space
9961 + *
9962 + * This program is free software; you can redistribute it and/or
9963 + * modify it under the terms of the GNU General Public License as
9964 + * published by the Free Software Foundation, located in the file
9965 + * LICENSE.
9966 + *
9967 + * $Id: s5.h,v 1.3 2003/06/10 18:54:51 jfd Exp $
9968 + *
9969 + */
9970 +
9971 +/* BCM5365 Address map */
9972 +#define KSEG1ADDR(x) ( (x) | 0xa0000000)
9973 +#define BCM5365_SDRAM 0x00000000 /* 0-128MB Physical SDRAM */
9974 +#define BCM5365_PCI_MEM 0x08000000 /* Host Mode PCI mem space (64MB) */
9975 +#define BCM5365_PCI_CFG 0x0c000000 /* Host Mode PCI cfg space (64MB) */
9976 +#define BCM5365_PCI_DMA 0x40000000 /* Client Mode PCI mem space (1GB)*/
9977 +#define BCM5365_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
9978 +#define BCM5365_ENUM 0x18000000 /* Beginning of core enum space */
9979 +
9980 +/* BCM5365 Core register space */
9981 +#define BCM5365_REG_CHIPC 0x18000000 /* Chipcommon registers */
9982 +#define BCM5365_REG_EMAC0 0x18001000 /* Ethernet MAC0 core registers */
9983 +#define BCM5365_REG_IPSEC 0x18002000 /* BCM582x CryptoCore registers */
9984 +#define BCM5365_REG_USB 0x18003000 /* USB core registers */
9985 +#define BCM5365_REG_PCI 0x18004000 /* PCI core registers */
9986 +#define BCM5365_REG_MIPS33 0x18005000 /* MIPS core registers */
9987 +#define BCM5365_REG_MEMC 0x18006000 /* MEMC core registers */
9988 +#define BCM5365_REG_UARTS (BCM5365_REG_CHIPC + 0x300) /* UART regs */
9989 +#define BCM5365_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
9990 +
9991 +/* COM Ports 1/2 */
9992 +#define BCM5365_UART (BCM5365_REG_UARTS)
9993 +#define BCM5365_UART_COM2 (BCM5365_REG_UARTS + 0x00000100)
9994 +
9995 +/* Registers common to MIPS33 Core used in 5365 */
9996 +#define MIPS33_FLASH_REGION 0x1fc00000 /* Boot FLASH Region */
9997 +#define MIPS33_EXTIF_REGION 0x1a000000 /* Chipcommon EXTIF region*/
9998 +#define BCM5365_EXTIF 0x1b000000 /* MISC_CS */
9999 +#define MIPS33_FLASH_REGION_AUX 0x1c000000 /* FLASH Region 2*/
10000 +
10001 +/* Internal Core Sonics Backplane Devices */
10002 +#define INTERNAL_UART_COM1 BCM5365_UART
10003 +#define INTERNAL_UART_COM2 BCM5365_UART_COM2
10004 +#define SB_REG_CHIPC BCM5365_REG_CHIPC
10005 +#define SB_REG_ENET0 BCM5365_REG_EMAC0
10006 +#define SB_REG_IPSEC BCM5365_REG_IPSEC
10007 +#define SB_REG_USB BCM5365_REG_USB
10008 +#define SB_REG_PCI BCM5365_REG_PCI
10009 +#define SB_REG_MIPS BCM5365_REG_MIPS33
10010 +#define SB_REG_MEMC BCM5365_REG_MEMC
10011 +#define SB_REG_MEMC_OFF 0x6000
10012 +#define SB_EXTIF_SPACE MIPS33_EXTIF_REGION
10013 +#define SB_FLASH_SPACE MIPS33_FLASH_REGION
10014 +
10015 +/*
10016 + * XXX
10017 + * 5365-specific backplane interrupt flag numbers. This should be done
10018 + * dynamically instead.
10019 + */
10020 +#define SBFLAG_PCI 0
10021 +#define SBFLAG_ENET0 1
10022 +#define SBFLAG_ILINE20 2
10023 +#define SBFLAG_CODEC 3
10024 +#define SBFLAG_USB 4
10025 +#define SBFLAG_EXTIF 5
10026 +#define SBFLAG_ENET1 6
10027 +
10028 +/* BCM95365 Local Bus devices */
10029 +#define BCM95365K_RESET_ADDR BCM5365_EXTIF
10030 +#define BCM95365K_BOARDID_ADDR (BCM5365_EXTIF | 0x4000)
10031 +#define BCM95365K_DOC_ADDR (BCM5365_EXTIF | 0x6000)
10032 +#define BCM95365K_LED_ADDR (BCM5365_EXTIF | 0xc000)
10033 +#define BCM95365K_TOD_REG_BASE (BCM95365K_NVRAM_ADDR | 0x1ff0)
10034 +#define BCM95365K_NVRAM_ADDR (BCM5365_EXTIF | 0xe000)
10035 +#define BCM95365K_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
10036 +
10037 +/* Write to DLR2416 VFD Display character RAM */
10038 +#define LED_REG(x) \
10039 + (*(volatile unsigned char *) (KSEG1ADDR(BCM95365K_LED_ADDR) + (x)))
10040 +
10041 +#ifdef CONFIG_VSIM
10042 +#define BCM5365_TRACE(trval) do { *((int *)0xa0002ff8) = (trval); \
10043 + } while (0)
10044 +#else
10045 +#define BCM5365_TRACE(trval) do { *((unsigned char *)\
10046 + KSEG1ADDR(BCM5365K_LED_ADDR)) = (trval); \
10047 + *((int *)0xa0002ff8) = (trval); } while (0)
10048 +#endif
10049 +
10050 +/* BCM9536R Local Bus devices */
10051 +#define BCM95365R_DOC_ADDR BCM5365_EXTIF
10052 +
10053 +
10054 +
10055 +#endif /*!_S5_H_ */
10056 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbchipc.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbchipc.h
10057 --- linux-2.6.12.5/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
10058 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbchipc.h 2005-08-28 11:12:20.468853376 +0200
10059 @@ -0,0 +1,281 @@
10060 +/*
10061 + * SiliconBackplane Chipcommon core hardware definitions.
10062 + *
10063 + * The chipcommon core provides chip identification, SB control,
10064 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
10065 + * gpio interface, extbus, and support for serial and parallel flashes.
10066 + *
10067 + * Copyright 2001-2003, Broadcom Corporation
10068 + * All Rights Reserved.
10069 + *
10070 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10071 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10072 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10073 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10074 + *
10075 + * $Id$
10076 + */
10077 +
10078 +#ifndef _SBCHIPC_H
10079 +#define _SBCHIPC_H
10080 +
10081 +
10082 +/* cpp contortions to concatenate w/arg prescan */
10083 +#ifndef PAD
10084 +#define _PADLINE(line) pad ## line
10085 +#define _XSTR(line) _PADLINE(line)
10086 +#define PAD _XSTR(__LINE__)
10087 +#endif /* PAD */
10088 +
10089 +typedef volatile struct {
10090 + uint32 chipid; /* 0x0 */
10091 + uint32 capabilities;
10092 + uint32 corecontrol; /* corerev >= 1 */
10093 + uint32 PAD[5];
10094 +
10095 + /* Interrupt control */
10096 + uint32 intstatus; /* 0x20 */
10097 + uint32 intmask;
10098 + uint32 PAD[6];
10099 +
10100 + /* serial flash interface registers */
10101 + uint32 flashcontrol; /* 0x40 */
10102 + uint32 flashaddress;
10103 + uint32 flashdata;
10104 + uint32 PAD[1];
10105 +
10106 + /* Silicon backplane configuration broadcast control */
10107 + uint32 broadcastaddress;
10108 + uint32 broadcastdata;
10109 + uint32 PAD[2];
10110 +
10111 + /* gpio - cleared only by power-on-reset */
10112 + uint32 gpioin; /* 0x60 */
10113 + uint32 gpioout;
10114 + uint32 gpioouten;
10115 + uint32 gpiocontrol;
10116 + uint32 gpiointpolarity;
10117 + uint32 gpiointmask;
10118 + uint32 PAD[2];
10119 +
10120 + /* Watchdog timer */
10121 + uint32 watchdog; /* 0x80 */
10122 + uint32 PAD[3];
10123 +
10124 + /* clock control */
10125 + uint32 clockcontrol_n; /* 0x90 */
10126 + uint32 clockcontrol_sb; /* aka m0 */
10127 + uint32 clockcontrol_pci; /* aka m1 */
10128 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
10129 + uint32 clockcontrol_mips; /* aka m3 */
10130 + uint32 uart_clkdiv; /* corerev >= 3 */
10131 + uint32 PAD[2];
10132 +
10133 + /* pll delay registers (corerev >= 4) */
10134 + uint32 pll_on_delay; /* 0xb0 */
10135 + uint32 fref_sel_delay;
10136 + uint32 slow_clk_ctl;
10137 + uint32 PAD[17];
10138 +
10139 + /* ExtBus control registers (corerev >= 3) */
10140 + uint32 cs01config; /* 0x100 */
10141 + uint32 cs01memwaitcnt;
10142 + uint32 cs01attrwaitcnt;
10143 + uint32 cs01iowaitcnt;
10144 + uint32 cs23config;
10145 + uint32 cs23memwaitcnt;
10146 + uint32 cs23attrwaitcnt;
10147 + uint32 cs23iowaitcnt;
10148 + uint32 cs4config;
10149 + uint32 cs4waitcnt;
10150 + uint32 parallelflashconfig;
10151 + uint32 parallelflashwaitcnt;
10152 + uint32 PAD[116];
10153 +
10154 + /* uarts */
10155 + uint8 uart0data; /* 0x300 */
10156 + uint8 uart0imr;
10157 + uint8 uart0fcr;
10158 + uint8 uart0lcr;
10159 + uint8 uart0mcr;
10160 + uint8 uart0lsr;
10161 + uint8 uart0msr;
10162 + uint8 uart0scratch;
10163 + uint8 PAD[248]; /* corerev >= 1 */
10164 +
10165 + uint8 uart1data; /* 0x400 */
10166 + uint8 uart1imr;
10167 + uint8 uart1fcr;
10168 + uint8 uart1lcr;
10169 + uint8 uart1mcr;
10170 + uint8 uart1lsr;
10171 + uint8 uart1msr;
10172 + uint8 uart1scratch;
10173 +} chipcregs_t;
10174 +
10175 +/* chipid */
10176 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
10177 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
10178 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
10179 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
10180 +#define CID_PKG_SHIFT 20 /* Package Option shift */
10181 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
10182 +#define CID_CC_SHIFT 24
10183 +
10184 +/* capabilities */
10185 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
10186 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
10187 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
10188 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
10189 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
10190 +#define CAP_EXTBUS 0x00000040 /* External bus present */
10191 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
10192 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
10193 +#define CAP_PWR_CTL 0x00040000 /* Power control */
10194 +
10195 +/* PLL type */
10196 +#define PLL_NONE 0x00000000
10197 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
10198 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
10199 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
10200 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
10201 +
10202 +/* corecontrol */
10203 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
10204 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
10205 +
10206 +/* intstatus/intmask */
10207 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
10208 +
10209 +/* slow_clk_ctl */
10210 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
10211 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
10212 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
10213 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
10214 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
10215 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
10216 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
10217 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
10218 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
10219 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
10220 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider mask, SlowClk = 1/(4+divisor) * crystal/PCI clock */
10221 +#define SCC_CD_SHF 16 /* CLockDivider shift */
10222 +
10223 +/* clockcontrol_n */
10224 +#define CN_N1_MASK 0x3f /* n1 control */
10225 +#define CN_N2_MASK 0x3f00 /* n2 control */
10226 +#define CN_N2_SHIFT 8
10227 +
10228 +/* clockcontrol_sb/pci/uart */
10229 +#define CC_M1_MASK 0x3f /* m1 control */
10230 +#define CC_M2_MASK 0x3f00 /* m2 control */
10231 +#define CC_M2_SHIFT 8
10232 +#define CC_M3_MASK 0x3f0000 /* m3 control */
10233 +#define CC_M3_SHIFT 16
10234 +#define CC_MC_MASK 0x1f000000 /* mux control */
10235 +#define CC_MC_SHIFT 24
10236 +
10237 +/* N3M Clock control values for 125Mhz */
10238 +#define CC_125_N 0x0802 /* Default values for bcm4310 */
10239 +#define CC_125_M 0x04020009
10240 +#define CC_125_M25 0x11090009
10241 +#define CC_125_M33 0x11090005
10242 +
10243 +/* N3M Clock control magic field values */
10244 +#define CC_F6_2 0x02 /* A factor of 2 in */
10245 +#define CC_F6_3 0x03 /* 6-bit fields like */
10246 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
10247 +#define CC_F6_5 0x09
10248 +#define CC_F6_6 0x11
10249 +#define CC_F6_7 0x21
10250 +
10251 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
10252 +
10253 +#define CC_MC_BYPASS 0x08
10254 +#define CC_MC_M1 0x04
10255 +#define CC_MC_M1M2 0x02
10256 +#define CC_MC_M1M2M3 0x01
10257 +#define CC_MC_M1M3 0x11
10258 +
10259 +/* Type 2 Clock control magic field values */
10260 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
10261 +#define CC_T2M2_BIAS 3 /* m2 bias */
10262 +
10263 +#define CC_T2MC_M1BYP 1
10264 +#define CC_T2MC_M2BYP 2
10265 +#define CC_T2MC_M3BYP 4
10266 +
10267 +/* Common clock base */
10268 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq */
10269 +
10270 +/* Flash types in the chipcommon capabilities register */
10271 +#define FLASH_NONE 0x000 /* No flash */
10272 +#define SFLASH_ST 0x100 /* ST serial flash */
10273 +#define SFLASH_AT 0x200 /* Atmel serial flash */
10274 +#define PFLASH 0x700 /* Parallel flash */
10275 +
10276 +/* Bits in the config registers */
10277 +#define CC_CFG_EN 0x0001 /* Enable */
10278 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
10279 +#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
10280 +#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
10281 +#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
10282 +#define CC_CFG_EM_IDE 0x000a /* IDE */
10283 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
10284 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
10285 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
10286 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
10287 +
10288 +/* Start/busy bit in flashcontrol */
10289 +#define SFLASH_START 0x80000000
10290 +#define SFLASH_BUSY SFLASH_START
10291 +
10292 +/* flashcontrol opcodes for ST flashes */
10293 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
10294 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
10295 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
10296 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
10297 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
10298 +#define SFLASH_ST_PP 0x0302 /* Page Program */
10299 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
10300 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
10301 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
10302 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
10303 +
10304 +/* Status register bits for ST flashes */
10305 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
10306 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
10307 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
10308 +#define SFLASH_ST_BP_SHIFT 2
10309 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
10310 +
10311 +/* flashcontrol opcodes for Atmel flashes */
10312 +#define SFLASH_AT_READ 0x07e8
10313 +#define SFLASH_AT_PAGE_READ 0x07d2
10314 +#define SFLASH_AT_BUF1_READ
10315 +#define SFLASH_AT_BUF2_READ
10316 +#define SFLASH_AT_STATUS 0x01d7
10317 +#define SFLASH_AT_BUF1_WRITE 0x0384
10318 +#define SFLASH_AT_BUF2_WRITE 0x0387
10319 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
10320 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
10321 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
10322 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
10323 +#define SFLASH_AT_PAGE_ERASE 0x0281
10324 +#define SFLASH_AT_BLOCK_ERASE 0x0250
10325 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
10326 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
10327 +#define SFLASH_AT_BUF1_LOAD 0x0253
10328 +#define SFLASH_AT_BUF2_LOAD 0x0255
10329 +#define SFLASH_AT_BUF1_COMPARE 0x0260
10330 +#define SFLASH_AT_BUF2_COMPARE 0x0261
10331 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
10332 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
10333 +
10334 +/* Status register bits for Atmel flashes */
10335 +#define SFLASH_AT_READY 0x80
10336 +#define SFLASH_AT_MISMATCH 0x40
10337 +#define SFLASH_AT_ID_MASK 0x38
10338 +#define SFLASH_AT_ID_SHIFT 3
10339 +
10340 +#endif /* _SBCHIPC_H */
10341 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbconfig.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbconfig.h
10342 --- linux-2.6.12.5/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
10343 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbconfig.h 2005-08-28 11:12:20.469853224 +0200
10344 @@ -0,0 +1,296 @@
10345 +/*
10346 + * Broadcom SiliconBackplane hardware register definitions.
10347 + *
10348 + * Copyright 2001-2003, Broadcom Corporation
10349 + * All Rights Reserved.
10350 + *
10351 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10352 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10353 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10354 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10355 + * $Id$
10356 + */
10357 +
10358 +#ifndef _SBCONFIG_H
10359 +#define _SBCONFIG_H
10360 +
10361 +/* cpp contortions to concatenate w/arg prescan */
10362 +#ifndef PAD
10363 +#define _PADLINE(line) pad ## line
10364 +#define _XSTR(line) _PADLINE(line)
10365 +#define PAD _XSTR(__LINE__)
10366 +#endif
10367 +
10368 +/*
10369 + * SiliconBackplane Address Map.
10370 + * All regions may not exist on all chips.
10371 + */
10372 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
10373 +#define SB_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
10374 +#define SB_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
10375 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
10376 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
10377 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
10378 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
10379 +#define SB_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
10380 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
10381 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
10382 +
10383 +/* enumeration space related defs */
10384 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
10385 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
10386 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
10387 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
10388 +
10389 +/* mips address */
10390 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
10391 +
10392 +/*
10393 + * Sonics Configuration Space Registers.
10394 + */
10395 +#ifdef _LANGUAGE_ASSEMBLY
10396 +
10397 +#define SBIPSFLAG 0x08
10398 +#define SBTPSFLAG 0x18
10399 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
10400 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
10401 +#define SBADMATCH3 0x60
10402 +#define SBADMATCH2 0x68
10403 +#define SBADMATCH1 0x70
10404 +#define SBIMSTATE 0x90
10405 +#define SBINTVEC 0x94
10406 +#define SBTMSTATELOW 0x98
10407 +#define SBTMSTATEHIGH 0x9c
10408 +#define SBBWA0 0xa0
10409 +#define SBIMCONFIGLOW 0xa8
10410 +#define SBIMCONFIGHIGH 0xac
10411 +#define SBADMATCH0 0xb0
10412 +#define SBTMCONFIGLOW 0xb8
10413 +#define SBTMCONFIGHIGH 0xbc
10414 +#define SBBCONFIG 0xc0
10415 +#define SBBSTATE 0xc8
10416 +#define SBACTCNFG 0xd8
10417 +#define SBFLAGST 0xe8
10418 +#define SBIDLOW 0xf8
10419 +#define SBIDHIGH 0xfc
10420 +
10421 +
10422 +#else
10423 +
10424 +typedef volatile struct _sbconfig {
10425 + uint32 PAD[2];
10426 + uint32 sbipsflag; /* initiator port ocp slave flag */
10427 + uint32 PAD[3];
10428 + uint32 sbtpsflag; /* target port ocp slave flag */
10429 + uint32 PAD[11];
10430 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
10431 + uint32 PAD;
10432 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
10433 + uint32 PAD[3];
10434 + uint32 sbadmatch3; /* address match3 */
10435 + uint32 PAD;
10436 + uint32 sbadmatch2; /* address match2 */
10437 + uint32 PAD;
10438 + uint32 sbadmatch1; /* address match1 */
10439 + uint32 PAD[7];
10440 + uint32 sbimstate; /* initiator agent state */
10441 + uint32 sbintvec; /* interrupt mask */
10442 + uint32 sbtmstatelow; /* target state */
10443 + uint32 sbtmstatehigh; /* target state */
10444 + uint32 sbbwa0; /* bandwidth allocation table0 */
10445 + uint32 PAD;
10446 + uint32 sbimconfiglow; /* initiator configuration */
10447 + uint32 sbimconfighigh; /* initiator configuration */
10448 + uint32 sbadmatch0; /* address match0 */
10449 + uint32 PAD;
10450 + uint32 sbtmconfiglow; /* target configuration */
10451 + uint32 sbtmconfighigh; /* target configuration */
10452 + uint32 sbbconfig; /* broadcast configuration */
10453 + uint32 PAD;
10454 + uint32 sbbstate; /* broadcast state */
10455 + uint32 PAD[3];
10456 + uint32 sbactcnfg; /* activate configuration */
10457 + uint32 PAD[3];
10458 + uint32 sbflagst; /* current sbflags */
10459 + uint32 PAD[3];
10460 + uint32 sbidlow; /* identification */
10461 + uint32 sbidhigh; /* identification */
10462 +} sbconfig_t;
10463 +
10464 +#endif /* _LANGUAGE_ASSEMBLY */
10465 +
10466 +/* sbipsflag */
10467 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
10468 +#define SBIPS_INT1_SHIFT 0
10469 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
10470 +#define SBIPS_INT2_SHIFT 8
10471 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
10472 +#define SBIPS_INT3_SHIFT 16
10473 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
10474 +#define SBIPS_INT4_SHIFT 24
10475 +
10476 +/* sbtpsflag */
10477 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
10478 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
10479 +
10480 +/* sbtmerrlog */
10481 +#define SBTMEL_CM 0x00000007 /* command */
10482 +#define SBTMEL_CI 0x0000ff00 /* connection id */
10483 +#define SBTMEL_EC 0x0f000000 /* error code */
10484 +#define SBTMEL_ME 0x80000000 /* multiple error */
10485 +
10486 +/* sbimstate */
10487 +#define SBIM_PC 0xf /* pipecount */
10488 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
10489 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
10490 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
10491 +#define SBIM_AP_TK 0x20 /* use token only */
10492 +#define SBIM_AP_RSV 0x30 /* reserved */
10493 +#define SBIM_IBE 0x20000 /* inbanderror */
10494 +#define SBIM_TO 0x40000 /* timeout */
10495 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
10496 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
10497 +
10498 +/* sbtmstatelow */
10499 +#define SBTML_RESET 0x1 /* reset */
10500 +#define SBTML_REJ 0x2 /* reject */
10501 +#define SBTML_CLK 0x10000 /* clock enable */
10502 +#define SBTML_FGC 0x20000 /* force gated clocks on */
10503 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
10504 +#define SBTML_PE 0x40000000 /* pme enable */
10505 +#define SBTML_BE 0x80000000 /* bist enable */
10506 +
10507 +/* sbtmstatehigh */
10508 +#define SBTMH_SERR 0x1 /* serror */
10509 +#define SBTMH_INT 0x2 /* interrupt */
10510 +#define SBTMH_BUSY 0x4 /* busy */
10511 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
10512 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
10513 +#define SBTMH_GCR 0x20000000 /* gated clock request */
10514 +#define SBTMH_BISTF 0x40000000 /* bist failed */
10515 +#define SBTMH_BISTD 0x80000000 /* bist done */
10516 +
10517 +/* sbbwa0 */
10518 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
10519 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
10520 +#define SBBWA_TAB1_SHIFT 16
10521 +
10522 +/* sbimconfiglow */
10523 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
10524 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
10525 +#define SBIMCL_RTO_SHIFT 4
10526 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
10527 +#define SBIMCL_CID_SHIFT 16
10528 +
10529 +/* sbimconfighigh */
10530 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
10531 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
10532 +#define SBIMCH_TEM_SHIFT 4
10533 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
10534 +#define SBIMCH_BEM_SHIFT 6
10535 +
10536 +/* sbadmatch0 */
10537 +#define SBAM_TYPE_MASK 0x3 /* address type */
10538 +#define SBAM_AD64 0x4 /* reserved */
10539 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
10540 +#define SBAM_ADINT0_SHIFT 3
10541 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
10542 +#define SBAM_ADINT1_SHIFT 3
10543 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
10544 +#define SBAM_ADINT2_SHIFT 3
10545 +#define SBAM_ADEN 0x400 /* enable */
10546 +#define SBAM_ADNEG 0x800 /* negative decode */
10547 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
10548 +#define SBAM_BASE0_SHIFT 8
10549 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
10550 +#define SBAM_BASE1_SHIFT 12
10551 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
10552 +#define SBAM_BASE2_SHIFT 16
10553 +
10554 +/* sbtmconfiglow */
10555 +#define SBTMCL_CD_MASK 0xff /* clock divide */
10556 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
10557 +#define SBTMCL_CO_SHIFT 11
10558 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
10559 +#define SBTMCL_IF_SHIFT 18
10560 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
10561 +#define SBTMCL_IM_SHIFT 24
10562 +
10563 +/* sbtmconfighigh */
10564 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
10565 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
10566 +#define SBTMCH_RM_SHIFT 2
10567 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
10568 +#define SBTMCH_SM_SHIFT 4
10569 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
10570 +#define SBTMCH_EM_SHIFT 8
10571 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
10572 +#define SBTMCH_IM_SHIFT 10
10573 +
10574 +/* sbbconfig */
10575 +#define SBBC_LAT_MASK 0x3 /* sb latency */
10576 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
10577 +#define SBBC_MAX0_SHIFT 16
10578 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
10579 +#define SBBC_MAX1_SHIFT 20
10580 +
10581 +/* sbbstate */
10582 +#define SBBS_SRD 0x1 /* st reg disable */
10583 +#define SBBS_HRD 0x2 /* hold reg disable */
10584 +
10585 +/* sbidlow */
10586 +#define SBIDL_CS_MASK 0x3 /* config space */
10587 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
10588 +#define SBIDL_AR_SHIFT 3
10589 +#define SBIDL_SYNCH 0x40 /* sync */
10590 +#define SBIDL_INIT 0x80 /* initiator */
10591 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
10592 +#define SBIDL_MINLAT_SHIFT 8
10593 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
10594 +#define SBIDL_MAXLAT_SHIFT 12
10595 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
10596 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
10597 +#define SBIDL_CW_SHIFT 18
10598 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
10599 +#define SBIDL_TP_SHIFT 20
10600 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
10601 +#define SBIDL_IP_SHIFT 24
10602 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
10603 +#define SBIDL_RV_SHIFT 28
10604 +
10605 +/* sbidhigh */
10606 +#define SBIDH_RC_MASK 0xf /* revision code*/
10607 +#define SBIDH_CC_MASK 0xfff0 /* core code */
10608 +#define SBIDH_CC_SHIFT 4
10609 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
10610 +#define SBIDH_VC_SHIFT 16
10611 +
10612 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
10613 +
10614 +/* vendor codes */
10615 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
10616 +
10617 +/* core codes */
10618 +#define SB_CC 0x800 /* chipcommon core */
10619 +#define SB_ILINE20 0x801 /* iline20 core */
10620 +#define SB_SDRAM 0x803 /* sdram core */
10621 +#define SB_PCI 0x804 /* pci core */
10622 +#define SB_MIPS 0x805 /* mips core */
10623 +#define SB_ENET 0x806 /* enet mac core */
10624 +#define SB_CODEC 0x807 /* v90 codec core */
10625 +#define SB_USB 0x808 /* usb 1.1 host/device core */
10626 +#define SB_ILINE100 0x80a /* iline100 core */
10627 +#define SB_IPSEC 0x80b /* ipsec core */
10628 +#define SB_PCMCIA 0x80d /* pcmcia core */
10629 +#define SB_MEMC 0x80f /* memc sdram core */
10630 +#define SB_EXTIF 0x811 /* external interface core */
10631 +#define SB_D11 0x812 /* 802.11 MAC core */
10632 +#define SB_MIPS33 0x816 /* mips3302 core */
10633 +#define SB_USB11H 0x817 /* usb 1.1 host core */
10634 +#define SB_USB11D 0x818 /* usb 1.1 device core */
10635 +#define SB_USB20H 0x819 /* usb 2.0 host core */
10636 +#define SB_USB20D 0x81A /* usb 2.0 device core */
10637 +#define SB_SDIOH 0x81B /* sdio host core */
10638 +#define SB_ROBO 0x81C /* robo switch core */
10639 +
10640 +#endif /* _SBCONFIG_H */
10641 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbextif.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbextif.h
10642 --- linux-2.6.12.5/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
10643 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbextif.h 2005-08-28 11:12:20.470853072 +0200
10644 @@ -0,0 +1,242 @@
10645 +/*
10646 + * Hardware-specific External Interface I/O core definitions
10647 + * for the BCM47xx family of SiliconBackplane-based chips.
10648 + *
10649 + * The External Interface core supports a total of three external chip selects
10650 + * supporting external interfaces. One of the external chip selects is
10651 + * used for Flash, one is used for PCMCIA, and the other may be
10652 + * programmed to support either a synchronous interface or an
10653 + * asynchronous interface. The asynchronous interface can be used to
10654 + * support external devices such as UARTs and the BCM2019 Bluetooth
10655 + * baseband processor.
10656 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
10657 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
10658 + *
10659 + * Copyright 2001-2003, Broadcom Corporation
10660 + * All Rights Reserved.
10661 + *
10662 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10663 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10664 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10665 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10666 + * $Id$
10667 + */
10668 +
10669 +#ifndef _SBEXTIF_H
10670 +#define _SBEXTIF_H
10671 +
10672 +/* external interface address space */
10673 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
10674 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
10675 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
10676 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
10677 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
10678 +
10679 +/* cpp contortions to concatenate w/arg prescan */
10680 +#ifndef PAD
10681 +#define _PADLINE(line) pad ## line
10682 +#define _XSTR(line) _PADLINE(line)
10683 +#define PAD _XSTR(__LINE__)
10684 +#endif /* PAD */
10685 +
10686 +/*
10687 + * The multiple instances of output and output enable registers
10688 + * are present to allow driver software for multiple cores to control
10689 + * gpio outputs without needing to share a single register pair.
10690 + */
10691 +struct gpiouser {
10692 + uint32 out;
10693 + uint32 outen;
10694 +};
10695 +#define NGPIOUSER 5
10696 +
10697 +typedef volatile struct {
10698 + uint32 corecontrol;
10699 + uint32 extstatus;
10700 + uint32 PAD[2];
10701 +
10702 + /* pcmcia control registers */
10703 + uint32 pcmcia_config;
10704 + uint32 pcmcia_memwait;
10705 + uint32 pcmcia_attrwait;
10706 + uint32 pcmcia_iowait;
10707 +
10708 + /* programmable interface control registers */
10709 + uint32 prog_config;
10710 + uint32 prog_waitcount;
10711 +
10712 + /* flash control registers */
10713 + uint32 flash_config;
10714 + uint32 flash_waitcount;
10715 + uint32 PAD[4];
10716 +
10717 + uint32 watchdog;
10718 +
10719 + /* clock control */
10720 + uint32 clockcontrol_n;
10721 + uint32 clockcontrol_sb;
10722 + uint32 clockcontrol_pci;
10723 + uint32 clockcontrol_mii;
10724 + uint32 PAD[3];
10725 +
10726 + /* gpio */
10727 + uint32 gpioin;
10728 + struct gpiouser gpio[NGPIOUSER];
10729 + uint32 PAD;
10730 + uint32 ejtagouten;
10731 + uint32 gpiointpolarity;
10732 + uint32 gpiointmask;
10733 + uint32 PAD[153];
10734 +
10735 + uint8 uartdata;
10736 + uint8 PAD[3];
10737 + uint8 uartimer;
10738 + uint8 PAD[3];
10739 + uint8 uartfcr;
10740 + uint8 PAD[3];
10741 + uint8 uartlcr;
10742 + uint8 PAD[3];
10743 + uint8 uartmcr;
10744 + uint8 PAD[3];
10745 + uint8 uartlsr;
10746 + uint8 PAD[3];
10747 + uint8 uartmsr;
10748 + uint8 PAD[3];
10749 + uint8 uartscratch;
10750 + uint8 PAD[3];
10751 +} extifregs_t;
10752 +
10753 +/* corecontrol */
10754 +#define CC_UE (1 << 0) /* uart enable */
10755 +
10756 +/* extstatus */
10757 +#define ES_EM (1 << 0) /* endian mode (ro) */
10758 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
10759 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
10760 +
10761 +/* gpio bit mask */
10762 +#define GPIO_BIT0 (1 << 0)
10763 +#define GPIO_BIT1 (1 << 1)
10764 +#define GPIO_BIT2 (1 << 2)
10765 +#define GPIO_BIT3 (1 << 3)
10766 +#define GPIO_BIT4 (1 << 4)
10767 +#define GPIO_BIT5 (1 << 5)
10768 +#define GPIO_BIT6 (1 << 6)
10769 +#define GPIO_BIT7 (1 << 7)
10770 +
10771 +
10772 +/* pcmcia/prog/flash_config */
10773 +#define CF_EN (1 << 0) /* enable */
10774 +#define CF_EM_MASK 0xe /* mode */
10775 +#define CF_EM_SHIFT 1
10776 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
10777 +#define CF_EM_SYNC 0x2 /* synchronous mode */
10778 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
10779 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
10780 +#define CF_BS (1 << 5) /* byteswap */
10781 +#define CF_CD_MASK 0xc0 /* clock divider */
10782 +#define CF_CD_SHIFT 6
10783 +#define CF_CD_DIV2 0x0 /* backplane/2 */
10784 +#define CF_CD_DIV3 0x40 /* backplane/3 */
10785 +#define CF_CD_DIV4 0x80 /* backplane/4 */
10786 +#define CF_CE (1 << 8) /* clock enable */
10787 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
10788 +
10789 +/* pcmcia_memwait */
10790 +#define PM_W0_MASK 0x3f /* waitcount0 */
10791 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
10792 +#define PM_W1_SHIFT 8
10793 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
10794 +#define PM_W2_SHIFT 16
10795 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
10796 +#define PM_W3_SHIFT 24
10797 +
10798 +/* pcmcia_attrwait */
10799 +#define PA_W0_MASK 0x3f /* waitcount0 */
10800 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
10801 +#define PA_W1_SHIFT 8
10802 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
10803 +#define PA_W2_SHIFT 16
10804 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
10805 +#define PA_W3_SHIFT 24
10806 +
10807 +/* pcmcia_iowait */
10808 +#define PI_W0_MASK 0x3f /* waitcount0 */
10809 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
10810 +#define PI_W1_SHIFT 8
10811 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
10812 +#define PI_W2_SHIFT 16
10813 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
10814 +#define PI_W3_SHIFT 24
10815 +
10816 +/* prog_waitcount */
10817 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
10818 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
10819 +#define PW_W1_SHIFT 8
10820 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
10821 +#define PW_W2_SHIFT 16
10822 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
10823 +#define PW_W3_SHIFT 24
10824 +
10825 +#define PW_W0 0x0000000c
10826 +#define PW_W1 0x00000a00
10827 +#define PW_W2 0x00020000
10828 +#define PW_W3 0x01000000
10829 +
10830 +/* flash_waitcount */
10831 +#define FW_W0_MASK 0x1f /* waitcount0 */
10832 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
10833 +#define FW_W1_SHIFT 8
10834 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
10835 +#define FW_W2_SHIFT 16
10836 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
10837 +#define FW_W3_SHIFT 24
10838 +
10839 +/* watchdog */
10840 +#define WATCHDOG_CLOCK 48000000 /* Hz */
10841 +
10842 +/* clockcontrol_n */
10843 +#define CN_N1_MASK 0x3f /* n1 control */
10844 +#define CN_N2_MASK 0x3f00 /* n2 control */
10845 +#define CN_N2_SHIFT 8
10846 +
10847 +/* clockcontrol_sb/pci/mii */
10848 +#define CC_M1_MASK 0x3f /* m1 control */
10849 +#define CC_M2_MASK 0x3f00 /* m2 control */
10850 +#define CC_M2_SHIFT 8
10851 +#define CC_M3_MASK 0x3f0000 /* m3 control */
10852 +#define CC_M3_SHIFT 16
10853 +#define CC_MC_MASK 0x1f000000 /* mux control */
10854 +#define CC_MC_SHIFT 24
10855 +
10856 +/* Clock control default values */
10857 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
10858 +#define CC_DEF_100 0x04020011
10859 +#define CC_DEF_33 0x11030011
10860 +#define CC_DEF_25 0x11050011
10861 +
10862 +/* Clock control values for 125Mhz */
10863 +#define CC_125_N 0x0802
10864 +#define CC_125_M 0x04020009
10865 +#define CC_125_M25 0x11090009
10866 +#define CC_125_M33 0x11090005
10867 +
10868 +/* Clock control magic field values */
10869 +#define CC_F6_2 0x02 /* A factor of 2 in */
10870 +#define CC_F6_3 0x03 /* 6-bit fields like */
10871 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
10872 +#define CC_F6_5 0x09
10873 +#define CC_F6_6 0x11
10874 +#define CC_F6_7 0x21
10875 +
10876 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
10877 +
10878 +#define CC_MC_BYPASS 0x08
10879 +#define CC_MC_M1 0x04
10880 +#define CC_MC_M1M2 0x02
10881 +#define CC_MC_M1M2M3 0x01
10882 +#define CC_MC_M1M3 0x11
10883 +
10884 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
10885 +
10886 +#endif /* _SBEXTIF_H */
10887 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbmemc.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbmemc.h
10888 --- linux-2.6.12.5/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
10889 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbmemc.h 2005-08-28 11:12:20.471852920 +0200
10890 @@ -0,0 +1,144 @@
10891 +/*
10892 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
10893 + *
10894 + * Copyright 2001-2003, Broadcom Corporation
10895 + * All Rights Reserved.
10896 + *
10897 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10898 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10899 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10900 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10901 + * $Id$
10902 + */
10903 +
10904 +#ifndef _SBMEMC_H
10905 +#define _SBMEMC_H
10906 +
10907 +#ifdef _LANGUAGE_ASSEMBLY
10908 +
10909 +#define MEMC_CONTROL 0x00
10910 +#define MEMC_CONFIG 0x04
10911 +#define MEMC_REFRESH 0x08
10912 +#define MEMC_BISTSTAT 0x0c
10913 +#define MEMC_MODEBUF 0x10
10914 +#define MEMC_BKCLS 0x14
10915 +#define MEMC_PRIORINV 0x18
10916 +#define MEMC_DRAMTIM 0x1c
10917 +#define MEMC_INTSTAT 0x20
10918 +#define MEMC_INTMASK 0x24
10919 +#define MEMC_INTINFO 0x28
10920 +#define MEMC_NCDLCTL 0x30
10921 +#define MEMC_RDNCDLCOR 0x34
10922 +#define MEMC_WRNCDLCOR 0x38
10923 +#define MEMC_MISCDLYCTL 0x3c
10924 +#define MEMC_DQSGATENCDL 0x40
10925 +#define MEMC_SPARE 0x44
10926 +#define MEMC_TPADDR 0x48
10927 +#define MEMC_TPDATA 0x4c
10928 +#define MEMC_BARRIER 0x50
10929 +#define MEMC_CORE 0x54
10930 +
10931 +
10932 +#else
10933 +
10934 +/* Sonics side: MEMC core registers */
10935 +typedef volatile struct sbmemcregs {
10936 + uint32 control;
10937 + uint32 config;
10938 + uint32 refresh;
10939 + uint32 biststat;
10940 + uint32 modebuf;
10941 + uint32 bkcls;
10942 + uint32 priorinv;
10943 + uint32 dramtim;
10944 + uint32 intstat;
10945 + uint32 intmask;
10946 + uint32 intinfo;
10947 + uint32 reserved1;
10948 + uint32 ncdlctl;
10949 + uint32 rdncdlcor;
10950 + uint32 wrncdlcor;
10951 + uint32 miscdlyctl;
10952 + uint32 dqsgatencdl;
10953 + uint32 spare;
10954 + uint32 tpaddr;
10955 + uint32 tpdata;
10956 + uint32 barrier;
10957 + uint32 core;
10958 +} sbmemcregs_t;
10959 +
10960 +#endif
10961 +
10962 +/* MEMC Core Init values (OCP ID 0x80f) */
10963 +
10964 +/* For sdr: */
10965 +#define MEMC_SD_CONFIG_INIT 0x00048000
10966 +#define MEMC_SD_DRAMTIM_INIT 0x000754da
10967 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
10968 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
10969 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
10970 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
10971 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
10972 +#define MEMC_SD_CONTROL_INIT0 0x00000002
10973 +#define MEMC_SD_CONTROL_INIT1 0x00000008
10974 +#define MEMC_SD_CONTROL_INIT2 0x00000004
10975 +#define MEMC_SD_CONTROL_INIT3 0x00000010
10976 +#define MEMC_SD_CONTROL_INIT4 0x00000001
10977 +#define MEMC_SD_MODEBUF_INIT 0x00000000
10978 +#define MEMC_SD_REFRESH_INIT 0x0000840f
10979 +
10980 +
10981 +/* This is for SDRM8X8X4 */
10982 +#define MEMC_SDR_INIT 0x0008
10983 +#define MEMC_SDR_MODE 0x32
10984 +#define MEMC_SDR_NCDL 0x00020032
10985 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
10986 +
10987 +/* For ddr: */
10988 +#define MEMC_CONFIG_INIT 0x00048000
10989 +#define MEMC_DRAMTIM_INIT 0x000754d9
10990 +#define MEMC_RDNCDLCOR_INIT 0x00000000
10991 +#define MEMC_WRNCDLCOR_INIT 0x49351200
10992 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
10993 +#define MEMC_DQSGATENCDL_INIT 0x00030000
10994 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
10995 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
10996 +#define MEMC_NCDLCTL_INIT 0x00002001
10997 +#define MEMC_CONTROL_INIT0 0x00000002
10998 +#define MEMC_CONTROL_INIT1 0x00000008
10999 +#define MEMC_MODEBUF_INIT0 0x00004000
11000 +#define MEMC_CONTROL_INIT2 0x00000010
11001 +#define MEMC_MODEBUF_INIT1 0x00000100
11002 +#define MEMC_CONTROL_INIT3 0x00000010
11003 +#define MEMC_CONTROL_INIT4 0x00000008
11004 +#define MEMC_REFRESH_INIT 0x0000840f
11005 +#define MEMC_CONTROL_INIT5 0x00000004
11006 +#define MEMC_MODEBUF_INIT2 0x00000000
11007 +#define MEMC_CONTROL_INIT6 0x00000010
11008 +#define MEMC_CONTROL_INIT7 0x00000001
11009 +
11010 +
11011 +/* This is for DDRM16X16X2 */
11012 +#define MEMC_DDR_INIT 0x0009
11013 +#define MEMC_DDR_MODE 0x62
11014 +#define MEMC_DDR_NCDL 0x0005050a
11015 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
11016 +
11017 +/* mask for sdr/ddr calibration registers */
11018 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
11019 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
11020 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
11021 +
11022 +/* masks for miscdlyctl registers */
11023 +#define MEMC_MISC_SM_MASK 0x30000000
11024 +#define MEMC_MISC_SM_SHIFT 28
11025 +#define MEMC_MISC_SD_MASK 0x0f000000
11026 +#define MEMC_MISC_SD_SHIFT 24
11027 +
11028 +/* hw threshhold for calculating wr/rd for sdr memc */
11029 +#define MEMC_CD_THRESHOLD 128
11030 +
11031 +/* Low bit of init register says if memc is ddr or sdr */
11032 +#define MEMC_CONFIG_DDR 0x00000001
11033 +
11034 +#endif /* _SBMEMC_H */
11035 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbmips.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbmips.h
11036 --- linux-2.6.12.5/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
11037 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbmips.h 2005-08-28 11:12:20.471852920 +0200
11038 @@ -0,0 +1,56 @@
11039 +/*
11040 + * Broadcom SiliconBackplane MIPS definitions
11041 + *
11042 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
11043 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
11044 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
11045 + * interface. The core revision is stored in the SB ID register in SB
11046 + * configuration space.
11047 + *
11048 + * Copyright 2001-2003, Broadcom Corporation
11049 + * All Rights Reserved.
11050 + *
11051 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11052 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11053 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11054 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11055 + *
11056 + * $Id$
11057 + */
11058 +
11059 +#ifndef _SBMIPS_H
11060 +#define _SBMIPS_H
11061 +
11062 +#ifndef _LANGUAGE_ASSEMBLY
11063 +
11064 +/* cpp contortions to concatenate w/arg prescan */
11065 +#ifndef PAD
11066 +#define _PADLINE(line) pad ## line
11067 +#define _XSTR(line) _PADLINE(line)
11068 +#define PAD _XSTR(__LINE__)
11069 +#endif /* PAD */
11070 +
11071 +typedef volatile struct {
11072 + uint32 corecontrol;
11073 + uint32 PAD[2];
11074 + uint32 biststatus;
11075 + uint32 PAD[4];
11076 + uint32 intstatus;
11077 + uint32 intmask;
11078 + uint32 timer;
11079 +} mipsregs_t;
11080 +
11081 +extern uint32 sb_flag(void *sbh);
11082 +extern uint sb_irq(void *sbh);
11083 +
11084 +extern void sb_serial_init(void *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
11085 +
11086 +extern void sb_mips_init(void *sbh);
11087 +extern uint32 sb_mips_clock(void *sbh);
11088 +extern bool sb_mips_setclock(void *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
11089 +
11090 +extern uint32 sb_memc_get_ncdl(void *sbh);
11091 +
11092 +#endif /* _LANGUAGE_ASSEMBLY */
11093 +
11094 +#endif /* _SBMIPS_H */
11095 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbpci.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbpci.h
11096 --- linux-2.6.12.5/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
11097 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbpci.h 2005-08-28 11:12:20.471852920 +0200
11098 @@ -0,0 +1,113 @@
11099 +/*
11100 + * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
11101 + *
11102 + * $Id$
11103 + * Copyright 2001-2003, Broadcom Corporation
11104 + * All Rights Reserved.
11105 + *
11106 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11107 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11108 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11109 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11110 + */
11111 +
11112 +#ifndef _SBPCI_H
11113 +#define _SBPCI_H
11114 +
11115 +/* cpp contortions to concatenate w/arg prescan */
11116 +#ifndef PAD
11117 +#define _PADLINE(line) pad ## line
11118 +#define _XSTR(line) _PADLINE(line)
11119 +#define PAD _XSTR(__LINE__)
11120 +#endif
11121 +
11122 +/* Sonics side: PCI core and host control registers */
11123 +typedef struct sbpciregs {
11124 + uint32 control; /* PCI control */
11125 + uint32 PAD[3];
11126 + uint32 arbcontrol; /* PCI arbiter control */
11127 + uint32 PAD[3];
11128 + uint32 intstatus; /* Interrupt status */
11129 + uint32 intmask; /* Interrupt mask */
11130 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
11131 + uint32 PAD[9];
11132 + uint32 bcastaddr; /* Sonics broadcast address */
11133 + uint32 bcastdata; /* Sonics broadcast data */
11134 + uint32 PAD[2];
11135 + uint32 gpioin; /* ro: gpio input (>=rev2) */
11136 + uint32 gpioout; /* rw: gpio output (>=rev2) */
11137 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
11138 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
11139 + uint32 PAD[36];
11140 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
11141 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
11142 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
11143 + uint32 PAD[445];
11144 + uint16 sprom[36]; /* SPROM shadow Area */
11145 + uint32 PAD[46];
11146 +} sbpciregs_t;
11147 +
11148 +/* PCI control */
11149 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
11150 +#define PCI_RST 0x02 /* Value driven out to pin */
11151 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
11152 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
11153 +
11154 +/* PCI arbiter control */
11155 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
11156 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
11157 +#define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
11158 +#define PCI_PARKID_SHIFT 1
11159 +#define PCI_PARKID_LAST 0 /* Last requestor */
11160 +#define PCI_PARKID_4710 1 /* 4710 */
11161 +#define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
11162 +#define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
11163 +
11164 +/* Interrupt status/mask */
11165 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
11166 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
11167 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
11168 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
11169 +#define PCI_PME 0x10 /* PCI PME# is asserted */
11170 +
11171 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
11172 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
11173 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
11174 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
11175 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
11176 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
11177 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
11178 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
11179 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
11180 +
11181 +/* Sonics broadcast address */
11182 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
11183 +
11184 +/* Sonics to PCI translation types */
11185 +#define SBTOPCI0_MASK 0xfc000000
11186 +#define SBTOPCI1_MASK 0xfc000000
11187 +#define SBTOPCI2_MASK 0xc0000000
11188 +#define SBTOPCI_MEM 0
11189 +#define SBTOPCI_IO 1
11190 +#define SBTOPCI_CFG0 2
11191 +#define SBTOPCI_CFG1 3
11192 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
11193 +#define SBTOPCI_BURST 0x8 /* burst enable */
11194 +
11195 +/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
11196 +#define cap_list rsvd_a[0]
11197 +#define bar0_window dev_dep[0x80 - 0x40]
11198 +#define bar1_window dev_dep[0x84 - 0x40]
11199 +#define sprom_control dev_dep[0x88 - 0x40]
11200 +
11201 +#ifndef _LANGUAGE_ASSEMBLY
11202 +
11203 +extern int sbpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
11204 +extern int sbpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
11205 +extern void sbpci_ban(uint16 core);
11206 +extern int sbpci_init(void *sbh);
11207 +extern void sbpci_check(void *sbh);
11208 +
11209 +#endif /* !_LANGUAGE_ASSEMBLY */
11210 +
11211 +#endif /* _SBPCI_H */
11212 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbpcmcia.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbpcmcia.h
11213 --- linux-2.6.12.5/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
11214 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbpcmcia.h 2005-08-28 11:12:20.472852768 +0200
11215 @@ -0,0 +1,131 @@
11216 +/*
11217 + * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
11218 + *
11219 + * $Id$
11220 + * Copyright 2001-2003, Broadcom Corporation
11221 + * All Rights Reserved.
11222 + *
11223 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11224 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11225 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11226 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11227 + */
11228 +
11229 +#ifndef _SBPCMCIA_H
11230 +#define _SBPCMCIA_H
11231 +
11232 +
11233 +/* All the addresses that are offsets in attribute space are divided
11234 + * by two to account for the fact that odd bytes are invalid in
11235 + * attribute space and our read/write routines make the space appear
11236 + * as if they didn't exist. Still we want to show the original numbers
11237 + * as documented in the hnd_pcmcia core manual.
11238 + */
11239 +
11240 +/* PCMCIA Function Configuration Registers */
11241 +#define PCMCIA_FCR (0x700 / 2)
11242 +
11243 +#define FCR0_OFF 0
11244 +#define FCR1_OFF (0x40 / 2)
11245 +#define FCR2_OFF (0x80 / 2)
11246 +#define FCR3_OFF (0xc0 / 2)
11247 +
11248 +#define PCMCIA_FCR0 (0x700 / 2)
11249 +#define PCMCIA_FCR1 (0x740 / 2)
11250 +#define PCMCIA_FCR2 (0x780 / 2)
11251 +#define PCMCIA_FCR3 (0x7c0 / 2)
11252 +
11253 +/* Standard PCMCIA FCR registers */
11254 +
11255 +#define PCMCIA_COR 0
11256 +
11257 +#define COR_RST 0x80
11258 +#define COR_LEV 0x40
11259 +#define COR_IRQEN 0x04
11260 +#define COR_BLREN 0x01
11261 +#define COR_FUNEN 0x01
11262 +
11263 +
11264 +#define PCICIA_FCSR (2 / 2)
11265 +#define PCICIA_PRR (4 / 2)
11266 +#define PCICIA_SCR (6 / 2)
11267 +#define PCICIA_ESR (8 / 2)
11268 +
11269 +
11270 +#define PCM_MEMOFF 0x0000
11271 +#define F0_MEMOFF 0x1000
11272 +#define F1_MEMOFF 0x2000
11273 +#define F2_MEMOFF 0x3000
11274 +#define F3_MEMOFF 0x4000
11275 +
11276 +/* Memory base in the function fcr's */
11277 +#define MEM_ADDR0 (0x728 / 2)
11278 +#define MEM_ADDR1 (0x72a / 2)
11279 +#define MEM_ADDR2 (0x72c / 2)
11280 +
11281 +/* PCMCIA base plus Srom access in fcr0: */
11282 +#define PCMCIA_ADDR0 (0x072e / 2)
11283 +#define PCMCIA_ADDR1 (0x0730 / 2)
11284 +#define PCMCIA_ADDR2 (0x0732 / 2)
11285 +
11286 +#define MEM_SEG (0x0734 / 2)
11287 +#define SROM_CS (0x0736 / 2)
11288 +#define SROM_DATAL (0x0738 / 2)
11289 +#define SROM_DATAH (0x073a / 2)
11290 +#define SROM_ADDRL (0x073c / 2)
11291 +#define SROM_ADDRH (0x073e / 2)
11292 +
11293 +/* Values for srom_cs: */
11294 +#define SROM_IDLE 0
11295 +#define SROM_WRITE 1
11296 +#define SROM_READ 2
11297 +#define SROM_WEN 4
11298 +#define SROM_WDS 7
11299 +#define SROM_DONE 8
11300 +
11301 +/* CIS stuff */
11302 +
11303 +/* The CIS stops where the FCRs start */
11304 +#define CIS_SIZE PCMCIA_FCR
11305 +
11306 +/* Standard tuples we know about */
11307 +
11308 +#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
11309 +#define CISTPL_FUNCE 0x22 /* Function extensions */
11310 +#define CISTPL_CFTABLE 0x1b /* Config table entry */
11311 +
11312 +/* Function extensions for LANs */
11313 +
11314 +#define LAN_TECH 1 /* Technology type */
11315 +#define LAN_SPEED 2 /* Raw bit rate */
11316 +#define LAN_MEDIA 3 /* Transmission media */
11317 +#define LAN_NID 4 /* Node identification (aka MAC addr) */
11318 +#define LAN_CONN 5 /* Connector standard */
11319 +
11320 +
11321 +/* CFTable */
11322 +#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
11323 +#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
11324 +#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
11325 +
11326 +/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
11327 + * take one for HNBU, and use "extensions" (a la FUNCE) within it.
11328 + */
11329 +
11330 +#define CISTPL_BRCM_HNBU 0x80
11331 +
11332 +/* Subtypes of BRCM_HNBU: */
11333 +
11334 +#define HNBU_CHIPID 0x01 /* Six bytes with PCI vendor &
11335 + * device id and chiprev
11336 + */
11337 +#define HNBU_BOARDREV 0x02 /* Two bytes board revision */
11338 +#define HNBU_PAPARMS 0x03 /* Eleven bytes PA parameters */
11339 +#define HNBU_OEM 0x04 /* Eight bytes OEM data */
11340 +#define HNBU_CC 0x05 /* Default country code */
11341 +#define HNBU_AA 0x06 /* Antennas available */
11342 +#define HNBU_AG 0x07 /* Antenna gain */
11343 +#define HNBU_BOARDFLAGS 0x08 /* board flags */
11344 +#define HNBU_LED 0x09 /* LED set */
11345 +
11346 +#endif /* _SBPCMCIA_H */
11347 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbsdram.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbsdram.h
11348 --- linux-2.6.12.5/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
11349 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbsdram.h 2005-08-28 11:12:20.472852768 +0200
11350 @@ -0,0 +1,75 @@
11351 +/*
11352 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
11353 + *
11354 + * Copyright 2001-2003, Broadcom Corporation
11355 + * All Rights Reserved.
11356 + *
11357 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11358 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11359 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11360 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11361 + * $Id$
11362 + */
11363 +
11364 +#ifndef _SBSDRAM_H
11365 +#define _SBSDRAM_H
11366 +
11367 +#ifndef _LANGUAGE_ASSEMBLY
11368 +
11369 +/* Sonics side: SDRAM core registers */
11370 +typedef volatile struct sbsdramregs {
11371 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
11372 + uint32 config; /* Initializes external SDRAM mode register */
11373 + uint32 refresh; /* Controls external SDRAM refresh rate */
11374 + uint32 pad1;
11375 + uint32 pad2;
11376 +} sbsdramregs_t;
11377 +
11378 +#endif
11379 +
11380 +/* SDRAM initialization control (initcontrol) register bits */
11381 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
11382 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
11383 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
11384 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
11385 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
11386 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
11387 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
11388 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
11389 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
11390 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
11391 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
11392 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
11393 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
11394 +
11395 +/* SDRAM configuration (config) register bits */
11396 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
11397 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
11398 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
11399 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
11400 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
11401 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
11402 +
11403 +/* SDRAM refresh control (refresh) register bits */
11404 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
11405 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
11406 +
11407 +/* SDRAM Core default Init values (OCP ID 0x803) */
11408 +#define SDRAM_INIT MEM4MX16X2
11409 +#define SDRAM_CONFIG SDRAM_BURSTFULL
11410 +#define SDRAM_REFRESH SDRAM_REF(0x40)
11411 +
11412 +#define MEM1MX16 0x009 /* 2 MB */
11413 +#define MEM1MX16X2 0x409 /* 4 MB */
11414 +#define MEM2MX8X2 0x809 /* 4 MB */
11415 +#define MEM2MX8X4 0xc09 /* 8 MB */
11416 +#define MEM2MX32 0x439 /* 8 MB */
11417 +#define MEM4MX16 0x019 /* 8 MB */
11418 +#define MEM4MX16X2 0x419 /* 16 MB */
11419 +#define MEM8MX8X2 0x819 /* 16 MB */
11420 +#define MEM8MX16 0x829 /* 16 MB */
11421 +#define MEM4MX32 0x429 /* 16 MB */
11422 +#define MEM8MX8X4 0xc19 /* 32 MB */
11423 +#define MEM8MX16X2 0xc29 /* 32 MB */
11424 +
11425 +#endif /* _SBSDRAM_H */
11426 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbutils.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbutils.h
11427 --- linux-2.6.12.5/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
11428 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbutils.h 2005-08-28 11:12:20.473852616 +0200
11429 @@ -0,0 +1,90 @@
11430 +/*
11431 + * Misc utility routines for accessing chip-specific features
11432 + * of Broadcom HNBU SiliconBackplane-based chips.
11433 + *
11434 + * Copyright 2001-2003, Broadcom Corporation
11435 + * All Rights Reserved.
11436 + *
11437 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11438 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11439 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11440 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11441 + *
11442 + * $Id$
11443 + */
11444 +
11445 +#ifndef _sbutils_h_
11446 +#define _sbutils_h_
11447 +
11448 +/* Board styles (bustype) */
11449 +#define BOARDSTYLE_SOC 0 /* Silicon Backplane */
11450 +#define BOARDSTYLE_PCI 1 /* PCI/MiniPCI board */
11451 +#define BOARDSTYLE_PCMCIA 2 /* PCMCIA board */
11452 +#define BOARDSTYLE_CARDBUS 3 /* Cardbus board */
11453 +
11454 +/*
11455 + * Many of the routines below take an 'sbh' handle as their first arg.
11456 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
11457 + * At any one time, the sbh is logically focused on one particular sb core
11458 + * (the "current core").
11459 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
11460 + */
11461 +
11462 +/* exported externs */
11463 +extern void *sb_attach(uint pcidev, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
11464 +extern void *sb_kattach(void);
11465 +extern void sb_detach(void *sbh);
11466 +extern uint sb_chip(void *sbh);
11467 +extern uint sb_chiprev(void *sbh);
11468 +extern uint sb_chippkg(void *sbh);
11469 +extern uint sb_boardvendor(void *sbh);
11470 +extern uint sb_boardtype(void *sbh);
11471 +extern uint sb_boardstyle(void *sbh);
11472 +extern uint sb_bus(void *sbh);
11473 +extern uint sb_corelist(void *sbh, uint coreid[]);
11474 +extern uint sb_coreid(void *sbh);
11475 +extern uint sb_coreidx(void *sbh);
11476 +extern uint sb_coreunit(void *sbh);
11477 +extern uint sb_corevendor(void *sbh);
11478 +extern uint sb_corerev(void *sbh);
11479 +extern void *sb_coreregs(void *sbh);
11480 +extern uint32 sb_coreflags(void *sbh, uint32 mask, uint32 val);
11481 +extern uint32 sb_coreflagshi(void *sbh, uint32 mask, uint32 val);
11482 +extern bool sb_iscoreup(void *sbh);
11483 +extern void *sb_setcoreidx(void *sbh, uint coreidx);
11484 +extern void *sb_setcore(void *sbh, uint coreid, uint coreunit);
11485 +extern void sb_commit(void *sbh);
11486 +extern uint32 sb_base(uint32 admatch);
11487 +extern uint32 sb_size(uint32 admatch);
11488 +extern void sb_core_reset(void *sbh, uint32 bits);
11489 +extern void sb_core_tofixup(void *sbh);
11490 +extern void sb_core_disable(void *sbh, uint32 bits);
11491 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
11492 +extern uint32 sb_clock(void *sbh);
11493 +extern void sb_pci_setup(void *sbh, uint32 *dmaoffset, uint coremask);
11494 +extern void sb_pcmcia_init(void *sbh);
11495 +extern void sb_watchdog(void *sbh, uint ticks);
11496 +extern void *sb_gpiosetcore(void *sbh);
11497 +extern uint32 sb_gpiocontrol(void *sbh, uint32 mask, uint32 val);
11498 +extern uint32 sb_gpioouten(void *sbh, uint32 mask, uint32 val);
11499 +extern uint32 sb_gpioout(void *sbh, uint32 mask, uint32 val);
11500 +extern uint32 sb_gpioin(void *sbh);
11501 +extern uint32 sb_gpiointpolarity(void *sbh, uint32 mask, uint32 val);
11502 +extern uint32 sb_gpiointmask(void *sbh, uint32 mask, uint32 val);
11503 +extern bool sb_taclear(void *sbh);
11504 +extern void sb_pwrctl_init(void *sbh);
11505 +extern uint16 sb_pwrctl_fast_pwrup_delay(void *sbh);
11506 +extern bool sb_pwrctl_clk(void *sbh, uint mode);
11507 +extern int sb_pwrctl_xtal(void *sbh, uint what, bool on);
11508 +extern void sb_register_intr_callback(void *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intr_arg);
11509 +
11510 +/* pwrctl xtal what flags */
11511 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
11512 +#define PLL 0x2 /* main chip pll */
11513 +
11514 +/* pwrctl clk mode */
11515 +#define CLK_FAST 0 /* force fast (pll) clock */
11516 +#define CLK_SLOW 1 /* force slow clock */
11517 +#define CLK_DYNAMIC 2 /* enable dynamic power control */
11518 +
11519 +#endif /* _sbutils_h_ */
11520 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sflash.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sflash.h
11521 --- linux-2.6.12.5/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
11522 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sflash.h 2005-08-28 11:12:20.473852616 +0200
11523 @@ -0,0 +1,46 @@
11524 +/*
11525 + * Broadcom SiliconBackplane chipcommon serial flash interface
11526 + *
11527 + * Copyright 2001-2003, Broadcom Corporation
11528 + * All Rights Reserved.
11529 + *
11530 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11531 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11532 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11533 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11534 + *
11535 + * $Id$
11536 + */
11537 +
11538 +#ifndef _sflash_h_
11539 +#define _sflash_h_
11540 +
11541 +#include <typedefs.h>
11542 +#include <sbchipc.h>
11543 +
11544 +/* GPIO based bank selection (1 GPIO bit) */
11545 +#define SFLASH_MAX_BANKS 1
11546 +#define SFLASH_GPIO_SHIFT 2
11547 +#define SFLASH_GPIO_MASK ((SFLASH_MAX_BANKS - 1) << SFLASH_GPIO_SHIFT)
11548 +
11549 +struct sflash_bank {
11550 + uint offset; /* Byte offset */
11551 + uint erasesize; /* Block size */
11552 + uint numblocks; /* Number of blocks */
11553 + uint size; /* Total bank size in bytes */
11554 +};
11555 +
11556 +struct sflash {
11557 + struct sflash_bank banks[SFLASH_MAX_BANKS]; /* GPIO selectable banks */
11558 + uint32 type; /* Type */
11559 + uint size; /* Total array size in bytes */
11560 +};
11561 +
11562 +/* Utility functions */
11563 +extern int sflash_poll(chipcregs_t *cc, uint offset);
11564 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
11565 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
11566 +extern int sflash_erase(chipcregs_t *cc, uint offset);
11567 +extern struct sflash * sflash_init(chipcregs_t *cc);
11568 +
11569 +#endif /* _sflash_h_ */
11570 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/trxhdr.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/trxhdr.h
11571 --- linux-2.6.12.5/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
11572 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/trxhdr.h 2005-08-28 11:12:20.474852464 +0200
11573 @@ -0,0 +1,31 @@
11574 +/*
11575 + * TRX image file header format.
11576 + *
11577 + * Copyright 2001-2003, Broadcom Corporation
11578 + * All Rights Reserved.
11579 + *
11580 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11581 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11582 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11583 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11584 + *
11585 + * $Id$
11586 + */
11587 +
11588 +#include <typedefs.h>
11589 +
11590 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
11591 +#define TRX_VERSION 1
11592 +#define TRX_MAX_LEN 0x3A0000
11593 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
11594 +
11595 +struct trx_header {
11596 + uint32 magic; /* "HDR0" */
11597 + uint32 len; /* Length of file including header */
11598 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
11599 + uint32 flag_version; /* 0:15 flags, 16:31 version */
11600 + uint32 offsets[3]; /* Offsets of partitions from start of header */
11601 +};
11602 +
11603 +/* Compatibility */
11604 +typedef struct trx_header TRXHDR, *PTRXHDR;
11605 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/typedefs.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/typedefs.h
11606 --- linux-2.6.12.5/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
11607 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/typedefs.h 2005-08-28 11:12:20.474852464 +0200
11608 @@ -0,0 +1,162 @@
11609 +/*
11610 + * Copyright 2001-2003, Broadcom Corporation
11611 + * All Rights Reserved.
11612 + *
11613 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11614 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11615 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11616 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11617 + * $Id$
11618 + */
11619 +
11620 +#ifndef _TYPEDEFS_H_
11621 +#define _TYPEDEFS_H_
11622 +
11623 +/*----------------------- define TRUE, FALSE, NULL, bool ----------------*/
11624 +#ifdef __cplusplus
11625 +
11626 +#ifndef FALSE
11627 +#define FALSE false
11628 +#endif
11629 +#ifndef TRUE
11630 +#define TRUE true
11631 +#endif
11632 +
11633 +#else /* !__cplusplus */
11634 +
11635 +#if defined(_WIN32)
11636 +
11637 +typedef unsigned char bool;
11638 +
11639 +#else
11640 +
11641 +#if defined(MACOSX) && defined(KERNEL)
11642 +#include <IOKit/IOTypes.h>
11643 +#else
11644 +typedef int bool;
11645 +#endif
11646 +
11647 +#endif
11648 +
11649 +#ifndef FALSE
11650 +#define FALSE 0
11651 +#endif
11652 +#ifndef TRUE
11653 +#define TRUE 1
11654 +
11655 +#ifndef NULL
11656 +#define NULL 0
11657 +#endif
11658 +
11659 +#endif
11660 +
11661 +#endif /* __cplusplus */
11662 +
11663 +#ifndef OFF
11664 +#define OFF 0
11665 +#endif
11666 +
11667 +#ifndef ON
11668 +#define ON 1
11669 +#endif
11670 +
11671 +/*----------------------- define uchar, ushort, uint, ulong ----------------*/
11672 +
11673 +typedef unsigned char uchar;
11674 +
11675 +#if defined(_WIN32) || defined(PMON) || defined(__MRC__) || defined(V2_HAL) || defined(_CFE_)
11676 +
11677 +#ifndef V2_HAL
11678 +typedef unsigned short ushort;
11679 +#endif
11680 +
11681 +typedef unsigned int uint;
11682 +typedef unsigned long ulong;
11683 +
11684 +#else
11685 +
11686 +/* pick up ushort & uint from standard types.h */
11687 +#if defined(linux) && defined(__KERNEL__)
11688 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
11689 +#else
11690 +#include <sys/types.h>
11691 +#if !defined(TARGETENV_sun4) && !defined(linux)
11692 +typedef unsigned long ulong;
11693 +#endif /* TARGETENV_sun4 */
11694 +#endif
11695 +#if defined(PMON)
11696 +typedef unsigned int uint;
11697 +typedef unsigned long long uint64;
11698 +#endif
11699 +
11700 +#endif /* WIN32 || PMON || .. */
11701 +
11702 +/*----------------------- define [u]int8/16/32/64 --------------------------*/
11703 +
11704 +
11705 +#ifdef V2_HAL
11706 +#include <bcmos.h>
11707 +#else
11708 +typedef signed char int8;
11709 +typedef signed short int16;
11710 +typedef signed int int32;
11711 +
11712 +typedef unsigned char uint8;
11713 +typedef unsigned short uint16;
11714 +typedef unsigned int uint32;
11715 +#endif /* V2_HAL */
11716 +
11717 +typedef float float32;
11718 +typedef double float64;
11719 +
11720 +/*
11721 + * abstracted floating point type allows for compile time selection of
11722 + * single or double precision arithmetic. Compiling with -DFLOAT32
11723 + * selects single precision; the default is double precision.
11724 + */
11725 +
11726 +#if defined(FLOAT32)
11727 +typedef float32 float_t;
11728 +#else /* default to double precision floating point */
11729 +typedef float64 float_t;
11730 +#endif /* FLOAT32 */
11731 +
11732 +#ifdef _MSC_VER /* Microsoft C */
11733 +typedef signed __int64 int64;
11734 +typedef unsigned __int64 uint64;
11735 +
11736 +#elif defined(__GNUC__) && !defined(__STRICT_ANSI__)
11737 +/* gcc understands signed/unsigned 64 bit types, but complains in ANSI mode */
11738 +typedef signed long long int64;
11739 +typedef unsigned long long uint64;
11740 +
11741 +#elif defined(__ICL) && !defined(__STDC__)
11742 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode */
11743 +typedef unsigned long long uint64;
11744 +
11745 +#endif /* _MSC_VER */
11746 +
11747 +
11748 +/*----------------------- define PTRSZ, INLINE --------------------------*/
11749 +
11750 +#define PTRSZ sizeof (char*)
11751 +
11752 +#ifndef INLINE
11753 +
11754 +#ifdef _MSC_VER
11755 +
11756 +#define INLINE __inline
11757 +
11758 +#elif __GNUC__
11759 +
11760 +#define INLINE __inline__
11761 +
11762 +#else
11763 +
11764 +#define INLINE
11765 +
11766 +#endif /* _MSC_VER */
11767 +
11768 +#endif /* INLINE */
11769 +
11770 +#endif /* _TYPEDEFS_H_ */
11771 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/wlioctl.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/wlioctl.h
11772 --- linux-2.6.12.5/arch/mips/bcm947xx/include/wlioctl.h 1970-01-01 01:00:00.000000000 +0100
11773 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/wlioctl.h 2005-08-28 11:12:20.475852312 +0200
11774 @@ -0,0 +1,690 @@
11775 +/*
11776 + * Custom OID/ioctl definitions for
11777 + * Broadcom 802.11abg Networking Device Driver
11778 + *
11779 + * Definitions subject to change without notice.
11780 + *
11781 + * Copyright 2001-2003, Broadcom Corporation
11782 + * All Rights Reserved.
11783 + *
11784 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11785 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11786 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11787 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11788 + *
11789 + * $Id$
11790 + */
11791 +
11792 +#ifndef _wlioctl_h_
11793 +#define _wlioctl_h_
11794 +
11795 +#include <typedefs.h>
11796 +#include <proto/ethernet.h>
11797 +#include <proto/802.11.h>
11798 +
11799 +#if defined(__GNUC__)
11800 +#define PACKED __attribute__((packed))
11801 +#else
11802 +#define PACKED
11803 +#endif
11804 +
11805 +/*
11806 + * Per-bss information structure.
11807 + */
11808 +
11809 +#define WL_NUMRATES 255 /* max # of rates in a rateset */
11810 +
11811 +typedef struct wl_rateset {
11812 + uint32 count; /* # rates in this set */
11813 + uint8 rates[WL_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */
11814 +} wl_rateset_t;
11815 +
11816 +#define WL_LEGACY_BSS_INFO_VERSION 106 /* an older supported version of wl_bss_info struct */
11817 +#define WL_BSS_INFO_VERSION 107 /* current version of wl_bss_info struct */
11818 +
11819 +typedef struct wl_bss_info106 {
11820 + uint version; /* version field */
11821 + struct ether_addr BSSID;
11822 + uint8 SSID_len;
11823 + uint8 SSID[32];
11824 + uint8 Privacy; /* 0=No WEP, 1=Use WEP */
11825 + int16 RSSI; /* receive signal strength (in dBm) */
11826 + uint16 beacon_period; /* units are Kusec */
11827 + uint16 atim_window; /* units are Kusec */
11828 + uint8 channel; /* Channel no. */
11829 + int8 infra; /* 0=IBSS, 1=infrastructure, 2=unknown */
11830 + struct {
11831 + uint count; /* # rates in this set */
11832 + uint8 rates[12]; /* rates in 500kbps units w/hi bit set if basic */
11833 + } rateset; /* supported rates */
11834 + uint8 dtim_period; /* DTIM period */
11835 + int8 phy_noise; /* noise right after tx (in dBm) */
11836 + uint16 capability; /* Capability information */
11837 + struct dot11_bcn_prb *prb; /* probe response frame (ioctl na) */
11838 + uint16 prb_len; /* probe response frame length (ioctl na) */
11839 + struct {
11840 + uint8 supported; /* wpa supported */
11841 + uint8 multicast; /* multicast cipher */
11842 + uint8 ucount; /* count of unicast ciphers */
11843 + uint8 unicast[4]; /* unicast ciphers */
11844 + uint8 acount; /* count of auth modes */
11845 + uint8 auth[4]; /* Authentication modes */
11846 + } wpa;
11847 +} wl_bss_info106_t;
11848 +
11849 +typedef struct wl_bss_info {
11850 + uint32 version; /* version field */
11851 + uint32 length; /* byte length of data in this record, starting at version and including IEs */
11852 + struct ether_addr BSSID;
11853 + uint16 beacon_period; /* units are Kusec */
11854 + uint16 capability; /* Capability information */
11855 + uint8 SSID_len;
11856 + uint8 SSID[32];
11857 + struct {
11858 + uint count; /* # rates in this set */
11859 + uint8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */
11860 + } rateset; /* supported rates */
11861 + uint8 channel; /* Channel no. */
11862 + uint16 atim_window; /* units are Kusec */
11863 + uint8 dtim_period; /* DTIM period */
11864 + int16 RSSI; /* receive signal strength (in dBm) */
11865 + int8 phy_noise; /* noise (in dBm) */
11866 + uint32 ie_length; /* byte length of Information Elements */
11867 + /* variable length Information Elements */
11868 +} wl_bss_info_t;
11869 +
11870 +typedef struct wl_scan_results {
11871 + uint32 buflen;
11872 + uint32 version;
11873 + uint32 count;
11874 + wl_bss_info_t bss_info[1];
11875 +} wl_scan_results_t;
11876 +/* size of wl_scan_results not including variable length array */
11877 +#define WL_SCAN_RESULTS_FIXED_SIZE 12
11878 +
11879 +/* uint32 list */
11880 +typedef struct wl_uint32_list {
11881 + /* in - # of elements, out - # of entries */
11882 + uint32 count;
11883 + /* variable length uint32 list */
11884 + uint32 element[1];
11885 +} wl_uint32_list_t;
11886 +
11887 +typedef struct wlc_ssid {
11888 + uint32 SSID_len;
11889 + uchar SSID[32];
11890 +} wlc_ssid_t;
11891 +
11892 +#define WLC_CNTRY_BUF_SZ 4 /* Country string is 3 bytes + NULL */
11893 +
11894 +typedef struct wl_channels_in_country {
11895 + uint32 buflen;
11896 + uint32 band;
11897 + char country_abbrev[WLC_CNTRY_BUF_SZ];
11898 + uint32 count;
11899 + uint32 channel[1];
11900 +} wl_channels_in_country_t;
11901 +
11902 +typedef struct wl_country_list {
11903 + uint32 buflen;
11904 + uint32 band_set;
11905 + uint32 band;
11906 + uint32 count;
11907 + char country_abbrev[1];
11908 +} wl_country_list_t;
11909 +
11910 +
11911 +/*
11912 +* Maximum # of keys that wl driver supports in S/W. Keys supported
11913 +* in H/W is less than or equal to WSEC_MAX_KEYS.
11914 +*/
11915 +#define WSEC_MAX_KEYS 54 /* Max # of keys (50 + 4 default keys) */
11916 +#define WSEC_MAX_DEFAULT_KEYS 4 /* # of default keys */
11917 +
11918 +/*
11919 +* Remove these two defines if access to crypto/tkhash.h
11920 +* is unconditionally permitted.
11921 +*/
11922 +#define TKHASH_P1_KEY_SIZE 10 /* size of TKHash Phase1 output, in bytes */
11923 +#define TKHASH_P2_KEY_SIZE 16 /* size of TKHash Phase2 output */
11924 +
11925 +/* Enumerate crypto algorithms */
11926 +#define CRYPTO_ALGO_OFF 0
11927 +#define CRYPTO_ALGO_WEP1 1
11928 +#define CRYPTO_ALGO_TKIP 2
11929 +#define CRYPTO_ALGO_WEP128 3
11930 +#define CRYPTO_ALGO_AES_CCM 4
11931 +#define CRYPTO_ALGO_AES_OCB_MSDU 5
11932 +#define CRYPTO_ALGO_AES_OCB_MPDU 6
11933 +#define CRYPTO_ALGO_NALG 7
11934 +
11935 +/* For use with wlc_wep_key.flags */
11936 +#define WSEC_PRIMARY_KEY (1 << 1) /* Indicates this key is the primary (ie tx) key */
11937 +#define WSEC_TKIP_ERROR (1 << 2) /* Provoke deliberate MIC error */
11938 +#define WSEC_REPLAY_ERROR (1 << 3) /* Provoke deliberate replay */
11939 +
11940 +#define WSEC_GEN_MIC_ERROR 0x0001
11941 +#define WSEC_GEN_REPLAY 0x0002
11942 +
11943 +typedef struct tkip_info {
11944 + uint16 phase1[TKHASH_P1_KEY_SIZE/sizeof(uint16)]; /* tkhash phase1 result */
11945 + uint8 phase2[TKHASH_P2_KEY_SIZE]; /* tkhash phase2 result */
11946 + uint32 micl;
11947 + uint32 micr;
11948 +} tkip_info_t;
11949 +
11950 +typedef struct wsec_iv {
11951 + uint32 hi; /* upper 32 bits of IV */
11952 + uint16 lo; /* lower 16 bits of IV */
11953 +} wsec_iv_t;
11954 +
11955 +typedef struct wsec_key {
11956 + uint32 index; /* key index */
11957 + uint32 len; /* key length */
11958 + uint8 data[DOT11_MAX_KEY_SIZE]; /* key data */
11959 + tkip_info_t tkip_tx; /* tkip transmit state */
11960 + tkip_info_t tkip_rx; /* tkip receive state */
11961 + uint32 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
11962 + uint32 flags; /* misc flags */
11963 + uint32 algo_hw; /* cache for hw register*/
11964 + uint32 aes_mode; /* cache for hw register*/
11965 + int iv_len; /* IV length */
11966 + int iv_initialized; /* has IV been initialized already? */
11967 + int icv_len; /* ICV length */
11968 + wsec_iv_t rxiv; /* Rx IV */
11969 + wsec_iv_t txiv; /* Tx IV */
11970 + struct ether_addr ea; /* per station */
11971 +} wsec_key_t;
11972 +
11973 +/* wireless security bitvec */
11974 +#define WEP_ENABLED 1
11975 +#define TKIP_ENABLED 2
11976 +#define AES_ENABLED 4
11977 +#define WSEC_SWFLAG 8
11978 +
11979 +#define WSEC_SW(wsec) ((wsec) & WSEC_SWFLAG)
11980 +#define WSEC_HW(wsec) (!WSEC_SW(wsec))
11981 +#define WSEC_WEP_ENABLED(wsec) ((wsec) & WEP_ENABLED)
11982 +#define WSEC_TKIP_ENABLED(wsec) ((wsec) & TKIP_ENABLED)
11983 +#define WSEC_AES_ENABLED(wsec) ((wsec) & AES_ENABLED)
11984 +#define WSEC_ENABLED(wsec) ((wsec) & (WEP_ENABLED | TKIP_ENABLED | AES_ENABLED))
11985 +
11986 +/* wireless authentication bit vector */
11987 +#define WPA_ENABLED 1
11988 +#define PSK_ENABLED 2
11989 +
11990 +#define WAUTH_WPA_ENABLED(wauth) ((wauth) & WPA_ENABLED)
11991 +#define WAUTH_PSK_ENABLED(wauth) ((wauth) & PSK_ENABLED)
11992 +#define WAUTH_ENABLED(wauth) ((wauth) & (WPA_ENABLED | PSK_ENABLED))
11993 +
11994 +/* group/mcast cipher */
11995 +#define WPA_MCAST_CIPHER(wsec) (((wsec) & TKIP_ENABLED) ? WPA_CIPHER_TKIP : \
11996 + ((wsec) & AES_ENABLED) ? WPA_CIPHER_AES_CCM : \
11997 + WPA_CIPHER_NONE)
11998 +
11999 +typedef struct wl_led_info {
12000 + uint32 index; /* led index */
12001 + uint32 behavior;
12002 + bool activehi;
12003 +} wl_led_info_t;
12004 +
12005 +/*
12006 + * definitions for driver messages passed from WL to NAS.
12007 + */
12008 +/* Use this to recognize wpa and 802.1x driver messages. */
12009 +static const uint8 wl_wpa_snap_template[] =
12010 + { 0xaa, 0xaa, 0x03, 0x00, 0x90, 0x4c };
12011 +
12012 +#define WL_WPA_MSG_IFNAME_MAX 16
12013 +
12014 +/* WPA driver message */
12015 +typedef struct wl_wpa_header {
12016 + struct ether_header eth;
12017 + struct dot11_llc_snap_header snap;
12018 + uint8 version;
12019 + uint8 type;
12020 + /* version 2 additions */
12021 + char ifname[WL_WPA_MSG_IFNAME_MAX];
12022 + /* version specific data */
12023 + /* uint8 data[1]; */
12024 +} wl_wpa_header_t PACKED;
12025 +
12026 +#define WL_WPA_HEADER_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN + 2 + WL_WPA_MSG_IFNAME_MAX)
12027 +
12028 +/* WPA driver message ethertype - private between wlc and nas */
12029 +#define WL_WPA_ETHER_TYPE 0x9999
12030 +
12031 +/* WPA driver message current version */
12032 +#define WL_WPA_MSG_VERSION 2
12033 +
12034 +/* Type field values for the 802.2 driver messages for WPA. */
12035 +#define WLC_ASSOC_MSG 1
12036 +#define WLC_DISASSOC_MSG 2
12037 +#define WLC_PTK_MIC_MSG 3
12038 +#define WLC_GTK_MIC_MSG 4
12039 +
12040 +/* 802.1x driver message */
12041 +typedef struct wl_eapol_header {
12042 + struct ether_header eth;
12043 + struct dot11_llc_snap_header snap;
12044 + uint8 version;
12045 + uint8 reserved;
12046 + char ifname[WL_WPA_MSG_IFNAME_MAX];
12047 + /* version specific data */
12048 + /* uint8 802_1x_msg[1]; */
12049 +} wl_eapol_header_t PACKED;
12050 +
12051 +#define WL_EAPOL_HEADER_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN + 2 + WL_WPA_MSG_IFNAME_MAX)
12052 +
12053 +/* 802.1x driver message ethertype - private between wlc and nas */
12054 +#define WL_EAPOL_ETHER_TYPE 0x999A
12055 +
12056 +/* 802.1x driver message current version */
12057 +#define WL_EAPOL_MSG_VERSION 1
12058 +
12059 +/* srom read/write struct passed through ioctl */
12060 +typedef struct {
12061 + uint byteoff; /* byte offset */
12062 + uint nbytes; /* number of bytes */
12063 + uint16 buf[1];
12064 +} srom_rw_t;
12065 +
12066 +/* R_REG and W_REG struct passed through ioctl */
12067 +typedef struct {
12068 + uint32 byteoff; /* byte offset of the field in d11regs_t */
12069 + uint32 val; /* read/write value of the field */
12070 + uint32 size; /* sizeof the field */
12071 +} rw_reg_t;
12072 +
12073 +/* Structure used by GET/SET_ATTEN ioctls */
12074 +typedef struct {
12075 + uint16 auto_ctrl; /* 1: Automatic control, 0: overriden */
12076 + uint16 bb; /* Baseband attenuation */
12077 + uint16 radio; /* Radio attenuation */
12078 + uint16 txctl1; /* Radio TX_CTL1 value */
12079 +} atten_t;
12080 +
12081 +/* Used to get specific STA parameters */
12082 +typedef struct {
12083 + uint32 val;
12084 + struct ether_addr ea;
12085 +} scb_val_t;
12086 +
12087 +/* callback registration data types */
12088 +
12089 +typedef struct _mac_event_params {
12090 + uint msg;
12091 + struct ether_addr *addr;
12092 + uint result;
12093 + uint status;
12094 + uint auth_type;
12095 +} mac_event_params_t;
12096 +
12097 +typedef struct _mic_error_params {
12098 + struct ether_addr *ea;
12099 + bool group;
12100 + bool flush_txq;
12101 +} mic_error_params_t;
12102 +
12103 +typedef enum _wl_callback {
12104 + WL_MAC_EVENT_CALLBACK = 0,
12105 + WL_LINK_UP_CALLBACK,
12106 + WL_LINK_DOWN_CALLBACK,
12107 + WL_MIC_ERROR_CALLBACK,
12108 + WL_LAST_CALLBACK
12109 +} wl_callback_t;
12110 +
12111 +typedef struct _callback {
12112 + void (*fn)(void *, void *);
12113 + void *context;
12114 +} callback_t;
12115 +
12116 +typedef struct _scan_callback {
12117 + void (*fn)(void *);
12118 + void *context;
12119 +} scan_callback_t;
12120 +
12121 +/* used to register an arbitrary callback via the IOCTL interface */
12122 +typedef struct _set_callback {
12123 + int index;
12124 + callback_t callback;
12125 +} set_callback_t;
12126 +
12127 +/*
12128 + * Country locale determines which channels are available to us.
12129 + */
12130 +typedef enum _wlc_locale {
12131 + WLC_WW = 0, /* Worldwide */
12132 + WLC_THA, /* Thailand */
12133 + WLC_ISR, /* Israel */
12134 + WLC_JDN, /* Jordan */
12135 + WLC_PRC, /* China */
12136 + WLC_JPN, /* Japan */
12137 + WLC_FCC, /* USA */
12138 + WLC_EUR, /* Europe */
12139 + WLC_USL, /* US Low Band only */
12140 + WLC_JPH, /* Japan High Band only */
12141 + WLC_ALL, /* All the channels in this band */
12142 + WLC_11D, /* Represents locale recieved by 11d beacons */
12143 + WLC_LAST_LOCALE,
12144 + WLC_UNDEFINED_LOCALE = 0xf
12145 +} wlc_locale_t;
12146 +
12147 +/* channel encoding */
12148 +typedef struct channel_info {
12149 + int hw_channel;
12150 + int target_channel;
12151 + int scan_channel;
12152 +} channel_info_t;
12153 +
12154 +/* For ioctls that take a list of MAC addresses */
12155 +struct maclist {
12156 + uint count; /* number of MAC addresses */
12157 + struct ether_addr ea[1]; /* variable length array of MAC addresses */
12158 +};
12159 +
12160 +/* get pkt count struct passed through ioctl */
12161 +typedef struct get_pktcnt {
12162 + uint rx_good_pkt;
12163 + uint rx_bad_pkt;
12164 + uint tx_good_pkt;
12165 + uint tx_bad_pkt;
12166 +} get_pktcnt_t;
12167 +
12168 +/* Linux network driver ioctl encoding */
12169 +typedef struct wl_ioctl {
12170 + int cmd; /* common ioctl definition */
12171 + void *buf; /* pointer to user buffer */
12172 + int len; /* length of user buffer */
12173 +} wl_ioctl_t;
12174 +
12175 +/*
12176 + * Structure for passing hardware and software
12177 + * revision info up from the driver.
12178 + */
12179 +typedef struct wlc_rev_info {
12180 + uint vendorid; /* PCI vendor id */
12181 + uint deviceid; /* device id of chip */
12182 + uint radiorev; /* radio revision */
12183 + uint chiprev; /* chip revision */
12184 + uint corerev; /* core revision */
12185 + uint boardid; /* board identifier (usu. PCI sub-device id) */
12186 + uint boardvendor; /* board vendor (usu. PCI sub-vendor id) */
12187 + uint boardrev; /* board revision */
12188 + uint driverrev; /* driver version */
12189 + uint ucoderev; /* microcode version */
12190 + uint bus; /* bus type */
12191 + uint chipnum; /* chip number */
12192 +} wlc_rev_info_t;
12193 +
12194 +/* check this magic number */
12195 +#define WLC_IOCTL_MAGIC 0x14e46c77
12196 +
12197 +/* bump this number if you change the ioctl interface */
12198 +#define WLC_IOCTL_VERSION 1
12199 +
12200 +/* maximum length buffer required */
12201 +#define WLC_IOCTL_MAXLEN 8192
12202 +
12203 +/* common ioctl definitions */
12204 +#define WLC_GET_MAGIC 0
12205 +#define WLC_GET_VERSION 1
12206 +#define WLC_UP 2
12207 +#define WLC_DOWN 3
12208 +#define WLC_DUMP 6
12209 +#define WLC_GET_MSGLEVEL 7
12210 +#define WLC_SET_MSGLEVEL 8
12211 +#define WLC_GET_PROMISC 9
12212 +#define WLC_SET_PROMISC 10
12213 +#define WLC_GET_RATE 12
12214 +#define WLC_SET_RATE 13
12215 +#define WLC_GET_INSTANCE 14
12216 +#define WLC_GET_FRAG 15
12217 +#define WLC_SET_FRAG 16
12218 +#define WLC_GET_RTS 17
12219 +#define WLC_SET_RTS 18
12220 +#define WLC_GET_INFRA 19
12221 +#define WLC_SET_INFRA 20
12222 +#define WLC_GET_AUTH 21
12223 +#define WLC_SET_AUTH 22
12224 +#define WLC_GET_BSSID 23
12225 +#define WLC_SET_BSSID 24
12226 +#define WLC_GET_SSID 25
12227 +#define WLC_SET_SSID 26
12228 +#define WLC_RESTART 27
12229 +#define WLC_GET_CHANNEL 29
12230 +#define WLC_SET_CHANNEL 30
12231 +#define WLC_GET_SRL 31
12232 +#define WLC_SET_SRL 32
12233 +#define WLC_GET_LRL 33
12234 +#define WLC_SET_LRL 34
12235 +#define WLC_GET_PLCPHDR 35
12236 +#define WLC_SET_PLCPHDR 36
12237 +#define WLC_GET_RADIO 37
12238 +#define WLC_SET_RADIO 38
12239 +#define WLC_GET_PHYTYPE 39
12240 +#define WLC_GET_WEP 42
12241 +#define WLC_SET_WEP 43
12242 +#define WLC_GET_KEY 44
12243 +#define WLC_SET_KEY 45
12244 +#define WLC_SCAN 50
12245 +#define WLC_SCAN_RESULTS 51
12246 +#define WLC_DISASSOC 52
12247 +#define WLC_REASSOC 53
12248 +#define WLC_GET_ROAM_TRIGGER 54
12249 +#define WLC_SET_ROAM_TRIGGER 55
12250 +#define WLC_GET_TXANT 61
12251 +#define WLC_SET_TXANT 62
12252 +#define WLC_GET_ANTDIV 63
12253 +#define WLC_SET_ANTDIV 64
12254 +#define WLC_GET_TXPWR 65
12255 +#define WLC_SET_TXPWR 66
12256 +#define WLC_GET_CLOSED 67
12257 +#define WLC_SET_CLOSED 68
12258 +#define WLC_GET_MACLIST 69
12259 +#define WLC_SET_MACLIST 70
12260 +#define WLC_GET_RATESET 71
12261 +#define WLC_SET_RATESET 72
12262 +#define WLC_GET_LOCALE 73
12263 +#define WLC_SET_LOCALE 74
12264 +#define WLC_GET_BCNPRD 75
12265 +#define WLC_SET_BCNPRD 76
12266 +#define WLC_GET_DTIMPRD 77
12267 +#define WLC_SET_DTIMPRD 78
12268 +#define WLC_GET_SROM 79
12269 +#define WLC_SET_SROM 80
12270 +#define WLC_GET_WEP_RESTRICT 81
12271 +#define WLC_SET_WEP_RESTRICT 82
12272 +#define WLC_GET_COUNTRY 83
12273 +#define WLC_SET_COUNTRY 84
12274 +#define WLC_GET_REVINFO 98
12275 +#define WLC_GET_MACMODE 105
12276 +#define WLC_SET_MACMODE 106
12277 +#define WLC_GET_GMODE 109
12278 +#define WLC_SET_GMODE 110
12279 +#define WLC_GET_CURR_RATESET 114 /* current rateset */
12280 +#define WLC_GET_SCANSUPPRESS 115
12281 +#define WLC_SET_SCANSUPPRESS 116
12282 +#define WLC_GET_AP 117
12283 +#define WLC_SET_AP 118
12284 +#define WLC_GET_EAP_RESTRICT 119
12285 +#define WLC_SET_EAP_RESTRICT 120
12286 +#define WLC_GET_WDSLIST 123
12287 +#define WLC_SET_WDSLIST 124
12288 +#define WLC_GET_RSSI 127
12289 +#define WLC_GET_WSEC 133
12290 +#define WLC_SET_WSEC 134
12291 +#define WLC_GET_BSS_INFO 136
12292 +#define WLC_GET_LAZYWDS 138
12293 +#define WLC_SET_LAZYWDS 139
12294 +#define WLC_GET_BANDLIST 140
12295 +#define WLC_GET_BAND 141
12296 +#define WLC_SET_BAND 142
12297 +#define WLC_GET_SHORTSLOT 144
12298 +#define WLC_GET_SHORTSLOT_OVERRIDE 145
12299 +#define WLC_SET_SHORTSLOT_OVERRIDE 146
12300 +#define WLC_GET_SHORTSLOT_RESTRICT 147
12301 +#define WLC_SET_SHORTSLOT_RESTRICT 148
12302 +#define WLC_GET_GMODE_PROTECTION 149
12303 +#define WLC_GET_GMODE_PROTECTION_OVERRIDE 150
12304 +#define WLC_SET_GMODE_PROTECTION_OVERRIDE 151
12305 +#define WLC_UPGRADE 152
12306 +#define WLC_GET_ASSOCLIST 159
12307 +#define WLC_GET_CLK 160
12308 +#define WLC_SET_CLK 161
12309 +#define WLC_GET_UP 162
12310 +#define WLC_OUT 163
12311 +#define WLC_GET_WPA_AUTH 164
12312 +#define WLC_SET_WPA_AUTH 165
12313 +#define WLC_GET_GMODE_PROTECTION_CONTROL 178
12314 +#define WLC_SET_GMODE_PROTECTION_CONTROL 179
12315 +#define WLC_GET_PHYLIST 180
12316 +#define WLC_GET_GMODE_PROTECTION_CTS 198
12317 +#define WLC_SET_GMODE_PROTECTION_CTS 199
12318 +#define WLC_GET_PIOMODE 203
12319 +#define WLC_SET_PIOMODE 204
12320 +#define WLC_SET_LED 209
12321 +#define WLC_GET_LED 210
12322 +#define WLC_GET_CHANNEL_SEL 215
12323 +#define WLC_START_CHANNEL_SEL 216
12324 +#define WLC_GET_VALID_CHANNELS 217
12325 +#define WLC_GET_FAKEFRAG 218
12326 +#define WLC_SET_FAKEFRAG 219
12327 +#define WLC_GET_WET 230
12328 +#define WLC_SET_WET 231
12329 +#define WLC_GET_KEY_PRIMARY 235
12330 +#define WLC_SET_KEY_PRIMARY 236
12331 +#define WLC_SCAN_WITH_CALLBACK 240
12332 +#define WLC_SET_CS_SCAN_TIMER 248
12333 +#define WLC_GET_CS_SCAN_TIMER 249
12334 +#define WLC_CURRENT_PWR 256
12335 +#define WLC_GET_CHANNELS_IN_COUNTRY 260
12336 +#define WLC_GET_COUNTRY_LIST 261
12337 +#define WLC_NVRAM_GET 264
12338 +#define WLC_NVRAM_SET 265
12339 +#define WLC_LAST 271 /* bump after adding */
12340 +
12341 +/*
12342 + * Minor kludge alert:
12343 + * Duplicate a few definitions that irelay requires from epiioctl.h here
12344 + * so caller doesn't have to include this file and epiioctl.h .
12345 + * If this grows any more, it would be time to move these irelay-specific
12346 + * definitions out of the epiioctl.h and into a separate driver common file.
12347 + */
12348 +#ifndef EPICTRL_COOKIE
12349 +#define EPICTRL_COOKIE 0xABADCEDE
12350 +#endif
12351 +
12352 +/* vx wlc ioctl's offset */
12353 +#define CMN_IOCTL_OFF 0x180
12354 +
12355 +/*
12356 + * custom OID support
12357 + *
12358 + * 0xFF - implementation specific OID
12359 + * 0xE4 - first byte of Broadcom PCI vendor ID
12360 + * 0x14 - second byte of Broadcom PCI vendor ID
12361 + * 0xXX - the custom OID number
12362 + */
12363 +
12364 +/* begin 0x1f values beyond the start of the ET driver range. */
12365 +#define WL_OID_BASE 0xFFE41420
12366 +
12367 +/* NDIS overrides */
12368 +#define OID_WL_GETINSTANCE (WL_OID_BASE + WLC_GET_INSTANCE)
12369 +
12370 +#define WL_DECRYPT_STATUS_SUCCESS 1
12371 +#define WL_DECRYPT_STATUS_FAILURE 2
12372 +#define WL_DECRYPT_STATUS_UNKNOWN 3
12373 +
12374 +/* allows user-mode app to poll the status of USB image upgrade */
12375 +#define WLC_UPGRADE_SUCCESS 0
12376 +#define WLC_UPGRADE_PENDING 1
12377 +
12378 +/* Bit masks for radio disabled status - returned by WL_GET_RADIO */
12379 +#define WL_RADIO_SW_DISABLE (1<<0)
12380 +#define WL_RADIO_HW_DISABLE (1<<1)
12381 +
12382 +/* Override bit for WLC_SET_TXPWR. if set, ignore other level limits */
12383 +#define WL_TXPWR_OVERRIDE (1<<31)
12384 +
12385 +
12386 +/* Bus types */
12387 +#define WL_SB_BUS 0 /* Silicon Backplane */
12388 +#define WL_PCI_BUS 1 /* PCI target */
12389 +#define WL_PCMCIA_BUS 2 /* PCMCIA target */
12390 +
12391 +/* band types */
12392 +#define WLC_BAND_AUTO 0 /* auto-select */
12393 +#define WLC_BAND_A 1 /* "a" band (5 Ghz) */
12394 +#define WLC_BAND_B 2 /* "b" band (2.4 Ghz) */
12395 +
12396 +/* MAC list modes */
12397 +#define WLC_MACMODE_DISABLED 0 /* MAC list disabled */
12398 +#define WLC_MACMODE_DENY 1 /* Deny specified (i.e. allow unspecified) */
12399 +#define WLC_MACMODE_ALLOW 2 /* Allow specified (i.e. deny unspecified) */
12400 +
12401 +/*
12402 + *
12403 + */
12404 +#define GMODE_LEGACY_B 0
12405 +#define GMODE_AUTO 1
12406 +#define GMODE_ONLY 2
12407 +#define GMODE_B_DEFERRED 3
12408 +#define GMODE_PERFORMANCE 4
12409 +#define GMODE_LRS 5
12410 +#define GMODE_MAX 6
12411 +
12412 +/* values for PLCPHdr_override */
12413 +#define WLC_PLCP_AUTO -1
12414 +#define WLC_PLCP_SHORT 0
12415 +#define WLC_PLCP_LONG 1
12416 +
12417 +/* values for g_protection_override */
12418 +#define WLC_G_PROTECTION_AUTO -1
12419 +#define WLC_G_PROTECTION_OFF 0
12420 +#define WLC_G_PROTECTION_ON 1
12421 +
12422 +/* values for g_protection_control */
12423 +#define WLC_G_PROTECTION_CTL_OFF 0
12424 +#define WLC_G_PROTECTION_CTL_LOCAL 1
12425 +#define WLC_G_PROTECTION_CTL_OVERLAP 2
12426 +
12427 +
12428 +
12429 +
12430 +
12431 +
12432 +/* max # of leds supported by GPIO (gpio pin# == led index#) */
12433 +#define WL_LED_NUMGPIO 16 /* gpio 0-15 */
12434 +
12435 +/* led per-pin behaviors */
12436 +#define WL_LED_OFF 0 /* always off */
12437 +#define WL_LED_ON 1 /* always on */
12438 +#define WL_LED_ACTIVITY 2 /* activity */
12439 +#define WL_LED_RADIO 3 /* radio enabled */
12440 +#define WL_LED_ARADIO 4 /* 5 Ghz radio enabled */
12441 +#define WL_LED_BRADIO 5 /* 2.4Ghz radio enabled */
12442 +#define WL_LED_BGMODE 6 /* on if gmode, off if bmode */
12443 +#define WL_LED_WI1 7
12444 +#define WL_LED_WI2 8
12445 +#define WL_LED_WI3 9
12446 +#define WL_LED_ASSOC 10 /* associated state indicator */
12447 +#define WL_LED_INACTIVE 11 /* null behavior (clears default behavior) */
12448 +#define WL_LED_NUMBEHAVIOR 12
12449 +
12450 +/* led behavior numeric value format */
12451 +#define WL_LED_BEH_MASK 0x7f /* behavior mask */
12452 +#define WL_LED_AL_MASK 0x80 /* activelow (polarity) bit */
12453 +
12454 +
12455 +/* rate check */
12456 +#define WL_RATE_OFDM(r) (((r) & 0x7f) == 12 || ((r) & 0x7f) == 18 || \
12457 + ((r) & 0x7f) == 24 || ((r) & 0x7f) == 36 || \
12458 + ((r) & 0x7f) == 48 || ((r) & 0x7f) == 72 || \
12459 + ((r) & 0x7f) == 96 || ((r) & 0x7f) == 108)
12460 +
12461 +
12462 +#undef PACKED
12463 +
12464 +#endif /* _wlioctl_h_ */
12465 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/int-handler.S linux-2.6.12.5-brcm/arch/mips/bcm947xx/int-handler.S
12466 --- linux-2.6.12.5/arch/mips/bcm947xx/int-handler.S 1970-01-01 01:00:00.000000000 +0100
12467 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/int-handler.S 2005-08-28 16:58:08.027788792 +0200
12468 @@ -0,0 +1,48 @@
12469 +/*
12470 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
12471 + *
12472 + * This program is free software; you can redistribute it and/or modify it
12473 + * under the terms of the GNU General Public License as published by the
12474 + * Free Software Foundation; either version 2 of the License, or (at your
12475 + * option) any later version.
12476 + *
12477 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12478 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12479 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12480 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
12481 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12482 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
12483 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12484 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
12485 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
12486 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12487 + *
12488 + * You should have received a copy of the GNU General Public License along
12489 + * with this program; if not, write to the Free Software Foundation, Inc.,
12490 + * 675 Mass Ave, Cambridge, MA 02139, USA.
12491 + */
12492 +
12493 +#include <asm/asm.h>
12494 +#include <asm/mipsregs.h>
12495 +#include <asm/regdef.h>
12496 +#include <asm/stackframe.h>
12497 +
12498 + .text
12499 + .set noreorder
12500 + .set noat
12501 + .align 5
12502 +
12503 + NESTED(bcm47xx_irq_handler, PT_SIZE, sp)
12504 + SAVE_ALL
12505 + CLI
12506 +
12507 + .set at
12508 + .set noreorder
12509 +
12510 + jal bcm47xx_irq_dispatch
12511 + move a0, sp
12512 +
12513 + j ret_from_irq
12514 + nop
12515 +
12516 + END(bcm47xx_irq_handler)
12517 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/irq.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/irq.c
12518 --- linux-2.6.12.5/arch/mips/bcm947xx/irq.c 1970-01-01 01:00:00.000000000 +0100
12519 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/irq.c 2005-08-28 16:58:26.178029536 +0200
12520 @@ -0,0 +1,68 @@
12521 +/*
12522 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
12523 + *
12524 + * This program is free software; you can redistribute it and/or modify it
12525 + * under the terms of the GNU General Public License as published by the
12526 + * Free Software Foundation; either version 2 of the License, or (at your
12527 + * option) any later version.
12528 + *
12529 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12530 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12531 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12532 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
12533 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12534 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
12535 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12536 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
12537 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
12538 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12539 + *
12540 + * You should have received a copy of the GNU General Public License along
12541 + * with this program; if not, write to the Free Software Foundation, Inc.,
12542 + * 675 Mass Ave, Cambridge, MA 02139, USA.
12543 + */
12544 +
12545 +#include <linux/config.h>
12546 +#include <linux/errno.h>
12547 +#include <linux/init.h>
12548 +#include <linux/interrupt.h>
12549 +#include <linux/irq.h>
12550 +#include <linux/module.h>
12551 +#include <linux/smp.h>
12552 +#include <linux/types.h>
12553 +
12554 +#include <asm/cpu.h>
12555 +#include <asm/io.h>
12556 +#include <asm/irq.h>
12557 +#include <asm/irq_cpu.h>
12558 +#include <asm/gdb-stub.h>
12559 +
12560 +extern asmlinkage void bcm47xx_irq_handler(void);
12561 +
12562 +void bcm47xx_irq_dispatch(struct pt_regs *regs)
12563 +{
12564 + u32 cause;
12565 +
12566 + cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
12567 +
12568 + clear_c0_status(cause);
12569 +
12570 + if (cause & CAUSEF_IP7)
12571 + do_IRQ(7, regs);
12572 + if (cause & CAUSEF_IP2)
12573 + do_IRQ(2, regs);
12574 + if (cause & CAUSEF_IP3)
12575 + do_IRQ(3, regs);
12576 + if (cause & CAUSEF_IP4)
12577 + do_IRQ(4, regs);
12578 + if (cause & CAUSEF_IP5)
12579 + do_IRQ(5, regs);
12580 + if (cause & CAUSEF_IP6)
12581 + do_IRQ(6, regs);
12582 +}
12583 +
12584 +void __init arch_init_irq(void)
12585 +{
12586 + set_except_vector(0, bcm47xx_irq_handler);
12587 + mips_cpu_irq_init(0);
12588 +}
12589 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/prom.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/prom.c
12590 --- linux-2.6.12.5/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
12591 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/prom.c 2005-08-28 16:58:41.789656208 +0200
12592 @@ -0,0 +1,59 @@
12593 +/*
12594 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
12595 + *
12596 + * This program is free software; you can redistribute it and/or modify it
12597 + * under the terms of the GNU General Public License as published by the
12598 + * Free Software Foundation; either version 2 of the License, or (at your
12599 + * option) any later version.
12600 + *
12601 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12602 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12603 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12604 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
12605 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12606 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
12607 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12608 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
12609 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
12610 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12611 + *
12612 + * You should have received a copy of the GNU General Public License along
12613 + * with this program; if not, write to the Free Software Foundation, Inc.,
12614 + * 675 Mass Ave, Cambridge, MA 02139, USA.
12615 + */
12616 +
12617 +#include <linux/init.h>
12618 +#include <linux/mm.h>
12619 +#include <linux/sched.h>
12620 +#include <linux/bootmem.h>
12621 +
12622 +#include <asm/addrspace.h>
12623 +#include <asm/bootinfo.h>
12624 +#include <asm/pmon.h>
12625 +
12626 +const char *get_system_type(void)
12627 +{
12628 + return "Broadcom BCM47xx";
12629 +}
12630 +
12631 +void __init prom_init(void)
12632 +{
12633 + unsigned long mem;
12634 +
12635 + mips_machgroup = MACH_GROUP_BRCM;
12636 + mips_machtype = MACH_BCM47XX;
12637 +
12638 + /* Figure out memory size by finding aliases */
12639 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
12640 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
12641 + *(unsigned long *)(prom_init))
12642 + break;
12643 + }
12644 +
12645 + add_memory_region(0, mem, BOOT_MEM_RAM);
12646 +}
12647 +
12648 +unsigned long __init prom_free_prom_memory(void)
12649 +{
12650 + return 0;
12651 +}
12652 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/setup.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/setup.c
12653 --- linux-2.6.12.5/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
12654 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/setup.c 2005-08-28 16:57:28.317825624 +0200
12655 @@ -0,0 +1,127 @@
12656 +/*
12657 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
12658 + *
12659 + * This program is free software; you can redistribute it and/or modify it
12660 + * under the terms of the GNU General Public License as published by the
12661 + * Free Software Foundation; either version 2 of the License, or (at your
12662 + * option) any later version.
12663 + *
12664 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12665 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12666 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12667 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
12668 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12669 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
12670 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12671 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
12672 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
12673 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12674 + *
12675 + * You should have received a copy of the GNU General Public License along
12676 + * with this program; if not, write to the Free Software Foundation, Inc.,
12677 + * 675 Mass Ave, Cambridge, MA 02139, USA.
12678 + */
12679 +
12680 +#include <linux/init.h>
12681 +#include <linux/types.h>
12682 +#include <linux/tty.h>
12683 +#include <linux/serial.h>
12684 +#include <linux/serial_core.h>
12685 +#include <linux/serial_reg.h>
12686 +#include <asm/time.h>
12687 +#include <asm/reboot.h>
12688 +
12689 +#include <typedefs.h>
12690 +#include <sbutils.h>
12691 +#include <sbmips.h>
12692 +#include <sbpci.h>
12693 +#include <sbconfig.h>
12694 +#include <bcmdevs.h>
12695 +
12696 +#if 1
12697 +
12698 +#define SER_PORT1(reg) (*((volatile unsigned char *)(0xb8000400+reg)))
12699 +
12700 +int putDebugChar(char c)
12701 +{
12702 + while (!(SER_PORT1(UART_LSR) & UART_LSR_THRE));
12703 + SER_PORT1(UART_TX) = c;
12704 +
12705 + return 1;
12706 +}
12707 +
12708 +char getDebugChar(void)
12709 +{
12710 + while (!(SER_PORT1(UART_LSR) & 1));
12711 + return SER_PORT1(UART_RX);
12712 +}
12713 +
12714 +
12715 +static int ser_line = 0;
12716 +
12717 +static void
12718 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
12719 +{
12720 + struct uart_port s;
12721 +
12722 + memset(&s, 0, sizeof(s));
12723 +
12724 + s.line = ser_line++;
12725 + s.membase = regs;
12726 + s.irq = irq + 2;
12727 + s.uartclk = baud_base;
12728 + s.flags = ASYNC_BOOT_AUTOCONF;
12729 + s.iotype = SERIAL_IO_MEM;
12730 + s.regshift = reg_shift;
12731 +
12732 + if (early_serial_setup(&s) != 0) {
12733 + printk(KERN_ERR "Serial setup failed!\n");
12734 + }
12735 +}
12736 +#endif
12737 +
12738 +extern void bcm47xx_time_init(void);
12739 +extern void bcm47xx_timer_setup(struct irqaction *irq);
12740 +
12741 +void *nvram_get(char *foo)
12742 +{
12743 + return NULL;
12744 +}
12745 +
12746 +void *sbh;
12747 +
12748 +static void bcm47xx_machine_restart(char *command)
12749 +{
12750 + /* Set the watchdog timer to reset immediately */
12751 + cli();
12752 + sb_watchdog(sbh, 1);
12753 + while (1);
12754 +}
12755 +
12756 +static void bcm47xx_machine_halt(void)
12757 +{
12758 + /* Disable interrupts and watchdog and spin forever */
12759 + cli();
12760 + sb_watchdog(sbh, 0);
12761 + while (1);
12762 +}
12763 +
12764 +static int __init bcm47xx_init(void)
12765 +{
12766 +
12767 + sbh = sb_kattach();
12768 + sb_mips_init(sbh);
12769 + sbpci_init(sbh);
12770 + sb_serial_init(sbh, serial_add);
12771 +
12772 + _machine_restart = bcm47xx_machine_restart;
12773 + _machine_halt = bcm47xx_machine_halt;
12774 + _machine_power_off = bcm47xx_machine_halt;
12775 +
12776 + board_time_init = bcm47xx_time_init;
12777 + board_timer_setup = bcm47xx_timer_setup;
12778 +
12779 + return 0;
12780 +}
12781 +
12782 +early_initcall(bcm47xx_init);
12783 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/time.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/time.c
12784 --- linux-2.6.12.5/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
12785 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/time.c 2005-08-28 16:57:55.440702320 +0200
12786 @@ -0,0 +1,59 @@
12787 +/*
12788 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
12789 + *
12790 + * This program is free software; you can redistribute it and/or modify it
12791 + * under the terms of the GNU General Public License as published by the
12792 + * Free Software Foundation; either version 2 of the License, or (at your
12793 + * option) any later version.
12794 + *
12795 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12796 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12797 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12798 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
12799 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12800 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
12801 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12802 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
12803 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
12804 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12805 + *
12806 + * You should have received a copy of the GNU General Public License along
12807 + * with this program; if not, write to the Free Software Foundation, Inc.,
12808 + * 675 Mass Ave, Cambridge, MA 02139, USA.
12809 + */
12810 +
12811 +#include <linux/config.h>
12812 +#include <linux/init.h>
12813 +#include <linux/kernel.h>
12814 +#include <linux/sched.h>
12815 +#include <linux/serial_reg.h>
12816 +#include <linux/interrupt.h>
12817 +#include <asm/addrspace.h>
12818 +#include <asm/io.h>
12819 +#include <asm/time.h>
12820 +
12821 +void __init
12822 +bcm47xx_time_init(void)
12823 +{
12824 + unsigned int hz;
12825 +
12826 + /*
12827 + * Use deterministic values for initial counter interrupt
12828 + * so that calibrate delay avoids encountering a counter wrap.
12829 + */
12830 + write_c0_count(0);
12831 + write_c0_compare(0xffff);
12832 +
12833 + hz = 200 * 1000 * 1000;
12834 +
12835 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
12836 + mips_hpt_frequency = hz / 2;
12837 +
12838 +}
12839 +
12840 +void __init
12841 +bcm47xx_timer_setup(struct irqaction *irq)
12842 +{
12843 + /* Enable the timer interrupt */
12844 + setup_irq(7, irq);
12845 +}
12846 diff -Nur linux-2.6.12.5/arch/mips/kernel/cpu-probe.c linux-2.6.12.5-brcm/arch/mips/kernel/cpu-probe.c
12847 --- linux-2.6.12.5/arch/mips/kernel/cpu-probe.c 2005-08-15 02:20:18.000000000 +0200
12848 +++ linux-2.6.12.5-brcm/arch/mips/kernel/cpu-probe.c 2005-08-28 11:12:20.538842736 +0200
12849 @@ -555,6 +555,28 @@
12850 }
12851 }
12852
12853 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
12854 +{
12855 + decode_config1(c);
12856 + switch (c->processor_id & 0xff00) {
12857 + case PRID_IMP_BCM3302:
12858 + c->cputype = CPU_BCM3302;
12859 + c->isa_level = MIPS_CPU_ISA_M32;
12860 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
12861 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
12862 + break;
12863 + case PRID_IMP_BCM4710:
12864 + c->cputype = CPU_BCM4710;
12865 + c->isa_level = MIPS_CPU_ISA_M32;
12866 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
12867 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
12868 + break;
12869 + default:
12870 + c->cputype = CPU_UNKNOWN;
12871 + break;
12872 + }
12873 +}
12874 +
12875 __init void cpu_probe(void)
12876 {
12877 struct cpuinfo_mips *c = &current_cpu_data;
12878 @@ -577,7 +599,9 @@
12879 case PRID_COMP_SIBYTE:
12880 cpu_probe_sibyte(c);
12881 break;
12882 -
12883 + case PRID_COMP_BROADCOM:
12884 + cpu_probe_broadcom(c);
12885 + break;
12886 case PRID_COMP_SANDCRAFT:
12887 cpu_probe_sandcraft(c);
12888 break;
12889 diff -Nur linux-2.6.12.5/arch/mips/kernel/head.S linux-2.6.12.5-brcm/arch/mips/kernel/head.S
12890 --- linux-2.6.12.5/arch/mips/kernel/head.S 2005-08-15 02:20:18.000000000 +0200
12891 +++ linux-2.6.12.5-brcm/arch/mips/kernel/head.S 2005-08-28 11:12:20.539842584 +0200
12892 @@ -122,6 +122,14 @@
12893 #endif
12894 .endm
12895
12896 +#ifdef CONFIG_BCM4710
12897 +#undef eret
12898 +#define eret nop; nop; eret
12899 +#endif
12900 +
12901 + j kernel_entry
12902 + nop
12903 +
12904 /*
12905 * Reserved space for exception handlers.
12906 * Necessary for machines which link their kernels at KSEG0.
12907 diff -Nur linux-2.6.12.5/arch/mips/kernel/proc.c linux-2.6.12.5-brcm/arch/mips/kernel/proc.c
12908 --- linux-2.6.12.5/arch/mips/kernel/proc.c 2005-08-15 02:20:18.000000000 +0200
12909 +++ linux-2.6.12.5-brcm/arch/mips/kernel/proc.c 2005-08-28 11:12:20.553840456 +0200
12910 @@ -75,7 +75,9 @@
12911 [CPU_VR4133] "NEC VR4133",
12912 [CPU_VR4181] "NEC VR4181",
12913 [CPU_VR4181A] "NEC VR4181A",
12914 - [CPU_SR71000] "Sandcraft SR71000"
12915 + [CPU_SR71000] "Sandcraft SR71000",
12916 + [CPU_BCM3302] "Broadcom BCM3302",
12917 + [CPU_BCM4710] "Broadcom BCM4710"
12918 };
12919
12920
12921 diff -Nur linux-2.6.12.5/arch/mips/mm/tlbex.c linux-2.6.12.5-brcm/arch/mips/mm/tlbex.c
12922 --- linux-2.6.12.5/arch/mips/mm/tlbex.c 2005-08-15 02:20:18.000000000 +0200
12923 +++ linux-2.6.12.5-brcm/arch/mips/mm/tlbex.c 2005-08-28 11:12:20.587835288 +0200
12924 @@ -851,6 +851,8 @@
12925 case CPU_4KSC:
12926 case CPU_20KC:
12927 case CPU_25KF:
12928 + case CPU_BCM3302:
12929 + case CPU_BCM4710:
12930 tlbw(p);
12931 break;
12932
12933 diff -Nur linux-2.6.12.5/arch/mips/pci/Makefile linux-2.6.12.5-brcm/arch/mips/pci/Makefile
12934 --- linux-2.6.12.5/arch/mips/pci/Makefile 2005-08-15 02:20:18.000000000 +0200
12935 +++ linux-2.6.12.5-brcm/arch/mips/pci/Makefile 2005-08-28 16:41:44.565297816 +0200
12936 @@ -18,6 +18,7 @@
12937 obj-$(CONFIG_MIPS_TX3927) += ops-jmr3927.o
12938 obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
12939 obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
12940 +obj-$(CONFIG_BCM947XX) += ops-sb.o fixup-bcm47xx.o pci-bcm47xx.o
12941
12942 #
12943 # These are still pretty much in the old state, watch, go blind.
12944 diff -Nur linux-2.6.12.5/arch/mips/pci/fixup-bcm47xx.c linux-2.6.12.5-brcm/arch/mips/pci/fixup-bcm47xx.c
12945 --- linux-2.6.12.5/arch/mips/pci/fixup-bcm47xx.c 1970-01-01 01:00:00.000000000 +0100
12946 +++ linux-2.6.12.5-brcm/arch/mips/pci/fixup-bcm47xx.c 2005-08-28 11:12:20.611831640 +0200
12947 @@ -0,0 +1,23 @@
12948 +#include <linux/init.h>
12949 +#include <linux/pci.h>
12950 +
12951 +/* Do platform specific device initialization at pci_enable_device() time */
12952 +int pcibios_plat_dev_init(struct pci_dev *dev)
12953 +{
12954 + return 0;
12955 +}
12956 +
12957 +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
12958 +{
12959 + u8 irq;
12960 +
12961 + if (dev->bus->number == 1)
12962 + return 2;
12963 +
12964 + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
12965 + return irq + 2;
12966 +}
12967 +
12968 +struct pci_fixup pcibios_fixups[] __initdata = {
12969 + { 0 }
12970 +};
12971 diff -Nur linux-2.6.12.5/arch/mips/pci/ops-sb.c linux-2.6.12.5-brcm/arch/mips/pci/ops-sb.c
12972 --- linux-2.6.12.5/arch/mips/pci/ops-sb.c 1970-01-01 01:00:00.000000000 +0100
12973 +++ linux-2.6.12.5-brcm/arch/mips/pci/ops-sb.c 2005-08-28 11:12:20.612831488 +0200
12974 @@ -0,0 +1,44 @@
12975 +#include <linux/kernel.h>
12976 +#include <linux/init.h>
12977 +#include <linux/pci.h>
12978 +#include <linux/types.h>
12979 +#include <asm/pci.h>
12980 +
12981 +#include <typedefs.h>
12982 +#include <sbpci.h>
12983 +
12984 +extern void *sbh;
12985 +//extern spinlock_t bcm47xx_sbh_lock;
12986 +
12987 +static int
12988 +sb_pci_read_config(struct pci_bus *bus, unsigned int devfn,
12989 + int reg, int size, u32 *val)
12990 +{
12991 + //unsigned long flags;
12992 + int ret;
12993 +
12994 +
12995 + //spin_lock_irqsave(&sbh_lock, flags);
12996 + ret = sbpci_read_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, val, size);
12997 + //spin_unlock_irqrestore(&sbh_lock, flags);
12998 +
12999 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
13000 +}
13001 +
13002 +static int
13003 +sb_pci_write_config(struct pci_bus *bus, unsigned int devfn,
13004 + int reg, int size, u32 val)
13005 +{
13006 +// unsigned long flags;
13007 + int ret;
13008 +
13009 +// spin_lock_irqsave(&sbh_lock, flags);
13010 + ret = sbpci_write_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, &val, size);
13011 +// spin_unlock_irqrestore(&sbh_lock, flags);
13012 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
13013 +}
13014 +
13015 +struct pci_ops sb_pci_ops = {
13016 + .read = sb_pci_read_config,
13017 + .write = sb_pci_write_config,
13018 +};
13019 diff -Nur linux-2.6.12.5/arch/mips/pci/pci-bcm47xx.c linux-2.6.12.5-brcm/arch/mips/pci/pci-bcm47xx.c
13020 --- linux-2.6.12.5/arch/mips/pci/pci-bcm47xx.c 1970-01-01 01:00:00.000000000 +0100
13021 +++ linux-2.6.12.5-brcm/arch/mips/pci/pci-bcm47xx.c 2005-08-28 11:12:20.612831488 +0200
13022 @@ -0,0 +1,61 @@
13023 +#include <linux/init.h>
13024 +#include <linux/pci.h>
13025 +#include <linux/types.h>
13026 +
13027 +#include <asm/cpu.h>
13028 +#include <asm/io.h>
13029 +
13030 +#include <typedefs.h>
13031 +#include <sbconfig.h>
13032 +
13033 +extern struct pci_ops sb_pci_ops;
13034 +
13035 +static struct resource sb_pci_mem_resource = {
13036 + .name = "SB PCI Memory resources",
13037 + .start = SB_ENUM_BASE,
13038 + .end = SB_ENUM_LIM - 1,
13039 + .flags = IORESOURCE_MEM,
13040 +};
13041 +
13042 +static struct resource sb_pci_io_resource = {
13043 + .name = "SB PCI I/O resources",
13044 + .start = 0x100,
13045 + .end = 0x1FF,
13046 + .flags = IORESOURCE_IO,
13047 +};
13048 +
13049 +static struct pci_controller bcm47xx_sb_pci_controller = {
13050 + .pci_ops = &sb_pci_ops,
13051 + .mem_resource = &sb_pci_mem_resource,
13052 + .io_resource = &sb_pci_io_resource,
13053 +};
13054 +
13055 +static struct resource ext_pci_mem_resource = {
13056 + .name = "Ext PCI Memory resources",
13057 + .start = SB_PCI_DMA,
13058 +// .end = 0x7FFFFFFF,
13059 + .end = 0x40FFFFFF,
13060 + .flags = IORESOURCE_MEM,
13061 +};
13062 +
13063 +static struct resource ext_pci_io_resource = {
13064 + .name = "Ext PCI I/O resources",
13065 + .start = 0x200,
13066 + .end = 0x2FF,
13067 + .flags = IORESOURCE_IO,
13068 +};
13069 +
13070 +static struct pci_controller bcm47xx_ext_pci_controller = {
13071 + .pci_ops = &sb_pci_ops,
13072 + .mem_resource = &ext_pci_mem_resource,
13073 + .io_resource = &ext_pci_io_resource,
13074 +};
13075 +
13076 +static int __init bcm47xx_pci_init(void)
13077 +{
13078 + register_pci_controller(&bcm47xx_sb_pci_controller);
13079 + register_pci_controller(&bcm47xx_ext_pci_controller);
13080 + return 0;
13081 +}
13082 +
13083 +early_initcall(bcm47xx_pci_init);
13084 diff -Nur linux-2.6.12.5/arch/mips/pci/pci.c linux-2.6.12.5-brcm/arch/mips/pci/pci.c
13085 --- linux-2.6.12.5/arch/mips/pci/pci.c 2005-08-15 02:20:18.000000000 +0200
13086 +++ linux-2.6.12.5-brcm/arch/mips/pci/pci.c 2005-08-28 11:12:20.629828904 +0200
13087 @@ -238,7 +238,8 @@
13088 if (dev->resource[i].flags & IORESOURCE_IO)
13089 offset = hose->io_offset;
13090 else if (dev->resource[i].flags & IORESOURCE_MEM)
13091 - offset = hose->mem_offset;
13092 + offset = 0x26000000;
13093 + // offset = hose->mem_offset;
13094
13095 dev->resource[i].start += offset;
13096 dev->resource[i].end += offset;
13097 diff -Nur linux-2.6.12.5/drivers/mtd/maps/Kconfig linux-2.6.12.5-brcm/drivers/mtd/maps/Kconfig
13098 --- linux-2.6.12.5/drivers/mtd/maps/Kconfig 2005-08-15 02:20:18.000000000 +0200
13099 +++ linux-2.6.12.5-brcm/drivers/mtd/maps/Kconfig 2005-08-28 16:21:23.595930936 +0200
13100 @@ -357,6 +357,12 @@
13101 Mapping for the Flaga digital module. If you don't have one, ignore
13102 this setting.
13103
13104 +config MTD_BCM47XX
13105 + tristate "BCM47xx flash device"
13106 + depends on MIPS && MTD_CFI && BCM947XX
13107 + help
13108 + Support for the flash chips on the BCM947xx board.
13109 +
13110 config MTD_BEECH
13111 tristate "CFI Flash device mapped on IBM 405LP Beech"
13112 depends on MTD_CFI && PPC32 && 40x && BEECH
13113 diff -Nur linux-2.6.12.5/drivers/mtd/maps/Makefile linux-2.6.12.5-brcm/drivers/mtd/maps/Makefile
13114 --- linux-2.6.12.5/drivers/mtd/maps/Makefile 2005-08-15 02:20:18.000000000 +0200
13115 +++ linux-2.6.12.5-brcm/drivers/mtd/maps/Makefile 2005-08-28 11:12:20.666823280 +0200
13116 @@ -31,6 +31,7 @@
13117 obj-$(CONFIG_MTD_PCMCIA) += pcmciamtd.o
13118 obj-$(CONFIG_MTD_RPXLITE) += rpxlite.o
13119 obj-$(CONFIG_MTD_TQM8XXL) += tqm8xxl.o
13120 +obj-$(CONFIG_MTD_BCM47XX) += bcm47xx-flash.o
13121 obj-$(CONFIG_MTD_SA1100) += sa1100-flash.o
13122 obj-$(CONFIG_MTD_IPAQ) += ipaq-flash.o
13123 obj-$(CONFIG_MTD_SBC_GXX) += sbc_gxx.o
13124 diff -Nur linux-2.6.12.5/drivers/mtd/maps/bcm47xx-flash.c linux-2.6.12.5-brcm/drivers/mtd/maps/bcm47xx-flash.c
13125 --- linux-2.6.12.5/drivers/mtd/maps/bcm47xx-flash.c 1970-01-01 01:00:00.000000000 +0100
13126 +++ linux-2.6.12.5-brcm/drivers/mtd/maps/bcm47xx-flash.c 2005-08-28 17:01:50.948899632 +0200
13127 @@ -0,0 +1,131 @@
13128 +/*
13129 + * Flash mapping for BCM947XX boards
13130 + *
13131 + * Copyright (C) 2001 Broadcom Corporation
13132 + *
13133 + * $Id: bcm47xx-flash.c,v 1.1 2004/10/21 07:18:31 jolt Exp $
13134 + */
13135 +
13136 +#include <linux/init.h>
13137 +#include <linux/module.h>
13138 +#include <linux/types.h>
13139 +#include <linux/kernel.h>
13140 +#include <asm/io.h>
13141 +#include <linux/mtd/mtd.h>
13142 +#include <linux/mtd/map.h>
13143 +#include <linux/mtd/partitions.h>
13144 +#include <linux/config.h>
13145 +
13146 +#define WINDOW_ADDR 0x1c000000
13147 +#define WINDOW_SIZE (0x400000*2)
13148 +#define BUSWIDTH 2
13149 +
13150 +static struct mtd_info *bcm947xx_mtd;
13151 +
13152 +static void bcm947xx_map_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
13153 +{
13154 +#define MIPS_MEMCPY_ALIGN 4
13155 + map_word ret;
13156 + ssize_t transfer;
13157 + ssize_t done = 0;
13158 + if ((len >= MIPS_MEMCPY_ALIGN) && (!(from & (MIPS_MEMCPY_ALIGN - 1))) && (!(((unsigned int)to & (MIPS_MEMCPY_ALIGN - 1))))) {
13159 + done = len & ~(MIPS_MEMCPY_ALIGN - 1);
13160 + memcpy_fromio(to, map->virt + from, done);
13161 + }
13162 + while (done < len) {
13163 + ret = map->read(map, from + done);
13164 + transfer = len - done;
13165 + if (transfer > map->bankwidth)
13166 + transfer = map->bankwidth;
13167 + memcpy((void *)((unsigned long)to + done), &ret.x[0], transfer);
13168 + done += transfer;
13169 + }
13170 +}
13171 +
13172 +static struct map_info bcm947xx_map = {
13173 + name: "Physically mapped flash",
13174 + size: WINDOW_SIZE,
13175 + bankwidth: BUSWIDTH,
13176 + phys: WINDOW_ADDR,
13177 +};
13178 +
13179 +#define SECTORS *64*1024
13180 +
13181 +#ifdef CONFIG_MTD_PARTITIONS
13182 +#if 0
13183 +static struct mtd_partition bcm947xx_parts[] = {
13184 +// 64 - 4 - 14 - 1 = 45 = 8 + 37
13185 + { name: "pmon", offset: 0, size: 4 SECTORS, mask_flags: MTD_WRITEABLE },
13186 + { name: "linux", offset: MTDPART_OFS_APPEND, size: 14 SECTORS },
13187 + { name: "rescue", offset: MTDPART_OFS_APPEND, size: 8 SECTORS },
13188 + { name: "rootfs", offset: MTDPART_OFS_APPEND, size: 37 SECTORS },
13189 + { name: "nvram", offset: MTDPART_OFS_APPEND, size: 1 SECTORS, mask_flags: MTD_WRITEABLE },
13190 +};
13191 +#else
13192 +static struct mtd_partition bcm947xx_parts[] = {
13193 + { name: "cfe",
13194 + offset: 0,
13195 + size: 384*1024,
13196 + mask_flags: MTD_WRITEABLE
13197 + },
13198 + { name: "config",
13199 + offset: MTDPART_OFS_APPEND,
13200 + size: 128*1024
13201 + },
13202 + { name: "linux",
13203 + offset: MTDPART_OFS_APPEND,
13204 + size: 10*128*1024
13205 + },
13206 + { name: "jffs",
13207 + offset: MTDPART_OFS_APPEND,
13208 + size: (8*1024*1024)-((384*1024)+(128*1024)+(10*128*1024)+(128*1024)),
13209 + },
13210 + { name: "nvram",
13211 + offset: MTDPART_OFS_APPEND,
13212 + size: 128*1024,
13213 + mask_flags: MTD_WRITEABLE
13214 + },
13215 +};
13216 +#endif
13217 +#endif
13218 +
13219 +int __init init_bcm947xx_map(void)
13220 +{
13221 + bcm947xx_map.virt = (unsigned long)ioremap(WINDOW_ADDR, WINDOW_SIZE);
13222 +
13223 + if (!bcm947xx_map.virt) {
13224 + printk("Failed to ioremap\n");
13225 + return -EIO;
13226 + }
13227 + simple_map_init(&bcm947xx_map);
13228 +
13229 + bcm947xx_map.copy_from = bcm947xx_map_copy_from;
13230 +
13231 + if (!(bcm947xx_mtd = do_map_probe("cfi_probe", &bcm947xx_map))) {
13232 + printk("Failed to do_map_probe\n");
13233 + iounmap((void *)bcm947xx_map.virt);
13234 + return -ENXIO;
13235 + }
13236 +
13237 + bcm947xx_mtd->owner = THIS_MODULE;
13238 +
13239 + printk(KERN_NOTICE "flash device: %x at %x\n", bcm947xx_mtd->size, WINDOW_ADDR);
13240 +
13241 +#ifdef CONFIG_MTD_PARTITIONS
13242 + return add_mtd_partitions(bcm947xx_mtd, bcm947xx_parts, sizeof(bcm947xx_parts)/sizeof(bcm947xx_parts[0]));
13243 +#else
13244 + return 0;
13245 +#endif
13246 +}
13247 +
13248 +void __exit cleanup_bcm947xx_map(void)
13249 +{
13250 +#ifdef CONFIG_MTD_PARTITIONS
13251 + del_mtd_partitions(bcm947xx_mtd);
13252 +#endif
13253 + map_destroy(bcm947xx_mtd);
13254 + iounmap((void *)bcm947xx_map.virt);
13255 +}
13256 +
13257 +module_init(init_bcm947xx_map);
13258 +module_exit(cleanup_bcm947xx_map);
13259 diff -Nur linux-2.6.12.5/drivers/net/b44.c linux-2.6.12.5-brcm/drivers/net/b44.c
13260 --- linux-2.6.12.5/drivers/net/b44.c 2005-08-15 02:20:18.000000000 +0200
13261 +++ linux-2.6.12.5-brcm/drivers/net/b44.c 2005-08-28 11:12:20.691819480 +0200
13262 @@ -1,7 +1,8 @@
13263 -/* b44.c: Broadcom 4400 device driver.
13264 +/* b44.c: Broadcom 4400/47xx device driver.
13265 *
13266 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
13267 - * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
13268 + * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
13269 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
13270 *
13271 * Distribute under GPL.
13272 */
13273 @@ -78,7 +79,7 @@
13274 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
13275
13276 MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
13277 -MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
13278 +MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver");
13279 MODULE_LICENSE("GPL");
13280 MODULE_VERSION(DRV_MODULE_VERSION);
13281
13282 @@ -93,6 +94,8 @@
13283 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
13284 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
13285 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
13286 + { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4713,
13287 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
13288 { } /* terminate list with empty entry */
13289 };
13290
13291 @@ -106,24 +109,13 @@
13292 static void b44_poll_controller(struct net_device *dev);
13293 #endif
13294
13295 -static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
13296 -{
13297 - return readl(bp->regs + reg);
13298 -}
13299 -
13300 -static inline void bw32(const struct b44 *bp,
13301 - unsigned long reg, unsigned long val)
13302 -{
13303 - writel(val, bp->regs + reg);
13304 -}
13305 -
13306 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
13307 u32 bit, unsigned long timeout, const int clear)
13308 {
13309 unsigned long i;
13310
13311 for (i = 0; i < timeout; i++) {
13312 - u32 val = br32(bp, reg);
13313 + u32 val = br32(reg);
13314
13315 if (clear && !(val & bit))
13316 break;
13317 @@ -154,7 +146,7 @@
13318
13319 static u32 ssb_get_core_rev(struct b44 *bp)
13320 {
13321 - return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
13322 + return (br32(B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
13323 }
13324
13325 static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
13326 @@ -165,13 +157,13 @@
13327 pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
13328 pci_rev = ssb_get_core_rev(bp);
13329
13330 - val = br32(bp, B44_SBINTVEC);
13331 + val = br32(B44_SBINTVEC);
13332 val |= cores;
13333 - bw32(bp, B44_SBINTVEC, val);
13334 + bw32(B44_SBINTVEC, val);
13335
13336 - val = br32(bp, SSB_PCI_TRANS_2);
13337 + val = br32(SSB_PCI_TRANS_2);
13338 val |= SSB_PCI_PREF | SSB_PCI_BURST;
13339 - bw32(bp, SSB_PCI_TRANS_2, val);
13340 + bw32(SSB_PCI_TRANS_2, val);
13341
13342 pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
13343
13344 @@ -180,18 +172,18 @@
13345
13346 static void ssb_core_disable(struct b44 *bp)
13347 {
13348 - if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
13349 + if (br32(B44_SBTMSLOW) & SBTMSLOW_RESET)
13350 return;
13351
13352 - bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
13353 + bw32(B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
13354 b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
13355 b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
13356 - bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
13357 + bw32(B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
13358 SBTMSLOW_REJECT | SBTMSLOW_RESET));
13359 - br32(bp, B44_SBTMSLOW);
13360 + br32(B44_SBTMSLOW);
13361 udelay(1);
13362 - bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
13363 - br32(bp, B44_SBTMSLOW);
13364 + bw32(B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
13365 + br32(B44_SBTMSLOW);
13366 udelay(1);
13367 }
13368
13369 @@ -200,58 +192,65 @@
13370 u32 val;
13371
13372 ssb_core_disable(bp);
13373 - bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
13374 - br32(bp, B44_SBTMSLOW);
13375 + bw32(B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
13376 + br32(B44_SBTMSLOW);
13377 udelay(1);
13378
13379 /* Clear SERR if set, this is a hw bug workaround. */
13380 - if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
13381 - bw32(bp, B44_SBTMSHIGH, 0);
13382 + if (br32(B44_SBTMSHIGH) & SBTMSHIGH_SERR)
13383 + bw32(B44_SBTMSHIGH, 0);
13384
13385 - val = br32(bp, B44_SBIMSTATE);
13386 + val = br32(B44_SBIMSTATE);
13387 if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
13388 - bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
13389 + bw32(B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
13390
13391 - bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
13392 - br32(bp, B44_SBTMSLOW);
13393 + bw32(B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
13394 + br32(B44_SBTMSLOW);
13395 udelay(1);
13396
13397 - bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
13398 - br32(bp, B44_SBTMSLOW);
13399 + bw32(B44_SBTMSLOW, (SBTMSLOW_CLOCK));
13400 + br32(B44_SBTMSLOW);
13401 udelay(1);
13402 }
13403
13404 +static int b44_4713_instance;
13405 +
13406 static int ssb_core_unit(struct b44 *bp)
13407 {
13408 -#if 0
13409 - u32 val = br32(bp, B44_SBADMATCH0);
13410 - u32 base;
13411 -
13412 - type = val & SBADMATCH0_TYPE_MASK;
13413 - switch (type) {
13414 - case 0:
13415 - base = val & SBADMATCH0_BS0_MASK;
13416 - break;
13417 -
13418 - case 1:
13419 - base = val & SBADMATCH0_BS1_MASK;
13420 - break;
13421 -
13422 - case 2:
13423 - default:
13424 - base = val & SBADMATCH0_BS2_MASK;
13425 - break;
13426 - };
13427 -#endif
13428 - return 0;
13429 + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
13430 + return b44_4713_instance++;
13431 + else
13432 + return 0;
13433 }
13434
13435 static int ssb_is_core_up(struct b44 *bp)
13436 {
13437 - return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
13438 + return ((br32(B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
13439 == SBTMSLOW_CLOCK);
13440 }
13441
13442 +static void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
13443 +{
13444 + u32 val;
13445 +
13446 + bw32(B44_CAM_CTRL, (CAM_CTRL_READ |
13447 + (index << CAM_CTRL_INDEX_SHIFT)));
13448 +
13449 + b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
13450 +
13451 + val = br32(B44_CAM_DATA_LO);
13452 +
13453 + data[2] = (val >> 24) & 0xFF;
13454 + data[3] = (val >> 16) & 0xFF;
13455 + data[4] = (val >> 8) & 0xFF;
13456 + data[5] = (val >> 0) & 0xFF;
13457 +
13458 + val = br32(B44_CAM_DATA_HI);
13459 +
13460 + data[0] = (val >> 8) & 0xFF;
13461 + data[1] = (val >> 0) & 0xFF;
13462 +}
13463 +
13464 static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
13465 {
13466 u32 val;
13467 @@ -260,19 +259,19 @@
13468 val |= ((u32) data[3]) << 16;
13469 val |= ((u32) data[4]) << 8;
13470 val |= ((u32) data[5]) << 0;
13471 - bw32(bp, B44_CAM_DATA_LO, val);
13472 + bw32(B44_CAM_DATA_LO, val);
13473 val = (CAM_DATA_HI_VALID |
13474 (((u32) data[0]) << 8) |
13475 (((u32) data[1]) << 0));
13476 - bw32(bp, B44_CAM_DATA_HI, val);
13477 - bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
13478 + bw32(B44_CAM_DATA_HI, val);
13479 + bw32(B44_CAM_CTRL, (CAM_CTRL_WRITE |
13480 (index << CAM_CTRL_INDEX_SHIFT)));
13481 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
13482 }
13483
13484 static inline void __b44_disable_ints(struct b44 *bp)
13485 {
13486 - bw32(bp, B44_IMASK, 0);
13487 + bw32(B44_IMASK, 0);
13488 }
13489
13490 static void b44_disable_ints(struct b44 *bp)
13491 @@ -280,34 +279,40 @@
13492 __b44_disable_ints(bp);
13493
13494 /* Flush posted writes. */
13495 - br32(bp, B44_IMASK);
13496 + br32(B44_IMASK);
13497 }
13498
13499 static void b44_enable_ints(struct b44 *bp)
13500 {
13501 - bw32(bp, B44_IMASK, bp->imask);
13502 + bw32(B44_IMASK, bp->imask);
13503 }
13504
13505 static int b44_readphy(struct b44 *bp, int reg, u32 *val)
13506 {
13507 int err;
13508
13509 - bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
13510 - bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
13511 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
13512 + return 0;
13513 +
13514 + bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
13515 + bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
13516 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
13517 (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
13518 (reg << MDIO_DATA_RA_SHIFT) |
13519 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
13520 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
13521 - *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
13522 + *val = br32(B44_MDIO_DATA) & MDIO_DATA_DATA;
13523
13524 return err;
13525 }
13526
13527 static int b44_writephy(struct b44 *bp, int reg, u32 val)
13528 {
13529 - bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
13530 - bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
13531 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
13532 + return 0;
13533 +
13534 + bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
13535 + bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
13536 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
13537 (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
13538 (reg << MDIO_DATA_RA_SHIFT) |
13539 @@ -344,6 +349,9 @@
13540 u32 val;
13541 int err;
13542
13543 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
13544 + return 0;
13545 +
13546 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
13547 if (err)
13548 return err;
13549 @@ -367,20 +375,20 @@
13550 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
13551 bp->flags |= pause_flags;
13552
13553 - val = br32(bp, B44_RXCONFIG);
13554 + val = br32(B44_RXCONFIG);
13555 if (pause_flags & B44_FLAG_RX_PAUSE)
13556 val |= RXCONFIG_FLOW;
13557 else
13558 val &= ~RXCONFIG_FLOW;
13559 - bw32(bp, B44_RXCONFIG, val);
13560 + bw32(B44_RXCONFIG, val);
13561
13562 - val = br32(bp, B44_MAC_FLOW);
13563 + val = br32(B44_MAC_FLOW);
13564 if (pause_flags & B44_FLAG_TX_PAUSE)
13565 val |= (MAC_FLOW_PAUSE_ENAB |
13566 (0xc0 & MAC_FLOW_RX_HI_WATER));
13567 else
13568 val &= ~MAC_FLOW_PAUSE_ENAB;
13569 - bw32(bp, B44_MAC_FLOW, val);
13570 + bw32(B44_MAC_FLOW, val);
13571 }
13572
13573 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
13574 @@ -414,6 +422,9 @@
13575 u32 val;
13576 int err;
13577
13578 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
13579 + return 0;
13580 +
13581 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
13582 goto out;
13583 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
13584 @@ -476,11 +487,11 @@
13585
13586 val = &bp->hw_stats.tx_good_octets;
13587 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
13588 - *val++ += br32(bp, reg);
13589 + *val++ += br32(reg);
13590 }
13591 val = &bp->hw_stats.rx_good_octets;
13592 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
13593 - *val++ += br32(bp, reg);
13594 + *val++ += br32(reg);
13595 }
13596 }
13597
13598 @@ -506,6 +517,19 @@
13599 {
13600 u32 bmsr, aux;
13601
13602 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
13603 + bp->flags |= B44_FLAG_100_BASE_T;
13604 + bp->flags |= B44_FLAG_FULL_DUPLEX;
13605 + if (!netif_carrier_ok(bp->dev)) {
13606 + u32 val = br32(B44_TX_CTRL);
13607 + val |= TX_CTRL_DUPLEX;
13608 + bw32(B44_TX_CTRL, val);
13609 + netif_carrier_on(bp->dev);
13610 + b44_link_report(bp);
13611 + }
13612 + return;
13613 + }
13614 +
13615 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
13616 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
13617 (bmsr != 0xffff)) {
13618 @@ -520,14 +544,14 @@
13619
13620 if (!netif_carrier_ok(bp->dev) &&
13621 (bmsr & BMSR_LSTATUS)) {
13622 - u32 val = br32(bp, B44_TX_CTRL);
13623 + u32 val = br32(B44_TX_CTRL);
13624 u32 local_adv, remote_adv;
13625
13626 if (bp->flags & B44_FLAG_FULL_DUPLEX)
13627 val |= TX_CTRL_DUPLEX;
13628 else
13629 val &= ~TX_CTRL_DUPLEX;
13630 - bw32(bp, B44_TX_CTRL, val);
13631 + bw32(B44_TX_CTRL, val);
13632
13633 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
13634 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
13635 @@ -572,7 +596,7 @@
13636 {
13637 u32 cur, cons;
13638
13639 - cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
13640 + cur = br32(B44_DMATX_STAT) & DMATX_STAT_CDMASK;
13641 cur /= sizeof(struct dma_desc);
13642
13643 /* XXX needs updating when NETIF_F_SG is supported */
13644 @@ -596,7 +620,7 @@
13645 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
13646 netif_wake_queue(bp->dev);
13647
13648 - bw32(bp, B44_GPTIMER, 0);
13649 + bw32(B44_GPTIMER, 0);
13650 }
13651
13652 /* Works like this. This chip writes a 'struct rx_header" 30 bytes
13653 @@ -713,7 +737,7 @@
13654 u32 cons, prod;
13655
13656 received = 0;
13657 - prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
13658 + prod = br32(B44_DMARX_STAT) & DMARX_STAT_CDMASK;
13659 prod /= sizeof(struct dma_desc);
13660 cons = bp->rx_cons;
13661
13662 @@ -792,7 +816,7 @@
13663 }
13664
13665 bp->rx_cons = cons;
13666 - bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
13667 + bw32(B44_DMARX_PTR, cons * sizeof(struct dma_desc));
13668
13669 return received;
13670 }
13671 @@ -856,8 +880,8 @@
13672
13673 spin_lock_irqsave(&bp->lock, flags);
13674
13675 - istat = br32(bp, B44_ISTAT);
13676 - imask = br32(bp, B44_IMASK);
13677 + istat = br32(B44_ISTAT);
13678 + imask = br32(B44_IMASK);
13679
13680 /* ??? What the fuck is the purpose of the interrupt mask
13681 * ??? register if we have to mask it out by hand anyways?
13682 @@ -877,8 +901,8 @@
13683 dev->name);
13684 }
13685
13686 - bw32(bp, B44_ISTAT, istat);
13687 - br32(bp, B44_ISTAT);
13688 + bw32(B44_ISTAT, istat);
13689 + br32(B44_ISTAT);
13690 }
13691 spin_unlock_irqrestore(&bp->lock, flags);
13692 return IRQ_RETVAL(handled);
13693 @@ -965,11 +989,11 @@
13694
13695 wmb();
13696
13697 - bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
13698 + bw32(B44_DMATX_PTR, entry * sizeof(struct dma_desc));
13699 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
13700 - bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
13701 + bw32(B44_DMATX_PTR, entry * sizeof(struct dma_desc));
13702 if (bp->flags & B44_FLAG_REORDER_BUG)
13703 - br32(bp, B44_DMATX_PTR);
13704 + br32(B44_DMATX_PTR);
13705
13706 if (TX_BUFFS_AVAIL(bp) < 1)
13707 netif_stop_queue(dev);
13708 @@ -1137,32 +1161,35 @@
13709 {
13710 unsigned long reg;
13711
13712 - bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
13713 + bw32(B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
13714 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
13715 - br32(bp, reg);
13716 + br32(reg);
13717 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
13718 - br32(bp, reg);
13719 + br32(reg);
13720 }
13721
13722 /* bp->lock is held. */
13723 static void b44_chip_reset(struct b44 *bp)
13724 {
13725 + unsigned int sb_clock;
13726 +
13727 if (ssb_is_core_up(bp)) {
13728 - bw32(bp, B44_RCV_LAZY, 0);
13729 - bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
13730 + bw32(B44_RCV_LAZY, 0);
13731 + bw32(B44_ENET_CTRL, ENET_CTRL_DISABLE);
13732 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
13733 - bw32(bp, B44_DMATX_CTRL, 0);
13734 + bw32(B44_DMATX_CTRL, 0);
13735 bp->tx_prod = bp->tx_cons = 0;
13736 - if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
13737 + if (br32(B44_DMARX_STAT) & DMARX_STAT_EMASK) {
13738 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
13739 100, 0);
13740 }
13741 - bw32(bp, B44_DMARX_CTRL, 0);
13742 + bw32(B44_DMARX_CTRL, 0);
13743 bp->rx_prod = bp->rx_cons = 0;
13744 } else {
13745 - ssb_pci_setup(bp, (bp->core_unit == 0 ?
13746 - SBINTVEC_ENET0 :
13747 - SBINTVEC_ENET1));
13748 + if (bp->pdev->device != PCI_DEVICE_ID_BCM4713)
13749 + ssb_pci_setup(bp, (bp->core_unit == 0 ?
13750 + SBINTVEC_ENET0 :
13751 + SBINTVEC_ENET1));
13752 }
13753
13754 ssb_core_reset(bp);
13755 @@ -1170,20 +1197,26 @@
13756 b44_clear_stats(bp);
13757
13758 /* Make PHY accessible. */
13759 - bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
13760 - (0x0d & MDIO_CTRL_MAXF_MASK)));
13761 - br32(bp, B44_MDIO_CTRL);
13762 -
13763 - if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
13764 - bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
13765 - br32(bp, B44_ENET_CTRL);
13766 + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
13767 + sb_clock = 100000000; /* 100 MHz */
13768 + else
13769 + sb_clock = 62500000; /* 62.5 MHz */
13770 +
13771 + bw32(B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
13772 + (((sb_clock + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO)
13773 + & MDIO_CTRL_MAXF_MASK)));
13774 + br32(B44_MDIO_CTRL);
13775 +
13776 + if (!(br32(B44_DEVCTRL) & DEVCTRL_IPP)) {
13777 + bw32(B44_ENET_CTRL, ENET_CTRL_EPSEL);
13778 + br32(B44_ENET_CTRL);
13779 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
13780 } else {
13781 - u32 val = br32(bp, B44_DEVCTRL);
13782 + u32 val = br32(B44_DEVCTRL);
13783
13784 if (val & DEVCTRL_EPR) {
13785 - bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
13786 - br32(bp, B44_DEVCTRL);
13787 + bw32(B44_DEVCTRL, (val & ~DEVCTRL_EPR));
13788 + br32(B44_DEVCTRL);
13789 udelay(100);
13790 }
13791 bp->flags |= B44_FLAG_INTERNAL_PHY;
13792 @@ -1200,13 +1233,13 @@
13793 /* bp->lock is held. */
13794 static void __b44_set_mac_addr(struct b44 *bp)
13795 {
13796 - bw32(bp, B44_CAM_CTRL, 0);
13797 + bw32(B44_CAM_CTRL, 0);
13798 if (!(bp->dev->flags & IFF_PROMISC)) {
13799 u32 val;
13800
13801 __b44_cam_write(bp, bp->dev->dev_addr, 0);
13802 - val = br32(bp, B44_CAM_CTRL);
13803 - bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
13804 + val = br32(B44_CAM_CTRL);
13805 + bw32(B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
13806 }
13807 }
13808
13809 @@ -1240,30 +1273,30 @@
13810 b44_setup_phy(bp);
13811
13812 /* Enable CRC32, set proper LED modes and power on PHY */
13813 - bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
13814 - bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
13815 + bw32(B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
13816 + bw32(B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
13817
13818 /* This sets the MAC address too. */
13819 __b44_set_rx_mode(bp->dev);
13820
13821 /* MTU + eth header + possible VLAN tag + struct rx_header */
13822 - bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
13823 - bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
13824 + bw32(B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
13825 + bw32(B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
13826
13827 - bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
13828 - bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
13829 - bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
13830 - bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
13831 + bw32(B44_TX_WMARK, 56); /* XXX magic */
13832 + bw32(B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
13833 + bw32(B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
13834 + bw32(B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
13835 (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
13836 - bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
13837 + bw32(B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
13838
13839 - bw32(bp, B44_DMARX_PTR, bp->rx_pending);
13840 + bw32(B44_DMARX_PTR, bp->rx_pending);
13841 bp->rx_prod = bp->rx_pending;
13842
13843 - bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
13844 + bw32(B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
13845
13846 - val = br32(bp, B44_ENET_CTRL);
13847 - bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
13848 + val = br32(B44_ENET_CTRL);
13849 + bw32(B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
13850 }
13851
13852 static int b44_open(struct net_device *dev)
13853 @@ -1416,11 +1449,11 @@
13854 int i=0;
13855 unsigned char zero[6] = {0,0,0,0,0,0};
13856
13857 - val = br32(bp, B44_RXCONFIG);
13858 + val = br32(B44_RXCONFIG);
13859 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
13860 if (dev->flags & IFF_PROMISC) {
13861 val |= RXCONFIG_PROMISC;
13862 - bw32(bp, B44_RXCONFIG, val);
13863 + bw32(B44_RXCONFIG, val);
13864 } else {
13865 __b44_set_mac_addr(bp);
13866
13867 @@ -1432,9 +1465,9 @@
13868 for(;i<64;i++) {
13869 __b44_cam_write(bp, zero, i);
13870 }
13871 - bw32(bp, B44_RXCONFIG, val);
13872 - val = br32(bp, B44_CAM_CTRL);
13873 - bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
13874 + bw32(B44_RXCONFIG, val);
13875 + val = br32(B44_CAM_CTRL);
13876 + bw32(B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
13877 }
13878 }
13879
13880 @@ -1704,19 +1737,41 @@
13881 {
13882 u8 eeprom[128];
13883 int err;
13884 + unsigned long flags;
13885
13886 - err = b44_read_eeprom(bp, &eeprom[0]);
13887 - if (err)
13888 - goto out;
13889 -
13890 - bp->dev->dev_addr[0] = eeprom[79];
13891 - bp->dev->dev_addr[1] = eeprom[78];
13892 - bp->dev->dev_addr[2] = eeprom[81];
13893 - bp->dev->dev_addr[3] = eeprom[80];
13894 - bp->dev->dev_addr[4] = eeprom[83];
13895 - bp->dev->dev_addr[5] = eeprom[82];
13896 -
13897 - bp->phy_addr = eeprom[90] & 0x1f;
13898 + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) {
13899 + /*
13900 + * BCM47xx boards don't have a EEPROM. The MAC is stored in
13901 + * a NVRAM area somewhere in the flash memory. As we don't
13902 + * know the location and/or the format of the NVRAM area
13903 + * here, we simply rely on the bootloader to write the
13904 + * MAC into the CAM.
13905 + */
13906 + spin_lock_irqsave(&bp->lock, flags);
13907 + __b44_cam_read(bp, bp->dev->dev_addr, 0);
13908 + spin_unlock_irqrestore(&bp->lock, flags);
13909 +
13910 + /*
13911 + * BCM47xx boards don't have a PHY. Usually there is a switch
13912 + * chip with multiple PHYs connected to the PHY port.
13913 + */
13914 + bp->phy_addr = B44_PHY_ADDR_NO_PHY;
13915 + bp->dma_offset = 0;
13916 + } else {
13917 + err = b44_read_eeprom(bp, &eeprom[0]);
13918 + if (err)
13919 + return err;
13920 +
13921 + bp->dev->dev_addr[0] = eeprom[79];
13922 + bp->dev->dev_addr[1] = eeprom[78];
13923 + bp->dev->dev_addr[2] = eeprom[81];
13924 + bp->dev->dev_addr[3] = eeprom[80];
13925 + bp->dev->dev_addr[4] = eeprom[83];
13926 + bp->dev->dev_addr[5] = eeprom[82];
13927 +
13928 + bp->phy_addr = eeprom[90] & 0x1f;
13929 + bp->dma_offset = SB_PCI_DMA;
13930 + }
13931
13932 /* With this, plus the rx_header prepended to the data by the
13933 * hardware, we'll land the ethernet header on a 2-byte boundary.
13934 @@ -1726,13 +1781,12 @@
13935 bp->imask = IMASK_DEF;
13936
13937 bp->core_unit = ssb_core_unit(bp);
13938 - bp->dma_offset = SB_PCI_DMA;
13939
13940 /* XXX - really required?
13941 bp->flags |= B44_FLAG_BUGGY_TXPTR;
13942 */
13943 -out:
13944 - return err;
13945 +
13946 + return 0;
13947 }
13948
13949 static int __devinit b44_init_one(struct pci_dev *pdev,
13950 @@ -1810,7 +1864,7 @@
13951
13952 spin_lock_init(&bp->lock);
13953
13954 - bp->regs = ioremap(b44reg_base, b44reg_len);
13955 + bp->regs = (unsigned long) ioremap(b44reg_base, b44reg_len);
13956 if (bp->regs == 0UL) {
13957 printk(KERN_ERR PFX "Cannot map device registers, "
13958 "aborting.\n");
13959 @@ -1871,7 +1925,8 @@
13960
13961 pci_save_state(bp->pdev);
13962
13963 - printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
13964 + printk(KERN_INFO "%s: Broadcom %s 10/100BaseT Ethernet ", dev->name,
13965 + (pdev->device == PCI_DEVICE_ID_BCM4713) ? "47xx" : "4400");
13966 for (i = 0; i < 6; i++)
13967 printk("%2.2x%c", dev->dev_addr[i],
13968 i == 5 ? '\n' : ':');
13969 @@ -1879,7 +1934,7 @@
13970 return 0;
13971
13972 err_out_iounmap:
13973 - iounmap(bp->regs);
13974 + iounmap((void *) bp->regs);
13975
13976 err_out_free_dev:
13977 free_netdev(dev);
13978 @@ -1901,7 +1956,7 @@
13979 struct b44 *bp = netdev_priv(dev);
13980
13981 unregister_netdev(dev);
13982 - iounmap(bp->regs);
13983 + iounmap((void *) bp->regs);
13984 free_netdev(dev);
13985 pci_release_regions(pdev);
13986 pci_disable_device(pdev);
13987 diff -Nur linux-2.6.12.5/drivers/net/b44.h linux-2.6.12.5-brcm/drivers/net/b44.h
13988 --- linux-2.6.12.5/drivers/net/b44.h 2005-08-15 02:20:18.000000000 +0200
13989 +++ linux-2.6.12.5-brcm/drivers/net/b44.h 2005-08-28 11:12:20.694819024 +0200
13990 @@ -292,6 +292,9 @@
13991 #define SSB_PCI_MASK1 0xfc000000
13992 #define SSB_PCI_MASK2 0xc0000000
13993
13994 +#define br32(REG) readl(bp->regs + (REG))
13995 +#define bw32(REG,VAL) writel((VAL), bp->regs + (REG))
13996 +
13997 /* 4400 PHY registers */
13998 #define B44_MII_AUXCTRL 24 /* Auxiliary Control */
13999 #define MII_AUXCTRL_DUPLEX 0x0001 /* Full Duplex */
14000 @@ -345,6 +348,8 @@
14001 };
14002
14003 #define B44_MCAST_TABLE_SIZE 32
14004 +#define B44_PHY_ADDR_NO_PHY 30
14005 +#define B44_MDC_RATIO 5000000
14006
14007 /* SW copy of device statistics, kept up to date by periodic timer
14008 * which probes HW values. Must have same relative layout as HW
14009 @@ -410,7 +415,7 @@
14010 struct net_device_stats stats;
14011 struct b44_hw_stats hw_stats;
14012
14013 - void __iomem *regs;
14014 + unsigned long regs;
14015 struct pci_dev *pdev;
14016 struct net_device *dev;
14017
14018 diff -Nur linux-2.6.12.5/include/asm-mips/bootinfo.h linux-2.6.12.5-brcm/include/asm-mips/bootinfo.h
14019 --- linux-2.6.12.5/include/asm-mips/bootinfo.h 2005-08-15 02:20:18.000000000 +0200
14020 +++ linux-2.6.12.5-brcm/include/asm-mips/bootinfo.h 2005-08-28 11:12:20.695818872 +0200
14021 @@ -213,6 +213,12 @@
14022 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
14023 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
14024
14025 +/*
14026 + * Valid machtype for group Broadcom
14027 + */
14028 +#define MACH_GROUP_BRCM 23 /* Broadcom */
14029 +#define MACH_BCM47XX 1 /* Broadcom BCM47xx */
14030 +
14031 #define CL_SIZE COMMAND_LINE_SIZE
14032
14033 const char *get_system_type(void);
14034 diff -Nur linux-2.6.12.5/include/asm-mips/cpu.h linux-2.6.12.5-brcm/include/asm-mips/cpu.h
14035 --- linux-2.6.12.5/include/asm-mips/cpu.h 2005-08-15 02:20:18.000000000 +0200
14036 +++ linux-2.6.12.5-brcm/include/asm-mips/cpu.h 2005-08-28 11:12:20.695818872 +0200
14037 @@ -87,6 +87,13 @@
14038 #define PRID_IMP_SR71000 0x0400
14039
14040 /*
14041 + * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
14042 + */
14043 +
14044 +#define PRID_IMP_BCM4710 0x4000
14045 +#define PRID_IMP_BCM3302 0x9000
14046 +
14047 +/*
14048 * Definitions for 7:0 on legacy processors
14049 */
14050
14051 @@ -177,7 +184,9 @@
14052 #define CPU_VR4133 56
14053 #define CPU_AU1550 57
14054 #define CPU_24K 58
14055 -#define CPU_LAST 58
14056 +#define CPU_BCM3302 59
14057 +#define CPU_BCM4710 60
14058 +#define CPU_LAST 60
14059
14060 /*
14061 * ISA Level encodings
14062 diff -Nur linux-2.6.12.5/include/asm-mips/mipsregs.h linux-2.6.12.5-brcm/include/asm-mips/mipsregs.h
14063 --- linux-2.6.12.5/include/asm-mips/mipsregs.h 2005-08-15 02:20:18.000000000 +0200
14064 +++ linux-2.6.12.5-brcm/include/asm-mips/mipsregs.h 2005-08-28 11:12:20.722814768 +0200
14065 @@ -790,10 +790,18 @@
14066 #define read_c0_config1() __read_32bit_c0_register($16, 1)
14067 #define read_c0_config2() __read_32bit_c0_register($16, 2)
14068 #define read_c0_config3() __read_32bit_c0_register($16, 3)
14069 +#define read_c0_config4() __read_32bit_c0_register($16, 4)
14070 +#define read_c0_config5() __read_32bit_c0_register($16, 5)
14071 +#define read_c0_config6() __read_32bit_c0_register($16, 6)
14072 +#define read_c0_config7() __read_32bit_c0_register($16, 7)
14073 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
14074 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
14075 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
14076 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
14077 +#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
14078 +#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
14079 +#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
14080 +#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
14081
14082 /*
14083 * The WatchLo register. There may be upto 8 of them.
14084 diff -Nur linux-2.6.12.5/include/linux/init.h linux-2.6.12.5-brcm/include/linux/init.h
14085 --- linux-2.6.12.5/include/linux/init.h 2005-08-15 02:20:18.000000000 +0200
14086 +++ linux-2.6.12.5-brcm/include/linux/init.h 2005-08-28 11:12:20.723814616 +0200
14087 @@ -86,6 +86,8 @@
14088 static initcall_t __initcall_##fn __attribute_used__ \
14089 __attribute__((__section__(".initcall" level ".init"))) = fn
14090
14091 +#define early_initcall(fn) __define_initcall(".early1",fn)
14092 +
14093 #define core_initcall(fn) __define_initcall("1",fn)
14094 #define postcore_initcall(fn) __define_initcall("2",fn)
14095 #define arch_initcall(fn) __define_initcall("3",fn)
14096 diff -Nur linux-2.6.12.5/include/linux/pci_ids.h linux-2.6.12.5-brcm/include/linux/pci_ids.h
14097 --- linux-2.6.12.5/include/linux/pci_ids.h 2005-08-15 02:20:18.000000000 +0200
14098 +++ linux-2.6.12.5-brcm/include/linux/pci_ids.h 2005-08-28 11:12:20.726814160 +0200
14099 @@ -2110,6 +2110,7 @@
14100 #define PCI_DEVICE_ID_TIGON3_5901_2 0x170e
14101 #define PCI_DEVICE_ID_BCM4401 0x4401
14102 #define PCI_DEVICE_ID_BCM4401B0 0x4402
14103 +#define PCI_DEVICE_ID_BCM4713 0x4713
14104
14105 #define PCI_VENDOR_ID_TOPIC 0x151f
14106 #define PCI_DEVICE_ID_TOPIC_TP560 0x0000
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