target/linux/brcm47xx/patches-2.6.28/700-ssb-gigabit-ethernet-driver.patch

   1 diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
   2 --- a/drivers/net/tg3.c
   3 +++ b/drivers/net/tg3.c
   4 @@ -40,6 +40,7 @@
   5  #include <linux/workqueue.h>
   6  #include <linux/prefetch.h>
   7  #include <linux/dma-mapping.h>
   8 +#include <linux/ssb/ssb_driver_gige.h>
   9
  10  #include <net/checksum.h>
  11  #include <net/ip.h>
  12 @@ -428,8 +429,9 @@ static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
  13  static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
  14  {
  15         tp->write32_mbox(tp, off, val);
  16 -       if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
  17 -           !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
  18 +       if ((tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) ||
  19 +           (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
  20 +            !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)))
  21                 tp->read32_mbox(tp, off);
  22  }
  23
  24 @@ -439,7 +441,7 @@ static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
  25         writel(val, mbox);
  26         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
  27                 writel(val, mbox);
  28 -       if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  29 +       if ((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES))
  30                 readl(mbox);
  31  }
  32
  33 @@ -711,7 +713,7 @@ static void tg3_switch_clocks(struct tg3 *tp)
  34
  35  #define PHY_BUSY_LOOPS 5000
  36
  37 -static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  38 +static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val)
  39  {
  40         u32 frame_val;
  41         unsigned int loops;
  42 @@ -725,7 +727,7 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  43
  44         *val = 0x0;
  45
  46 -       frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
  47 +       frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  48                       MI_COM_PHY_ADDR_MASK);
  49         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  50                       MI_COM_REG_ADDR_MASK);
  51 @@ -760,7 +762,12 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  52         return ret;
  53  }
  54
  55 -static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  56 +static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  57 +{
  58 +       return __tg3_readphy(tp, PHY_ADDR, reg, val);
  59 +}
  60 +
  61 +static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val)
  62  {
  63         u32 frame_val;
  64         unsigned int loops;
  65 @@ -776,7 +783,7 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  66                 udelay(80);
  67         }
  68
  69 -       frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
  70 +       frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  71                       MI_COM_PHY_ADDR_MASK);
  72         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  73                       MI_COM_REG_ADDR_MASK);
  74 @@ -809,6 +816,11 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  75         return ret;
  76  }
  77
  78 +static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  79 +{
  80 +       return __tg3_writephy(tp, PHY_ADDR, reg, val);
  81 +}
  82 +
  83  static int tg3_bmcr_reset(struct tg3 *tp)
  84  {
  85         u32 phy_control;
  86 @@ -2232,8 +2244,10 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
  87         tg3_frob_aux_power(tp);
  88
  89         /* Workaround for unstable PLL clock */
  90 -       if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
  91 -           (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
  92 +       if ((tp->phy_id & PHY_ID_MASK != PHY_ID_BCM5750_2) &&
  93 +                               /* !!! FIXME !!! */
  94 +           ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
  95 +           (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
  96                 u32 val = tr32(0x7d00);
  97
  98                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
  99 @@ -2725,6 +2739,14 @@ relink:
 100
 101                 tg3_phy_copper_begin(tp);
 102
 103 +               if (tp->tg3_flags3 & TG3_FLG3_ROBOSWITCH) {
 104 +                       current_link_up = 1;
 105 +                       current_speed = SPEED_1000; //FIXME
 106 +                       current_duplex = DUPLEX_FULL;
 107 +                       tp->link_config.active_speed = current_speed;
 108 +                       tp->link_config.active_duplex = current_duplex;
 109 +               }
 110 +
 111                 tg3_readphy(tp, MII_BMSR, &tmp);
 112                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
 113                     (tmp & BMSR_LSTATUS))
 114 @@ -5659,6 +5681,11 @@ static int tg3_poll_fw(struct tg3 *tp)
 115         int i;
 116         u32 val;
 117
 118 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
 119 +               /* We don't use firmware. */
 120 +               return 0;
 121 +       }
 122 +
 123         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
 124                 /* Wait up to 20ms for init done. */
 125                 for (i = 0; i < 200; i++) {
 126 @@ -5902,6 +5929,14 @@ static int tg3_chip_reset(struct tg3 *tp)
 127                 tw32(0x5000, 0x400);
 128         }
 129
 130 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
 131 +               /* BCM4785: In order to avoid repercussions from using potentially
 132 +                * defective internal ROM, stop the Rx RISC CPU, which is not
 133 +                * required. */
 134 +               tg3_stop_fw(tp);
 135 +               tg3_halt_cpu(tp, RX_CPU_BASE);
 136 +       }
 137 +
 138         tw32(GRC_MODE, tp->grc_mode);
 139
 140         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
 141 @@ -6176,9 +6211,12 @@ static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
 142                 return -ENODEV;
 143         }
 144
 145 -       /* Clear firmware's nvram arbitration. */
 146 -       if (tp->tg3_flags & TG3_FLAG_NVRAM)
 147 -               tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
 148 +       if (!(tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)) {
 149 +               /* Clear firmware's nvram arbitration. */
 150 +               if (tp->tg3_flags & TG3_FLAG_NVRAM)
 151 +                       tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
 152 +       }
 153 +
 154         return 0;
 155  }
 156
 157 @@ -6259,6 +6297,11 @@ static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
 158         struct fw_info info;
 159         int err, i;
 160
 161 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
 162 +               /* We don't use firmware. */
 163 +               return 0;
 164 +       }
 165 +
 166         info.text_base = TG3_FW_TEXT_ADDR;
 167         info.text_len = TG3_FW_TEXT_LEN;
 168         info.text_data = &tg3FwText[0];
 169 @@ -6817,6 +6860,11 @@ static int tg3_load_tso_firmware(struct tg3 *tp)
 170         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
 171         int err, i;
 172
 173 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
 174 +               /* We don't use firmware. */
 175 +               return 0;
 176 +       }
 177 +
 178         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
 179                 return 0;
 180
 181 @@ -7776,6 +7824,11 @@ static void tg3_timer(unsigned long __opaque)
 182
 183         spin_lock(&tp->lock);
 184
 185 +       if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
 186 +               /* BCM4785: Flush posted writes from GbE to host memory. */
 187 +               tr32(HOSTCC_MODE);
 188 +       }
 189 +
 190         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
 191                 /* All of this garbage is because when using non-tagged
 192                  * IRQ status the mailbox/status_block protocol the chip
 193 @@ -9469,6 +9522,11 @@ static int tg3_test_nvram(struct tg3 *tp)
 194         __le32 *buf;
 195         int i, j, k, err = 0, size;
 196
 197 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
 198 +               /* We don't have NVRAM. */
 199 +               return 0;
 200 +       }
 201 +
 202         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
 203                 return -EIO;
 204
 205 @@ -10262,7 +10320,7 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 206                         return -EAGAIN;
 207
 208                 spin_lock_bh(&tp->lock);
 209 -               err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
 210 +               err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
 211                 spin_unlock_bh(&tp->lock);
 212
 213                 data->val_out = mii_regval;
 214 @@ -10281,7 +10339,7 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 215                         return -EAGAIN;
 216
 217                 spin_lock_bh(&tp->lock);
 218 -               err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
 219 +               err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
 220                 spin_unlock_bh(&tp->lock);
 221
 222                 return err;
 223 @@ -10759,6 +10817,12 @@ static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
 224  /* Chips other than 5700/5701 use the NVRAM for fetching info. */
 225  static void __devinit tg3_nvram_init(struct tg3 *tp)
 226  {
 227 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
 228 +               /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
 229 +               tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
 230 +               return;
 231 +       }
 232 +
 233         tw32_f(GRC_EEPROM_ADDR,
 234              (EEPROM_ADDR_FSM_RESET |
 235               (EEPROM_DEFAULT_CLOCK_PERIOD <<
 236 @@ -10900,6 +10964,9 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
 237  {
 238         int ret;
 239
 240 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
 241 +               return -ENODEV;
 242 +
 243         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
 244                 return tg3_nvram_read_using_eeprom(tp, offset, val);
 245
 246 @@ -11147,6 +11214,9 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
 247  {
 248         int ret;
 249
 250 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
 251 +               return -ENODEV;
 252 +
 253         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
 254                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
 255                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
 256 @@ -12205,7 +12275,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
 257                 tp->write32 = tg3_write_flush_reg32;
 258         }
 259
 260 -
 261         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
 262             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
 263                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
 264 @@ -12241,6 +12310,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
 265               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
 266                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
 267
 268 +       if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
 269 +               tp->write32_tx_mbox = tg3_write_flush_reg32;
 270 +               tp->write32_rx_mbox = tg3_write_flush_reg32;
 271 +       }
 272 +
 273         /* Get eeprom hw config before calling tg3_set_power_state().
 274          * In particular, the TG3_FLG2_IS_NIC flag must be
 275          * determined before calling tg3_set_power_state() so that
 276 @@ -12640,6 +12714,10 @@ static int __devinit tg3_get_device_address(struct tg3 *tp)
 277         }
 278
 279         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
 280 +               if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
 281 +                       ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
 282 +       }
 283 +       if (!is_valid_ether_addr(&dev->dev_addr[0])) {
 284  #ifdef CONFIG_SPARC
 285                 if (!tg3_get_default_macaddr_sparc(tp))
 286                         return 0;
 287 @@ -13131,6 +13209,7 @@ static char * __devinit tg3_phy_string(struct tg3 *tp)
 288         case PHY_ID_BCM5704:    return "5704";
 289         case PHY_ID_BCM5705:    return "5705";
 290         case PHY_ID_BCM5750:    return "5750";
 291 +       case PHY_ID_BCM5750_2:  return "5750-2";
 292         case PHY_ID_BCM5752:    return "5752";
 293         case PHY_ID_BCM5714:    return "5714";
 294         case PHY_ID_BCM5780:    return "5780";
 295 @@ -13317,6 +13396,13 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
 296                 tp->msg_enable = tg3_debug;
 297         else
 298                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
 299 +       if (pdev_is_ssb_gige_core(pdev)) {
 300 +               tp->tg3_flags3 |= TG3_FLG3_IS_SSB_CORE;
 301 +               if (ssb_gige_must_flush_posted_writes(pdev))
 302 +                       tp->tg3_flags3 |= TG3_FLG3_FLUSH_POSTED_WRITES;
 303 +               if (ssb_gige_have_roboswitch(pdev))
 304 +                       tp->tg3_flags3 |= TG3_FLG3_ROBOSWITCH;
 305 +       }
 306
 307         /* The word/byte swap controls here control register access byte
 308          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
 309 diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
 310 --- a/drivers/net/tg3.h
 311 +++ b/drivers/net/tg3.h
 312 @@ -2516,6 +2516,9 @@ struct tg3 {
 313  #define TG3_FLG3_RGMII_STD_IBND_DISABLE        0x00000100
 314  #define TG3_FLG3_RGMII_EXT_IBND_RX_EN  0x00000200
 315  #define TG3_FLG3_RGMII_EXT_IBND_TX_EN  0x00000400
 316 +#define TG3_FLG3_IS_SSB_CORE           0x00000800
 317 +#define TG3_FLG3_FLUSH_POSTED_WRITES   0x00001000
 318 +#define TG3_FLG3_ROBOSWITCH            0x00002000
 319
 320         struct timer_list               timer;
 321         u16                             timer_counter;
 322 @@ -2574,6 +2577,7 @@ struct tg3 {
 323  #define PHY_ID_BCM5714                 0x60008340
 324  #define PHY_ID_BCM5780                 0x60008350
 325  #define PHY_ID_BCM5755                 0xbc050cc0
 326 +#define PHY_ID_BCM5750_2               0xbc050cd0
 327  #define PHY_ID_BCM5787                 0xbc050ce0
 328  #define PHY_ID_BCM5756                 0xbc050ed0
 329  #define PHY_ID_BCM5784                 0xbc050fa0
 330 @@ -2613,7 +2617,7 @@ struct tg3 {
 331          (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
 332          (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
 333          (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
 334 -        (X) == PHY_ID_BCM8002)
 335 +        (X) == PHY_ID_BCM8002 || (X) == PHY_ID_BCM5750_2)
 336
 337         struct tg3_hw_stats             *hw_stats;
 338         dma_addr_t                      stats_mapping;