ar71xx: experimental 2.6.32 support
[openwrt.git] / target / linux / ifxmips / patches-2.6.30 / 130-ethernet.patch
1 Index: linux-2.6.30.8/drivers/net/Kconfig
2 ===================================================================
3 --- linux-2.6.30.8.orig/drivers/net/Kconfig 2009-10-19 21:31:30.000000000 +0200
4 +++ linux-2.6.30.8/drivers/net/Kconfig 2009-10-19 21:31:32.000000000 +0200
5 @@ -353,6 +353,12 @@
6
7 source "drivers/net/arm/Kconfig"
8
9 +config IFXMIPS_MII0
10 + tristate "Infineon IFXMips eth0 driver"
11 + depends on IFXMIPS
12 + help
13 + Support for the MII0 inside the IFXMips SOC
14 +
15 config AX88796
16 tristate "ASIX AX88796 NE2000 clone support"
17 depends on ARM || MIPS || SUPERH
18 Index: linux-2.6.30.8/drivers/net/Makefile
19 ===================================================================
20 --- linux-2.6.30.8.orig/drivers/net/Makefile 2009-10-19 21:31:30.000000000 +0200
21 +++ linux-2.6.30.8/drivers/net/Makefile 2009-10-19 21:31:32.000000000 +0200
22 @@ -234,6 +234,7 @@
23 obj-$(CONFIG_MLX4_CORE) += mlx4/
24 obj-$(CONFIG_ENC28J60) += enc28j60.o
25 obj-$(CONFIG_ETHOC) += ethoc.o
26 +obj-$(CONFIG_IFXMIPS_MII0) += ifxmips_mii0.o
27
28 obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o
29
30 Index: linux-2.6.30.8/drivers/net/ifxmips_mii0.c
31 ===================================================================
32 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
33 +++ linux-2.6.30.8/drivers/net/ifxmips_mii0.c 2009-10-19 21:41:10.000000000 +0200
34 @@ -0,0 +1,389 @@
35 +/*
36 + * This program is free software; you can redistribute it and/or modify
37 + * it under the terms of the GNU General Public License as published by
38 + * the Free Software Foundation; either version 2 of the License, or
39 + * (at your option) any later version.
40 + *
41 + * This program is distributed in the hope that it will be useful,
42 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
43 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
44 + * GNU General Public License for more details.
45 + *
46 + * You should have received a copy of the GNU General Public License
47 + * along with this program; if not, write to the Free Software
48 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
49 + *
50 + * Copyright (C) 2005 Wu Qi Ming <Qi-Ming.Wu@infineon.com>
51 + * Copyright (C) 2008 John Crispin <blogic@openwrt.org>
52 + */
53 +
54 +#include <linux/kernel.h>
55 +#include <linux/slab.h>
56 +#include <linux/errno.h>
57 +#include <linux/types.h>
58 +#include <linux/interrupt.h>
59 +#include <linux/uaccess.h>
60 +#include <linux/in.h>
61 +#include <linux/netdevice.h>
62 +#include <linux/etherdevice.h>
63 +#include <linux/ip.h>
64 +#include <linux/tcp.h>
65 +#include <linux/skbuff.h>
66 +#include <linux/mm.h>
67 +#include <linux/platform_device.h>
68 +#include <linux/ethtool.h>
69 +#include <linux/init.h>
70 +#include <linux/delay.h>
71 +
72 +#include <asm/checksum.h>
73 +
74 +#include <ifxmips.h>
75 +#include <ifxmips_dma.h>
76 +#include <ifxmips_pmu.h>
77 +
78 +struct ifxmips_mii_priv {
79 + struct net_device_stats stats;
80 + struct dma_device_info *dma_device;
81 + struct sk_buff *skb;
82 +};
83 +
84 +static struct net_device *ifxmips_mii0_dev;
85 +static unsigned char mac_addr[MAX_ADDR_LEN];
86 +
87 +void ifxmips_write_mdio(u32 phy_addr, u32 phy_reg, u16 phy_data)
88 +{
89 + u32 val = MDIO_ACC_REQUEST |
90 + ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
91 + ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) |
92 + phy_data;
93 +
94 + while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST)
95 + ;
96 + ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC);
97 +}
98 +EXPORT_SYMBOL(ifxmips_write_mdio);
99 +
100 +unsigned short ifxmips_read_mdio(u32 phy_addr, u32 phy_reg)
101 +{
102 + u32 val = MDIO_ACC_REQUEST | MDIO_ACC_READ |
103 + ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
104 + ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET);
105 +
106 + while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST)
107 + ;
108 + ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC);
109 + while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST)
110 + ;
111 + val = ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
112 + return val;
113 +}
114 +EXPORT_SYMBOL(ifxmips_read_mdio);
115 +
116 +int ifxmips_ifxmips_mii_open(struct net_device *dev)
117 +{
118 + struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)netdev_priv(dev);
119 + struct dma_device_info *dma_dev = priv->dma_device;
120 + int i;
121 +
122 + for (i = 0; i < dma_dev->max_rx_chan_num; i++) {
123 + if ((dma_dev->rx_chan[i])->control == IFXMIPS_DMA_CH_ON)
124 + (dma_dev->rx_chan[i])->open(dma_dev->rx_chan[i]);
125 + }
126 + netif_start_queue(dev);
127 + return 0;
128 +}
129 +
130 +int ifxmips_mii_release(struct net_device *dev)
131 +{
132 + struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)netdev_priv(dev);
133 + struct dma_device_info *dma_dev = priv->dma_device;
134 + int i;
135 +
136 + for (i = 0; i < dma_dev->max_rx_chan_num; i++)
137 + dma_dev->rx_chan[i]->close(dma_dev->rx_chan[i]);
138 + netif_stop_queue(dev);
139 + return 0;
140 +}
141 +
142 +int ifxmips_mii_hw_receive(struct net_device *dev, struct dma_device_info *dma_dev)
143 +{
144 + struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)netdev_priv(dev);
145 + unsigned char *buf = NULL;
146 + struct sk_buff *skb = NULL;
147 + int len = 0;
148 +
149 + len = dma_device_read(dma_dev, &buf, (void **)&skb);
150 +
151 + if (len >= ETHERNET_PACKET_DMA_BUFFER_SIZE) {
152 + printk(KERN_INFO "ifxmips_mii0: packet too large %d\n", len);
153 + goto ifxmips_mii_hw_receive_err_exit;
154 + }
155 +
156 + /* remove CRC */
157 + len -= 4;
158 + if (skb == NULL) {
159 + printk(KERN_INFO "ifxmips_mii0: cannot restore pointer\n");
160 + goto ifxmips_mii_hw_receive_err_exit;
161 + }
162 +
163 + if (len > (skb->end - skb->tail)) {
164 + printk(KERN_INFO "ifxmips_mii0: BUG, len:%d end:%p tail:%p\n",
165 + (len+4), skb->end, skb->tail);
166 + goto ifxmips_mii_hw_receive_err_exit;
167 + }
168 +
169 + skb_put(skb, len);
170 + skb->dev = dev;
171 + skb->protocol = eth_type_trans(skb, dev);
172 + netif_rx(skb);
173 +
174 + priv->stats.rx_packets++;
175 + priv->stats.rx_bytes += len;
176 + return 0;
177 +
178 +ifxmips_mii_hw_receive_err_exit:
179 + if (len == 0) {
180 + if (skb)
181 + dev_kfree_skb_any(skb);
182 + priv->stats.rx_errors++;
183 + priv->stats.rx_dropped++;
184 + return -EIO;
185 + } else {
186 + return len;
187 + }
188 +}
189 +
190 +int ifxmips_mii_hw_tx(char *buf, int len, struct net_device *dev)
191 +{
192 + int ret = 0;
193 + struct ifxmips_mii_priv *priv = netdev_priv(dev);
194 + struct dma_device_info *dma_dev = priv->dma_device;
195 + ret = dma_device_write(dma_dev, buf, len, priv->skb);
196 + return ret;
197 +}
198 +
199 +int ifxmips_mii_tx(struct sk_buff *skb, struct net_device *dev)
200 +{
201 + int len;
202 + char *data;
203 + struct ifxmips_mii_priv *priv = netdev_priv(dev);
204 + struct dma_device_info *dma_dev = priv->dma_device;
205 +
206 + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
207 + data = skb->data;
208 + priv->skb = skb;
209 + dev->trans_start = jiffies;
210 + /* TODO: we got more than 1 dma channel,
211 + so we should do something intelligent here to select one */
212 + dma_dev->current_tx_chan = 0;
213 +
214 + wmb();
215 +
216 + if (ifxmips_mii_hw_tx(data, len, dev) != len) {
217 + dev_kfree_skb_any(skb);
218 + priv->stats.tx_errors++;
219 + priv->stats.tx_dropped++;
220 + } else {
221 + priv->stats.tx_packets++;
222 + priv->stats.tx_bytes += len;
223 + }
224 +
225 + return 0;
226 +}
227 +
228 +void ifxmips_mii_tx_timeout(struct net_device *dev)
229 +{
230 + int i;
231 + struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)netdev_priv(dev);
232 +
233 + priv->stats.tx_errors++;
234 + for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
235 + priv->dma_device->tx_chan[i]->disable_irq(priv->dma_device->tx_chan[i]);
236 + netif_wake_queue(dev);
237 + return;
238 +}
239 +
240 +int dma_intr_handler(struct dma_device_info *dma_dev, int status)
241 +{
242 + int i;
243 +
244 + switch (status) {
245 + case RCV_INT:
246 + ifxmips_mii_hw_receive(ifxmips_mii0_dev, dma_dev);
247 + break;
248 +
249 + case TX_BUF_FULL_INT:
250 + printk(KERN_INFO "ifxmips_mii0: tx buffer full\n");
251 + netif_stop_queue(ifxmips_mii0_dev);
252 + for (i = 0; i < dma_dev->max_tx_chan_num; i++) {
253 + if ((dma_dev->tx_chan[i])->control == IFXMIPS_DMA_CH_ON)
254 + dma_dev->tx_chan[i]->enable_irq(dma_dev->tx_chan[i]);
255 + }
256 + break;
257 +
258 + case TRANSMIT_CPT_INT:
259 + for (i = 0; i < dma_dev->max_tx_chan_num; i++)
260 + dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i]);
261 +
262 + netif_wake_queue(ifxmips_mii0_dev);
263 + break;
264 + }
265 +
266 + return 0;
267 +}
268 +
269 +unsigned char *ifxmips_etop_dma_buffer_alloc(int len, int *byte_offset, void **opt)
270 +{
271 + unsigned char *buffer = NULL;
272 + struct sk_buff *skb = NULL;
273 +
274 + skb = dev_alloc_skb(ETHERNET_PACKET_DMA_BUFFER_SIZE);
275 + if (skb == NULL)
276 + return NULL;
277 +
278 + buffer = (unsigned char *)(skb->data);
279 + skb_reserve(skb, 2);
280 + *(int *)opt = (int)skb;
281 + *byte_offset = 2;
282 +
283 + return buffer;
284 +}
285 +
286 +void ifxmips_etop_dma_buffer_free(unsigned char *dataptr, void *opt)
287 +{
288 + struct sk_buff *skb = NULL;
289 +
290 + if (opt == NULL) {
291 + kfree(dataptr);
292 + } else {
293 + skb = (struct sk_buff *)opt;
294 + dev_kfree_skb_any(skb);
295 + }
296 +}
297 +
298 +static struct net_device_stats *ifxmips_get_stats(struct net_device *dev)
299 +{
300 + return &((struct ifxmips_mii_priv *)netdev_priv(dev))->stats;
301 +}
302 +
303 +static int ifxmips_mii_dev_init(struct net_device *dev)
304 +{
305 + int i;
306 + struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)netdev_priv(dev);
307 + ether_setup(dev);
308 + printk(KERN_INFO "ifxmips_mii0: %s is up\n", dev->name);
309 + dev->open = ifxmips_ifxmips_mii_open;
310 + dev->stop = ifxmips_mii_release;
311 + dev->hard_start_xmit = ifxmips_mii_tx;
312 + dev->get_stats = ifxmips_get_stats;
313 + dev->tx_timeout = ifxmips_mii_tx_timeout;
314 + dev->watchdog_timeo = 10 * HZ;
315 + memset(priv, 0, sizeof(struct ifxmips_mii_priv));
316 + priv->dma_device = dma_device_reserve("PPE");
317 + if (!priv->dma_device) {
318 + BUG();
319 + return -ENODEV;
320 + }
321 + priv->dma_device->buffer_alloc = &ifxmips_etop_dma_buffer_alloc;
322 + priv->dma_device->buffer_free = &ifxmips_etop_dma_buffer_free;
323 + priv->dma_device->intr_handler = &dma_intr_handler;
324 + priv->dma_device->max_rx_chan_num = 4;
325 +
326 + for (i = 0; i < priv->dma_device->max_rx_chan_num; i++) {
327 + priv->dma_device->rx_chan[i]->packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE;
328 + priv->dma_device->rx_chan[i]->control = IFXMIPS_DMA_CH_ON;
329 + }
330 +
331 + for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
332 + if (i == 0)
333 + priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_ON;
334 + else
335 + priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_OFF;
336 +
337 + dma_device_register(priv->dma_device);
338 +
339 + printk(KERN_INFO "ifxmips_mii0: using mac=");
340 + for (i = 0; i < 6; i++) {
341 + dev->dev_addr[i] = mac_addr[i];
342 + printk("%02X%c", dev->dev_addr[i], (i == 5) ? ('\n') : (':'));
343 + }
344 + return 0;
345 +}
346 +
347 +static void ifxmips_mii_chip_init(int mode)
348 +{
349 + ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
350 + ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_PPE);
351 +
352 + if (mode == REV_MII_MODE)
353 + ifxmips_w32_mask(PPE32_MII_MASK, PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG);
354 + else if (mode == MII_MODE)
355 + ifxmips_w32_mask(PPE32_MII_MASK, PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG);
356 + ifxmips_w32(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL);
357 + ifxmips_w32(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG);
358 + wmb();
359 +}
360 +
361 +static int ifxmips_mii_probe(struct platform_device *dev)
362 +{
363 + int result = 0;
364 + unsigned char *mac = (unsigned char *)dev->dev.platform_data;
365 + ifxmips_mii0_dev = alloc_etherdev(sizeof(struct ifxmips_mii_priv));
366 + ifxmips_mii0_dev->init = ifxmips_mii_dev_init;
367 + memcpy(mac_addr, mac, 6);
368 + strcpy(ifxmips_mii0_dev->name, "eth%d");
369 + ifxmips_mii_chip_init(REV_MII_MODE);
370 + result = register_netdev(ifxmips_mii0_dev);
371 + if (result) {
372 + printk(KERN_INFO "ifxmips_mii0: error %i registering device \"%s\"\n", result, ifxmips_mii0_dev->name);
373 + goto out;
374 + }
375 +
376 + printk(KERN_INFO "ifxmips_mii0: driver loaded!\n");
377 +
378 +out:
379 + return result;
380 +}
381 +
382 +static int ifxmips_mii_remove(struct platform_device *dev)
383 +{
384 + struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)netdev_priv(ifxmips_mii0_dev);
385 +
386 + printk(KERN_INFO "ifxmips_mii0: ifxmips_mii0 cleanup\n");
387 +
388 + dma_device_unregister(priv->dma_device);
389 + dma_device_release(priv->dma_device);
390 + kfree(priv->dma_device);
391 + unregister_netdev(ifxmips_mii0_dev);
392 + return 0;
393 +}
394 +
395 +static struct platform_driver ifxmips_mii_driver = {
396 + .probe = ifxmips_mii_probe,
397 + .remove = ifxmips_mii_remove,
398 + .driver = {
399 + .name = "ifxmips_mii0",
400 + .owner = THIS_MODULE,
401 + },
402 +};
403 +
404 +int __init ifxmips_mii_init(void)
405 +{
406 + int ret = platform_driver_register(&ifxmips_mii_driver);
407 + if (ret)
408 + printk(KERN_INFO "ifxmips_mii0: Error registering platfom driver!");
409 + return ret;
410 +}
411 +
412 +static void __exit ifxmips_mii_cleanup(void)
413 +{
414 + platform_driver_unregister(&ifxmips_mii_driver);
415 +}
416 +
417 +module_init(ifxmips_mii_init);
418 +module_exit(ifxmips_mii_cleanup);
419 +
420 +MODULE_LICENSE("GPL");
421 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
422 +MODULE_DESCRIPTION("ethernet driver for IFXMIPS boards");
423 +
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