[brcm63xx] bcm6345 fixes from AndyI
[openwrt.git] / target / linux / pxa / patches-2.6.21 / 010-bkpxa-pxa-cpufreq.patch
1 Status: WORKS
2 PXA CPU frequency change support
3 added mods from Stefan Eletzhofer and Lothar Weissmann
4
5 #
6 # Patch managed by http://www.mn-logistik.de/unsupported/pxa250/patcher
7 #
8
9 --- a/arch/arm/Kconfig
10 +++ b/arch/arm/Kconfig
11 @@ -800,7 +800,7 @@ config KEXEC
12
13 endmenu
14
15 -if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX )
16 +if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA )
17
18 menu "CPU Frequency scaling"
19
20 @@ -838,6 +838,12 @@ config CPU_FREQ_IMX
21
22 endmenu
23
24 +config CPU_FREQ_PXA
25 + bool
26 + depends on CPU_FREQ && ARCH_PXA
27 + default y
28 + select CPU_FREQ_DEFAULT_GOV_USERSPACE
29 +
30 endif
31
32 menu "Floating point emulation"
33 --- a/arch/arm/mach-pxa/Makefile
34 +++ b/arch/arm/mach-pxa/Makefile
35 @@ -32,6 +32,7 @@ obj-$(CONFIG_LEDS) += $(led-y)
36 # Misc features
37 obj-$(CONFIG_PM) += pm.o sleep.o
38 obj-$(CONFIG_PXA_SSP) += ssp.o
39 +obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o
40
41 ifeq ($(CONFIG_PXA27x),y)
42 obj-$(CONFIG_PM) += standby.o
43 --- /dev/null
44 +++ b/arch/arm/mach-pxa/cpu-pxa.c
45 @@ -0,0 +1,321 @@
46 +/*
47 + * linux/arch/arm/mach-pxa/cpu-pxa.c
48 + *
49 + * Copyright (C) 2002,2003 Intrinsyc Software
50 + *
51 + * This program is free software; you can redistribute it and/or modify
52 + * it under the terms of the GNU General Public License as published by
53 + * the Free Software Foundation; either version 2 of the License, or
54 + * (at your option) any later version.
55 + *
56 + * This program is distributed in the hope that it will be useful,
57 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
58 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
59 + * GNU General Public License for more details.
60 + *
61 + * You should have received a copy of the GNU General Public License
62 + * along with this program; if not, write to the Free Software
63 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
64 + *
65 + * History:
66 + * 31-Jul-2002 : Initial version [FB]
67 + * 29-Jan-2003 : added PXA255 support [FB]
68 + * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
69 + *
70 + * Note:
71 + * This driver may change the memory bus clock rate, but will not do any
72 + * platform specific access timing changes... for example if you have flash
73 + * memory connected to CS0, you will need to register a platform specific
74 + * notifier which will adjust the memory access strobes to maintain a
75 + * minimum strobe width.
76 + *
77 + */
78 +
79 +#include <linux/kernel.h>
80 +#include <linux/module.h>
81 +#include <linux/sched.h>
82 +#include <linux/init.h>
83 +#include <linux/cpufreq.h>
84 +
85 +#include <asm/hardware.h>
86 +#include <asm/arch/pxa-regs.h>
87 +
88 +#define DEBUG 0
89 +
90 +#ifdef DEBUG
91 + static unsigned int freq_debug = DEBUG;
92 + MODULE_PARM(freq_debug, "i");
93 + MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
94 +#else
95 + #define freq_debug 0
96 +#endif
97 +
98 +typedef struct
99 +{
100 + unsigned int khz;
101 + unsigned int membus;
102 + unsigned int cccr;
103 + unsigned int div2;
104 +} pxa_freqs_t;
105 +
106 +/* Define the refresh period in mSec for the SDRAM and the number of rows */
107 +#define SDRAM_TREF 64 /* standard 64ms SDRAM */
108 +#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */
109 +#define MDREFR_DRI(x) ((x*SDRAM_TREF)/(SDRAM_ROWS*32))
110 +
111 +#define CCLKCFG_TURBO 0x1
112 +#define CCLKCFG_FCS 0x2
113 +#define PXA25x_MIN_FREQ 99500
114 +#define PXA25x_MAX_FREQ 398100
115 +#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
116 +#define MDREFR_DRI_MASK 0xFFF
117 +
118 +
119 +/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
120 +static pxa_freqs_t pxa255_run_freqs[] =
121 +{
122 + /* CPU MEMBUS CCCR DIV2*/
123 + { 99500, 99500, 0x121, 1}, /* run= 99, turbo= 99, PXbus=50, SDRAM=50 */
124 + {132700, 132700, 0x123, 1}, /* run=133, turbo=133, PXbus=66, SDRAM=66 */
125 + {199100, 99500, 0x141, 0}, /* run=199, turbo=199, PXbus=99, SDRAM=99 */
126 + {265400, 132700, 0x143, 1}, /* run=265, turbo=265, PXbus=133, SDRAM=66 */
127 + {331800, 165900, 0x145, 1}, /* run=331, turbo=331, PXbus=166, SDRAM=83 */
128 + {398100, 99500, 0x161, 0}, /* run=398, turbo=398, PXbus=196, SDRAM=99 */
129 + {0,}
130 +};
131 +#define NUM_RUN_FREQS (sizeof(pxa255_run_freqs)/sizeof(pxa_freqs_t))
132 +
133 +static struct cpufreq_frequency_table pxa255_run_freq_table[NUM_RUN_FREQS+1];
134 +
135 +/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
136 +static pxa_freqs_t pxa255_turbo_freqs[] =
137 +{
138 + /* CPU MEMBUS CCCR DIV2*/
139 + { 99500, 99500, 0x121, 1}, /* run=99, turbo= 99, PXbus=50, SDRAM=50 */
140 + {199100, 99500, 0x221, 0}, /* run=99, turbo=199, PXbus=50, SDRAM=99 */
141 + {298500, 99500, 0x321, 0}, /* run=99, turbo=287, PXbus=50, SDRAM=99 */
142 + {298600, 99500, 0x1c1, 0}, /* run=199, turbo=287, PXbus=99, SDRAM=99 */
143 + {398100, 99500, 0x241, 0}, /* run=199, turbo=398, PXbus=99, SDRAM=99 */
144 + {0,}
145 +};
146 +#define NUM_TURBO_FREQS (sizeof(pxa255_turbo_freqs)/sizeof(pxa_freqs_t))
147 +
148 +static struct cpufreq_frequency_table pxa255_turbo_freq_table[NUM_TURBO_FREQS+1];
149 +
150 +extern unsigned get_clk_frequency_khz(int info);
151 +
152 +/* find a valid frequency point */
153 +static int pxa_verify_policy(struct cpufreq_policy *policy)
154 +{
155 + int ret;
156 + struct cpufreq_frequency_table *pxa_freqs_table;
157 +
158 + if(policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
159 + pxa_freqs_table = pxa255_run_freq_table;
160 + } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
161 + pxa_freqs_table = pxa255_turbo_freq_table;
162 + } else {
163 + printk("CPU PXA: Unknown policy found. "
164 + "Using CPUFREQ_POLICY_PERFORMANCE\n");
165 + pxa_freqs_table = pxa255_run_freq_table;
166 + }
167 + ret=cpufreq_frequency_table_verify(policy, pxa_freqs_table);
168 +
169 + if(freq_debug) {
170 + printk("Verified CPU policy: %dKhz min to %dKhz max\n",
171 + policy->min, policy->max);
172 + }
173 +
174 + return ret;
175 +}
176 +
177 +static int pxa_set_target(struct cpufreq_policy *policy,
178 + unsigned int target_freq,
179 + unsigned int relation)
180 +{
181 + int idx;
182 + unsigned long cpus_allowed;
183 + int cpu = policy->cpu;
184 + struct cpufreq_freqs freqs;
185 + pxa_freqs_t *pxa_freq_settings;
186 + struct cpufreq_frequency_table *pxa_freqs_table;
187 + unsigned long flags;
188 + unsigned int unused;
189 + unsigned int preset_mdrefr, postset_mdrefr;
190 +
191 + /*
192 + * Save this threads cpus_allowed mask.
193 + */
194 + cpus_allowed = current->cpus_allowed;
195 +
196 + /*
197 + * Bind to the specified CPU. When this call returns,
198 + * we should be running on the right CPU.
199 + */
200 + set_cpus_allowed(current, 1 << cpu);
201 + BUG_ON(cpu != smp_processor_id());
202 +
203 + /* Get the current policy */
204 + if(policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
205 + pxa_freq_settings = pxa255_run_freqs;
206 + pxa_freqs_table = pxa255_run_freq_table;
207 + }else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
208 + pxa_freq_settings = pxa255_turbo_freqs;
209 + pxa_freqs_table = pxa255_turbo_freq_table;
210 + }else {
211 + printk("CPU PXA: Unknown policy found. "
212 + "Using CPUFREQ_POLICY_PERFORMANCE\n");
213 + pxa_freq_settings = pxa255_run_freqs;
214 + pxa_freqs_table = pxa255_run_freq_table;
215 + }
216 +
217 + /* Lookup the next frequency */
218 + if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
219 + target_freq, relation, &idx)) {
220 + return -EINVAL;
221 + }
222 +
223 + freqs.old = policy->cur;
224 + freqs.new = pxa_freq_settings[idx].khz;
225 + freqs.cpu = policy->cpu;
226 + if(freq_debug) {
227 + printk(KERN_INFO "Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
228 + freqs.new/1000, (pxa_freq_settings[idx].div2) ?
229 + (pxa_freq_settings[idx].membus/2000) :
230 + (pxa_freq_settings[idx].membus/1000));
231 + }
232 +
233 + void *ramstart = phys_to_virt(0xa0000000);
234 +
235 + /*
236 + * Tell everyone what we're about to do...
237 + * you should add a notify client with any platform specific
238 + * Vcc changing capability
239 + */
240 + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
241 +
242 + /* Calculate the next MDREFR. If we're slowing down the SDRAM clock
243 + * we need to preset the smaller DRI before the change. If we're speeding
244 + * up we need to set the larger DRI value after the change.
245 + */
246 + preset_mdrefr = postset_mdrefr = MDREFR;
247 + if((MDREFR & MDREFR_DRI_MASK) > MDREFR_DRI(pxa_freq_settings[idx].membus)) {
248 + preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) |
249 + MDREFR_DRI(pxa_freq_settings[idx].membus);
250 + }
251 + postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) |
252 + MDREFR_DRI(pxa_freq_settings[idx].membus);
253 +
254 + /* If we're dividing the memory clock by two for the SDRAM clock, this
255 + * must be set prior to the change. Clearing the divide must be done
256 + * after the change.
257 + */
258 + if(pxa_freq_settings[idx].div2) {
259 + preset_mdrefr |= MDREFR_DB2_MASK;
260 + postset_mdrefr |= MDREFR_DB2_MASK;
261 + } else {
262 + postset_mdrefr &= ~MDREFR_DB2_MASK;
263 + }
264 +
265 + local_irq_save(flags);
266 +
267 + /* Set new the CCCR */
268 + CCCR = pxa_freq_settings[idx].cccr;
269 +
270 + __asm__ __volatile__(" \
271 + ldr r4, [%1] ; /* load MDREFR */ \
272 + b 2f ; \
273 + .align 5 ; \
274 +1: \
275 + str %4, [%1] ; /* preset the MDREFR */ \
276 + mcr p14, 0, %2, c6, c0, 0 ; /* set CCLKCFG[FCS] */ \
277 + str %5, [%1] ; /* postset the MDREFR */ \
278 + \
279 + b 3f ; \
280 +2: b 1b ; \
281 +3: nop ; \
282 + "
283 + : "=&r" (unused)
284 + : "r" (&MDREFR), "r" (CCLKCFG_TURBO|CCLKCFG_FCS), "r" (ramstart), \
285 + "r" (preset_mdrefr), "r" (postset_mdrefr)
286 + : "r4", "r5");
287 + local_irq_restore(flags);
288 +
289 + /*
290 + * Restore the CPUs allowed mask.
291 + */
292 + set_cpus_allowed(current, cpus_allowed);
293 +
294 + /*
295 + * Tell everyone what we've just done...
296 + * you should add a notify client with any platform specific
297 + * SDRAM refresh timer adjustments
298 + */
299 + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
300 +
301 + return 0;
302 +}
303 +
304 +static int pxa_cpufreq_init(struct cpufreq_policy *policy)
305 +{
306 + unsigned long cpus_allowed;
307 + unsigned int cpu = policy->cpu;
308 + int i;
309 +
310 + cpus_allowed = current->cpus_allowed;
311 +
312 + set_cpus_allowed(current, 1 << cpu);
313 + BUG_ON(cpu != smp_processor_id());
314 +
315 + /* set default policy and cpuinfo */
316 + policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
317 + policy->policy = CPUFREQ_POLICY_PERFORMANCE;
318 + policy->cpuinfo.max_freq = PXA25x_MAX_FREQ;
319 + policy->cpuinfo.min_freq = PXA25x_MIN_FREQ;
320 + policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
321 + policy->cur = get_clk_frequency_khz(0); /* current freq */
322 + policy->min = policy->max = policy->cur;
323 +
324 + /* Generate the run cpufreq_frequency_table struct */
325 + for(i=0;i<NUM_RUN_FREQS;i++) {
326 + pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
327 + pxa255_run_freq_table[i].index = i;
328 + }
329 + pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
330 + /* Generate the turbo cpufreq_frequency_table struct */
331 + for(i=0;i<NUM_TURBO_FREQS;i++) {
332 + pxa255_turbo_freq_table[i].frequency = pxa255_turbo_freqs[i].khz;
333 + pxa255_turbo_freq_table[i].index = i;
334 + }
335 + pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
336 +
337 + set_cpus_allowed(current, cpus_allowed);
338 + printk(KERN_INFO "PXA CPU frequency change support initialized\n");
339 +
340 + return 0;
341 +}
342 +
343 +static struct cpufreq_driver pxa_cpufreq_driver = {
344 + .verify = pxa_verify_policy,
345 + .target = pxa_set_target,
346 + .init = pxa_cpufreq_init,
347 + .name = "PXA25x",
348 +};
349 +
350 +static int __init pxa_cpu_init(void)
351 +{
352 + return cpufreq_register_driver(&pxa_cpufreq_driver);
353 +}
354 +
355 +static void __exit pxa_cpu_exit(void)
356 +{
357 + cpufreq_unregister_driver(&pxa_cpufreq_driver);
358 +}
359 +
360 +
361 +MODULE_AUTHOR ("Intrinsyc Software Inc.");
362 +MODULE_DESCRIPTION ("CPU frequency changing driver for the PXA architecture");
363 +MODULE_LICENSE("GPL");
364 +module_init(pxa_cpu_init);
365 +module_exit(pxa_cpu_exit);
366 +
367 --- a/Documentation/cpu-freq/user-guide.txt
368 +++ b/Documentation/cpu-freq/user-guide.txt
369 @@ -18,7 +18,7 @@
370 Contents:
371 ---------
372 1. Supported Architectures and Processors
373 -1.1 ARM
374 +1.1 ARM, PXA
375 1.2 x86
376 1.3 sparc64
377 1.4 ppc
378 @@ -37,14 +37,15 @@ Contents:
379 1. Supported Architectures and Processors
380 =========================================
381
382 -1.1 ARM
383 --------
384 +1.1 ARM, PXA
385 +------------
386
387 The following ARM processors are supported by cpufreq:
388
389 ARM Integrator
390 ARM-SA1100
391 ARM-SA1110
392 +Intel PXA
393
394
395 1.2 x86
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