2 * ADM5120 HCD (Host Controller Driver) for USB
4 * Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
6 * This file was derived from: drivers/usb/host/ohci-hcd.c
7 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
8 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
10 * [ Initialisation is based on Linus' ]
11 * [ uhci code and gregs ahcd fragments ]
12 * [ (C) Copyright 1999 Linus Torvalds ]
13 * [ (C) Copyright 1999 Gregory P. Smith]
15 * This file is licenced under the GPL.
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/pci.h>
21 #include <linux/kernel.h>
22 #include <linux/delay.h>
23 #include <linux/ioport.h>
24 #include <linux/sched.h>
25 #include <linux/slab.h>
26 #include <linux/errno.h>
27 #include <linux/init.h>
28 #include <linux/timer.h>
29 #include <linux/list.h>
30 #include <linux/usb.h>
31 #include <linux/usb/otg.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/dmapool.h>
34 #include <linux/reboot.h>
38 #include <asm/system.h>
39 #include <asm/unaligned.h>
40 #include <asm/byteorder.h>
42 #include "../core/hcd.h"
43 #include "../core/hub.h"
45 #define DRIVER_VERSION "0.14.1"
46 #define DRIVER_AUTHOR "Gabor Juhos <juhosg at openwrt.org>"
47 #define DRIVER_DESC "ADMtek USB 1.1 Host Controller Driver"
49 /*-------------------------------------------------------------------------*/
51 #undef ADMHC_VERBOSE_DEBUG /* not always helpful */
53 /* For initializing controller (mask in an HCFS mode too) */
54 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
56 #define ADMHC_INTR_INIT \
57 ( ADMHC_INTR_MIE | ADMHC_INTR_INSM | ADMHC_INTR_FATI \
58 | ADMHC_INTR_RESI | ADMHC_INTR_TDC | ADMHC_INTR_BABI )
60 /*-------------------------------------------------------------------------*/
62 static const char hcd_name
[] = "admhc-hcd";
64 #define STATECHANGE_DELAY msecs_to_jiffies(300)
68 static void admhc_dump(struct admhcd
*ahcd
, int verbose
);
69 static int admhc_init(struct admhcd
*ahcd
);
70 static void admhc_stop(struct usb_hcd
*hcd
);
72 #include "adm5120-dbg.c"
73 #include "adm5120-mem.c"
74 #include "adm5120-pm.c"
75 #include "adm5120-hub.c"
76 #include "adm5120-q.c"
78 /*-------------------------------------------------------------------------*/
81 * queue up an urb for anything except the root hub
83 static int admhc_urb_enqueue(struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
,
84 struct urb
*urb
, gfp_t mem_flags
)
86 struct admhcd
*ahcd
= hcd_to_admhcd(hcd
);
88 struct urb_priv
*urb_priv
;
89 unsigned int pipe
= urb
->pipe
;
94 #ifdef ADMHC_VERBOSE_DEBUG
95 spin_lock_irqsave(&ahcd
->lock
, flags
);
96 urb_print(ahcd
, urb
, "ENQEUE", usb_pipein(pipe
));
97 spin_unlock_irqrestore(&ahcd
->lock
, flags
);
100 /* every endpoint has an ed, locate and maybe (re)initialize it */
101 ed
= ed_get(ahcd
, ep
, urb
->dev
, pipe
, urb
->interval
);
105 /* for the private part of the URB we need the number of TDs */
108 if (urb
->transfer_buffer_length
> TD_DATALEN_MAX
)
109 /* td_submit_urb() doesn't yet handle these */
112 /* 1 TD for setup, 1 for ACK, plus ... */
116 /* one TD for every 4096 Bytes (can be upto 8K) */
117 td_cnt
+= urb
->transfer_buffer_length
/ TD_DATALEN_MAX
;
118 /* ... and for any remaining bytes ... */
119 if ((urb
->transfer_buffer_length
% TD_DATALEN_MAX
) != 0)
121 /* ... and maybe a zero length packet to wrap it up */
124 else if ((urb
->transfer_flags
& URB_ZERO_PACKET
) != 0
125 && (urb
->transfer_buffer_length
126 % usb_maxpacket(urb
->dev
, pipe
,
127 usb_pipeout (pipe
))) == 0)
132 * for Interrupt IN/OUT transactions, each ED contains
134 * TODO: check transfer_buffer_length?
138 case PIPE_ISOCHRONOUS
:
139 /* number of packets from URB */
140 td_cnt
= urb
->number_of_packets
;
144 urb_priv
= urb_priv_alloc(ahcd
, td_cnt
, mem_flags
);
150 spin_lock_irqsave(&ahcd
->lock
, flags
);
151 /* don't submit to a dead HC */
152 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
)) {
156 if (!HC_IS_RUNNING(hcd
->state
)) {
161 /* in case of unlink-during-submit */
162 spin_lock(&urb
->lock
);
163 if (urb
->status
!= -EINPROGRESS
) {
164 spin_unlock(&urb
->lock
);
165 urb
->hcpriv
= urb_priv
;
166 finish_urb(ahcd
, urb
);
171 /* schedule the ed if needed */
172 if (ed
->state
== ED_IDLE
) {
173 ret
= ed_schedule(ahcd
, ed
);
177 if (ed
->type
== PIPE_ISOCHRONOUS
) {
178 u16 frame
= admhc_frame_no(ahcd
);
180 /* delay a few frames before the first TD */
181 frame
+= max_t (u16
, 8, ed
->interval
);
182 frame
&= ~(ed
->interval
- 1);
184 urb
->start_frame
= frame
;
186 /* yes, only URB_ISO_ASAP is supported, and
187 * urb->start_frame is never used as input.
190 } else if (ed
->type
== PIPE_ISOCHRONOUS
)
191 urb
->start_frame
= ed
->last_iso
+ ed
->interval
;
193 /* fill the TDs and link them to the ed; and
194 * enable that part of the schedule, if needed
195 * and update count of queued periodic urbs
197 urb
->hcpriv
= urb_priv
;
198 td_submit_urb(ahcd
, urb
);
200 #ifdef ADMHC_VERBOSE_DEBUG
201 admhc_dump_ed(ahcd
, "admhc_urb_enqueue", urb_priv
->ed
, 1);
205 spin_unlock(&urb
->lock
);
208 urb_priv_free(ahcd
, urb_priv
);
210 spin_unlock_irqrestore(&ahcd
->lock
, flags
);
215 * decouple the URB from the HC queues (TDs, urb_priv); it's
216 * already marked using urb->status. reporting is always done
217 * asynchronously, and we might be dealing with an urb that's
218 * partially transferred, or an ED with other urbs being unlinked.
220 static int admhc_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
)
222 struct admhcd
*ahcd
= hcd_to_admhcd(hcd
);
225 spin_lock_irqsave(&ahcd
->lock
, flags
);
227 #ifdef ADMHC_VERBOSE_DEBUG
228 urb_print(ahcd
, urb
, "DEQUEUE", 1);
231 if (HC_IS_RUNNING(hcd
->state
)) {
232 struct urb_priv
*urb_priv
;
234 /* Unless an IRQ completed the unlink while it was being
235 * handed to us, flag it for unlink and giveback, and force
236 * some upcoming INTR_SF to call finish_unlinks()
238 urb_priv
= urb
->hcpriv
;
240 if (urb_priv
->ed
->state
== ED_OPER
)
241 start_ed_unlink(ahcd
, urb_priv
->ed
);
245 * with HC dead, we won't respect hc queue pointers
246 * any more ... just clean up every urb's memory.
249 finish_urb(ahcd
, urb
);
251 spin_unlock_irqrestore(&ahcd
->lock
, flags
);
256 /*-------------------------------------------------------------------------*/
258 /* frees config/altsetting state for endpoints,
259 * including ED memory, dummy TD, and bulk/intr data toggle
262 static void admhc_endpoint_disable(struct usb_hcd
*hcd
,
263 struct usb_host_endpoint
*ep
)
265 struct admhcd
*ahcd
= hcd_to_admhcd(hcd
);
267 struct ed
*ed
= ep
->hcpriv
;
268 unsigned limit
= 1000;
270 /* ASSERT: any requests/urbs are being unlinked */
271 /* ASSERT: nobody can be submitting urbs for this any more */
276 #ifdef ADMHC_VERBOSE_DEBUG
277 spin_lock_irqsave(&ahcd
->lock
, flags
);
278 admhc_dump_ed(ahcd
, "EP-DISABLE", ed
, 1);
279 spin_unlock_irqrestore(&ahcd
->lock
, flags
);
283 spin_lock_irqsave(&ahcd
->lock
, flags
);
285 if (!HC_IS_RUNNING(hcd
->state
)) {
288 finish_unlinks(ahcd
, 0);
292 case ED_UNLINK
: /* wait for hw to finish? */
293 /* major IRQ delivery trouble loses INTR_SOFI too... */
295 admhc_warn(ahcd
, "IRQ INTR_SOFI lossage\n");
298 spin_unlock_irqrestore(&ahcd
->lock
, flags
);
299 schedule_timeout_uninterruptible(1);
301 case ED_IDLE
: /* fully unlinked */
302 if (list_empty(&ed
->td_list
)) {
303 td_free (ahcd
, ed
->dummy
);
307 /* else FALL THROUGH */
309 /* caller was supposed to have unlinked any requests;
310 * that's not our job. can't recover; must leak ed.
312 admhc_err(ahcd
, "leak ed %p (#%02x) state %d%s\n",
313 ed
, ep
->desc
.bEndpointAddress
, ed
->state
,
314 list_empty(&ed
->td_list
) ? "" : " (has tds)");
315 td_free(ahcd
, ed
->dummy
);
321 spin_unlock_irqrestore(&ahcd
->lock
, flags
);
325 static int admhc_get_frame_number(struct usb_hcd
*hcd
)
327 struct admhcd
*ahcd
= hcd_to_admhcd(hcd
);
329 return admhc_frame_no(ahcd
);
332 static void admhc_usb_reset(struct admhcd
*ahcd
)
335 ahcd
->hc_control
= admhc_readl(ahcd
, &ahcd
->regs
->control
);
336 ahcd
->hc_control
&= OHCI_CTRL_RWC
;
337 admhc_writel(ahcd
, ahcd
->hc_control
, &ahcd
->regs
->control
);
340 ahcd
->host_control
= ADMHC_BUSS_RESET
;
341 admhc_writel(ahcd
, ahcd
->host_control
,&ahcd
->regs
->host_control
);
345 /* admhc_shutdown forcibly disables IRQs and DMA, helping kexec and
346 * other cases where the next software may expect clean state from the
347 * "firmware". this is bus-neutral, unlike shutdown() methods.
350 admhc_shutdown(struct usb_hcd
*hcd
)
354 ahcd
= hcd_to_admhcd(hcd
);
355 admhc_intr_disable(ahcd
, ADMHC_INTR_MIE
);
356 admhc_dma_disable(ahcd
);
357 admhc_usb_reset(ahcd
);
358 /* flush the writes */
359 admhc_writel_flush(ahcd
);
362 /*-------------------------------------------------------------------------*
364 *-------------------------------------------------------------------------*/
366 static void admhc_eds_cleanup(struct admhcd
*ahcd
)
368 if (ahcd
->ed_tails
[PIPE_INTERRUPT
]) {
369 ed_free(ahcd
, ahcd
->ed_tails
[PIPE_INTERRUPT
]);
370 ahcd
->ed_tails
[PIPE_INTERRUPT
] = NULL
;
373 if (ahcd
->ed_tails
[PIPE_ISOCHRONOUS
]) {
374 ed_free(ahcd
, ahcd
->ed_tails
[PIPE_ISOCHRONOUS
]);
375 ahcd
->ed_tails
[PIPE_ISOCHRONOUS
] = NULL
;
378 if (ahcd
->ed_tails
[PIPE_CONTROL
]) {
379 ed_free(ahcd
, ahcd
->ed_tails
[PIPE_CONTROL
]);
380 ahcd
->ed_tails
[PIPE_CONTROL
] = NULL
;
383 if (ahcd
->ed_tails
[PIPE_BULK
]) {
384 ed_free(ahcd
, ahcd
->ed_tails
[PIPE_BULK
]);
385 ahcd
->ed_tails
[PIPE_BULK
] = NULL
;
388 ahcd
->ed_head
= NULL
;
391 #define ED_DUMMY_INFO (ED_SPEED_FULL | ED_SKIP)
393 static int admhc_eds_init(struct admhcd
*ahcd
)
397 ed
= ed_create(ahcd
, PIPE_INTERRUPT
, ED_DUMMY_INFO
);
401 ahcd
->ed_tails
[PIPE_INTERRUPT
] = ed
;
403 ed
= ed_create(ahcd
, PIPE_ISOCHRONOUS
, ED_DUMMY_INFO
);
407 ahcd
->ed_tails
[PIPE_ISOCHRONOUS
] = ed
;
408 ed
->ed_prev
= ahcd
->ed_tails
[PIPE_INTERRUPT
];
409 ahcd
->ed_tails
[PIPE_INTERRUPT
]->ed_next
= ed
;
410 ahcd
->ed_tails
[PIPE_INTERRUPT
]->hwNextED
= cpu_to_hc32(ahcd
, ed
->dma
);
412 ed
= ed_create(ahcd
, PIPE_CONTROL
, ED_DUMMY_INFO
);
416 ahcd
->ed_tails
[PIPE_CONTROL
] = ed
;
417 ed
->ed_prev
= ahcd
->ed_tails
[PIPE_ISOCHRONOUS
];
418 ahcd
->ed_tails
[PIPE_ISOCHRONOUS
]->ed_next
= ed
;
419 ahcd
->ed_tails
[PIPE_ISOCHRONOUS
]->hwNextED
= cpu_to_hc32(ahcd
, ed
->dma
);
421 ed
= ed_create(ahcd
, PIPE_BULK
, ED_DUMMY_INFO
);
425 ahcd
->ed_tails
[PIPE_BULK
] = ed
;
426 ed
->ed_prev
= ahcd
->ed_tails
[PIPE_CONTROL
];
427 ahcd
->ed_tails
[PIPE_CONTROL
]->ed_next
= ed
;
428 ahcd
->ed_tails
[PIPE_CONTROL
]->hwNextED
= cpu_to_hc32(ahcd
, ed
->dma
);
430 ahcd
->ed_head
= ahcd
->ed_tails
[PIPE_INTERRUPT
];
432 #ifdef ADMHC_VERBOSE_DEBUG
433 admhc_dump_ed(ahcd
, "ed intr", ahcd
->ed_tails
[PIPE_INTERRUPT
], 1);
434 admhc_dump_ed(ahcd
, "ed isoc", ahcd
->ed_tails
[PIPE_ISOCHRONOUS
], 1);
435 admhc_dump_ed(ahcd
, "ed ctrl", ahcd
->ed_tails
[PIPE_CONTROL
], 1);
436 admhc_dump_ed(ahcd
, "ed bulk", ahcd
->ed_tails
[PIPE_BULK
], 1);
442 admhc_eds_cleanup(ahcd
);
446 /* init memory, and kick BIOS/SMM off */
448 static int admhc_init(struct admhcd
*ahcd
)
450 struct usb_hcd
*hcd
= admhcd_to_hcd(ahcd
);
454 ahcd
->regs
= hcd
->regs
;
456 /* Disable HC interrupts */
457 admhc_intr_disable(ahcd
, ADMHC_INTR_MIE
);
459 /* Read the number of ports unless overridden */
460 if (ahcd
->num_ports
== 0)
461 ahcd
->num_ports
= admhc_read_rhdesc(ahcd
) & ADMHC_RH_NUMP
;
463 ret
= admhc_mem_init(ahcd
);
467 /* init dummy endpoints */
468 ret
= admhc_eds_init(ahcd
);
472 create_debug_files(ahcd
);
481 /*-------------------------------------------------------------------------*/
483 /* Start an OHCI controller, set the BUS operational
484 * resets USB and controller
487 static int admhc_run(struct admhcd
*ahcd
)
490 int first
= ahcd
->fminterval
== 0;
491 struct usb_hcd
*hcd
= admhcd_to_hcd(ahcd
);
495 /* boot firmware should have set this up (5.1.1.3.1) */
497 temp
= admhc_readl(ahcd
, &ahcd
->regs
->fminterval
);
498 ahcd
->fminterval
= temp
& ADMHC_SFI_FI_MASK
;
499 if (ahcd
->fminterval
!= FI
)
500 admhc_dbg(ahcd
, "fminterval delta %d\n",
501 ahcd
->fminterval
- FI
);
503 (FSLDP(ahcd
->fminterval
) << ADMHC_SFI_FSLDP_SHIFT
);
504 /* also: power/overcurrent flags in rhdesc */
507 #if 0 /* TODO: not applicable */
508 /* Reset USB nearly "by the book". RemoteWakeupConnected was
509 * saved if boot firmware (BIOS/SMM/...) told us it's connected,
510 * or if bus glue did the same (e.g. for PCI add-in cards with
513 if ((ahcd
->hc_control
& OHCI_CTRL_RWC
) != 0
514 && !device_may_wakeup(hcd
->self
.controller
))
515 device_init_wakeup(hcd
->self
.controller
, 1);
518 switch (ahcd
->host_control
& ADMHC_HC_BUSS
) {
519 case ADMHC_BUSS_OPER
:
522 case ADMHC_BUSS_SUSPEND
:
524 case ADMHC_BUSS_RESUME
:
525 ahcd
->host_control
= ADMHC_BUSS_RESUME
;
526 temp
= 10 /* msec wait */;
528 /* case ADMHC_BUSS_RESET: */
530 ahcd
->host_control
= ADMHC_BUSS_RESET
;
531 temp
= 50 /* msec wait */;
534 admhc_writel(ahcd
, ahcd
->host_control
, &ahcd
->regs
->host_control
);
536 /* flush the writes */
537 admhc_writel_flush(ahcd
);
540 temp
= admhc_read_rhdesc(ahcd
);
541 if (!(temp
& ADMHC_RH_NPS
)) {
542 /* power down each port */
543 for (temp
= 0; temp
< ahcd
->num_ports
; temp
++)
544 admhc_write_portstatus(ahcd
, temp
, ADMHC_PS_CPP
);
546 /* flush those writes */
547 admhc_writel_flush(ahcd
);
549 /* 2msec timelimit here means no irqs/preempt */
550 spin_lock_irq(&ahcd
->lock
);
552 admhc_writel(ahcd
, ADMHC_CTRL_SR
, &ahcd
->regs
->gencontrol
);
553 temp
= 30; /* ... allow extra time */
554 while ((admhc_readl(ahcd
, &ahcd
->regs
->gencontrol
) & ADMHC_CTRL_SR
) != 0) {
556 spin_unlock_irq(&ahcd
->lock
);
557 admhc_err(ahcd
, "USB HC reset timed out!\n");
563 /* enable HOST mode, before access any host specific register */
564 admhc_writel(ahcd
, ADMHC_CTRL_UHFE
, &ahcd
->regs
->gencontrol
);
566 /* Tell the controller where the descriptor list is */
567 admhc_writel(ahcd
, (u32
)ahcd
->ed_head
->dma
, &ahcd
->regs
->hosthead
);
569 periodic_reinit(ahcd
);
571 /* use rhsc irqs after khubd is fully initialized */
573 hcd
->uses_new_polling
= 1;
576 /* wake on ConnectStatusChange, matching external hubs */
577 admhc_writel(ahcd
, RH_HS_DRWE
, &ahcd
->regs
->roothub
.status
);
579 /* FIXME roothub_write_status (ahcd, ADMHC_RH_DRWE); */
582 /* Choose the interrupts we care about now, others later on demand */
583 admhc_intr_ack(ahcd
, ~0);
584 admhc_intr_enable(ahcd
, ADMHC_INTR_INIT
);
586 admhc_writel(ahcd
, ADMHC_RH_NPS
| ADMHC_RH_LPSC
, &ahcd
->regs
->rhdesc
);
588 /* flush those writes */
589 admhc_writel_flush(ahcd
);
591 /* start controller operations */
592 ahcd
->host_control
= ADMHC_BUSS_OPER
;
593 admhc_writel(ahcd
, ahcd
->host_control
, &ahcd
->regs
->host_control
);
596 while ((admhc_readl(ahcd
, &ahcd
->regs
->host_control
)
597 & ADMHC_HC_BUSS
) != ADMHC_BUSS_OPER
) {
599 spin_unlock_irq(&ahcd
->lock
);
600 admhc_err(ahcd
, "unable to setup operational mode!\n");
606 hcd
->state
= HC_STATE_RUNNING
;
608 ahcd
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
611 /* FIXME: enabling DMA is always failed here for an unknown reason */
612 admhc_dma_enable(ahcd
);
615 while ((admhc_readl(ahcd
, &ahcd
->regs
->host_control
)
616 & ADMHC_HC_DMAE
) != ADMHC_HC_DMAE
) {
618 spin_unlock_irq(&ahcd
->lock
);
619 admhc_err(ahcd
, "unable to enable DMA!\n");
628 spin_unlock_irq(&ahcd
->lock
);
630 mdelay(ADMHC_POTPGT
);
635 /*-------------------------------------------------------------------------*/
637 /* an interrupt happens */
639 static irqreturn_t
admhc_irq(struct usb_hcd
*hcd
)
641 struct admhcd
*ahcd
= hcd_to_admhcd(hcd
);
642 struct admhcd_regs __iomem
*regs
= ahcd
->regs
;
645 ints
= admhc_readl(ahcd
, ®s
->int_status
);
646 if ((ints
& ADMHC_INTR_INTA
) == 0) {
647 /* no unmasked interrupt status is set */
651 ints
&= admhc_readl(ahcd
, ®s
->int_enable
);
653 if (ints
& ADMHC_INTR_FATI
) {
654 /* e.g. due to PCI Master/Target Abort */
656 admhc_err(ahcd
, "Fatal Error, controller disabled\n");
658 admhc_usb_reset(ahcd
);
661 if (ints
& ADMHC_INTR_BABI
) {
662 admhc_intr_disable(ahcd
, ADMHC_INTR_BABI
);
663 admhc_intr_ack(ahcd
, ADMHC_INTR_BABI
);
664 admhc_err(ahcd
, "Babble Detected\n");
667 if (ints
& ADMHC_INTR_INSM
) {
668 admhc_vdbg(ahcd
, "Root Hub Status Change\n");
669 ahcd
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
670 admhc_intr_ack(ahcd
, ADMHC_INTR_RESI
| ADMHC_INTR_INSM
);
672 /* NOTE: Vendors didn't always make the same implementation
673 * choices for RHSC. Many followed the spec; RHSC triggers
674 * on an edge, like setting and maybe clearing a port status
675 * change bit. With others it's level-triggered, active
676 * until khubd clears all the port status change bits. We'll
677 * always disable it here and rely on polling until khubd
680 admhc_intr_disable(ahcd
, ADMHC_INTR_INSM
);
681 usb_hcd_poll_rh_status(hcd
);
682 } else if (ints
& ADMHC_INTR_RESI
) {
683 /* For connect and disconnect events, we expect the controller
684 * to turn on RHSC along with RD. But for remote wakeup events
685 * this might not happen.
687 admhc_vdbg(ahcd
, "Resume Detect\n");
688 admhc_intr_ack(ahcd
, ADMHC_INTR_RESI
);
690 if (ahcd
->autostop
) {
691 spin_lock(&ahcd
->lock
);
692 admhc_rh_resume(ahcd
);
693 spin_unlock(&ahcd
->lock
);
695 usb_hcd_resume_root_hub(hcd
);
698 if (ints
& ADMHC_INTR_TDC
) {
699 admhc_vdbg(ahcd
, "Transfer Descriptor Complete\n");
700 admhc_intr_ack(ahcd
, ADMHC_INTR_TDC
);
701 if (HC_IS_RUNNING(hcd
->state
))
702 admhc_intr_disable(ahcd
, ADMHC_INTR_TDC
);
703 spin_lock(&ahcd
->lock
);
704 admhc_td_complete(ahcd
);
705 spin_unlock(&ahcd
->lock
);
706 if (HC_IS_RUNNING(hcd
->state
))
707 admhc_intr_enable(ahcd
, ADMHC_INTR_TDC
);
710 if (ints
& ADMHC_INTR_SO
) {
711 /* could track INTR_SO to reduce available PCI/... bandwidth */
712 admhc_vdbg(ahcd
, "Schedule Overrun\n");
716 spin_lock(&ahcd
->lock
);
717 if (ahcd
->ed_rm_list
)
718 finish_unlinks(ahcd
, admhc_frame_no(ahcd
));
720 if ((ints
& ADMHC_INTR_SOFI
) != 0 && !ahcd
->ed_rm_list
721 && HC_IS_RUNNING(hcd
->state
))
722 admhc_intr_disable(ahcd
, ADMHC_INTR_SOFI
);
723 spin_unlock(&ahcd
->lock
);
725 if (ints
& ADMHC_INTR_SOFI
) {
726 admhc_vdbg(ahcd
, "Start Of Frame\n");
727 spin_lock(&ahcd
->lock
);
729 /* handle any pending ED removes */
730 finish_unlinks(ahcd
, admhc_frameno(ahcd
));
732 /* leaving INTR_SOFI enabled when there's still unlinking
733 * to be done in the (next frame).
735 if ((ahcd
->ed_rm_list
== NULL
) ||
736 HC_IS_RUNNING(hcd
->state
) == 0)
738 * disable INTR_SOFI if there are no unlinking to be
739 * done (in the next frame)
741 admhc_intr_disable(ahcd
, ADMHC_INTR_SOFI
);
743 spin_unlock(&ahcd
->lock
);
747 if (HC_IS_RUNNING(hcd
->state
)) {
748 admhc_intr_ack(ahcd
, ints
);
749 admhc_intr_enable(ahcd
, ADMHC_INTR_MIE
);
750 admhc_writel_flush(ahcd
);
756 /*-------------------------------------------------------------------------*/
758 static void admhc_stop(struct usb_hcd
*hcd
)
760 struct admhcd
*ahcd
= hcd_to_admhcd(hcd
);
764 flush_scheduled_work();
766 admhc_usb_reset(ahcd
);
767 admhc_intr_disable(ahcd
, ADMHC_INTR_MIE
);
769 free_irq(hcd
->irq
, hcd
);
772 remove_debug_files(ahcd
);
773 admhc_eds_cleanup(ahcd
);
774 admhc_mem_cleanup(ahcd
);
777 /*-------------------------------------------------------------------------*/
779 #ifdef CONFIG_MIPS_ADM5120
780 #include "adm5120-drv.c"
781 #define PLATFORM_DRIVER usb_hcd_adm5120_driver
784 #if !defined(PLATFORM_DRIVER)
785 #error "missing bus glue for admhc-hcd"
788 #define DRIVER_INFO DRIVER_DESC " version " DRIVER_VERSION
790 static int __init
admhc_hcd_mod_init(void)
797 pr_info("%s: " DRIVER_INFO
"\n", hcd_name
);
798 pr_info("%s: block sizes: ed %Zd td %Zd\n", hcd_name
,
799 sizeof (struct ed
), sizeof (struct td
));
801 #ifdef PLATFORM_DRIVER
802 ret
= platform_driver_register(&PLATFORM_DRIVER
);
809 #ifdef PLATFORM_DRIVER
810 platform_driver_unregister(&PLATFORM_DRIVER
);
815 module_init(admhc_hcd_mod_init
);
817 static void __exit
admhc_hcd_mod_exit(void)
819 platform_driver_unregister(&PLATFORM_DRIVER
);
821 module_exit(admhc_hcd_mod_exit
);
823 MODULE_AUTHOR(DRIVER_AUTHOR
);
824 MODULE_DESCRIPTION(DRIVER_INFO
);
825 MODULE_VERSION(DRIVER_VERSION
);
826 MODULE_LICENSE("GPL");
This page took 0.08857 seconds and 5 git commands to generate.