ar71xx: ag71xx: make ring sizes configurable via ethtool
[openwrt.git] / target / linux / cns21xx / patches-2.6.37 / 101-cns21xx-serial-support.patch
1 --- a/arch/arm/mach-cns21xx/common.h
2 +++ b/arch/arm/mach-cns21xx/common.h
3 @@ -15,4 +15,7 @@ void __init cns21xx_init_irq(void);
4
5 extern struct sys_timer cns21xx_timer;
6
7 +int __init cns21xx_register_uart0(void);
8 +int __init cns21xx_register_uart1(void);
9 +
10 #endif /* _MACH_CNS21XX_COMMON_H */
11 --- /dev/null
12 +++ b/arch/arm/mach-cns21xx/devices.c
13 @@ -0,0 +1,79 @@
14 +/*
15 + * Copyright (c) 2008 Cavium Networks
16 + * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
17 + *
18 + * This file is free software; you can redistribute it and/or modify
19 + * it under the terms of the GNU General Public License, Version 2, as
20 + * published by the Free Software Foundation.
21 + */
22 +
23 +#include <linux/kernel.h>
24 +#include <linux/init.h>
25 +#include <linux/platform_device.h>
26 +#include <linux/serial_8250.h>
27 +
28 +#include <mach/irqs.h>
29 +#include <mach/hardware.h>
30 +#include <mach/cns21xx.h>
31 +#include <mach/cns21xx_misc.h>
32 +
33 +#define CNS21XX_UART_CLOCK 24000000
34 +
35 +#define CNS21XX_UART_FLAGS (UPF_SKIP_TEST | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST)
36 +
37 +static struct plat_serial8250_port cns21xx_uart0_data[] = {
38 + {
39 + .mapbase = CNS21XX_UART0_BASE,
40 + .membase = (void *) CNS21XX_UART0_BASE_VIRT,
41 + .irq = CNS21XX_IRQ_UART0,
42 + .uartclk = CNS21XX_UART_CLOCK,
43 + .regshift = 2,
44 + .iotype = UPIO_MEM,
45 + .type = PORT_16550A,
46 + .flags = CNS21XX_UART_FLAGS,
47 + }, {
48 + /* terminating entry */
49 + },
50 +};
51 +
52 +static struct platform_device cns21xx_uart0_device = {
53 + .name = "serial8250",
54 + .id = PLAT8250_DEV_PLATFORM,
55 + .dev = {
56 + .platform_data = cns21xx_uart0_data,
57 + },
58 +};
59 +
60 +int __init cns21xx_register_uart0(void)
61 +{
62 + return platform_device_register(&cns21xx_uart0_device);
63 +}
64 +
65 +static struct plat_serial8250_port cns21xx_uart1_data[] = {
66 + {
67 + .mapbase = CNS21XX_UART1_BASE,
68 + .membase = (void *) CNS21XX_UART1_BASE_VIRT,
69 + .irq = CNS21XX_IRQ_UART1,
70 + .uartclk = CNS21XX_UART_CLOCK,
71 + .regshift = 2,
72 + .iotype = UPIO_MEM,
73 + .type = PORT_16550A,
74 + .flags = CNS21XX_UART_FLAGS,
75 + }, {
76 + /* terminating entry */
77 + },
78 +};
79 +
80 +static struct platform_device cns21xx_uart1_device = {
81 + .name = "serial8250",
82 + .id = PLAT8250_DEV_PLATFORM1,
83 + .dev = {
84 + .platform_data = cns21xx_uart1_data,
85 + },
86 +};
87 +
88 +int __init cns21xx_register_uart1(void)
89 +{
90 + HAL_MISC_ENABLE_UART1_PINS();
91 + return platform_device_register(&cns21xx_uart1_device);
92 +}
93 --- a/arch/arm/mach-cns21xx/Makefile
94 +++ b/arch/arm/mach-cns21xx/Makefile
95 @@ -4,7 +4,7 @@
96
97 # Object file lists.
98
99 -obj-y := core.o irq.o mm.o time.o
100 +obj-y := core.o devices.o irq.o mm.o time.o
101
102 # machine specific files
103
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