target/linux/adm5120/files/arch/mips/pci/ops-adm5120.c

   1 /*
   2  *  $Id$
   3  *
   4  *  ADM5120 specific PCI operations
   5  *
   6  *  Copyright (C) ADMtek Incorporated.
   7  *  Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
   8  *  Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
   9  *  Copyright (C) 2007 OpenWrt.org
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version 2
  14  *  of the License, or (at your option) any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *  GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; if not, write to the
  23  *  Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  24  *  Boston, MA  02110-1301, USA.
  25  *
  26  */
  27
  28 #include <linux/types.h>
  29 #include <linux/kernel.h>
  30 #include <linux/pci.h>
  31 #include <linux/spinlock.h>
  32
  33 #include <asm/mach-adm5120/adm5120_defs.h>
  34
  35 #define DEBUG   0
  36 #if DEBUG
  37 #define DBG(f, ...) printk(f, ## __VA_ARGS__ )
  38 #else
  39 #define DBG(f, ...)
  40 #endif
  41
  42 #define PCI_ENABLE 0x80000000
  43
  44 static spinlock_t pci_lock = SPIN_LOCK_UNLOCKED;
  45
  46 static inline void write_cfgaddr(u32 addr)
  47 {
  48         *(volatile u32*)KSEG1ADDR(ADM5120_PCICFG_ADDR) = (addr | PCI_ENABLE);
  49 }
  50
  51 static inline void write_cfgdata(u32 data)
  52 {
  53         *(volatile u32*)KSEG1ADDR(ADM5120_PCICFG_DATA) = data;
  54
  55 }
  56
  57 static inline u32 read_cfgdata(void)
  58 {
  59         return (*(volatile u32*)KSEG1ADDR(ADM5120_PCICFG_DATA));
  60 }
  61
  62 static inline u32 mkaddr(struct pci_bus *bus, unsigned int devfn, int where)
  63 {
  64         return (((bus->number & 0xFF) << 16) | ((devfn & 0xFF) << 8) | \
  65                 (where & 0xFC));
  66 }
  67
  68 static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
  69                            int size, u32 *val)
  70 {
  71         unsigned long flags;
  72         u32 data;
  73
  74         spin_lock_irqsave(&pci_lock, flags);
  75         write_cfgaddr(mkaddr(bus,devfn,where));
  76         data = read_cfgdata();
  77
  78         DBG("PCI: cfg_read  %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
  79                 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, data);
  80
  81         switch (size) {
  82         case 1:
  83                 if (where & 1)
  84                         data >>= 8;
  85                 if (where & 2)
  86                         data >>= 16;
  87                 data &= 0xFF;
  88                 break;
  89         case 2:
  90                 if (where & 2)
  91                         data >>= 16;
  92                 data &= 0xFFFF;
  93                 break;
  94         }
  95
  96         *val = data;
  97         DBG(", 0x%08X returned\n", data);
  98         spin_unlock_irqrestore(&pci_lock, flags);
  99
 100         return PCIBIOS_SUCCESSFUL;
 101 }
 102
 103 static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
 104                             int size, u32 val)
 105 {
 106         unsigned long flags;
 107         u32 data;
 108         int s;
 109
 110         spin_lock_irqsave(&pci_lock, flags);
 111         write_cfgaddr(mkaddr(bus,devfn,where));
 112         data = read_cfgdata();
 113
 114         DBG("PCI: cfg_write %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
 115                 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, data);
 116
 117         switch (size) {
 118         case 1:
 119                 s = ((where & 3) << 3);
 120                 data &= ~(0xFF << s);
 121                 data |= ((val & 0xFF) << s);
 122                 break;
 123         case 2:
 124                 s = ((where & 2) << 4);
 125                 data &= ~(0xFFFF << s);
 126                 data |= ((val & 0xFFFF) << s);
 127                 break;
 128         case 4:
 129                 data = val;
 130                 break;
 131         }
 132
 133         write_cfgdata(data);
 134         DBG(", 0x%08X written\n", data);
 135         spin_unlock_irqrestore(&pci_lock, flags);
 136
 137         return PCIBIOS_SUCCESSFUL;
 138 }
 139
 140 struct pci_ops adm5120_pci_ops = {
 141         .read   = pci_config_read,
 142         .write  = pci_config_write,
 143 };