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fix errors in unresolved weak symbols on arm
[openwrt.git] / target / linux / generic-2.6 / patches-2.6.28 / 976-ssb_update.patch
1 --- /dev/null
2 +++ b/drivers/ssb/driver_chipcommon_pmu.c
3 @@ -0,0 +1,602 @@
4 +/*
5 + * Sonics Silicon Backplane
6 + * Broadcom ChipCommon Power Management Unit driver
7 + *
8 + * Copyright 2009, Michael Buesch <mb@bu3sch.de>
9 + * Copyright 2007, Broadcom Corporation
10 + *
11 + * Licensed under the GNU/GPL. See COPYING for details.
12 + */
13 +
14 +#include <linux/ssb/ssb.h>
15 +#include <linux/ssb/ssb_regs.h>
16 +#include <linux/ssb/ssb_driver_chipcommon.h>
17 +#include <linux/delay.h>
18 +
19 +#include "ssb_private.h"
20 +
21 +static u32 ssb_chipco_pll_read(struct ssb_chipcommon *cc, u32 offset)
22 +{
23 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset);
24 + return chipco_read32(cc, SSB_CHIPCO_PLLCTL_DATA);
25 +}
26 +
27 +static void ssb_chipco_pll_write(struct ssb_chipcommon *cc,
28 + u32 offset, u32 value)
29 +{
30 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset);
31 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, value);
32 +}
33 +
34 +static void ssb_chipco_regctl_maskset(struct ssb_chipcommon *cc,
35 + u32 offset, u32 mask, u32 set)
36 +{
37 + u32 value;
38 +
39 + chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR);
40 + chipco_write32(cc, SSB_CHIPCO_REGCTL_ADDR, offset);
41 + chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR);
42 + value = chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA);
43 + value &= mask;
44 + value |= set;
45 + chipco_write32(cc, SSB_CHIPCO_REGCTL_DATA, value);
46 + chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA);
47 +}
48 +
49 +struct pmu0_plltab_entry {
50 + u16 freq; /* Crystal frequency in kHz.*/
51 + u8 xf; /* Crystal frequency value for PMU control */
52 + u8 wb_int;
53 + u32 wb_frac;
54 +};
55 +
56 +static const struct pmu0_plltab_entry pmu0_plltab[] = {
57 + { .freq = 12000, .xf = 1, .wb_int = 73, .wb_frac = 349525, },
58 + { .freq = 13000, .xf = 2, .wb_int = 67, .wb_frac = 725937, },
59 + { .freq = 14400, .xf = 3, .wb_int = 61, .wb_frac = 116508, },
60 + { .freq = 15360, .xf = 4, .wb_int = 57, .wb_frac = 305834, },
61 + { .freq = 16200, .xf = 5, .wb_int = 54, .wb_frac = 336579, },
62 + { .freq = 16800, .xf = 6, .wb_int = 52, .wb_frac = 399457, },
63 + { .freq = 19200, .xf = 7, .wb_int = 45, .wb_frac = 873813, },
64 + { .freq = 19800, .xf = 8, .wb_int = 44, .wb_frac = 466033, },
65 + { .freq = 20000, .xf = 9, .wb_int = 44, .wb_frac = 0, },
66 + { .freq = 25000, .xf = 10, .wb_int = 70, .wb_frac = 419430, },
67 + { .freq = 26000, .xf = 11, .wb_int = 67, .wb_frac = 725937, },
68 + { .freq = 30000, .xf = 12, .wb_int = 58, .wb_frac = 699050, },
69 + { .freq = 38400, .xf = 13, .wb_int = 45, .wb_frac = 873813, },
70 + { .freq = 40000, .xf = 14, .wb_int = 45, .wb_frac = 0, },
71 +};
72 +#define SSB_PMU0_DEFAULT_XTALFREQ 20000
73 +
74 +static const struct pmu0_plltab_entry * pmu0_plltab_find_entry(u32 crystalfreq)
75 +{
76 + const struct pmu0_plltab_entry *e;
77 + unsigned int i;
78 +
79 + for (i = 0; i < ARRAY_SIZE(pmu0_plltab); i++) {
80 + e = &pmu0_plltab[i];
81 + if (e->freq == crystalfreq)
82 + return e;
83 + }
84 +
85 + return NULL;
86 +}
87 +
88 +/* Tune the PLL to the crystal speed. crystalfreq is in kHz. */
89 +static void ssb_pmu0_pllinit_r0(struct ssb_chipcommon *cc,
90 + u32 crystalfreq)
91 +{
92 + struct ssb_bus *bus = cc->dev->bus;
93 + const struct pmu0_plltab_entry *e = NULL;
94 + u32 pmuctl, tmp, pllctl;
95 + unsigned int i;
96 +
97 + if ((bus->chip_id == 0x5354) && !crystalfreq) {
98 + /* The 5354 crystal freq is 25MHz */
99 + crystalfreq = 25000;
100 + }
101 + if (crystalfreq)
102 + e = pmu0_plltab_find_entry(crystalfreq);
103 + if (!e)
104 + e = pmu0_plltab_find_entry(SSB_PMU0_DEFAULT_XTALFREQ);
105 + BUG_ON(!e);
106 + crystalfreq = e->freq;
107 + cc->pmu.crystalfreq = e->freq;
108 +
109 + /* Check if the PLL already is programmed to this frequency. */
110 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
111 + if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) {
112 + /* We're already there... */
113 + return;
114 + }
115 +
116 + ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
117 + (crystalfreq / 1000), (crystalfreq % 1000));
118 +
119 + /* First turn the PLL off. */
120 + switch (bus->chip_id) {
121 + case 0x4328:
122 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
123 + ~(1 << SSB_PMURES_4328_BB_PLL_PU));
124 + chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
125 + ~(1 << SSB_PMURES_4328_BB_PLL_PU));
126 + break;
127 + case 0x5354:
128 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
129 + ~(1 << SSB_PMURES_5354_BB_PLL_PU));
130 + chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
131 + ~(1 << SSB_PMURES_5354_BB_PLL_PU));
132 + break;
133 + default:
134 + SSB_WARN_ON(1);
135 + }
136 + for (i = 1500; i; i--) {
137 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
138 + if (!(tmp & SSB_CHIPCO_CLKCTLST_HAVEHT))
139 + break;
140 + udelay(10);
141 + }
142 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
143 + if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
144 + ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
145 +
146 + /* Set PDIV in PLL control 0. */
147 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0);
148 + if (crystalfreq >= SSB_PMU0_PLLCTL0_PDIV_FREQ)
149 + pllctl |= SSB_PMU0_PLLCTL0_PDIV_MSK;
150 + else
151 + pllctl &= ~SSB_PMU0_PLLCTL0_PDIV_MSK;
152 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL0, pllctl);
153 +
154 + /* Set WILD in PLL control 1. */
155 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL1);
156 + pllctl &= ~SSB_PMU0_PLLCTL1_STOPMOD;
157 + pllctl &= ~(SSB_PMU0_PLLCTL1_WILD_IMSK | SSB_PMU0_PLLCTL1_WILD_FMSK);
158 + pllctl |= ((u32)e->wb_int << SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT) & SSB_PMU0_PLLCTL1_WILD_IMSK;
159 + pllctl |= ((u32)e->wb_frac << SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT) & SSB_PMU0_PLLCTL1_WILD_FMSK;
160 + if (e->wb_frac == 0)
161 + pllctl |= SSB_PMU0_PLLCTL1_STOPMOD;
162 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL1, pllctl);
163 +
164 + /* Set WILD in PLL control 2. */
165 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL2);
166 + pllctl &= ~SSB_PMU0_PLLCTL2_WILD_IMSKHI;
167 + pllctl |= (((u32)e->wb_int >> 4) << SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT) & SSB_PMU0_PLLCTL2_WILD_IMSKHI;
168 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL2, pllctl);
169 +
170 + /* Set the crystalfrequency and the divisor. */
171 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
172 + pmuctl &= ~SSB_CHIPCO_PMU_CTL_ILP_DIV;
173 + pmuctl |= (((crystalfreq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT)
174 + & SSB_CHIPCO_PMU_CTL_ILP_DIV;
175 + pmuctl &= ~SSB_CHIPCO_PMU_CTL_XTALFREQ;
176 + pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ;
177 + chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl);
178 +}
179 +
180 +struct pmu1_plltab_entry {
181 + u16 freq; /* Crystal frequency in kHz.*/
182 + u8 xf; /* Crystal frequency value for PMU control */
183 + u8 ndiv_int;
184 + u32 ndiv_frac;
185 + u8 p1div;
186 + u8 p2div;
187 +};
188 +
189 +static const struct pmu1_plltab_entry pmu1_plltab[] = {
190 + { .freq = 12000, .xf = 1, .p1div = 3, .p2div = 22, .ndiv_int = 0x9, .ndiv_frac = 0xFFFFEF, },
191 + { .freq = 13000, .xf = 2, .p1div = 1, .p2div = 6, .ndiv_int = 0xb, .ndiv_frac = 0x483483, },
192 + { .freq = 14400, .xf = 3, .p1div = 1, .p2div = 10, .ndiv_int = 0xa, .ndiv_frac = 0x1C71C7, },
193 + { .freq = 15360, .xf = 4, .p1div = 1, .p2div = 5, .ndiv_int = 0xb, .ndiv_frac = 0x755555, },
194 + { .freq = 16200, .xf = 5, .p1div = 1, .p2div = 10, .ndiv_int = 0x5, .ndiv_frac = 0x6E9E06, },
195 + { .freq = 16800, .xf = 6, .p1div = 1, .p2div = 10, .ndiv_int = 0x5, .ndiv_frac = 0x3CF3CF, },
196 + { .freq = 19200, .xf = 7, .p1div = 1, .p2div = 9, .ndiv_int = 0x5, .ndiv_frac = 0x17B425, },
197 + { .freq = 19800, .xf = 8, .p1div = 1, .p2div = 11, .ndiv_int = 0x4, .ndiv_frac = 0xA57EB, },
198 + { .freq = 20000, .xf = 9, .p1div = 1, .p2div = 11, .ndiv_int = 0x4, .ndiv_frac = 0, },
199 + { .freq = 24000, .xf = 10, .p1div = 3, .p2div = 11, .ndiv_int = 0xa, .ndiv_frac = 0, },
200 + { .freq = 25000, .xf = 11, .p1div = 5, .p2div = 16, .ndiv_int = 0xb, .ndiv_frac = 0, },
201 + { .freq = 26000, .xf = 12, .p1div = 1, .p2div = 2, .ndiv_int = 0x10, .ndiv_frac = 0xEC4EC4, },
202 + { .freq = 30000, .xf = 13, .p1div = 3, .p2div = 8, .ndiv_int = 0xb, .ndiv_frac = 0, },
203 + { .freq = 38400, .xf = 14, .p1div = 1, .p2div = 5, .ndiv_int = 0x4, .ndiv_frac = 0x955555, },
204 + { .freq = 40000, .xf = 15, .p1div = 1, .p2div = 2, .ndiv_int = 0xb, .ndiv_frac = 0, },
205 +};
206 +
207 +#define SSB_PMU1_DEFAULT_XTALFREQ 15360
208 +
209 +static const struct pmu1_plltab_entry * pmu1_plltab_find_entry(u32 crystalfreq)
210 +{
211 + const struct pmu1_plltab_entry *e;
212 + unsigned int i;
213 +
214 + for (i = 0; i < ARRAY_SIZE(pmu1_plltab); i++) {
215 + e = &pmu1_plltab[i];
216 + if (e->freq == crystalfreq)
217 + return e;
218 + }
219 +
220 + return NULL;
221 +}
222 +
223 +/* Tune the PLL to the crystal speed. crystalfreq is in kHz. */
224 +static void ssb_pmu1_pllinit_r0(struct ssb_chipcommon *cc,
225 + u32 crystalfreq)
226 +{
227 + struct ssb_bus *bus = cc->dev->bus;
228 + const struct pmu1_plltab_entry *e = NULL;
229 + u32 buffer_strength = 0;
230 + u32 tmp, pllctl, pmuctl;
231 + unsigned int i;
232 +
233 + if (bus->chip_id == 0x4312) {
234 + /* We do not touch the BCM4312 PLL and assume
235 + * the default crystal settings work out-of-the-box. */
236 + cc->pmu.crystalfreq = 20000;
237 + return;
238 + }
239 +
240 + if (crystalfreq)
241 + e = pmu1_plltab_find_entry(crystalfreq);
242 + if (!e)
243 + e = pmu1_plltab_find_entry(SSB_PMU1_DEFAULT_XTALFREQ);
244 + BUG_ON(!e);
245 + crystalfreq = e->freq;
246 + cc->pmu.crystalfreq = e->freq;
247 +
248 + /* Check if the PLL already is programmed to this frequency. */
249 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
250 + if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) {
251 + /* We're already there... */
252 + return;
253 + }
254 +
255 + ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
256 + (crystalfreq / 1000), (crystalfreq % 1000));
257 +
258 + /* First turn the PLL off. */
259 + switch (bus->chip_id) {
260 + case 0x4325:
261 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
262 + ~((1 << SSB_PMURES_4325_BBPLL_PWRSW_PU) |
263 + (1 << SSB_PMURES_4325_HT_AVAIL)));
264 + chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
265 + ~((1 << SSB_PMURES_4325_BBPLL_PWRSW_PU) |
266 + (1 << SSB_PMURES_4325_HT_AVAIL)));
267 + /* Adjust the BBPLL to 2 on all channels later. */
268 + buffer_strength = 0x222222;
269 + break;
270 + default:
271 + SSB_WARN_ON(1);
272 + }
273 + for (i = 1500; i; i--) {
274 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
275 + if (!(tmp & SSB_CHIPCO_CLKCTLST_HAVEHT))
276 + break;
277 + udelay(10);
278 + }
279 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
280 + if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
281 + ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
282 +
283 + /* Set p1div and p2div. */
284 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0);
285 + pllctl &= ~(SSB_PMU1_PLLCTL0_P1DIV | SSB_PMU1_PLLCTL0_P2DIV);
286 + pllctl |= ((u32)e->p1div << SSB_PMU1_PLLCTL0_P1DIV_SHIFT) & SSB_PMU1_PLLCTL0_P1DIV;
287 + pllctl |= ((u32)e->p2div << SSB_PMU1_PLLCTL0_P2DIV_SHIFT) & SSB_PMU1_PLLCTL0_P2DIV;
288 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, pllctl);
289 +
290 + /* Set ndiv int and ndiv mode */
291 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL2);
292 + pllctl &= ~(SSB_PMU1_PLLCTL2_NDIVINT | SSB_PMU1_PLLCTL2_NDIVMODE);
293 + pllctl |= ((u32)e->ndiv_int << SSB_PMU1_PLLCTL2_NDIVINT_SHIFT) & SSB_PMU1_PLLCTL2_NDIVINT;
294 + pllctl |= (1 << SSB_PMU1_PLLCTL2_NDIVMODE_SHIFT) & SSB_PMU1_PLLCTL2_NDIVMODE;
295 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, pllctl);
296 +
297 + /* Set ndiv frac */
298 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL3);
299 + pllctl &= ~SSB_PMU1_PLLCTL3_NDIVFRAC;
300 + pllctl |= ((u32)e->ndiv_frac << SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT) & SSB_PMU1_PLLCTL3_NDIVFRAC;
301 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, pllctl);
302 +
303 + /* Change the drive strength, if required. */
304 + if (buffer_strength) {
305 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL5);
306 + pllctl &= ~SSB_PMU1_PLLCTL5_CLKDRV;
307 + pllctl |= (buffer_strength << SSB_PMU1_PLLCTL5_CLKDRV_SHIFT) & SSB_PMU1_PLLCTL5_CLKDRV;
308 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, pllctl);
309 + }
310 +
311 + /* Tune the crystalfreq and the divisor. */
312 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
313 + pmuctl &= ~(SSB_CHIPCO_PMU_CTL_ILP_DIV | SSB_CHIPCO_PMU_CTL_XTALFREQ);
314 + pmuctl |= ((((u32)e->freq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT)
315 + & SSB_CHIPCO_PMU_CTL_ILP_DIV;
316 + pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ;
317 + chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl);
318 +}
319 +
320 +static void ssb_pmu_pll_init(struct ssb_chipcommon *cc)
321 +{
322 + struct ssb_bus *bus = cc->dev->bus;
323 + u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
324 +
325 + if (bus->bustype == SSB_BUSTYPE_SSB) {
326 + /* TODO: The user may override the crystal frequency. */
327 + }
328 +
329 + switch (bus->chip_id) {
330 + case 0x4312:
331 + case 0x4325:
332 + ssb_pmu1_pllinit_r0(cc, crystalfreq);
333 + break;
334 + case 0x4328:
335 + case 0x5354:
336 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
337 + break;
338 + default:
339 + ssb_printk(KERN_ERR PFX
340 + "ERROR: PLL init unknown for device %04X\n",
341 + bus->chip_id);
342 + }
343 +}
344 +
345 +struct pmu_res_updown_tab_entry {
346 + u8 resource; /* The resource number */
347 + u16 updown; /* The updown value */
348 +};
349 +
350 +enum pmu_res_depend_tab_task {
351 + PMU_RES_DEP_SET = 1,
352 + PMU_RES_DEP_ADD,
353 + PMU_RES_DEP_REMOVE,
354 +};
355 +
356 +struct pmu_res_depend_tab_entry {
357 + u8 resource; /* The resource number */
358 + u8 task; /* SET | ADD | REMOVE */
359 + u32 depend; /* The depend mask */
360 +};
361 +
362 +static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4328a0[] = {
363 + { .resource = SSB_PMURES_4328_EXT_SWITCHER_PWM, .updown = 0x0101, },
364 + { .resource = SSB_PMURES_4328_BB_SWITCHER_PWM, .updown = 0x1F01, },
365 + { .resource = SSB_PMURES_4328_BB_SWITCHER_BURST, .updown = 0x010F, },
366 + { .resource = SSB_PMURES_4328_BB_EXT_SWITCHER_BURST, .updown = 0x0101, },
367 + { .resource = SSB_PMURES_4328_ILP_REQUEST, .updown = 0x0202, },
368 + { .resource = SSB_PMURES_4328_RADIO_SWITCHER_PWM, .updown = 0x0F01, },
369 + { .resource = SSB_PMURES_4328_RADIO_SWITCHER_BURST, .updown = 0x0F01, },
370 + { .resource = SSB_PMURES_4328_ROM_SWITCH, .updown = 0x0101, },
371 + { .resource = SSB_PMURES_4328_PA_REF_LDO, .updown = 0x0F01, },
372 + { .resource = SSB_PMURES_4328_RADIO_LDO, .updown = 0x0F01, },
373 + { .resource = SSB_PMURES_4328_AFE_LDO, .updown = 0x0F01, },
374 + { .resource = SSB_PMURES_4328_PLL_LDO, .updown = 0x0F01, },
375 + { .resource = SSB_PMURES_4328_BG_FILTBYP, .updown = 0x0101, },
376 + { .resource = SSB_PMURES_4328_TX_FILTBYP, .updown = 0x0101, },
377 + { .resource = SSB_PMURES_4328_RX_FILTBYP, .updown = 0x0101, },
378 + { .resource = SSB_PMURES_4328_XTAL_PU, .updown = 0x0101, },
379 + { .resource = SSB_PMURES_4328_XTAL_EN, .updown = 0xA001, },
380 + { .resource = SSB_PMURES_4328_BB_PLL_FILTBYP, .updown = 0x0101, },
381 + { .resource = SSB_PMURES_4328_RF_PLL_FILTBYP, .updown = 0x0101, },
382 + { .resource = SSB_PMURES_4328_BB_PLL_PU, .updown = 0x0701, },
383 +};
384 +
385 +static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4328a0[] = {
386 + {
387 + /* Adjust ILP Request to avoid forcing EXT/BB into burst mode. */
388 + .resource = SSB_PMURES_4328_ILP_REQUEST,
389 + .task = PMU_RES_DEP_SET,
390 + .depend = ((1 << SSB_PMURES_4328_EXT_SWITCHER_PWM) |
391 + (1 << SSB_PMURES_4328_BB_SWITCHER_PWM)),
392 + },
393 +};
394 +
395 +static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4325a0[] = {
396 + { .resource = SSB_PMURES_4325_XTAL_PU, .updown = 0x1501, },
397 +};
398 +
399 +static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4325a0[] = {
400 + {
401 + /* Adjust HT-Available dependencies. */
402 + .resource = SSB_PMURES_4325_HT_AVAIL,
403 + .task = PMU_RES_DEP_ADD,
404 + .depend = ((1 << SSB_PMURES_4325_RX_PWRSW_PU) |
405 + (1 << SSB_PMURES_4325_TX_PWRSW_PU) |
406 + (1 << SSB_PMURES_4325_LOGEN_PWRSW_PU) |
407 + (1 << SSB_PMURES_4325_AFE_PWRSW_PU)),
408 + },
409 +};
410 +
411 +static void ssb_pmu_resources_init(struct ssb_chipcommon *cc)
412 +{
413 + struct ssb_bus *bus = cc->dev->bus;
414 + u32 min_msk = 0, max_msk = 0;
415 + unsigned int i;
416 + const struct pmu_res_updown_tab_entry *updown_tab = NULL;
417 + unsigned int updown_tab_size;
418 + const struct pmu_res_depend_tab_entry *depend_tab = NULL;
419 + unsigned int depend_tab_size;
420 +
421 + switch (bus->chip_id) {
422 + case 0x4312:
423 + /* We keep the default settings:
424 + * min_msk = 0xCBB
425 + * max_msk = 0x7FFFF
426 + */
427 + break;
428 + case 0x4325:
429 + /* Power OTP down later. */
430 + min_msk = (1 << SSB_PMURES_4325_CBUCK_BURST) |
431 + (1 << SSB_PMURES_4325_LNLDO2_PU);
432 + if (chipco_read32(cc, SSB_CHIPCO_CHIPSTAT) &
433 + SSB_CHIPCO_CHST_4325_PMUTOP_2B)
434 + min_msk |= (1 << SSB_PMURES_4325_CLDO_CBUCK_BURST);
435 + /* The PLL may turn on, if it decides so. */
436 + max_msk = 0xFFFFF;
437 + updown_tab = pmu_res_updown_tab_4325a0;
438 + updown_tab_size = ARRAY_SIZE(pmu_res_updown_tab_4325a0);
439 + depend_tab = pmu_res_depend_tab_4325a0;
440 + depend_tab_size = ARRAY_SIZE(pmu_res_depend_tab_4325a0);
441 + break;
442 + case 0x4328:
443 + min_msk = (1 << SSB_PMURES_4328_EXT_SWITCHER_PWM) |
444 + (1 << SSB_PMURES_4328_BB_SWITCHER_PWM) |
445 + (1 << SSB_PMURES_4328_XTAL_EN);
446 + /* The PLL may turn on, if it decides so. */
447 + max_msk = 0xFFFFF;
448 + updown_tab = pmu_res_updown_tab_4328a0;
449 + updown_tab_size = ARRAY_SIZE(pmu_res_updown_tab_4328a0);
450 + depend_tab = pmu_res_depend_tab_4328a0;
451 + depend_tab_size = ARRAY_SIZE(pmu_res_depend_tab_4328a0);
452 + break;
453 + case 0x5354:
454 + /* The PLL may turn on, if it decides so. */
455 + max_msk = 0xFFFFF;
456 + break;
457 + default:
458 + ssb_printk(KERN_ERR PFX
459 + "ERROR: PMU resource config unknown for device %04X\n",
460 + bus->chip_id);
461 + }
462 +
463 + if (updown_tab) {
464 + for (i = 0; i < updown_tab_size; i++) {
465 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_TABSEL,
466 + updown_tab[i].resource);
467 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_UPDNTM,
468 + updown_tab[i].updown);
469 + }
470 + }
471 + if (depend_tab) {
472 + for (i = 0; i < depend_tab_size; i++) {
473 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_TABSEL,
474 + depend_tab[i].resource);
475 + switch (depend_tab[i].task) {
476 + case PMU_RES_DEP_SET:
477 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
478 + depend_tab[i].depend);
479 + break;
480 + case PMU_RES_DEP_ADD:
481 + chipco_set32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
482 + depend_tab[i].depend);
483 + break;
484 + case PMU_RES_DEP_REMOVE:
485 + chipco_mask32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
486 + ~(depend_tab[i].depend));
487 + break;
488 + default:
489 + SSB_WARN_ON(1);
490 + }
491 + }
492 + }
493 +
494 + /* Set the resource masks. */
495 + if (min_msk)
496 + chipco_write32(cc, SSB_CHIPCO_PMU_MINRES_MSK, min_msk);
497 + if (max_msk)
498 + chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
499 +}
500 +
501 +void ssb_pmu_init(struct ssb_chipcommon *cc)
502 +{
503 + struct ssb_bus *bus = cc->dev->bus;
504 + u32 pmucap;
505 +
506 + if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
507 + return;
508 +
509 + pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP);
510 + cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION);
511 +
512 + ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
513 + cc->pmu.rev, pmucap);
514 +
515 + if (cc->pmu.rev >= 1) {
516 + if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) {
517 + chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
518 + ~SSB_CHIPCO_PMU_CTL_NOILPONW);
519 + } else {
520 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
521 + SSB_CHIPCO_PMU_CTL_NOILPONW);
522 + }
523 + }
524 + ssb_pmu_pll_init(cc);
525 + ssb_pmu_resources_init(cc);
526 +}
527 +
528 +void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
529 + enum ssb_pmu_ldo_volt_id id, u32 voltage)
530 +{
531 + struct ssb_bus *bus = cc->dev->bus;
532 + u32 addr, shift, mask;
533 +
534 + switch (bus->chip_id) {
535 + case 0x4328:
536 + case 0x5354:
537 + switch (id) {
538 + case LDO_VOLT1:
539 + addr = 2;
540 + shift = 25;
541 + mask = 0xF;
542 + break;
543 + case LDO_VOLT2:
544 + addr = 3;
545 + shift = 1;
546 + mask = 0xF;
547 + break;
548 + case LDO_VOLT3:
549 + addr = 3;
550 + shift = 9;
551 + mask = 0xF;
552 + break;
553 + case LDO_PAREF:
554 + addr = 3;
555 + shift = 17;
556 + mask = 0x3F;
557 + break;
558 + default:
559 + SSB_WARN_ON(1);
560 + return;
561 + }
562 + break;
563 + case 0x4312:
564 + if (SSB_WARN_ON(id != LDO_PAREF))
565 + return;
566 + addr = 0;
567 + shift = 21;
568 + mask = 0x3F;
569 + break;
570 + default:
571 + return;
572 + }
573 +
574 + ssb_chipco_regctl_maskset(cc, addr, ~(mask << shift),
575 + (voltage & mask) << shift);
576 +}
577 +
578 +void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on)
579 +{
580 + struct ssb_bus *bus = cc->dev->bus;
581 + int ldo;
582 +
583 + switch (bus->chip_id) {
584 + case 0x4312:
585 + ldo = SSB_PMURES_4312_PA_REF_LDO;
586 + break;
587 + case 0x4328:
588 + ldo = SSB_PMURES_4328_PA_REF_LDO;
589 + break;
590 + case 0x5354:
591 + ldo = SSB_PMURES_5354_PA_REF_LDO;
592 + break;
593 + default:
594 + return;
595 + }
596 +
597 + if (on)
598 + chipco_set32(cc, SSB_CHIPCO_PMU_MINRES_MSK, 1 << ldo);
599 + else
600 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK, ~(1 << ldo));
601 + chipco_read32(cc, SSB_CHIPCO_PMU_MINRES_MSK); //SPEC FIXME found via mmiotrace - dummy read?
602 +}
603 +
604 +EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
605 +EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
606 --- a/drivers/ssb/Kconfig
607 +++ b/drivers/ssb/Kconfig
608 @@ -53,11 +53,11 @@ config SSB_B43_PCI_BRIDGE
609
610 config SSB_PCMCIAHOST_POSSIBLE
611 bool
612 - depends on SSB && (PCMCIA = y || PCMCIA = SSB) && EXPERIMENTAL
613 + depends on SSB && (PCMCIA = y || PCMCIA = SSB)
614 default y
615
616 config SSB_PCMCIAHOST
617 - bool "Support for SSB on PCMCIA-bus host (EXPERIMENTAL)"
618 + bool "Support for SSB on PCMCIA-bus host"
619 depends on SSB_PCMCIAHOST_POSSIBLE
620 select SSB_SPROM
621 help
622 @@ -107,14 +107,14 @@ config SSB_DRIVER_PCICORE
623 If unsure, say Y
624
625 config SSB_PCICORE_HOSTMODE
626 - bool "Hostmode support for SSB PCI core (EXPERIMENTAL)"
627 - depends on SSB_DRIVER_PCICORE && SSB_DRIVER_MIPS && EXPERIMENTAL
628 + bool "Hostmode support for SSB PCI core"
629 + depends on SSB_DRIVER_PCICORE && SSB_DRIVER_MIPS
630 help
631 PCIcore hostmode operation (external PCI bus).
632
633 config SSB_DRIVER_MIPS
634 - bool "SSB Broadcom MIPS core driver (EXPERIMENTAL)"
635 - depends on SSB && MIPS && EXPERIMENTAL
636 + bool "SSB Broadcom MIPS core driver"
637 + depends on SSB && MIPS
638 select SSB_SERIAL
639 help
640 Driver for the Sonics Silicon Backplane attached
641 @@ -126,11 +126,13 @@ config SSB_DRIVER_MIPS
642 config SSB_EMBEDDED
643 bool
644 depends on SSB_DRIVER_MIPS
645 + select USB_EHCI_HCD_SSB if USB_EHCI_HCD
646 + select USB_OHCI_HCD_SSB if USB_OHCI_HCD
647 default y
648
649 config SSB_DRIVER_EXTIF
650 - bool "SSB Broadcom EXTIF core driver (EXPERIMENTAL)"
651 - depends on SSB_DRIVER_MIPS && EXPERIMENTAL
652 + bool "SSB Broadcom EXTIF core driver"
653 + depends on SSB_DRIVER_MIPS
654 help
655 Driver for the Sonics Silicon Backplane attached
656 Broadcom EXTIF core.
657 --- a/drivers/ssb/Makefile
658 +++ b/drivers/ssb/Makefile
659 @@ -9,6 +9,7 @@ ssb-$(CONFIG_SSB_PCMCIAHOST) += pcmcia.
660
661 # built-in drivers
662 ssb-y += driver_chipcommon.o
663 +ssb-y += driver_chipcommon_pmu.o
664 ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
665 ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
666 ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
667 --- a/drivers/ssb/b43_pci_bridge.c
668 +++ b/drivers/ssb/b43_pci_bridge.c
669 @@ -18,9 +18,11 @@
670
671 static const struct pci_device_id b43_pci_bridge_tbl[] = {
672 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4301) },
673 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4306) },
674 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4307) },
675 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4311) },
676 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4312) },
677 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4315) },
678 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4318) },
679 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
680 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
681 @@ -29,6 +31,7 @@ static const struct pci_device_id b43_pc
682 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
683 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4328) },
684 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
685 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
686 { 0, },
687 };
688 MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
689 --- a/drivers/ssb/main.c
690 +++ b/drivers/ssb/main.c
691 @@ -1359,8 +1359,10 @@ static int __init ssb_modinit(void)
692 ssb_buses_lock();
693 err = ssb_attach_queued_buses();
694 ssb_buses_unlock();
695 - if (err)
696 + if (err) {
697 bus_unregister(&ssb_bustype);
698 + goto out;
699 + }
700
701 err = b43_pci_ssb_bridge_init();
702 if (err) {
703 @@ -1376,7 +1378,7 @@ static int __init ssb_modinit(void)
704 /* don't fail SSB init because of this */
705 err = 0;
706 }
707 -
708 +out:
709 return err;
710 }
711 /* ssb must be initialized after PCI but before the ssb drivers.
712 --- a/drivers/ssb/pci.c
713 +++ b/drivers/ssb/pci.c
714 @@ -169,8 +169,14 @@ err_pci:
715 /* Get the word-offset for a SSB_SPROM_XXX define. */
716 #define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
717 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
718 -#define SPEX(_outvar, _offset, _mask, _shift) \
719 +#define SPEX16(_outvar, _offset, _mask, _shift) \
720 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
721 +#define SPEX32(_outvar, _offset, _mask, _shift) \
722 + out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
723 + in[SPOFF(_offset)]) & (_mask)) >> (_shift))
724 +#define SPEX(_outvar, _offset, _mask, _shift) \
725 + SPEX16(_outvar, _offset, _mask, _shift)
726 +
727
728 static inline u8 ssb_crc8(u8 crc, u8 data)
729 {
730 @@ -467,6 +473,96 @@ static void sprom_extract_r45(struct ssb
731 /* TODO - get remaining rev 4 stuff needed */
732 }
733
734 +static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
735 +{
736 + int i;
737 + u16 v;
738 +
739 + /* extract the MAC address */
740 + for (i = 0; i < 3; i++) {
741 + v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
742 + *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
743 + }
744 + SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
745 + SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
746 + SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
747 + SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
748 + SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);
749 + SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
750 + SSB_SPROM8_ANTAVAIL_A_SHIFT);
751 + SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
752 + SSB_SPROM8_ANTAVAIL_BG_SHIFT);
753 + SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
754 + SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
755 + SSB_SPROM8_ITSSI_BG_SHIFT);
756 + SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
757 + SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
758 + SSB_SPROM8_ITSSI_A_SHIFT);
759 + SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
760 + SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
761 + SSB_SPROM8_MAXP_AL_SHIFT);
762 + SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
763 + SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
764 + SSB_SPROM8_GPIOA_P1_SHIFT);
765 + SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
766 + SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
767 + SSB_SPROM8_GPIOB_P3_SHIFT);
768 + SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
769 + SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
770 + SSB_SPROM8_TRI5G_SHIFT);
771 + SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
772 + SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
773 + SSB_SPROM8_TRI5GH_SHIFT);
774 + SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);
775 + SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
776 + SSB_SPROM8_RXPO5G_SHIFT);
777 + SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
778 + SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
779 + SSB_SPROM8_RSSISMC2G_SHIFT);
780 + SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
781 + SSB_SPROM8_RSSISAV2G_SHIFT);
782 + SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
783 + SSB_SPROM8_BXA2G_SHIFT);
784 + SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
785 + SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
786 + SSB_SPROM8_RSSISMC5G_SHIFT);
787 + SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
788 + SSB_SPROM8_RSSISAV5G_SHIFT);
789 + SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
790 + SSB_SPROM8_BXA5G_SHIFT);
791 + SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);
792 + SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);
793 + SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);
794 + SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);
795 + SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);
796 + SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);
797 + SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);
798 + SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);
799 + SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);
800 + SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);
801 + SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);
802 + SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);
803 + SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);
804 + SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);
805 + SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);
806 + SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);
807 + SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
808 +
809 + /* Extract the antenna gain values. */
810 + SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
811 + SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
812 + SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
813 + SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
814 + SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
815 + SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
816 + SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
817 + SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
818 + memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
819 + sizeof(out->antenna_gain.ghz5));
820 +
821 + /* TODO - get remaining rev 8 stuff needed */
822 +}
823 +
824 static int sprom_extract(struct ssb_bus *bus, struct ssb_sprom *out,
825 const u16 *in, u16 size)
826 {
827 @@ -487,15 +583,26 @@ static int sprom_extract(struct ssb_bus
828 out->revision = 4;
829 sprom_extract_r45(out, in);
830 } else {
831 - if (out->revision == 0)
832 - goto unsupported;
833 - if (out->revision >= 1 && out->revision <= 3) {
834 + switch (out->revision) {
835 + case 1:
836 + case 2:
837 + case 3:
838 sprom_extract_r123(out, in);
839 - }
840 - if (out->revision == 4 || out->revision == 5)
841 + break;
842 + case 4:
843 + case 5:
844 sprom_extract_r45(out, in);
845 - if (out->revision > 5)
846 - goto unsupported;
847 + break;
848 + case 8:
849 + sprom_extract_r8(out, in);
850 + break;
851 + default:
852 + ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
853 + " revision %d detected. Will extract"
854 + " v1\n", out->revision);
855 + out->revision = 1;
856 + sprom_extract_r123(out, in);
857 + }
858 }
859
860 if (out->boardflags_lo == 0xFFFF)
861 @@ -504,11 +611,6 @@ static int sprom_extract(struct ssb_bus
862 out->boardflags_hi = 0; /* per specs */
863
864 return 0;
865 -unsupported:
866 - ssb_printk(KERN_WARNING PFX "Unsupported SPROM revision %d "
867 - "detected. Will extract v1\n", out->revision);
868 - sprom_extract_r123(out, in);
869 - return 0;
870 }
871
872 static int ssb_pci_sprom_get(struct ssb_bus *bus,
873 --- a/drivers/ssb/pcmcia.c
874 +++ b/drivers/ssb/pcmcia.c
875 @@ -583,7 +583,7 @@ static int ssb_pcmcia_sprom_write_all(st
876 ssb_printk(".");
877 err = ssb_pcmcia_sprom_write(bus, i, sprom[i]);
878 if (err) {
879 - ssb_printk("\n" KERN_NOTICE PFX
880 + ssb_printk(KERN_NOTICE PFX
881 "Failed to write to SPROM.\n");
882 failed = 1;
883 break;
884 @@ -591,7 +591,7 @@ static int ssb_pcmcia_sprom_write_all(st
885 }
886 err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEDIS);
887 if (err) {
888 - ssb_printk("\n" KERN_NOTICE PFX
889 + ssb_printk(KERN_NOTICE PFX
890 "Could not disable SPROM write access.\n");
891 failed = 1;
892 }
893 @@ -678,7 +678,8 @@ int ssb_pcmcia_get_invariants(struct ssb
894 sprom->board_rev = tuple.TupleData[1];
895 break;
896 case SSB_PCMCIA_CIS_PA:
897 - GOTO_ERROR_ON(tuple.TupleDataLen != 9,
898 + GOTO_ERROR_ON((tuple.TupleDataLen != 9) &&
899 + (tuple.TupleDataLen != 10),
900 "pa tpl size");
901 sprom->pa0b0 = tuple.TupleData[1] |
902 ((u16)tuple.TupleData[2] << 8);
903 @@ -718,7 +719,8 @@ int ssb_pcmcia_get_invariants(struct ssb
904 sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
905 break;
906 case SSB_PCMCIA_CIS_BFLAGS:
907 - GOTO_ERROR_ON(tuple.TupleDataLen != 3,
908 + GOTO_ERROR_ON((tuple.TupleDataLen != 3) &&
909 + (tuple.TupleDataLen != 5),
910 "bfl tpl size");
911 sprom->boardflags_lo = tuple.TupleData[1] |
912 ((u16)tuple.TupleData[2] << 8);
913 --- a/include/linux/ssb/ssb.h
914 +++ b/include/linux/ssb/ssb.h
915 @@ -27,24 +27,54 @@ struct ssb_sprom {
916 u8 et1mdcport; /* MDIO for enet1 */
917 u8 board_rev; /* Board revision number from SPROM. */
918 u8 country_code; /* Country Code */
919 - u8 ant_available_a; /* A-PHY antenna available bits (up to 4) */
920 - u8 ant_available_bg; /* B/G-PHY antenna available bits (up to 4) */
921 + u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
922 + u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
923 u16 pa0b0;
924 u16 pa0b1;
925 u16 pa0b2;
926 u16 pa1b0;
927 u16 pa1b1;
928 u16 pa1b2;
929 + u16 pa1lob0;
930 + u16 pa1lob1;
931 + u16 pa1lob2;
932 + u16 pa1hib0;
933 + u16 pa1hib1;
934 + u16 pa1hib2;
935 u8 gpio0; /* GPIO pin 0 */
936 u8 gpio1; /* GPIO pin 1 */
937 u8 gpio2; /* GPIO pin 2 */
938 u8 gpio3; /* GPIO pin 3 */
939 - u16 maxpwr_a; /* A-PHY Amplifier Max Power (in dBm Q5.2) */
940 - u16 maxpwr_bg; /* B/G-PHY Amplifier Max Power (in dBm Q5.2) */
941 + u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
942 + u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
943 + u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
944 + u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
945 u8 itssi_a; /* Idle TSSI Target for A-PHY */
946 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
947 - u16 boardflags_lo; /* Boardflags (low 16 bits) */
948 - u16 boardflags_hi; /* Boardflags (high 16 bits) */
949 + u8 tri2g; /* 2.4GHz TX isolation */
950 + u8 tri5gl; /* 5.2GHz TX isolation */
951 + u8 tri5g; /* 5.3GHz TX isolation */
952 + u8 tri5gh; /* 5.8GHz TX isolation */
953 + u8 rxpo2g; /* 2GHz RX power offset */
954 + u8 rxpo5g; /* 5GHz RX power offset */
955 + u8 rssisav2g; /* 2GHz RSSI params */
956 + u8 rssismc2g;
957 + u8 rssismf2g;
958 + u8 bxa2g; /* 2GHz BX arch */
959 + u8 rssisav5g; /* 5GHz RSSI params */
960 + u8 rssismc5g;
961 + u8 rssismf5g;
962 + u8 bxa5g; /* 5GHz BX arch */
963 + u16 cck2gpo; /* CCK power offset */
964 + u32 ofdm2gpo; /* 2.4GHz OFDM power offset */
965 + u32 ofdm5glpo; /* 5.2GHz OFDM power offset */
966 + u32 ofdm5gpo; /* 5.3GHz OFDM power offset */
967 + u32 ofdm5ghpo; /* 5.8GHz OFDM power offset */
968 + u16 boardflags_lo; /* Board flags (bits 0-15) */
969 + u16 boardflags_hi; /* Board flags (bits 16-31) */
970 + u16 boardflags2_lo; /* Board flags (bits 32-47) */
971 + u16 boardflags2_hi; /* Board flags (bits 48-63) */
972 + /* TODO store board flags in a single u64 */
973
974 /* Antenna gain values for up to 4 antennas
975 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
976 @@ -58,7 +88,7 @@ struct ssb_sprom {
977 } ghz5; /* 5GHz band */
978 } antenna_gain;
979
980 - /* TODO - add any parameters needed from rev 2, 3, or 4 SPROMs */
981 + /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
982 };
983
984 /* Information about the PCB the circuitry is soldered on. */
985 @@ -208,6 +238,7 @@ enum ssb_bustype {
986 SSB_BUSTYPE_SSB, /* This SSB bus is the system bus */
987 SSB_BUSTYPE_PCI, /* SSB is connected to PCI bus */
988 SSB_BUSTYPE_PCMCIA, /* SSB is connected to PCMCIA bus */
989 + SSB_BUSTYPE_SDIO, /* SSB is connected to SDIO bus */
990 };
991
992 /* board_vendor */
993 @@ -240,8 +271,12 @@ struct ssb_bus {
994
995 /* The core in the basic address register window. (PCI bus only) */
996 struct ssb_device *mapped_device;
997 - /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
998 - u8 mapped_pcmcia_seg;
999 + union {
1000 + /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
1001 + u8 mapped_pcmcia_seg;
1002 + /* Current SSB base address window for SDIO. */
1003 + u32 sdio_sbaddr;
1004 + };
1005 /* Lock for core and segment switching.
1006 * On PCMCIA-host busses this is used to protect the whole MMIO access. */
1007 spinlock_t bar_lock;
1008 @@ -252,6 +287,11 @@ struct ssb_bus {
1009 struct pci_dev *host_pci;
1010 /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
1011 struct pcmcia_device *host_pcmcia;
1012 + /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
1013 + struct sdio_func *host_sdio;
1014 +
1015 + /* See enum ssb_quirks */
1016 + unsigned int quirks;
1017
1018 #ifdef CONFIG_SSB_SPROM
1019 /* Mutex to protect the SPROM writing. */
1020 @@ -306,6 +346,11 @@ struct ssb_bus {
1021 #endif /* DEBUG */
1022 };
1023
1024 +enum ssb_quirks {
1025 + /* SDIO connected card requires performing a read after writing a 32-bit value */
1026 + SSB_QUIRK_SDIO_READ_AFTER_WRITE32 = (1 << 0),
1027 +};
1028 +
1029 /* The initialization-invariants. */
1030 struct ssb_init_invariants {
1031 /* Versioning information about the PCB. */
1032 --- a/include/linux/ssb/ssb_driver_chipcommon.h
1033 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
1034 @@ -181,6 +181,16 @@
1035 #define SSB_CHIPCO_PROG_WAITCNT 0x0124
1036 #define SSB_CHIPCO_FLASH_CFG 0x0128
1037 #define SSB_CHIPCO_FLASH_WAITCNT 0x012C
1038 +#define SSB_CHIPCO_CLKCTLST 0x01E0 /* Clock control and status (rev >= 20) */
1039 +#define SSB_CHIPCO_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
1040 +#define SSB_CHIPCO_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
1041 +#define SSB_CHIPCO_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
1042 +#define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
1043 +#define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
1044 +#define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
1045 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
1046 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
1047 +#define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
1048 #define SSB_CHIPCO_UART0_DATA 0x0300
1049 #define SSB_CHIPCO_UART0_IMR 0x0304
1050 #define SSB_CHIPCO_UART0_FCR 0x0308
1051 @@ -197,6 +207,196 @@
1052 #define SSB_CHIPCO_UART1_LSR 0x0414
1053 #define SSB_CHIPCO_UART1_MSR 0x0418
1054 #define SSB_CHIPCO_UART1_SCRATCH 0x041C
1055 +/* PMU registers (rev >= 20) */
1056 +#define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */
1057 +#define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
1058 +#define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16
1059 +#define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
1060 +#define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
1061 +#define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
1062 +#define SSB_CHIPCO_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */
1063 +#define SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT 2
1064 +#define SSB_CHIPCO_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */
1065 +#define SSB_CHIPCO_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */
1066 +#define SSB_CHIPCO_PMU_CAP 0x0604 /* PMU capabilities */
1067 +#define SSB_CHIPCO_PMU_CAP_REVISION 0x000000FF /* Revision mask */
1068 +#define SSB_CHIPCO_PMU_STAT 0x0608 /* PMU status */
1069 +#define SSB_CHIPCO_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
1070 +#define SSB_CHIPCO_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
1071 +#define SSB_CHIPCO_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
1072 +#define SSB_CHIPCO_PMU_STAT_HAVEHT 0x00000004 /* HT available */
1073 +#define SSB_CHIPCO_PMU_STAT_RESINIT 0x00000003 /* Res init */
1074 +#define SSB_CHIPCO_PMU_RES_STAT 0x060C /* PMU res status */
1075 +#define SSB_CHIPCO_PMU_RES_PEND 0x0610 /* PMU res pending */
1076 +#define SSB_CHIPCO_PMU_TIMER 0x0614 /* PMU timer */
1077 +#define SSB_CHIPCO_PMU_MINRES_MSK 0x0618 /* PMU min res mask */
1078 +#define SSB_CHIPCO_PMU_MAXRES_MSK 0x061C /* PMU max res mask */
1079 +#define SSB_CHIPCO_PMU_RES_TABSEL 0x0620 /* PMU res table sel */
1080 +#define SSB_CHIPCO_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */
1081 +#define SSB_CHIPCO_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */
1082 +#define SSB_CHIPCO_PMU_RES_TIMER 0x062C /* PMU res timer */
1083 +#define SSB_CHIPCO_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */
1084 +#define SSB_CHIPCO_PMU_WATCHDOG 0x0634 /* PMU watchdog */
1085 +#define SSB_CHIPCO_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
1086 +#define SSB_CHIPCO_PMU_RES_REQT 0x0644 /* PMU res req timer */
1087 +#define SSB_CHIPCO_PMU_RES_REQM 0x0648 /* PMU res req mask */
1088 +#define SSB_CHIPCO_CHIPCTL_ADDR 0x0650
1089 +#define SSB_CHIPCO_CHIPCTL_DATA 0x0654
1090 +#define SSB_CHIPCO_REGCTL_ADDR 0x0658
1091 +#define SSB_CHIPCO_REGCTL_DATA 0x065C
1092 +#define SSB_CHIPCO_PLLCTL_ADDR 0x0660
1093 +#define SSB_CHIPCO_PLLCTL_DATA 0x0664
1094 +
1095 +
1096 +
1097 +/** PMU PLL registers */
1098 +
1099 +/* PMU rev 0 PLL registers */
1100 +#define SSB_PMU0_PLLCTL0 0
1101 +#define SSB_PMU0_PLLCTL0_PDIV_MSK 0x00000001
1102 +#define SSB_PMU0_PLLCTL0_PDIV_FREQ 25000 /* kHz */
1103 +#define SSB_PMU0_PLLCTL1 1
1104 +#define SSB_PMU0_PLLCTL1_WILD_IMSK 0xF0000000 /* Wild int mask (low nibble) */
1105 +#define SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT 28
1106 +#define SSB_PMU0_PLLCTL1_WILD_FMSK 0x0FFFFF00 /* Wild frac mask */
1107 +#define SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT 8
1108 +#define SSB_PMU0_PLLCTL1_STOPMOD 0x00000040 /* Stop mod */
1109 +#define SSB_PMU0_PLLCTL2 2
1110 +#define SSB_PMU0_PLLCTL2_WILD_IMSKHI 0x0000000F /* Wild int mask (high nibble) */
1111 +#define SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT 0
1112 +
1113 +/* PMU rev 1 PLL registers */
1114 +#define SSB_PMU1_PLLCTL0 0
1115 +#define SSB_PMU1_PLLCTL0_P1DIV 0x00F00000 /* P1 div */
1116 +#define SSB_PMU1_PLLCTL0_P1DIV_SHIFT 20
1117 +#define SSB_PMU1_PLLCTL0_P2DIV 0x0F000000 /* P2 div */
1118 +#define SSB_PMU1_PLLCTL0_P2DIV_SHIFT 24
1119 +#define SSB_PMU1_PLLCTL1 1
1120 +#define SSB_PMU1_PLLCTL1_M1DIV 0x000000FF /* M1 div */
1121 +#define SSB_PMU1_PLLCTL1_M1DIV_SHIFT 0
1122 +#define SSB_PMU1_PLLCTL1_M2DIV 0x0000FF00 /* M2 div */
1123 +#define SSB_PMU1_PLLCTL1_M2DIV_SHIFT 8
1124 +#define SSB_PMU1_PLLCTL1_M3DIV 0x00FF0000 /* M3 div */
1125 +#define SSB_PMU1_PLLCTL1_M3DIV_SHIFT 16
1126 +#define SSB_PMU1_PLLCTL1_M4DIV 0xFF000000 /* M4 div */
1127 +#define SSB_PMU1_PLLCTL1_M4DIV_SHIFT 24
1128 +#define SSB_PMU1_PLLCTL2 2
1129 +#define SSB_PMU1_PLLCTL2_M5DIV 0x000000FF /* M5 div */
1130 +#define SSB_PMU1_PLLCTL2_M5DIV_SHIFT 0
1131 +#define SSB_PMU1_PLLCTL2_M6DIV 0x0000FF00 /* M6 div */
1132 +#define SSB_PMU1_PLLCTL2_M6DIV_SHIFT 8
1133 +#define SSB_PMU1_PLLCTL2_NDIVMODE 0x000E0000 /* NDIV mode */
1134 +#define SSB_PMU1_PLLCTL2_NDIVMODE_SHIFT 17
1135 +#define SSB_PMU1_PLLCTL2_NDIVINT 0x1FF00000 /* NDIV int */
1136 +#define SSB_PMU1_PLLCTL2_NDIVINT_SHIFT 20
1137 +#define SSB_PMU1_PLLCTL3 3
1138 +#define SSB_PMU1_PLLCTL3_NDIVFRAC 0x00FFFFFF /* NDIV frac */
1139 +#define SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT 0
1140 +#define SSB_PMU1_PLLCTL4 4
1141 +#define SSB_PMU1_PLLCTL5 5
1142 +#define SSB_PMU1_PLLCTL5_CLKDRV 0xFFFFFF00 /* clk drv */
1143 +#define SSB_PMU1_PLLCTL5_CLKDRV_SHIFT 8
1144 +
1145 +/* BCM4312 PLL resource numbers. */
1146 +#define SSB_PMURES_4312_SWITCHER_BURST 0
1147 +#define SSB_PMURES_4312_SWITCHER_PWM 1
1148 +#define SSB_PMURES_4312_PA_REF_LDO 2
1149 +#define SSB_PMURES_4312_CORE_LDO_BURST 3
1150 +#define SSB_PMURES_4312_CORE_LDO_PWM 4
1151 +#define SSB_PMURES_4312_RADIO_LDO 5
1152 +#define SSB_PMURES_4312_ILP_REQUEST 6
1153 +#define SSB_PMURES_4312_BG_FILTBYP 7
1154 +#define SSB_PMURES_4312_TX_FILTBYP 8
1155 +#define SSB_PMURES_4312_RX_FILTBYP 9
1156 +#define SSB_PMURES_4312_XTAL_PU 10
1157 +#define SSB_PMURES_4312_ALP_AVAIL 11
1158 +#define SSB_PMURES_4312_BB_PLL_FILTBYP 12
1159 +#define SSB_PMURES_4312_RF_PLL_FILTBYP 13
1160 +#define SSB_PMURES_4312_HT_AVAIL 14
1161 +
1162 +/* BCM4325 PLL resource numbers. */
1163 +#define SSB_PMURES_4325_BUCK_BOOST_BURST 0
1164 +#define SSB_PMURES_4325_CBUCK_BURST 1
1165 +#define SSB_PMURES_4325_CBUCK_PWM 2
1166 +#define SSB_PMURES_4325_CLDO_CBUCK_BURST 3
1167 +#define SSB_PMURES_4325_CLDO_CBUCK_PWM 4
1168 +#define SSB_PMURES_4325_BUCK_BOOST_PWM 5
1169 +#define SSB_PMURES_4325_ILP_REQUEST 6
1170 +#define SSB_PMURES_4325_ABUCK_BURST 7
1171 +#define SSB_PMURES_4325_ABUCK_PWM 8
1172 +#define SSB_PMURES_4325_LNLDO1_PU 9
1173 +#define SSB_PMURES_4325_LNLDO2_PU 10
1174 +#define SSB_PMURES_4325_LNLDO3_PU 11
1175 +#define SSB_PMURES_4325_LNLDO4_PU 12
1176 +#define SSB_PMURES_4325_XTAL_PU 13
1177 +#define SSB_PMURES_4325_ALP_AVAIL 14
1178 +#define SSB_PMURES_4325_RX_PWRSW_PU 15
1179 +#define SSB_PMURES_4325_TX_PWRSW_PU 16
1180 +#define SSB_PMURES_4325_RFPLL_PWRSW_PU 17
1181 +#define SSB_PMURES_4325_LOGEN_PWRSW_PU 18
1182 +#define SSB_PMURES_4325_AFE_PWRSW_PU 19
1183 +#define SSB_PMURES_4325_BBPLL_PWRSW_PU 20
1184 +#define SSB_PMURES_4325_HT_AVAIL 21
1185 +
1186 +/* BCM4328 PLL resource numbers. */
1187 +#define SSB_PMURES_4328_EXT_SWITCHER_PWM 0
1188 +#define SSB_PMURES_4328_BB_SWITCHER_PWM 1
1189 +#define SSB_PMURES_4328_BB_SWITCHER_BURST 2
1190 +#define SSB_PMURES_4328_BB_EXT_SWITCHER_BURST 3
1191 +#define SSB_PMURES_4328_ILP_REQUEST 4
1192 +#define SSB_PMURES_4328_RADIO_SWITCHER_PWM 5
1193 +#define SSB_PMURES_4328_RADIO_SWITCHER_BURST 6
1194 +#define SSB_PMURES_4328_ROM_SWITCH 7
1195 +#define SSB_PMURES_4328_PA_REF_LDO 8
1196 +#define SSB_PMURES_4328_RADIO_LDO 9
1197 +#define SSB_PMURES_4328_AFE_LDO 10
1198 +#define SSB_PMURES_4328_PLL_LDO 11
1199 +#define SSB_PMURES_4328_BG_FILTBYP 12
1200 +#define SSB_PMURES_4328_TX_FILTBYP 13
1201 +#define SSB_PMURES_4328_RX_FILTBYP 14
1202 +#define SSB_PMURES_4328_XTAL_PU 15
1203 +#define SSB_PMURES_4328_XTAL_EN 16
1204 +#define SSB_PMURES_4328_BB_PLL_FILTBYP 17
1205 +#define SSB_PMURES_4328_RF_PLL_FILTBYP 18
1206 +#define SSB_PMURES_4328_BB_PLL_PU 19
1207 +
1208 +/* BCM5354 PLL resource numbers. */
1209 +#define SSB_PMURES_5354_EXT_SWITCHER_PWM 0
1210 +#define SSB_PMURES_5354_BB_SWITCHER_PWM 1
1211 +#define SSB_PMURES_5354_BB_SWITCHER_BURST 2
1212 +#define SSB_PMURES_5354_BB_EXT_SWITCHER_BURST 3
1213 +#define SSB_PMURES_5354_ILP_REQUEST 4
1214 +#define SSB_PMURES_5354_RADIO_SWITCHER_PWM 5
1215 +#define SSB_PMURES_5354_RADIO_SWITCHER_BURST 6
1216 +#define SSB_PMURES_5354_ROM_SWITCH 7
1217 +#define SSB_PMURES_5354_PA_REF_LDO 8
1218 +#define SSB_PMURES_5354_RADIO_LDO 9
1219 +#define SSB_PMURES_5354_AFE_LDO 10
1220 +#define SSB_PMURES_5354_PLL_LDO 11
1221 +#define SSB_PMURES_5354_BG_FILTBYP 12
1222 +#define SSB_PMURES_5354_TX_FILTBYP 13
1223 +#define SSB_PMURES_5354_RX_FILTBYP 14
1224 +#define SSB_PMURES_5354_XTAL_PU 15
1225 +#define SSB_PMURES_5354_XTAL_EN 16
1226 +#define SSB_PMURES_5354_BB_PLL_FILTBYP 17
1227 +#define SSB_PMURES_5354_RF_PLL_FILTBYP 18
1228 +#define SSB_PMURES_5354_BB_PLL_PU 19
1229 +
1230 +
1231 +
1232 +/** Chip specific Chip-Status register contents. */
1233 +#define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
1234 +#define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
1235 +#define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
1236 +#define SSB_CHIPCO_CHST_4325_OTP_SEL 2 /* OTP is powered up, no SPROM */
1237 +#define SSB_CHIPCO_CHST_4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
1238 +#define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE 0x00000004
1239 +#define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE_SHIFT 2
1240 +#define SSB_CHIPCO_CHST_4325_RCAL_VALID 0x00000008
1241 +#define SSB_CHIPCO_CHST_4325_RCAL_VALID_SHIFT 3
1242 +#define SSB_CHIPCO_CHST_4325_RCAL_VALUE 0x000001F0
1243 +#define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
1244 +#define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
1245
1246
1247
1248 @@ -353,11 +553,20 @@
1249 struct ssb_device;
1250 struct ssb_serial_port;
1251
1252 +/* Data for the PMU, if available.
1253 + * Check availability with ((struct ssb_chipcommon)->capabilities & SSB_CHIPCO_CAP_PMU)
1254 + */
1255 +struct ssb_chipcommon_pmu {
1256 + u8 rev; /* PMU revision */
1257 + u32 crystalfreq; /* The active crystal frequency (in kHz) */
1258 +};
1259 +
1260 struct ssb_chipcommon {
1261 struct ssb_device *dev;
1262 u32 capabilities;
1263 /* Fast Powerup Delay constant */
1264 u16 fast_pwrup_delay;
1265 + struct ssb_chipcommon_pmu pmu;
1266 };
1267
1268 static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
1269 @@ -365,6 +574,17 @@ static inline bool ssb_chipco_available(
1270 return (cc->dev != NULL);
1271 }
1272
1273 +/* Register access */
1274 +#define chipco_read32(cc, offset) ssb_read32((cc)->dev, offset)
1275 +#define chipco_write32(cc, offset, val) ssb_write32((cc)->dev, offset, val)
1276 +
1277 +#define chipco_mask32(cc, offset, mask) \
1278 + chipco_write32(cc, offset, chipco_read32(cc, offset) & (mask))
1279 +#define chipco_set32(cc, offset, set) \
1280 + chipco_write32(cc, offset, chipco_read32(cc, offset) | (set))
1281 +#define chipco_maskset32(cc, offset, mask, set) \
1282 + chipco_write32(cc, offset, (chipco_read32(cc, offset) & (mask)) | (set))
1283 +
1284 extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
1285
1286 extern void ssb_chipco_suspend(struct ssb_chipcommon *cc);
1287 @@ -406,4 +626,18 @@ extern int ssb_chipco_serial_init(struct
1288 struct ssb_serial_port *ports);
1289 #endif /* CONFIG_SSB_SERIAL */
1290
1291 +/* PMU support */
1292 +extern void ssb_pmu_init(struct ssb_chipcommon *cc);
1293 +
1294 +enum ssb_pmu_ldo_volt_id {
1295 + LDO_PAREF = 0,
1296 + LDO_VOLT1,
1297 + LDO_VOLT2,
1298 + LDO_VOLT3,
1299 +};
1300 +
1301 +void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
1302 + enum ssb_pmu_ldo_volt_id id, u32 voltage);
1303 +void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
1304 +
1305 #endif /* LINUX_SSB_CHIPCO_H_ */
1306 --- a/include/linux/ssb/ssb_regs.h
1307 +++ b/include/linux/ssb/ssb_regs.h
1308 @@ -162,7 +162,7 @@
1309
1310 /* SPROM shadow area. If not otherwise noted, fields are
1311 * two bytes wide. Note that the SPROM can _only_ be read
1312 - * in two-byte quantinies.
1313 + * in two-byte quantities.
1314 */
1315 #define SSB_SPROMSIZE_WORDS 64
1316 #define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16))
1317 @@ -326,6 +326,94 @@
1318 #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
1319 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
1320
1321 +/* SPROM Revision 8 */
1322 +#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
1323 +#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
1324 +#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
1325 +#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
1326 +#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
1327 +#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
1328 +#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
1329 +#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
1330 +#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
1331 +#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
1332 +#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
1333 +#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
1334 +#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
1335 +#define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
1336 +#define SSB_SPROM8_AGAIN0_SHIFT 0
1337 +#define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
1338 +#define SSB_SPROM8_AGAIN1_SHIFT 8
1339 +#define SSB_SPROM8_AGAIN23 0x10A0
1340 +#define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
1341 +#define SSB_SPROM8_AGAIN2_SHIFT 0
1342 +#define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
1343 +#define SSB_SPROM8_AGAIN3_SHIFT 8
1344 +#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
1345 +#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
1346 +#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
1347 +#define SSB_SPROM8_GPIOA_P1_SHIFT 8
1348 +#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
1349 +#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
1350 +#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
1351 +#define SSB_SPROM8_GPIOB_P3_SHIFT 8
1352 +#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
1353 +#define SSB_SPROM8_RSSISMF2G 0x000F
1354 +#define SSB_SPROM8_RSSISMC2G 0x00F0
1355 +#define SSB_SPROM8_RSSISMC2G_SHIFT 4
1356 +#define SSB_SPROM8_RSSISAV2G 0x0700
1357 +#define SSB_SPROM8_RSSISAV2G_SHIFT 8
1358 +#define SSB_SPROM8_BXA2G 0x1800
1359 +#define SSB_SPROM8_BXA2G_SHIFT 11
1360 +#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
1361 +#define SSB_SPROM8_RSSISMF5G 0x000F
1362 +#define SSB_SPROM8_RSSISMC5G 0x00F0
1363 +#define SSB_SPROM8_RSSISMC5G_SHIFT 4
1364 +#define SSB_SPROM8_RSSISAV5G 0x0700
1365 +#define SSB_SPROM8_RSSISAV5G_SHIFT 8
1366 +#define SSB_SPROM8_BXA5G 0x1800
1367 +#define SSB_SPROM8_BXA5G_SHIFT 11
1368 +#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
1369 +#define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
1370 +#define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
1371 +#define SSB_SPROM8_TRI5G_SHIFT 8
1372 +#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
1373 +#define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
1374 +#define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
1375 +#define SSB_SPROM8_TRI5GH_SHIFT 8
1376 +#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
1377 +#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
1378 +#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
1379 +#define SSB_SPROM8_RXPO5G_SHIFT 8
1380 +#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
1381 +#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
1382 +#define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1383 +#define SSB_SPROM8_ITSSI_BG_SHIFT 8
1384 +#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
1385 +#define SSB_SPROM8_PA0B1 0x10C4
1386 +#define SSB_SPROM8_PA0B2 0x10C6
1387 +#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
1388 +#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
1389 +#define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
1390 +#define SSB_SPROM8_ITSSI_A_SHIFT 8
1391 +#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
1392 +#define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
1393 +#define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
1394 +#define SSB_SPROM8_MAXP_AL_SHIFT 8
1395 +#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
1396 +#define SSB_SPROM8_PA1B1 0x10CE
1397 +#define SSB_SPROM8_PA1B2 0x10D0
1398 +#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
1399 +#define SSB_SPROM8_PA1LOB1 0x10D4
1400 +#define SSB_SPROM8_PA1LOB2 0x10D6
1401 +#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
1402 +#define SSB_SPROM8_PA1HIB1 0x10DA
1403 +#define SSB_SPROM8_PA1HIB2 0x10DC
1404 +#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
1405 +#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
1406 +#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
1407 +#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
1408 +#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
1409
1410 /* Values for SSB_SPROM1_BINF_CCODE */
1411 enum {
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