target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h

   1 /*
   2  *  Atheros AR71xx built-in ethernet mac driver
   3  *
   4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Based on Atheros' AG7100 driver
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #ifndef __AG71XX_H
  15 #define __AG71XX_H
  16
  17 #include <linux/kernel.h>
  18 #include <linux/version.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/types.h>
  22 #include <linux/random.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/ethtool.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/phy.h>
  29 #include <linux/skbuff.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/workqueue.h>
  32
  33 #include <linux/bitops.h>
  34
  35 #include <asm/mach-ar71xx/ar71xx.h>
  36 #include <asm/mach-ar71xx/platform.h>
  37
  38 #define ETH_FCS_LEN     4
  39
  40 #define AG71XX_DRV_NAME         "ag71xx"
  41 #define AG71XX_DRV_VERSION      "0.5.25"
  42
  43 #define AG71XX_NAPI_WEIGHT      64
  44 #define AG71XX_OOM_REFILL       (1 + HZ/10)
  45
  46 #define AG71XX_INT_ERR  (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
  47 #define AG71XX_INT_TX   (AG71XX_INT_TX_PS)
  48 #define AG71XX_INT_RX   (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
  49
  50 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
  51 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
  52
  53 #define AG71XX_TX_FIFO_LEN      2048
  54 #define AG71XX_TX_MTU_LEN       1536
  55 #define AG71XX_RX_PKT_RESERVE   64
  56 #define AG71XX_RX_PKT_SIZE      \
  57         (AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN)
  58
  59 #define AG71XX_TX_RING_SIZE     64
  60 #define AG71XX_TX_THRES_STOP    (AG71XX_TX_RING_SIZE - 4)
  61 #define AG71XX_TX_THRES_WAKEUP  \
  62                 (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
  63
  64 #define AG71XX_RX_RING_SIZE     128
  65
  66 #ifdef CONFIG_AG71XX_DEBUG
  67 #define DBG(fmt, args...)       printk(KERN_DEBUG fmt, ## args)
  68 #else
  69 #define DBG(fmt, args...)       do {} while (0)
  70 #endif
  71
  72 #define ag71xx_assert(_cond)                                            \
  73 do {                                                                    \
  74         if (_cond)                                                      \
  75                 break;                                                  \
  76         printk("%s,%d: assertion failed\n", __FILE__, __LINE__);        \
  77         BUG();                                                          \
  78 } while (0)
  79
  80 struct ag71xx_desc {
  81         u32     data;
  82         u32     ctrl;
  83 #define DESC_EMPTY      BIT(31)
  84 #define DESC_MORE       BIT(24)
  85 #define DESC_PKTLEN_M   0xfff
  86         u32     next;
  87         u32     pad;
  88 } __attribute__((aligned(4)));
  89
  90 struct ag71xx_buf {
  91         struct sk_buff  *skb;
  92         struct ag71xx_desc *desc;
  93 };
  94
  95 struct ag71xx_ring {
  96         struct ag71xx_buf       *buf;
  97         u8                      *descs_cpu;
  98         dma_addr_t              descs_dma;
  99         unsigned int            desc_size;
 100         unsigned int            curr;
 101         unsigned int            dirty;
 102         unsigned int            size;
 103 };
 104
 105 struct ag71xx_mdio {
 106         struct mii_bus          *mii_bus;
 107         int                     mii_irq[PHY_MAX_ADDR];
 108         void __iomem            *mdio_base;
 109         struct ag71xx_mdio_platform_data *pdata;
 110 };
 111
 112 struct ag71xx_int_stats {
 113         unsigned long           rx_pr;
 114         unsigned long           rx_be;
 115         unsigned long           rx_of;
 116         unsigned long           tx_ps;
 117         unsigned long           tx_be;
 118         unsigned long           tx_ur;
 119         unsigned long           total;
 120 };
 121
 122 struct ag71xx_napi_stats {
 123         unsigned long           napi_calls;
 124         unsigned long           rx_count;
 125         unsigned long           rx_packets;
 126         unsigned long           rx_packets_max;
 127         unsigned long           tx_count;
 128         unsigned long           tx_packets;
 129         unsigned long           tx_packets_max;
 130
 131         unsigned long           rx[AG71XX_NAPI_WEIGHT + 1];
 132         unsigned long           tx[AG71XX_NAPI_WEIGHT + 1];
 133 };
 134
 135 struct ag71xx_debug {
 136         struct dentry           *debugfs_dir;
 137         struct dentry           *debugfs_int_stats;
 138         struct dentry           *debugfs_napi_stats;
 139
 140         struct ag71xx_int_stats int_stats;
 141         struct ag71xx_napi_stats napi_stats;
 142 };
 143
 144 struct ag71xx {
 145         void __iomem            *mac_base;
 146         void __iomem            *mii_ctrl;
 147
 148         spinlock_t              lock;
 149         struct platform_device  *pdev;
 150         struct net_device       *dev;
 151         struct napi_struct      napi;
 152         u32                     msg_enable;
 153
 154         struct ag71xx_ring      rx_ring;
 155         struct ag71xx_ring      tx_ring;
 156
 157         struct mii_bus          *mii_bus;
 158         struct phy_device       *phy_dev;
 159
 160         unsigned int            link;
 161         unsigned int            speed;
 162         int                     duplex;
 163
 164         struct work_struct      restart_work;
 165         struct timer_list       oom_timer;
 166
 167 #ifdef CONFIG_AG71XX_DEBUG_FS
 168         struct ag71xx_debug     debug;
 169 #endif
 170 };
 171
 172 extern struct ethtool_ops ag71xx_ethtool_ops;
 173
 174 int ag71xx_mdio_driver_init(void) __init;
 175 void ag71xx_mdio_driver_exit(void);
 176
 177 int ag71xx_phy_connect(struct ag71xx *ag);
 178 void ag71xx_phy_disconnect(struct ag71xx *ag);
 179 void ag71xx_phy_start(struct ag71xx *ag);
 180 void ag71xx_phy_stop(struct ag71xx *ag);
 181
 182 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
 183 {
 184         return ag->pdev->dev.platform_data;
 185 }
 186
 187 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
 188 {
 189         return ((desc->ctrl & DESC_EMPTY) != 0);
 190 }
 191
 192 static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 193 {
 194         return (desc->ctrl & DESC_PKTLEN_M);
 195 }
 196
 197 /* Register offsets */
 198 #define AG71XX_REG_MAC_CFG1     0x0000
 199 #define AG71XX_REG_MAC_CFG2     0x0004
 200 #define AG71XX_REG_MAC_IPG      0x0008
 201 #define AG71XX_REG_MAC_HDX      0x000c
 202 #define AG71XX_REG_MAC_MFL      0x0010
 203 #define AG71XX_REG_MII_CFG      0x0020
 204 #define AG71XX_REG_MII_CMD      0x0024
 205 #define AG71XX_REG_MII_ADDR     0x0028
 206 #define AG71XX_REG_MII_CTRL     0x002c
 207 #define AG71XX_REG_MII_STATUS   0x0030
 208 #define AG71XX_REG_MII_IND      0x0034
 209 #define AG71XX_REG_MAC_IFCTL    0x0038
 210 #define AG71XX_REG_MAC_ADDR1    0x0040
 211 #define AG71XX_REG_MAC_ADDR2    0x0044
 212 #define AG71XX_REG_FIFO_CFG0    0x0048
 213 #define AG71XX_REG_FIFO_CFG1    0x004c
 214 #define AG71XX_REG_FIFO_CFG2    0x0050
 215 #define AG71XX_REG_FIFO_CFG3    0x0054
 216 #define AG71XX_REG_FIFO_CFG4    0x0058
 217 #define AG71XX_REG_FIFO_CFG5    0x005c
 218 #define AG71XX_REG_FIFO_RAM0    0x0060
 219 #define AG71XX_REG_FIFO_RAM1    0x0064
 220 #define AG71XX_REG_FIFO_RAM2    0x0068
 221 #define AG71XX_REG_FIFO_RAM3    0x006c
 222 #define AG71XX_REG_FIFO_RAM4    0x0070
 223 #define AG71XX_REG_FIFO_RAM5    0x0074
 224 #define AG71XX_REG_FIFO_RAM6    0x0078
 225 #define AG71XX_REG_FIFO_RAM7    0x007c
 226
 227 #define AG71XX_REG_TX_CTRL      0x0180
 228 #define AG71XX_REG_TX_DESC      0x0184
 229 #define AG71XX_REG_TX_STATUS    0x0188
 230 #define AG71XX_REG_RX_CTRL      0x018c
 231 #define AG71XX_REG_RX_DESC      0x0190
 232 #define AG71XX_REG_RX_STATUS    0x0194
 233 #define AG71XX_REG_INT_ENABLE   0x0198
 234 #define AG71XX_REG_INT_STATUS   0x019c
 235
 236 #define MAC_CFG1_TXE            BIT(0)  /* Tx Enable */
 237 #define MAC_CFG1_STX            BIT(1)  /* Synchronize Tx Enable */
 238 #define MAC_CFG1_RXE            BIT(2)  /* Rx Enable */
 239 #define MAC_CFG1_SRX            BIT(3)  /* Synchronize Rx Enable */
 240 #define MAC_CFG1_TFC            BIT(4)  /* Tx Flow Control Enable */
 241 #define MAC_CFG1_RFC            BIT(5)  /* Rx Flow Control Enable */
 242 #define MAC_CFG1_LB             BIT(8)  /* Loopback mode */
 243 #define MAC_CFG1_SR             BIT(31) /* Soft Reset */
 244
 245 #define MAC_CFG2_FDX            BIT(0)
 246 #define MAC_CFG2_CRC_EN         BIT(1)
 247 #define MAC_CFG2_PAD_CRC_EN     BIT(2)
 248 #define MAC_CFG2_LEN_CHECK      BIT(4)
 249 #define MAC_CFG2_HUGE_FRAME_EN  BIT(5)
 250 #define MAC_CFG2_IF_1000        BIT(9)
 251 #define MAC_CFG2_IF_10_100      BIT(8)
 252
 253 #define FIFO_CFG0_WTM           BIT(0)  /* Watermark Module */
 254 #define FIFO_CFG0_RXS           BIT(1)  /* Rx System Module */
 255 #define FIFO_CFG0_RXF           BIT(2)  /* Rx Fabric Module */
 256 #define FIFO_CFG0_TXS           BIT(3)  /* Tx System Module */
 257 #define FIFO_CFG0_TXF           BIT(4)  /* Tx Fabric Module */
 258 #define FIFO_CFG0_ALL   (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
 259                         | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
 260
 261 #define FIFO_CFG0_ENABLE_SHIFT  8
 262
 263 #define FIFO_CFG4_DE            BIT(0)  /* Drop Event */
 264 #define FIFO_CFG4_DV            BIT(1)  /* RX_DV Event */
 265 #define FIFO_CFG4_FC            BIT(2)  /* False Carrier */
 266 #define FIFO_CFG4_CE            BIT(3)  /* Code Error */
 267 #define FIFO_CFG4_CR            BIT(4)  /* CRC error */
 268 #define FIFO_CFG4_LM            BIT(5)  /* Length Mismatch */
 269 #define FIFO_CFG4_LO            BIT(6)  /* Length out of range */
 270 #define FIFO_CFG4_OK            BIT(7)  /* Packet is OK */
 271 #define FIFO_CFG4_MC            BIT(8)  /* Multicast Packet */
 272 #define FIFO_CFG4_BC            BIT(9)  /* Broadcast Packet */
 273 #define FIFO_CFG4_DR            BIT(10) /* Dribble */
 274 #define FIFO_CFG4_LE            BIT(11) /* Long Event */
 275 #define FIFO_CFG4_CF            BIT(12) /* Control Frame */
 276 #define FIFO_CFG4_PF            BIT(13) /* Pause Frame */
 277 #define FIFO_CFG4_UO            BIT(14) /* Unsupported Opcode */
 278 #define FIFO_CFG4_VT            BIT(15) /* VLAN tag detected */
 279 #define FIFO_CFG4_FT            BIT(16) /* Frame Truncated */
 280 #define FIFO_CFG4_UC            BIT(17) /* Unicast Packet */
 281
 282 #define FIFO_CFG5_DE            BIT(0)  /* Drop Event */
 283 #define FIFO_CFG5_DV            BIT(1)  /* RX_DV Event */
 284 #define FIFO_CFG5_FC            BIT(2)  /* False Carrier */
 285 #define FIFO_CFG5_CE            BIT(3)  /* Code Error */
 286 #define FIFO_CFG5_LM            BIT(4)  /* Length Mismatch */
 287 #define FIFO_CFG5_LO            BIT(5)  /* Length Out of Range */
 288 #define FIFO_CFG5_OK            BIT(6)  /* Packet is OK */
 289 #define FIFO_CFG5_MC            BIT(7)  /* Multicast Packet */
 290 #define FIFO_CFG5_BC            BIT(8)  /* Broadcast Packet */
 291 #define FIFO_CFG5_DR            BIT(9)  /* Dribble */
 292 #define FIFO_CFG5_CF            BIT(10) /* Control Frame */
 293 #define FIFO_CFG5_PF            BIT(11) /* Pause Frame */
 294 #define FIFO_CFG5_UO            BIT(12) /* Unsupported Opcode */
 295 #define FIFO_CFG5_VT            BIT(13) /* VLAN tag detected */
 296 #define FIFO_CFG5_LE            BIT(14) /* Long Event */
 297 #define FIFO_CFG5_FT            BIT(15) /* Frame Truncated */
 298 #define FIFO_CFG5_16            BIT(16) /* unknown */
 299 #define FIFO_CFG5_17            BIT(17) /* unknown */
 300 #define FIFO_CFG5_SF            BIT(18) /* Short Frame */
 301 #define FIFO_CFG5_BM            BIT(19) /* Byte Mode */
 302
 303 #define AG71XX_INT_TX_PS        BIT(0)
 304 #define AG71XX_INT_TX_UR        BIT(1)
 305 #define AG71XX_INT_TX_BE        BIT(3)
 306 #define AG71XX_INT_RX_PR        BIT(4)
 307 #define AG71XX_INT_RX_OF        BIT(6)
 308 #define AG71XX_INT_RX_BE        BIT(7)
 309
 310 #define MAC_IFCTL_SPEED         BIT(16)
 311
 312 #define MII_CFG_CLK_DIV_4       0
 313 #define MII_CFG_CLK_DIV_6       2
 314 #define MII_CFG_CLK_DIV_8       3
 315 #define MII_CFG_CLK_DIV_10      4
 316 #define MII_CFG_CLK_DIV_14      5
 317 #define MII_CFG_CLK_DIV_20      6
 318 #define MII_CFG_CLK_DIV_28      7
 319 #define MII_CFG_RESET           BIT(31)
 320
 321 #define MII_CMD_WRITE           0x0
 322 #define MII_CMD_READ            0x1
 323 #define MII_ADDR_SHIFT          8
 324 #define MII_IND_BUSY            BIT(0)
 325 #define MII_IND_INVALID         BIT(2)
 326
 327 #define TX_CTRL_TXE             BIT(0)  /* Tx Enable */
 328
 329 #define TX_STATUS_PS            BIT(0)  /* Packet Sent */
 330 #define TX_STATUS_UR            BIT(1)  /* Tx Underrun */
 331 #define TX_STATUS_BE            BIT(3)  /* Bus Error */
 332
 333 #define RX_CTRL_RXE             BIT(0)  /* Rx Enable */
 334
 335 #define RX_STATUS_PR            BIT(0)  /* Packet Received */
 336 #define RX_STATUS_OF            BIT(2)  /* Rx Overflow */
 337 #define RX_STATUS_BE            BIT(3)  /* Bus Error */
 338
 339 #define MII_CTRL_IF_MASK        3
 340 #define MII_CTRL_SPEED_SHIFT    4
 341 #define MII_CTRL_SPEED_MASK     3
 342 #define MII_CTRL_SPEED_10       0
 343 #define MII_CTRL_SPEED_100      1
 344 #define MII_CTRL_SPEED_1000     2
 345
 346 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
 347 {
 348         void __iomem *r;
 349
 350         switch (reg) {
 351         case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
 352         case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
 353                 r = ag->mac_base + reg;
 354                 __raw_writel(value, r);
 355
 356                 /* flush write */
 357                 (void) __raw_readl(r);
 358                 break;
 359         default:
 360                 BUG();
 361         }
 362 }
 363
 364 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
 365 {
 366         void __iomem *r;
 367         u32 ret;
 368
 369         switch (reg) {
 370         case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
 371         case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
 372                 r = ag->mac_base + reg;
 373                 ret = __raw_readl(r);
 374                 break;
 375         default:
 376                 BUG();
 377         }
 378
 379         return ret;
 380 }
 381
 382 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
 383 {
 384         void __iomem *r;
 385
 386         switch (reg) {
 387         case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
 388         case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
 389                 r = ag->mac_base + reg;
 390                 __raw_writel(__raw_readl(r) | mask, r);
 391
 392                 /* flush write */
 393                 (void)__raw_readl(r);
 394                 break;
 395         default:
 396                 BUG();
 397         }
 398 }
 399
 400 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
 401 {
 402         void __iomem *r;
 403
 404         switch (reg) {
 405         case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
 406         case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
 407                 r = ag->mac_base + reg;
 408                 __raw_writel(__raw_readl(r) & ~mask, r);
 409
 410                 /* flush write */
 411                 (void) __raw_readl(r);
 412                 break;
 413         default:
 414                 BUG();
 415         }
 416 }
 417
 418 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
 419 {
 420         ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
 421 }
 422
 423 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
 424 {
 425         ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
 426 }
 427
 428 static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
 429 {
 430         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 431
 432         if (pdata->is_ar724x)
 433                 return;
 434
 435         __raw_writel(value, ag->mii_ctrl);
 436
 437         /* flush write */
 438         __raw_readl(ag->mii_ctrl);
 439 }
 440
 441 static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
 442 {
 443         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 444
 445         if (pdata->is_ar724x)
 446                 return 0xffffffff;
 447
 448         return __raw_readl(ag->mii_ctrl);
 449 }
 450
 451 static void inline ag71xx_mii_ctrl_set_if(struct ag71xx *ag,
 452                                           unsigned int mii_if)
 453 {
 454         u32 t;
 455
 456         t = ag71xx_mii_ctrl_rr(ag);
 457         t &= ~(MII_CTRL_IF_MASK);
 458         t |= (mii_if & MII_CTRL_IF_MASK);
 459         ag71xx_mii_ctrl_wr(ag, t);
 460 }
 461
 462 static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
 463                                              unsigned int speed)
 464 {
 465         u32 t;
 466
 467         t = ag71xx_mii_ctrl_rr(ag);
 468         t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
 469         t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
 470         ag71xx_mii_ctrl_wr(ag, t);
 471 }
 472
 473 #ifdef CONFIG_AG71XX_AR8216_SUPPORT
 474 void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
 475 int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
 476 #else
 477 static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
 478                                            struct sk_buff *skb)
 479 {
 480 }
 481
 482 static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
 483                                               struct sk_buff *skb)
 484 {
 485         return 0;
 486 }
 487 #endif
 488
 489 #ifdef CONFIG_AG71XX_DEBUG_FS
 490 int ag71xx_debugfs_root_init(void);
 491 void ag71xx_debugfs_root_exit(void);
 492 int ag71xx_debugfs_init(struct ag71xx *ag);
 493 void ag71xx_debugfs_exit(struct ag71xx *ag);
 494 void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status);
 495 void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx);
 496 #else
 497 static inline int ag71xx_debugfs_root_init(void) { return 0; }
 498 static inline void ag71xx_debugfs_root_exit(void) {}
 499 static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }
 500 static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}
 501 static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag,
 502                                                    u32 status) {}
 503 static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag,
 504                                                     int rx, int tx) {}
 505 #endif /* CONFIG_AG71XX_DEBUG_FS */
 506
 507 #endif /* _AG71XX_H */