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[openwrt.git] / package / rt2x00 / src / rt61pci.c
1 /*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
27 /*
28 * Set enviroment defines for rt2x00.h
29 */
30 #define DRV_NAME "rt61pci"
31
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/version.h>
35 #include <linux/init.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/delay.h>
39 #include <linux/etherdevice.h>
40 #include <linux/eeprom_93cx6.h>
41
42 #include <asm/io.h>
43
44 #include "rt2x00.h"
45 #include "rt2x00lib.h"
46 #include "rt2x00pci.h"
47 #include "rt61pci.h"
48
49 /*
50 * Register access.
51 * BBP and RF register require indirect register access,
52 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
53 * These indirect registers work with busy bits,
54 * and we will try maximal REGISTER_BUSY_COUNT times to access
55 * the register while taking a REGISTER_BUSY_DELAY us delay
56 * between each attampt. When the busy bit is still set at that time,
57 * the access attempt is considered to have failed,
58 * and we will print an error.
59 */
60 static u32 rt61pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
61 {
62 u32 reg;
63 unsigned int i;
64
65 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
66 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
67 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
68 break;
69 udelay(REGISTER_BUSY_DELAY);
70 }
71
72 return reg;
73 }
74
75 static void rt61pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
76 const u8 reg_id, const u8 value)
77 {
78 u32 reg;
79
80 /*
81 * Wait until the BBP becomes ready.
82 */
83 reg = rt61pci_bbp_check(rt2x00dev);
84 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
85 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
86 return;
87 }
88
89 /*
90 * Write the data into the BBP.
91 */
92 reg = 0;
93 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
94 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, reg_id);
95 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
96 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
97
98 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
99 }
100
101 static void rt61pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
102 const u8 reg_id, u8 *value)
103 {
104 u32 reg;
105
106 /*
107 * Wait until the BBP becomes ready.
108 */
109 reg = rt61pci_bbp_check(rt2x00dev);
110 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
111 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
112 return;
113 }
114
115 /*
116 * Write the request into the BBP.
117 */
118 reg =0;
119 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, reg_id);
120 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
121 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
122
123 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
124
125 /*
126 * Wait until the BBP becomes ready.
127 */
128 reg = rt61pci_bbp_check(rt2x00dev);
129 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
130 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
131 *value = 0xff;
132 return;
133 }
134
135 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
136 }
137
138 static void rt61pci_rf_write(const struct rt2x00_dev *rt2x00dev,
139 const u32 value)
140 {
141 u32 reg;
142 unsigned int i;
143
144 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
145 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
146 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
147 goto rf_write;
148 udelay(REGISTER_BUSY_DELAY);
149 }
150
151 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
152 return;
153
154 rf_write:
155 reg = 0;
156 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
157 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
158 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
159 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
160
161 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
162 }
163
164 static void rt61pci_mcu_request(const struct rt2x00_dev *rt2x00dev,
165 const u8 command, const u8 token, const u8 arg0, const u8 arg1)
166 {
167 u32 reg;
168
169 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
170
171 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
172 ERROR(rt2x00dev, "mcu request error. "
173 "Request 0x%02x failed for token 0x%02x.\n",
174 command, token);
175 return;
176 }
177
178 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
179 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
180 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
181 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
182 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
183
184 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
185 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
186 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
187 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
188 }
189
190 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
191 {
192 struct rt2x00_dev *rt2x00dev = eeprom->data;
193 u32 reg;
194
195 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
196
197 eeprom->reg_data_in = !!rt2x00_get_field32(reg,
198 E2PROM_CSR_DATA_IN);
199 eeprom->reg_data_out = !!rt2x00_get_field32(reg,
200 E2PROM_CSR_DATA_OUT);
201 eeprom->reg_data_clock = !!rt2x00_get_field32(reg,
202 E2PROM_CSR_DATA_CLOCK);
203 eeprom->reg_chip_select = !!rt2x00_get_field32(reg,
204 E2PROM_CSR_CHIP_SELECT);
205 }
206
207 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
208 {
209 struct rt2x00_dev *rt2x00dev = eeprom->data;
210 u32 reg = 0;
211
212 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN,
213 !!eeprom->reg_data_in);
214 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT,
215 !!eeprom->reg_data_out);
216 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
217 !!eeprom->reg_data_clock);
218 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
219 !!eeprom->reg_chip_select);
220
221 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
222 }
223
224 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
225 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
226
227 static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
228 const unsigned long word, void *data)
229 {
230 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
231 }
232
233 static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
234 const unsigned long word, void *data)
235 {
236 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), *((u32*)data));
237 }
238
239 static void rt61pci_read_eeprom(struct rt2x00_dev *rt2x00dev,
240 const unsigned long word, void *data)
241 {
242 rt2x00_eeprom_read(rt2x00dev, word, data);
243 }
244
245 static void rt61pci_write_eeprom(struct rt2x00_dev *rt2x00dev,
246 const unsigned long word, void *data)
247 {
248 rt2x00_eeprom_write(rt2x00dev, word, *((u16*)data));
249 }
250
251 static void rt61pci_read_bbp(struct rt2x00_dev *rt2x00dev,
252 const unsigned long word, void *data)
253 {
254 rt61pci_bbp_read(rt2x00dev, word, data);
255 }
256
257 static void rt61pci_write_bbp(struct rt2x00_dev *rt2x00dev,
258 const unsigned long word, void *data)
259 {
260 rt61pci_bbp_write(rt2x00dev, word, *((u8*)data));
261 }
262
263 static const struct rt2x00debug rt61pci_rt2x00debug = {
264 .owner = THIS_MODULE,
265 .reg_csr = {
266 .read = rt61pci_read_csr,
267 .write = rt61pci_write_csr,
268 .word_size = sizeof(u32),
269 .word_count = CSR_REG_SIZE / sizeof(u32),
270 },
271 .reg_eeprom = {
272 .read = rt61pci_read_eeprom,
273 .write = rt61pci_write_eeprom,
274 .word_size = sizeof(u16),
275 .word_count = EEPROM_SIZE / sizeof(u16),
276 },
277 .reg_bbp = {
278 .read = rt61pci_read_bbp,
279 .write = rt61pci_write_bbp,
280 .word_size = sizeof(u8),
281 .word_count = BBP_SIZE / sizeof(u8),
282 },
283 };
284 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
285
286 #ifdef CONFIG_RT61PCI_RFKILL
287 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
288 {
289 u32 reg;
290
291 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
292 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);;
293 }
294 #endif /* CONFIG_RT2400PCI_RFKILL */
295
296 /*
297 * Configuration handlers.
298 */
299 static void rt61pci_config_bssid(struct rt2x00_dev *rt2x00dev, u8 *bssid)
300 {
301 u32 reg[2];
302
303 memset(&reg, 0, sizeof(reg));
304 memcpy(&reg, bssid, ETH_ALEN);
305
306 rt2x00_set_field32(&reg[1], MAC_CSR5_BSS_ID_MASK, 3);
307
308 /*
309 * The BSSID is passed to us as an array of bytes,
310 * that array is little endian, so no need for byte ordering.
311 */
312 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, &reg, sizeof(reg));
313 }
314
315 static void rt61pci_config_promisc(struct rt2x00_dev *rt2x00dev,
316 const int promisc)
317 {
318 u32 reg;
319
320 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
321 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME, !promisc);
322 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
323 }
324
325 static void rt61pci_config_type(struct rt2x00_dev *rt2x00dev,
326 const int type)
327 {
328 u32 reg;
329
330 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
331
332 /*
333 * Apply hardware packet filter.
334 */
335 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
336
337 if (!is_monitor_present(&rt2x00dev->interface) &&
338 (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_STA))
339 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS, 1);
340 else
341 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS, 0);
342
343 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC, 1);
344 if (is_monitor_present(&rt2x00dev->interface)) {
345 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL, 0);
346 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL, 0);
347 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 0);
348 } else {
349 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL, 1);
350 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL, 1);
351 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
352 }
353
354 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST, 0);
355 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BORADCAST, 0);
356
357 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
358
359 /*
360 * Enable synchronisation.
361 */
362 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
363 if (is_interface_present(&rt2x00dev->interface)) {
364 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
365 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
366 }
367
368 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
369 if (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_AP)
370 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 2);
371 else if (type == IEEE80211_IF_TYPE_STA)
372 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 1);
373 else if (is_monitor_present(&rt2x00dev->interface) &&
374 !is_interface_present(&rt2x00dev->interface))
375 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
376
377 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
378 }
379
380 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
381 const int value, const int channel, const int txpower)
382 {
383 u8 reg = 0;
384 u32 rf1 = 0;
385 u32 rf2 = value;
386 u32 rf3 = 0;
387 u32 rf4 = 0;
388
389 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags) || channel <= 14)
390 rf1 = 0x00002ccc;
391 else if (channel == 36 ||
392 (channel >= 100 && channel <= 116) ||
393 channel >= 157)
394 rf1 = 0x00002cd4;
395 else
396 rf1 = 0x00002cd0;
397
398 if (channel <= 14) {
399 rf3 = 0x00068455;
400 } else if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
401 if (channel >= 36 && channel <= 48)
402 rf3 = 0x0009be55;
403 else if (channel >= 52 && channel <= 64)
404 rf3 = 0x0009ae55;
405 else if (channel >= 100 && channel <= 112)
406 rf3 = 0x000bae55;
407 else
408 rf3 = 0x000bbe55;
409 } else {
410 switch (channel) {
411 case 36:
412 case 40:
413 case 44:
414 rf3 = 0x00098455;
415 break;
416 case 48:
417 rf3 = 0x00098655;
418 break;
419 case 52:
420 rf3 = 0x00098855;
421 break;
422 case 56:
423 rf3 = 0x00098c55;
424
425 case 60:
426 rf3 = 0x00098e55;
427 break;
428 case 64:
429 rf3 = 0x00099255;
430 break;
431 case 100:
432 case 104:
433 case 108:
434 rf3 = 0x000b9855;
435 break;
436 case 112:
437 case 116:
438 case 120:
439 case 124:
440 rf3 = 0x000b9a55;
441 break;
442 case 128:
443 case 132:
444 rf3 = 0x000b9c55;
445 break;
446 case 136:
447 case 140:
448 rf3 = 0x000b9e55;
449 break;
450 case 149:
451 case 153:
452 case 157:
453 case 161:
454 case 165:
455 rf3 = 0x000ba255;
456 break;
457 }
458 }
459
460 if (channel < 14) {
461 if (channel & 1)
462 rf4 = 0x000ffa0b;
463 else
464 rf4 = 0x000ffa1f;
465 } else if (channel == 14) {
466 rf4 = 0x000ffa13;
467 } else if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
468 switch (channel) {
469 case 36:
470 case 56:
471 case 116:
472 case 136:
473 rf4 = 0x000ffa23;
474 break;
475 case 40:
476 case 60:
477 case 100:
478 case 120:
479 case 140:
480 rf4 = 0x000ffa03;
481 break;
482 case 44:
483 case 64:
484 case 104:
485 case 124:
486 rf4 = 0x000ffa0b;
487 break;
488 case 48:
489 case 108:
490 case 128:
491 rf4 = 0x000ffa13;
492 break;
493 case 52:
494 case 112:
495 case 132:
496 rf4 = 0x000ffa1b;
497 break;
498 case 149:
499 rf4 = 0x000ffa1f;
500 break;
501 case 153:
502 rf4 = 0x000ffa27;
503 break;
504 case 157:
505 rf4 = 0x000ffa07;
506 break;
507 case 161:
508 rf4 = 0x000ffa0f;
509 break;
510 case 165:
511 rf4 = 0x000ffa17;
512 break;
513 }
514 } else {
515 switch (channel) {
516 case 36:
517 case 40:
518 case 60:
519 case 140:
520 case 100:
521 case 104:
522 case 108:
523 case 112:
524 case 116:
525 case 120:
526 rf4 = 0x000c0a03;
527 break;
528 case 44:
529 case 64:
530 case 124:
531 case 149:
532 rf4 = 0x000c0a1b;
533 break;
534 case 48:
535 case 128:
536 case 153:
537 rf4 = 0x000c0a0b;
538 break;
539 case 52:
540 case 132:
541 rf4 = 0x000c0a23;
542 break;
543 case 56:
544 case 136:
545 rf4 = 0x000c0a13;
546 break;
547 case 157:
548 case 161:
549 case 165:
550 rf4 = 0x000c0a17;
551 break;
552 }
553 }
554
555 /*
556 * Set TXpower.
557 */
558 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
559
560 /*
561 * Set Frequency offset.
562 */
563 rt2x00_set_field32(&rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
564
565 rt61pci_rf_write(rt2x00dev, rf1);
566 rt61pci_rf_write(rt2x00dev, rf2);
567 rt61pci_rf_write(rt2x00dev, rf3 & ~0x00000004);
568 rt61pci_rf_write(rt2x00dev, rf4);
569
570 udelay(200);
571
572 rt61pci_rf_write(rt2x00dev, rf1);
573 rt61pci_rf_write(rt2x00dev, rf2);
574 rt61pci_rf_write(rt2x00dev, rf3 | 0x00000004);
575 rt61pci_rf_write(rt2x00dev, rf4);
576
577 udelay(200);
578
579 rt61pci_rf_write(rt2x00dev, rf1);
580 rt61pci_rf_write(rt2x00dev, rf2);
581 rt61pci_rf_write(rt2x00dev, rf3 & ~0x00000004);
582 rt61pci_rf_write(rt2x00dev, rf4);
583
584 rt61pci_bbp_read(rt2x00dev, 3, &reg);
585 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
586 rt2x00_rf(&rt2x00dev->chip, RF2527))
587 reg &= ~0x01;
588 else
589 reg |= 0x01;
590 rt61pci_bbp_write(rt2x00dev, 3, reg);
591
592 msleep(1);
593
594 /*
595 * Update rf fields
596 */
597 rt2x00dev->rf1 = rf1;
598 rt2x00dev->rf2 = rf2;
599 rt2x00dev->rf3 = rf3;
600 rt2x00dev->rf4 = rf4;
601 rt2x00dev->tx_power = txpower;
602 }
603
604 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
605 const int txpower)
606 {
607 rt2x00_set_field32(&rt2x00dev->rf3, RF3_TXPOWER,
608 TXPOWER_TO_DEV(txpower));
609
610 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf1);
611 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf2);
612 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf3 & ~0x00000004);
613 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf4);
614
615 udelay(200);
616
617 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf1);
618 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf2);
619 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf3 | 0x00000004);
620 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf4);
621
622 udelay(200);
623
624 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf1);
625 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf2);
626 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf3 & ~0x00000004);
627 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf4);
628 }
629
630 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
631 const int antenna_tx, const int antenna_rx)
632 {
633 u32 reg;
634 u8 r3;
635 u8 r4;
636 u8 r77;
637
638 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
639
640 if (rt2x00dev->curr_hwmode == HWMODE_A) {
641 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
642 rt61pci_bbp_write(rt2x00dev, 17, 0x38);
643 rt61pci_bbp_write(rt2x00dev, 96, 0x78);
644 rt61pci_bbp_write(rt2x00dev, 104, 0x48);
645 rt61pci_bbp_write(rt2x00dev, 75, 0x80);
646 rt61pci_bbp_write(rt2x00dev, 86, 0x80);
647 rt61pci_bbp_write(rt2x00dev, 88, 0x80);
648 } else {
649 rt61pci_bbp_write(rt2x00dev, 17, 0x28);
650 rt61pci_bbp_write(rt2x00dev, 96, 0x58);
651 rt61pci_bbp_write(rt2x00dev, 104, 0x38);
652 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
653 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
654 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
655 }
656 rt61pci_bbp_write(rt2x00dev, 35, 0x60);
657 rt61pci_bbp_write(rt2x00dev, 97, 0x58);
658 rt61pci_bbp_write(rt2x00dev, 98, 0x58);
659
660 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 0);
661 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 1);
662 } else {
663 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
664 rt61pci_bbp_write(rt2x00dev, 17, 0x30);
665 rt61pci_bbp_write(rt2x00dev, 96, 0x68);
666 rt61pci_bbp_write(rt2x00dev, 104, 0x3c);
667 rt61pci_bbp_write(rt2x00dev, 75, 0x80);
668 rt61pci_bbp_write(rt2x00dev, 86, 0x80);
669 rt61pci_bbp_write(rt2x00dev, 88, 0x80);
670 } else {
671 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
672 rt61pci_bbp_write(rt2x00dev, 96, 0x48);
673 rt61pci_bbp_write(rt2x00dev, 104, 0x2c);
674 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
675 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
676 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
677 }
678 rt61pci_bbp_write(rt2x00dev, 35, 0x50);
679 rt61pci_bbp_write(rt2x00dev, 97, 0x48);
680 rt61pci_bbp_write(rt2x00dev, 98, 0x48);
681
682 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 1);
683 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 0);
684 }
685
686 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
687
688 rt61pci_bbp_read(rt2x00dev, 3, &r3);
689 rt61pci_bbp_read(rt2x00dev, 4, &r4);
690 rt61pci_bbp_read(rt2x00dev, 77, &r77);
691
692 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
693 rt2x00_rf(&rt2x00dev->chip, RF2527))
694 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
695
696 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
697 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
698 if (antenna_rx == ANTENNA_DIVERSITY) {
699 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
700 if (rt2x00dev->curr_hwmode != HWMODE_A)
701 rt2x00_set_field8(&r4, BBP_R4_RX_BG_MODE, 1);
702 } else if (antenna_rx == ANTENNA_A) {
703 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
704 if (rt2x00dev->curr_hwmode == HWMODE_A)
705 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
706 else
707 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
708 rt61pci_bbp_write(rt2x00dev, 77, r77);
709 } else if (antenna_rx == ANTENNA_B) {
710 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
711 if (rt2x00dev->curr_hwmode == HWMODE_A)
712 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
713 else
714 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
715 rt61pci_bbp_write(rt2x00dev, 77, r77);
716 }
717 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527) ||
718 (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
719 test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))) {
720 if (antenna_rx == ANTENNA_DIVERSITY) {
721 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
722 rt2x00_set_field8(&r4, BBP_R4_RX_BG_MODE, 1);
723 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
724 test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
725 } else if (antenna_rx == ANTENNA_A) {
726 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
727 rt2x00_set_field8(&r4, BBP_R4_RX_BG_MODE, 1);
728 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
729 test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
730 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
731 rt61pci_bbp_write(rt2x00dev, 77, r77);
732 } else if (antenna_rx == ANTENNA_B) {
733 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
734 rt2x00_set_field8(&r4, BBP_R4_RX_BG_MODE, 1);
735 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
736 test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
737 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
738 rt61pci_bbp_write(rt2x00dev, 77, r77);
739 }
740 }
741
742 /*
743 * TODO: RF2529 with another antenna value then 2 are ignored.
744 * The legacy driver is unclear whether in those cases there is
745 * a possibility to switch antenna.
746 */
747
748 rt61pci_bbp_write(rt2x00dev, 3, r3);
749 rt61pci_bbp_write(rt2x00dev, 4, r4);
750 }
751
752 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
753 const int short_slot_time, const int beacon_int)
754 {
755 u32 reg;
756
757 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
758 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME,
759 short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
760 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
761
762 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
763 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, SIFS);
764 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
765 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, EIFS);
766 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
767
768 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
769 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
770 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
771
772 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
773 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
774 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
775
776 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
777 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, beacon_int * 16);
778 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
779 }
780
781 static void rt61pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
782 {
783 struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
784 u32 reg;
785 u32 value;
786 u32 preamble;
787
788 preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE)
789 ? SHORT_PREAMBLE : PREAMBLE;
790
791 /*
792 * Extract the allowed ratemask from the device specific rate value,
793 * We need to set TXRX_CSR5 to the basic rate mask so we need to mask
794 * off the non-basic rates.
795 */
796 reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATE;
797
798 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, reg);
799
800 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
801 value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
802 SHORT_DIFS : DIFS) +
803 PLCP + preamble + get_duration(ACK_SIZE, 10);
804 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, value);
805 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
806
807 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
808 if (preamble == SHORT_PREAMBLE)
809 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 1);
810 else
811 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 0);
812 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
813 }
814
815 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
816 const int phymode)
817 {
818 struct ieee80211_hw_mode *mode;
819 struct ieee80211_rate *rate;
820
821 if (phymode == MODE_IEEE80211A)
822 rt2x00dev->curr_hwmode = HWMODE_A;
823 else if (phymode == MODE_IEEE80211B)
824 rt2x00dev->curr_hwmode = HWMODE_B;
825 else
826 rt2x00dev->curr_hwmode = HWMODE_G;
827
828 mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
829 rate = &mode->rates[mode->num_rates - 1];
830
831 rt61pci_config_rate(rt2x00dev, rate->val2);
832 }
833
834 static void rt61pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, u8 *addr)
835 {
836 u32 reg[2];
837
838 memset(&reg, 0, sizeof(reg));
839 memcpy(&reg, addr, ETH_ALEN);
840
841 rt2x00_set_field32(&reg[1], MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
842
843 /*
844 * The MAC address is passed to us as an array of bytes,
845 * that array is little endian, so no need for byte ordering.
846 */
847 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, &reg, sizeof(reg));
848 }
849
850 /*
851 * LED functions.
852 */
853 static void rt61pci_enable_led(struct rt2x00_dev *rt2x00dev)
854 {
855 u32 reg;
856 u16 led_reg;
857 u8 arg0;
858 u8 arg1;
859
860 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
861 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
862 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
863 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
864
865 led_reg = rt2x00dev->led_reg;
866 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 1);
867 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A)
868 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 1);
869 else
870 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 1);
871
872 arg0 = led_reg & 0xff;
873 arg1 = (led_reg >> 8) & 0xff;
874
875 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
876 }
877
878 static void rt61pci_disable_led(struct rt2x00_dev *rt2x00dev)
879 {
880 u16 led_reg;
881 u8 arg0;
882 u8 arg1;
883
884 led_reg = rt2x00dev->led_reg;
885 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 0);
886 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
887 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
888
889 arg0 = led_reg & 0xff;
890 arg1 = (led_reg >> 8) & 0xff;
891
892 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
893 }
894
895 static void rt61pci_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
896 {
897 u8 led;
898
899 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
900 return;
901
902 /*
903 * Led handling requires a positive value for the rssi,
904 * to do that correctly we need to add the correction.
905 */
906 rssi += rt2x00dev->rssi_offset;
907
908 if (rssi <= 30)
909 led = 0;
910 else if (rssi <= 39)
911 led = 1;
912 else if (rssi <= 49)
913 led = 2;
914 else if (rssi <= 53)
915 led = 3;
916 else if (rssi <= 63)
917 led = 4;
918 else
919 led = 5;
920
921 rt61pci_mcu_request(rt2x00dev, MCU_LED_STRENGTH, 0xff, led, 0);
922 }
923
924 /*
925 * Link tuning
926 */
927 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
928 {
929 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
930 u32 reg;
931 u8 r17;
932 u8 up_bound;
933 u8 low_bound;
934
935 /*
936 * Update Led strength
937 */
938 rt61pci_activity_led(rt2x00dev, rssi);
939
940 rt61pci_bbp_read(rt2x00dev, 17, &r17);
941
942 /*
943 * Determine r17 bounds.
944 */
945 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
946 low_bound = 0x28;
947 up_bound = 0x48;
948 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
949 low_bound += 0x10;
950 up_bound += 0x10;
951 }
952 } else {
953 low_bound = 0x20;
954 up_bound = 0x40;
955 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
956 low_bound += 0x10;
957 up_bound += 0x10;
958 }
959 }
960
961 /*
962 * Special big-R17 for very short distance
963 */
964 if (rssi >= -35) {
965 if (r17 != 0x60)
966 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
967 return;
968 }
969
970 /*
971 * Special big-R17 for short distance
972 */
973 if (rssi >= -58) {
974 if (r17 != up_bound)
975 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
976 return;
977 }
978
979 /*
980 * Special big-R17 for middle-short distance
981 */
982 if (rssi >= -66) {
983 low_bound += 0x10;
984 if (r17 != low_bound)
985 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
986 return;
987 }
988
989 /*
990 * Special mid-R17 for middle distance
991 */
992 if (rssi >= -74) {
993 low_bound += 0x08;
994 if (r17 != low_bound)
995 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
996 return;
997 }
998
999 /*
1000 * Special case: Change up_bound based on the rssi.
1001 * Lower up_bound when rssi is weaker then -74 dBm.
1002 */
1003 up_bound -= 2 * (-74 - rssi);
1004 if (low_bound > up_bound)
1005 up_bound = low_bound;
1006
1007 if (r17 > up_bound) {
1008 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
1009 return;
1010 }
1011
1012 /*
1013 * r17 does not yet exceed upper limit, continue and base
1014 * the r17 tuning on the false CCA count.
1015 */
1016 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1017 rt2x00dev->link.false_cca =
1018 rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1019
1020 if (rt2x00dev->link.false_cca > 512 && r17 < up_bound) {
1021 if (++r17 > up_bound)
1022 r17 = up_bound;
1023 rt61pci_bbp_write(rt2x00dev, 17, r17);
1024 rt2x00dev->rx_status.noise = r17;
1025 } else if (rt2x00dev->link.false_cca < 100 && r17 > low_bound) {
1026 if (--r17 < low_bound)
1027 r17 = low_bound;
1028 rt61pci_bbp_write(rt2x00dev, 17, r17);
1029 rt2x00dev->rx_status.noise = r17;
1030 }
1031 }
1032
1033 /*
1034 * Firmware name function.
1035 */
1036 static char *rt61pci_get_fw_name(struct rt2x00_dev *rt2x00dev)
1037 {
1038 char *fw_name;
1039
1040 switch (rt2x00dev->chip.rt) {
1041 case RT2561:
1042 fw_name = FIRMWARE_RT2561;
1043 break;
1044 case RT2561s:
1045 fw_name = FIRMWARE_RT2561s;
1046 break;
1047 case RT2661:
1048 fw_name = FIRMWARE_RT2661;
1049 break;
1050 default:
1051 fw_name = NULL;
1052 break;
1053 }
1054
1055 return fw_name;
1056 }
1057
1058 /*
1059 * Initialization functions.
1060 */
1061 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
1062 const size_t len)
1063 {
1064 int i;
1065 u32 reg;
1066
1067 /*
1068 * Wait for stable hardware.
1069 */
1070 for (i = 0; i < 100; i++) {
1071 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1072 if (reg)
1073 break;
1074 msleep(1);
1075 }
1076
1077 if (!reg) {
1078 ERROR(rt2x00dev, "Unstable hardware.\n");
1079 return -EBUSY;
1080 }
1081
1082 /*
1083 * Prepare MCU and mailbox for firmware loading.
1084 */
1085 reg = 0;
1086 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1087 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1088 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1089 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1090 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1091
1092 /*
1093 * Write firmware to device.
1094 */
1095 reg = 0;
1096 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1097 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1098 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1099
1100 rt2x00pci_register_multiwrite(
1101 rt2x00dev, FIRMWARE_IMAGE_BASE, data, len);
1102
1103 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1104 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1105
1106 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1107 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1108
1109 for (i = 0; i < 100; i++) {
1110 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1111 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1112 break;
1113 msleep(1);
1114 }
1115
1116 if (i == 100) {
1117 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1118 return -EBUSY;
1119 }
1120
1121 /*
1122 * Reset MAC and BBP registers.
1123 */
1124 reg = 0;
1125 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1126 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1127 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1128
1129 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1130 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1131 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1132 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1133
1134 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1135 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1136 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1137
1138 return 0;
1139 }
1140
1141 static void rt61pci_init_rxring(struct rt2x00_dev *rt2x00dev)
1142 {
1143 struct data_desc *rxd;
1144 unsigned int i;
1145 u32 word;
1146
1147 memset(rt2x00dev->rx->data_addr, 0x00,
1148 rt2x00_get_ring_size(rt2x00dev->rx));
1149
1150 for (i = 0; i < rt2x00dev->rx->stats.limit; i++) {
1151 rxd = rt2x00dev->rx->entry[i].priv;
1152
1153 rt2x00_desc_read(rxd, 5, &word);
1154 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1155 rt2x00dev->rx->entry[i].data_dma);
1156 rt2x00_desc_write(rxd, 5, word);
1157
1158 rt2x00_desc_read(rxd, 0, &word);
1159 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1160 rt2x00_desc_write(rxd, 0, word);
1161 }
1162
1163 rt2x00_ring_index_clear(rt2x00dev->rx);
1164 }
1165
1166 static void rt61pci_init_txring(struct rt2x00_dev *rt2x00dev,
1167 const int queue)
1168 {
1169 struct data_ring *ring = rt2x00_get_ring(rt2x00dev, queue);
1170 struct data_desc *txd;
1171 unsigned int i;
1172 u32 word;
1173
1174 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1175
1176 for (i = 0; i < ring->stats.limit; i++) {
1177 txd = ring->entry[i].priv;
1178
1179 rt2x00_desc_read(txd, 1, &word);
1180 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1181 rt2x00_desc_write(txd, 1, word);
1182
1183 rt2x00_desc_read(txd, 5, &word);
1184 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, queue);
1185 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, i);
1186 rt2x00_desc_write(txd, 5, word);
1187
1188 rt2x00_desc_read(txd, 6, &word);
1189 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1190 ring->entry[i].data_dma);
1191 rt2x00_desc_write(txd, 6, word);
1192
1193 rt2x00_desc_read(txd, 0, &word);
1194 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1195 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1196 rt2x00_desc_write(txd, 0, word);
1197 }
1198
1199 rt2x00_ring_index_clear(ring);
1200 }
1201
1202 static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
1203 {
1204 u32 reg;
1205
1206 /*
1207 * Initialize rings.
1208 */
1209 rt61pci_init_rxring(rt2x00dev);
1210 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1211 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1212 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA2);
1213 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA3);
1214 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA4);
1215 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
1216
1217 /*
1218 * Initialize registers.
1219 */
1220 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1221 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1222 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
1223 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1224 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
1225 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1226 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].stats.limit);
1227 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1228 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].stats.limit);
1229 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1230
1231 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1232 rt2x00_set_field32(&reg, TX_RING_CSR1_MGMT_RING_SIZE,
1233 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].stats.limit);
1234 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1235 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size / 4);
1236 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1237
1238 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1239 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1240 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
1241 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1242
1243 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1244 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1245 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
1246 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1247
1248 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1249 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1250 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].data_dma);
1251 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1252
1253 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1254 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1255 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].data_dma);
1256 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1257
1258 rt2x00pci_register_read(rt2x00dev, MGMT_BASE_CSR, &reg);
1259 rt2x00_set_field32(&reg, MGMT_BASE_CSR_RING_REGISTER,
1260 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].data_dma);
1261 rt2x00pci_register_write(rt2x00dev, MGMT_BASE_CSR, reg);
1262
1263 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1264 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE,
1265 rt2x00dev->rx->stats.limit);
1266 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1267 rt2x00dev->rx->desc_size / 4);
1268 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1269 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1270
1271 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1272 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1273 rt2x00dev->rx->data_dma);
1274 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1275
1276 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, 0x000000aa);
1277 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, 0x0000001f);
1278 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, 0x00000002);
1279
1280 return 0;
1281 }
1282
1283 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1284 {
1285 u32 reg;
1286
1287 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1288 return -EBUSY;
1289
1290 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1291
1292 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1293 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1294 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
1295 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
1296 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1297 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1298
1299 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, 0x9eb39eb3);
1300 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, 0x8a8b8c8d);
1301 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, 0x00858687);
1302
1303 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, 0x2e31353b);
1304 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, 0x2a2a2a2c);
1305
1306 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1307
1308 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1309
1310 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1311
1312 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1313 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1314 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1315
1316 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1317 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1318 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1319 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1320
1321 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1322 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1323 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1324 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1325
1326 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1327 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1328 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1329
1330 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1331 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1332 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1333 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1334
1335 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1336
1337 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1338
1339 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1340
1341 /*
1342 * We must clear the error counters.
1343 * These registers are cleared on read,
1344 * so we may pass a useless variable to store the value.
1345 */
1346 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1347 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1348 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1349
1350 /*
1351 * Reset MAC and BBP registers.
1352 */
1353 reg = 0;
1354 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1355 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1356 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1357
1358 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1359 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1360 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1361 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1362
1363 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1364 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1365 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1366
1367 return 0;
1368 }
1369
1370 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1371 {
1372 unsigned int i;
1373 u16 eeprom;
1374 u8 reg_id;
1375 u8 value;
1376
1377 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1378 rt61pci_bbp_read(rt2x00dev, 0, &value);
1379 if ((value != 0xff) && (value != 0x00))
1380 goto continue_csr_init;
1381 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1382 udelay(REGISTER_BUSY_DELAY);
1383 }
1384
1385 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1386 return -EACCES;
1387
1388 continue_csr_init:
1389 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1390 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1391 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
1392 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1393 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1394 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1395 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1396 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1397 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1398 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1399 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1400 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1401 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1402 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1403 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1404 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1405 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1406 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1407 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1408 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1409 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1410 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1411 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1412 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1413 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1414
1415 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1416 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1417 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1418
1419 if (eeprom != 0xffff && eeprom != 0x0000) {
1420 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1421 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1422 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1423 reg_id, value);
1424 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1425 }
1426 }
1427 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1428
1429 return 0;
1430 }
1431
1432 /*
1433 * Device state switch handlers.
1434 */
1435 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1436 enum dev_state state)
1437 {
1438 u32 reg;
1439
1440 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1441 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1442 state == STATE_RADIO_RX_OFF);
1443 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1444 }
1445
1446 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev, int enabled)
1447 {
1448 u32 reg;
1449
1450 /*
1451 * When interrupts are being enabled, the interrupt registers
1452 * should clear the register to assure a clean state.
1453 */
1454 if (enabled) {
1455 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1456 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1457
1458 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1459 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1460 }
1461
1462 /*
1463 * Only toggle the interrupts bits we are going to use.
1464 * Non-checked interrupt bits are disabled by default.
1465 */
1466 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1467 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, !enabled);
1468 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, !enabled);
1469 rt2x00_set_field32(&reg, INT_MASK_CSR_BEACON_DONE, !enabled);
1470 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, !enabled);
1471 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1472 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1473
1474 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1475 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, !enabled);
1476 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, !enabled);
1477 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, !enabled);
1478 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, !enabled);
1479 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, !enabled);
1480 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, !enabled);
1481 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, !enabled);
1482 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, !enabled);
1483 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1484 }
1485
1486 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1487 {
1488 /*
1489 * Initialize all registers.
1490 */
1491 if (rt61pci_init_rings(rt2x00dev) ||
1492 rt61pci_init_registers(rt2x00dev) ||
1493 rt61pci_init_bbp(rt2x00dev)) {
1494 ERROR(rt2x00dev, "Register initialization failed.\n");
1495 return -EIO;
1496 }
1497
1498 /*
1499 * Enable interrupts.
1500 */
1501 rt61pci_toggle_irq(rt2x00dev, 1);
1502
1503 /*
1504 * Enable RX.
1505 */
1506 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, 0x00000001);
1507
1508 /*
1509 * Enable LED
1510 */
1511 rt61pci_enable_led(rt2x00dev);
1512
1513 return 0;
1514 }
1515
1516 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1517 {
1518 u32 reg;
1519
1520 /*
1521 * Disable LED
1522 */
1523 rt61pci_disable_led(rt2x00dev);
1524
1525 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1526
1527 /*
1528 * Disable synchronisation.
1529 */
1530 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1531
1532 /*
1533 * Cancel RX and TX.
1534 */
1535 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1536 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1537 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1538 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1539 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1540 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_MGMT, 1);
1541 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1542
1543 /*
1544 * Disable interrupts.
1545 */
1546 rt61pci_toggle_irq(rt2x00dev, 0);
1547 }
1548
1549 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev,
1550 enum dev_state state)
1551 {
1552 u32 reg;
1553 unsigned int i;
1554 char put_to_sleep;
1555 char current_state;
1556
1557 put_to_sleep = (state != STATE_AWAKE);
1558
1559 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1560 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1561 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1562 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1563
1564 if (put_to_sleep) {
1565 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
1566 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
1567 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
1568 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0x00, 0x00);
1569 } else {
1570 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
1571 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
1572 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
1573 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0x00, 0x00);
1574 }
1575
1576 /*
1577 * Device is not guaranteed to be in the requested state yet.
1578 * We must wait until the register indicates that the
1579 * device has entered the correct state.
1580 */
1581 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1582 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1583 current_state = rt2x00_get_field32(reg,
1584 MAC_CSR12_BBP_CURRENT_STATE);
1585 if (current_state == !put_to_sleep)
1586 return 0;
1587 msleep(10);
1588 }
1589
1590 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1591 "current device state %d.\n", !put_to_sleep, current_state);
1592
1593 return -EBUSY;
1594 }
1595
1596 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1597 enum dev_state state)
1598 {
1599 int retval = 0;
1600
1601 switch (state) {
1602 case STATE_RADIO_ON:
1603 retval = rt61pci_enable_radio(rt2x00dev);
1604 break;
1605 case STATE_RADIO_OFF:
1606 rt61pci_disable_radio(rt2x00dev);
1607 break;
1608 case STATE_RADIO_RX_ON:
1609 case STATE_RADIO_RX_OFF:
1610 rt61pci_toggle_rx(rt2x00dev, state);
1611 break;
1612 case STATE_DEEP_SLEEP:
1613 case STATE_SLEEP:
1614 case STATE_STANDBY:
1615 case STATE_AWAKE:
1616 retval = rt61pci_set_state(rt2x00dev, state);
1617 break;
1618 default:
1619 retval = -ENOTSUPP;
1620 break;
1621 }
1622
1623 return retval;
1624 }
1625
1626 /*
1627 * TX descriptor initialization
1628 */
1629 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1630 struct data_entry *entry, struct data_desc *txd,
1631 struct data_entry_desc *desc, struct ieee80211_hdr *ieee80211hdr,
1632 unsigned int length, struct ieee80211_tx_control *control)
1633 {
1634 u32 word;
1635
1636 /*
1637 * Start writing the descriptor words.
1638 */
1639 rt2x00_desc_read(txd, 1, &word);
1640 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1641 rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->ring->tx_params.aifs);
1642 rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->ring->tx_params.cw_min);
1643 rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->ring->tx_params.cw_max);
1644 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1645 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1646 rt2x00_desc_write(txd, 1, word);
1647
1648 rt2x00_desc_read(txd, 2, &word);
1649 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1650 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1651 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1652 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1653 rt2x00_desc_write(txd, 2, word);
1654
1655 rt2x00_desc_read(txd, 5, &word);
1656 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1657 TXPOWER_TO_DEV(control->power_level));
1658 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1659 rt2x00_desc_write(txd, 5, word);
1660
1661 rt2x00_desc_read(txd, 11, &word);
1662 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, length);
1663 rt2x00_desc_write(txd, 11, word);
1664
1665 rt2x00_desc_read(txd, 0, &word);
1666 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1667 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1668 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1669 test_bit(ENTRY_TXD_MORE_FRAG, &entry->flags));
1670 rt2x00_set_field32(&word, TXD_W0_ACK,
1671 test_bit(ENTRY_TXD_REQ_ACK, &entry->flags));
1672 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1673 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &entry->flags));
1674 rt2x00_set_field32(&word, TXD_W0_OFDM,
1675 test_bit(ENTRY_TXD_OFDM_RATE, &entry->flags));
1676 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1677 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 0);
1678 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1679 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1680 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1681 rt2x00_desc_write(txd, 0, word);
1682 }
1683
1684 /*
1685 * TX data initialization
1686 */
1687 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, int queue)
1688 {
1689 u32 reg;
1690
1691 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1692 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1693 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1694 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1695 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1696 }
1697 return;
1698 }
1699
1700 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1701 if (queue == IEEE80211_TX_QUEUE_DATA0)
1702 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1);
1703 else if (queue == IEEE80211_TX_QUEUE_DATA1)
1704 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1);
1705 else if (queue == IEEE80211_TX_QUEUE_DATA2)
1706 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1);
1707 else if (queue == IEEE80211_TX_QUEUE_DATA3)
1708 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1);
1709 else if (queue == IEEE80211_TX_QUEUE_DATA4)
1710 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_MGMT, 1);
1711 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1712 }
1713
1714 /*
1715 * RX control handlers
1716 */
1717 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1718 {
1719 u16 eeprom;
1720 char offset;
1721 char lna;
1722
1723 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1724 switch (lna) {
1725 case 3:
1726 offset = 90;
1727 break;
1728 case 2:
1729 offset = 74;
1730 break;
1731 case 1:
1732 offset = 64;
1733 break;
1734 default:
1735 return 0;
1736 }
1737
1738 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1739 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1740 offset += 14;
1741
1742 if (lna == 3 || lna == 2)
1743 offset += 10;
1744
1745 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1746 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1747 } else {
1748 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1749 offset += 14;
1750
1751 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1752 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1753 }
1754
1755 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1756 }
1757
1758 static int rt61pci_fill_rxdone(struct data_entry *entry,
1759 int *signal, int *rssi, int *ofdm)
1760 {
1761 struct data_desc *rxd = entry->priv;
1762 u32 word0;
1763 u32 word1;
1764
1765 rt2x00_desc_read(rxd, 0, &word0);
1766 rt2x00_desc_read(rxd, 1, &word1);
1767
1768 /*
1769 * TODO: Don't we need to keep statistics
1770 * updated about these errors?
1771 */
1772 if (rt2x00_get_field32(word0, RXD_W0_CRC) ||
1773 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR))
1774 return -EINVAL;
1775
1776 /*
1777 * Obtain the status about this packet.
1778 */
1779 *signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1780 *rssi = rt61pci_agc_to_rssi(entry->ring->rt2x00dev, word1);
1781 *ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1782
1783 return rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1784 }
1785
1786 /*
1787 * Interrupt functions.
1788 */
1789 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1790 {
1791 struct data_ring *ring;
1792 struct data_entry *entry;
1793 struct data_desc *txd;
1794 u32 word;
1795 u32 reg;
1796 int index;
1797 int tx_status;
1798 int retry;
1799
1800 while (1) {
1801 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1802 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1803 break;
1804
1805 /*
1806 * Skip this entry when it contains an invalid
1807 * ring identication number.
1808 */
1809 ring = rt2x00_get_ring(rt2x00dev,
1810 rt2x00_get_field32(reg, STA_CSR4_PID_TYPE));
1811 if (unlikely(!ring))
1812 continue;
1813
1814 /*
1815 * Skip this entry when it contains an invalid
1816 * index number.
1817 */
1818 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1819 if (unlikely(index >= ring->stats.limit))
1820 continue;
1821
1822 entry = &ring->entry[index];
1823 txd = entry->priv;
1824 rt2x00_desc_read(txd, 0, &word);
1825
1826 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1827 !rt2x00_get_field32(word, TXD_W0_VALID))
1828 return;
1829
1830 /*
1831 * Obtain the status about this packet.
1832 */
1833 tx_status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1834 retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1835
1836 rt2x00lib_txdone(entry, tx_status, retry);
1837
1838 /*
1839 * Make this entry available for reuse.
1840 */
1841 entry->flags = 0;
1842 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1843 rt2x00_desc_write(txd, 0, word);
1844 rt2x00_ring_index_done_inc(entry->ring);
1845
1846 /*
1847 * If the data ring was full before the txdone handler
1848 * we must make sure the packet queue in the mac80211 stack
1849 * is reenabled when the txdone handler has finished.
1850 */
1851 if (!rt2x00_ring_full(ring))
1852 ieee80211_wake_queue(rt2x00dev->hw,
1853 entry->tx_status.control.queue);
1854 }
1855 }
1856
1857 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1858 {
1859 struct rt2x00_dev *rt2x00dev = dev_instance;
1860 u32 reg;
1861
1862 /*
1863 * Get the interrupt sources & saved to local variable.
1864 * Write register value back to clear pending interrupts.
1865 */
1866 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1867 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1868
1869 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1870 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1871
1872 if (!reg)
1873 return IRQ_NONE;
1874
1875 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1876 return IRQ_HANDLED;
1877
1878 /*
1879 * Handle interrupts, walk through all bits
1880 * and run the tasks, the bits are checked in order of
1881 * priority.
1882 */
1883
1884 /*
1885 * 1 - Beacon timer expired interrupt.
1886 */
1887 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))
1888 rt2x00pci_beacondone(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
1889
1890 /*
1891 * 2 - Rx ring done interrupt.
1892 */
1893 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1894 rt2x00pci_rxdone(rt2x00dev);
1895
1896 /*
1897 * 3 - Tx ring done interrupt.
1898 */
1899 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1900 rt61pci_txdone(rt2x00dev);
1901
1902 return IRQ_HANDLED;
1903 }
1904
1905 /*
1906 * Device initialization functions.
1907 */
1908 static int rt61pci_alloc_eeprom(struct rt2x00_dev *rt2x00dev)
1909 {
1910 struct eeprom_93cx6 eeprom;
1911 u32 reg;
1912 u16 word;
1913 u8 *mac;
1914 char value;
1915
1916 /*
1917 * Allocate the eeprom memory, check the eeprom width
1918 * and copy the entire eeprom into this allocated memory.
1919 */
1920 rt2x00dev->eeprom = kzalloc(EEPROM_SIZE, GFP_KERNEL);
1921 if (!rt2x00dev->eeprom)
1922 return -ENOMEM;
1923
1924 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1925
1926 eeprom.data = rt2x00dev;
1927 eeprom.register_read = rt61pci_eepromregister_read;
1928 eeprom.register_write = rt61pci_eepromregister_write;
1929 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1930 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1931 eeprom.reg_data_in = 0;
1932 eeprom.reg_data_out = 0;
1933 eeprom.reg_data_clock = 0;
1934 eeprom.reg_chip_select = 0;
1935
1936 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1937 EEPROM_SIZE / sizeof(u16));
1938
1939 /*
1940 * Start validation of the data that has been read.
1941 */
1942 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1943 if (!is_valid_ether_addr(mac)) {
1944 random_ether_addr(mac);
1945 EEPROM(rt2x00dev, "MAC: " MAC_FMT "\n", MAC_ARG(mac));
1946 }
1947
1948 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1949 if (word == 0xffff) {
1950 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1951 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 2);
1952 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 2);
1953 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1954 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1955 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1956 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1957 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1958 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1959 }
1960
1961 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1962 if (word == 0xffff) {
1963 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1964 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1965 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1966 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1967 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1968 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1969 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1970 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1971 }
1972
1973 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1974 if (word == 0xffff) {
1975 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1976 LED_MODE_DEFAULT);
1977 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1978 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1979 }
1980
1981 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1982 if (word == 0xffff) {
1983 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1984 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1985 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1986 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1987 }
1988
1989 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1990 if (word == 0xffff) {
1991 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1992 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1993 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1994 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1995 } else {
1996 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1997 if (value < -10 || value > 10)
1998 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1999 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2000 if (value < -10 || value > 10)
2001 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2002 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2003 }
2004
2005 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2006 if (word == 0xffff) {
2007 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2008 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2009 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2010 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2011 } else {
2012 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2013 if (value < -10 || value > 10)
2014 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2015 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2016 if (value < -10 || value > 10)
2017 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2018 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2019 }
2020
2021 return 0;
2022 }
2023
2024 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2025 {
2026 u32 reg;
2027 u16 value;
2028 u16 eeprom;
2029 u16 device;
2030
2031 /*
2032 * Read EEPROM word for configuration.
2033 */
2034 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2035
2036 /*
2037 * Identify RF chipset.
2038 * To determine the RT chip we have to read the
2039 * PCI header of the device.
2040 */
2041 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
2042 PCI_CONFIG_HEADER_DEVICE, &device);
2043 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2044 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2045 rt2x00_set_chip(rt2x00dev, device, value, reg);
2046
2047 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2048 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2049 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2050 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2051 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2052 return -ENODEV;
2053 }
2054
2055 /*
2056 * Identify default antenna configuration.
2057 */
2058 rt2x00dev->hw->conf.antenna_sel_tx = rt2x00_get_field16(eeprom,
2059 EEPROM_ANTENNA_TX_DEFAULT);
2060 rt2x00dev->hw->conf.antenna_sel_rx = rt2x00_get_field16(eeprom,
2061 EEPROM_ANTENNA_RX_DEFAULT);
2062
2063 /*
2064 * Read the Frame type.
2065 */
2066 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2067 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2068
2069 /*
2070 * Determine number of antenna's.
2071 */
2072 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2073 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2074
2075 /*
2076 * Detect if this device has an hardware controlled radio.
2077 */
2078 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2079 __set_bit(DEVICE_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2080
2081 /*
2082 * Read frequency offset and RF programming sequence.
2083 */
2084 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2085 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2086 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2087
2088 rt2x00dev->freq_offset =
2089 rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2090
2091 /*
2092 * Read external LNA informations.
2093 */
2094 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2095
2096 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2097 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2098 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2099 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2100
2101 /*
2102 * Store led settings, for correct led behaviour.
2103 * If the eeprom value is invalid,
2104 * switch to default led mode.
2105 */
2106 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2107
2108 rt2x00dev->led_mode = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2109
2110 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
2111 rt2x00dev->led_mode);
2112 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
2113 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_GPIO_0));
2114 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
2115 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_GPIO_1));
2116 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
2117 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_GPIO_2));
2118 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
2119 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_GPIO_3));
2120 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
2121 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_GPIO_4));
2122 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
2123 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2124 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
2125 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_RDY_G));
2126 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
2127 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_RDY_A));
2128
2129 return 0;
2130 }
2131
2132 /*
2133 * RF value list for RF5225, RF5325, RF2527 & RF2529
2134 * Supports: 2.4 GHz
2135 */
2136 static const u32 rf_vals_bg[] = {
2137 0x00004786, 0x00004786, 0x0000478a, 0x0000478a, 0x0000478e,
2138 0x0000478e, 0x00004792, 0x00004792, 0x00004796, 0x00004796,
2139 0x0000479a, 0x0000479a, 0x0000479e, 0x000047a2
2140 };
2141
2142 /*
2143 * RF value list for RF5225 & RF5325 (supplement to vals_bg)
2144 * Supports: 5.2 GHz, rf_sequence disabled
2145 */
2146 static const u32 rf_vals_a_5x_noseq[] = {
2147 0x0000499a, 0x000049a2, 0x000049a6, 0x000049aa, 0x000049ae,
2148 0x000049b2, 0x000049ba, 0x000049be, 0x00004a2a, 0x00004a2e,
2149 0x00004a32, 0x00004a36, 0x00004a3a, 0x00004a82, 0x00004a86,
2150 0x00004a8a, 0x00004a8e, 0x00004a92, 0x00004a9a, 0x00004aa2,
2151 0x00004aa6, 0x00004aae, 0x00004ab2, 0x00004ab6
2152 };
2153
2154 /*
2155 * RF value list for RF5225 & RF5325 (supplement to vals_bg)
2156 * Supports: 5.2 GHz, rf_sequence enabled
2157 */
2158 static const u32 rf_vals_a_5x_seq[] = {
2159 0x0004481a, 0x00044682, 0x00044686, 0x0004468e, 0x00044692,
2160 0x0004469a, 0x000446a2, 0x000446a6, 0x0004489a, 0x000448a2,
2161 0x000448aa, 0x000448b2, 0x000448ba, 0x00044702, 0x00044706,
2162 0x0004470e, 0x00044712, 0x0004471a, 0x00044722, 0x0004472e,
2163 0x00044736, 0x0004490a, 0x00044912, 0x0004491a
2164 };
2165
2166 static void rt61pci_init_hw_mode(struct rt2x00_dev *rt2x00dev)
2167 {
2168 struct hw_mode_spec *spec = &rt2x00dev->spec;
2169 u8 *txpower;
2170 unsigned int i;
2171
2172 /*
2173 * Initialize all hw fields.
2174 */
2175 rt2x00dev->hw->flags = IEEE80211_HW_HOST_GEN_BEACON |
2176 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2177 IEEE80211_HW_WEP_INCLUDE_IV |
2178 IEEE80211_HW_DATA_NULLFUNC_ACK |
2179 IEEE80211_HW_NO_TKIP_WMM_HWACCEL |
2180 IEEE80211_HW_MONITOR_DURING_OPER |
2181 IEEE80211_HW_NO_PROBE_FILTERING;
2182 rt2x00dev->hw->extra_tx_headroom = 0;
2183 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2184 rt2x00dev->hw->max_noise = MAX_RX_NOISE;
2185 rt2x00dev->hw->queues = 5;
2186
2187 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2188 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2189 rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0));
2190
2191 /*
2192 * Convert tx_power array in eeprom.
2193 */
2194 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2195 for (i = 0; i < 14; i++)
2196 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2197
2198 /*
2199 * Initialize hw_mode information.
2200 */
2201 spec->num_modes = 2;
2202 spec->num_rates = 12;
2203 spec->num_channels = 14;
2204 spec->tx_power_a = NULL;
2205 spec->tx_power_bg = txpower;
2206 spec->tx_power_default = DEFAULT_TXPOWER;
2207 spec->chan_val_a = NULL;
2208 spec->chan_val_bg = rf_vals_bg;
2209
2210 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2211 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2212 spec->num_modes = 3;
2213 spec->num_channels += 24;
2214
2215 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2216 for (i = 0; i < 14; i++)
2217 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2218
2219 spec->tx_power_a = txpower;
2220 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags))
2221 spec->chan_val_a = rf_vals_a_5x_noseq;
2222 else
2223 spec->chan_val_a = rf_vals_a_5x_seq;
2224 }
2225 }
2226
2227 static int rt61pci_init_hw(struct rt2x00_dev *rt2x00dev)
2228 {
2229 int retval;
2230
2231 /*
2232 * Allocate eeprom data.
2233 */
2234 retval = rt61pci_alloc_eeprom(rt2x00dev);
2235 if (retval)
2236 return retval;
2237
2238 retval = rt61pci_init_eeprom(rt2x00dev);
2239 if (retval)
2240 return retval;
2241
2242 /*
2243 * Initialize hw specifications.
2244 */
2245 rt61pci_init_hw_mode(rt2x00dev);
2246
2247 /*
2248 * This device requires firmware
2249 */
2250 __set_bit(FIRMWARE_REQUIRED, &rt2x00dev->flags);
2251
2252 /*
2253 * Set the rssi offset.
2254 */
2255 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2256
2257 return 0;
2258 }
2259
2260 /*
2261 * IEEE80211 stack callback functions.
2262 */
2263 static int rt61pci_get_stats(struct ieee80211_hw *hw,
2264 struct ieee80211_low_level_stats *stats)
2265 {
2266 struct rt2x00_dev *rt2x00dev = hw->priv;
2267 u32 reg;
2268
2269 /*
2270 * Update FCS error count from register.
2271 * The dot11ACKFailureCount, dot11RTSFailureCount and
2272 * dot11RTSSuccessCount are updated in interrupt time.
2273 */
2274 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
2275 rt2x00dev->low_level_stats.dot11FCSErrorCount +=
2276 rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
2277
2278 memcpy(stats, &rt2x00dev->low_level_stats, sizeof(*stats));
2279
2280 return 0;
2281 }
2282
2283 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2284 u32 short_retry, u32 long_retry)
2285 {
2286 struct rt2x00_dev *rt2x00dev = hw->priv;
2287 u32 reg;
2288
2289 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2290 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2291 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2292 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2293
2294 return 0;
2295 }
2296
2297 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2298 {
2299 struct rt2x00_dev *rt2x00dev = hw->priv;
2300 u64 tsf;
2301 u32 reg;
2302
2303 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2304 tsf = (u64)rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2305 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2306 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2307
2308 return tsf;
2309 }
2310
2311 static void rt61pci_reset_tsf(struct ieee80211_hw *hw)
2312 {
2313 struct rt2x00_dev *rt2x00dev = hw->priv;
2314
2315 rt2x00pci_register_write(rt2x00dev, TXRX_CSR12, 0);
2316 rt2x00pci_register_write(rt2x00dev, TXRX_CSR13, 0);
2317 }
2318
2319 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2320 .tx = rt2x00lib_tx,
2321 .reset = rt2x00lib_reset,
2322 .add_interface = rt2x00lib_add_interface,
2323 .remove_interface = rt2x00lib_remove_interface,
2324 .config = rt2x00lib_config,
2325 .config_interface = rt2x00lib_config_interface,
2326 .set_multicast_list = rt2x00lib_set_multicast_list,
2327 .get_stats = rt61pci_get_stats,
2328 .set_retry_limit = rt61pci_set_retry_limit,
2329 .conf_tx = rt2x00lib_conf_tx,
2330 .get_tx_stats = rt2x00lib_get_tx_stats,
2331 .get_tsf = rt61pci_get_tsf,
2332 .reset_tsf = rt61pci_reset_tsf,
2333 .beacon_update = rt2x00pci_beacon_update,
2334 };
2335
2336 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2337 .irq_handler = rt61pci_interrupt,
2338 .init_hw = rt61pci_init_hw,
2339 .get_fw_name = rt61pci_get_fw_name,
2340 .load_firmware = rt61pci_load_firmware,
2341 .initialize = rt2x00pci_initialize,
2342 .uninitialize = rt2x00pci_uninitialize,
2343 .set_device_state = rt61pci_set_device_state,
2344 #ifdef CONFIG_RT61PCI_RFKILL
2345 .rfkill_poll = rt61pci_rfkill_poll,
2346 #endif /* CONFIG_RT61PCI_RFKILL */
2347 .link_tuner = rt61pci_link_tuner,
2348 .write_tx_desc = rt61pci_write_tx_desc,
2349 .write_tx_data = rt2x00pci_write_tx_data,
2350 .kick_tx_queue = rt61pci_kick_tx_queue,
2351 .fill_rxdone = rt61pci_fill_rxdone,
2352 .config_type = rt61pci_config_type,
2353 .config_phymode = rt61pci_config_phymode,
2354 .config_channel = rt61pci_config_channel,
2355 .config_mac_addr = rt61pci_config_mac_addr,
2356 .config_bssid = rt61pci_config_bssid,
2357 .config_promisc = rt61pci_config_promisc,
2358 .config_txpower = rt61pci_config_txpower,
2359 .config_antenna = rt61pci_config_antenna,
2360 .config_duration = rt61pci_config_duration,
2361 };
2362
2363 static const struct rt2x00_ops rt61pci_ops = {
2364 .name = DRV_NAME,
2365 .rxd_size = RXD_DESC_SIZE,
2366 .txd_size = TXD_DESC_SIZE,
2367 .lib = &rt61pci_rt2x00_ops,
2368 .hw = &rt61pci_mac80211_ops,
2369 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2370 .debugfs = &rt61pci_rt2x00debug,
2371 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2372 };
2373
2374 /*
2375 * RT61pci module information.
2376 */
2377 static struct pci_device_id rt61pci_device_table[] = {
2378 /* RT2561s */
2379 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2380 /* RT2561 v2 */
2381 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2382 /* RT2661 */
2383 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2384 { 0, }
2385 };
2386
2387 MODULE_AUTHOR(DRV_PROJECT);
2388 MODULE_VERSION(DRV_VERSION);
2389 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2390 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2391 "PCI & PCMCIA chipset based cards");
2392 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2393 MODULE_FIRMWARE(FIRMWARE_RT2561);
2394 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2395 MODULE_FIRMWARE(FIRMWARE_RT2661);
2396 MODULE_LICENSE("GPL");
2397
2398 static struct pci_driver rt61pci_driver = {
2399 .name = DRV_NAME,
2400 .id_table = rt61pci_device_table,
2401 .probe = rt2x00pci_probe,
2402 .remove = __devexit_p(rt2x00pci_remove),
2403 #ifdef CONFIG_PM
2404 .suspend = rt2x00pci_suspend,
2405 .resume = rt2x00pci_resume,
2406 #endif /* CONFIG_PM */
2407 };
2408
2409 static int __init rt61pci_init(void)
2410 {
2411 return pci_register_driver(&rt61pci_driver);
2412 }
2413
2414 static void __exit rt61pci_exit(void)
2415 {
2416 pci_unregister_driver(&rt61pci_driver);
2417 }
2418
2419 module_init(rt61pci_init);
2420 module_exit(rt61pci_exit);
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