target/linux/danube/files/arch/mips/danube/setup.c

   1 /*
   2  *   arch/mips/danube/setup.c
   3  *
   4  *   This program is free software; you can redistribute it and/or modify
   5  *   it under the terms of the GNU General Public License as published by
   6  *   the Free Software Foundation; either version 2 of the License, or
   7  *   (at your option) any later version.
   8  *
   9  *   This program is distributed in the hope that it will be useful,
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *   GNU General Public License for more details.
  13  *
  14  *   You should have received a copy of the GNU General Public License
  15  *   along with this program; if not, write to the Free Software
  16  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  17  *
  18  *   Copyright (C) 2004 peng.liu@infineon.com
  19  *
  20  *   Rewrite of Infineon Danube code, thanks to infineon for the support,
  21  *   software and hardware
  22  *
  23  *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
  24  *
  25  */
  26
  27 #include <linux/init.h>
  28
  29 #include <asm/time.h>
  30 #include <asm/traps.h>
  31 #include <asm/cpu.h>
  32 #include <asm/irq.h>
  33 #include <asm/danube/danube.h>
  34 #include <asm/danube/danube_irq.h>
  35
  36 static unsigned int r4k_offset; /* Amount to increment compare reg each time */
  37 static unsigned int r4k_cur;    /* What counter should be at next timer irq */
  38
  39 extern void danube_reboot_setup (void);
  40 void prom_printf (const char * fmt, ...);
  41
  42 void
  43 __init bus_error_init (void)
  44 {
  45                 /* nothing yet */
  46 }
  47
  48 unsigned int
  49 danube_get_ddr_hz (void)
  50 {
  51         switch (readl(DANUBE_CGU_SYS) & 0x3)
  52         {
  53         case 0:
  54                 return CLOCK_167M;
  55         case 1:
  56                 return CLOCK_133M;
  57         case 2:
  58                 return CLOCK_111M;
  59         }
  60         return CLOCK_83M;
  61 }
  62 EXPORT_SYMBOL(danube_get_ddr_hz);
  63
  64 unsigned int
  65 danube_get_cpu_hz (void)
  66 {
  67         unsigned int ddr_clock = danube_get_ddr_hz();
  68         switch (readl(DANUBE_CGU_SYS) & 0xc)
  69         {
  70         case 0:
  71                 return CLOCK_333M;
  72         case 4:
  73                 return ddr_clock;
  74         }
  75         return ddr_clock << 1;
  76 }
  77 EXPORT_SYMBOL(danube_get_cpu_hz);
  78
  79 unsigned int
  80 danube_get_fpi_hz (void)
  81 {
  82         unsigned int ddr_clock = danube_get_ddr_hz();
  83         if (readl(DANUBE_CGU_SYS) & 0x40)
  84         {
  85                 return ddr_clock >> 1;
  86         }
  87         return ddr_clock;
  88 }
  89 EXPORT_SYMBOL(danube_get_fpi_hz);
  90
  91 unsigned int
  92 danube_get_cpu_ver (void)
  93 {
  94         return readl(DANUBE_MCD_CHIPID) & 0xFFFFF000;
  95 }
  96 EXPORT_SYMBOL(danube_get_cpu_ver);
  97
  98 void
  99 danube_time_init (void)
 100 {
 101         mips_hpt_frequency = danube_get_cpu_hz() / 2;
 102         r4k_offset = mips_hpt_frequency / HZ;
 103         printk("mips_hpt_frequency:%d\n", mips_hpt_frequency);
 104         printk("r4k_offset: %08x(%d)\n", r4k_offset, r4k_offset);
 105 }
 106
 107 int
 108 danube_be_handler(struct pt_regs *regs, int is_fixup)
 109 {
 110         /*TODO*/
 111         printk(KERN_ERR "TODO: BUS error\n");
 112
 113         return MIPS_BE_FATAL;
 114 }
 115
 116 /* ISR GPTU Timer 6 for high resolution timer */
 117 static irqreturn_t
 118 danube_timer6_interrupt(int irq, void *dev_id)
 119 {
 120         timer_interrupt(DANUBE_TIMER6_INT, NULL);
 121
 122         return IRQ_HANDLED;
 123 }
 124
 125 static struct irqaction hrt_irqaction = {
 126         .handler = danube_timer6_interrupt,
 127         .flags = IRQF_DISABLED,
 128         .name = "hrt",
 129 };
 130
 131 void __init
 132 plat_timer_setup (struct irqaction *irq)
 133 {
 134         unsigned int retval;
 135
 136         setup_irq(MIPS_CPU_TIMER_IRQ, irq);
 137
 138         r4k_cur = (read_c0_count() + r4k_offset);
 139         write_c0_compare(r4k_cur);
 140
 141         writel(readl(DANUBE_PMU_PWDCR) & ~(DANUBE_PMU_PWDCR_GPT|DANUBE_PMU_PWDCR_FPI), DANUBE_PMU_PWDCR);
 142
 143         writel(0x100, DANUBE_GPTU_GPT_CLC);
 144
 145         writel(0xffff, DANUBE_GPTU_GPT_CAPREL);
 146         writel(0x80C0, DANUBE_GPTU_GPT_T6CON);
 147
 148         retval = setup_irq(DANUBE_TIMER6_INT, &hrt_irqaction);
 149
 150         if (retval)
 151         {
 152                 prom_printf("reqeust_irq failed %d. HIGH_RES_TIMER is diabled\n", DANUBE_TIMER6_INT);
 153         }
 154 }
 155
 156 void __init
 157 plat_mem_setup (void)
 158 {
 159         u32 status;
 160         prom_printf("This %s has a cpu rev of 0x%X\n", BOARD_SYSTEM_TYPE, danube_get_cpu_ver());
 161
 162         //TODO WHY ???
 163         /* clear RE bit*/
 164         status = read_c0_status();
 165         status &= (~(1<<25));
 166         write_c0_status(status);
 167
 168         danube_reboot_setup();
 169         board_time_init = danube_time_init;
 170         board_be_handler = &danube_be_handler;
 171
 172         ioport_resource.start = IOPORT_RESOURCE_START;
 173         ioport_resource.end = IOPORT_RESOURCE_END;
 174         iomem_resource.start = IOMEM_RESOURCE_START;
 175         iomem_resource.end = IOMEM_RESOURCE_END;
 176 }