2 * linux/arch/mips/boot/compressed/head.S
4 * Copyright (C) 2005-2008 Ingenic Semiconductor Inc.
8 #include <asm/cacheops.h>
9 #include <asm/cachectl.h>
10 #include <asm/regdef.h>
12 #define IndexInvalidate_I 0x00
13 #define IndexWriteBack_D 0x01
18 move s0, a0 /* Save the boot loader transfered args */
25 1: sw zero, 0(a0) /* Clear BSS section */
29 la sp, (.stack + 8192)
35 la k0, decompress_kernel
59 li k0, 0x80000000 # start address
60 li k1, 0x80004000 # end address (16KB I-Cache)
65 cache IndexWriteBack_D, 0(k0)
66 cache IndexWriteBack_D, 32(k0)
67 cache IndexWriteBack_D, 64(k0)
68 cache IndexWriteBack_D, 96(k0)
69 cache IndexInvalidate_I, 0(k0)
70 cache IndexInvalidate_I, 32(k0)
71 cache IndexInvalidate_I, 64(k0)
72 cache IndexInvalidate_I, 96(k0)