2 * linux/drivers/usb/gadget/jz4740_udc.c
4 * Ingenic JZ4740 on-chip high speed USB device controller
6 * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
7 * Author: <jlwei@ingenic.cn>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
16 * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint.
18 * - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk.
19 * - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints.
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/delay.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/list.h>
31 #include <linux/interrupt.h>
32 #include <linux/proc_fs.h>
33 #include <linux/usb.h>
34 #include <linux/usb/gadget.h>
36 #include <asm/byteorder.h>
39 #include <asm/system.h>
40 #include <asm/mach-jz4740/jz4740.h>
41 #include <asm/mach-jz4740/clock.h>
43 #include "jz4740_udc.h"
45 #define JZ_REG_UDC_FADDR 0x00 /* Function Address 8-bit */
46 #define JZ_REG_UDC_POWER 0x01 /* Power Managemetn 8-bit */
47 #define JZ_REG_UDC_INTRIN 0x02 /* Interrupt IN 16-bit */
48 #define JZ_REG_UDC_INTROUT 0x04 /* Interrupt OUT 16-bit */
49 #define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */
50 #define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */
51 #define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */
52 #define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */
53 #define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */
54 #define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */
55 #define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */
57 #define JZ_REG_UDC_CSR0 0x12 /* EP0 CSR 8-bit */
58 #define JZ_REG_UDC_INMAXP 0x10 /* EP1-2 IN Max Pkt Size 16-bit */
59 #define JZ_REG_UDC_INCSR 0x12 /* EP1-2 IN CSR LSB 8/16bit */
60 #define JZ_REG_UDC_INCSRH 0x13 /* EP1-2 IN CSR MSB 8-bit */
61 #define JZ_REG_UDC_OUTMAXP 0x14 /* EP1 OUT Max Pkt Size 16-bit */
62 #define JZ_REG_UDC_OUTCSR 0x16 /* EP1 OUT CSR LSB 8/16bit */
63 #define JZ_REG_UDC_OUTCSRH 0x17 /* EP1 OUT CSR MSB 8-bit */
64 #define JZ_REG_UDC_OUTCOUNT 0x18 /* bytes in EP0/1 OUT FIFO 16-bit */
66 #define JZ_REG_UDC_EP_FIFO(x) (4 * (x) + 0x20)
68 #define JZ_REG_UDC_EPINFO 0x78 /* Endpoint information */
69 #define JZ_REG_UDC_RAMINFO 0x79 /* RAM information */
71 #define JZ_REG_UDC_INTR 0x200 /* DMA pending interrupts */
72 #define JZ_REG_UDC_CNTL1 0x204 /* DMA channel 1 control */
73 #define JZ_REG_UDC_ADDR1 0x208 /* DMA channel 1 AHB memory addr */
74 #define JZ_REG_UDC_COUNT1 0x20c /* DMA channel 1 byte count */
75 #define JZ_REG_UDC_CNTL2 0x214 /* DMA channel 2 control */
76 #define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */
77 #define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */
79 /* Power register bit masks */
80 #define USB_POWER_SUSPENDM 0x01
81 #define USB_POWER_RESUME 0x04
82 #define USB_POWER_HSMODE 0x10
83 #define USB_POWER_HSENAB 0x20
84 #define USB_POWER_SOFTCONN 0x40
86 /* Interrupt register bit masks */
87 #define USB_INTR_SUSPEND 0x01
88 #define USB_INTR_RESUME 0x02
89 #define USB_INTR_RESET 0x04
91 #define USB_INTR_EP0 0x0001
92 #define USB_INTR_INEP1 0x0002
93 #define USB_INTR_INEP2 0x0004
94 #define USB_INTR_OUTEP1 0x0002
97 #define USB_CSR0_OUTPKTRDY 0x01
98 #define USB_CSR0_INPKTRDY 0x02
99 #define USB_CSR0_SENTSTALL 0x04
100 #define USB_CSR0_DATAEND 0x08
101 #define USB_CSR0_SETUPEND 0x10
102 #define USB_CSR0_SENDSTALL 0x20
103 #define USB_CSR0_SVDOUTPKTRDY 0x40
104 #define USB_CSR0_SVDSETUPEND 0x80
106 /* Endpoint CSR register bits */
107 #define USB_INCSRH_AUTOSET 0x80
108 #define USB_INCSRH_ISO 0x40
109 #define USB_INCSRH_MODE 0x20
110 #define USB_INCSRH_DMAREQENAB 0x10
111 #define USB_INCSRH_DMAREQMODE 0x04
112 #define USB_INCSR_CDT 0x40
113 #define USB_INCSR_SENTSTALL 0x20
114 #define USB_INCSR_SENDSTALL 0x10
115 #define USB_INCSR_FF 0x08
116 #define USB_INCSR_UNDERRUN 0x04
117 #define USB_INCSR_FFNOTEMPT 0x02
118 #define USB_INCSR_INPKTRDY 0x01
119 #define USB_OUTCSRH_AUTOCLR 0x80
120 #define USB_OUTCSRH_ISO 0x40
121 #define USB_OUTCSRH_DMAREQENAB 0x20
122 #define USB_OUTCSRH_DNYT 0x10
123 #define USB_OUTCSRH_DMAREQMODE 0x08
124 #define USB_OUTCSR_CDT 0x80
125 #define USB_OUTCSR_SENTSTALL 0x40
126 #define USB_OUTCSR_SENDSTALL 0x20
127 #define USB_OUTCSR_FF 0x10
128 #define USB_OUTCSR_DATAERR 0x08
129 #define USB_OUTCSR_OVERRUN 0x04
130 #define USB_OUTCSR_FFFULL 0x02
131 #define USB_OUTCSR_OUTPKTRDY 0x01
133 /* Testmode register bits */
134 #define USB_TEST_SE0NAK 0x01
135 #define USB_TEST_J 0x02
136 #define USB_TEST_K 0x04
137 #define USB_TEST_PACKET 0x08
139 /* DMA control bits */
140 #define USB_CNTL_ENA 0x01
141 #define USB_CNTL_DIR_IN 0x02
142 #define USB_CNTL_MODE_1 0x04
143 #define USB_CNTL_INTR_EN 0x08
144 #define USB_CNTL_EP(n) ((n) << 4)
145 #define USB_CNTL_BURST_0 (0 << 9)
146 #define USB_CNTL_BURST_4 (1 << 9)
147 #define USB_CNTL_BURST_8 (2 << 9)
148 #define USB_CNTL_BURST_16 (3 << 9)
152 # define DEBUG(fmt,args...) do {} while(0)
156 # define DEBUG_EP0(fmt,args...) do {} while(0)
159 # define DEBUG_SETUP(fmt,args...) do {} while(0)
162 static unsigned int udc_debug
= 0; /* 0: normal mode, 1: test udc cable type mode */
164 module_param(udc_debug
, int, 0);
165 MODULE_PARM_DESC(udc_debug
, "test udc cable or power type");
167 static unsigned int use_dma
= 0; /* 1: use DMA, 0: use PIO */
169 module_param(use_dma
, int, 0);
170 MODULE_PARM_DESC(use_dma
, "DMA mode enable flag");
172 struct jz4740_udc
*the_controller
;
175 * Local declarations.
177 static void jz4740_ep0_kick(struct jz4740_udc
*dev
, struct jz4740_ep
*ep
);
178 static void jz4740_handle_ep0(struct jz4740_udc
*dev
, uint32_t intr
);
180 static void done(struct jz4740_ep
*ep
, struct jz4740_request
*req
,
182 static void pio_irq_enable(struct jz4740_ep
*ep
);
183 static void pio_irq_disable(struct jz4740_ep
*ep
);
184 static void stop_activity(struct jz4740_udc
*dev
,
185 struct usb_gadget_driver
*driver
);
186 static void nuke(struct jz4740_ep
*ep
, int status
);
187 static void flush(struct jz4740_ep
*ep
);
188 static void udc_set_address(struct jz4740_udc
*dev
, unsigned char address
);
190 /*-------------------------------------------------------------------------*/
192 /* inline functions of register read/write/set/clear */
194 static inline uint8_t usb_readb(struct jz4740_udc
*udc
, size_t reg
)
196 return readb(udc
->base
+ reg
);
199 static inline uint16_t usb_readw(struct jz4740_udc
*udc
, size_t reg
)
201 return readw(udc
->base
+ reg
);
204 static inline uint32_t usb_readl(struct jz4740_udc
*udc
, size_t reg
)
206 return readl(udc
->base
+ reg
);
209 static inline void usb_writeb(struct jz4740_udc
*udc
, size_t reg
, uint8_t val
)
211 writeb(val
, udc
->base
+ reg
);
214 static inline void usb_writew(struct jz4740_udc
*udc
, size_t reg
, uint16_t val
)
216 writew(val
, udc
->base
+ reg
);
219 static inline void usb_writel(struct jz4740_udc
*udc
, size_t reg
, uint32_t val
)
221 writel(val
, udc
->base
+ reg
);
224 static inline void usb_setb(struct jz4740_udc
*udc
, size_t reg
, uint8_t mask
)
226 usb_writeb(udc
, reg
, usb_readb(udc
, reg
) | mask
);
229 static inline void usb_setw(struct jz4740_udc
*udc
, size_t reg
, uint8_t mask
)
231 usb_writew(udc
, reg
, usb_readw(udc
, reg
) | mask
);
234 static inline void usb_setl(struct jz4740_udc
*udc
, size_t reg
, uint32_t mask
)
236 usb_writel(udc
, reg
, usb_readl(udc
, reg
) | mask
);
239 static inline void usb_clearb(struct jz4740_udc
*udc
, size_t reg
, uint8_t mask
)
241 usb_writeb(udc
, reg
, usb_readb(udc
, reg
) & ~mask
);
244 static inline void usb_clearw(struct jz4740_udc
*udc
, size_t reg
, uint16_t mask
)
246 usb_writew(udc
, reg
, usb_readw(udc
, reg
) & ~mask
);
249 static inline void usb_clearl(struct jz4740_udc
*udc
, size_t reg
, uint32_t mask
)
251 usb_writel(udc
, reg
, usb_readl(udc
, reg
) & ~mask
);
254 /*-------------------------------------------------------------------------*/
256 static inline void jz_udc_set_index(struct jz4740_udc
*udc
, uint8_t index
)
258 usb_writeb(udc
, JZ_REG_UDC_INDEX
, index
);
261 static inline void jz_udc_select_ep(struct jz4740_ep
*ep
)
263 jz_udc_set_index(ep
->dev
, ep_index(ep
));
266 static inline int write_packet(struct jz4740_ep
*ep
,
267 struct jz4740_request
*req
, int max
)
270 int length
, nlong
, nbyte
;
271 DEBUG("%s:%s[%d]\n", __FILE__
, __func__
, __LINE__
);
273 buf
= req
->req
.buf
+ req
->req
.actual
;
276 length
= req
->req
.length
- req
->req
.actual
;
277 length
= min(length
, max
);
278 req
->req
.actual
+= length
;
280 DEBUG("Write %d (max %d), fifo %x\n", length
, max
, ep
->fifo
);
283 nbyte
= length
& 0x3;
285 usb_writel(ep
->dev
, ep
->fifo
, *((uint32_t *)buf
));
289 usb_writeb(ep
->dev
, ep
->fifo
, *buf
++);
295 static inline int read_packet(struct jz4740_ep
*ep
,
296 struct jz4740_request
*req
, int count
)
299 int length
, nlong
, nbyte
;
300 DEBUG("%s:%s[%d]\n", __FILE__
, __func__
, __LINE__
);
302 buf
= req
->req
.buf
+ req
->req
.actual
;
305 length
= req
->req
.length
- req
->req
.actual
;
306 length
= min(length
, count
);
307 req
->req
.actual
+= length
;
309 DEBUG("Read %d, fifo %x\n", length
, ep
->fifo
);
312 nbyte
= length
& 0x3;
314 *((uint32_t *)buf
) = usb_readl(ep
->dev
, ep
->fifo
);
318 *buf
++ = usb_readb(ep
->dev
, ep
->fifo
);
324 /*-------------------------------------------------------------------------*/
327 * udc_disable - disable USB device controller
329 static void udc_disable(struct jz4740_udc
*dev
)
331 DEBUG("%s:%s[%d]\n", __FILE__
, __func__
, __LINE__
);
333 udc_set_address(dev
, 0);
335 /* Disable interrupts */
336 usb_writew(dev
, JZ_REG_UDC_INTRINE
, 0);
337 usb_writew(dev
, JZ_REG_UDC_INTROUTE
, 0);
338 usb_writeb(dev
, JZ_REG_UDC_INTRUSBE
, 0);
341 usb_writel(dev
, JZ_REG_UDC_CNTL1
, 0);
342 usb_writel(dev
, JZ_REG_UDC_CNTL2
, 0);
344 /* Disconnect from usb */
345 usb_clearb(dev
, JZ_REG_UDC_POWER
, USB_POWER_SOFTCONN
);
347 /* Disable the USB PHY */
348 #ifdef CONFIG_SOC_JZ4740
349 REG_CPM_SCR
&= ~CPM_SCR_USBPHY_ENABLE
;
350 #elif defined(CONFIG_SOC_JZ4750) || defined(CONFIG_SOC_JZ4750D)
351 REG_CPM_OPCR
&= ~CPM_OPCR_UDCPHY_ENABLE
;
354 dev
->ep0state
= WAIT_FOR_SETUP
;
355 dev
->gadget
.speed
= USB_SPEED_UNKNOWN
;
361 * udc_reinit - initialize software state
363 static void udc_reinit(struct jz4740_udc
*dev
)
366 DEBUG("%s:%s[%d]\n", __FILE__
, __func__
, __LINE__
);
368 /* device/ep0 records init */
369 INIT_LIST_HEAD(&dev
->gadget
.ep_list
);
370 INIT_LIST_HEAD(&dev
->gadget
.ep0
->ep_list
);
371 dev
->ep0state
= WAIT_FOR_SETUP
;
373 for (i
= 0; i
< UDC_MAX_ENDPOINTS
; i
++) {
374 struct jz4740_ep
*ep
= &dev
->ep
[i
];
377 list_add_tail(&ep
->ep
.ep_list
, &dev
->gadget
.ep_list
);
379 INIT_LIST_HEAD(&ep
->queue
);
386 /* until it's enabled, this UDC should be completely invisible
389 static void udc_enable(struct jz4740_udc
*dev
)
392 DEBUG("%s:%s[%d]\n", __FILE__
, __func__
, __LINE__
);
394 /* UDC state is incorrect - Added by River */
395 if (dev
->state
!= UDC_STATE_ENABLE
) {
399 dev
->gadget
.speed
= USB_SPEED_UNKNOWN
;
401 /* Flush FIFO for each */
402 for (i
= 0; i
< UDC_MAX_ENDPOINTS
; i
++) {
403 struct jz4740_ep
*ep
= &dev
->ep
[i
];
405 jz_udc_set_index(dev
, ep_index(ep
));
409 /* Set this bit to allow the UDC entering low-power mode when
410 * there are no actions on the USB bus.
411 * UDC still works during this bit was set.
415 /* Enable the USB PHY */
416 #ifdef CONFIG_SOC_JZ4740
417 REG_CPM_SCR
|= CPM_SCR_USBPHY_ENABLE
;
418 #elif defined(CONFIG_SOC_JZ4750) || defined(CONFIG_SOC_JZ4750D)
419 REG_CPM_OPCR
|= CPM_OPCR_UDCPHY_ENABLE
;
422 /* Disable interrupts */
423 /* usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
424 usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
425 usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/
427 /* Enable interrupts */
428 usb_setw(dev
, JZ_REG_UDC_INTRINE
, USB_INTR_EP0
);
429 usb_setb(dev
, JZ_REG_UDC_INTRUSBE
, USB_INTR_RESET
);
430 /* Don't enable rest of the interrupts */
431 /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2);
432 usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */
435 /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */
438 usb_setb(dev
, JZ_REG_UDC_POWER
, USB_POWER_HSENAB
);
440 /* Let host detect UDC:
441 * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this
442 * transistor on and pull the USBDP pin HIGH.
444 usb_setb(dev
, JZ_REG_UDC_POWER
, USB_POWER_SOFTCONN
);
449 /*-------------------------------------------------------------------------*/
451 /* keeping it simple:
452 * - one bus driver, initted first;
453 * - one function driver, initted second
457 * Register entry point for the peripheral controller driver.
460 int usb_gadget_register_driver(struct usb_gadget_driver
*driver
)
462 struct jz4740_udc
*dev
= the_controller
;
465 if (!driver
|| !driver
->bind
) {
477 /* hook up the driver */
478 dev
->driver
= driver
;
479 dev
->gadget
.dev
.driver
= &driver
->driver
;
481 retval
= driver
->bind(&dev
->gadget
);
483 DEBUG("%s: bind to driver %s --> error %d\n", dev
->gadget
.name
,
484 driver
->driver
.name
, retval
);
489 /* then enable host detection and ep0; and we're ready
490 * for set_configuration as well as eventual disconnect.
494 DEBUG("%s: registered gadget driver '%s'\n", dev
->gadget
.name
,
495 driver
->driver
.name
);
500 EXPORT_SYMBOL(usb_gadget_register_driver
);
502 static void stop_activity(struct jz4740_udc
*dev
,
503 struct usb_gadget_driver
*driver
)
507 DEBUG("%s:%s[%d]\n", __FILE__
, __func__
, __LINE__
);
509 /* don't disconnect drivers more than once */
510 if (dev
->gadget
.speed
== USB_SPEED_UNKNOWN
)
512 dev
->gadget
.speed
= USB_SPEED_UNKNOWN
;
514 /* prevent new request submissions, kill any outstanding requests */
515 for (i
= 0; i
< UDC_MAX_ENDPOINTS
; i
++) {
516 struct jz4740_ep
*ep
= &dev
->ep
[i
];
520 jz_udc_set_index(dev
, ep_index(ep
));
521 nuke(ep
, -ESHUTDOWN
);
524 /* report disconnect; the driver is already quiesced */
526 spin_unlock(&dev
->lock
);
527 driver
->disconnect(&dev
->gadget
);
528 spin_lock(&dev
->lock
);
531 /* re-init driver-visible data structures */
537 * Unregister entry point for the peripheral controller driver.
539 int usb_gadget_unregister_driver(struct usb_gadget_driver
*driver
)
541 struct jz4740_udc
*dev
= the_controller
;
543 DEBUG("%s:%s[%d]\n", __FILE__
, __func__
, __LINE__
);
547 if (!driver
|| driver
!= dev
->driver
)
552 spin_lock_irqsave(&dev
->lock
, flags
);
554 stop_activity(dev
, driver
);
555 spin_unlock_irqrestore(&dev
->lock
, flags
);
557 driver
->unbind(&dev
->gadget
);
561 DEBUG("unregistered driver '%s'\n", driver
->driver
.name
);
566 EXPORT_SYMBOL(usb_gadget_unregister_driver
);
568 /*-------------------------------------------------------------------------*/
571 * Starting DMA using mode 1
573 static void kick_dma(struct jz4740_ep
*ep
, struct jz4740_request
*req
)
575 struct jz4740_udc
*dev
= ep
->dev
;
576 uint32_t count
= req
->req
.length
;
577 uint32_t physaddr
= virt_to_phys((void *)req
->req
.buf
);
579 DEBUG("%s:%s[%d]\n", __FILE__
, __func__
, __LINE__
);
581 jz_udc_select_ep(ep
);
583 if (ep_is_in(ep
)) { /* Bulk-IN transfer using DMA channel 1 */
584 ep
->reg_addr
= JZ_REG_UDC_ADDR1
;
586 dma_cache_wback_inv((unsigned long)req
->req
.buf
, count
);
590 usb_writeb(dev
, JZ_REG_UDC_INCSRH
,
591 USB_INCSRH_DMAREQENAB
| USB_INCSRH_AUTOSET
| USB_INCSRH_DMAREQMODE
);
593 usb_writel(dev
, JZ_REG_UDC_ADDR1
, physaddr
);
594 usb_writel(dev
, JZ_REG_UDC_COUNT1
, count
);
595 usb_writel(dev
, JZ_REG_UDC_CNTL1
, USB_CNTL_ENA
| USB_CNTL_DIR_IN
| USB_CNTL_MODE_1
|
596 USB_CNTL_INTR_EN
| USB_CNTL_BURST_16
| USB_CNTL_EP(ep_index(ep
)));
598 else { /* Bulk-OUT transfer using DMA channel 2 */
599 ep
->reg_addr
= JZ_REG_UDC_ADDR2
;
601 dma_cache_wback_inv((unsigned long)req
->req
.buf
, count
);
605 usb_setb(dev
, JZ_REG_UDC_OUTCSRH
,
606 USB_OUTCSRH_DMAREQENAB
| USB_OUTCSRH_AUTOCLR
| USB_OUTCSRH_DMAREQMODE
);
608 usb_writel(dev
, JZ_REG_UDC_ADDR2
, physaddr
);
609 usb_writel(dev
, JZ_REG_UDC_COUNT2
, count
);
610 usb_writel(dev
, JZ_REG_UDC_CNTL2
, USB_CNTL_ENA
| USB_CNTL_MODE_1
|
611 USB_CNTL_INTR_EN
| USB_CNTL_BURST_16
| USB_CNTL_EP(ep_index(ep
)));
615 /*-------------------------------------------------------------------------*/
617 /** Write request to FIFO (max write == maxp size)
618 * Return: 0 = still running, 1 = completed, negative = errno
619 * NOTE: INDEX register must be set for EP
621 static int write_fifo(struct jz4740_ep
*ep
, struct jz4740_request
*req
)
623 struct jz4740_udc
*dev
= ep
->dev
;
625 uint32_t physaddr
= virt_to_phys((void *)req
->req
.buf
);
627 DEBUG("%s:%s[%d]\n", __FILE__
, __func__
, __LINE__
);
628 max
= le16_to_cpu(ep
->desc
->wMaxPacketSize
);
633 /* DMA interrupt generated due to the last packet loaded into the FIFO */
635 dma_count
= usb_readl(dev
, ep
->reg_addr
) - physaddr
;
636 req
->req
.actual
+= dma_count
;
638 if (dma_count
% max
) {
639 /* If the last packet is less than MAXP, set INPKTRDY manually */
640 usb_setb(dev
, ep
->csr
, USB_INCSR_INPKTRDY
);
644 if (list_empty(&ep
->queue
)) {
649 /* advance the request queue */
650 req
= list_entry(ep
->queue
.next
, struct jz4740_request
, queue
);
657 * PIO mode handling starts here ...
660 csr
= usb_readb(dev
, ep
->csr
);
662 if (!(csr
& USB_INCSR_FFNOTEMPT
)) {
664 int is_last
, is_short
;
666 count
= write_packet(ep
, req
, max
);
667 usb_setb(dev
, ep
->csr
, USB_INCSR_INPKTRDY
);
669 /* last packet is usually short (or a zlp) */
670 if (unlikely(count
!= max
))
671 is_last
= is_short
= 1;
673 if (likely(req
->req
.length
!= req
->req
.actual
)
678 /* interrupt/iso maxpacket may not fill the fifo */
679 is_short
= unlikely(max
< ep_maxpacket(ep
));
682 DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__
,
684 is_last
? "/L" : "", is_short
? "/S" : "",
685 req
->req
.length
- req
->req
.actual
, req
);
687 /* requests complete when all IN data is in the FIFO */
690 if (list_empty(&ep
->queue
)) {
696 DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep
));
702 /** Read to request from FIFO (max read == bytes in fifo)
703 * Return: 0 = still running, 1 = completed, negative = errno
704 * NOTE: INDEX register must be set for EP
706 static int read_fifo(struct jz4740_ep
*ep
, struct jz4740_request
*req
)
708 struct jz4740_udc
*dev
= ep
->dev
;
710 unsigned count
, is_short
;
711 uint32_t physaddr
= virt_to_phys((void *)req
->req
.buf
);
716 /* DMA interrupt generated due to a packet less than MAXP loaded into the FIFO */
718 dma_count
= usb_readl(dev
, ep
->reg_addr
) - physaddr
;
719 req
->req
.actual
+= dma_count
;
721 /* Disable interrupt and DMA */
723 usb_writel(dev
, JZ_REG_UDC_CNTL2
, 0);
725 /* Read all bytes from this packet */
726 count
= usb_readw(dev
, JZ_REG_UDC_OUTCOUNT
);
727 count
= read_packet(ep
, req
, count
);
730 /* If the last packet is greater than zero, clear OUTPKTRDY manually */
731 usb_clearb(dev
, ep
->csr
, USB_OUTCSR_OUTPKTRDY
);
735 if (!list_empty(&ep
->queue
)) {
736 /* advance the request queue */
737 req
= list_entry(ep
->queue
.next
, struct jz4740_request
, queue
);
745 * PIO mode handling starts here ...
748 /* make sure there's a packet in the FIFO. */
749 csr
= usb_readb(dev
, ep
->csr
);
750 if (!(csr
& USB_OUTCSR_OUTPKTRDY
)) {
751 DEBUG("%s: Packet NOT ready!\n", __FUNCTION__
);
755 /* read all bytes from this packet */
756 count
= usb_readw(dev
, JZ_REG_UDC_OUTCOUNT
);
758 is_short
= (count
< ep
->ep
.maxpacket
);
760 count
= read_packet(ep
, req
, count
);
762 DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n",
763 ep
->ep
.name
, csr
, count
,
764 is_short
? "/S" : "", req
, req
->req
.actual
, req
->req
.length
);
766 /* Clear OutPktRdy */
767 usb_clearb(dev
, ep
->csr
, USB_OUTCSR_OUTPKTRDY
);
770 if (is_short
|| req
->req
.actual
== req
->req
.length
) {
773 if (list_empty(&ep
->queue
))
778 /* finished that packet. the next one may be waiting... */
783 * done - retire a request; caller blocked irqs
784 * INDEX register is preserved to keep same
786 static void done(struct jz4740_ep
*ep
, struct jz4740_request
*req
, int status
)
788 unsigned int stopped
= ep
->stopped
;
792 DEBUG("%s, %p\n", __FUNCTION__
, ep
);
793 list_del_init(&req
->queue
);
795 if (likely(req
->req
.status
== -EINPROGRESS
))
796 req
->req
.status
= status
;
798 status
= req
->req
.status
;
800 if (status
&& status
!= -ESHUTDOWN
)
801 DEBUG("complete %s req %p stat %d len %u/%u\n",
802 ep
->ep
.name
, &req
->req
, status
,
803 req
->req
.actual
, req
->req
.length
);
805 /* don't modify queue heads during completion callback */
807 /* Read current index (completion may modify it) */
808 spin_lock_irqsave(&ep
->dev
->lock
, flags
);
809 index
= usb_readb(ep
->dev
, JZ_REG_UDC_INDEX
);
811 req
->req
.complete(&ep
->ep
, &req
->req
);
814 jz_udc_set_index(ep
->dev
, index
);
815 spin_unlock_irqrestore(&ep
->dev
->lock
, flags
);
816 ep
->stopped
= stopped
;
819 /** Enable EP interrupt */
820 static void pio_irq_enable(struct jz4740_ep
*ep
)
822 uint8_t index
= ep_index(ep
);
823 struct jz4740_udc
*dev
= ep
->dev
;
824 DEBUG("%s: EP%d %s\n", __FUNCTION__
, ep_index(ep
), ep_is_in(ep
) ? "IN": "OUT");
830 usb_setw(dev
, JZ_REG_UDC_INTRINE
, BIT(index
));
831 dev
->in_mask
|= BIT(index
);
834 DEBUG("Unknown endpoint: %d\n", index
);
841 usb_setw(dev
, JZ_REG_UDC_INTROUTE
, BIT(index
));
842 dev
->out_mask
|= BIT(index
);
845 DEBUG("Unknown endpoint: %d\n", index
);
851 /** Disable EP interrupt */
852 static void pio_irq_disable(struct jz4740_ep
*ep
)
854 uint8_t index
= ep_index(ep
);
855 struct jz4740_udc
*dev
= ep
->dev
;
857 DEBUG("%s: EP%d %s\n", __FUNCTION__
, ep_index(ep
), ep_is_in(ep
) ? "IN": "OUT");
860 switch (ep_index(ep
)) {
863 usb_clearw(ep
->dev
, JZ_REG_UDC_INTRINE
, BIT(index
));
864 dev
->in_mask
&= ~BIT(index
);
867 DEBUG("Unknown endpoint: %d\n", index
);
872 switch (ep_index(ep
)) {
874 usb_clearw(ep
->dev
, JZ_REG_UDC_INTROUTE
, BIT(index
));
875 dev
->out_mask
&= ~BIT(index
);
878 DEBUG("Unknown endpoint: %d\n", index
);
885 * nuke - dequeue ALL requests
887 static void nuke(struct jz4740_ep
*ep
, int status
)
889 struct jz4740_request
*req
;
891 DEBUG("%s, %p\n", __FUNCTION__
, ep
);
896 /* called with irqs blocked */
897 while (!list_empty(&ep
->queue
)) {
898 req
= list_entry(ep
->queue
.next
, struct jz4740_request
, queue
);
899 done(ep
, req
, status
);
902 /* Disable IRQ if EP is enabled (has descriptor) */
908 * NOTE: INDEX register must be set before this call
910 static void flush(struct jz4740_ep
*ep
)
912 DEBUG("%s: %s\n", __FUNCTION__
, ep
->ep
.name
);
917 usb_setb(ep
->dev
, ep
->csr
, USB_INCSR_FF
);
920 usb_setb(ep
->dev
, ep
->csr
, USB_OUTCSR_FF
);
928 * jz4740_in_epn - handle IN interrupt
930 static void jz4740_in_epn(struct jz4740_udc
*dev
, uint32_t ep_idx
, uint32_t intr
)
933 struct jz4740_ep
*ep
= &dev
->ep
[ep_idx
+ 1];
934 struct jz4740_request
*req
;
935 DEBUG("%s:%s[%d]\n", __FILE__
, __func__
, __LINE__
);
937 jz_udc_set_index(dev
, ep_index(ep
));
939 csr
= usb_readb(dev
, ep
->csr
);
940 DEBUG("%s: %d, csr %x\n", __FUNCTION__
, ep_idx
, csr
);
942 if (csr
& USB_INCSR_SENTSTALL
) {
943 DEBUG("USB_INCSR_SENTSTALL\n");
944 usb_clearb(dev
, ep
->csr
, USB_INCSR_SENTSTALL
);
949 DEBUG("%s: NO EP DESC\n", __FUNCTION__
);
953 if (list_empty(&ep
->queue
))
956 req
= list_entry(ep
->queue
.next
, struct jz4740_request
, queue
);
958 DEBUG("req: %p\n", req
);
969 static void jz4740_out_epn(struct jz4740_udc
*dev
, uint32_t ep_idx
, uint32_t intr
)
971 struct jz4740_ep
*ep
= &dev
->ep
[ep_idx
];
972 struct jz4740_request
*req
;
974 DEBUG("%s: %d\n", __FUNCTION__
, ep_idx
);
976 jz_udc_set_index(dev
, ep_index(ep
));
981 /* DMA starts here ... */
982 if (list_empty(&ep
->queue
))
985 req
= list_entry(ep
->queue
.next
, struct jz4740_request
, queue
);
993 * PIO mode starts here ...
996 while ((csr
= usb_readb(dev
, ep
->csr
)) &
997 (USB_OUTCSR_OUTPKTRDY
| USB_OUTCSR_SENTSTALL
)) {
998 DEBUG("%s: %x\n", __FUNCTION__
, csr
);
1000 if (csr
& USB_OUTCSR_SENTSTALL
) {
1001 DEBUG("%s: stall sent, flush fifo\n",
1003 /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */
1005 } else if (csr
& USB_OUTCSR_OUTPKTRDY
) {
1006 if (list_empty(&ep
->queue
))
1010 list_entry(ep
->queue
.next
,
1011 struct jz4740_request
,
1015 DEBUG("%s: NULL REQ %d\n",
1016 __FUNCTION__
, ep_idx
);
1024 /* Throw packet away.. */
1025 DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__
, ep
, ep_idx
);
1030 /** Halt specific EP
1031 * Return 0 if success
1032 * NOTE: Sets INDEX register to EP !
1034 static int jz4740_set_halt(struct usb_ep
*_ep
, int value
)
1036 struct jz4740_udc
*dev
;
1037 struct jz4740_ep
*ep
;
1038 unsigned long flags
;
1040 DEBUG("%s:%s[%d]\n", __FILE__
, __func__
, __LINE__
);
1042 ep
= container_of(_ep
, struct jz4740_ep
, ep
);
1043 if (unlikely(!_ep
|| (!ep
->desc
&& ep
->type
!= ep_control
))) {
1044 DEBUG("%s, bad ep\n", __FUNCTION__
);
1050 spin_lock_irqsave(&dev
->lock
, flags
);
1052 jz_udc_select_ep(ep
);
1054 DEBUG("%s, ep %d, val %d\n", __FUNCTION__
, ep_index(ep
), value
);
1056 if (ep_index(ep
) == 0) {
1058 usb_setb(dev
, JZ_REG_UDC_CSR0
, USB_CSR0_SENDSTALL
);
1059 } else if (ep_is_in(ep
)) {
1060 uint32_t csr
= usb_readb(dev
, ep
->csr
);
1061 if (value
&& ((csr
& USB_INCSR_FFNOTEMPT
)
1062 || !list_empty(&ep
->queue
))) {
1064 * Attempts to halt IN endpoints will fail (returning -EAGAIN)
1065 * if any transfer requests are still queued, or if the controller
1066 * FIFO still holds bytes that the host hasn\92t collected.
1068 spin_unlock_irqrestore(&dev
->lock
, flags
);
1070 ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n",
1071 (csr
& USB_INCSR_FFNOTEMPT
),
1072 !list_empty(&ep
->queue
));
1077 usb_setb(dev
, ep
->csr
, USB_INCSR_SENDSTALL
);
1080 usb_clearb(dev
, ep
->csr
, USB_INCSR_SENDSTALL
);
1081 usb_setb(dev
, ep
->csr
, USB_INCSR_CDT
);
1087 usb_setb(dev
, ep
->csr
, USB_OUTCSR_SENDSTALL
);
1090 usb_clearb(dev
, ep
->csr
, USB_OUTCSR_SENDSTALL
);
1091 usb_setb(dev
, ep
->csr
, USB_OUTCSR_CDT
);
1101 spin_unlock_irqrestore(&dev
->lock
, flags
);
1103 DEBUG("%s %s halted\n", _ep
->name
, value
== 0 ? "NOT" : "IS");
1109 static int jz4740_ep_enable(struct usb_ep
*_ep
,
1110 const struct usb_endpoint_descriptor
*desc
)
1112 struct jz4740_ep
*ep
;
1113 struct jz4740_udc
*dev
;
1114 unsigned long flags
;
1115 uint32_t max
, csrh
= 0;
1117 DEBUG("%s: trying to enable %s\n", __FUNCTION__
, _ep
->name
);
1122 ep
= container_of(_ep
, struct jz4740_ep
, ep
);
1123 if (ep
->desc
|| ep
->type
== ep_control
1124 || desc
->bDescriptorType
!= USB_DT_ENDPOINT
1125 || ep
->bEndpointAddress
!= desc
->bEndpointAddress
) {
1126 DEBUG("%s, bad ep or descriptor\n", __FUNCTION__
);
1130 /* xfer types must match, except that interrupt ~= bulk */
1131 if (ep
->bmAttributes
!= desc
->bmAttributes
1132 && ep
->bmAttributes
!= USB_ENDPOINT_XFER_BULK
1133 && desc
->bmAttributes
!= USB_ENDPOINT_XFER_INT
) {
1134 DEBUG("%s, %s type mismatch\n", __FUNCTION__
, _ep
->name
);
1139 if (!dev
->driver
|| dev
->gadget
.speed
== USB_SPEED_UNKNOWN
) {
1140 DEBUG("%s, bogus device state\n", __FUNCTION__
);
1144 max
= le16_to_cpu(desc
->wMaxPacketSize
);
1146 spin_lock_irqsave(&ep
->dev
->lock
, flags
);
1148 /* Configure the endpoint */
1149 jz_udc_set_index(dev
, desc
->bEndpointAddress
& 0x0F);
1151 usb_writew(dev
, JZ_REG_UDC_INMAXP
, max
);
1152 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
1153 case USB_ENDPOINT_XFER_BULK
:
1154 case USB_ENDPOINT_XFER_INT
:
1155 csrh
&= ~USB_INCSRH_ISO
;
1157 case USB_ENDPOINT_XFER_ISOC
:
1158 csrh
|= USB_INCSRH_ISO
;
1161 usb_writeb(dev
, JZ_REG_UDC_INCSRH
, csrh
);
1164 usb_writew(dev
, JZ_REG_UDC_OUTMAXP
, max
);
1165 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
1166 case USB_ENDPOINT_XFER_BULK
:
1167 csrh
&= ~USB_OUTCSRH_ISO
;
1169 case USB_ENDPOINT_XFER_INT
:
1170 csrh
&= ~USB_OUTCSRH_ISO
;
1171 csrh
|= USB_OUTCSRH_DNYT
;
1173 case USB_ENDPOINT_XFER_ISOC
:
1174 csrh
|= USB_OUTCSRH_ISO
;
1177 usb_writeb(dev
, JZ_REG_UDC_OUTCSRH
, csrh
);
1184 ep
->ep
.maxpacket
= max
;
1186 spin_unlock_irqrestore(&ep
->dev
->lock
, flags
);
1188 /* Reset halt state (does flush) */
1189 jz4740_set_halt(_ep
, 0);
1191 DEBUG("%s: enabled %s\n", __FUNCTION__
, _ep
->name
);
1197 * NOTE: Sets INDEX register
1199 static int jz4740_ep_disable(struct usb_ep
*_ep
)
1201 struct jz4740_ep
*ep
;
1202 unsigned long flags
;
1204 DEBUG("%s, %p\n", __FUNCTION__
, _ep
);
1206 ep
= container_of(_ep
, struct jz4740_ep
, ep
);
1207 if (!_ep
|| !ep
->desc
) {
1208 DEBUG("%s, %s not enabled\n", __FUNCTION__
,
1209 _ep
? ep
->ep
.name
: NULL
);
1213 spin_lock_irqsave(&ep
->dev
->lock
, flags
);
1215 jz_udc_select_ep(ep
);
1217 /* Nuke all pending requests (does flush) */
1218 nuke(ep
, -ESHUTDOWN
);
1220 /* Disable ep IRQ */
1221 pio_irq_disable(ep
);
1226 spin_unlock_irqrestore(&ep
->dev
->lock
, flags
);
1228 DEBUG("%s: disabled %s\n", __FUNCTION__
, _ep
->name
);
1232 static struct usb_request
*jz4740_alloc_request(struct usb_ep
*ep
, gfp_t gfp_flags
)
1234 struct jz4740_request
*req
;
1236 DEBUG("%s, %p\n", __FUNCTION__
, ep
);
1238 req
= kzalloc(sizeof(*req
), gfp_flags
);
1242 INIT_LIST_HEAD(&req
->queue
);
1247 static void jz4740_free_request(struct usb_ep
*ep
, struct usb_request
*_req
)
1249 struct jz4740_request
*req
;
1251 DEBUG("%s, %p\n", __FUNCTION__
, ep
);
1253 req
= container_of(_req
, struct jz4740_request
, req
);
1254 WARN_ON(!list_empty(&req
->queue
));
1258 /*--------------------------------------------------------------------*/
1260 /** Queue one request
1261 * Kickstart transfer if needed
1262 * NOTE: Sets INDEX register
1264 static int jz4740_queue(struct usb_ep
*_ep
, struct usb_request
*_req
,
1267 struct jz4740_request
*req
;
1268 struct jz4740_ep
*ep
;
1269 struct jz4740_udc
*dev
;
1270 unsigned long flags
;
1272 DEBUG("%s, %p\n", __FUNCTION__
, _ep
);
1274 req
= container_of(_req
, struct jz4740_request
, req
);
1276 (!_req
|| !_req
->complete
|| !_req
->buf
1277 || !list_empty(&req
->queue
))) {
1278 DEBUG("%s, bad params\n", __FUNCTION__
);
1282 ep
= container_of(_ep
, struct jz4740_ep
, ep
);
1283 if (unlikely(!_ep
|| (!ep
->desc
&& ep
->type
!= ep_control
))) {
1284 DEBUG("%s, bad ep\n", __FUNCTION__
);
1289 if (unlikely(!dev
->driver
|| dev
->gadget
.speed
== USB_SPEED_UNKNOWN
)) {
1290 DEBUG("%s, bogus device state %p\n", __FUNCTION__
, dev
->driver
);
1294 DEBUG("%s queue req %p, len %d buf %p\n", _ep
->name
, _req
, _req
->length
,
1297 spin_lock_irqsave(&dev
->lock
, flags
);
1299 _req
->status
= -EINPROGRESS
;
1302 /* kickstart this i/o queue? */
1303 DEBUG("Add to %d Q %d %d\n", ep_index(ep
), list_empty(&ep
->queue
),
1305 if (list_empty(&ep
->queue
) && likely(!ep
->stopped
)) {
1308 if (unlikely(ep_index(ep
) == 0)) {
1310 list_add_tail(&req
->queue
, &ep
->queue
);
1311 jz4740_ep0_kick(dev
, ep
);
1313 } else if (use_dma
) {
1318 else if (ep_is_in(ep
)) {
1320 jz_udc_set_index(dev
, ep_index(ep
));
1321 csr
= usb_readb(dev
, ep
->csr
);
1323 if (!(csr
& USB_INCSR_FFNOTEMPT
)) {
1324 if (write_fifo(ep
, req
) == 1)
1329 jz_udc_set_index(dev
, ep_index(ep
));
1330 csr
= usb_readb(dev
, ep
->csr
);
1332 if (csr
& USB_OUTCSR_OUTPKTRDY
) {
1333 if (read_fifo(ep
, req
) == 1)
1339 /* pio or dma irq handler advances the queue. */
1340 if (likely(req
!= 0))
1341 list_add_tail(&req
->queue
, &ep
->queue
);
1343 spin_unlock_irqrestore(&dev
->lock
, flags
);
1348 /* dequeue JUST ONE request */
1349 static int jz4740_dequeue(struct usb_ep
*_ep
, struct usb_request
*_req
)
1351 struct jz4740_ep
*ep
;
1352 struct jz4740_request
*req
;
1353 unsigned long flags
;
1355 DEBUG("%s, %p\n", __FUNCTION__
, _ep
);
1357 ep
= container_of(_ep
, struct jz4740_ep
, ep
);
1358 if (!_ep
|| ep
->type
== ep_control
)
1361 spin_lock_irqsave(&ep
->dev
->lock
, flags
);
1363 /* make sure it's actually queued on this endpoint */
1364 list_for_each_entry(req
, &ep
->queue
, queue
) {
1365 if (&req
->req
== _req
)
1368 if (&req
->req
!= _req
) {
1369 spin_unlock_irqrestore(&ep
->dev
->lock
, flags
);
1372 done(ep
, req
, -ECONNRESET
);
1374 spin_unlock_irqrestore(&ep
->dev
->lock
, flags
);
1378 /** Return bytes in EP FIFO
1379 * NOTE: Sets INDEX register to EP
1381 static int jz4740_fifo_status(struct usb_ep
*_ep
)
1385 struct jz4740_ep
*ep
;
1386 unsigned long flags
;
1388 ep
= container_of(_ep
, struct jz4740_ep
, ep
);
1390 DEBUG("%s, bad ep\n", __FUNCTION__
);
1394 DEBUG("%s, %d\n", __FUNCTION__
, ep_index(ep
));
1396 /* LPD can't report unclaimed bytes from IN fifos */
1400 spin_lock_irqsave(&ep
->dev
->lock
, flags
);
1401 jz_udc_set_index(ep
->dev
, ep_index(ep
));
1403 csr
= usb_readb(ep
->dev
, ep
->csr
);
1404 if (ep
->dev
->gadget
.speed
!= USB_SPEED_UNKNOWN
||
1406 count
= usb_readw(ep
->dev
, JZ_REG_UDC_OUTCOUNT
);
1409 spin_unlock_irqrestore(&ep
->dev
->lock
, flags
);
1415 * NOTE: Sets INDEX register to EP
1417 static void jz4740_fifo_flush(struct usb_ep
*_ep
)
1419 struct jz4740_ep
*ep
;
1420 unsigned long flags
;
1422 DEBUG("%s:%s[%d]\n", __FILE__
, __func__
, __LINE__
);
1424 ep
= container_of(_ep
, struct jz4740_ep
, ep
);
1425 if (unlikely(!_ep
|| (!ep
->desc
&& ep
->type
== ep_control
))) {
1426 DEBUG("%s, bad ep\n", __FUNCTION__
);
1430 spin_lock_irqsave(&ep
->dev
->lock
, flags
);
1432 jz_udc_set_index(ep
->dev
, ep_index(ep
));
1435 spin_unlock_irqrestore(&ep
->dev
->lock
, flags
);
1438 /****************************************************************/
1439 /* End Point 0 related functions */
1440 /****************************************************************/
1442 /* return: 0 = still running, 1 = completed, negative = errno */
1443 static int write_fifo_ep0(struct jz4740_ep
*ep
, struct jz4740_request
*req
)
1449 DEBUG("%s:%s[%d]\n", __FILE__
, __func__
, __LINE__
);
1450 max
= ep_maxpacket(ep
);
1452 count
= write_packet(ep
, req
, max
);
1454 /* last packet is usually short (or a zlp) */
1455 if (unlikely(count
!= max
))
1458 if (likely(req
->req
.length
!= req
->req
.actual
) || req
->req
.zero
)
1464 DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__
,
1466 is_last
? "/L" : "", req
->req
.length
- req
->req
.actual
, req
);
1468 /* requests complete when all IN data is in the FIFO */
1477 static inline int jz4740_fifo_read(struct jz4740_ep
*ep
,
1478 unsigned char *cp
, int max
)
1481 int count
= usb_readw(ep
->dev
, JZ_REG_UDC_OUTCOUNT
);
1487 *cp
++ = usb_readb(ep
->dev
, ep
->fifo
);
1492 static inline void jz4740_fifo_write(struct jz4740_ep
*ep
,
1493 unsigned char *cp
, int count
)
1495 DEBUG("fifo_write: %d %d\n", ep_index(ep
), count
);
1497 usb_writeb(ep
->dev
, ep
->fifo
, *cp
++);
1500 static int read_fifo_ep0(struct jz4740_ep
*ep
, struct jz4740_request
*req
)
1502 struct jz4740_udc
*dev
= ep
->dev
;
1505 unsigned bufferspace
, count
, is_short
;
1507 DEBUG_EP0("%s\n", __FUNCTION__
);
1509 csr
= usb_readb(dev
, JZ_REG_UDC_CSR0
);
1510 if (!(csr
& USB_CSR0_OUTPKTRDY
))
1513 buf
= req
->req
.buf
+ req
->req
.actual
;
1515 bufferspace
= req
->req
.length
- req
->req
.actual
;
1517 /* read all bytes from this packet */
1518 if (likely(csr
& USB_CSR0_OUTPKTRDY
)) {
1519 count
= usb_readw(dev
, JZ_REG_UDC_OUTCOUNT
);
1520 req
->req
.actual
+= min(count
, bufferspace
);
1524 is_short
= (count
< ep
->ep
.maxpacket
);
1525 DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n",
1526 ep
->ep
.name
, csr
, count
,
1527 is_short
? "/S" : "", req
, req
->req
.actual
, req
->req
.length
);
1529 while (likely(count
-- != 0)) {
1530 uint8_t byte
= (uint8_t)usb_readl(dev
, ep
->fifo
);
1532 if (unlikely(bufferspace
== 0)) {
1533 /* this happens when the driver's buffer
1534 * is smaller than what the host sent.
1535 * discard the extra data.
1537 if (req
->req
.status
!= -EOVERFLOW
)
1538 DEBUG_EP0("%s overflow %d\n", ep
->ep
.name
,
1540 req
->req
.status
= -EOVERFLOW
;
1548 if (is_short
|| req
->req
.actual
== req
->req
.length
) {
1553 /* finished that packet. the next one may be waiting... */
1558 * udc_set_address - set the USB address for this device
1561 * Called from control endpoint function after it decodes a set address setup packet.
1563 static void udc_set_address(struct jz4740_udc
*dev
, unsigned char address
)
1565 DEBUG_EP0("%s: %d\n", __FUNCTION__
, address
);
1567 dev
->usb_address
= address
;
1568 usb_writeb(dev
, JZ_REG_UDC_FADDR
, address
);
1572 * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY)
1574 * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1576 * set USB_CSR0_SVDOUTPKTRDY bit
1577 if last set USB_CSR0_DATAEND bit
1579 static void jz4740_ep0_out(struct jz4740_udc
*dev
, uint32_t csr
, int kickstart
)
1581 struct jz4740_request
*req
;
1582 struct jz4740_ep
*ep
= &dev
->ep
[0];
1585 DEBUG_EP0("%s: %x\n", __FUNCTION__
, csr
);
1587 if (list_empty(&ep
->queue
))
1590 req
= list_entry(ep
->queue
.next
, struct jz4740_request
, queue
);
1593 if (req
->req
.length
== 0) {
1594 DEBUG_EP0("ZERO LENGTH OUT!\n");
1595 usb_setb(dev
, JZ_REG_UDC_CSR0
, (USB_CSR0_SVDOUTPKTRDY
| USB_CSR0_DATAEND
));
1596 dev
->ep0state
= WAIT_FOR_SETUP
;
1598 } else if (kickstart
) {
1599 usb_setb(dev
, JZ_REG_UDC_CSR0
, (USB_CSR0_SVDOUTPKTRDY
));
1602 ret
= read_fifo_ep0(ep
, req
);
1605 DEBUG_EP0("%s: finished, waiting for status\n",
1607 usb_setb(dev
, JZ_REG_UDC_CSR0
, (USB_CSR0_SVDOUTPKTRDY
| USB_CSR0_DATAEND
));
1608 dev
->ep0state
= WAIT_FOR_SETUP
;
1610 /* Not done yet.. */
1611 DEBUG_EP0("%s: not finished\n", __FUNCTION__
);
1612 usb_setb(dev
, JZ_REG_UDC_CSR0
, USB_CSR0_SVDOUTPKTRDY
);
1615 DEBUG_EP0("NO REQ??!\n");
1622 static int jz4740_ep0_in(struct jz4740_udc
*dev
, uint32_t csr
)
1624 struct jz4740_request
*req
;
1625 struct jz4740_ep
*ep
= &dev
->ep
[0];
1626 int ret
, need_zlp
= 0;
1628 DEBUG_EP0("%s: %x\n", __FUNCTION__
, csr
);
1630 if (list_empty(&ep
->queue
))
1633 req
= list_entry(ep
->queue
.next
, struct jz4740_request
, queue
);
1636 DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__
);
1640 if (req
->req
.length
== 0) {
1641 usb_setb(dev
, JZ_REG_UDC_CSR0
, (USB_CSR0_INPKTRDY
| USB_CSR0_DATAEND
));
1642 dev
->ep0state
= WAIT_FOR_SETUP
;
1646 if (req
->req
.length
- req
->req
.actual
== EP0_MAXPACKETSIZE
) {
1647 /* Next write will end with the packet size, */
1648 /* so we need zero-length-packet */
1652 ret
= write_fifo_ep0(ep
, req
);
1654 if (ret
== 1 && !need_zlp
) {
1656 DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__
);
1658 usb_setb(dev
, JZ_REG_UDC_CSR0
, (USB_CSR0_INPKTRDY
| USB_CSR0_DATAEND
));
1659 dev
->ep0state
= WAIT_FOR_SETUP
;
1661 DEBUG_EP0("%s: not finished\n", __FUNCTION__
);
1662 usb_setb(dev
, JZ_REG_UDC_CSR0
, USB_CSR0_INPKTRDY
);
1666 DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__
);
1667 usb_setb(dev
, JZ_REG_UDC_CSR0
, USB_CSR0_INPKTRDY
);
1668 dev
->ep0state
= DATA_STATE_NEED_ZLP
;
1674 static int jz4740_handle_get_status(struct jz4740_udc
*dev
,
1675 struct usb_ctrlrequest
*ctrl
)
1677 struct jz4740_ep
*ep0
= &dev
->ep
[0];
1678 struct jz4740_ep
*qep
;
1679 int reqtype
= (ctrl
->bRequestType
& USB_RECIP_MASK
);
1682 DEBUG("%s:%s[%d]\n", __FILE__
, __func__
, __LINE__
);
1684 if (reqtype
== USB_RECIP_INTERFACE
) {
1685 /* This is not supported.
1686 * And according to the USB spec, this one does nothing..
1689 DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n");
1690 } else if (reqtype
== USB_RECIP_DEVICE
) {
1691 DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n");
1692 val
|= (1 << 0); /* Self powered */
1693 /*val |= (1<<1); *//* Remote wakeup */
1694 } else if (reqtype
== USB_RECIP_ENDPOINT
) {
1695 int ep_num
= (ctrl
->wIndex
& ~USB_DIR_IN
);
1698 ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n",
1699 ep_num
, ctrl
->wLength
);
1701 if (ctrl
->wLength
> 2 || ep_num
> 3)
1704 qep
= &dev
->ep
[ep_num
];
1705 if (ep_is_in(qep
) != ((ctrl
->wIndex
& USB_DIR_IN
) ? 1 : 0)
1706 && ep_index(qep
) != 0) {
1710 jz_udc_set_index(dev
, ep_index(qep
));
1712 /* Return status on next IN token */
1713 switch (qep
->type
) {
1716 (usb_readb(dev
, qep
->csr
) & USB_CSR0_SENDSTALL
) ==
1722 (usb_readb(dev
, qep
->csr
) & USB_INCSR_SENDSTALL
) ==
1723 USB_INCSR_SENDSTALL
;
1727 (usb_readb(dev
, qep
->csr
) & USB_OUTCSR_SENDSTALL
) ==
1728 USB_OUTCSR_SENDSTALL
;
1732 /* Back to EP0 index */
1733 jz_udc_set_index(dev
, 0);
1735 DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num
,
1738 DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype
);
1742 /* Clear "out packet ready" */
1743 usb_setb(dev
, JZ_REG_UDC_CSR0
, USB_CSR0_SVDOUTPKTRDY
);
1744 /* Put status to FIFO */
1745 jz4740_fifo_write(ep0
, (uint8_t *)&val
, sizeof(val
));
1746 /* Issue "In packet ready" */
1747 usb_setb(dev
, JZ_REG_UDC_CSR0
, (USB_CSR0_INPKTRDY
| USB_CSR0_DATAEND
));
1753 * WAIT_FOR_SETUP (OUTPKTRDY)
1754 * - read data packet from EP0 FIFO
1757 * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1759 * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits
1761 static void jz4740_ep0_setup(struct jz4740_udc
*dev
, uint32_t csr
)
1763 struct jz4740_ep
*ep
= &dev
->ep
[0];
1764 struct usb_ctrlrequest ctrl
;
1767 DEBUG_SETUP("%s: %x\n", __FUNCTION__
, csr
);
1769 /* Nuke all previous transfers */
1772 /* read control req from fifo (8 bytes) */
1773 jz4740_fifo_read(ep
, (unsigned char *)&ctrl
, 8);
1775 DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n",
1776 ctrl
.bRequestType
, ctrl
.bRequest
,
1777 ctrl
.wValue
, ctrl
.wIndex
, ctrl
.wLength
);
1779 /* Set direction of EP0 */
1780 if (likely(ctrl
.bRequestType
& USB_DIR_IN
)) {
1781 ep
->bEndpointAddress
|= USB_DIR_IN
;
1783 ep
->bEndpointAddress
&= ~USB_DIR_IN
;
1786 /* Handle some SETUP packets ourselves */
1787 switch (ctrl
.bRequest
) {
1788 case USB_REQ_SET_ADDRESS
:
1789 if (ctrl
.bRequestType
!= (USB_TYPE_STANDARD
| USB_RECIP_DEVICE
))
1792 DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl
.wValue
);
1793 udc_set_address(dev
, ctrl
.wValue
);
1794 usb_setb(dev
, JZ_REG_UDC_CSR0
, (USB_CSR0_SVDOUTPKTRDY
| USB_CSR0_DATAEND
));
1797 case USB_REQ_SET_CONFIGURATION
:
1798 if (ctrl
.bRequestType
!= (USB_TYPE_STANDARD
| USB_RECIP_DEVICE
))
1801 DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl
.wValue
);
1802 /* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1804 /* Enable RESUME and SUSPEND interrupts */
1805 usb_setb(dev
, JZ_REG_UDC_INTRUSBE
, (USB_INTR_RESUME
| USB_INTR_SUSPEND
));
1808 case USB_REQ_SET_INTERFACE
:
1809 if (ctrl
.bRequestType
!= (USB_TYPE_STANDARD
| USB_RECIP_DEVICE
))
1812 DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl
.wValue
);
1813 /* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1816 case USB_REQ_GET_STATUS
:
1817 if (jz4740_handle_get_status(dev
, &ctrl
) == 0)
1820 case USB_REQ_CLEAR_FEATURE
:
1821 case USB_REQ_SET_FEATURE
:
1822 if (ctrl
.bRequestType
== USB_RECIP_ENDPOINT
) {
1823 struct jz4740_ep
*qep
;
1824 int ep_num
= (ctrl
.wIndex
& 0x0f);
1826 /* Support only HALT feature */
1827 if (ctrl
.wValue
!= 0 || ctrl
.wLength
!= 0
1828 || ep_num
> 3 || ep_num
< 1)
1831 qep
= &dev
->ep
[ep_num
];
1832 spin_unlock(&dev
->lock
);
1833 if (ctrl
.bRequest
== USB_REQ_SET_FEATURE
) {
1834 DEBUG_SETUP("SET_FEATURE (%d)\n",
1836 jz4740_set_halt(&qep
->ep
, 1);
1838 DEBUG_SETUP("CLR_FEATURE (%d)\n",
1840 jz4740_set_halt(&qep
->ep
, 0);
1842 spin_lock(&dev
->lock
);
1844 jz_udc_set_index(dev
, 0);
1846 /* Reply with a ZLP on next IN token */
1847 usb_setb(dev
, JZ_REG_UDC_CSR0
,
1848 (USB_CSR0_SVDOUTPKTRDY
| USB_CSR0_DATAEND
));
1857 /* gadget drivers see class/vendor specific requests,
1858 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1862 /* device-2-host (IN) or no data setup command, process immediately */
1863 spin_unlock(&dev
->lock
);
1865 i
= dev
->driver
->setup(&dev
->gadget
, &ctrl
);
1866 spin_lock(&dev
->lock
);
1868 if (unlikely(i
< 0)) {
1869 /* setup processing failed, force stall */
1871 (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n",
1873 jz_udc_set_index(dev
, 0);
1874 usb_setb(dev
, JZ_REG_UDC_CSR0
, (USB_CSR0_SVDOUTPKTRDY
| USB_CSR0_DATAEND
| USB_CSR0_SENDSTALL
));
1876 /* ep->stopped = 1; */
1877 dev
->ep0state
= WAIT_FOR_SETUP
;
1880 DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl
.wLength
);
1881 /* if (!ctrl.wLength) {
1882 usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1889 * DATA_STATE_NEED_ZLP
1891 static void jz4740_ep0_in_zlp(struct jz4740_udc
*dev
, uint32_t csr
)
1893 DEBUG_EP0("%s: %x\n", __FUNCTION__
, csr
);
1895 usb_setb(dev
, JZ_REG_UDC_CSR0
, (USB_CSR0_INPKTRDY
| USB_CSR0_DATAEND
));
1896 dev
->ep0state
= WAIT_FOR_SETUP
;
1900 * handle ep0 interrupt
1902 static void jz4740_handle_ep0(struct jz4740_udc
*dev
, uint32_t intr
)
1904 struct jz4740_ep
*ep
= &dev
->ep
[0];
1907 DEBUG("%s:%s[%d]\n", __FILE__
, __func__
, __LINE__
);
1909 jz_udc_set_index(dev
, 0);
1910 csr
= usb_readb(dev
, JZ_REG_UDC_CSR0
);
1912 DEBUG_EP0("%s: csr = %x state = \n", __FUNCTION__
, csr
);//, state_names[dev->ep0state]);
1915 * if SENT_STALL is set
1916 * - clear the SENT_STALL bit
1918 if (csr
& USB_CSR0_SENTSTALL
) {
1919 DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__
, csr
);
1920 usb_clearb(dev
, JZ_REG_UDC_CSR0
, USB_CSR0_SENDSTALL
| USB_CSR0_SENTSTALL
);
1921 nuke(ep
, -ECONNABORTED
);
1922 dev
->ep0state
= WAIT_FOR_SETUP
;
1927 * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear
1930 * - set IN_PKT_RDY | DATA_END
1934 if (!(csr
& (USB_CSR0_INPKTRDY
| USB_CSR0_OUTPKTRDY
))) {
1935 DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n",
1938 switch (dev
->ep0state
) {
1939 case DATA_STATE_XMIT
:
1940 DEBUG_EP0("continue with DATA_STATE_XMIT\n");
1941 jz4740_ep0_in(dev
, csr
);
1943 case DATA_STATE_NEED_ZLP
:
1944 DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n");
1945 jz4740_ep0_in_zlp(dev
, csr
);
1949 // DEBUG_EP0("Odd state!! state = %s\n",
1950 // state_names[dev->ep0state]);
1951 dev
->ep0state
= WAIT_FOR_SETUP
;
1953 /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */
1960 * if SETUPEND is set
1961 * - abort the last transfer
1962 * - set SERVICED_SETUP_END_BIT
1964 if (csr
& USB_CSR0_SETUPEND
) {
1965 DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__
, csr
);
1967 usb_setb(dev
, JZ_REG_UDC_CSR0
, USB_CSR0_SVDSETUPEND
);
1969 dev
->ep0state
= WAIT_FOR_SETUP
;
1973 * if USB_CSR0_OUTPKTRDY is set
1974 * - read data packet from EP0 FIFO
1977 * set SVDOUTPKTRDY | DATAEND | SENDSTALL bits
1979 * set SVDOUTPKTRDY | DATAEND bits
1981 if (csr
& USB_CSR0_OUTPKTRDY
) {
1983 DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__
,
1986 switch (dev
->ep0state
) {
1987 case WAIT_FOR_SETUP
:
1988 DEBUG_EP0("WAIT_FOR_SETUP\n");
1989 jz4740_ep0_setup(dev
, csr
);
1992 case DATA_STATE_RECV
:
1993 DEBUG_EP0("DATA_STATE_RECV\n");
1994 jz4740_ep0_out(dev
, csr
, 0);
1999 DEBUG_EP0("strange state!! 2. send stall? state = %d\n",
2006 static void jz4740_ep0_kick(struct jz4740_udc
*dev
, struct jz4740_ep
*ep
)
2010 jz_udc_set_index(dev
, 0);
2012 DEBUG_EP0("%s: %x\n", __FUNCTION__
, csr
);
2014 /* Clear "out packet ready" */
2017 usb_setb(dev
, JZ_REG_UDC_CSR0
, USB_CSR0_SVDOUTPKTRDY
);
2018 csr
= usb_readb(dev
, JZ_REG_UDC_CSR0
);
2019 dev
->ep0state
= DATA_STATE_XMIT
;
2020 jz4740_ep0_in(dev
, csr
);
2022 csr
= usb_readb(dev
, JZ_REG_UDC_CSR0
);
2023 dev
->ep0state
= DATA_STATE_RECV
;
2024 jz4740_ep0_out(dev
, csr
, 1);
2028 /** Handle USB RESET interrupt
2030 static void jz4740_reset_irq(struct jz4740_udc
*dev
)
2032 dev
->gadget
.speed
= (usb_readb(dev
, JZ_REG_UDC_POWER
) & USB_POWER_HSMODE
) ?
2033 USB_SPEED_HIGH
: USB_SPEED_FULL
;
2035 DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__
, dev
->usb_address
,
2036 (dev
->gadget
.speed
== USB_SPEED_HIGH
) ? "HIGH":"FULL" );
2040 * jz4740 usb device interrupt handler.
2042 static irqreturn_t
jz4740_udc_irq(int irq
, void *_dev
)
2044 struct jz4740_udc
*dev
= _dev
;
2047 uint32_t intr_usb
= usb_readb(dev
, JZ_REG_UDC_INTRUSB
) & 0x7; /* mask SOF */
2048 uint32_t intr_in
= usb_readw(dev
, JZ_REG_UDC_INTRIN
);
2049 uint32_t intr_out
= usb_readw(dev
, JZ_REG_UDC_INTROUT
);
2050 uint32_t intr_dma
= usb_readb(dev
, JZ_REG_UDC_INTR
);
2052 if (!intr_usb
&& !intr_in
&& !intr_out
&& !intr_dma
)
2056 DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n",
2057 intr_out
, intr_in
, intr_usb
);
2059 spin_lock(&dev
->lock
);
2060 index
= usb_readb(dev
, JZ_REG_UDC_INDEX
);
2062 /* Check for resume from suspend mode */
2063 if ((intr_usb
& USB_INTR_RESUME
) &&
2064 (usb_readb(dev
, JZ_REG_UDC_INTRUSBE
) & USB_INTR_RESUME
)) {
2065 DEBUG("USB resume\n");
2066 dev
->driver
->resume(&dev
->gadget
); /* We have suspend(), so we must have resume() too. */
2069 /* Check for system interrupts */
2070 if (intr_usb
& USB_INTR_RESET
) {
2071 DEBUG("USB reset\n");
2072 jz4740_reset_irq(dev
);
2075 /* Check for endpoint 0 interrupt */
2076 if (intr_in
& USB_INTR_EP0
) {
2077 DEBUG("USB_INTR_EP0 (control)\n");
2078 jz4740_handle_ep0(dev
, intr_in
);
2081 /* Check for Bulk-IN DMA interrupt */
2082 if (intr_dma
& 0x1) {
2084 struct jz4740_ep
*ep
;
2085 ep_num
= (usb_readl(dev
, JZ_REG_UDC_CNTL1
) >> 4) & 0xf;
2086 ep
= &dev
->ep
[ep_num
+ 1];
2087 jz_udc_set_index(dev
, ep_num
);
2088 usb_setb(dev
, ep
->csr
, USB_INCSR_INPKTRDY
);
2089 /* jz4740_in_epn(dev, ep_num, intr_in);*/
2092 /* Check for Bulk-OUT DMA interrupt */
2093 if (intr_dma
& 0x2) {
2095 ep_num
= (usb_readl(dev
, JZ_REG_UDC_CNTL2
) >> 4) & 0xf;
2096 jz4740_out_epn(dev
, ep_num
, intr_out
);
2099 /* Check for each configured endpoint interrupt */
2100 if (intr_in
& USB_INTR_INEP1
) {
2101 DEBUG("USB_INTR_INEP1\n");
2102 jz4740_in_epn(dev
, 1, intr_in
);
2105 if (intr_in
& USB_INTR_INEP2
) {
2106 DEBUG("USB_INTR_INEP2\n");
2107 jz4740_in_epn(dev
, 2, intr_in
);
2110 if (intr_out
& USB_INTR_OUTEP1
) {
2111 DEBUG("USB_INTR_OUTEP1\n");
2112 jz4740_out_epn(dev
, 1, intr_out
);
2115 /* Check for suspend mode */
2116 if ((intr_usb
& USB_INTR_SUSPEND
) &&
2117 (usb_readb(dev
, JZ_REG_UDC_INTRUSBE
) & USB_INTR_SUSPEND
)) {
2118 DEBUG("USB suspend\n");
2119 dev
->driver
->suspend(&dev
->gadget
);
2120 /* Host unloaded from us, can do something, such as flushing
2121 the NAND block cache etc. */
2124 jz_udc_set_index(dev
, index
);
2126 spin_unlock(&dev
->lock
);
2133 /*-------------------------------------------------------------------------*/
2135 /* Common functions - Added by River */
2136 static struct jz4740_udc udc_dev
;
2138 static inline struct jz4740_udc
*gadget_to_udc(struct usb_gadget
*gadget
)
2140 return container_of(gadget
, struct jz4740_udc
, gadget
);
2144 static int jz4740_udc_get_frame(struct usb_gadget
*_gadget
)
2146 DEBUG("%s, %p\n", __FUNCTION__
, _gadget
);
2147 return usb_readw(gadget_to_udc(_gadget
), JZ_REG_UDC_FRAME
);
2150 static int jz4740_udc_wakeup(struct usb_gadget
*_gadget
)
2152 /* host may not have enabled remote wakeup */
2153 /*if ((UDCCS0 & UDCCS0_DRWF) == 0)
2154 return -EHOSTUNREACH;
2155 udc_set_mask_UDCCR(UDCCR_RSM); */
2159 static int jz4740_udc_pullup(struct usb_gadget
*_gadget
, int on
)
2161 struct jz4740_udc
*udc
= gadget_to_udc(_gadget
);
2163 unsigned long flags
;
2165 local_irq_save(flags
);
2168 udc
->state
= UDC_STATE_ENABLE
;
2171 udc
->state
= UDC_STATE_DISABLE
;
2175 local_irq_restore(flags
);
2180 static const struct usb_gadget_ops jz4740_udc_ops
= {
2181 .get_frame
= jz4740_udc_get_frame
,
2182 .wakeup
= jz4740_udc_wakeup
,
2183 .pullup
= jz4740_udc_pullup
,
2184 /* current versions must always be self-powered */
2187 static struct usb_ep_ops jz4740_ep_ops
= {
2188 .enable
= jz4740_ep_enable
,
2189 .disable
= jz4740_ep_disable
,
2191 .alloc_request
= jz4740_alloc_request
,
2192 .free_request
= jz4740_free_request
,
2194 .queue
= jz4740_queue
,
2195 .dequeue
= jz4740_dequeue
,
2197 .set_halt
= jz4740_set_halt
,
2198 .fifo_status
= jz4740_fifo_status
,
2199 .fifo_flush
= jz4740_fifo_flush
,
2203 /*-------------------------------------------------------------------------*/
2205 static struct jz4740_udc udc_dev
= {
2208 .ops
= &jz4740_udc_ops
,
2209 .ep0
= &udc_dev
.ep
[0].ep
,
2212 .init_name
= "gadget",
2216 /* control endpoint */
2220 .ops
= &jz4740_ep_ops
,
2221 .maxpacket
= EP0_MAXPACKETSIZE
,
2225 .bEndpointAddress
= 0,
2229 .fifo
= JZ_REG_UDC_EP_FIFO(0),
2230 .csr
= JZ_REG_UDC_CSR0
,
2233 /* bulk out endpoint */
2236 .name
= "ep1out-bulk",
2237 .ops
= &jz4740_ep_ops
,
2238 .maxpacket
= EPBULK_MAXPACKETSIZE
,
2242 .bEndpointAddress
= 1,
2243 .bmAttributes
= USB_ENDPOINT_XFER_BULK
,
2245 .type
= ep_bulk_out
,
2246 .fifo
= JZ_REG_UDC_EP_FIFO(1),
2247 .csr
= JZ_REG_UDC_OUTCSR
,
2250 /* bulk in endpoint */
2253 .name
= "ep1in-bulk",
2254 .ops
= &jz4740_ep_ops
,
2255 .maxpacket
= EPBULK_MAXPACKETSIZE
,
2259 .bEndpointAddress
= 1 | USB_DIR_IN
,
2260 .bmAttributes
= USB_ENDPOINT_XFER_BULK
,
2263 .fifo
= JZ_REG_UDC_EP_FIFO(1),
2264 .csr
= JZ_REG_UDC_INCSR
,
2267 /* interrupt in endpoint */
2270 .name
= "ep2in-int",
2271 .ops
= &jz4740_ep_ops
,
2272 .maxpacket
= EPINTR_MAXPACKETSIZE
,
2276 .bEndpointAddress
= 2 | USB_DIR_IN
,
2277 .bmAttributes
= USB_ENDPOINT_XFER_INT
,
2279 .type
= ep_interrupt
,
2280 .fifo
= JZ_REG_UDC_EP_FIFO(2),
2281 .csr
= JZ_REG_UDC_INCSR
,
2285 static void gadget_release(struct device
*_dev
)
2290 static int jz4740_udc_probe(struct platform_device
*pdev
)
2292 struct jz4740_udc
*dev
= &udc_dev
;
2295 spin_lock_init(&dev
->lock
);
2296 the_controller
= dev
;
2298 dev
->dev
= &pdev
->dev
;
2299 dev_set_name(&dev
->gadget
.dev
, "gadget");
2300 dev
->gadget
.dev
.parent
= &pdev
->dev
;
2301 dev
->gadget
.dev
.dma_mask
= pdev
->dev
.dma_mask
;
2302 dev
->gadget
.dev
.release
= gadget_release
;
2304 ret
= device_register(&dev
->gadget
.dev
);
2308 platform_set_drvdata(pdev
, dev
);
2310 dev
->mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2314 dev_err(&pdev
->dev
, "Failed to get mmio memory resource\n");
2315 goto err_device_unregister
;
2318 dev
->mem
= request_mem_region(dev
->mem
->start
, resource_size(dev
->mem
), pdev
->name
);
2322 dev_err(&pdev
->dev
, "Failed to request mmio memory region\n");
2323 goto err_device_unregister
;
2326 dev
->base
= ioremap(dev
->mem
->start
, resource_size(dev
->mem
));
2330 dev_err(&pdev
->dev
, "Failed to ioremap mmio memory\n");
2331 goto err_release_mem_region
;
2334 dev
->irq
= platform_get_irq(pdev
, 0);
2336 ret
= request_irq(dev
->irq
, jz4740_udc_irq
, IRQF_DISABLED
,
2339 dev_err(&pdev
->dev
, "Failed to request irq: %d\n", ret
);
2350 err_release_mem_region
:
2351 release_mem_region(dev
->mem
->start
, resource_size(dev
->mem
));
2352 err_device_unregister
:
2353 device_unregister(&dev
->gadget
.dev
);
2354 platform_set_drvdata(pdev
, NULL
);
2361 static int jz4740_udc_remove(struct platform_device
*pdev
)
2363 struct jz4740_udc
*dev
= platform_get_drvdata(pdev
);
2369 #ifdef UDC_PROC_FILE
2370 remove_proc_entry(proc_node_name
, NULL
);
2373 free_irq(dev
->irq
, dev
);
2375 release_mem_region(dev
->mem
->start
, resource_size(dev
->mem
));
2377 platform_set_drvdata(pdev
, NULL
);
2378 device_unregister(&dev
->gadget
.dev
);
2379 the_controller
= NULL
;
2384 static struct platform_driver udc_driver
= {
2385 .probe
= jz4740_udc_probe
,
2386 .remove
= jz4740_udc_remove
,
2389 .owner
= THIS_MODULE
,
2393 /*-------------------------------------------------------------------------*/
2395 static int __init
udc_init (void)
2397 return platform_driver_register(&udc_driver
);
2400 static void __exit
udc_exit (void)
2402 platform_driver_unregister(&udc_driver
);
2405 module_init(udc_init
);
2406 module_exit(udc_exit
);
2408 MODULE_DESCRIPTION("JZ4740 USB Device Controller");
2409 MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>");
2410 MODULE_LICENSE("GPL");