1 --- a/drivers/net/ethernet/broadcom/tg3.c
2 +++ b/drivers/net/ethernet/broadcom/tg3.c
4 #include <linux/prefetch.h>
5 #include <linux/dma-mapping.h>
6 #include <linux/firmware.h>
7 +#include <linux/ssb/ssb_driver_gige.h>
9 #include <net/checksum.h>
11 @@ -530,7 +531,8 @@ static void _tw32_flush(struct tg3 *tp,
12 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
14 tp->write32_mbox(tp, off, val);
15 - if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
16 + if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
17 + (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND)))
18 tp->read32_mbox(tp, off);
21 @@ -540,7 +542,7 @@ static void tg3_write32_tx_mbox(struct t
23 if (tg3_flag(tp, TXD_MBOX_HWBUG))
25 - if (tg3_flag(tp, MBOX_WRITE_REORDER))
26 + if (tg3_flag(tp, MBOX_WRITE_REORDER) || tg3_flag(tp, FLUSH_POSTED_WRITES))
30 @@ -943,7 +945,7 @@ static void tg3_switch_clocks(struct tg3
32 #define PHY_BUSY_LOOPS 5000
34 -static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
35 +static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val)
39 @@ -957,7 +959,7 @@ static int tg3_readphy(struct tg3 *tp, i
43 - frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
44 + frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
45 MI_COM_PHY_ADDR_MASK);
46 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
47 MI_COM_REG_ADDR_MASK);
48 @@ -992,7 +994,12 @@ static int tg3_readphy(struct tg3 *tp, i
52 -static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
53 +static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
55 + return __tg3_readphy(tp, tp->phy_addr, reg, val);
58 +static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val)
62 @@ -1008,7 +1015,7 @@ static int tg3_writephy(struct tg3 *tp,
66 - frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
67 + frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
68 MI_COM_PHY_ADDR_MASK);
69 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
70 MI_COM_REG_ADDR_MASK);
71 @@ -1041,6 +1048,11 @@ static int tg3_writephy(struct tg3 *tp,
75 +static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
77 + return __tg3_writephy(tp, tp->phy_addr, reg, val);
80 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
83 @@ -2963,6 +2975,9 @@ static int tg3_nvram_read(struct tg3 *tp
87 + if (tg3_flag(tp, IS_SSB_CORE))
90 if (!tg3_flag(tp, NVRAM))
91 return tg3_nvram_read_using_eeprom(tp, offset, val);
93 @@ -3045,9 +3060,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
97 - /* Clear firmware's nvram arbitration. */
98 - if (tg3_flag(tp, NVRAM))
99 - tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
100 + if (!tg3_flag(tp, IS_SSB_CORE)) {
101 + /* Clear firmware's nvram arbitration. */
102 + if (tg3_flag(tp, NVRAM))
103 + tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
109 @@ -3166,6 +3184,11 @@ static int tg3_load_tso_firmware(struct
110 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
113 + if (tg3_flag(tp, IS_SSB_CORE)) {
114 + /* We don't use firmware. */
118 if (tg3_flag(tp, HW_TSO_1) ||
119 tg3_flag(tp, HW_TSO_2) ||
120 tg3_flag(tp, HW_TSO_3))
121 @@ -3512,8 +3535,10 @@ static int tg3_power_down_prepare(struct
122 tg3_frob_aux_power(tp, true);
124 /* Workaround for unstable PLL clock */
125 - if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
126 - (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
127 + if ((tp->phy_id & TG3_PHY_ID_MASK) != TG3_PHY_ID_BCM5750_2 &&
128 + /* !!! FIXME !!! */
129 + ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
130 + (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
131 u32 val = tr32(0x7d00);
133 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
134 @@ -4041,6 +4066,14 @@ relink:
135 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
136 tg3_phy_copper_begin(tp);
138 + if (tg3_flag(tp, ROBOSWITCH)) {
139 + current_link_up = 1;
140 + current_speed = SPEED_1000; /* FIXME */
141 + current_duplex = DUPLEX_FULL;
142 + tp->link_config.active_speed = current_speed;
143 + tp->link_config.active_duplex = current_duplex;
146 tg3_readphy(tp, MII_BMSR, &bmsr);
147 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
148 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
149 @@ -7747,6 +7780,11 @@ static int tg3_chip_reset(struct tg3 *tp
153 + if (tg3_flag(tp, IS_SSB_CORE)) {
154 + /* We don't use firmware. */
158 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
159 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
160 tw32(GRC_VCPU_EXT_CTRL,
161 @@ -7845,6 +7883,14 @@ static int tg3_chip_reset(struct tg3 *tp
165 + if (tg3_flag(tp, IS_SSB_CORE)) {
166 + /* BCM4785: In order to avoid repercussions from using potentially
167 + * defective internal ROM, stop the Rx RISC CPU, which is not
170 + tg3_halt_cpu(tp, RX_CPU_BASE);
173 tw32(GRC_MODE, tp->grc_mode);
175 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
176 @@ -9220,6 +9266,11 @@ static void tg3_timer(unsigned long __op
177 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
178 tg3_chk_missed_msi(tp);
180 + if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
181 + /* BCM4785: Flush posted writes from GbE to host memory. */
185 if (!tg3_flag(tp, TAGGED_STATUS)) {
186 /* All of this garbage is because when using non-tagged
187 * IRQ status the mailbox/status_block protocol the chip
188 @@ -9509,6 +9560,11 @@ static int tg3_request_firmware(struct t
192 + if (tg3_flag(tp, IS_SSB_CORE)) {
193 + /* We don't use firmware. */
197 fw_data = (void *)tp->fw->data;
199 /* Firmware blob starts with version numbers, followed by
200 @@ -10867,6 +10923,11 @@ static int tg3_test_nvram(struct tg3 *tp
201 if (tg3_flag(tp, NO_NVRAM))
204 + if (tg3_flag(tp, IS_SSB_CORE)) {
205 + /* We don't have NVRAM. */
209 if (tg3_nvram_read(tp, 0, &magic) != 0)
212 @@ -11827,7 +11888,7 @@ static int tg3_ioctl(struct net_device *
215 spin_lock_bh(&tp->lock);
216 - err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
217 + err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
218 spin_unlock_bh(&tp->lock);
220 data->val_out = mii_regval;
221 @@ -11843,7 +11904,7 @@ static int tg3_ioctl(struct net_device *
224 spin_lock_bh(&tp->lock);
225 - err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
226 + err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
227 spin_unlock_bh(&tp->lock);
230 @@ -12573,6 +12634,13 @@ static void __devinit tg3_get_5720_nvram
231 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
232 static void __devinit tg3_nvram_init(struct tg3 *tp)
234 + if (tg3_flag(tp, IS_SSB_CORE)) {
235 + /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
236 + tg3_flag_clear(tp, NVRAM);
237 + tg3_flag_clear(tp, NVRAM_BUFFERED);
241 tw32_f(GRC_EEPROM_ADDR,
242 (EEPROM_ADDR_FSM_RESET |
243 (EEPROM_DEFAULT_CLOCK_PERIOD <<
244 @@ -12839,6 +12907,9 @@ static int tg3_nvram_write_block(struct
248 + if (tg3_flag(tp, IS_SSB_CORE))
251 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
252 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
253 ~GRC_LCLCTRL_GPIO_OUTPUT1);
254 @@ -14263,6 +14334,11 @@ static int __devinit tg3_get_invariants(
258 + if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
259 + tp->write32_tx_mbox = tg3_write_flush_reg32;
260 + tp->write32_rx_mbox = tg3_write_flush_reg32;
263 /* Get eeprom hw config before calling tg3_set_power_state().
264 * In particular, the TG3_FLAG_IS_NIC flag must be
265 * determined before calling tg3_set_power_state() so that
266 @@ -14673,6 +14749,8 @@ static int __devinit tg3_get_device_addr
269 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
270 + if (tg3_flag(tp, IS_SSB_CORE))
271 + ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
273 if (!tg3_get_default_macaddr_sparc(tp))
275 @@ -15171,6 +15249,7 @@ static char * __devinit tg3_phy_string(s
276 case TG3_PHY_ID_BCM5704: return "5704";
277 case TG3_PHY_ID_BCM5705: return "5705";
278 case TG3_PHY_ID_BCM5750: return "5750";
279 + case TG3_PHY_ID_BCM5750_2: return "5750-2";
280 case TG3_PHY_ID_BCM5752: return "5752";
281 case TG3_PHY_ID_BCM5714: return "5714";
282 case TG3_PHY_ID_BCM5780: return "5780";
283 @@ -15366,6 +15445,13 @@ static int __devinit tg3_init_one(struct
284 tp->msg_enable = tg3_debug;
286 tp->msg_enable = TG3_DEF_MSG_ENABLE;
287 + if (pdev_is_ssb_gige_core(pdev)) {
288 + tg3_flag_set(tp, IS_SSB_CORE);
289 + if (ssb_gige_must_flush_posted_writes(pdev))
290 + tg3_flag_set(tp, FLUSH_POSTED_WRITES);
291 + if (ssb_gige_have_roboswitch(pdev))
292 + tg3_flag_set(tp, ROBOSWITCH);
295 /* The word/byte swap controls here control register access byte
296 * swapping. DMA data byte swapping is controlled in the GRC_MODE
297 --- a/drivers/net/ethernet/broadcom/tg3.h
298 +++ b/drivers/net/ethernet/broadcom/tg3.h
299 @@ -2922,6 +2922,9 @@ enum TG3_FLAGS {
301 TG3_FLAG_4K_FIFO_LIMIT,
302 TG3_FLAG_RESET_TASK_PENDING,
303 + TG3_FLAG_IS_SSB_CORE,
304 + TG3_FLAG_FLUSH_POSTED_WRITES,
305 + TG3_FLAG_ROBOSWITCH,
307 /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
308 TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */
309 @@ -3071,6 +3074,7 @@ struct tg3 {
310 #define TG3_PHY_ID_BCM5704 0x60008190
311 #define TG3_PHY_ID_BCM5705 0x600081a0
312 #define TG3_PHY_ID_BCM5750 0x60008180
313 +#define TG3_PHY_ID_BCM5750_2 0xbc050cd0
314 #define TG3_PHY_ID_BCM5752 0x60008100
315 #define TG3_PHY_ID_BCM5714 0x60008340
316 #define TG3_PHY_ID_BCM5780 0x60008350
317 @@ -3108,7 +3112,7 @@ struct tg3 {
318 (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
319 (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
320 (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
321 - (X) == TG3_PHY_ID_BCM8002)
322 + (X) == TG3_PHY_ID_BCM8002 || (X) == TG3_PHY_ID_BCM5750_2)
325 #define TG3_PHYFLG_IS_LOW_POWER 0x00000001