target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c

   1 /*
   2  *  Atheros AR724x PCI host controller driver
   3  *
   4  *  Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  *  Parts of this file are based on Atheros' 2.6.15 BSP
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License version 2 as published
  10  *  by the Free Software Foundation.
  11  */
  12
  13 #include <linux/resource.h>
  14 #include <linux/types.h>
  15 #include <linux/delay.h>
  16 #include <linux/bitops.h>
  17 #include <linux/pci.h>
  18 #include <linux/pci_regs.h>
  19 #include <linux/interrupt.h>
  20
  21 #include <asm/mach-ar71xx/ar71xx.h>
  22 #include <asm/mach-ar71xx/pci.h>
  23
  24 #undef DEBUG
  25 #ifdef DEBUG
  26 #define DBG(fmt, args...)       printk(KERN_INFO fmt, ## args)
  27 #else
  28 #define DBG(fmt, args...)
  29 #endif
  30
  31 static void __iomem *ar724x_pci_localcfg_base;
  32 static void __iomem *ar724x_pci_devcfg_base;
  33 static int ar724x_pci_fixup_enable;
  34
  35 static DEFINE_SPINLOCK(ar724x_pci_lock);
  36
  37 static inline void ar724x_pci_wr(unsigned reg, u32 val)
  38 {
  39         void __iomem *base;
  40
  41         base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
  42         __raw_writel(val, base + reg);
  43         (void) __raw_readl(base + reg);
  44         iounmap(base);
  45 }
  46
  47 static inline void ar724x_pci_wr_nf(unsigned reg, u32 val)
  48 {
  49         void __iomem *base;
  50
  51         base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
  52         __raw_writel(val, base + reg);
  53         iounmap(base);
  54 }
  55
  56 static inline u32 ar724x_pci_rr(unsigned reg)
  57 {
  58         void __iomem *base;
  59         u32 ret;
  60
  61         base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
  62         ret = __raw_readl(base + reg);
  63         iounmap(base);
  64         return ret;
  65 }
  66
  67 static void ar724x_pci_read(void __iomem *base, int where, int size, u32 *value)
  68 {
  69         unsigned long flags;
  70         u32 data;
  71
  72         spin_lock_irqsave(&ar724x_pci_lock, flags);
  73         data = __raw_readl(base + (where & ~3));
  74
  75         switch (size) {
  76         case 1:
  77                 if (where & 1)
  78                         data >>= 8;
  79                 if (where & 2)
  80                         data >>= 16;
  81                 data &= 0xFF;
  82                 break;
  83         case 2:
  84                 if (where & 2)
  85                         data >>= 16;
  86                 data &= 0xFFFF;
  87                 break;
  88         }
  89
  90         *value = data;
  91         spin_unlock_irqrestore(&ar724x_pci_lock, flags);
  92 }
  93
  94 static void ar724x_pci_write(void __iomem *base, int where, int size, u32 value)
  95 {
  96         unsigned long flags;
  97         u32 data;
  98         int s;
  99
 100         spin_lock_irqsave(&ar724x_pci_lock, flags);
 101         data = __raw_readl(base + (where & ~3));
 102
 103         switch (size) {
 104         case 1:
 105                 s = ((where & 3) << 3);
 106                 data &= ~(0xFF << s);
 107                 data |= ((value & 0xFF) << s);
 108                 break;
 109         case 2:
 110                 s = ((where & 2) << 3);
 111                 data &= ~(0xFFFF << s);
 112                 data |= ((value & 0xFFFF) << s);
 113                 break;
 114         case 4:
 115                 data = value;
 116                 break;
 117         }
 118
 119         __raw_writel(data, base + (where & ~3));
 120         /* flush write */
 121         (void)__raw_readl(base + (where & ~3));
 122         spin_unlock_irqrestore(&ar724x_pci_lock, flags);
 123 }
 124
 125 static int ar724x_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 126                                   int where, int size, u32 *value)
 127 {
 128
 129         if (bus->number != 0 || devfn != 0)
 130                 return PCIBIOS_DEVICE_NOT_FOUND;
 131
 132         ar724x_pci_read(ar724x_pci_devcfg_base, where, size, value);
 133
 134         DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
 135                         bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
 136                         where, size, *value);
 137
 138         /*
 139          * WAR for BAR issue - We are unable to access the PCI device space
 140          * if we set the BAR with proper base address
 141          */
 142         if ((where == 0x10) && (size == 4))
 143                 ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0xffff);
 144
 145         return PCIBIOS_SUCCESSFUL;
 146 }
 147
 148 static int ar724x_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 149                                    int where, int size, u32 value)
 150 {
 151         if (bus->number != 0 || devfn != 0)
 152                 return PCIBIOS_DEVICE_NOT_FOUND;
 153
 154         DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
 155                 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
 156                 where, size, value);
 157
 158         ar724x_pci_write(ar724x_pci_devcfg_base, where, size, value);
 159
 160         return PCIBIOS_SUCCESSFUL;
 161 }
 162
 163 static void ar724x_pci_fixup(struct pci_dev *dev)
 164 {
 165         u16 cmd;
 166
 167         if (!ar724x_pci_fixup_enable)
 168                 return;
 169
 170         if (dev->bus->number != 0 || dev->devfn != 0)
 171                 return;
 172
 173         /* setup COMMAND register */
 174         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 175         cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
 176                PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
 177                PCI_COMMAND_FAST_BACK;
 178
 179         pci_write_config_word(dev, PCI_COMMAND, cmd);
 180 }
 181 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar724x_pci_fixup);
 182
 183 int __init ar724x_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
 184                                   uint8_t pin)
 185 {
 186         int irq = -1;
 187         int i;
 188
 189         for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
 190                 struct ar71xx_pci_irq *entry;
 191                 entry = &ar71xx_pci_irq_map[i];
 192
 193                 if (entry->slot == slot && entry->pin == pin) {
 194                         irq = entry->irq;
 195                         break;
 196                 }
 197         }
 198
 199         if (irq < 0)
 200                 printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
 201                                 pin, pci_name((struct pci_dev *)dev));
 202         else
 203                 printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
 204                                 irq, pin, pci_name((struct pci_dev *)dev));
 205
 206         return irq;
 207 }
 208
 209 static struct pci_ops ar724x_pci_ops = {
 210         .read   = ar724x_pci_read_config,
 211         .write  = ar724x_pci_write_config,
 212 };
 213
 214 static struct resource ar724x_pci_io_resource = {
 215         .name           = "PCI IO space",
 216         .start          = 0,
 217         .end            = 0,
 218         .flags          = IORESOURCE_IO,
 219 };
 220
 221 static struct resource ar724x_pci_mem_resource = {
 222         .name           = "PCI memory space",
 223         .start          = AR71XX_PCI_MEM_BASE,
 224         .end            = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
 225         .flags          = IORESOURCE_MEM
 226 };
 227
 228 static struct pci_controller ar724x_pci_controller = {
 229         .pci_ops        = &ar724x_pci_ops,
 230         .mem_resource   = &ar724x_pci_mem_resource,
 231         .io_resource    = &ar724x_pci_io_resource,
 232 };
 233
 234 static void __init ar724x_pci_reset(void)
 235 {
 236         ar71xx_device_stop(AR724X_RESET_PCIE);
 237         ar71xx_device_stop(AR724X_RESET_PCIE_PHY);
 238         ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL);
 239         udelay(100);
 240
 241         ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL);
 242         udelay(100);
 243         ar71xx_device_start(AR724X_RESET_PCIE_PHY);
 244         ar71xx_device_start(AR724X_RESET_PCIE);
 245 }
 246
 247 static int __init ar724x_pci_setup(void)
 248 {
 249         u32 t;
 250
 251         /* setup COMMAND register */
 252         t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
 253             PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;
 254
 255         ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t);
 256         ar724x_pci_write(ar724x_pci_localcfg_base, 0x20, 4, 0x1ff01000);
 257         ar724x_pci_write(ar724x_pci_localcfg_base, 0x24, 4, 0x1ff01000);
 258
 259         t = ar724x_pci_rr(AR724X_PCI_REG_RESET);
 260         if (t != 0x7) {
 261                 udelay(100000);
 262                 ar724x_pci_wr_nf(AR724X_PCI_REG_RESET, 0);
 263                 udelay(100);
 264                 ar724x_pci_wr_nf(AR724X_PCI_REG_RESET, 4);
 265                 udelay(100000);
 266         }
 267
 268         ar724x_pci_wr(AR724X_PCI_REG_APP, AR724X_PCI_APP_LTSSM_ENABLE);
 269         udelay(1000);
 270
 271         t = ar724x_pci_rr(AR724X_PCI_REG_APP);
 272         if ((t & AR724X_PCI_APP_LTSSM_ENABLE) == 0x0) {
 273                 printk(KERN_WARNING "PCI: no PCIe module found\n");
 274                 return -ENODEV;
 275         }
 276
 277         return 0;
 278 }
 279
 280 static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
 281 {
 282         u32 pending;
 283
 284         pending = ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) &
 285                   ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
 286
 287         if (pending & AR724X_PCI_INT_DEV0)
 288                 generic_handle_irq(AR71XX_PCI_IRQ_DEV0);
 289
 290         else
 291                 spurious_interrupt();
 292 }
 293
 294 static void ar724x_pci_irq_unmask(unsigned int irq)
 295 {
 296         switch (irq) {
 297         case AR71XX_PCI_IRQ_DEV0:
 298                 irq -= AR71XX_PCI_IRQ_BASE;
 299                 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
 300                               ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) |
 301                                             AR724X_PCI_INT_DEV0);
 302                 /* flush write */
 303                 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
 304         }
 305 }
 306
 307 static void ar724x_pci_irq_mask(unsigned int irq)
 308 {
 309         switch (irq) {
 310         case AR71XX_PCI_IRQ_DEV0:
 311                 irq -= AR71XX_PCI_IRQ_BASE;
 312                 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
 313                               ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) &
 314                                             ~AR724X_PCI_INT_DEV0);
 315                 /* flush write */
 316                 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
 317
 318                 ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS,
 319                               ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) |
 320                                             AR724X_PCI_INT_DEV0);
 321                 /* flush write */
 322                 ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS);
 323         }
 324 }
 325
 326 static struct irq_chip ar724x_pci_irq_chip = {
 327         .name           = "AR724X PCI ",
 328         .mask           = ar724x_pci_irq_mask,
 329         .unmask         = ar724x_pci_irq_unmask,
 330         .mask_ack       = ar724x_pci_irq_mask,
 331 };
 332
 333 static void __init ar724x_pci_irq_init(void)
 334 {
 335         u32 t;
 336         int i;
 337
 338         t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
 339         if (t & (AR724X_RESET_PCIE | AR724X_RESET_PCIE_PHY |
 340                  AR724X_RESET_PCIE_PHY_SERIAL)) {
 341                 return;
 342         }
 343
 344         ar724x_pci_wr(AR724X_PCI_REG_INT_MASK, 0);
 345         ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS, 0);
 346
 347         for (i = AR71XX_PCI_IRQ_BASE;
 348              i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
 349                 irq_desc[i].status = IRQ_DISABLED;
 350                 set_irq_chip_and_handler(i, &ar724x_pci_irq_chip,
 351                                          handle_level_irq);
 352         }
 353
 354         set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar724x_pci_irq_handler);
 355 }
 356
 357 int __init ar724x_pcibios_init(void)
 358 {
 359         int ret;
 360
 361         ar724x_pci_localcfg_base = ioremap_nocache(AR724X_PCI_CRP_BASE,
 362                                                    AR724X_PCI_CRP_SIZE);
 363
 364         ar724x_pci_devcfg_base = ioremap_nocache(AR724X_PCI_CFG_BASE,
 365                                                  AR724X_PCI_CFG_SIZE);
 366
 367         ar724x_pci_reset();
 368         ret = ar724x_pci_setup();
 369         if (ret)
 370                 return ret;
 371
 372         ar724x_pci_fixup_enable = 1;
 373         ar724x_pci_irq_init();
 374         register_pci_controller(&ar724x_pci_controller);
 375
 376         return 0;
 377 }