[ar71xx] experimental support for the Planex MZK-W04NU board
[openwrt.git] / target / linux / generic-2.6 / patches-2.6.23 / 301-mmc_sdhci_fixes.patch
1 --- a/drivers/mmc/host/sdhci.c
2 +++ b/drivers/mmc/host/sdhci.c
3 @@ -481,16 +481,16 @@
4 * Controller doesn't count down when in single block mode.
5 */
6 if (data->blocks == 1)
7 - blocks = (data->error == MMC_ERR_NONE) ? 0 : 1;
8 + blocks = (data->error == 0) ? 0 : 1;
9 else
10 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
11 data->bytes_xfered = data->blksz * (data->blocks - blocks);
12
13 - if ((data->error == MMC_ERR_NONE) && blocks) {
14 + if (!data->error && blocks) {
15 printk(KERN_ERR "%s: Controller signalled completion even "
16 "though there were blocks left.\n",
17 mmc_hostname(host->mmc));
18 - data->error = MMC_ERR_FAILED;
19 + data->error = -EIO;
20 }
21
22 if (data->stop) {
23 @@ -498,7 +498,7 @@
24 * The controller needs a reset of internal state machines
25 * upon error conditions.
26 */
27 - if (data->error != MMC_ERR_NONE) {
28 + if (data->error) {
29 sdhci_reset(host, SDHCI_RESET_CMD);
30 sdhci_reset(host, SDHCI_RESET_DATA);
31 }
32 @@ -533,7 +533,7 @@
33 printk(KERN_ERR "%s: Controller never released "
34 "inhibit bit(s).\n", mmc_hostname(host->mmc));
35 sdhci_dumpregs(host);
36 - cmd->error = MMC_ERR_FAILED;
37 + cmd->error = -EIO;
38 tasklet_schedule(&host->finish_tasklet);
39 return;
40 }
41 @@ -554,7 +554,7 @@
42 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
43 printk(KERN_ERR "%s: Unsupported response type!\n",
44 mmc_hostname(host->mmc));
45 - cmd->error = MMC_ERR_INVALID;
46 + cmd->error = -EINVAL;
47 tasklet_schedule(&host->finish_tasklet);
48 return;
49 }
50 @@ -601,7 +601,7 @@
51 }
52 }
53
54 - host->cmd->error = MMC_ERR_NONE;
55 + host->cmd->error = 0;
56
57 if (host->data && host->data_early)
58 sdhci_finish_data(host);
59 @@ -722,7 +722,7 @@
60 host->mrq = mrq;
61
62 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
63 - host->mrq->cmd->error = MMC_ERR_TIMEOUT;
64 + host->mrq->cmd->error = -ENOMEDIUM;
65 tasklet_schedule(&host->finish_tasklet);
66 } else
67 sdhci_send_command(host, mrq->cmd);
68 @@ -831,7 +831,7 @@
69 sdhci_reset(host, SDHCI_RESET_CMD);
70 sdhci_reset(host, SDHCI_RESET_DATA);
71
72 - host->mrq->cmd->error = MMC_ERR_FAILED;
73 + host->mrq->cmd->error = -ENOMEDIUM;
74 tasklet_schedule(&host->finish_tasklet);
75 }
76 }
77 @@ -859,9 +859,9 @@
78 * The controller needs a reset of internal state machines
79 * upon error conditions.
80 */
81 - if ((mrq->cmd->error != MMC_ERR_NONE) ||
82 - (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
83 - (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
84 + if (mrq->cmd->error ||
85 + (mrq->data && (mrq->data->error ||
86 + (mrq->data->stop && mrq->data->stop->error)))) {
87
88 /* Some controllers need this kick or reset won't work here */
89 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
90 @@ -906,13 +906,13 @@
91 sdhci_dumpregs(host);
92
93 if (host->data) {
94 - host->data->error = MMC_ERR_TIMEOUT;
95 + host->data->error = -ETIMEDOUT;
96 sdhci_finish_data(host);
97 } else {
98 if (host->cmd)
99 - host->cmd->error = MMC_ERR_TIMEOUT;
100 + host->cmd->error = -ETIMEDOUT;
101 else
102 - host->mrq->cmd->error = MMC_ERR_TIMEOUT;
103 + host->mrq->cmd->error = -ETIMEDOUT;
104
105 tasklet_schedule(&host->finish_tasklet);
106 }
107 @@ -941,13 +941,12 @@
108 }
109
110 if (intmask & SDHCI_INT_TIMEOUT)
111 - host->cmd->error = MMC_ERR_TIMEOUT;
112 - else if (intmask & SDHCI_INT_CRC)
113 - host->cmd->error = MMC_ERR_BADCRC;
114 - else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
115 - host->cmd->error = MMC_ERR_FAILED;
116 + host->cmd->error = -ETIMEDOUT;
117 + else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
118 + SDHCI_INT_INDEX))
119 + host->cmd->error = -EILSEQ;
120
121 - if (host->cmd->error != MMC_ERR_NONE)
122 + if (host->cmd->error)
123 tasklet_schedule(&host->finish_tasklet);
124 else if (intmask & SDHCI_INT_RESPONSE)
125 sdhci_finish_command(host);
126 @@ -974,13 +973,11 @@
127 }
128
129 if (intmask & SDHCI_INT_DATA_TIMEOUT)
130 - host->data->error = MMC_ERR_TIMEOUT;
131 - else if (intmask & SDHCI_INT_DATA_CRC)
132 - host->data->error = MMC_ERR_BADCRC;
133 - else if (intmask & SDHCI_INT_DATA_END_BIT)
134 - host->data->error = MMC_ERR_FAILED;
135 + host->data->error = -ETIMEDOUT;
136 + else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
137 + host->data->error = -EILSEQ;
138
139 - if (host->data->error != MMC_ERR_NONE)
140 + if (host->data->error)
141 sdhci_finish_data(host);
142 else {
143 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
144 @@ -1312,7 +1309,7 @@
145 mmc->ops = &sdhci_ops;
146 mmc->f_min = host->max_clk / 256;
147 mmc->f_max = host->max_clk;
148 - mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
149 + mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE;
150
151 if (caps & SDHCI_CAN_DO_HISPD)
152 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
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