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patch madwifi-ng to use master mode by default
[openwrt.git] / openwrt / target / linux / aruba-2.6 / patches / 000-aruba.patch
1 diff -Nur linux-2.6.15/arch/mips/aruba/Makefile linux-2.6.15-openwrt/arch/mips/aruba/Makefile
2 --- linux-2.6.15/arch/mips/aruba/Makefile 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.15-openwrt/arch/mips/aruba/Makefile 2006-01-10 00:32:32.000000000 +0100
4 @@ -0,0 +1,49 @@
5 +###############################################################################
6 +#
7 +# BRIEF MODULE DESCRIPTION
8 +# Makefile for IDT EB434 BSP
9 +#
10 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
11 +#
12 +# This program is free software; you can redistribute it and/or modify it
13 +# under the terms of the GNU General Public License as published by the
14 +# Free Software Foundation; either version 2 of the License, or (at your
15 +# option) any later version.
16 +#
17 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 +#
28 +# You should have received a copy of the GNU General Public License along
29 +# with this program; if not, write to the Free Software Foundation, Inc.,
30 +# 675 Mass Ave, Cambridge, MA 02139, USA.
31 +#
32 +#
33 +###############################################################################
34 +# May 2004 rkt, neb
35 +#
36 +# Initial Release
37 +#
38 +#
39 +#
40 +###############################################################################
41 +
42 +
43 +# .S.s:
44 +# $(CPP) $(CFLAGS) $< -o $*.s
45 +# .S.o:
46 +# $(CC) $(CFLAGS) -c $< -o $*.o
47 +
48 +obj-y := prom.o setup.o idtIRQ.o irq.o time.o flash_lock.o wdt_merlot.o
49 +obj-$(CONFIG_SERIAL_8250) += serial.o
50 +
51 +subdir-y += nvram
52 +obj-y += nvram/built-in.o
53 +
54 diff -Nur linux-2.6.15/arch/mips/aruba/nvram/Makefile linux-2.6.15-openwrt/arch/mips/aruba/nvram/Makefile
55 --- linux-2.6.15/arch/mips/aruba/nvram/Makefile 1970-01-01 01:00:00.000000000 +0100
56 +++ linux-2.6.15-openwrt/arch/mips/aruba/nvram/Makefile 2006-01-10 00:32:32.000000000 +0100
57 @@ -0,0 +1,46 @@
58 +###############################################################################
59 +#
60 +# BRIEF MODULE DESCRIPTION
61 +# Makefile for IDT EB434 nvram access routines
62 +#
63 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
64 +#
65 +# This program is free software; you can redistribute it and/or modify it
66 +# under the terms of the GNU General Public License as published by the
67 +# Free Software Foundation; either version 2 of the License, or (at your
68 +# option) any later version.
69 +#
70 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
71 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
72 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
73 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
74 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
75 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
76 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
77 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
80 +#
81 +# You should have received a copy of the GNU General Public License along
82 +# with this program; if not, write to the Free Software Foundation, Inc.,
83 +# 675 Mass Ave, Cambridge, MA 02139, USA.
84 +#
85 +#
86 +###############################################################################
87 +# May 2004 rkt, neb
88 +#
89 +# Initial Release
90 +#
91 +#
92 +#
93 +###############################################################################
94 +
95 +obj-y := nvram434.o
96 +obj-m := $(O_TARGET)
97 +
98 +
99 +
100 +
101 +
102 +
103 +
104 diff -Nur linux-2.6.15/arch/mips/aruba/nvram/nvram434.c linux-2.6.15-openwrt/arch/mips/aruba/nvram/nvram434.c
105 --- linux-2.6.15/arch/mips/aruba/nvram/nvram434.c 1970-01-01 01:00:00.000000000 +0100
106 +++ linux-2.6.15-openwrt/arch/mips/aruba/nvram/nvram434.c 2006-01-10 00:32:32.000000000 +0100
107 @@ -0,0 +1,392 @@
108 +/**************************************************************************
109 + *
110 + * BRIEF MODULE DESCRIPTION
111 + * nvram interface routines.
112 + *
113 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
114 + *
115 + * This program is free software; you can redistribute it and/or modify it
116 + * under the terms of the GNU General Public License as published by the
117 + * Free Software Foundation; either version 2 of the License, or (at your
118 + * option) any later version.
119 + *
120 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
121 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
122 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
123 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
124 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
125 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
126 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
127 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
128 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
129 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
130 + *
131 + * You should have received a copy of the GNU General Public License along
132 + * with this program; if not, write to the Free Software Foundation, Inc.,
133 + * 675 Mass Ave, Cambridge, MA 02139, USA.
134 + *
135 + *
136 + **************************************************************************
137 + * May 2004 rkt, neb
138 + *
139 + * Initial Release
140 + *
141 + *
142 + *
143 + **************************************************************************
144 + */
145 +
146 +#include <linux/ctype.h>
147 +#include <linux/string.h>
148 +
149 +//#include <asm/ds1553rtc.h>
150 +#include "nvram434.h"
151 +#define NVRAM_BASE 0xbfff8000
152 +
153 +extern void setenv (char *e, char *v, int rewrite);
154 +extern void unsetenv (char *e);
155 +extern void mapenv (int (*func)(char *, char *));
156 +extern char *getenv (char *s);
157 +extern void purgeenv(void);
158 +
159 +static void nvram_initenv(void);
160 +
161 +static unsigned char
162 +nvram_getbyte(int offs)
163 +{
164 + return(*((unsigned char*)(NVRAM_BASE + offs)));
165 +}
166 +
167 +static void
168 +nvram_setbyte(int offs, unsigned char val)
169 +{
170 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
171 +
172 + *nvramDataPointer = val;
173 +}
174 +
175 +/*
176 + * BigEndian!
177 + */
178 +static unsigned short
179 +nvram_getshort(int offs)
180 +{
181 + return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
182 +}
183 +
184 +static void
185 +nvram_setshort(int offs, unsigned short val)
186 +{
187 + nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
188 + nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
189 +}
190 +#if 0
191 +static unsigned int
192 +nvram_getint(int offs)
193 +{
194 + unsigned int val;
195 + val = nvram_getbyte(offs) << 24;
196 + val |= nvram_getbyte(offs + 1) << 16;
197 + val |= nvram_getbyte(offs + 2) << 8;
198 + val |= nvram_getbyte(offs + 3);
199 + return(val);
200 +}
201 +
202 +static void
203 +nvram_setint(int offs, unsigned int val)
204 +{
205 + nvram_setbyte(offs, val >> 24);
206 + nvram_setbyte(offs + 1, val >> 16);
207 + nvram_setbyte(offs + 2, val >> 8);
208 + nvram_setbyte(offs + 3, val);
209 +}
210 +#endif
211 +/*
212 + * calculate NVRAM checksum
213 + */
214 +static unsigned short
215 +nvram_calcsum(void)
216 +{
217 + unsigned short sum = NV_MAGIC;
218 + int i;
219 +
220 + for (i = ENV_BASE; i < ENV_TOP; i += 2)
221 + sum += nvram_getshort(i);
222 + return(sum);
223 +}
224 +
225 +/*
226 + * update the nvram checksum
227 + */
228 +static void
229 +nvram_updatesum (void)
230 +{
231 + nvram_setshort(NVOFF_CSUM, nvram_calcsum());
232 +}
233 +
234 +/*
235 + * test validity of nvram by checksumming it
236 + */
237 +static int
238 +nvram_isvalid(void)
239 +{
240 + static int is_valid;
241 +
242 + if (is_valid)
243 + return(1);
244 +
245 + if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
246 + printk("nvram_isvalid FAILED\n");
247 + //nvram_initenv();
248 + }
249 + is_valid = 1;
250 + return(1);
251 +}
252 +
253 +/* return nvram address of environment string */
254 +static int
255 +nvram_matchenv(char *s)
256 +{
257 + int envsize, envp, n, i, varsize;
258 + char *var;
259 +
260 + envsize = nvram_getshort(NVOFF_ENVSIZE);
261 +
262 + if (envsize > ENV_AVAIL)
263 + return(0); /* sanity */
264 +
265 + envp = ENV_BASE;
266 +
267 + if ((n = strlen (s)) > 255)
268 + return(0);
269 +
270 + while (envsize > 0) {
271 + varsize = nvram_getbyte(envp);
272 + if (varsize == 0 || (envp + varsize) > ENV_TOP)
273 + return(0); /* sanity */
274 + for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
275 + char c1 = nvram_getbyte(i);
276 + char c2 = *var;
277 + if (islower(c1))
278 + c1 = toupper(c1);
279 + if (islower(c2))
280 + c2 = toupper(c2);
281 + if (c1 != c2)
282 + break;
283 + }
284 + if (i > envp + n) { /* match so far */
285 + if (n == varsize - 1) /* match on boolean */
286 + return(envp);
287 + if (nvram_getbyte(i) == '=') /* exact match on variable */
288 + return(envp);
289 + }
290 + envsize -= varsize;
291 + envp += varsize;
292 + }
293 + return(0);
294 +}
295 +
296 +static void nvram_initenv(void)
297 +{
298 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
299 + nvram_setshort(NVOFF_ENVSIZE, 0);
300 +
301 + nvram_updatesum();
302 +}
303 +
304 +static void
305 +nvram_delenv(char *s)
306 +{
307 + int nenvp, envp, envsize, nbytes;
308 +
309 + envp = nvram_matchenv(s);
310 + if (envp == 0)
311 + return;
312 +
313 + nenvp = envp + nvram_getbyte(envp);
314 + envsize = nvram_getshort(NVOFF_ENVSIZE);
315 + nbytes = envsize - (nenvp - ENV_BASE);
316 + nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
317 + while (nbytes--) {
318 + nvram_setbyte(envp, nvram_getbyte(nenvp));
319 + envp++;
320 + nenvp++;
321 + }
322 + nvram_updatesum();
323 +}
324 +
325 +static int
326 +nvram_setenv(char *s, char *v)
327 +{
328 + int ns, nv, total;
329 + int envp;
330 +
331 + if (!nvram_isvalid())
332 + return(-1);
333 +
334 + nvram_delenv(s);
335 + ns = strlen(s);
336 + if (ns == 0)
337 + return (-1);
338 + if (v && *v) {
339 + nv = strlen(v);
340 + total = ns + nv + 2;
341 + }
342 + else {
343 + nv = 0;
344 + total = ns + 1;
345 + }
346 + if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
347 + return(-1);
348 +
349 + envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
350 +
351 + nvram_setbyte(envp, (unsigned char) total);
352 + envp++;
353 +
354 + while (ns--) {
355 + nvram_setbyte(envp, *s);
356 + envp++;
357 + s++;
358 + }
359 +
360 + if (nv) {
361 + nvram_setbyte(envp, '=');
362 + envp++;
363 + while (nv--) {
364 + nvram_setbyte(envp, *v);
365 + envp++;
366 + v++;
367 + }
368 + }
369 + nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
370 + nvram_updatesum();
371 + return 0;
372 +}
373 +
374 +static char *
375 +nvram_getenv(char *s)
376 +{
377 + static char buf[256]; /* FIXME: this cannot be static */
378 + int envp, ns, nbytes, i;
379 +
380 + if (!nvram_isvalid())
381 + return "INVALID NVRAM"; //((char *)0);
382 +
383 + envp = nvram_matchenv(s);
384 + if (envp == 0)
385 + return "NOT FOUND"; //((char *)0);
386 + ns = strlen(s);
387 + if (nvram_getbyte(envp) == ns + 1) /* boolean */
388 + buf[0] = '\0';
389 + else {
390 + nbytes = nvram_getbyte(envp) - (ns + 2);
391 + envp += ns + 2;
392 + for (i = 0; i < nbytes; i++)
393 + buf[i] = nvram_getbyte(envp++);
394 + buf[i] = '\0';
395 + }
396 + return(buf);
397 +}
398 +
399 +static void
400 +nvram_unsetenv(char *s)
401 +{
402 + if (!nvram_isvalid())
403 + return;
404 +
405 + nvram_delenv(s);
406 +}
407 +
408 +/*
409 + * apply func to each string in environment
410 + */
411 +static void
412 +nvram_mapenv(int (*func)(char *, char *))
413 +{
414 + int envsize, envp, n, i, seeneql;
415 + char name[256], value[256];
416 + char c, *s;
417 +
418 + if (!nvram_isvalid())
419 + return;
420 +
421 + envsize = nvram_getshort(NVOFF_ENVSIZE);
422 + envp = ENV_BASE;
423 +
424 + while (envsize > 0) {
425 + value[0] = '\0';
426 + seeneql = 0;
427 + s = name;
428 + n = nvram_getbyte(envp);
429 + for (i = envp + 1; i < envp + n; i++) {
430 + c = nvram_getbyte(i);
431 + if ((c == '=') && !seeneql) {
432 + *s = '\0';
433 + s = value;
434 + seeneql = 1;
435 + continue;
436 + }
437 + *s++ = c;
438 + }
439 + *s = '\0';
440 + (*func)(name, value);
441 + envsize -= n;
442 + envp += n;
443 + }
444 +}
445 +#if 0
446 +static unsigned int
447 +digit(char c)
448 +{
449 + if ('0' <= c && c <= '9')
450 + return (c - '0');
451 + if ('A' <= c && c <= 'Z')
452 + return (10 + c - 'A');
453 + if ('a' <= c && c <= 'z')
454 + return (10 + c - 'a');
455 + return (~0);
456 +}
457 +#endif
458 +/*
459 + * Wrappers to allow 'special' environment variables to get processed
460 + */
461 +void
462 +setenv(char *e, char *v, int rewrite)
463 +{
464 + if (nvram_getenv(e) && !rewrite)
465 + return;
466 +
467 + nvram_setenv(e, v);
468 +}
469 +
470 +char *
471 +getenv(char *e)
472 +{
473 + return(nvram_getenv(e));
474 +}
475 +
476 +void
477 +unsetenv(char *e)
478 +{
479 + nvram_unsetenv(e);
480 +}
481 +
482 +void
483 +purgeenv()
484 +{
485 + int i;
486 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
487 +
488 + for (i = ENV_BASE; i < ENV_TOP; i++)
489 + *nvramDataPointer++ = 0;
490 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
491 + nvram_setshort(NVOFF_ENVSIZE, 0);
492 + nvram_setshort(NVOFF_CSUM, NV_MAGIC);
493 +}
494 +
495 +void
496 +mapenv(int (*func)(char *, char *))
497 +{
498 + nvram_mapenv(func);
499 +}
500 diff -Nur linux-2.6.15/arch/mips/aruba/nvram/nvram434.h linux-2.6.15-openwrt/arch/mips/aruba/nvram/nvram434.h
501 --- linux-2.6.15/arch/mips/aruba/nvram/nvram434.h 1970-01-01 01:00:00.000000000 +0100
502 +++ linux-2.6.15-openwrt/arch/mips/aruba/nvram/nvram434.h 2006-01-10 00:32:32.000000000 +0100
503 @@ -0,0 +1,66 @@
504 +/**************************************************************************
505 + *
506 + * BRIEF MODULE DESCRIPTION
507 + * nvram definitions.
508 + *
509 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
510 + *
511 + * This program is free software; you can redistribute it and/or modify it
512 + * under the terms of the GNU General Public License as published by the
513 + * Free Software Foundation; either version 2 of the License, or (at your
514 + * option) any later version.
515 + *
516 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
517 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
518 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
519 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
520 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
521 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
522 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
523 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
524 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
525 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
526 + *
527 + * You should have received a copy of the GNU General Public License along
528 + * with this program; if not, write to the Free Software Foundation, Inc.,
529 + * 675 Mass Ave, Cambridge, MA 02139, USA.
530 + *
531 + *
532 + **************************************************************************
533 + * May 2004 rkt, neb
534 + *
535 + * Initial Release
536 + *
537 + *
538 + *
539 + **************************************************************************
540 + */
541 +
542 +
543 +#ifndef _NVRAM_
544 +#define _NVRAM_
545 +#define NVOFFSET 0 /* use all of NVRAM */
546 +
547 +/* Offsets to reserved locations */
548 + /* size description */
549 +#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */
550 +#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment checksum */
551 +#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' */
552 +#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte */
553 +#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address */
554 +#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table */
555 +
556 +#define NV_MAGIC 0xdeaf /* nvram magic number */
557 +#define NV_RESERVED 6 /* number of reserved bytes */
558 +
559 +#undef NVOFF_ETHADDR
560 +#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)
561 +
562 +/* number of bytes available for environment */
563 +#define ENV_BASE (NVOFFSET + NV_RESERVED)
564 +#define ENV_TOP 0x2000
565 +#define ENV_AVAIL (ENV_TOP - ENV_BASE)
566 +
567 +#endif /* _NVRAM_ */
568 +
569 +
570 diff -Nur linux-2.6.15/arch/mips/aruba/prom.c linux-2.6.15-openwrt/arch/mips/aruba/prom.c
571 --- linux-2.6.15/arch/mips/aruba/prom.c 1970-01-01 01:00:00.000000000 +0100
572 +++ linux-2.6.15-openwrt/arch/mips/aruba/prom.c 2006-01-10 00:32:32.000000000 +0100
573 @@ -0,0 +1,111 @@
574 +/**************************************************************************
575 + *
576 + * BRIEF MODULE DESCRIPTION
577 + * prom interface routines
578 + *
579 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
580 + *
581 + * This program is free software; you can redistribute it and/or modify it
582 + * under the terms of the GNU General Public License as published by the
583 + * Free Software Foundation; either version 2 of the License, or (at your
584 + * option) any later version.
585 + *
586 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
587 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
588 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
589 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
590 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
591 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
592 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
593 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
594 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
595 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
596 + *
597 + * You should have received a copy of the GNU General Public License along
598 + * with this program; if not, write to the Free Software Foundation, Inc.,
599 + * 675 Mass Ave, Cambridge, MA 02139, USA.
600 + *
601 + *
602 + **************************************************************************
603 + * May 2004 rkt, neb
604 + *
605 + * Initial Release
606 + *
607 + *
608 + *
609 + **************************************************************************
610 + */
611 +
612 +#include <linux/config.h>
613 +#include <linux/init.h>
614 +#include <linux/mm.h>
615 +#include <linux/module.h>
616 +#include <linux/string.h>
617 +#include <linux/console.h>
618 +#include <asm/bootinfo.h>
619 +#include <linux/bootmem.h>
620 +#include <linux/ioport.h>
621 +#include <linux/serial.h>
622 +#include <linux/serialP.h>
623 +#include <asm/serial.h>
624 +#include <linux/ioport.h>
625 +
626 +unsigned int idt_cpu_freq;
627 +EXPORT_SYMBOL(idt_cpu_freq);
628 +
629 +unsigned int arch_has_pci=0;
630 +
631 +/* Kernel Boot parameters */
632 +static unsigned char bootparm[] = "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2";
633 +
634 +extern unsigned long mips_machgroup;
635 +extern unsigned long mips_machtype;
636 +
637 +extern void setup_serial_port(void);
638 +extern char * getenv(char *e);
639 +
640 +/* IDT 79EB434 memory map -- we really should be auto sizing it */
641 +#define RAM_SIZE 32*1024*1024
642 +
643 +char *__init prom_getcmdline(void)
644 +{
645 + return &(arcs_cmdline[0]);
646 +}
647 +
648 +void __init prom_init(void)
649 +{
650 + char *boardname;
651 + sprintf(arcs_cmdline, "%s", bootparm);
652 +
653 + /* set our arch type */
654 + mips_machgroup = MACH_GROUP_ARUBA;
655 + mips_machtype = MACH_ARUBA_UNKNOWN;
656 +
657 + boardname=getenv("boardname");
658 +
659 + if (!strcmp(boardname,"Muscat")) {
660 + mips_machtype = MACH_ARUBA_AP70;
661 + idt_cpu_freq = 133000000;
662 + arch_has_pci=1;
663 + } else if (!strcmp(boardname,"Mataro")) {
664 + mips_machtype = MACH_ARUBA_AP65;
665 + idt_cpu_freq = 110000000;
666 + } else if (!strcmp(boardname,"Merlot")) {
667 + mips_machtype = MACH_ARUBA_AP60;
668 + idt_cpu_freq = 90000000;
669 + }
670 +
671 + /* turn on the console */
672 + setup_serial_port();
673 +
674 + /*
675 + * give all RAM to boot allocator,
676 + * except where the kernel was loaded
677 + */
678 + add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
679 +}
680 +
681 +void prom_free_prom_memory(void)
682 +{
683 + printk("stubbed prom_free_prom_memory()\n");
684 +}
685 diff -Nur linux-2.6.15/arch/mips/aruba/serial.c linux-2.6.15-openwrt/arch/mips/aruba/serial.c
686 --- linux-2.6.15/arch/mips/aruba/serial.c 1970-01-01 01:00:00.000000000 +0100
687 +++ linux-2.6.15-openwrt/arch/mips/aruba/serial.c 2006-01-10 00:32:32.000000000 +0100
688 @@ -0,0 +1,94 @@
689 +/**************************************************************************
690 + *
691 + * BRIEF MODULE DESCRIPTION
692 + * Serial port initialisation.
693 + *
694 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
695 + *
696 + * This program is free software; you can redistribute it and/or modify it
697 + * under the terms of the GNU General Public License as published by the
698 + * Free Software Foundation; either version 2 of the License, or (at your
699 + * option) any later version.
700 + *
701 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
702 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
703 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
704 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
705 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
706 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
707 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
708 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
709 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
710 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
711 + *
712 + * You should have received a copy of the GNU General Public License along
713 + * with this program; if not, write to the Free Software Foundation, Inc.,
714 + * 675 Mass Ave, Cambridge, MA 02139, USA.
715 + *
716 + *
717 + **************************************************************************
718 + * May 2004 rkt, neb
719 + *
720 + * Initial Release
721 + *
722 + *
723 + *
724 + **************************************************************************
725 + */
726 +
727 +
728 +#include <linux/config.h>
729 +#include <linux/init.h>
730 +#include <linux/sched.h>
731 +#include <linux/pci.h>
732 +#include <linux/interrupt.h>
733 +#include <linux/tty.h>
734 +#include <linux/serial.h>
735 +#include <linux/serial_core.h>
736 +
737 +#include <asm/time.h>
738 +#include <asm/cpu.h>
739 +#include <asm/bootinfo.h>
740 +#include <asm/irq.h>
741 +#include <asm/serial.h>
742 +
743 +#include <asm/idt-boards/rc32434/rc32434.h>
744 +
745 +extern int __init early_serial_setup(struct uart_port *port);
746 +
747 +#define BASE_BAUD (1843200 / 16)
748 +
749 +extern unsigned int idt_cpu_freq;
750 +
751 +extern int __init setup_serial_port(void)
752 +{
753 + static struct uart_port serial_req[2];
754 +
755 + memset(serial_req, 0, sizeof(serial_req));
756 + serial_req[0].type = PORT_16550A;
757 + serial_req[0].line = 0;
758 + serial_req[0].flags = STD_COM_FLAGS;
759 + serial_req[0].iotype = SERIAL_IO_MEM;
760 + serial_req[0].regshift = 2;
761 +
762 + switch (mips_machtype) {
763 + case MACH_ARUBA_AP70:
764 + serial_req[0].irq = 104;
765 + serial_req[0].mapbase = KSEG1ADDR(0x18058003);
766 + serial_req[0].membase = (char *) KSEG1ADDR(0x18058003);
767 + serial_req[0].uartclk = idt_cpu_freq;
768 + break;
769 + case MACH_ARUBA_AP65:
770 + case MACH_ARUBA_AP60:
771 + default:
772 + serial_req[0].irq = 12;
773 + serial_req[0].mapbase = KSEG1ADDR(0xbc000003);
774 + serial_req[0].membase = (char *) KSEG1ADDR(0xbc000003);
775 + serial_req[0].uartclk = idt_cpu_freq / 2;
776 + break;
777 + }
778 +
779 + early_serial_setup(&serial_req[0]);
780 +
781 + return(0);
782 +}
783 diff -Nur linux-2.6.15/arch/mips/aruba/setup.c linux-2.6.15-openwrt/arch/mips/aruba/setup.c
784 --- linux-2.6.15/arch/mips/aruba/setup.c 1970-01-01 01:00:00.000000000 +0100
785 +++ linux-2.6.15-openwrt/arch/mips/aruba/setup.c 2006-01-10 00:32:32.000000000 +0100
786 @@ -0,0 +1,124 @@
787 +/**************************************************************************
788 + *
789 + * BRIEF MODULE DESCRIPTION
790 + * setup routines for IDT EB434 boards
791 + *
792 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
793 + *
794 + * This program is free software; you can redistribute it and/or modify it
795 + * under the terms of the GNU General Public License as published by the
796 + * Free Software Foundation; either version 2 of the License, or (at your
797 + * option) any later version.
798 + *
799 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
800 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
801 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
802 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
803 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
804 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
805 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
806 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
807 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
808 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
809 + *
810 + * You should have received a copy of the GNU General Public License along
811 + * with this program; if not, write to the Free Software Foundation, Inc.,
812 + * 675 Mass Ave, Cambridge, MA 02139, USA.
813 + *
814 + *
815 + **************************************************************************
816 + * May 2004 rkt, neb
817 + *
818 + * Initial Release
819 + *
820 + *
821 + *
822 + **************************************************************************
823 + */
824 +
825 +#include <linux/init.h>
826 +#include <linux/mm.h>
827 +#include <linux/sched.h>
828 +#include <linux/irq.h>
829 +#include <asm/bootinfo.h>
830 +#include <asm/io.h>
831 +#include <linux/ioport.h>
832 +#include <asm/mipsregs.h>
833 +#include <asm/pgtable.h>
834 +#include <asm/reboot.h>
835 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
836 +#include <asm/idt-boards/rc32434/rc32434.h>
837 +
838 +extern char *__init prom_getcmdline(void);
839 +
840 +extern void (*board_time_init) (void);
841 +extern void (*board_timer_setup) (struct irqaction * irq);
842 +extern void aruba_time_init(void);
843 +extern void aruba_timer_setup(struct irqaction *irq);
844 +extern void aruba_reset(void);
845 +
846 +#define epldMask ((volatile unsigned char *)0xB900000d)
847 +
848 +static void aruba_machine_restart(char *command)
849 +{
850 + switch (mips_machtype) {
851 + case MACH_ARUBA_AP70:
852 + *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
853 + break;
854 + case MACH_ARUBA_AP65:
855 + case MACH_ARUBA_AP60:
856 + default:
857 + /* Reset*/
858 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
859 + udelay(100);
860 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
861 + udelay(100);
862 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
863 + break;
864 + }
865 +}
866 +
867 +static void aruba_machine_halt(void)
868 +{
869 + for (;;) continue;
870 +}
871 +
872 +extern char * getenv(char *e);
873 +extern void unlock_ap60_70_flash(void);
874 +extern void wdt_merlot_disable(void);
875 +
876 +void __init plat_setup(void)
877 +{
878 + board_time_init = aruba_time_init;
879 +
880 + board_timer_setup = aruba_timer_setup;
881 +
882 + _machine_restart = aruba_machine_restart;
883 + _machine_halt = aruba_machine_halt;
884 + _machine_power_off = aruba_machine_halt;
885 +
886 + set_io_port_base(KSEG1);
887 +
888 + /* Enable PCI interrupts in EPLD Mask register */
889 + *epldMask = 0x0;
890 + *(epldMask + 1) = 0x0;
891 +
892 + write_c0_wired(0);
893 + unlock_ap60_70_flash();
894 +
895 + printk("BOARD - %s\n",getenv("boardname"));
896 +
897 + wdt_merlot_disable();
898 +
899 + return 0;
900 +}
901 +
902 +int page_is_ram(unsigned long pagenr)
903 +{
904 + return 1;
905 +}
906 +
907 +const char *get_system_type(void)
908 +{
909 + return "MIPS IDT32434 - ARUBA";
910 +}
911 diff -Nur linux-2.6.15/arch/mips/aruba/time.c linux-2.6.15-openwrt/arch/mips/aruba/time.c
912 --- linux-2.6.15/arch/mips/aruba/time.c 1970-01-01 01:00:00.000000000 +0100
913 +++ linux-2.6.15-openwrt/arch/mips/aruba/time.c 2006-01-10 00:32:32.000000000 +0100
914 @@ -0,0 +1,108 @@
915 +/**************************************************************************
916 + *
917 + * BRIEF MODULE DESCRIPTION
918 + * timer routines for IDT EB434 boards
919 + *
920 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
921 + *
922 + * This program is free software; you can redistribute it and/or modify it
923 + * under the terms of the GNU General Public License as published by the
924 + * Free Software Foundation; either version 2 of the License, or (at your
925 + * option) any later version.
926 + *
927 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
928 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
929 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
930 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
931 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
932 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
933 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
934 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
935 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
936 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
937 + *
938 + * You should have received a copy of the GNU General Public License along
939 + * with this program; if not, write to the Free Software Foundation, Inc.,
940 + * 675 Mass Ave, Cambridge, MA 02139, USA.
941 + *
942 + *
943 + **************************************************************************
944 + * May 2004 rkt, neb
945 + *
946 + * Initial Release
947 + *
948 + *
949 + *
950 + **************************************************************************
951 + */
952 +
953 +#include <linux/config.h>
954 +#include <linux/init.h>
955 +#include <linux/kernel_stat.h>
956 +#include <linux/sched.h>
957 +#include <linux/spinlock.h>
958 +#include <linux/mc146818rtc.h>
959 +#include <linux/irq.h>
960 +#include <linux/timex.h>
961 +
962 +#include <linux/param.h>
963 +#include <asm/mipsregs.h>
964 +#include <asm/ptrace.h>
965 +#include <asm/time.h>
966 +#include <asm/hardirq.h>
967 +
968 +#include <asm/mipsregs.h>
969 +#include <asm/ptrace.h>
970 +#include <asm/debug.h>
971 +#include <asm/time.h>
972 +
973 +#include <asm/idt-boards/rc32434/rc32434.h>
974 +
975 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
976 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
977 +
978 +extern unsigned int idt_cpu_freq;
979 +
980 +static unsigned long __init cal_r4koff(void)
981 +{
982 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
983 + return (mips_hpt_frequency / HZ);
984 +}
985 +
986 +void __init aruba_time_init(void)
987 +{
988 + unsigned int est_freq, flags;
989 + local_irq_save(flags);
990 +
991 + printk("calculating r4koff... ");
992 + r4k_offset = cal_r4koff();
993 + printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
994 +
995 + est_freq = 2 * r4k_offset * HZ;
996 + est_freq += 5000; /* round */
997 + est_freq -= est_freq % 10000;
998 + printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
999 + (est_freq % 1000000) * 100 / 1000000);
1000 + local_irq_restore(flags);
1001 +
1002 +}
1003 +
1004 +void __init aruba_timer_setup(struct irqaction *irq)
1005 +{
1006 + /* we are using the cpu counter for timer interrupts */
1007 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1008 +
1009 + /* to generate the first timer interrupt */
1010 + r4k_cur = (read_c0_count() + r4k_offset);
1011 + write_c0_compare(r4k_cur);
1012 +
1013 +}
1014 +
1015 +asmlinkage void aruba_timer_interrupt(int irq, struct pt_regs *regs)
1016 +{
1017 + irq_enter();
1018 + kstat_this_cpu.irqs[irq]++;
1019 +
1020 + timer_interrupt(irq, NULL, regs);
1021 + irq_exit();
1022 +}
1023 diff -Nur linux-2.6.15/arch/mips/aruba/wdt_merlot.c linux-2.6.15-openwrt/arch/mips/aruba/wdt_merlot.c
1024 --- linux-2.6.15/arch/mips/aruba/wdt_merlot.c 1970-01-01 01:00:00.000000000 +0100
1025 +++ linux-2.6.15-openwrt/arch/mips/aruba/wdt_merlot.c 2006-01-10 00:32:32.000000000 +0100
1026 @@ -0,0 +1,30 @@
1027 +#include <linux/config.h>
1028 +#include <linux/kernel.h>
1029 +#include <asm/bootinfo.h>
1030 +
1031 +void wdt_merlot_disable()
1032 +{
1033 + volatile __u32 *wdt_errcs;
1034 + volatile __u32 *wdt_wtc;
1035 + volatile __u32 *wdt_ctl;
1036 + volatile __u32 val;
1037 +
1038 + switch (mips_machtype) {
1039 + case MACH_ARUBA_AP70:
1040 + wdt_errcs = (__u32 *) 0xb8030030;
1041 + wdt_wtc = (__u32 *) 0xb803003c;
1042 + val = *wdt_errcs;
1043 + val &= ~0x201;
1044 + *wdt_errcs = val;
1045 + val = *wdt_wtc;
1046 + val &= ~0x1;
1047 + *wdt_wtc = val;
1048 + break;
1049 + case MACH_ARUBA_AP65:
1050 + case MACH_ARUBA_AP60:
1051 + default:
1052 + wdt_ctl = (__u32 *) 0xbc003008;
1053 + *wdt_ctl = 0;
1054 + break;
1055 + }
1056 +}
1057 diff -Nur linux-2.6.15/arch/mips/Kconfig linux-2.6.15-openwrt/arch/mips/Kconfig
1058 --- linux-2.6.15/arch/mips/Kconfig 2006-01-03 04:21:10.000000000 +0100
1059 +++ linux-2.6.15-openwrt/arch/mips/Kconfig 2006-01-10 00:32:32.000000000 +0100
1060 @@ -227,6 +227,18 @@
1061 either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
1062 a kernel for this platform.
1063
1064 +config MACH_ARUBA
1065 + bool "Support for the ARUBA product line"
1066 + select DMA_NONCOHERENT
1067 + select IRQ_CPU
1068 + select CPU_HAS_PREFETCH
1069 + select HW_HAS_PCI
1070 + select SWAP_IO_SPACE
1071 + select SYS_SUPPORTS_32BIT_KERNEL
1072 + select SYS_HAS_CPU_MIPS32_R1
1073 + select SYS_SUPPORTS_BIG_ENDIAN
1074 +
1075 +
1076 config MACH_JAZZ
1077 bool "Support for the Jazz family of machines"
1078 select ARC
1079 diff -Nur linux-2.6.15/arch/mips/Makefile linux-2.6.15-openwrt/arch/mips/Makefile
1080 --- linux-2.6.15/arch/mips/Makefile 2006-01-03 04:21:10.000000000 +0100
1081 +++ linux-2.6.15-openwrt/arch/mips/Makefile 2006-01-10 00:32:32.000000000 +0100
1082 @@ -258,6 +258,14 @@
1083 #
1084
1085 #
1086 +# Aruba
1087 +#
1088 +
1089 +core-$(CONFIG_MACH_ARUBA) += arch/mips/aruba/
1090 +cflags-$(CONFIG_MACH_ARUBA) += -Iinclude/asm-mips/aruba
1091 +load-$(CONFIG_MACH_ARUBA) += 0x80100000
1092 +
1093 +#
1094 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
1095 #
1096 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
1097 diff -Nur linux-2.6.15/arch/mips/mm/tlbex.c linux-2.6.15-openwrt/arch/mips/mm/tlbex.c
1098 --- linux-2.6.15/arch/mips/mm/tlbex.c 2006-01-03 04:21:10.000000000 +0100
1099 +++ linux-2.6.15-openwrt/arch/mips/mm/tlbex.c 2006-01-10 00:32:32.000000000 +0100
1100 @@ -852,7 +852,6 @@
1101
1102 case CPU_R10000:
1103 case CPU_R12000:
1104 - case CPU_4KC:
1105 case CPU_SB1:
1106 case CPU_SB1A:
1107 case CPU_4KSC:
1108 @@ -880,6 +879,7 @@
1109 tlbw(p);
1110 break;
1111
1112 + case CPU_4KC:
1113 case CPU_4KEC:
1114 case CPU_24K:
1115 case CPU_34K:
1116 diff -Nur linux-2.6.15/drivers/net/Kconfig linux-2.6.15-openwrt/drivers/net/Kconfig
1117 --- linux-2.6.15/drivers/net/Kconfig 2006-01-03 04:21:10.000000000 +0100
1118 +++ linux-2.6.15-openwrt/drivers/net/Kconfig 2006-01-10 00:32:32.000000000 +0100
1119 @@ -176,6 +176,13 @@
1120
1121 source "drivers/net/arm/Kconfig"
1122
1123 +config IDT_RC32434_ETH
1124 + tristate "IDT RC32434 Local Ethernet support"
1125 + depends on NET_ETHERNET
1126 + help
1127 + IDT RC32434 has one local ethernet port. Say Y here to enable it.
1128 + To compile this driver as a module, choose M here.
1129 +
1130 config MACE
1131 tristate "MACE (Power Mac ethernet) support"
1132 depends on NET_ETHERNET && PPC_PMAC && PPC32
1133 diff -Nur linux-2.6.15/drivers/net/Makefile linux-2.6.15-openwrt/drivers/net/Makefile
1134 --- linux-2.6.15/drivers/net/Makefile 2006-01-03 04:21:10.000000000 +0100
1135 +++ linux-2.6.15-openwrt/drivers/net/Makefile 2006-01-10 00:32:33.000000000 +0100
1136 @@ -190,6 +190,7 @@
1137 obj-$(CONFIG_SMC91X) += smc91x.o
1138 obj-$(CONFIG_DM9000) += dm9000.o
1139 obj-$(CONFIG_FEC_8XX) += fec_8xx/
1140 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
1141
1142 obj-$(CONFIG_ARM) += arm/
1143 obj-$(CONFIG_DEV_APPLETALK) += appletalk/
1144 diff -Nur linux-2.6.15/drivers/net/rc32434_eth.c linux-2.6.15-openwrt/drivers/net/rc32434_eth.c
1145 --- linux-2.6.15/drivers/net/rc32434_eth.c 1970-01-01 01:00:00.000000000 +0100
1146 +++ linux-2.6.15-openwrt/drivers/net/rc32434_eth.c 2006-01-10 00:32:33.000000000 +0100
1147 @@ -0,0 +1,1268 @@
1148 +/**************************************************************************
1149 + *
1150 + * BRIEF MODULE DESCRIPTION
1151 + * Driver for the IDT RC32434 on-chip ethernet controller.
1152 + *
1153 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1154 + *
1155 + * This program is free software; you can redistribute it and/or modify it
1156 + * under the terms of the GNU General Public License as published by the
1157 + * Free Software Foundation; either version 2 of the License, or (at your
1158 + * option) any later version.
1159 + *
1160 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1161 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1162 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1163 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1164 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1165 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1166 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1167 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1168 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1169 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1170 + *
1171 + * You should have received a copy of the GNU General Public License along
1172 + * with this program; if not, write to the Free Software Foundation, Inc.,
1173 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1174 + *
1175 + *
1176 + **************************************************************************
1177 + * May 2004 rkt, neb
1178 + *
1179 + * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
1180 + *
1181 + * Aug 2004 Sadik
1182 + *
1183 + * Added NAPI
1184 + *
1185 + **************************************************************************
1186 + */
1187 +
1188 +#include <linux/config.h>
1189 +#include <linux/module.h>
1190 +#include <linux/kernel.h>
1191 +#include <linux/moduleparam.h>
1192 +#include <linux/sched.h>
1193 +#include <linux/ctype.h>
1194 +#include <linux/types.h>
1195 +#include <linux/fcntl.h>
1196 +#include <linux/interrupt.h>
1197 +#include <linux/ptrace.h>
1198 +#include <linux/init.h>
1199 +#include <linux/ioport.h>
1200 +#include <linux/proc_fs.h>
1201 +#include <linux/in.h>
1202 +#include <linux/slab.h>
1203 +#include <linux/string.h>
1204 +#include <linux/delay.h>
1205 +#include <linux/netdevice.h>
1206 +#include <linux/etherdevice.h>
1207 +#include <linux/skbuff.h>
1208 +#include <linux/errno.h>
1209 +#include <asm/bootinfo.h>
1210 +#include <asm/system.h>
1211 +#include <asm/bitops.h>
1212 +#include <asm/pgtable.h>
1213 +#include <asm/segment.h>
1214 +#include <asm/io.h>
1215 +#include <asm/dma.h>
1216 +
1217 +#include "rc32434_eth.h"
1218 +
1219 +#define DRIVER_VERSION "(mar2904)"
1220 +
1221 +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
1222 +
1223 +
1224 +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
1225 + ((dev)->dev_addr[1]))
1226 +#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
1227 + ((dev)->dev_addr[3] << 16) | \
1228 + ((dev)->dev_addr[4] << 8) | \
1229 + ((dev)->dev_addr[5]))
1230 +
1231 +#define MII_CLOCK 1250000 /* no more than 2.5MHz */
1232 +static char mac0[18] = "08:00:06:05:40:01";
1233 +
1234 +MODULE_PARM(mac0, "c18");
1235 +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
1236 +
1237 +static struct rc32434_if_t {
1238 + char *name;
1239 + struct net_device *dev;
1240 + char* mac_str;
1241 + int weight;
1242 + u32 iobase;
1243 + u32 rxdmabase;
1244 + u32 txdmabase;
1245 + int rx_dma_irq;
1246 + int tx_dma_irq;
1247 + int rx_ovr_irq;
1248 + int tx_und_irq;
1249 +} rc32434_iflist[] =
1250 +{
1251 + {
1252 + "rc32434_eth0", NULL, mac0,
1253 + 64,
1254 + ETH0_PhysicalAddress,
1255 + ETH0_RX_DMA_ADDR,
1256 + ETH0_TX_DMA_ADDR,
1257 + ETH0_DMA_RX_IRQ,
1258 + ETH0_DMA_TX_IRQ,
1259 + ETH0_RX_OVR_IRQ,
1260 + ETH0_TX_UND_IRQ
1261 + }
1262 +};
1263 +
1264 +
1265 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1266 +{
1267 + int i, j;
1268 + unsigned char result, value;
1269 +
1270 + for (i=0; i<6; i++) {
1271 + result = 0;
1272 + if (i != 5 && *(macstr+2) != ':') {
1273 + ERR("invalid mac address format: %d %c\n",
1274 + i, *(macstr+2));
1275 + return -EINVAL;
1276 + }
1277 + for (j=0; j<2; j++) {
1278 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1279 + toupper(*macstr)-'A'+10) < 16) {
1280 + result = result*16 + value;
1281 + macstr++;
1282 + }
1283 + else {
1284 + ERR("invalid mac address "
1285 + "character: %c\n", *macstr);
1286 + return -EINVAL;
1287 + }
1288 + }
1289 +
1290 + macstr++;
1291 + dev->dev_addr[i] = result;
1292 + }
1293 +
1294 + return 0;
1295 +}
1296 +
1297 +
1298 +
1299 +static inline void rc32434_abort_tx(struct net_device *dev)
1300 +{
1301 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1302 + rc32434_abort_dma(dev, lp->tx_dma_regs);
1303 +
1304 +}
1305 +
1306 +static inline void rc32434_abort_rx(struct net_device *dev)
1307 +{
1308 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1309 + rc32434_abort_dma(dev, lp->rx_dma_regs);
1310 +
1311 +}
1312 +
1313 +static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td)
1314 +{
1315 + rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
1316 +}
1317 +
1318 +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1319 +{
1320 + rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1321 +}
1322 +
1323 +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
1324 +{
1325 + rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
1326 +}
1327 +
1328 +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1329 +{
1330 + rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1331 +}
1332 +
1333 +#ifdef RC32434_PROC_DEBUG
1334 +static int rc32434_read_proc(char *buf, char **start, off_t fpos,
1335 + int length, int *eof, void *data)
1336 +{
1337 + struct net_device *dev = (struct net_device *)data;
1338 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1339 + int len = 0;
1340 +
1341 + /* print out header */
1342 + len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
1343 + len += sprintf (buf + len,
1344 + "DMA halt count = %10d, DMA run count = %10d\n",
1345 + lp->dma_halt_cnt, lp->dma_run_cnt);
1346 +
1347 + if (fpos >= len) {
1348 + *start = buf;
1349 + *eof = 1;
1350 + return 0;
1351 + }
1352 + *start = buf + fpos;
1353 +
1354 + if ((len -= fpos) > length)
1355 + return length;
1356 + *eof = 1;
1357 +
1358 + return len;
1359 +
1360 +}
1361 +#endif
1362 +
1363 +
1364 +/*
1365 + * Restart the RC32434 ethernet controller.
1366 + */
1367 +static int rc32434_restart(struct net_device *dev)
1368 +{
1369 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1370 +
1371 + /*
1372 + * Disable interrupts
1373 + */
1374 + disable_irq(lp->rx_irq);
1375 + disable_irq(lp->tx_irq);
1376 +#ifdef RC32434_REVISION
1377 + disable_irq(lp->ovr_irq);
1378 +#endif
1379 + disable_irq(lp->und_irq);
1380 +
1381 + /* Mask F E bit in Tx DMA */
1382 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
1383 + /* Mask D H E bit in Rx DMA */
1384 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
1385 +
1386 + rc32434_init(dev);
1387 + rc32434_multicast_list(dev);
1388 +
1389 + enable_irq(lp->und_irq);
1390 +#ifdef RC32434_REVISION
1391 + enable_irq(lp->ovr_irq);
1392 +#endif
1393 + enable_irq(lp->tx_irq);
1394 + enable_irq(lp->rx_irq);
1395 +
1396 + return 0;
1397 +}
1398 +
1399 +int rc32434_init_module(void)
1400 +{
1401 +#ifdef CONFIG_MACH_ARUBA
1402 + if (mips_machtype != MACH_ARUBA_AP70)
1403 + return 1;
1404 +#endif
1405 +
1406 + printk(KERN_INFO DRIVER_NAME " \n");
1407 + return rc32434_probe(0);
1408 +}
1409 +
1410 +static int rc32434_probe(int port_num)
1411 +{
1412 + struct rc32434_if_t *bif = &rc32434_iflist[port_num];
1413 + struct rc32434_local *lp = NULL;
1414 + struct net_device *dev = NULL;
1415 + int i, retval,err;
1416 +
1417 + dev = alloc_etherdev(sizeof(struct rc32434_local));
1418 + if(!dev) {
1419 + ERR("rc32434_eth: alloc_etherdev failed\n");
1420 + return -1;
1421 + }
1422 +
1423 + SET_MODULE_OWNER(dev);
1424 + bif->dev = dev;
1425 +
1426 +#ifdef CONFIG_MACH_ARUBA
1427 + {
1428 + extern char * getenv(char *e);
1429 + memcpy(bif->mac_str, getenv("ethaddr"), 17);
1430 + }
1431 +#endif
1432 +
1433 + printk("mac: %s\n", bif->mac_str);
1434 + if ((retval = parse_mac_addr(dev, bif->mac_str))) {
1435 + ERR("MAC address parse failed\n");
1436 + free_netdev(dev);
1437 + return -1;
1438 + }
1439 +
1440 +
1441 + /* Initialize the device structure. */
1442 + if (dev->priv == NULL) {
1443 + lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
1444 + memset(lp, 0, sizeof(struct rc32434_local));
1445 + }
1446 + else {
1447 + lp = (struct rc32434_local *)dev->priv;
1448 + }
1449 +
1450 + lp->rx_irq = bif->rx_dma_irq;
1451 + lp->tx_irq = bif->tx_dma_irq;
1452 + lp->ovr_irq = bif->rx_ovr_irq;
1453 + lp->und_irq = bif->tx_und_irq;
1454 +
1455 + lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
1456 +
1457 + if (!lp->eth_regs) {
1458 + ERR("Can't remap eth registers\n");
1459 + retval = -ENXIO;
1460 + goto probe_err_out;
1461 + }
1462 +
1463 + lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
1464 +
1465 + if (!lp->rx_dma_regs) {
1466 + ERR("Can't remap Rx DMA registers\n");
1467 + retval = -ENXIO;
1468 + goto probe_err_out;
1469 + }
1470 + lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
1471 +
1472 + if (!lp->tx_dma_regs) {
1473 + ERR("Can't remap Tx DMA registers\n");
1474 + retval = -ENXIO;
1475 + goto probe_err_out;
1476 + }
1477 +
1478 +#ifdef RC32434_PROC_DEBUG
1479 + lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
1480 + rc32434_read_proc, dev);
1481 +#endif
1482 +
1483 + lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1484 + if (!lp->td_ring) {
1485 + ERR("Can't allocate descriptors\n");
1486 + retval = -ENOMEM;
1487 + goto probe_err_out;
1488 + }
1489 +
1490 + dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
1491 +
1492 + /* now convert TD_RING pointer to KSEG1 */
1493 + lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
1494 + lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
1495 +
1496 +
1497 + spin_lock_init(&lp->lock);
1498 +
1499 + dev->base_addr = bif->iobase;
1500 + /* just use the rx dma irq */
1501 + dev->irq = bif->rx_dma_irq;
1502 +
1503 + dev->priv = lp;
1504 +
1505 + dev->open = rc32434_open;
1506 + dev->stop = rc32434_close;
1507 + dev->hard_start_xmit = rc32434_send_packet;
1508 + dev->get_stats = rc32434_get_stats;
1509 + dev->set_multicast_list = &rc32434_multicast_list;
1510 + dev->tx_timeout = rc32434_tx_timeout;
1511 + dev->watchdog_timeo = RC32434_TX_TIMEOUT;
1512 +
1513 +#ifdef CONFIG_IDT_USE_NAPI
1514 + dev->poll = rc32434_poll;
1515 + dev->weight = bif->weight;
1516 + printk("Using NAPI with weight %d\n",dev->weight);
1517 +#else
1518 + lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1519 + tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
1520 +#endif
1521 + lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1522 + tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
1523 +
1524 + if ((err = register_netdev(dev))) {
1525 + printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
1526 + free_netdev(dev);
1527 + retval = -EINVAL;
1528 + goto probe_err_out;
1529 + }
1530 +
1531 + INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
1532 + for (i = 0; i < 6; i++) {
1533 + printk("%2.2x", dev->dev_addr[i]);
1534 + if (i<5)
1535 + printk(":");
1536 + }
1537 + printk("\n");
1538 +
1539 + return 0;
1540 +
1541 + probe_err_out:
1542 + rc32434_cleanup_module();
1543 + ERR(" failed. Returns %d\n", retval);
1544 + return retval;
1545 +
1546 +}
1547 +
1548 +
1549 +static void rc32434_cleanup_module(void)
1550 +{
1551 + int i;
1552 +
1553 + for (i = 0; rc32434_iflist[i].iobase; i++) {
1554 + struct rc32434_if_t * bif = &rc32434_iflist[i];
1555 + if (bif->dev != NULL) {
1556 + struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
1557 + if (lp != NULL) {
1558 + if (lp->eth_regs)
1559 + iounmap((void*)lp->eth_regs);
1560 + if (lp->rx_dma_regs)
1561 + iounmap((void*)lp->rx_dma_regs);
1562 + if (lp->tx_dma_regs)
1563 + iounmap((void*)lp->tx_dma_regs);
1564 + if (lp->td_ring)
1565 + kfree((void*)KSEG0ADDR(lp->td_ring));
1566 +
1567 +#ifdef RC32434_PROC_DEBUG
1568 + if (lp->ps) {
1569 + remove_proc_entry(bif->name, proc_net);
1570 + }
1571 +#endif
1572 + kfree(lp);
1573 + }
1574 +
1575 + unregister_netdev(bif->dev);
1576 + free_netdev(bif->dev);
1577 + kfree(bif->dev);
1578 + }
1579 + }
1580 +}
1581 +
1582 +
1583 +
1584 +static int rc32434_open(struct net_device *dev)
1585 +{
1586 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1587 +
1588 + /* Initialize */
1589 + if (rc32434_init(dev)) {
1590 + ERR("Error: cannot open the Ethernet device\n");
1591 + return -EAGAIN;
1592 + }
1593 +
1594 + /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
1595 + if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
1596 + SA_SHIRQ | SA_INTERRUPT,
1597 + "rc32434 ethernet Rx", dev)) {
1598 + ERR(": unable to get Rx DMA IRQ %d\n",
1599 + lp->rx_irq);
1600 + return -EAGAIN;
1601 + }
1602 + if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
1603 + SA_SHIRQ | SA_INTERRUPT,
1604 + "rc32434 ethernet Tx", dev)) {
1605 + ERR(": unable to get Tx DMA IRQ %d\n",
1606 + lp->tx_irq);
1607 + free_irq(lp->rx_irq, dev);
1608 + return -EAGAIN;
1609 + }
1610 +
1611 +#ifdef RC32434_REVISION
1612 + /* Install handler for overrun error. */
1613 + if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
1614 + SA_SHIRQ | SA_INTERRUPT,
1615 + "Ethernet Overflow", dev)) {
1616 + ERR(": unable to get OVR IRQ %d\n",
1617 + lp->ovr_irq);
1618 + free_irq(lp->rx_irq, dev);
1619 + free_irq(lp->tx_irq, dev);
1620 + return -EAGAIN;
1621 + }
1622 +#endif
1623 +
1624 + /* Install handler for underflow error. */
1625 + if (request_irq(lp->und_irq, &rc32434_und_interrupt,
1626 + SA_SHIRQ | SA_INTERRUPT,
1627 + "Ethernet Underflow", dev)) {
1628 + ERR(": unable to get UND IRQ %d\n",
1629 + lp->und_irq);
1630 + free_irq(lp->rx_irq, dev);
1631 + free_irq(lp->tx_irq, dev);
1632 +#ifdef RC32434_REVISION
1633 + free_irq(lp->ovr_irq, dev);
1634 +#endif
1635 + return -EAGAIN;
1636 + }
1637 +
1638 +
1639 + return 0;
1640 +}
1641 +
1642 +
1643 +
1644 +
1645 +static int rc32434_close(struct net_device *dev)
1646 +{
1647 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1648 + u32 tmp;
1649 +
1650 + /* Disable interrupts */
1651 + disable_irq(lp->rx_irq);
1652 + disable_irq(lp->tx_irq);
1653 +#ifdef RC32434_REVISION
1654 + disable_irq(lp->ovr_irq);
1655 +#endif
1656 + disable_irq(lp->und_irq);
1657 +
1658 + tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
1659 + tmp = tmp | DMASM_f_m | DMASM_e_m;
1660 + rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
1661 +
1662 + tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
1663 + tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
1664 + rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
1665 +
1666 + free_irq(lp->rx_irq, dev);
1667 + free_irq(lp->tx_irq, dev);
1668 +#ifdef RC32434_REVISION
1669 + free_irq(lp->ovr_irq, dev);
1670 +#endif
1671 + free_irq(lp->und_irq, dev);
1672 + return 0;
1673 +}
1674 +
1675 +
1676 +/* transmit packet */
1677 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
1678 +{
1679 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1680 + unsigned long flags;
1681 + u32 length;
1682 + DMAD_t td;
1683 +
1684 +
1685 + spin_lock_irqsave(&lp->lock, flags);
1686 +
1687 + td = &lp->td_ring[lp->tx_chain_tail];
1688 +
1689 + /* stop queue when full, drop pkts if queue already full */
1690 + if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
1691 + lp->tx_full = 1;
1692 +
1693 + if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
1694 + netif_stop_queue(dev);
1695 + }
1696 + else {
1697 + lp->stats.tx_dropped++;
1698 + dev_kfree_skb_any(skb);
1699 + spin_unlock_irqrestore(&lp->lock, flags);
1700 + return 1;
1701 + }
1702 + }
1703 +
1704 + lp->tx_count ++;
1705 +
1706 + lp->tx_skb[lp->tx_chain_tail] = skb;
1707 +
1708 + length = skb->len;
1709 +
1710 + /* Setup the transmit descriptor. */
1711 + td->ca = CPHYSADDR(skb->data);
1712 +
1713 + if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
1714 + if( lp->tx_chain_status == empty ) {
1715 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1716 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1717 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1718 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1719 + }
1720 + else {
1721 + td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */
1722 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1723 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1724 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1725 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1726 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1727 + lp->tx_chain_status = empty;
1728 + }
1729 + }
1730 + else {
1731 + if( lp->tx_chain_status == empty ) {
1732 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1733 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1734 + lp->tx_chain_status = filled;
1735 + }
1736 + else {
1737 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1738 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1739 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1740 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1741 + }
1742 + }
1743 +
1744 + dev->trans_start = jiffies;
1745 +
1746 + spin_unlock_irqrestore(&lp->lock, flags);
1747 +
1748 + return 0;
1749 +}
1750 +
1751 +
1752 +/* Ethernet MII-PHY Handler */
1753 +static void rc32434_mii_handler(unsigned long data)
1754 +{
1755 + struct net_device *dev = (struct net_device *)data;
1756 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1757 + unsigned long flags;
1758 + unsigned long duplex_status;
1759 + int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
1760 +
1761 + spin_lock_irqsave(&lp->lock, flags);
1762 +
1763 + /* Two ports are using the same MII, the difference is the PHY address */
1764 + rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
1765 + rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
1766 + rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
1767 + rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
1768 + while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
1769 +
1770 + ERR("irq:%x port_addr:%x RDD:%x\n",
1771 + lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
1772 + duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
1773 + if(duplex_status != lp->duplex_mode) {
1774 + ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
1775 + lp->duplex_mode = duplex_status;
1776 + rc32434_restart(dev);
1777 + }
1778 +
1779 + lp->mii_phy_timer.expires = jiffies + 10 * HZ;
1780 + add_timer(&lp->mii_phy_timer);
1781 +
1782 + spin_unlock_irqrestore(&lp->lock, flags);
1783 +
1784 +}
1785 +
1786 +#ifdef RC32434_REVISION
1787 +/* Ethernet Rx Overflow interrupt */
1788 +static irqreturn_t
1789 +rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1790 +{
1791 + struct net_device *dev = (struct net_device *)dev_id;
1792 + struct rc32434_local *lp;
1793 + unsigned int ovr;
1794 + irqreturn_t retval = IRQ_NONE;
1795 +
1796 + ASSERT(dev != NULL);
1797 +
1798 + lp = (struct rc32434_local *)dev->priv;
1799 + spin_lock(&lp->lock);
1800 + ovr = rc32434_readl(&lp->eth_regs->ethintfc);
1801 +
1802 + if(ovr & ETHINTFC_ovr_m) {
1803 + netif_stop_queue(dev);
1804 +
1805 + /* clear OVR bit */
1806 + rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
1807 +
1808 + /* Restart interface */
1809 + rc32434_restart(dev);
1810 + retval = IRQ_HANDLED;
1811 + }
1812 + spin_unlock(&lp->lock);
1813 +
1814 + return retval;
1815 +}
1816 +
1817 +#endif
1818 +
1819 +
1820 +/* Ethernet Tx Underflow interrupt */
1821 +static irqreturn_t
1822 +rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1823 +{
1824 + struct net_device *dev = (struct net_device *)dev_id;
1825 + struct rc32434_local *lp;
1826 + unsigned int und;
1827 + irqreturn_t retval = IRQ_NONE;
1828 +
1829 + ASSERT(dev != NULL);
1830 +
1831 + lp = (struct rc32434_local *)dev->priv;
1832 +
1833 + spin_lock(&lp->lock);
1834 +
1835 + und = rc32434_readl(&lp->eth_regs->ethintfc);
1836 +
1837 + if(und & ETHINTFC_und_m) {
1838 + netif_stop_queue(dev);
1839 +
1840 + rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
1841 +
1842 + /* Restart interface */
1843 + rc32434_restart(dev);
1844 + retval = IRQ_HANDLED;
1845 + }
1846 +
1847 + spin_unlock(&lp->lock);
1848 +
1849 + return retval;
1850 +}
1851 +
1852 +
1853 +/* Ethernet Rx DMA interrupt */
1854 +static irqreturn_t
1855 +rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1856 +{
1857 + struct net_device *dev = (struct net_device *)dev_id;
1858 + struct rc32434_local* lp;
1859 + volatile u32 dmas,dmasm;
1860 + irqreturn_t retval;
1861 +
1862 + ASSERT(dev != NULL);
1863 +
1864 + lp = (struct rc32434_local *)dev->priv;
1865 +
1866 + spin_lock(&lp->lock);
1867 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
1868 + if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
1869 + /* Mask D H E bit in Rx DMA */
1870 + dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
1871 + rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
1872 +#ifdef CONFIG_IDT_USE_NAPI
1873 + if(netif_rx_schedule_prep(dev))
1874 + __netif_rx_schedule(dev);
1875 +#else
1876 + tasklet_hi_schedule(lp->rx_tasklet);
1877 +#endif
1878 +
1879 + if (dmas & DMAS_e_m)
1880 + ERR(": DMA error\n");
1881 +
1882 + retval = IRQ_HANDLED;
1883 + }
1884 + else
1885 + retval = IRQ_NONE;
1886 +
1887 + spin_unlock(&lp->lock);
1888 + return retval;
1889 +}
1890 +
1891 +#ifdef CONFIG_IDT_USE_NAPI
1892 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
1893 +#else
1894 +static void rc32434_rx_tasklet(unsigned long rx_data_dev)
1895 +#endif
1896 +{
1897 + struct net_device *dev = (struct net_device *)rx_data_dev;
1898 + struct rc32434_local* lp = netdev_priv(dev);
1899 + volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done];
1900 + struct sk_buff *skb, *skb_new;
1901 + u8* pkt_buf;
1902 + u32 devcs, count, pkt_len, pktuncrc_len;
1903 + volatile u32 dmas;
1904 +#ifdef CONFIG_IDT_USE_NAPI
1905 + u32 received = 0;
1906 + int rx_work_limit = min(*budget,dev->quota);
1907 +#else
1908 + unsigned long flags;
1909 + spin_lock_irqsave(&lp->lock, flags);
1910 +#endif
1911 +
1912 + while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
1913 +#ifdef CONFIG_IDT_USE_NAPI
1914 + if(--rx_work_limit <0)
1915 + {
1916 + break;
1917 + }
1918 +#endif
1919 + /* init the var. used for the later operations within the while loop */
1920 + skb_new = NULL;
1921 + devcs = rd->devcs;
1922 + pkt_len = RCVPKT_LENGTH(devcs);
1923 + skb = lp->rx_skb[lp->rx_next_done];
1924 +
1925 + if (count < 64) {
1926 + lp->stats.rx_errors++;
1927 + lp->stats.rx_dropped++;
1928 + }
1929 + else if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) {
1930 + /* check that this is a whole packet */
1931 + /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
1932 + lp->stats.rx_errors++;
1933 + lp->stats.rx_dropped++;
1934 + }
1935 + else if ( (devcs & ETHRX_rok_m) ) {
1936 +
1937 + {
1938 + /* must be the (first and) last descriptor then */
1939 + pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
1940 +
1941 + pktuncrc_len = pkt_len - 4;
1942 + /* invalidate the cache */
1943 + dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
1944 +
1945 + /* Malloc up new buffer. */
1946 + skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
1947 +
1948 + if (skb_new != NULL){
1949 + /* Make room */
1950 + skb_put(skb, pktuncrc_len);
1951 +
1952 + skb->protocol = eth_type_trans(skb, dev);
1953 +
1954 + /* pass the packet to upper layers */
1955 +#ifdef CONFIG_IDT_USE_NAPI
1956 + netif_receive_skb(skb);
1957 +#else
1958 + netif_rx(skb);
1959 +#endif
1960 +
1961 + dev->last_rx = jiffies;
1962 + lp->stats.rx_packets++;
1963 + lp->stats.rx_bytes += pktuncrc_len;
1964 +
1965 + if (IS_RCV_MP(devcs))
1966 + lp->stats.multicast++;
1967 +
1968 + /* 16 bit align */
1969 + skb_reserve(skb_new, 2);
1970 +
1971 + skb_new->dev = dev;
1972 + lp->rx_skb[lp->rx_next_done] = skb_new;
1973 + }
1974 + else {
1975 + ERR("no memory, dropping rx packet.\n");
1976 + lp->stats.rx_errors++;
1977 + lp->stats.rx_dropped++;
1978 + }
1979 + }
1980 +
1981 + }
1982 + else {
1983 + /* This should only happen if we enable accepting broken packets */
1984 + lp->stats.rx_errors++;
1985 + lp->stats.rx_dropped++;
1986 +
1987 + /* add statistics counters */
1988 + if (IS_RCV_CRC_ERR(devcs)) {
1989 + DBG(2, "RX CRC error\n");
1990 + lp->stats.rx_crc_errors++;
1991 + }
1992 + else if (IS_RCV_LOR_ERR(devcs)) {
1993 + DBG(2, "RX LOR error\n");
1994 + lp->stats.rx_length_errors++;
1995 + }
1996 + else if (IS_RCV_LE_ERR(devcs)) {
1997 + DBG(2, "RX LE error\n");
1998 + lp->stats.rx_length_errors++;
1999 + }
2000 + else if (IS_RCV_OVR_ERR(devcs)) {
2001 + lp->stats.rx_over_errors++;
2002 + }
2003 + else if (IS_RCV_CV_ERR(devcs)) {
2004 + /* code violation */
2005 + DBG(2, "RX CV error\n");
2006 + lp->stats.rx_frame_errors++;
2007 + }
2008 + else if (IS_RCV_CES_ERR(devcs)) {
2009 + DBG(2, "RX Preamble error\n");
2010 + }
2011 + }
2012 +
2013 + rd->devcs = 0;
2014 +
2015 + /* restore descriptor's curr_addr */
2016 + if(skb_new)
2017 + rd->ca = CPHYSADDR(skb_new->data);
2018 + else
2019 + rd->ca = CPHYSADDR(skb->data);
2020 +
2021 + rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
2022 + lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m);
2023 +
2024 + lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
2025 + rd = &lp->rd_ring[lp->rx_next_done];
2026 + rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
2027 + }
2028 +#ifdef CONFIG_IDT_USE_NAPI
2029 + dev->quota -= received;
2030 + *budget =- received;
2031 + if(rx_work_limit < 0)
2032 + goto not_done;
2033 +#endif
2034 +
2035 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
2036 +
2037 + if(dmas & DMAS_h_m) {
2038 + rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
2039 +#ifdef RC32434_PROC_DEBUG
2040 + lp->dma_halt_cnt++;
2041 +#endif
2042 + rd->devcs = 0;
2043 + skb = lp->rx_skb[lp->rx_next_done];
2044 + rd->ca = CPHYSADDR(skb->data);
2045 + rc32434_chain_rx(lp,rd);
2046 + }
2047 +
2048 +#ifdef CONFIG_IDT_USE_NAPI
2049 + netif_rx_complete(dev);
2050 +#endif
2051 + /* Enable D H E bit in Rx DMA */
2052 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
2053 +#ifdef CONFIG_IDT_USE_NAPI
2054 + return 0;
2055 + not_done:
2056 + return 1;
2057 +#else
2058 + spin_unlock_irqrestore(&lp->lock, flags);
2059 + return;
2060 +#endif
2061 +
2062 +
2063 +}
2064 +
2065 +
2066 +
2067 +/* Ethernet Tx DMA interrupt */
2068 +static irqreturn_t
2069 +rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2070 +{
2071 + struct net_device *dev = (struct net_device *)dev_id;
2072 + struct rc32434_local *lp;
2073 + volatile u32 dmas,dmasm;
2074 + irqreturn_t retval;
2075 +
2076 + ASSERT(dev != NULL);
2077 +
2078 + lp = (struct rc32434_local *)dev->priv;
2079 +
2080 + spin_lock(&lp->lock);
2081 +
2082 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2083 +
2084 + if (dmas & (DMAS_f_m | DMAS_e_m)) {
2085 + dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
2086 + /* Mask F E bit in Tx DMA */
2087 + rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2088 +
2089 + tasklet_hi_schedule(lp->tx_tasklet);
2090 +
2091 + if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
2092 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
2093 + lp->tx_chain_status = empty;
2094 + lp->tx_chain_head = lp->tx_chain_tail;
2095 + dev->trans_start = jiffies;
2096 + }
2097 +
2098 + if (dmas & DMAS_e_m)
2099 + ERR(": DMA error\n");
2100 +
2101 + retval = IRQ_HANDLED;
2102 + }
2103 + else
2104 + retval = IRQ_NONE;
2105 +
2106 + spin_unlock(&lp->lock);
2107 +
2108 + return retval;
2109 +}
2110 +
2111 +
2112 +static void rc32434_tx_tasklet(unsigned long tx_data_dev)
2113 +{
2114 + struct net_device *dev = (struct net_device *)tx_data_dev;
2115 + struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
2116 + volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
2117 + u32 devcs;
2118 + unsigned long flags;
2119 + volatile u32 dmas;
2120 +
2121 + spin_lock_irqsave(&lp->lock, flags);
2122 +
2123 + /* process all desc that are done */
2124 + while(IS_DMA_FINISHED(td->control)) {
2125 + if(lp->tx_full == 1) {
2126 + netif_wake_queue(dev);
2127 + lp->tx_full = 0;
2128 + }
2129 +
2130 + devcs = lp->td_ring[lp->tx_next_done].devcs;
2131 + if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
2132 + lp->stats.tx_errors++;
2133 + lp->stats.tx_dropped++;
2134 +
2135 + /* should never happen */
2136 + DBG(1, __FUNCTION__ ": split tx ignored\n");
2137 + }
2138 + else if (IS_TX_TOK(devcs)) {
2139 + lp->stats.tx_packets++;
2140 + }
2141 + else {
2142 + lp->stats.tx_errors++;
2143 + lp->stats.tx_dropped++;
2144 +
2145 + /* underflow */
2146 + if (IS_TX_UND_ERR(devcs))
2147 + lp->stats.tx_fifo_errors++;
2148 +
2149 + /* oversized frame */
2150 + if (IS_TX_OF_ERR(devcs))
2151 + lp->stats.tx_aborted_errors++;
2152 +
2153 + /* excessive deferrals */
2154 + if (IS_TX_ED_ERR(devcs))
2155 + lp->stats.tx_carrier_errors++;
2156 +
2157 + /* collisions: medium busy */
2158 + if (IS_TX_EC_ERR(devcs))
2159 + lp->stats.collisions++;
2160 +
2161 + /* late collision */
2162 + if (IS_TX_LC_ERR(devcs))
2163 + lp->stats.tx_window_errors++;
2164 +
2165 + }
2166 +
2167 + /* We must always free the original skb */
2168 + if (lp->tx_skb[lp->tx_next_done] != NULL) {
2169 + dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
2170 + lp->tx_skb[lp->tx_next_done] = NULL;
2171 + }
2172 +
2173 + lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
2174 + lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
2175 + lp->td_ring[lp->tx_next_done].link = 0;
2176 + lp->td_ring[lp->tx_next_done].ca = 0;
2177 + lp->tx_count --;
2178 +
2179 + /* go on to next transmission */
2180 + lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
2181 + td = &lp->td_ring[lp->tx_next_done];
2182 +
2183 + }
2184 +
2185 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2186 + rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
2187 +
2188 + /* Enable F E bit in Tx DMA */
2189 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2190 + spin_unlock_irqrestore(&lp->lock, flags);
2191 +
2192 +}
2193 +
2194 +
2195 +static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
2196 +{
2197 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2198 + return &lp->stats;
2199 +}
2200 +
2201 +
2202 +/*
2203 + * Set or clear the multicast filter for this adaptor.
2204 + */
2205 +static void rc32434_multicast_list(struct net_device *dev)
2206 +{
2207 + /* listen to broadcasts always and to treat */
2208 + /* IFF bits independantly */
2209 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2210 + unsigned long flags;
2211 + u32 recognise = ETHARC_ab_m; /* always accept broadcasts */
2212 +
2213 + if (dev->flags & IFF_PROMISC) /* set promiscuous mode */
2214 + recognise |= ETHARC_pro_m;
2215 +
2216 + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
2217 + recognise |= ETHARC_am_m; /* all multicast & bcast */
2218 + else if (dev->mc_count > 0) {
2219 + DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
2220 + recognise |= ETHARC_am_m; /* for the time being */
2221 + }
2222 +
2223 + spin_lock_irqsave(&lp->lock, flags);
2224 + rc32434_writel(recognise, &lp->eth_regs->etharc);
2225 + spin_unlock_irqrestore(&lp->lock, flags);
2226 +}
2227 +
2228 +
2229 +static void rc32434_tx_timeout(struct net_device *dev)
2230 +{
2231 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2232 + unsigned long flags;
2233 +
2234 + spin_lock_irqsave(&lp->lock, flags);
2235 + rc32434_restart(dev);
2236 + spin_unlock_irqrestore(&lp->lock, flags);
2237 +
2238 +}
2239 +
2240 +
2241 +/*
2242 + * Initialize the RC32434 ethernet controller.
2243 + */
2244 +static int rc32434_init(struct net_device *dev)
2245 +{
2246 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2247 + int i, j;
2248 +
2249 + /* Disable DMA */
2250 + rc32434_abort_tx(dev);
2251 + rc32434_abort_rx(dev);
2252 +
2253 + /* reset ethernet logic */
2254 + rc32434_writel(0, &lp->eth_regs->ethintfc);
2255 + while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
2256 + dev->trans_start = jiffies;
2257 +
2258 + /* Enable Ethernet Interface */
2259 + rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
2260 +
2261 +#ifndef CONFIG_IDT_USE_NAPI
2262 + tasklet_disable(lp->rx_tasklet);
2263 +#endif
2264 + tasklet_disable(lp->tx_tasklet);
2265 +
2266 + /* Initialize the transmit Descriptors */
2267 + for (i = 0; i < RC32434_NUM_TDS; i++) {
2268 + lp->td_ring[i].control = DMAD_iof_m;
2269 + lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
2270 + lp->td_ring[i].ca = 0;
2271 + lp->td_ring[i].link = 0;
2272 + if (lp->tx_skb[i] != NULL) {
2273 + dev_kfree_skb_any(lp->tx_skb[i]);
2274 + lp->tx_skb[i] = NULL;
2275 + }
2276 + }
2277 + lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0;
2278 + lp-> tx_chain_status = empty;
2279 +
2280 + /*
2281 + * Initialize the receive descriptors so that they
2282 + * become a circular linked list, ie. let the last
2283 + * descriptor point to the first again.
2284 + */
2285 + for (i=0; i<RC32434_NUM_RDS; i++) {
2286 + struct sk_buff *skb = lp->rx_skb[i];
2287 +
2288 + if (lp->rx_skb[i] == NULL) {
2289 + skb = dev_alloc_skb(RC32434_RBSIZE + 2);
2290 + if (skb == NULL) {
2291 + ERR("No memory in the system\n");
2292 + for (j = 0; j < RC32434_NUM_RDS; j ++)
2293 + if (lp->rx_skb[j] != NULL)
2294 + dev_kfree_skb_any(lp->rx_skb[j]);
2295 +
2296 + return 1;
2297 + }
2298 + else {
2299 + skb->dev = dev;
2300 + skb_reserve(skb, 2);
2301 + lp->rx_skb[i] = skb;
2302 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2303 +
2304 + }
2305 + }
2306 + lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
2307 + lp->rd_ring[i].devcs = 0;
2308 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2309 + lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
2310 +
2311 + }
2312 + /* loop back */
2313 + lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
2314 + lp->rx_next_done = 0;
2315 +
2316 + lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
2317 + lp->rx_chain_head = 0;
2318 + lp->rx_chain_tail = 0;
2319 + lp->rx_chain_status = empty;
2320 +
2321 + rc32434_writel(0, &lp->rx_dma_regs->dmas);
2322 + /* Start Rx DMA */
2323 + rc32434_start_rx(lp, &lp->rd_ring[0]);
2324 +
2325 + /* Enable F E bit in Tx DMA */
2326 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2327 + /* Enable D H E bit in Rx DMA */
2328 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
2329 +
2330 + /* Accept only packets destined for this Ethernet device address */
2331 + rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
2332 +
2333 + /* Set all Ether station address registers to their initial values */
2334 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
2335 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
2336 +
2337 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
2338 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
2339 +
2340 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
2341 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
2342 +
2343 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
2344 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
2345 +
2346 +
2347 + /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
2348 + rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
2349 + //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode
2350 +
2351 + /* Back to back inter-packet-gap */
2352 + rc32434_writel(0x15, &lp->eth_regs->ethipgt);
2353 + /* Non - Back to back inter-packet-gap */
2354 + rc32434_writel(0x12, &lp->eth_regs->ethipgr);
2355 +
2356 + /* Management Clock Prescaler Divisor */
2357 + /* Clock independent setting */
2358 + rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
2359 + &lp->eth_regs->ethmcp);
2360 +
2361 + /* don't transmit until fifo contains 48b */
2362 + rc32434_writel(48, &lp->eth_regs->ethfifott);
2363 +
2364 + rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
2365 +
2366 +#ifndef CONFIG_IDT_USE_NAPI
2367 + tasklet_enable(lp->rx_tasklet);
2368 +#endif
2369 + tasklet_enable(lp->tx_tasklet);
2370 +
2371 + netif_start_queue(dev);
2372 +
2373 +
2374 + return 0;
2375 +
2376 +}
2377 +
2378 +
2379 +#ifndef MODULE
2380 +
2381 +static int __init rc32434_setup(char *options)
2382 +{
2383 + /* no options yet */
2384 + return 1;
2385 +}
2386 +
2387 +static int __init rc32434_setup_ethaddr0(char *options)
2388 +{
2389 + memcpy(mac0, options, 17);
2390 + mac0[17]= '\0';
2391 + return 1;
2392 +}
2393 +
2394 +__setup("rc32434eth=", rc32434_setup);
2395 +__setup("ethaddr0=", rc32434_setup_ethaddr0);
2396 +
2397 +
2398 +#endif /* MODULE */
2399 +
2400 +module_init(rc32434_init_module);
2401 +module_exit(rc32434_cleanup_module);
2402 +
2403 +
2404 +
2405 +
2406 +
2407 +
2408 +
2409 +
2410 +
2411 +
2412 +
2413 +
2414 +
2415 +
2416 diff -Nur linux-2.6.15/drivers/net/rc32434_eth.h linux-2.6.15-openwrt/drivers/net/rc32434_eth.h
2417 --- linux-2.6.15/drivers/net/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
2418 +++ linux-2.6.15-openwrt/drivers/net/rc32434_eth.h 2006-01-10 00:32:33.000000000 +0100
2419 @@ -0,0 +1,187 @@
2420 +/**************************************************************************
2421 + *
2422 + * BRIEF MODULE DESCRIPTION
2423 + * Definitions for IDT RC32434 on-chip ethernet controller.
2424 + *
2425 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2426 + *
2427 + * This program is free software; you can redistribute it and/or modify it
2428 + * under the terms of the GNU General Public License as published by the
2429 + * Free Software Foundation; either version 2 of the License, or (at your
2430 + * option) any later version.
2431 + *
2432 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2433 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2434 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2435 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2436 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2437 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2438 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2439 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2440 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2441 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2442 + *
2443 + * You should have received a copy of the GNU General Public License along
2444 + * with this program; if not, write to the Free Software Foundation, Inc.,
2445 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2446 + *
2447 + *
2448 + **************************************************************************
2449 + * May 2004 rkt, neb
2450 + *
2451 + * Initial Release
2452 + *
2453 + * Aug 2004
2454 + *
2455 + * Added NAPI
2456 + *
2457 + **************************************************************************
2458 + */
2459 +
2460 +
2461 +#include <asm/idt-boards/rc32434/rc32434.h>
2462 +#include <asm/idt-boards/rc32434/rc32434_dma_v.h>
2463 +#include <asm/idt-boards/rc32434/rc32434_eth_v.h>
2464 +
2465 +#define RC32434_DEBUG 2
2466 +//#define RC32434_PROC_DEBUG
2467 +#undef RC32434_DEBUG
2468 +
2469 +#ifdef RC32434_DEBUG
2470 +
2471 +/* use 0 for production, 1 for verification, >2 for debug */
2472 +static int rc32434_debug = RC32434_DEBUG;
2473 +#define ASSERT(expr) \
2474 + if(!(expr)) { \
2475 + printk( "Assertion failed! %s,%s,%s,line=%d\n", \
2476 + #expr,__FILE__,__FUNCTION__,__LINE__); }
2477 +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2478 +#else
2479 +#define ASSERT(expr) do {} while (0)
2480 +#define DBG(lvl, format, arg...) do {} while (0)
2481 +#endif
2482 +
2483 +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2484 +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
2485 +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
2486 +
2487 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
2488 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
2489 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
2490 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
2491 +
2492 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
2493 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
2494 +
2495 +/* the following must be powers of two */
2496 +#ifdef CONFIG_IDT_USE_NAPI
2497 +#define RC32434_NUM_RDS 64 /* number of receive descriptors */
2498 +#define RC32434_NUM_TDS 64 /* number of transmit descriptors */
2499 +#else
2500 +#define RC32434_NUM_RDS 128 /* number of receive descriptors */
2501 +#define RC32434_NUM_TDS 128 /* number of transmit descriptors */
2502 +#endif
2503 +
2504 +#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
2505 +#define RC32434_RDS_MASK (RC32434_NUM_RDS-1)
2506 +#define RC32434_TDS_MASK (RC32434_NUM_TDS-1)
2507 +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
2508 +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
2509 +
2510 +#define RC32434_TX_TIMEOUT HZ * 100
2511 +
2512 +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
2513 +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
2514 +
2515 +enum status { filled, empty};
2516 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
2517 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
2518 +
2519 +
2520 +/* Information that need to be kept for each board. */
2521 +struct rc32434_local {
2522 + ETH_t eth_regs;
2523 + DMA_Chan_t rx_dma_regs;
2524 + DMA_Chan_t tx_dma_regs;
2525 + volatile DMAD_t td_ring; /* transmit descriptor ring */
2526 + volatile DMAD_t rd_ring; /* receive descriptor ring */
2527 +
2528 + struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */
2529 + struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */
2530 +
2531 +#ifndef CONFIG_IDT_USE_NAPI
2532 + struct tasklet_struct * rx_tasklet;
2533 +#endif
2534 + struct tasklet_struct * tx_tasklet;
2535 +
2536 + int rx_next_done;
2537 + int rx_chain_head;
2538 + int rx_chain_tail;
2539 + enum status rx_chain_status;
2540 +
2541 + int tx_next_done;
2542 + int tx_chain_head;
2543 + int tx_chain_tail;
2544 + enum status tx_chain_status;
2545 + int tx_count;
2546 + int tx_full;
2547 +
2548 + struct timer_list mii_phy_timer;
2549 + unsigned long duplex_mode;
2550 +
2551 + int rx_irq;
2552 + int tx_irq;
2553 + int ovr_irq;
2554 + int und_irq;
2555 +
2556 + struct net_device_stats stats;
2557 + spinlock_t lock;
2558 +
2559 + /* debug /proc entry */
2560 + struct proc_dir_entry *ps;
2561 + int dma_halt_cnt; int dma_run_cnt;
2562 +};
2563 +
2564 +extern unsigned int idt_cpu_freq;
2565 +
2566 +/* Index to functions, as function prototypes. */
2567 +static int rc32434_open(struct net_device *dev);
2568 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
2569 +static void rc32434_mii_handler(unsigned long data);
2570 +static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2571 +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2572 +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2573 +#ifdef RC32434_REVISION
2574 +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2575 +#endif
2576 +static int rc32434_close(struct net_device *dev);
2577 +static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
2578 +static void rc32434_multicast_list(struct net_device *dev);
2579 +static int rc32434_init(struct net_device *dev);
2580 +static void rc32434_tx_timeout(struct net_device *dev);
2581 +
2582 +static void rc32434_tx_tasklet(unsigned long tx_data_dev);
2583 +#ifdef CONFIG_IDT_USE_NAPI
2584 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
2585 +#else
2586 +static void rc32434_rx_tasklet(unsigned long rx_data_dev);
2587 +#endif
2588 +static void rc32434_cleanup_module(void);
2589 +static int rc32434_probe(int port_num);
2590 +int rc32434_init_module(void);
2591 +
2592 +
2593 +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
2594 +{
2595 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
2596 + rc32434_writel(0x10, &ch->dmac);
2597 +
2598 + while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
2599 + dev->trans_start = jiffies;
2600 +
2601 + rc32434_writel(0, &ch->dmas);
2602 + }
2603 +
2604 + rc32434_writel(0, &ch->dmadptr);
2605 + rc32434_writel(0, &ch->dmandptr);
2606 +}
2607 diff -Nur linux-2.6.15/include/asm-mips/bootinfo.h linux-2.6.15-openwrt/include/asm-mips/bootinfo.h
2608 --- linux-2.6.15/include/asm-mips/bootinfo.h 2006-01-03 04:21:10.000000000 +0100
2609 +++ linux-2.6.15-openwrt/include/asm-mips/bootinfo.h 2006-01-10 00:32:33.000000000 +0100
2610 @@ -218,6 +218,17 @@
2611 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
2612 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
2613
2614 +
2615 +/*
2616 + * Valid machtype for group ARUBA
2617 + */
2618 +#define MACH_GROUP_ARUBA 23
2619 +#define MACH_ARUBA_UNKNOWN 0
2620 +#define MACH_ARUBA_AP60 1
2621 +#define MACH_ARUBA_AP65 2
2622 +#define MACH_ARUBA_AP70 3
2623 +#define MACH_ARUBA_AP40 4
2624 +
2625 #define CL_SIZE COMMAND_LINE_SIZE
2626
2627 const char *get_system_type(void);
2628 diff -Nur linux-2.6.15/include/asm-mips/cpu.h linux-2.6.15-openwrt/include/asm-mips/cpu.h
2629 --- linux-2.6.15/include/asm-mips/cpu.h 2006-01-03 04:21:10.000000000 +0100
2630 +++ linux-2.6.15-openwrt/include/asm-mips/cpu.h 2006-01-10 00:32:33.000000000 +0100
2631 @@ -53,6 +53,9 @@
2632 #define PRID_IMP_R12000 0x0e00
2633 #define PRID_IMP_R8000 0x1000
2634 #define PRID_IMP_PR4450 0x1200
2635 +#define PRID_IMP_RC32334 0x1800
2636 +#define PRID_IMP_RC32355 0x1900
2637 +#define PRID_IMP_RC32365 0x1900
2638 #define PRID_IMP_R4600 0x2000
2639 #define PRID_IMP_R4700 0x2100
2640 #define PRID_IMP_TX39 0x2200
2641 @@ -196,7 +199,8 @@
2642 #define CPU_34K 60
2643 #define CPU_PR4450 61
2644 #define CPU_SB1A 62
2645 -#define CPU_LAST 62
2646 +#define CPU_RC32300 63
2647 +#define CPU_LAST 63
2648
2649 /*
2650 * ISA Level encodings
2651 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32300.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32300.h
2652 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32300.h 1970-01-01 01:00:00.000000000 +0100
2653 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32300.h 2006-01-10 00:32:33.000000000 +0100
2654 @@ -0,0 +1,142 @@
2655 +/**************************************************************************
2656 + *
2657 + * BRIEF MODULE DESCRIPTION
2658 + * RC32300 helper routines
2659 + *
2660 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2661 + *
2662 + * This program is free software; you can redistribute it and/or modify it
2663 + * under the terms of the GNU General Public License as published by the
2664 + * Free Software Foundation; either version 2 of the License, or (at your
2665 + * option) any later version.
2666 + *
2667 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2668 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2669 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2670 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2671 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2672 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2673 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2674 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2675 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2676 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2677 + *
2678 + * You should have received a copy of the GNU General Public License along
2679 + * with this program; if not, write to the Free Software Foundation, Inc.,
2680 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2681 + *
2682 + *
2683 + **************************************************************************
2684 + * May 2004 P. Sadik.
2685 + *
2686 + * Initial Release
2687 + *
2688 + *
2689 + *
2690 + **************************************************************************
2691 + */
2692 +
2693 +#ifndef __IDT_RC32300_H__
2694 +#define __IDT_RC32300_H__
2695 +
2696 +#include <linux/delay.h>
2697 +#include <asm/io.h>
2698 +
2699 +
2700 +/* cpu pipeline flush */
2701 +static inline void rc32300_sync(void)
2702 +{
2703 + __asm__ volatile ("sync");
2704 +}
2705 +
2706 +static inline void rc32300_sync_udelay(int us)
2707 +{
2708 + __asm__ volatile ("sync");
2709 + udelay(us);
2710 +}
2711 +
2712 +static inline void rc32300_sync_delay(int ms)
2713 +{
2714 + __asm__ volatile ("sync");
2715 + mdelay(ms);
2716 +}
2717 +
2718 +/*
2719 + * Macros to access internal RC32300 registers. No byte
2720 + * swapping should be done when accessing the internal
2721 + * registers.
2722 + */
2723 +
2724 +static inline u8 rc32300_readb(unsigned long pa)
2725 +{
2726 + return *((volatile u8 *)KSEG1ADDR(pa));
2727 +}
2728 +static inline u16 rc32300_readw(unsigned long pa)
2729 +{
2730 + return *((volatile u16 *)KSEG1ADDR(pa));
2731 +}
2732 +static inline u32 rc32300_readl(unsigned long pa)
2733 +{
2734 + return *((volatile u32 *)KSEG1ADDR(pa));
2735 +}
2736 +static inline void rc32300_writeb(u8 val, unsigned long pa)
2737 +{
2738 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
2739 +}
2740 +static inline void rc32300_writew(u16 val, unsigned long pa)
2741 +{
2742 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
2743 +}
2744 +static inline void rc32300_writel(u32 val, unsigned long pa)
2745 +{
2746 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
2747 +}
2748 +
2749 +
2750 +#define local_readb __raw_readb
2751 +#define local_readw __raw_readw
2752 +#define local_readl __raw_readl
2753 +
2754 +#define local_writeb __raw_writeb
2755 +#define local_writew __raw_writew
2756 +#define local_writel __raw_writel
2757 +
2758 +
2759 +/*
2760 + * C access to CLZ and CLO instructions
2761 + * (count leading zeroes/ones).
2762 + */
2763 +static inline int rc32300_clz(unsigned long val)
2764 +{
2765 + int ret;
2766 + __asm__ volatile (
2767 + ".set\tnoreorder\n\t"
2768 + ".set\tnoat\n\t"
2769 + ".set\tmips32\n\t"
2770 + "clz\t%0,%1\n\t"
2771 + ".set\tmips0\n\t"
2772 + ".set\tat\n\t"
2773 + ".set\treorder"
2774 + : "=r" (ret)
2775 + : "r" (val));
2776 +
2777 + return ret;
2778 +}
2779 +static inline int rc32300_clo(unsigned long val)
2780 +{
2781 + int ret;
2782 + __asm__ volatile (
2783 + ".set\tnoreorder\n\t"
2784 + ".set\tnoat\n\t"
2785 + ".set\tmips32\n\t"
2786 + "clo\t%0,%1\n\t"
2787 + ".set\tmips0\n\t"
2788 + ".set\tat\n\t"
2789 + ".set\treorder"
2790 + : "=r" (ret)
2791 + : "r" (val));
2792 +
2793 + return ret;
2794 +}
2795 +
2796 +#endif // __IDT_RC32300_H__
2797 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32334.h
2798 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32334.h 1970-01-01 01:00:00.000000000 +0100
2799 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32334.h 2006-01-10 00:32:33.000000000 +0100
2800 @@ -0,0 +1,207 @@
2801 +/**************************************************************************
2802 + *
2803 + * BRIEF MODULE DESCRIPTION
2804 + * Definitions for IDT RC32334 CPU.
2805 + *
2806 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2807 + *
2808 + * This program is free software; you can redistribute it and/or modify it
2809 + * under the terms of the GNU General Public License as published by the
2810 + * Free Software Foundation; either version 2 of the License, or (at your
2811 + * option) any later version.
2812 + *
2813 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2814 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2815 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2816 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2817 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2818 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2819 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2820 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2821 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2822 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2823 + *
2824 + * You should have received a copy of the GNU General Public License along
2825 + * with this program; if not, write to the Free Software Foundation, Inc.,
2826 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2827 + *
2828 + *
2829 + **************************************************************************
2830 + * May 2004 P. Sadik.
2831 + *
2832 + * Initial Release
2833 + *
2834 + *
2835 + *
2836 + **************************************************************************
2837 + */
2838 +
2839 +
2840 +#ifndef __IDT_RC32334_H__
2841 +#define __IDT_RC32334_H__
2842 +
2843 +#include <linux/delay.h>
2844 +#include <asm/io.h>
2845 +
2846 +/* Base address of internal registers */
2847 +#define RC32334_REG_BASE 0x18000000
2848 +
2849 +/* CPU and IP Bus Control */
2850 +#define CPU_PORT_WIDTH 0xffffe200 // virtual!
2851 +#define CPU_BTA 0xffffe204 // virtual!
2852 +#define CPU_BUSERR_ADDR 0xffffe208 // virtual!
2853 +#define CPU_IP_BTA (RC32334_REG_BASE + 0x0000)
2854 +#define CPU_IP_ADDR_LATCH (RC32334_REG_BASE + 0x0004)
2855 +#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
2856 +#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
2857 +#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
2858 +#define CPU_IP_SYSID (RC32334_REG_BASE + 0x0018)
2859 +
2860 +/* Memory Controller */
2861 +#define MEM_BASE_BANK0 (RC32334_REG_BASE + 0x0080)
2862 +#define MEM_MASK_BANK0 (RC32334_REG_BASE + 0x0084)
2863 +#define MEM_CNTL_BANK0 (RC32334_REG_BASE + 0x0200)
2864 +#define MEM_BASE_BANK1 (RC32334_REG_BASE + 0x0088)
2865 +#define MEM_MASK_BANK1 (RC32334_REG_BASE + 0x008c)
2866 +#define MEM_CNTL_BANK1 (RC32334_REG_BASE + 0x0204)
2867 +#define MEM_CNTL_BANK2 (RC32334_REG_BASE + 0x0208)
2868 +#define MEM_CNTL_BANK3 (RC32334_REG_BASE + 0x020c)
2869 +#define MEM_CNTL_BANK4 (RC32334_REG_BASE + 0x0210)
2870 +#define MEM_CNTL_BANK5 (RC32334_REG_BASE + 0x0214)
2871 +
2872 +/* PCI Controller */
2873 +#define PCI_INTR_PEND (RC32334_REG_BASE + 0x05b0)
2874 +#define PCI_INTR_MASK (RC32334_REG_BASE + 0x05b4)
2875 +#define PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05b8)
2876 +#define CPU2PCI_INTR_PEND (RC32334_REG_BASE + 0x05c0)
2877 +#define CPU2PCI_INTR_MASK (RC32334_REG_BASE + 0x05c4)
2878 +#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
2879 +#define PCI2CPU_INTR_PEND (RC32334_REG_BASE + 0x05d0)
2880 +#define PCI2CPU_INTR_MASK (RC32334_REG_BASE + 0x05d4)
2881 +#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
2882 +#define PCI_MEM1_BASE (RC32334_REG_BASE + 0x20b0)
2883 +#define PCI_MEM2_BASE (RC32334_REG_BASE + 0x20b8)
2884 +#define PCI_MEM3_BASE (RC32334_REG_BASE + 0x20c0)
2885 +#define PCI_IO1_BASE (RC32334_REG_BASE + 0x20c8)
2886 +#define PCI_ARBITRATION (RC32334_REG_BASE + 0x20e0)
2887 +#define PCI_CPU_MEM1_BASE (RC32334_REG_BASE + 0x20e8)
2888 +#define PCI_CPU_IO_BASE (RC32334_REG_BASE + 0x2100)
2889 +#define PCI_CFG_CNTL (RC32334_REG_BASE + 0x2cf8)
2890 +#define PCI_CFG_DATA (RC32334_REG_BASE + 0x2cfc)
2891 +
2892 +/* Timers */
2893 +#define TIMER0_CNTL (RC32334_REG_BASE + 0x0700)
2894 +#define TIMER0_COUNT (RC32334_REG_BASE + 0x0704)
2895 +#define TIMER0_COMPARE (RC32334_REG_BASE + 0x0708)
2896 +#define TIMER_REG_OFFSET 0x10
2897 +
2898 +/* Programmable I/O */
2899 +#define PIO_DATA0 (RC32334_REG_BASE + 0x0600)
2900 +#define PIO_DATA1 (RC32334_REG_BASE + 0x0610)
2901 +
2902 +/*
2903 + * DMA
2904 + *
2905 + * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
2906 + *
2907 + * DMA0: 18001400
2908 + * DMA1: 18001440
2909 + * DMA2: 18001900
2910 + * DMA3: 18001940
2911 + * NB: dma number must be immediate value or variable.
2912 + * It MUST NOT be a function since it would get called twice!
2913 + */
2914 +#define DMA_IO(n) (((n)>1?0x500:0)+((n)&1?0x40:0))
2915 +
2916 +#define RC32300_IO_DMA(n) (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
2917 +#define RC32300_DMA_CONFREG(n) RC32300_IO_DMA(n)
2918 +#define RC32300_DMA_BASEREG(n) (RC32300_IO_DMA(n)+0x4)
2919 +
2920 +#define RC32300_DMA_CURRREG(n) (RC32300_IO_DMA(n)+0x8)
2921 +#define RC32300_DMA_STATREG(n) (RC32300_IO_DMA(n)+0x10)
2922 +#define RC32300_DMA_SRCREG(n) (RC32300_IO_DMA(n)+0x14)
2923 +#define RC32300_DMA_DSTREG(n) (RC32300_IO_DMA(n)+0x18)
2924 +#define RC32300_DMA_NEXTREG(n) (RC32300_IO_DMA(n)+0x1c)
2925 +
2926 +#define RC32300_DMA_IRQ(n) (GROUP7_IRQ_BASE+5*(n))
2927 +
2928 +/* Expansion Interrupt Controller */
2929 +#define IC_GROUP0_PEND (RC32334_REG_BASE + 0x0500)
2930 +#define IC_GROUP0_MASK (RC32334_REG_BASE + 0x0504)
2931 +#define IC_GROUP0_CLEAR (RC32334_REG_BASE + 0x0508)
2932 +#define IC_GROUP_OFFSET 0x10
2933 +
2934 +#define NUM_INTR_GROUPS 15
2935 +/*
2936 + * The IRQ mapping is as follows:
2937 + *
2938 + * IRQ Mapped To
2939 + * --- -------------------
2940 + * 0 SW0 (IP0) SW0 intr
2941 + * 1 SW1 (IP1) SW1 intr
2942 + * 2 Int0 (IP2) board-specific
2943 + * 3 Int1 (IP3) board-specific
2944 + * 4 Int2 (IP4) board-specific
2945 + * - Int3 (IP5) not used, mapped to IRQ's 8 and up
2946 + * 6 Int4 (IP6) board-specific
2947 + * 7 Int5 (IP7) CP0 Timer
2948 + *
2949 + * IRQ's 8 and up are all mapped to Int3 (IP5), which
2950 + * internally on the RC32334 is routed to the Expansion
2951 + * Interrupt Controller.
2952 + */
2953 +#define MIPS_CPU_TIMER_IRQ 7
2954 +
2955 +#define GROUP1_IRQ_BASE 8 // bus error
2956 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 1) // PIO active low
2957 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 12) // PIO active high
2958 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 8) // Timer Rollovers
2959 +#define GROUP5_IRQ_BASE (GROUP4_IRQ_BASE + 8) // UART0
2960 +#define GROUP6_IRQ_BASE (GROUP5_IRQ_BASE + 3) // UART1
2961 +#define GROUP7_IRQ_BASE (GROUP6_IRQ_BASE + 3) // DMA Ch0
2962 +#define GROUP8_IRQ_BASE (GROUP7_IRQ_BASE + 5) // DMA Ch1
2963 +#define GROUP9_IRQ_BASE (GROUP8_IRQ_BASE + 5) // DMA Ch2
2964 +#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5) // DMA Ch3
2965 +#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5) // PCI Ctlr errors
2966 +#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4) // PCI Satellite Mode
2967 +#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
2968 +#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4) // SPI
2969 +
2970 +#define RC32334_NR_IRQS (GROUP14_IRQ_BASE + 1)
2971 +
2972 +/* 16550 UARTs */
2973 +#ifdef __MIPSEB__
2974 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
2975 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
2976 +#else
2977 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
2978 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
2979 +#endif
2980 +
2981 +#define RC32300_UART0_IRQ GROUP5_IRQ_BASE
2982 +#define RC32300_UART1_IRQ GROUP6_IRQ_BASE
2983 +
2984 +#define IDT_CLOCK_MULT 2
2985 +
2986 +/* NVRAM */
2987 +#define NVRAM_BASE 0x12000000
2988 +#define NVRAM_ENVSIZE_OFF 4
2989 +#define NVRAM_ENVSTART_OFF 0x40
2990 +
2991 +/* LCD 4-digit display */
2992 +#define LCD_CLEAR 0x14000400
2993 +#define LCD_DIGIT0 0x1400000f
2994 +#define LCD_DIGIT1 0x14000008
2995 +#define LCD_DIGIT2 0x14000007
2996 +#define LCD_DIGIT3 0x14000003
2997 +
2998 +/* Interrupts routed on 79S334A board (see rc32334.h) */
2999 +#define RC32334_SCC8530_IRQ 2
3000 +#define RC32334_PCI_INTA_IRQ 3
3001 +#define RC32334_PCI_INTB_IRQ 4
3002 +#define RC32334_PCI_INTC_IRQ 6
3003 +#define RC32334_PCI_INTD_IRQ 7
3004 +
3005 +#define RAM_SIZE (32*1024*1024)
3006 +
3007 +#endif // __IDT_RC32334_H__
3008 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
3009 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 1970-01-01 01:00:00.000000000 +0100
3010 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 2006-01-10 00:32:33.000000000 +0100
3011 @@ -0,0 +1,206 @@
3012 +/**************************************************************************
3013 + *
3014 + * BRIEF MODULE DESCRIPTION
3015 + * DMA controller defines on IDT RC32355
3016 + *
3017 + * Copyright 2004 IDT Inc.
3018 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3019 + *
3020 + *
3021 + * This program is free software; you can redistribute it and/or modify it
3022 + * under the terms of the GNU General Public License as published by the
3023 + * Free Software Foundation; either version 2 of the License, or (at your
3024 + * option) any later version.
3025 + *
3026 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3027 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3028 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3029 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3030 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3031 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3032 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3033 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3034 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3035 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3036 + *
3037 + * You should have received a copy of the GNU General Public License along
3038 + * with this program; if not, write to the Free Software Foundation, Inc.,
3039 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3040 + *
3041 + *
3042 + * May 2004 rkt
3043 + * Initial Release
3044 + *
3045 + **************************************************************************
3046 + */
3047 +
3048 +#ifndef BANYAN_DMA_H
3049 +#define BANYAN_DMA_H
3050 +#include <asm/idt-boards/rc32300/rc32300.h>
3051 +
3052 +/*
3053 + * An image of one RC32355 dma channel registers
3054 + */
3055 +typedef struct {
3056 + u32 dmac;
3057 + u32 dmas;
3058 + u32 dmasm;
3059 + u32 dmadptr;
3060 + u32 dmandptr;
3061 +} rc32355_dma_ch_t;
3062 +
3063 +/*
3064 + * An image of all RC32355 dma channel registers
3065 + */
3066 +typedef struct {
3067 + rc32355_dma_ch_t ch[16];
3068 +} rc32355_dma_regs_t;
3069 +
3070 +
3071 +#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
3072 +
3073 +
3074 +/* DMAC register layout */
3075 +
3076 +#define DMAC_RUN 0x1 /* Halts processing when cleared */
3077 +#define DMAC_DM 0x2 /* Done Mask, ignore DMA events */
3078 +#define DMAC_MODE_MASK 0xC /* DMA operating mode */
3079 +
3080 +#define DMAC_MODE_AUTO 0x0 /* DMA Auto Request Mode */
3081 +#define DMAC_MODE_BURST 0x4 /* DMA Burst Request Mode */
3082 +#define DMAC_MODE_TFER 0x8 /* DMA Transfer Request Mode */
3083 +
3084 +/* DMAS and DMASM register layout */
3085 +
3086 +#define DMAS_F 0x01 /* Finished */
3087 +#define DMAS_D 0x02 /* Done */
3088 +#define DMAS_C 0x04 /* Chain */
3089 +#define DMAS_E 0x08 /* Error */
3090 +#define DMAS_H 0x10 /* Halt */
3091 +
3092 +/* Polling count for DMAS_H bit in DMAS register after halting DMA */
3093 +#define DMA_HALT_TIMEOUT 500
3094 +
3095 +
3096 +static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
3097 +{
3098 + int timeout=1;
3099 +
3100 + if (local_readl(&ch->dmac) & DMAC_RUN) {
3101 + local_writel(0, &ch->dmac);
3102 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
3103 + if (local_readl(&ch->dmas) & DMAS_H) {
3104 + local_writel(0, &ch->dmas);
3105 + break;
3106 + }
3107 + }
3108 + }
3109 +
3110 + return timeout ? 0 : 1;
3111 +}
3112 +
3113 +static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3114 +{
3115 + local_writel(0, &ch->dmandptr);
3116 + local_writel(dma_addr, &ch->dmadptr);
3117 +}
3118 +
3119 +static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3120 +{
3121 + local_writel(dma_addr, &ch->dmandptr);
3122 +}
3123 +
3124 +
3125 +/* The following can be used to describe DMA channels 0 to 15, and the */
3126 +/* sub device's needed to select them in the DMADESC_DS_MASK field */
3127 +
3128 +#define DMA_CHAN_ATM01 0 /* ATM interface 0,1 chan */
3129 +
3130 +#define DMA_CHAN_ATM0IN 0 /* ATM interface 0 input */
3131 +#define DMA_DEV_ATM0IN 0 /* ATM interface 0 input */
3132 +
3133 +#define DMA_CHAN_ATM1IN 0 /* ATM interface 1 input */
3134 +#define DMA_DEV_ATM1IN 1 /* ATM interface 1 input */
3135 +
3136 +#define DMA_CHAN_ATM0OUT 0 /* ATM interface 0 output */
3137 +#define DMA_DEV_ATM0OUT 2 /* ATM interface 0 output */
3138 +
3139 +#define DMA_CHAN_ATM1OUT 0 /* ATM interface 1 output */
3140 +#define DMA_DEV_ATM1OUT 3 /* ATM interface 1 output */
3141 +
3142 +/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
3143 +#define DMA_CHAN_ATMVCC(entry) ((entry)+1) /* ATM VC cache entry */
3144 +#define DMA_DEV_ATMVCC(entry) 0
3145 +
3146 +#define DMA_CHAN_MEMTOMEM 6 /* Memory to memory DMA */
3147 +#define DMA_DEV_MEMTOMEM 1 /* Memory to memory DMA */
3148 +
3149 +#define DMA_CHAN_ATMFMB0 7 /* ATM Frame Mode Buffer 0 */
3150 +#define DMA_DEV_ATMFMB0 1 /* ATM Frame Mode Buffer 0 */
3151 +
3152 +#define DMA_CHAN_ATMFMB1 8 /* ATM Frame Mode Buffer 1 */
3153 +#define DMA_DEV_ATMFMB1 1 /* ATM Frame Mode Buffer 1 */
3154 +
3155 +#define DMA_CHAN_ETHERIN 9 /* Ethernet input */
3156 +#define DMA_DEV_ETHERIN 0 /* Ethernet input */
3157 +
3158 +#define DMA_CHAN_ETHEROUT 10 /* Ethernet output */
3159 +#define DMA_DEV_ETHEROUT 0 /* Ethernet output */
3160 +
3161 +#define DMA_CHAN_TDMIN 11 /* TDM Bus input */
3162 +#define DMA_DEV_TDMIN 0 /* TDM Bus input */
3163 +
3164 +#define DMA_CHAN_TDMOUT 12 /* TDM Bus output */
3165 +#define DMA_DEV_TDMOUT 0 /* TDM Bus output */
3166 +
3167 +#define DMA_CHAN_USBIN 13 /* USB input */
3168 +#define DMA_DEV_USBIN 0 /* USB input */
3169 +
3170 +#define DMA_CHAN_USBOUT 14 /* USB output */
3171 +#define DMA_DEV_USBOUT 0 /* USB output */
3172 +
3173 +#define DMA_CHAN_EXTERN 15 /* External DMA */
3174 +#define DMA_DEV_EXTERN 0 /* External DMA */
3175 +
3176 +/*
3177 + * An RC32355 dma descriptor in system memory
3178 + */
3179 +typedef struct {
3180 + u32 cmdstat; /* control and status */
3181 + u32 curr_addr; /* current address of data */
3182 + u32 devcs; /* peripheral-specific control and status */
3183 + u32 link; /* link to next descriptor */
3184 +} rc32355_dma_desc_t;
3185 +
3186 +/* Values for the descriptor cmdstat word */
3187 +
3188 +#define DMADESC_F 0x80000000u /* Finished bit */
3189 +#define DMADESC_D 0x40000000u /* Done bit */
3190 +#define DMADESC_T 0x20000000u /* Terminated bit */
3191 +#define DMADESC_IOD 0x10000000u /* Interrupt On Done */
3192 +#define DMADESC_IOF 0x08000000u /* Interrupt On Finished */
3193 +#define DMADESC_COD 0x04000000u /* Chain On Done */
3194 +#define DMADESC_COF 0x02000000u /* Chain On Finished */
3195 +
3196 +#define DMADESC_DEVCMD_MASK 0x01C00000u /* Device Command mask */
3197 +#define DMADESC_DEVCMD_SHIFT 22 /* Device Command shift */
3198 +
3199 +#define DMADESC_DS_MASK 0x00300000u /* Device Select mask */
3200 +#define DMADESC_DS_SHIFT 20 /* Device Select shift */
3201 +
3202 +#define DMADESC_COUNT_MASK 0x0003FFFFu /* Byte Count mask */
3203 +#define DMADESC_COUNT_SHIFT 0 /* Byte Count shift */
3204 +
3205 +#define IS_DMA_FINISHED(X) ( ( (X) & DMADESC_F ) >> 31) /* F Bit */
3206 +#define IS_DMA_DONE(X) ( ( (X) & DMADESC_D ) >> 30) /* D Bit */
3207 +#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29) /* T Bit */
3208 +#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
3209 +
3210 +#define DMA_DEVCMD(devcmd) \
3211 + (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
3212 +#define DMA_DS(ds) \
3213 + (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
3214 +#define DMA_COUNT(count) \
3215 + ((count) & DMADESC_COUNT_MASK)
3216 +
3217 +#endif /* RC32355_DMA_H */
3218 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
3219 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 1970-01-01 01:00:00.000000000 +0100
3220 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 2006-01-10 00:32:33.000000000 +0100
3221 @@ -0,0 +1,442 @@
3222 +/**************************************************************************
3223 + *
3224 + * BRIEF MODULE DESCRIPTION
3225 + * Ethernet registers on IDT RC32355
3226 + *
3227 + * Copyright 2004 IDT Inc.
3228 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3229 + *
3230 + *
3231 + * This program is free software; you can redistribute it and/or modify it
3232 + * under the terms of the GNU General Public License as published by the
3233 + * Free Software Foundation; either version 2 of the License, or (at your
3234 + * option) any later version.
3235 + *
3236 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3237 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3238 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3239 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3240 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3241 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3242 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3243 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3244 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3245 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3246 + *
3247 + * You should have received a copy of the GNU General Public License along
3248 + * with this program; if not, write to the Free Software Foundation, Inc.,
3249 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3250 + *
3251 + *
3252 + * May 2004 rkt
3253 + * Initial Release
3254 + *
3255 + **************************************************************************
3256 + */
3257 +
3258 +
3259 +#ifndef RC32355_ETHER_H
3260 +#define RC32355_ETHER_H
3261 +
3262 +#include <asm/idt-boards/rc32300/rc32355_dma.h>
3263 +
3264 +/*
3265 + * A partial image of the RC32355 ethernet registers
3266 + */
3267 +typedef struct {
3268 + u32 ethintfc;
3269 + u32 ethfifott;
3270 + u32 etharc;
3271 + u32 ethhash0;
3272 + u32 ethhash1;
3273 + u32 ethfifost;
3274 + u32 ethfifos;
3275 + u32 ethodeops;
3276 + u32 ethis;
3277 + u32 ethos;
3278 + u32 ethmcp;
3279 + u32 _u1;
3280 + u32 ethid;
3281 + u32 _u2;
3282 + u32 _u3;
3283 + u32 _u4;
3284 + u32 ethod;
3285 + u32 _u5;
3286 + u32 _u6;
3287 + u32 _u7;
3288 + u32 ethodeop;
3289 + u32 _u8[43];
3290 + u32 ethsal0;
3291 + u32 ethsah0;
3292 + u32 ethsal1;
3293 + u32 ethsah1;
3294 + u32 ethsal2;
3295 + u32 ethsah2;
3296 + u32 ethsal3;
3297 + u32 ethsah3;
3298 + u32 ethrbc;
3299 + u32 ethrpc;
3300 + u32 ethrupc;
3301 + u32 ethrfc;
3302 + u32 ethtbc;
3303 + u32 ethgpf;
3304 + u32 _u9[50];
3305 + u32 ethmac1;
3306 + u32 ethmac2;
3307 + u32 ethipgt;
3308 + u32 ethipgr;
3309 + u32 ethclrt;
3310 + u32 ethmaxf;
3311 + u32 _u10;
3312 + u32 ethmtest;
3313 + u32 miimcfg;
3314 + u32 miimcmd;
3315 + u32 miimaddr;
3316 + u32 miimwtd;
3317 + u32 miimrdd;
3318 + u32 miimind;
3319 + u32 _u11;
3320 + u32 _u12;
3321 + u32 ethcfsa0;
3322 + u32 ethcfsa1;
3323 + u32 ethcfsa2;
3324 +} rc32355_eth_regs_t;
3325 +
3326 +#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
3327 +
3328 +#define ETH_INTFC (RC32355_ETH_BASE + 0x000) /* INTerFace Control */
3329 +#define ETH_FIFOTT (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold */
3330 +#define ETH_ARC (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl */
3331 +#define ETH_HASH0 (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
3332 +#define ETH_HASH1 (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
3333 +#define ETH_FIFOST (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
3334 +#define ETH_FIFOS (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
3335 +#define ETH_ODEOPS (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
3336 +#define ETH_IS (RC32355_ETH_BASE + 0x020) /* Input Status */
3337 +#define ETH_OS (RC32355_ETH_BASE + 0x024) /* Output Status */
3338 +#define ETH_MCP (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
3339 +#define ETH_ID (RC32355_ETH_BASE + 0x030) /* Input Data register */
3340 +#define ETH_OD (RC32355_ETH_BASE + 0x040) /* Output Data register */
3341 +#define ETH_ODEOP (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
3342 +
3343 +/* for n in { 0, 1, 2, 3 } */
3344 +#define ETH_SAL(n) (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
3345 +#define ETH_SAH(n) (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
3346 +
3347 +#define ETH_RBC (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
3348 +#define ETH_RPC (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
3349 +#define ETH_RUPC (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
3350 +#define ETH_RFC (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
3351 +#define ETH_TBC (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
3352 +#define ETH_GPF (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
3353 +#define ETH_MAC1 (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
3354 +#define ETH_MAC2 (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
3355 +#define ETH_IPGT (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
3356 +#define ETH_IPGR (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
3357 +#define ETH_CLRT (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
3358 +#define ETH_MAXF (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
3359 +#define ETH_MTEST (RC32355_ETH_BASE + 0x21C) /* MAC Test */
3360 +
3361 +#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
3362 +#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command */
3363 +#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
3364 +#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
3365 +#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
3366 +#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
3367 +
3368 +/* for n in { 0, 1, 2 } */
3369 +#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4)) /* Station Addr */
3370 +
3371 +
3372 +/*
3373 + * Register Interpretations follow
3374 + */
3375 +
3376 +/******************************************************************************
3377 + * ETHINTFC register
3378 + *****************************************************************************/
3379 +
3380 +#define ETHERINTFC_EN (1<<0)
3381 +#define ETHERINTFC_ITS (1<<1)
3382 +#define ETHERINTFC_RES (1<<2)
3383 +#define ETHERINTFC_RIP (1<<2)
3384 +#define ETHERINTFC_JAM (1<<3)
3385 +
3386 +/******************************************************************************
3387 + * ETHFIFOTT register
3388 + *****************************************************************************/
3389 +
3390 +#define ETHERFIFOTT_TTH(v) (((v)&0x3f)<<0)
3391 +
3392 +/******************************************************************************
3393 + * ETHARC register
3394 + *****************************************************************************/
3395 +
3396 +#define ETHERARC_PRO (1<<0)
3397 +#define ETHERARC_AM (1<<1)
3398 +#define ETHERARC_AFM (1<<2)
3399 +#define ETHERARC_AB (1<<3)
3400 +
3401 +/******************************************************************************
3402 + * ETHHASH registers
3403 + *****************************************************************************/
3404 +
3405 +#define ETHERHASH0(v) (((v)&0xffff)<<0)
3406 +#define ETHERHASH1(v) (((v)&0xffff)<<0)
3407 +
3408 +/******************************************************************************
3409 + * ETHSA registers
3410 + *****************************************************************************/
3411 +
3412 +#define ETHERSAL0(v) (((v)&0xffff)<<0)
3413 +#define ETHERSAL1(v) (((v)&0xffff)<<0)
3414 +#define ETHERSAL2(v) (((v)&0xffff)<<0)
3415 +#define ETHERSAL3(v) (((v)&0xffff)<<0)
3416 +#define ETHERSAH0(v) (((v)&0xff)<<0)
3417 +#define ETHERSAH1(v) (((v)&0xff)<<0)
3418 +#define ETHERSAH2(v) (((v)&0xff)<<0)
3419 +#define ETHERSAH3(v) (((v)&0xff)<<0)
3420 +
3421 +/******************************************************************************
3422 + * ETHFIFOST register
3423 + *****************************************************************************/
3424 +
3425 +#define ETHERFIFOST_IRTH(v) (((v)&0x3f)<<0)
3426 +#define ETHERFIFOST_ORTH(v) (((v)&0x3f)<<16)
3427 +
3428 +/******************************************************************************
3429 + * ETHFIFOS register
3430 + *****************************************************************************/
3431 +
3432 +#define ETHERFIFOS_IR (1<<0)
3433 +#define ETHERFIFOS_OR (1<<1)
3434 +#define ETHERFIFOS_OVR (1<<2)
3435 +#define ETHERFIFOS_UND (1<<3)
3436 +
3437 +/******************************************************************************
3438 + * DATA registers
3439 + *****************************************************************************/
3440 +
3441 +#define ETHERID(v) (((v)&0xffff)<<0)
3442 +#define ETHEROD(v) (((v)&0xffff)<<0)
3443 +
3444 +/******************************************************************************
3445 + * ETHODEOPS register
3446 + *****************************************************************************/
3447 +
3448 +#define ETHERODEOPS_SIZE(v) (((v)&0x3)<<0)
3449 +
3450 +/******************************************************************************
3451 + * ETHODEOP register
3452 + *****************************************************************************/
3453 +
3454 +#define ETHERODEOP(v) (((v)&0xffff)<<0)
3455 +
3456 +/******************************************************************************
3457 + * ETHIS register
3458 + *****************************************************************************/
3459 +
3460 +#define ETHERIS_EOP (1<<0)
3461 +#define ETHERIS_ROK (1<<2)
3462 +#define ETHERIS_FM (1<<3)
3463 +#define ETHERIS_MP (1<<4)
3464 +#define ETHERIS_BP (1<<5)
3465 +#define ETHERIS_VLT (1<<6)
3466 +#define ETHERIS_CF (1<<7)
3467 +#define ETHERIS_OVR (1<<8)
3468 +#define ETHERIS_CRC (1<<9)
3469 +#define ETHERIS_CV (1<<10)
3470 +#define ETHERIS_DB (1<<11)
3471 +#define ETHERIS_LE (1<<12)
3472 +#define ETHERIS_LOR (1<<13)
3473 +#define ETHERIS_SIZE(v) (((v)&0x3)<<14)
3474 +#define ETHERIS_LENGTH(v) (((v)&0xff)<<16)
3475 +
3476 +/******************************************************************************
3477 + * ETHOS register
3478 + *****************************************************************************/
3479 +
3480 +#define ETHEROS_T (1<<0)
3481 +#define ETHEROS_TOK (1<<6)
3482 +#define ETHEROS_MP (1<<7)
3483 +#define ETHEROS_BP (1<<8)
3484 +#define ETHEROS_UND (1<<9)
3485 +#define ETHEROS_OF (1<<10)
3486 +#define ETHEROS_ED (1<<11)
3487 +#define ETHEROS_EC (1<<12)
3488 +#define ETHEROS_LC (1<<13)
3489 +#define ETHEROS_TD (1<<14)
3490 +#define ETHEROS_CRC (1<<15)
3491 +#define ETHEROS_LE (1<<16)
3492 +#define ETHEROS_CC(v) (((v)&0xf)<<17)
3493 +#define ETHEROS_PFD (1<<21)
3494 +
3495 +/******************************************************************************
3496 + * Statistics registers
3497 + *****************************************************************************/
3498 +
3499 +#define ETHERRBC(v) (((v)&0xffff)<<0)
3500 +#define ETHERRPC(v) (((v)&0xffff)<<0)
3501 +#define ETHERRUPC(v) (((v)&0xffff)<<0)
3502 +#define ETHERRFC(v) (((v)&0xffff)<<0)
3503 +#define ETHERTBC(v) (((v)&0xffff)<<0)
3504 +
3505 +/******************************************************************************
3506 + * ETHGPF register
3507 + *****************************************************************************/
3508 +
3509 +#define ETHERGPF_PTV(v) (((v)&0xff)<<0)
3510 +
3511 +/******************************************************************************
3512 + * MAC registers
3513 + *****************************************************************************/
3514 +//ETHMAC1
3515 +#define ETHERMAC1_RE (1<<0)
3516 +#define ETHERMAC1_PAF (1<<1)
3517 +#define ETHERMAC1_RFC (1<<2)
3518 +#define ETHERMAC1_TFC (1<<3)
3519 +#define ETHERMAC1_LB (1<<4)
3520 +#define ETHERMAC1_MR (1<<15)
3521 +
3522 +//ETHMAC2
3523 +#define ETHERMAC2_FD (1<<0)
3524 +#define ETHERMAC2_FLC (1<<1)
3525 +#define ETHERMAC2_HFE (1<<2)
3526 +#define ETHERMAC2_DC (1<<3)
3527 +#define ETHERMAC2_CEN (1<<4)
3528 +#define ETHERMAC2_PE (1<<5)
3529 +#define ETHERMAC2_VPE (1<<6)
3530 +#define ETHERMAC2_APE (1<<7)
3531 +#define ETHERMAC2_PPE (1<<8)
3532 +#define ETHERMAC2_LPE (1<<9)
3533 +#define ETHERMAC2_NB (1<<12)
3534 +#define ETHERMAC2_BP (1<<13)
3535 +#define ETHERMAC2_ED (1<<14)
3536 +
3537 +//ETHIPGT
3538 +#define ETHERIPGT(v) (((v)&0x3f)<<0)
3539 +
3540 +//ETHIPGR
3541 +#define ETHERIPGR_IPGR1(v) (((v)&0x3f)<<0)
3542 +#define ETHERIPGR_IPGR2(v) (((v)&0x3f)<<8)
3543 +
3544 +//ETHCLRT
3545 +#define ETHERCLRT_MAXRET(v) (((v)&0x3f)<<0)
3546 +#define ETHERCLRT_COLWIN(v) (((v)&0x3f)<<8)
3547 +
3548 +//ETHMAXF
3549 +#define ETHERMAXF(v) (((v)&0x3f)<<0)
3550 +
3551 +//ETHMTEST
3552 +#define ETHERMTEST_TB (1<<2)
3553 +
3554 +//ETHMCP
3555 +#define ETHERMCP_DIV(v) (((v)&0xff)<<0)
3556 +
3557 +//MIIMCFG
3558 +#define ETHERMIIMCFG_CS(v) (((v)&0x3)<<2)
3559 +#define ETHERMIIMCFG_R (1<<15)
3560 +
3561 +//MIIMCMD
3562 +#define ETHERMIIMCMD_RD (1<<0)
3563 +#define ETHERMIIMCMD_SCN (1<<1)
3564 +
3565 +//MIIMADDR
3566 +#define ETHERMIIMADDR_REGADDR(v) (((v)&0x1f)<<0)
3567 +#define ETHERMIIMADDR_PHYADDR(v) (((v)&0x1f)<<8)
3568 +
3569 +//MIIMWTD
3570 +#define ETHERMIIMWTD(v) (((v)&0xff)<<0)
3571 +
3572 +//MIIMRDD
3573 +#define ETHERMIIMRDD(v) (((v)&0xff)<<0)
3574 +
3575 +//MIIMIND
3576 +#define ETHERMIIMIND_BSY (1<<0)
3577 +#define ETHERMIIMIND_SCN (1<<1)
3578 +#define ETHERMIIMIND_NV (1<<2)
3579 +
3580 +//DMA DEVCS IN
3581 +#define ETHERDMA_IN_LENGTH(v) (((v)&0xffff)<<16)
3582 +#define ETHERDMA_IN_CES (1<<14)
3583 +#define ETHERDMA_IN_LOR (1<<13)
3584 +#define ETHERDMA_IN_LE (1<<12)
3585 +#define ETHERDMA_IN_DB (1<<11)
3586 +#define ETHERDMA_IN_CV (1<<10)
3587 +#define ETHERDMA_IN_CRC (1<<9)
3588 +#define ETHERDMA_IN_OVR (1<<8)
3589 +#define ETHERDMA_IN_CF (1<<7)
3590 +#define ETHERDMA_IN_VLT (1<<6)
3591 +#define ETHERDMA_IN_BP (1<<5)
3592 +#define ETHERDMA_IN_MP (1<<4)
3593 +#define ETHERDMA_IN_FM (1<<3)
3594 +#define ETHERDMA_IN_ROK (1<<2)
3595 +#define ETHERDMA_IN_LD (1<<1)
3596 +#define ETHERDMA_IN_FD (1<<0)
3597 +
3598 +//DMA DEVCS OUT
3599 +#define ETHERDMA_OUT_CC(v) (((v)&0xf)<<17)
3600 +#define ETHERDMA_OUT_CNT 0x001e0000
3601 +#define ETHERDMA_OUT_SHFT 17
3602 +#define ETHERDMA_OUT_LE (1<<16)
3603 +
3604 +#define ETHERDMA_OUT_CRC (1<<15)
3605 +#define ETHERDMA_OUT_TD (1<<14)
3606 +#define ETHERDMA_OUT_LC (1<<13)
3607 +#define ETHERDMA_OUT_EC (1<<12)
3608 +#define ETHERDMA_OUT_ED (1<<11)
3609 +#define ETHERDMA_OUT_OF (1<<10)
3610 +#define ETHERDMA_OUT_UND (1<<9)
3611 +#define ETHERDMA_OUT_BP (1<<8)
3612 +#define ETHERDMA_OUT_MP (1<<7)
3613 +#define ETHERDMA_OUT_TOK (1<<6)
3614 +#define ETHERDMA_OUT_HEN (1<<5)
3615 +#define ETHERDMA_OUT_CEN (1<<4)
3616 +#define ETHERDMA_OUT_PEN (1<<3)
3617 +#define ETHERDMA_OUT_OEN (1<<2)
3618 +#define ETHERDMA_OUT_LD (1<<1)
3619 +#define ETHERDMA_OUT_FD (1<<0)
3620 +
3621 +#define RCV_ERRS \
3622 + (ETHERDMA_IN_OVR | ETHERDMA_IN_CRC | ETHERDMA_IN_CV | ETHERDMA_IN_LE)
3623 +#define TX_ERRS \
3624 + (ETHERDMA_OUT_LC | ETHERDMA_OUT_EC | ETHERDMA_OUT_ED | \
3625 + ETHERDMA_OUT_OF | ETHERDMA_OUT_UND)
3626 +
3627 +#define IS_RCV_ROK(X) (((X) & (1<<2)) >> 2) /* Receive Okay */
3628 +#define IS_RCV_FM(X) (((X) & (1<<3)) >> 3) /* Is Filter Match */
3629 +#define IS_RCV_MP(X) (((X) & (1<<4)) >> 4) /* Is it MP */
3630 +#define IS_RCV_BP(X) (((X) & (1<<5)) >> 5) /* Is it BP */
3631 +#define IS_RCV_VLT(X) (((X) & (1<<6)) >> 6) /* VLAN Tag Detect */
3632 +#define IS_RCV_CF(X) (((X) & (1<<7)) >> 7) /* Control Frame */
3633 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<8)) >> 8) /* Receive Overflow */
3634 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<9)) >> 9) /* CRC Error */
3635 +#define IS_RCV_CV_ERR(X) (((X) & (1<<10))>>10) /* Code Violation */
3636 +#define IS_RCV_DB_ERR(X) (((X) & (1<<11))>>11) /* Dribble Bits */
3637 +#define IS_RCV_LE_ERR(X) (((X) & (1<<12))>>12) /* Length error */
3638 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<13))>>13) /* Length Out of
3639 + Range */
3640 +#define IS_RCV_CES_ERR(X) (((X) & (1<<14))>>14) /* Preamble error */
3641 +#define RCVPKT_LENGTH(X) (((X) & 0xFFFF0000)>>16) /* Length of the
3642 + received packet */
3643 +
3644 +#define IS_TX_TOK(X) (((X) & (1<<6) ) >> 6 ) /* Transmit Okay */
3645 +#define IS_TX_MP(X) (((X) & (1<<7) ) >> 7 ) /* Multicast */
3646 +
3647 +#define IS_TX_BP(X) (((X) & (1<<8) ) >> 8 ) /* Broadcast */
3648 +#define IS_TX_UND_ERR(X) (((X) & (1<<9) ) >> 9 ) /* Transmit FIFO
3649 + Underflow */
3650 +#define IS_TX_OF_ERR(X) (((X) & (1<<10)) >>10 ) /* Oversized frame */
3651 +#define IS_TX_ED_ERR(X) (((X) & (1<<11)) >>11 ) /* Excessive
3652 + deferral */
3653 +#define IS_TX_EC_ERR(X) (((X) & (1<<12)) >>12 ) /* Excessive
3654 + collisions */
3655 +#define IS_TX_LC_ERR(X) (((X) & (1<<13)) >>13 ) /* Late Collision */
3656 +#define IS_TX_TD_ERR(X) (((X) & (1<<14)) >>14 ) /* Transmit deferred*/
3657 +#define IS_TX_CRC_ERR(X) (((X) & (1<<15)) >>15 ) /* CRC Error */
3658 +#define IS_TX_LE_ERR(X) (((X) & (1<<16)) >>16 ) /* Length Error */
3659 +
3660 +#define TX_COLLISION_COUNT(X) (((X) & 0x001E0000u)>>17) /* Collision Count */
3661 +
3662 +#endif /* RC32355_ETHER_H */
3663 +
3664 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355.h
3665 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355.h 1970-01-01 01:00:00.000000000 +0100
3666 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355.h 2006-01-10 00:32:33.000000000 +0100
3667 @@ -0,0 +1,177 @@
3668 +/**************************************************************************
3669 + *
3670 + * BRIEF MODULE DESCRIPTION
3671 + * Definitions for IDT RC32355 CPU.
3672 + *
3673 + * Copyright 2004 IDT Inc.
3674 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3675 + *
3676 + *
3677 + * This program is free software; you can redistribute it and/or modify it
3678 + * under the terms of the GNU General Public License as published by the
3679 + * Free Software Foundation; either version 2 of the License, or (at your
3680 + * option) any later version.
3681 + *
3682 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3683 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3684 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3685 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3686 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3687 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3688 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3689 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3690 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3691 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3692 + *
3693 + * You should have received a copy of the GNU General Public License along
3694 + * with this program; if not, write to the Free Software Foundation, Inc.,
3695 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3696 + *
3697 + *
3698 + * May 2004 rkt
3699 + * Initial Release
3700 + *
3701 + **************************************************************************
3702 + */
3703 +
3704 +
3705 +#ifndef _RC32355_H_
3706 +#define _RC32355_H_
3707 +
3708 +#include <linux/delay.h>
3709 +#include <asm/io.h>
3710 +
3711 +/* Base address of internal registers */
3712 +#define RC32355_REG_BASE 0x18000000
3713 +
3714 +/* System ID Registers */
3715 +#define CPU_SYSID (RC32355_REG_BASE + 0x00018)
3716 +#define CPU_BTADDR (RC32355_REG_BASE + 0x0001c)
3717 +#define CPU_REV (RC32355_REG_BASE + 0x0002c)
3718 +
3719 +/* Reset Controller */
3720 +#define RESET_CNTL (RC32355_REG_BASE + 0x08000)
3721 +
3722 +/* Device Controller */
3723 +#define DEV0_BASE (RC32355_REG_BASE + 0x10000)
3724 +#define DEV0_MASK (RC32355_REG_BASE + 0x10004)
3725 +#define DEV0_CNTL (RC32355_REG_BASE + 0x10008)
3726 +#define DEV0_TIMING (RC32355_REG_BASE + 0x1000c)
3727 +#define DEV_REG_OFFSET 0x10
3728 +
3729 +/* SDRAM Controller */
3730 +#define SDRAM0_BASE (RC32355_REG_BASE + 0x18000)
3731 +#define SDRAM0_MASK (RC32355_REG_BASE + 0x18004)
3732 +#define SDRAM1_BASE (RC32355_REG_BASE + 0x18008)
3733 +#define SDRAM1_MASK (RC32355_REG_BASE + 0x1800c)
3734 +#define SDRAM_CNTL (RC32355_REG_BASE + 0x18010)
3735 +
3736 +/* Bus Arbiter */
3737 +#define BUS_ARB_CNTL0 (RC32355_REG_BASE + 0x20000)
3738 +#define BUS_ARB_CNTL1 (RC32355_REG_BASE + 0x20004)
3739 +
3740 +/* Counters/Timers */
3741 +#define TIMER0_COUNT (RC32355_REG_BASE + 0x28000)
3742 +#define TIMER0_COMPARE (RC32355_REG_BASE + 0x28004)
3743 +#define TIMER0_CNTL (RC32355_REG_BASE + 0x28008)
3744 +#define TIMER_REG_OFFSET 0x0C
3745 +
3746 +/* System Integrity */
3747 +
3748 +/* Interrupt Controller */
3749 +#define IC_GROUP0_PEND (RC32355_REG_BASE + 0x30000)
3750 +#define IC_GROUP0_MASK (RC32355_REG_BASE + 0x30004)
3751 +#define IC_GROUP_OFFSET 0x08
3752 +
3753 +#define NUM_INTR_GROUPS 5
3754 +/*
3755 + * The IRQ mapping is as follows:
3756 + *
3757 + * IRQ Mapped To
3758 + * --- -------------------
3759 + * 0 SW0 (IP0) SW0 intr
3760 + * 1 SW1 (IP1) SW1 intr
3761 + * - Int0 (IP2) mapped to GROUP0_IRQ_BASE
3762 + * - Int1 (IP3) mapped to GROUP1_IRQ_BASE
3763 + * - Int2 (IP4) mapped to GROUP2_IRQ_BASE
3764 + * - Int3 (IP5) mapped to GROUP3_IRQ_BASE
3765 + * - Int4 (IP6) mapped to GROUP4_IRQ_BASE
3766 + * 7 Int5 (IP7) CP0 Timer
3767 + *
3768 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
3769 + * internally on the RC32355 is routed to the Expansion
3770 + * Interrupt Controller.
3771 + */
3772 +#define MIPS_CPU_TIMER_IRQ 7
3773 +
3774 +#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
3775 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) // DMA
3776 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) // ATM
3777 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) // TDM, Eth, USB, UARTs, I2C
3778 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) // GPIO
3779 +
3780 +#define RC32355_NR_IRQS (GROUP4_IRQ_BASE + 32)
3781 +
3782 +/* DMA - see rc32355_dma.h for full list of registers */
3783 +
3784 +#define RC32355_DMA_BASE (RC32355_REG_BASE + 0x38000)
3785 +#define DMA_CHAN_OFFSET 0x14
3786 +
3787 +/* GPIO Controller */
3788 +
3789 +/* TDM Bus */
3790 +
3791 +/* 16550 UARTs */
3792 +#ifdef __MIPSEB__
3793 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50003)
3794 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50023)
3795 +#else
3796 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50000)
3797 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50020)
3798 +#endif
3799 +
3800 +#define RC32300_UART0_IRQ (GROUP3_IRQ_BASE + 14)
3801 +#define RC32300_UART1_IRQ (GROUP3_IRQ_BASE + 17)
3802 +
3803 +/* ATM */
3804 +
3805 +/* Ethernet - see rc32355_eth.h for full list of registers */
3806 +
3807 +#define RC32355_ETH_BASE (RC32355_REG_BASE + 0x60000)
3808 +
3809 +
3810 +#define IDT_CLOCK_MULT 2
3811 +
3812 +/* Memory map of 79EB355 board */
3813 +
3814 +/* DRAM */
3815 +#define RAM_BASE 0x00000000
3816 +#define RAM_SIZE (32*1024*1024)
3817 +
3818 +/* SRAM (device 1) */
3819 +#define SRAM_BASE 0x02000000
3820 +#define SRAM_SIZE 0x00100000
3821 +
3822 +/* FLASH (device 2) */
3823 +#define FLASH_BASE 0x0C000000
3824 +#define FLASH_SIZE 0x00C00000
3825 +
3826 +/* ATM PHY (device 4) */
3827 +#define ATM_PHY_BASE 0x14000000
3828 +
3829 +/* TDM switch (device 3) */
3830 +#define TDM_BASE 0x1A000000
3831 +
3832 +/* LCD panel (device 3) */
3833 +#define LCD_BASE 0x1A002000
3834 +
3835 +/* RTC (DS1511W) (device 3) */
3836 +#define RTC_BASE 0x1A004000
3837 +
3838 +/* NVRAM (256 bytes internal to the DS1511 RTC) */
3839 +#define NVRAM_ADDR RTC_BASE + 0x10
3840 +#define NVRAM_DATA RTC_BASE + 0x13
3841 +#define NVRAM_ENVSIZE_OFF 4
3842 +#define NVRAM_ENVSTART_OFF 32
3843 +
3844 +#endif /* _RC32355_H_ */
3845 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_dma.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h
3846 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 1970-01-01 01:00:00.000000000 +0100
3847 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 2006-01-10 00:32:33.000000000 +0100
3848 @@ -0,0 +1,226 @@
3849 +/**************************************************************************
3850 + *
3851 + * BRIEF MODULE DESCRIPTION
3852 + * RC32365/336 DMA hardware abstraction.
3853 + *
3854 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
3855 + *
3856 + * This program is free software; you can redistribute it and/or modify it
3857 + * under the terms of the GNU General Public License as published by the
3858 + * Free Software Foundation; either version 2 of the License, or (at your
3859 + * option) any later version.
3860 + *
3861 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3862 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3863 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3864 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3865 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3866 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3867 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3868 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3869 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3870 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3871 + *
3872 + * You should have received a copy of the GNU General Public License along
3873 + * with this program; if not, write to the Free Software Foundation, Inc.,
3874 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3875 + *
3876 + *
3877 + **************************************************************************
3878 + * May 2004 P. Sadik.
3879 + *
3880 + * Initial Release
3881 + *
3882 + *
3883 + *
3884 + **************************************************************************
3885 + */
3886 +
3887 +#ifndef __IDT_RC32365_DMA_H__
3888 +#define __IDT_RC32365_DMA_H__
3889 +
3890 +enum
3891 +{
3892 + DMA0_PhysicalAddress = 0x18038000,
3893 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
3894 +
3895 + DMA0_VirtualAddress = 0xb8038000,
3896 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
3897 +} ;
3898 +
3899 +/*
3900 + * DMA descriptor (in physical memory).
3901 + */
3902 +
3903 +typedef struct DMAD_s
3904 +{
3905 + u32 control ; // Control. use DMAD_*
3906 + u32 ca ; // Current Address.
3907 + u32 devcs ; // Device control and status.
3908 + u32 link ; // Next descriptor in chain.
3909 +} volatile *DMAD_t ;
3910 +
3911 +enum
3912 +{
3913 + DMAD_size = sizeof (struct DMAD_s),
3914 + DMAD_count_b = 0, // in DMAD_t -> control
3915 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
3916 + DMAD_ds_b = 20, // in DMAD_t -> control
3917 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
3918 + DMAD_ds_extToMem0_v = 0,
3919 + DMAD_ds_memToExt0_v = 1,
3920 + DMAD_ds_extToMem1_v = 0,
3921 + DMAD_ds_memToExt1_v = 1,
3922 + DMAD_ds_ethRcv0_v = 0,
3923 + DMAD_ds_ethXmt0_v = 0,
3924 + DMAD_ds_ethRcv1_v = 0,
3925 + DMAD_ds_ethXmt2_v = 0,
3926 + DMAD_ds_memToFifo_v = 0,
3927 + DMAD_ds_fifoToMem_v = 0,
3928 + DMAD_ds_rng_de_v = 1,//randomNumberGenerator on LC/DE
3929 + DMAD_ds_pciToMem_v = 0,
3930 + DMAD_ds_memToPci_v = 0,
3931 + DMAD_ds_securityInput_v = 0,
3932 + DMAD_ds_securityOutput_v = 0,
3933 + DMAD_ds_rng_se_v = 0,//randomNumberGenerator on SE
3934 +
3935 + DMAD_devcmd_b = 22, // in DMAD_t -> control
3936 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
3937 + DMAD_devcmd_byte_v = 0, //memory-to-memory
3938 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
3939 + DMAD_devcmd_word_v = 2, //memory-to-memory
3940 + DMAD_devcmd_2words_v = 3, //memory-to-memory
3941 + DMAD_devcmd_4words_v = 4, //memory-to-memory
3942 + DMAD_devcmd_6words_v = 5, //memory-to-memory
3943 + DMAD_devcmd_8words_v = 6, //memory-to-memory
3944 + DMAD_devcmd_16words_v = 7, //memory-to-memory
3945 + DMAD_cof_b = 25, // chain on finished
3946 + DMAD_cof_m = 0x02000000, //
3947 + DMAD_cod_b = 26, // chain on done
3948 + DMAD_cod_m = 0x04000000, //
3949 + DMAD_iof_b = 27, // interrupt on finished
3950 + DMAD_iof_m = 0x08000000, //
3951 + DMAD_iod_b = 28, // interrupt on done
3952 + DMAD_iod_m = 0x10000000, //
3953 + DMAD_t_b = 29, // terminated
3954 + DMAD_t_m = 0x20000000, //
3955 + DMAD_d_b = 30, // done
3956 + DMAD_d_m = 0x40000000, //
3957 + DMAD_f_b = 31, // finished
3958 + DMAD_f_m = 0x80000000, //
3959 +} ;
3960 +
3961 +/*
3962 + * DMA register (within Internal Register Map).
3963 + */
3964 +
3965 +struct DMA_Chan_s
3966 +{
3967 + u32 dmac ; // Control.
3968 + u32 dmas ; // Status.
3969 + u32 dmasm ; // Mask.
3970 + u32 dmadptr ; // Descriptor pointer.
3971 + u32 dmandptr ; // Next descriptor pointer.
3972 +};
3973 +
3974 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
3975 +
3976 +//DMA_Channels use DMACH_count instead
3977 +
3978 +enum
3979 +{
3980 + DMAC_run_b = 0, //
3981 + DMAC_run_m = 0x00000001, //
3982 + DMAC_dm_b = 1, // done mask
3983 + DMAC_dm_m = 0x00000002, //
3984 + DMAC_mode_b = 2, //
3985 + DMAC_mode_m = 0x0000000c, //
3986 + DMAC_mode_auto_v = 0,
3987 + DMAC_mode_burst_v = 1,
3988 + DMAC_mode_transfer_v = 2, //usually used
3989 + DMAC_mode_reserved_v = 3,
3990 + DMAC_a_b = 4, //
3991 + DMAC_a_m = 0x00000010, //
3992 +
3993 + DMAS_f_b = 0, // finished (sticky)
3994 + DMAS_f_m = 0x00000001, //
3995 + DMAS_d_b = 1, // done (sticky)
3996 + DMAS_d_m = 0x00000002, //
3997 + DMAS_c_b = 2, // chain (sticky)
3998 + DMAS_c_m = 0x00000004, //
3999 + DMAS_e_b = 3, // error (sticky)
4000 + DMAS_e_m = 0x00000008, //
4001 + DMAS_h_b = 4, // halt (sticky)
4002 + DMAS_h_m = 0x00000010, //
4003 +
4004 + DMASM_f_b = 0, // finished (1=mask)
4005 + DMASM_f_m = 0x00000001, //
4006 + DMASM_d_b = 1, // done (1=mask)
4007 + DMASM_d_m = 0x00000002, //
4008 + DMASM_c_b = 2, // chain (1=mask)
4009 + DMASM_c_m = 0x00000004, //
4010 + DMASM_e_b = 3, // error (1=mask)
4011 + DMASM_e_m = 0x00000008, //
4012 + DMASM_h_b = 4, // halt (1=mask)
4013 + DMASM_h_m = 0x00000010, //
4014 +} ;
4015 +
4016 +/*
4017 + * DMA channel definitions
4018 + */
4019 +
4020 +enum
4021 +{
4022 + DMACH_ethRcv0 = 0,
4023 + DMACH_ethXmt0 = 1,
4024 + DMACH_ethRcv1 = 2,
4025 + DMACH_ethXmt2 = 3,
4026 + DMACH_pciToMem = 4,
4027 + DMACH_memToPci = 5,
4028 + DMACH_securityInput = 6,
4029 + DMACH_securityOutput = 7,
4030 + DMACH_rng = 8,
4031 +
4032 + DMACH_count //must be last
4033 +};
4034 +
4035 +
4036 +typedef struct DMAC_s
4037 +{
4038 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
4039 +} volatile *DMA_t ;
4040 +
4041 +
4042 +/*
4043 + * External DMA parameters
4044 +*/
4045 +
4046 +enum
4047 +{
4048 + DMADEVCMD_ts_b = 0, // ts field in devcmd
4049 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
4050 + DMADEVCMD_ts_byte_v = 0,
4051 + DMADEVCMD_ts_halfword_v = 1,
4052 + DMADEVCMD_ts_word_v = 2,
4053 + DMADEVCMD_ts_2word_v = 3,
4054 + DMADEVCMD_ts_4word_v = 4,
4055 + DMADEVCMD_ts_6word_v = 5,
4056 + DMADEVCMD_ts_8word_v = 6,
4057 + DMADEVCMD_ts_16word_v = 7
4058 +};
4059 +
4060 +
4061 +#if 1 // aws - Compatibility.
4062 +# define EXTDMA_ts_b DMADEVCMD_ts_b
4063 +# define EXTDMA_ts_m DMADEVCMD_ts_m
4064 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
4065 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
4066 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
4067 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
4068 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
4069 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
4070 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
4071 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
4072 +#endif // aws - Compatibility.
4073 +
4074 +#endif // __IDT_RC32365_DMA_H__
4075 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h
4076 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 1970-01-01 01:00:00.000000000 +0100
4077 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 2006-01-10 00:32:33.000000000 +0100
4078 @@ -0,0 +1,86 @@
4079 +/**************************************************************************
4080 + *
4081 + * BRIEF MODULE DESCRIPTION
4082 + * RC32365/336 DMA interface routines.
4083 + *
4084 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4085 + *
4086 + * This program is free software; you can redistribute it and/or modify it
4087 + * under the terms of the GNU General Public License as published by the
4088 + * Free Software Foundation; either version 2 of the License, or (at your
4089 + * option) any later version.
4090 + *
4091 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4092 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4093 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4094 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4095 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4096 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4097 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4098 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4099 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4100 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4101 + *
4102 + * You should have received a copy of the GNU General Public License along
4103 + * with this program; if not, write to the Free Software Foundation, Inc.,
4104 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4105 + *
4106 + *
4107 + **************************************************************************
4108 + * May 2004 P. Sadik.
4109 + *
4110 + * Initial Release
4111 + *
4112 + *
4113 + *
4114 + **************************************************************************
4115 + */
4116 +
4117 +#ifndef __IDT_RC32365_DMA_V_H__
4118 +#define __IDT_RC32365_DMA_V_H__
4119 +
4120 +
4121 +#include <asm/idt-boards/rc32300/rc32300.h>
4122 +#include <asm/idt-boards/rc32300/rc32365_dma.h>
4123 +#include <asm/idt-boards/rc32300/rc32365.h>
4124 +
4125 +#define DMA_CHAN_OFFSET 0x14
4126 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
4127 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
4128 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
4129 +
4130 +#define DMA_COUNT(count) \
4131 + ((count) & DMAD_count_m)
4132 +
4133 +#define DMA_HALT_TIMEOUT 500
4134 +
4135 +static inline int rc32365_halt_dma(DMA_Chan_t ch)
4136 +{
4137 + int timeout=1;
4138 + if (local_readl(&ch->dmac) & DMAC_run_m) {
4139 + local_writel(0, &ch->dmac);
4140 +
4141 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
4142 + if (local_readl(&ch->dmas) & DMAS_h_m) {
4143 + local_writel(0, &ch->dmas);
4144 + break;
4145 + }
4146 + }
4147 +
4148 + }
4149 +
4150 + return timeout ? 0 : 1;
4151 +}
4152 +
4153 +
4154 +static inline void rc32365_start_dma(DMA_Chan_t ch, u32 dma_addr)
4155 +{
4156 + local_writel(0, &ch->dmandptr);
4157 + local_writel(dma_addr, &ch->dmadptr);
4158 +}
4159 +
4160 +static inline void rc32365_chain_dma(DMA_Chan_t ch, u32 dma_addr)
4161 +{
4162 + local_writel(dma_addr, &ch->dmandptr);
4163 +}
4164 +#endif //__IDT_RC32365_DMA_V_H__
4165 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_eth.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h
4166 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 1970-01-01 01:00:00.000000000 +0100
4167 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 2006-01-10 00:32:33.000000000 +0100
4168 @@ -0,0 +1,344 @@
4169 +/**************************************************************************
4170 + *
4171 + * BRIEF MODULE DESCRIPTION
4172 + * RC32365/336 Ethernet hardware abstraction.
4173 + *
4174 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4175 + *
4176 + * This program is free software; you can redistribute it and/or modify it
4177 + * under the terms of the GNU General Public License as published by the
4178 + * Free Software Foundation; either version 2 of the License, or (at your
4179 + * option) any later version.
4180 + *
4181 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4182 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4183 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4184 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4185 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4186 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4187 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4188 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4189 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4190 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4191 + *
4192 + * You should have received a copy of the GNU General Public License along
4193 + * with this program; if not, write to the Free Software Foundation, Inc.,
4194 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4195 + *
4196 + *
4197 + **************************************************************************
4198 + * May 2004 P. Sadik.
4199 + *
4200 + * Initial Release
4201 + *
4202 + *
4203 + *
4204 + **************************************************************************
4205 + */
4206 +
4207 +#ifndef __IDT_RC32365_ETH_H__
4208 +#define __IDT_RC32365_ETH_H__
4209 +
4210 +enum
4211 +{
4212 + ETH0_PhysicalAddress = 0x18058000,
4213 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
4214 + ETH0_VirtualAddress = 0xb8058000,
4215 +
4216 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
4217 +
4218 + ETH1_PhysicalAddress = 0x18060000,
4219 + ETH1_VirtualAddress = 0xb8060000, // Default
4220 +} ;
4221 +
4222 +typedef struct
4223 +{
4224 + u32 ethintfc ;
4225 + u32 ethfifott ;
4226 + u32 etharc ;
4227 + u32 ethhash0 ;
4228 + u32 ethhash1 ;
4229 + u32 ethu0 [4] ; // Reserved.
4230 + u32 ethpfs ;
4231 + u32 ethmcp ;
4232 + u32 eth_u1 [10] ; // Reserved.
4233 + u32 ethspare ;
4234 + u32 eth_u2 [42] ; // Reserved.
4235 + u32 ethsal0 ;
4236 + u32 ethsah0 ;
4237 + u32 ethsal1 ;
4238 + u32 ethsah1 ;
4239 + u32 ethsal2 ;
4240 + u32 ethsah2 ;
4241 + u32 ethsal3 ;
4242 + u32 ethsah3 ;
4243 + u32 ethrbc ;
4244 + u32 ethrpc ;
4245 + u32 ethrupc ;
4246 + u32 ethrfc ;
4247 + u32 ethtbc ;
4248 + u32 ethgpf ;
4249 + u32 eth_u9 [50] ; // Reserved.
4250 + u32 ethmac1 ;
4251 + u32 ethmac2 ;
4252 + u32 ethipgt ;
4253 + u32 ethipgr ;
4254 + u32 ethclrt ;
4255 + u32 ethmaxf ;
4256 + u32 eth_u10 ; // Reserved.
4257 + u32 ethmtest ;
4258 + u32 miimcfg ;
4259 + u32 miimcmd ;
4260 + u32 miimaddr ;
4261 + u32 miimwtd ;
4262 + u32 miimrdd ;
4263 + u32 miimind ;
4264 + u32 eth_u11 ; // Reserved.
4265 + u32 eth_u12 ; // Reserved.
4266 + u32 ethcfsa0 ;
4267 + u32 ethcfsa1 ;
4268 + u32 ethcfsa2 ;
4269 +} volatile *ETH_t;
4270 +
4271 +enum
4272 +{
4273 + ETHINTFC_en_b = 0,
4274 + ETHINTFC_en_m = 0x00000001,
4275 + ETHINTFC_its_b = 1,
4276 + ETHINTFC_its_m = 0x00000002,
4277 + ETHINTFC_rip_b = 2,
4278 + ETHINTFC_rip_m = 0x00000004,
4279 + ETHINTFC_jam_b = 3,
4280 + ETHINTFC_jam_m = 0x00000008,
4281 + ETHINTFC_ovr_b = 4,
4282 + ETHINTFC_ovr_m = 0x00000010,
4283 + ETHINTFC_und_b = 5,
4284 + ETHINTFC_und_m = 0x00000020,
4285 +
4286 + ETHFIFOTT_tth_b = 0,
4287 + ETHFIFOTT_tth_m = 0x0000007f,
4288 +
4289 + ETHARC_pro_b = 0,
4290 + ETHARC_pro_m = 0x00000001,
4291 + ETHARC_am_b = 1,
4292 + ETHARC_am_m = 0x00000002,
4293 + ETHARC_afm_b = 2,
4294 + ETHARC_afm_m = 0x00000004,
4295 + ETHARC_ab_b = 3,
4296 + ETHARC_ab_m = 0x00000008,
4297 +
4298 + ETHSAL_byte5_b = 0,
4299 + ETHSAL_byte5_m = 0x000000ff,
4300 + ETHSAL_byte4_b = 8,
4301 + ETHSAL_byte4_m = 0x0000ff00,
4302 + ETHSAL_byte3_b = 16,
4303 + ETHSAL_byte3_m = 0x00ff0000,
4304 + ETHSAL_byte2_b = 24,
4305 + ETHSAL_byte2_m = 0xff000000,
4306 +
4307 + ETHSAH_byte1_b = 0,
4308 + ETHSAH_byte1_m = 0x000000ff,
4309 + ETHSAH_byte0_b = 8,
4310 + ETHSAH_byte0_m = 0x0000ff00,
4311 +
4312 + ETHGPF_ptv_b = 0,
4313 + ETHGPF_ptv_m = 0x0000ffff,
4314 +
4315 + ETHPFS_pfd_b = 0,
4316 + ETHPFS_pfd_m = 0x00000001,
4317 +
4318 + ETHCFSA0_cfsa4_b = 0,
4319 + ETHCFSA0_cfsa4_m = 0x000000ff,
4320 + ETHCFSA0_cfsa5_b = 8,
4321 + ETHCFSA0_cfsa5_m = 0x0000ff00,
4322 +
4323 + ETHCFSA1_cfsa2_b = 0,
4324 + ETHCFSA1_cfsa2_m = 0x000000ff,
4325 + ETHCFSA1_cfsa3_b = 8,
4326 + ETHCFSA1_cfsa3_m = 0x0000ff00,
4327 +
4328 + ETHCFSA2_cfsa0_b = 0,
4329 + ETHCFSA2_cfsa0_m = 0x000000ff,
4330 + ETHCFSA2_cfsa1_b = 8,
4331 + ETHCFSA2_cfsa1_m = 0x0000ff00,
4332 +
4333 + ETHMAC1_re_b = 0,
4334 + ETHMAC1_re_m = 0x00000001,
4335 + ETHMAC1_paf_b = 1,
4336 + ETHMAC1_paf_m = 0x00000002,
4337 + ETHMAC1_rfc_b = 2,
4338 + ETHMAC1_rfc_m = 0x00000004,
4339 + ETHMAC1_tfc_b = 3,
4340 + ETHMAC1_tfc_m = 0x00000008,
4341 + ETHMAC1_lb_b = 4,
4342 + ETHMAC1_lb_m = 0x00000010,
4343 + ETHMAC1_mr_b = 31,
4344 + ETHMAC1_mr_m = 0x80000000,
4345 +
4346 + ETHMAC2_fd_b = 0,
4347 + ETHMAC2_fd_m = 0x00000001,
4348 + ETHMAC2_flc_b = 1,
4349 + ETHMAC2_flc_m = 0x00000002,
4350 + ETHMAC2_hfe_b = 2,
4351 + ETHMAC2_hfe_m = 0x00000004,
4352 + ETHMAC2_dc_b = 3,
4353 + ETHMAC2_dc_m = 0x00000008,
4354 + ETHMAC2_cen_b = 4,
4355 + ETHMAC2_cen_m = 0x00000010,
4356 + ETHMAC2_pe_b = 5,
4357 + ETHMAC2_pe_m = 0x00000020,
4358 + ETHMAC2_vpe_b = 6,
4359 + ETHMAC2_vpe_m = 0x00000040,
4360 + ETHMAC2_ape_b = 7,
4361 + ETHMAC2_ape_m = 0x00000080,
4362 + ETHMAC2_ppe_b = 8,
4363 + ETHMAC2_ppe_m = 0x00000100,
4364 + ETHMAC2_lpe_b = 9,
4365 + ETHMAC2_lpe_m = 0x00000200,
4366 + ETHMAC2_nb_b = 12,
4367 + ETHMAC2_nb_m = 0x00001000,
4368 + ETHMAC2_bp_b = 13,
4369 + ETHMAC2_bp_m = 0x00002000,
4370 + ETHMAC2_ed_b = 14,
4371 + ETHMAC2_ed_m = 0x00004000,
4372 +
4373 + ETHIPGT_ipgt_b = 0,
4374 + ETHIPGT_ipgt_m = 0x0000007f,
4375 +
4376 + ETHIPGR_ipgr2_b = 0,
4377 + ETHIPGR_ipgr2_m = 0x0000007f,
4378 + ETHIPGR_ipgr1_b = 8,
4379 + ETHIPGR_ipgr1_m = 0x00007f00,
4380 +
4381 + ETHCLRT_maxret_b = 0,
4382 + ETHCLRT_maxret_m = 0x0000000f,
4383 + ETHCLRT_colwin_b = 8,
4384 + ETHCLRT_colwin_m = 0x00003f00,
4385 +
4386 + ETHMAXF_maxf_b = 0,
4387 + ETHMAXF_maxf_m = 0x0000ffff,
4388 +
4389 + ETHMTEST_tb_b = 2,
4390 + ETHMTEST_tb_m = 0x00000004,
4391 +
4392 + ETHMCP_div_b = 0,
4393 + ETHMCP_div_m = 0x000000ff,
4394 +
4395 + MIIMCFG_rsv_b = 0,
4396 + MIIMCFG_rsv_m = 0x0000000c,
4397 +
4398 + MIIMCMD_rd_b = 0,
4399 + MIIMCMD_rd_m = 0x00000001,
4400 + MIIMCMD_scn_b = 1,
4401 + MIIMCMD_scn_m = 0x00000002,
4402 +
4403 + MIIMADDR_regaddr_b = 0,
4404 + MIIMADDR_regaddr_m = 0x0000001f,
4405 + MIIMADDR_phyaddr_b = 8,
4406 + MIIMADDR_phyaddr_m = 0x00001f00,
4407 +
4408 + MIIMWTD_wdata_b = 0,
4409 + MIIMWTD_wdata_m = 0x0000ffff,
4410 +
4411 + MIIMRDD_rdata_b = 0,
4412 + MIIMRDD_rdata_m = 0x0000ffff,
4413 +
4414 + MIIMIND_bsy_b = 0,
4415 + MIIMIND_bsy_m = 0x00000001,
4416 + MIIMIND_scn_b = 1,
4417 + MIIMIND_scn_m = 0x00000002,
4418 + MIIMIND_nv_b = 2,
4419 + MIIMIND_nv_m = 0x00000004,
4420 +
4421 +} ;
4422 +
4423 +/*
4424 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
4425 + */
4426 +enum
4427 +{
4428 + ETHRX_fd_b = 0,
4429 + ETHRX_fd_m = 0x00000001,
4430 + ETHRX_ld_b = 1,
4431 + ETHRX_ld_m = 0x00000002,
4432 + ETHRX_rok_b = 2,
4433 + ETHRX_rok_m = 0x00000004,
4434 + ETHRX_fm_b = 3,
4435 + ETHRX_fm_m = 0x00000008,
4436 + ETHRX_mp_b = 4,
4437 + ETHRX_mp_m = 0x00000010,
4438 + ETHRX_bp_b = 5,
4439 + ETHRX_bp_m = 0x00000020,
4440 + ETHRX_vlt_b = 6,
4441 + ETHRX_vlt_m = 0x00000040,
4442 + ETHRX_cf_b = 7,
4443 + ETHRX_cf_m = 0x00000080,
4444 + ETHRX_ovr_b = 8,
4445 + ETHRX_ovr_m = 0x00000100,
4446 + ETHRX_crc_b = 9,
4447 + ETHRX_crc_m = 0x00000200,
4448 + ETHRX_cv_b = 10,
4449 + ETHRX_cv_m = 0x00000400,
4450 + ETHRX_db_b = 11,
4451 + ETHRX_db_m = 0x00000800,
4452 + ETHRX_le_b = 12,
4453 + ETHRX_le_m = 0x00001000,
4454 + ETHRX_lor_b = 13,
4455 + ETHRX_lor_m = 0x00002000,
4456 + ETHRX_ces_b = 14,
4457 + ETHRX_ces_m = 0x00004000,
4458 + ETHRX_length_b = 16,
4459 + ETHRX_length_m = 0xffff0000,
4460 +
4461 + ETHTX_fd_b = 0,
4462 + ETHTX_fd_m = 0x00000001,
4463 + ETHTX_ld_b = 1,
4464 + ETHTX_ld_m = 0x00000002,
4465 + ETHTX_oen_b = 2,
4466 + ETHTX_oen_m = 0x00000004,
4467 + ETHTX_pen_b = 3,
4468 + ETHTX_pen_m = 0x00000008,
4469 + ETHTX_cen_b = 4,
4470 + ETHTX_cen_m = 0x00000010,
4471 + ETHTX_hen_b = 5,
4472 + ETHTX_hen_m = 0x00000020,
4473 + ETHTX_tok_b = 6,
4474 + ETHTX_tok_m = 0x00000040,
4475 + ETHTX_mp_b = 7,
4476 + ETHTX_mp_m = 0x00000080,
4477 + ETHTX_bp_b = 8,
4478 + ETHTX_bp_m = 0x00000100,
4479 + ETHTX_und_b = 9,
4480 + ETHTX_und_m = 0x00000200,
4481 + ETHTX_of_b = 10,
4482 + ETHTX_of_m = 0x00000400,
4483 + ETHTX_ed_b = 11,
4484 + ETHTX_ed_m = 0x00000800,
4485 + ETHTX_ec_b = 12,
4486 + ETHTX_ec_m = 0x00001000,
4487 + ETHTX_lc_b = 13,
4488 + ETHTX_lc_m = 0x00002000,
4489 + ETHTX_td_b = 14,
4490 + ETHTX_td_m = 0x00004000,
4491 + ETHTX_crc_b = 15,
4492 + ETHTX_crc_m = 0x00008000,
4493 + ETHTX_le_b = 16,
4494 + ETHTX_le_m = 0x00010000,
4495 + ETHTX_cc_b = 17,
4496 + ETHTX_cc_m = 0x001E0000,
4497 +} ;
4498 +
4499 +enum
4500 +{
4501 + ETH0_IPABMC_PhysicalAddress = 0x18040010,
4502 + ETH0_IPABMC_VirtualAddress = 0xb8040000,
4503 + ETH1_IPABMC_PhysicalAddress = 0x18040018,
4504 + ETH1_IPABMC_VirtualAddress = 0xb8040018,
4505 +} ;
4506 +
4507 +typedef struct
4508 +{
4509 + u32 ipabmcrx ;
4510 + u32 ipabmctx ;
4511 +}volatile *IPABM_ETH_t;
4512 +#endif //__IDT_RC32365_ETH_H__
4513 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h
4514 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h 1970-01-01 01:00:00.000000000 +0100
4515 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h 2006-01-10 00:32:33.000000000 +0100
4516 @@ -0,0 +1,72 @@
4517 +/**************************************************************************
4518 + *
4519 + * BRIEF MODULE DESCRIPTION
4520 + * RC32365/336 Ethernet status checking.
4521 + *
4522 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4523 + *
4524 + * This program is free software; you can redistribute it and/or modify it
4525 + * under the terms of the GNU General Public License as published by the
4526 + * Free Software Foundation; either version 2 of the License, or (at your
4527 + * option) any later version.
4528 + *
4529 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4530 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4531 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4532 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4533 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4534 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4535 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4536 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4537 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4538 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4539 + *
4540 + * You should have received a copy of the GNU General Public License along
4541 + * with this program; if not, write to the Free Software Foundation, Inc.,
4542 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4543 + *
4544 + *
4545 + **************************************************************************
4546 + * May 2004 P. Sadik.
4547 + *
4548 + * Initial Release
4549 + *
4550 + *
4551 + *
4552 + **************************************************************************
4553 + */
4554 +
4555 +#ifndef __IDT_RC32365_ETH_V_H__
4556 +#define __IDT_RC32365_ETH_V_H__
4557 +#include <asm/idt-boards/rc32300/rc32365_eth.h>
4558 +
4559 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
4560 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
4561 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
4562 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
4563 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
4564 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
4565 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
4566 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
4567 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
4568 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
4569 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
4570 +
4571 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
4572 +
4573 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
4574 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
4575 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
4576 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
4577 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
4578 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
4579 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
4580 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
4581 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
4582 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
4583 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
4584 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
4585 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
4586 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
4587 +
4588 +#endif //__IDT_RC32365_ETH_V_H__
4589 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h
4590 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h 1970-01-01 01:00:00.000000000 +0100
4591 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h 2006-01-10 00:32:33.000000000 +0100
4592 @@ -0,0 +1,181 @@
4593 +/**************************************************************************
4594 + *
4595 + * BRIEF MODULE DESCRIPTION
4596 + * RC32365/336 GPIO hardware abstraction.
4597 + *
4598 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4599 + *
4600 + * This program is free software; you can redistribute it and/or modify it
4601 + * under the terms of the GNU General Public License as published by the
4602 + * Free Software Foundation; either version 2 of the License, or (at your
4603 + * option) any later version.
4604 + *
4605 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4606 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4607 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4608 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4609 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4610 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4611 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4612 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4613 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4614 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4615 + *
4616 + * You should have received a copy of the GNU General Public License along
4617 + * with this program; if not, write to the Free Software Foundation, Inc.,
4618 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4619 + *
4620 + *
4621 + **************************************************************************
4622 + * May 2004 P. Sadik.
4623 + *
4624 + * Initial Release
4625 + *
4626 + *
4627 + *
4628 + **************************************************************************
4629 + */
4630 +
4631 +#ifndef __IDT_RC32365_GPIO_H__
4632 +#define __IDT_RC32365_GPIO_H__
4633 +
4634 +enum
4635 +{
4636 + GPIO0_PhysicalAddress = 0x18048000,
4637 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
4638 +
4639 + GPIO0_VirtualAddress = 0xb8048000,
4640 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
4641 +} ;
4642 +
4643 +typedef struct
4644 +{
4645 + u32 gpiofunc; /* GPIO Function Register
4646 + * gpiofunc[x]==0 bit = gpio
4647 + * func[x]==1 bit = altfunc
4648 + */
4649 + u32 gpiocfg; /* GPIO Configuration Register
4650 + * gpiocfg[x]==0 bit = input
4651 + * gpiocfg[x]==1 bit = output
4652 + */
4653 + u32 gpiod; /* GPIO Data Register
4654 + * gpiod[x] read/write gpio pinX status
4655 + */
4656 + u32 gpioilevel; /* GPIO Interrupt Status Register
4657 + * interrupt level (see gpioistat)
4658 + */
4659 + u32 gpioistat; /* Gpio Interrupt Status Register
4660 + * istat[x] = (gpiod[x] == level[x])
4661 + * cleared in ISR (STICKY bits)
4662 + */
4663 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
4664 +} volatile * GPIO_t ;
4665 +
4666 +typedef enum
4667 +{
4668 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
4669 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
4670 + GPIO_input_v = 0, // gpiocfg use pin as input.
4671 + GPIO_output_v = 1, // gpiocfg use pin as output.
4672 + GPIO_pin0_b = 0,
4673 + GPIO_pin0_m = 0x00000001,
4674 + GPIO_pin1_b = 1,
4675 + GPIO_pin1_m = 0x00000002,
4676 + GPIO_pin2_b = 2,
4677 + GPIO_pin2_m = 0x00000004,
4678 + GPIO_pin3_b = 3,
4679 + GPIO_pin3_m = 0x00000008,
4680 + GPIO_pin4_b = 4,
4681 + GPIO_pin4_m = 0x00000010,
4682 + GPIO_pin5_b = 5,
4683 + GPIO_pin5_m = 0x00000020,
4684 + GPIO_pin6_b = 6,
4685 + GPIO_pin6_m = 0x00000040,
4686 + GPIO_pin7_b = 7,
4687 + GPIO_pin7_m = 0x00000080,
4688 + GPIO_pin8_b = 8,
4689 + GPIO_pin8_m = 0x00000100,
4690 + GPIO_pin9_b = 9,
4691 + GPIO_pin9_m = 0x00000200,
4692 + GPIO_pin10_b = 10,
4693 + GPIO_pin10_m = 0x00000400,
4694 + GPIO_pin11_b = 11,
4695 + GPIO_pin11_m = 0x00000800,
4696 + GPIO_pin12_b = 12,
4697 + GPIO_pin12_m = 0x00001000,
4698 + GPIO_pin13_b = 13,
4699 + GPIO_pin13_m = 0x00002000,
4700 + GPIO_pin14_b = 14,
4701 + GPIO_pin14_m = 0x00004000,
4702 + GPIO_pin15_b = 15,
4703 + GPIO_pin15_m = 0x00008000,
4704 +
4705 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
4706 +
4707 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
4708 + GPIO_u0sout_m = GPIO_pin0_m,
4709 + GPIO_u0sout_cfg_v = GPIO_output_v,
4710 +
4711 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
4712 + GPIO_u0sinp_m = GPIO_pin1_m,
4713 + GPIO_u0sinp_cfg_v = GPIO_input_v,
4714 +
4715 + GPIO_maddr22_b = GPIO_pin2_b, // M&P bus bit 22.
4716 + GPIO_maddr22_m = GPIO_pin2_m,
4717 + GPIO_maddr22_cfg_v = GPIO_output_v,
4718 +
4719 + GPIO_maddr23_b = GPIO_pin3_b, // M&P bus bit 23.
4720 + GPIO_maddr23_m = GPIO_pin3_m,
4721 + GPIO_maddr23_cfg_v = GPIO_output_v,
4722 +
4723 + GPIO_maddr24_b = GPIO_pin4_b, // M&P bus bit 24.
4724 + GPIO_maddr24_m = GPIO_pin4_m,
4725 + GPIO_maddr24_cfg_v = GPIO_output_v,
4726 +
4727 + GPIO_maddr25_b = GPIO_pin5_b, // M&P bus bit 25.
4728 + GPIO_maddr25_m = GPIO_pin5_m,
4729 + GPIO_maddr25_cfg_v = GPIO_output_v,
4730 +
4731 + GPIO_rngclk_b = GPIO_pin6_b, // reserved.
4732 + GPIO_rngclk_m = GPIO_pin6_m,
4733 + GPIO_rngclk_cfg_v = GPIO_input_v,
4734 +
4735 + GPIO_sdckenp_b = GPIO_pin7_b, // reserved.
4736 + GPIO_sdckenp_m = GPIO_pin7_m,
4737 + GPIO_sdckenp_cfg_v = GPIO_output_v,
4738 +
4739 + GPIO_cen1_b = GPIO_pin8_b, // reserved.
4740 + GPIO_cen1_m = GPIO_pin8_m,
4741 + GPIO_cen1_cfg_v = GPIO_output_v,
4742 +
4743 + GPIO_cen2_b = GPIO_pin9_b, // reserved.
4744 + GPIO_cen2_m = GPIO_pin9_m,
4745 + GPIO_cen2_cfg_v = GPIO_output_v,
4746 +
4747 + GPIO_regn_b = GPIO_pin10_b, // reserved.
4748 + GPIO_regn_m = GPIO_pin10_m,
4749 + GPIO_regn_cfg_v = GPIO_output_v,
4750 +
4751 + GPIO_iordn_b = GPIO_pin11_b, // reserved.
4752 + GPIO_iordn_m = GPIO_pin11_m,
4753 + GPIO_iordn_cfg_v = GPIO_output_v,
4754 +
4755 + GPIO_iowrn_b = GPIO_pin12_b, // reserved.
4756 + GPIO_iowrn_m = GPIO_pin12_m,
4757 + GPIO_iowrn_cfg_v = GPIO_output_v,
4758 +
4759 + GPIO_pcireqn2_b = GPIO_pin13_b, // PCI messaging int.
4760 + GPIO_pcireqn2_m = GPIO_pin13_m,
4761 + GPIO_pcireqn2_cfg_v = GPIO_input_v,
4762 +
4763 + GPIO_pcigntn2_b = GPIO_pin14_b, // PCI messaging int.
4764 + GPIO_pcigntn2_m = GPIO_pin14_m,
4765 + GPIO_pcigntn2_cfg_v = GPIO_output_v,
4766 +
4767 + GPIO_pcimuintn_b = GPIO_pin15_b, // PCI messaging int.
4768 + GPIO_pcimuintn_m = GPIO_pin15_m,
4769 + GPIO_pcimuintn_cfg_v= GPIO_output_v,
4770 +
4771 +} GPIO_DEFS_t;
4772 +
4773 +#endif //__IDT_RC32365_GPIO_H__
4774 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h
4775 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h 1970-01-01 01:00:00.000000000 +0100
4776 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h 2006-01-10 00:32:33.000000000 +0100
4777 @@ -0,0 +1,91 @@
4778 +/**************************************************************************
4779 + *
4780 + * BRIEF MODULE DESCRIPTION
4781 + * Routines to set/clear/toggle GPIO on RC32365
4782 + *
4783 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4784 + *
4785 + * This program is free software; you can redistribute it and/or modify it
4786 + * under the terms of the GNU General Public License as published by the
4787 + * Free Software Foundation; either version 2 of the License, or (at your
4788 + * option) any later version.
4789 + *
4790 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4791 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4792 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4793 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4794 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4795 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4796 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4797 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4798 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4799 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4800 + *
4801 + * You should have received a copy of the GNU General Public License along
4802 + * with this program; if not, write to the Free Software Foundation, Inc.,
4803 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4804 + *
4805 + *
4806 + **************************************************************************
4807 + * May 2004 P. Sadik.
4808 + *
4809 + * Initial Release
4810 + *
4811 + *
4812 + *
4813 + **************************************************************************
4814 + */
4815 +#ifndef __IDT_RC32365_GPIO_V_H__
4816 +#define __IDT_RC32365_GPIO_V_H__
4817 +
4818 +
4819 +#ifdef _LANGUAGE_ASSEMBLY
4820 +#define SET_GPIO(pin) \
4821 + lui t5,0xb804 ; \
4822 + ori t5,t5,0x8000 ; \
4823 + lw t4,8(t5) ; \
4824 + ori t4,t4,pin ; \
4825 + sw t4,8(t5) ;
4826 +
4827 +#define CLEAR_GPIO(pin) \
4828 + lui t5,0xb804 ; \
4829 + ori t5,t5,0x8000 ; \
4830 + lw t4,8(t5) ; \
4831 + lui t6,0xFFFF; \
4832 + ori t6,t6,0xFFFF; \
4833 + xori t6,t6,pin ; \
4834 + and t4,t6 ; \
4835 + sw t4,8(t5) ;
4836 +
4837 +#define TOGGLE_GPIO(pin) \
4838 + lui t5,0xb804 ; \
4839 + ori t5,t5,0x8000 ; \
4840 + lw t4,8(t5) ; \
4841 + xori t4,t4,pin ; \
4842 + sw t4,8(t5) ;
4843 +
4844 +#else // !_LANGUAGE_ASSEMBLY
4845 +#include <asm/rc32300/types.h>
4846 +#include <asm/rc32300/rc32365_gpio.h>
4847 +#include <asm/rc32300/rc32365.h>
4848 +
4849 +static inline void set_gpio(unsigned long pin)
4850 +{
4851 + idt_gpio->gpiod |= pin;
4852 +}
4853 +
4854 +static inline void clear_gpio(unsigned long pin)
4855 +{
4856 + idt_gpio->gpiod &= ~pin;
4857 +}
4858 +static inline void toggle_gpio(unsigned long pin)
4859 +{
4860 + idt_gpio->gpiod ^= pin;
4861 +}
4862 +#define SET_GPIO(pin) set_gpio(pin)
4863 +#define CLEAR_GPIO(pin) clear_gpio(pin)
4864 +#define TOGGLE_GPIO(pin) toggle_gpio(pin)
4865 +#endif // _LANGUAGE_ASSEMBLY
4866 +
4867 +#endif //__IDT_RC32365_GPIO_V_H__
4868 +
4869 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365.h
4870 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365.h 1970-01-01 01:00:00.000000000 +0100
4871 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365.h 2006-01-10 00:32:33.000000000 +0100
4872 @@ -0,0 +1,160 @@
4873 +/**************************************************************************
4874 + *
4875 + * BRIEF MODULE DESCRIPTION
4876 + * Definitions for IDT RC32365 CPU.
4877 + *
4878 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4879 + *
4880 + * This program is free software; you can redistribute it and/or modify it
4881 + * under the terms of the GNU General Public License as published by the
4882 + * Free Software Foundation; either version 2 of the License, or (at your
4883 + * option) any later version.
4884 + *
4885 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4886 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4887 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4888 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4889 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4890 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4891 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4892 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4893 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4894 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4895 + *
4896 + * You should have received a copy of the GNU General Public License along
4897 + * with this program; if not, write to the Free Software Foundation, Inc.,
4898 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4899 + *
4900 + *
4901 + **************************************************************************
4902 + * May 2004 P. Sadik.
4903 + *
4904 + * Initial Release
4905 + *
4906 + *
4907 + *
4908 + **************************************************************************
4909 + */
4910 +
4911 +#ifndef __IDT_RC32365_H__
4912 +#define __IDT_RC32365_H__
4913 +
4914 +extern unsigned int cedar_za;
4915 +
4916 +/* Base address of internal registers */
4917 +#define RC32365_REG_BASE 0x18000000
4918 +
4919 +/* System ID Registers */
4920 +#define CPU_SYSID (RC32365_REG_BASE + 0x00018)
4921 +#define CPU_DEVTYPE (RC32365_REG_BASE + 0x0001c)
4922 +
4923 +/* Reset Controller */
4924 +#define RESET_CNTL (RC32365_REG_BASE + 0x08000)
4925 +#define BOOT_VECTOR (RC32365_REG_BASE + 0x08004)
4926 +
4927 +/* Device Controller */
4928 +#define DEV0_BASE (RC32365_REG_BASE + 0x10000)
4929 +#define DEV0_MASK (RC32365_REG_BASE + 0x10004)
4930 +#define DEV0_CNTL (RC32365_REG_BASE + 0x10008)
4931 +#define DEV0_TIMING (RC32365_REG_BASE + 0x1000c)
4932 +#define DEV_REG_OFFSET 0x10
4933 +
4934 +/* SDRAM Controller */
4935 +#define SDRAM0_BASE (RC32365_REG_BASE + 0x18000)
4936 +#define SDRAM0_MASK (RC32365_REG_BASE + 0x18004)
4937 +#define SDRAM1_BASE (RC32365_REG_BASE + 0x18008)
4938 +#define SDRAM1_MASK (RC32365_REG_BASE + 0x1800c)
4939 +#define SDRAM_CNTL (RC32365_REG_BASE + 0x18010)
4940 +
4941 +/* Counters/Timers */
4942 +#define TIMER0_COUNT (RC32365_REG_BASE + 0x20000)
4943 +#define TIMER0_COMPARE (RC32365_REG_BASE + 0x20004)
4944 +#define TIMER0_CNTL (RC32365_REG_BASE + 0x20008)
4945 +#define TIMER0_SELECT (RC32365_REG_BASE + 0x2000c)
4946 +#define TIMER_REG_OFFSET 0x10
4947 +
4948 +/* System Integrity */
4949 +
4950 +/* Interrupt Controller */
4951 +#define IC_GROUP0_PEND (RC32365_REG_BASE + 0x30000)
4952 +#define IC_GROUP0_TEST (RC32365_REG_BASE + 0x30004)
4953 +#define IC_GROUP0_MASK (RC32365_REG_BASE + 0x30008)
4954 +#define IC_GROUP_OFFSET 0x0c
4955 +
4956 +#define NUM_INTR_GROUPS 5
4957 +/*
4958 + * The IRQ mapping is as follows:
4959 + *
4960 + * IRQ Mapped To
4961 + * --- -------------------
4962 + * 0 SW0 (IP0) SW0 intr
4963 + * 1 SW1 (IP1) SW1 intr
4964 + * - Int0 (IP2) mapped to GROUP0_IRQ_BASE
4965 + * - Int1 (IP3) mapped to GROUP1_IRQ_BASE
4966 + * - Int2 (IP4) mapped to GROUP2_IRQ_BASE
4967 + * - Int3 (IP5) mapped to GROUP3_IRQ_BASE
4968 + * - Int4 (IP6) mapped to GROUP4_IRQ_BASE
4969 + * 7 Int5 (IP7) CP0 Timer
4970 + *
4971 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
4972 + * internally on the RC32365 is routed to the Expansion
4973 + * Interrupt Controller.
4974 + */
4975 +#define MIPS_CPU_TIMER_IRQ 7
4976 +
4977 +#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
4978 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) // DMA
4979 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) // RNG, SEC
4980 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) // Eth, PCI, UARTs
4981 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) // GPIO
4982 +
4983 +#define RC32365_NR_IRQS (GROUP4_IRQ_BASE + 32)
4984 +
4985 +/* DMA - see rc32365_dma.h for full list of registers */
4986 +
4987 +#define RC32365_DMA_BASE (RC32365_REG_BASE + 0x38000)
4988 +#define DMA_CHAN_OFFSET 0x14
4989 +
4990 +/* GPIO Controller */
4991 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
4992 +
4993 +/* 16550 UARTs */
4994 +#ifdef __MIPSEB__
4995 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50003)
4996 +#else
4997 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50000)
4998 +#endif
4999 +#define RC32300_UART0_IRQ (GROUP3_IRQ_BASE + 0)
5000 +
5001 +/* Ethernet - see rc32365_eth.h for full list of registers */
5002 +
5003 +#define RC32365_ETH_BASE (RC32365_REG_BASE + 0x58000)
5004 +
5005 +#define IDT_CLOCK_MULT 2
5006 +
5007 +/* FLASH (device 1) */
5008 +#define FLASH_BASE 0x08000000
5009 +#define FLASH_SIZE 0x00800000
5010 +
5011 +/* LCD 4-digit display (device 2) */
5012 +#define LCD_DIGIT0 0x0C000003
5013 +#define LCD_DIGIT1 0x0C000002
5014 +#define LCD_DIGIT2 0x0C000001
5015 +#define LCD_DIGIT3 0x0C000000
5016 +
5017 +/* RTC (DS1553) (device 2) */
5018 +#define RTC_BASE 0x0c800000
5019 +/* NVRAM */
5020 +#define NVRAM_BASE RTC_BASE
5021 +#define NVRAM_ENVSIZE_OFF 4
5022 +#define NVRAM_ENVSTART_OFF 32
5023 +
5024 +/* Interrupts routed on 79EB365 board */
5025 +#define RC32365_PCI_INTA_IRQ (GROUP4_IRQ_BASE + 8)
5026 +#define RC32365_PCI_INTB_IRQ (GROUP4_IRQ_BASE + 9)
5027 +#define RC32365_PCI_INTC_IRQ (GROUP4_IRQ_BASE + 10)
5028 +#define RC32365_PCI_INTD_IRQ (GROUP4_IRQ_BASE + 11)
5029 +
5030 +#define RAM_SIZE (32 * 1024 * 1024)
5031 +
5032 +#endif //__IDT_RC32365_H__
5033 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_pci.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h
5034 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 1970-01-01 01:00:00.000000000 +0100
5035 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 2006-01-10 00:32:33.000000000 +0100
5036 @@ -0,0 +1,515 @@
5037 +/**************************************************************************
5038 + *
5039 + * BRIEF MODULE DESCRIPTION
5040 + * Datatype declaration for IDT 79EB365/336 PCI
5041 + *
5042 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5043 + *
5044 + * This program is free software; you can redistribute it and/or modify it
5045 + * under the terms of the GNU General Public License as published by the
5046 + * Free Software Foundation; either version 2 of the License, or (at your
5047 + * option) any later version.
5048 + *
5049 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5050 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5051 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5052 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5053 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5054 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5055 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5056 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5057 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5058 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5059 + *
5060 + * You should have received a copy of the GNU General Public License along
5061 + * with this program; if not, write to the Free Software Foundation, Inc.,
5062 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5063 + *
5064 + *
5065 + **************************************************************************
5066 + * May 2004 P. Sadik.
5067 + *
5068 + * Initial Release
5069 + *
5070 + *
5071 + *
5072 + **************************************************************************
5073 + */
5074 +
5075 +#ifndef __IDT_RC32365_PCI_H__
5076 +#define __IDT_RC32365_PCI_H__
5077 +
5078 +enum
5079 +{
5080 + PCI0_PhysicalAddress = 0x18068000,
5081 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
5082 +
5083 + PCI0_VirtualAddress = 0xb8068000,
5084 + PCI_VirtualAddress = PCI0_VirtualAddress,
5085 +} ;
5086 +
5087 +enum
5088 +{
5089 + PCI_LbaCount = 4, // Local base addresses.
5090 +} ;
5091 +
5092 +typedef struct
5093 +{
5094 + u32 a ; // Address.
5095 + u32 c ; // Control.
5096 + u32 m ; // mapping.
5097 +} PCI_Map_s ;
5098 +
5099 +typedef struct
5100 +{
5101 + u32 pcic ;
5102 + u32 pcis ;
5103 + u32 pcism ;
5104 + u32 pcicfga ;
5105 + u32 pcicfgd ;
5106 + PCI_Map_s pcilba [PCI_LbaCount] ;
5107 + u32 pcidac ;
5108 + u32 pcidas ;
5109 + u32 pcidasm ;
5110 + u32 pcidad ;
5111 + u32 pcidma8c ;
5112 + u32 pcidma9c ;
5113 + u32 pcitc ;
5114 +} volatile *PCI_t ;
5115 +
5116 +// PCI messaging unit.
5117 +enum
5118 +{
5119 + PCIM_Count = 2,
5120 +} ;
5121 +typedef struct
5122 +{
5123 + u32 pciim [PCIM_Count] ;
5124 + u32 pciom [PCIM_Count] ;
5125 + u32 pciid ;
5126 + u32 pciiic ;
5127 + u32 pciiim ;
5128 + u32 pciiod ;
5129 + u32 pciioic ;
5130 + u32 pciioim ;
5131 +} volatile *PCIM_t ;
5132 +
5133 +/*******************************************************************************
5134 + *
5135 + * PCI Control Register
5136 + *
5137 + ******************************************************************************/
5138 +enum
5139 +{
5140 + PCIC_en_b = 0,
5141 + PCIC_en_m = 0x00000001,
5142 + PCIC_tnr_b = 1,
5143 + PCIC_tnr_m = 0x00000002,
5144 + PCIC_sce_b = 2,
5145 + PCIC_sce_m = 0x00000004,
5146 + PCIC_ien_b = 3,
5147 + PCIC_ien_m = 0x00000008,
5148 + PCIC_aaa_b = 4,
5149 + PCIC_aaa_m = 0x00000010,
5150 + PCIC_eap_b = 5,
5151 + PCIC_eap_m = 0x00000020,
5152 + PCIC_pcim_b = 6,
5153 + PCIC_pcim_m = 0x000001c0,
5154 + PCIC_pcim_disabled_v = 0,
5155 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
5156 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
5157 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
5158 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
5159 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
5160 + PCIC_pcim_reserved6_v = 6,
5161 + PCIC_pcim_reserved7_v = 7,
5162 + PCIC_igm_b = 9,
5163 + PCIC_igm_m = 0x00000200,
5164 +} ;
5165 +
5166 +/*******************************************************************************
5167 + *
5168 + * PCI Status Register
5169 + *
5170 + ******************************************************************************/
5171 +enum {
5172 + PCIS_eed_b = 0,
5173 + PCIS_eed_m = 0x00000001,
5174 + PCIS_wr_b = 1,
5175 + PCIS_wr_m = 0x00000002,
5176 + PCIS_nmi_b = 2,
5177 + PCIS_nmi_m = 0x00000004,
5178 + PCIS_ii_b = 3,
5179 + PCIS_ii_m = 0x00000008,
5180 + PCIS_cwe_b = 4,
5181 + PCIS_cwe_m = 0x00000010,
5182 + PCIS_cre_b = 5,
5183 + PCIS_cre_m = 0x00000020,
5184 + PCIS_mdpe_b = 6,
5185 + PCIS_mdpe_m = 0x00000040,
5186 + PCIS_sta_b = 7,
5187 + PCIS_sta_m = 0x00000080,
5188 + PCIS_rta_b = 8,
5189 + PCIS_rta_m = 0x00000100,
5190 + PCIS_rma_b = 9,
5191 + PCIS_rma_m = 0x00000200,
5192 + PCIS_sse_b = 10,
5193 + PCIS_sse_m = 0x00000400,
5194 + PCIS_ose_b = 11,
5195 + PCIS_ose_m = 0x00000800,
5196 + PCIS_pe_b = 12,
5197 + PCIS_pe_m = 0x00001000,
5198 + PCIS_tae_b = 13,
5199 + PCIS_tae_m = 0x00002000,
5200 + PCIS_rle_b = 14,
5201 + PCIS_rle_m = 0x00004000,
5202 + PCIS_bme_b = 15,
5203 + PCIS_bme_m = 0x00008000,
5204 + PCIS_prd_b = 16,
5205 + PCIS_prd_m = 0x00010000,
5206 + PCIS_rip_b = 17,
5207 + PCIS_rip_m = 0x00020000,
5208 +} ;
5209 +
5210 +/*******************************************************************************
5211 + *
5212 + * PCI Status Mask Register
5213 + *
5214 + ******************************************************************************/
5215 +enum {
5216 + PCISM_eed_b = 0,
5217 + PCISM_eed_m = 0x00000001,
5218 + PCISM_wr_b = 1,
5219 + PCISM_wr_m = 0x00000002,
5220 + PCISM_nmi_b = 2,
5221 + PCISM_nmi_m = 0x00000004,
5222 + PCISM_ii_b = 3,
5223 + PCISM_ii_m = 0x00000008,
5224 + PCISM_cwe_b = 4,
5225 + PCISM_cwe_m = 0x00000010,
5226 + PCISM_cre_b = 5,
5227 + PCISM_cre_m = 0x00000020,
5228 + PCISM_mdpe_b = 6,
5229 + PCISM_mdpe_m = 0x00000040,
5230 + PCISM_sta_b = 7,
5231 + PCISM_sta_m = 0x00000080,
5232 + PCISM_rta_b = 8,
5233 + PCISM_rta_m = 0x00000100,
5234 + PCISM_rma_b = 9,
5235 + PCISM_rma_m = 0x00000200,
5236 + PCISM_sse_b = 10,
5237 + PCISM_sse_m = 0x00000400,
5238 + PCISM_ose_b = 11,
5239 + PCISM_ose_m = 0x00000800,
5240 + PCISM_pe_b = 12,
5241 + PCISM_pe_m = 0x00001000,
5242 + PCISM_tae_b = 13,
5243 + PCISM_tae_m = 0x00002000,
5244 + PCISM_rle_b = 14,
5245 + PCISM_rle_m = 0x00004000,
5246 + PCISM_bme_b = 15,
5247 + PCISM_bme_m = 0x00008000,
5248 + PCISM_prd_b = 16,
5249 + PCISM_prd_m = 0x00010000,
5250 + PCISM_rip_b = 17,
5251 + PCISM_rip_m = 0x00020000,
5252 +} ;
5253 +
5254 +/*******************************************************************************
5255 + *
5256 + * PCI Configuration Address Register
5257 + *
5258 + ******************************************************************************/
5259 +enum {
5260 + PCICFGA_reg_b = 2,
5261 + PCICFGA_reg_m = 0x000000fc,
5262 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
5263 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
5264 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
5265 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
5266 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
5267 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
5268 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
5269 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
5270 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
5271 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
5272 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
5273 + PCICFGA_reg_pba0m_v = 0x48>>2,
5274 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
5275 + PCICFGA_reg_pba1m_v = 0x50>>2,
5276 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
5277 + PCICFGA_reg_pba2m_v = 0x58>>2,
5278 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
5279 + PCICFGA_reg_pba3m_v = 0x60>>2,
5280 + PCICFGA_reg_pmgt_v = 0x64>>2,
5281 + PCICFGA_func_b = 8,
5282 + PCICFGA_func_m = 0x00000700,
5283 + PCICFGA_dev_b = 11,
5284 + PCICFGA_dev_m = 0x0000f800,
5285 + PCICFGA_dev_internal_v = 0,
5286 + PCICFGA_bus_b = 16,
5287 + PCICFGA_bus_m = 0x00ff0000,
5288 + PCICFGA_bus_type0_v = 0, //local bus
5289 + PCICFGA_en_b = 31, // read only
5290 + PCICFGA_en_m = 0x80000000,
5291 +} ;
5292 +
5293 +enum {
5294 + PCFGID_vendor_b = 0,
5295 + PCFGID_vendor_m = 0x0000ffff,
5296 + PCFGID_vendor_IDT_v = 0x111d,
5297 + PCFGID_device_b = 16,
5298 + PCFGID_device_m = 0xffff0000,
5299 + PCFGID_device_Acaciade_v = 0x0207,
5300 +
5301 + PCFG04_command_ioena_b = 1,
5302 + PCFG04_command_ioena_m = 0x00000001,
5303 + PCFG04_command_memena_b = 2,
5304 + PCFG04_command_memena_m = 0x00000002,
5305 + PCFG04_command_bmena_b = 3,
5306 + PCFG04_command_bmena_m = 0x00000004,
5307 + PCFG04_command_mwinv_b = 5,
5308 + PCFG04_command_mwinv_m = 0x00000010,
5309 + PCFG04_command_parena_b = 7,
5310 + PCFG04_command_parena_m = 0x00000040,
5311 + PCFG04_command_serrena_b = 9,
5312 + PCFG04_command_serrena_m = 0x00000100,
5313 + PCFG04_command_fastbbena_b = 10,
5314 + PCFG04_command_fastbbena_m = 0x00000200,
5315 + PCFG04_status_b = 16,
5316 + PCFG04_status_m = 0xffff0000,
5317 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
5318 + PCFG04_status_66MHz_m = 0x00200000,
5319 + PCFG04_status_fbb_b = 23,
5320 + PCFG04_status_fbb_m = 0x00800000,
5321 + PCFG04_status_mdpe_b = 24,
5322 + PCFG04_status_mdpe_m = 0x01000000,
5323 + PCFG04_status_dst_b = 25,
5324 + PCFG04_status_dst_m = 0x06000000,
5325 + PCFG04_status_sta_b = 27,
5326 + PCFG04_status_sta_m = 0x08000000,
5327 + PCFG04_status_rta_b = 28,
5328 + PCFG04_status_rta_m = 0x10000000,
5329 + PCFG04_status_rma_b = 29,
5330 + PCFG04_status_rma_m = 0x20000000,
5331 + PCFG04_status_sse_b = 30,
5332 + PCFG04_status_sse_m = 0x40000000,
5333 + PCFG04_status_pe_b = 31,
5334 + PCFG04_status_pe_m = 0x40000000,
5335 +
5336 + PCFG08_revId_b = 0,
5337 + PCFG08_revId_m = 0x000000ff,
5338 + PCFG08_classCode_b = 0,
5339 + PCFG08_classCode_m = 0xffffff00,
5340 + PCFG08_classCode_bridge_v = 06,
5341 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
5342 + PCFG0C_cacheline_b = 0,
5343 + PCFG0C_cacheline_m = 0x000000ff,
5344 + PCFG0C_masterLatency_b = 8,
5345 + PCFG0C_masterLatency_m = 0x0000ff00,
5346 + PCFG0C_headerType_b = 16,
5347 + PCFG0C_headerType_m = 0x00ff0000,
5348 + PCFG0C_bist_b = 24,
5349 + PCFG0C_bist_m = 0xff000000,
5350 +
5351 + PCIPBA_msi_b = 0,
5352 + PCIPBA_msi_m = 0x00000001,
5353 + PCIPBA_p_b = 3,
5354 + PCIPBA_p_m = 0x00000004,
5355 + PCIPBA_baddr_b = 8,
5356 + PCIPBA_baddr_m = 0xffffff00,
5357 +
5358 + PCFGSS_vendorId_b = 0,
5359 + PCFGSS_vendorId_m = 0x0000ffff,
5360 + PCFGSS_id_b = 16,
5361 + PCFGSS_id_m = 0xffff0000,
5362 +
5363 + PCFG3C_interruptLine_b = 0,
5364 + PCFG3C_interruptLine_m = 0x000000ff,
5365 + PCFG3C_interruptPin_b = 8,
5366 + PCFG3C_interruptPin_m = 0x0000ff00,
5367 + PCFG3C_minGrant_b = 16,
5368 + PCFG3C_minGrant_m = 0x00ff0000,
5369 + PCFG3C_maxLat_b = 24,
5370 + PCFG3C_maxLat_m = 0xff000000,
5371 +
5372 + PCIPBAC_msi_b = 0,
5373 + PCIPBAC_msi_m = 0x00000001,
5374 + PCIPBAC_p_b = 1,
5375 + PCIPBAC_p_m = 0x00000002,
5376 + PCIPBAC_size_b = 2,
5377 + PCIPBAC_size_m = 0x0000007c,
5378 + PCIPBAC_sb_b = 7,
5379 + PCIPBAC_sb_m = 0x00000080,
5380 + PCIPBAC_pp_b = 8,
5381 + PCIPBAC_pp_m = 0x00000100,
5382 + PCIPBAC_mr_b = 9,
5383 + PCIPBAC_mr_m = 0x00000600,
5384 + PCIPBAC_mr_read_v =0, //no prefetching
5385 + PCIPBAC_mr_readLine_v =1,
5386 + PCIPBAC_mr_readMult_v =2,
5387 + PCIPBAC_mrl_b = 11,
5388 + PCIPBAC_mrl_m = 0x00000800,
5389 + PCIPBAC_mrm_b = 12,
5390 + PCIPBAC_mrm_m = 0x00001000,
5391 + PCIPBAC_trp_b = 13,
5392 + PCIPBAC_trp_m = 0x00002000,
5393 +
5394 + PCFG40_trdyTimeout_b = 0,
5395 + PCFG40_trdyTimeout_m = 0x000000ff,
5396 + PCFG40_retryLim_b = 8,
5397 + PCFG40_retryLim_m = 0x0000ff00,
5398 +};
5399 +
5400 +/*******************************************************************************
5401 + *
5402 + * PCI Local Base Address [0|1|2|3] Register
5403 + *
5404 + ******************************************************************************/
5405 +enum {
5406 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
5407 + PCILBA_baddr_m = 0xffffff00,
5408 +} ;
5409 +/*******************************************************************************
5410 + *
5411 + * PCI Local Base Address Control Register
5412 + *
5413 + ******************************************************************************/
5414 +enum {
5415 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
5416 + PCILBAC_msi_m = 0x00000001,
5417 + PCILBAC_msi_mem_v = 0,
5418 + PCILBAC_msi_io_v = 1,
5419 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
5420 + PCILBAC_size_m = 0x0000007c,
5421 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
5422 + PCILBAC_sb_m = 0x00000080,
5423 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
5424 + PCILBAC_rt_m = 0x00000100,
5425 + PCILBAC_rt_noprefetch_v = 0, // mem read
5426 + PCILBAC_rt_prefetch_v = 1, // mem readline
5427 +} ;
5428 +
5429 +/*******************************************************************************
5430 + *
5431 + * PCI Local Base Address [0|1|2|3] Mapping Register
5432 + *
5433 + ******************************************************************************/
5434 +enum {
5435 + PCILBAM_maddr_b = 8,
5436 + PCILBAM_maddr_m = 0xffffff00,
5437 +} ;
5438 +
5439 +/*******************************************************************************
5440 + *
5441 + * PCI Decoupled Access Control Register
5442 + *
5443 + ******************************************************************************/
5444 +enum {
5445 + PCIDAC_den_b = 0,
5446 + PCIDAC_den_m = 0x00000001,
5447 +} ;
5448 +
5449 +/*******************************************************************************
5450 + *
5451 + * PCI Decoupled Access Status Register
5452 + *
5453 + ******************************************************************************/
5454 +enum {
5455 + PCIDAS_d_b = 0,
5456 + PCIDAS_d_m = 0x00000001,
5457 + PCIDAS_b_b = 1,
5458 + PCIDAS_b_m = 0x00000002,
5459 + PCIDAS_e_b = 2,
5460 + PCIDAS_e_m = 0x00000004,
5461 + PCIDAS_ofe_b = 3,
5462 + PCIDAS_ofe_m = 0x00000008,
5463 + PCIDAS_off_b = 4,
5464 + PCIDAS_off_m = 0x00000010,
5465 + PCIDAS_ife_b = 5,
5466 + PCIDAS_ife_m = 0x00000020,
5467 + PCIDAS_iff_b = 6,
5468 + PCIDAS_iff_m = 0x00000040,
5469 +} ;
5470 +
5471 +/*******************************************************************************
5472 + *
5473 + * PCI DMA Channel 8 Configuration Register
5474 + *
5475 + ******************************************************************************/
5476 +enum
5477 +{
5478 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
5479 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
5480 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
5481 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
5482 +} ;
5483 +
5484 +/*******************************************************************************
5485 + *
5486 + * PCI DMA Channel 9 Configuration Register
5487 + *
5488 + ******************************************************************************/
5489 +enum
5490 +{
5491 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
5492 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
5493 +} ;
5494 +
5495 +/*******************************************************************************
5496 + *
5497 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
5498 + *
5499 + ******************************************************************************/
5500 +enum {
5501 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
5502 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
5503 + // These are for reads (DMA channel 8)
5504 + PCIDMAD_devcmd_mr_v = 0, //memory read
5505 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
5506 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
5507 + PCIDMAD_devcmd_ior_v = 3, //I/O read
5508 + // These are for writes (DMA channel 9)
5509 + PCIDMAD_devcmd_mw_v = 0, //memory write
5510 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
5511 + PCIDMAD_devcmd_iow_v = 3, //I/O write
5512 +
5513 + // Swap byte field applies to both DMA channel 8 and 9
5514 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
5515 + PCIDMAD_sb_m = 0x01000000, // swap byte field
5516 +} ;
5517 +
5518 +
5519 +/*******************************************************************************
5520 + *
5521 + * PCI Target Control Register
5522 + *
5523 + ******************************************************************************/
5524 +enum
5525 +{
5526 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
5527 + PCITC_rtimer_m = 0x000000ff,
5528 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
5529 + PCITC_dtimer_m = 0x0000ff00,
5530 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
5531 + PCITC_rdr_m = 0x00040000,
5532 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
5533 + PCITC_ddt_m = 0x00080000,
5534 +} ;
5535 +/*******************************************************************************
5536 + *
5537 + * PCI messaging unit [applies to both inbound and outbound registers ]
5538 + *
5539 + ******************************************************************************/
5540 +enum
5541 +{
5542 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5543 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
5544 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5545 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
5546 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5547 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
5548 +};
5549 +
5550 +
5551 +#endif // __IDT_RC32365_PCI_H__
5552 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h
5553 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h 1970-01-01 01:00:00.000000000 +0100
5554 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h 2006-01-10 00:32:33.000000000 +0100
5555 @@ -0,0 +1,217 @@
5556 +/**************************************************************************
5557 + *
5558 + * BRIEF MODULE DESCRIPTION
5559 + * PCI header values for IDT 79EB365/336
5560 + *
5561 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5562 + *
5563 + * This program is free software; you can redistribute it and/or modify it
5564 + * under the terms of the GNU General Public License as published by the
5565 + * Free Software Foundation; either version 2 of the License, or (at your
5566 + * option) any later version.
5567 + *
5568 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5569 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5570 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5571 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5572 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5573 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5574 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5575 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5576 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5577 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5578 + *
5579 + * You should have received a copy of the GNU General Public License along
5580 + * with this program; if not, write to the Free Software Foundation, Inc.,
5581 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5582 + *
5583 + *
5584 + **************************************************************************
5585 + * May 2004 P. Sadik.
5586 + *
5587 + * Initial Release
5588 + *
5589 + *
5590 + *
5591 + **************************************************************************
5592 + */
5593 +
5594 +#ifndef __IDT_RC32365_PCI_V_H__
5595 +#define __IDT_RC32365_PCI_V_H__
5596 +
5597 +
5598 +#define PCI_MSG_VirtualAddress 0xB806C010
5599 +#define rc32365_pci ((volatile PCI_t) PCI0_VirtualAddress)
5600 +#define rc32365_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
5601 +
5602 +#define PCIM_SHFT 0x6
5603 +#define PCIM_BIT_LEN 0x7
5604 +#define PCIM_H_EA 0x3
5605 +#define PCIM_H_IA_FIX 0x4
5606 +#define PCIM_H_IA_RR 0x5
5607 +
5608 +#define PCI_ADDR_START 0x50000000
5609 +
5610 +#define CPUTOPCI_MEM_WIN 0x02000000
5611 +#define CPUTOPCI_IO_WIN 0x00100000
5612 +#define PCILBA_SIZE_SHFT 2
5613 +#define PCILBA_SIZE_MASK 0x1F
5614 +#define SIZE_256MB 0x1C
5615 +#define SIZE_128MB 0x1B
5616 +#define SIZE_64MB 0x1A
5617 +#define SIZE_32MB 0x19
5618 +#define SIZE_16MB 0x18
5619 +#define SIZE_4MB 0x16
5620 +#define SIZE_2MB 0x15
5621 +#define SIZE_1MB 0x14
5622 +#define CEDAR_CONFIG0_ADDR 0x80000000
5623 +#define CEDAR_CONFIG1_ADDR 0x80000004
5624 +#define CEDAR_CONFIG2_ADDR 0x80000008
5625 +#define CEDAR_CONFIG3_ADDR 0x8000000C
5626 +#define CEDAR_CONFIG4_ADDR 0x80000010
5627 +#define CEDAR_CONFIG5_ADDR 0x80000014
5628 +#define CEDAR_CONFIG6_ADDR 0x80000018
5629 +#define CEDAR_CONFIG7_ADDR 0x8000001C
5630 +#define CEDAR_CONFIG8_ADDR 0x80000020
5631 +#define CEDAR_CONFIG9_ADDR 0x80000024
5632 +#define CEDAR_CONFIG10_ADDR 0x80000028
5633 +#define CEDAR_CONFIG11_ADDR 0x8000002C
5634 +#define CEDAR_CONFIG12_ADDR 0x80000030
5635 +#define CEDAR_CONFIG13_ADDR 0x80000034
5636 +#define CEDAR_CONFIG14_ADDR 0x80000038
5637 +#define CEDAR_CONFIG15_ADDR 0x8000003C
5638 +#define CEDAR_CONFIG16_ADDR 0x80000040
5639 +#define CEDAR_CONFIG17_ADDR 0x80000044
5640 +#define CEDAR_CONFIG18_ADDR 0x80000048
5641 +#define CEDAR_CONFIG19_ADDR 0x8000004C
5642 +#define CEDAR_CONFIG20_ADDR 0x80000050
5643 +#define CEDAR_CONFIG21_ADDR 0x80000054
5644 +#define CEDAR_CONFIG22_ADDR 0x80000058
5645 +#define CEDAR_CONFIG23_ADDR 0x8000005C
5646 +#define CEDAR_CONFIG24_ADDR 0x80000060
5647 +#define CEDAR_CONFIG25_ADDR 0x80000064
5648 +#define CEDAR_CMD (PCFG04_command_ioena_m | \
5649 + PCFG04_command_memena_m | \
5650 + PCFG04_command_bmena_m | \
5651 + PCFG04_command_mwinv_m | \
5652 + PCFG04_command_parena_m | \
5653 + PCFG04_command_serrena_m )
5654 +
5655 +#define CEDAR_STAT (PCFG04_status_mdpe_m | \
5656 + PCFG04_status_sta_m | \
5657 + PCFG04_status_rta_m | \
5658 + PCFG04_status_rma_m | \
5659 + PCFG04_status_sse_m | \
5660 + PCFG04_status_pe_m)
5661 +
5662 +#define CEDAR_CNFG1 ((CEDAR_STAT << 16) | \
5663 + CEDAR_CMD)
5664 +
5665 +#define CEDAR_REVID 0
5666 +#define CEDAR_CLASS_CODE 0
5667 +#define CEDAR_CNFG2 ((CEDAR_CLASS_CODE << 8) | \
5668 + CEDAR_REVID)
5669 +
5670 +#define CEDAR_CACHE_LINE_SIZE 4
5671 +#define CEDAR_MASTER_LAT 0x3c
5672 +#define CEDAR_HEADER_TYPE 0
5673 +#define CEDAR_BIST 0
5674 +
5675 +#define CEDAR_CNFG3 ((CEDAR_BIST << 24) | \
5676 + (CEDAR_HEADER_TYPE << 16) | \
5677 + (CEDAR_MASTER_LAT << 8) | \
5678 + CEDAR_CACHE_LINE_SIZE)
5679 +
5680 +#define CEDAR_BAR0 0x00000008 /* 128 MB Memory */
5681 +#define CEDAR_BAR1 0x18800001 /* 1 MB IO */
5682 +#define CEDAR_BAR2 0x18000001 /* 2 MB IO window for Cedar
5683 + internal Registers */
5684 +#define CEDAR_BAR3 0x48000008 /* Spare 128 MB Memory */
5685 +
5686 +#define CEDAR_CNFG4 CEDAR_BAR0
5687 +#define CEDAR_CNFG5 CEDAR_BAR1
5688 +#define CEDAR_CNFG6 CEDAR_BAR2
5689 +#define CEDAR_CNFG7 CEDAR_BAR3
5690 +
5691 +#define CEDAR_SUBSYS_VENDOR_ID 0
5692 +#define CEDAR_SUBSYSTEM_ID 0
5693 +#define CEDAR_CNFG8 0
5694 +#define CEDAR_CNFG9 0
5695 +#define CEDAR_CNFG10 0
5696 +#define CEDAR_CNFG11 ((CEDAR_SUBSYS_VENDOR_ID << 16) | \
5697 + CEDAR_SUBSYSTEM_ID)
5698 +#define CEDAR_INT_LINE 1
5699 +#define CEDAR_INT_PIN 1
5700 +#define CEDAR_MIN_GNT 8
5701 +#define CEDAR_MAX_LAT 0x38
5702 +#define CEDAR_CNFG12 0
5703 +#define CEDAR_CNFG13 0
5704 +#define CEDAR_CNFG14 0
5705 +#define CEDAR_CNFG15 ((CEDAR_MAX_LAT << 24) | \
5706 + (CEDAR_MIN_GNT << 16) | \
5707 + (CEDAR_INT_PIN << 8) | \
5708 + CEDAR_INT_LINE)
5709 +#define CEDAR_RETRY_LIMIT 0x80
5710 +#define CEDAR_TRDY_LIMIT 0x80
5711 +#define CEDAR_CNFG16 ((CEDAR_RETRY_LIMIT << 8) | \
5712 + CEDAR_TRDY_LIMIT)
5713 +#define PCI_PBAxC_R 0x0
5714 +#define PCI_PBAxC_RL 0x1
5715 +#define PCI_PBAxC_RM 0x2
5716 +#define SIZE_SHFT 2
5717 +#ifdef __MIPSEB__
5718 +#define CEDAR_PBA0C (((1 & 0x3) << PCIPBAC_mr_b) | \
5719 + PCIPBAC_pp_m | \
5720 + PCIPBAC_sb_m | \
5721 + (SIZE_128MB << SIZE_SHFT) | \
5722 + PCIPBAC_p_m)
5723 +#else
5724 +
5725 +#define CEDAR_PBA0C (((1 & 0x3) << PCIPBAC_mr_b) | \
5726 + PCIPBAC_pp_m | \
5727 + (SIZE_128MB << SIZE_SHFT) | \
5728 + PCIPBAC_p_m)
5729 +#endif
5730 +#define CEDAR_CNFG17 CEDAR_PBA0C
5731 +#define CEDAR_PBA0M 0x0
5732 +#define CEDAR_CNFG18 CEDAR_PBA0M
5733 +
5734 +#ifdef __MIPSEB__
5735 +#define CEDAR_PBA1C ((SIZE_1MB << SIZE_SHFT) | \
5736 + PCIPBAC_sb_m | \
5737 + PCIPBAC_msi_m)
5738 +#else
5739 +#define CEDAR_PBA1C ((SIZE_1MB << SIZE_SHFT) | \
5740 + PCIPBAC_msi_m)
5741 +#endif
5742 +#define CEDAR_CNFG19 CEDAR_PBA1C
5743 +#define CEDAR_PBA1M 0x0
5744 +#define CEDAR_CNFG20 CEDAR_PBA1M
5745 +
5746 +#ifdef __MIPSEB__
5747 +#define CEDAR_PBA2C ((SIZE_2MB << SIZE_SHFT) | \
5748 + PCIPBAC_sb_m | \
5749 + PCIPBAC_msi_m)
5750 +#else
5751 +#define CEDAR_PBA2C ((SIZE_2MB << SIZE_SHFT) | \
5752 + PCIPBAC_msi_m)
5753 +#endif
5754 +
5755 +#define CEDAR_CNFG21 CEDAR_PBA2C
5756 +#define CEDAR_PBA2M 0x18000000
5757 +#define CEDAR_CNFG22 CEDAR_PBA2M
5758 +
5759 +#ifdef __MIPSEB__
5760 +#define CEDAR_PBA3C PCIPBAC_sb_m
5761 +#else
5762 +#define CEDAR_PBA3C 0
5763 +#endif
5764 +
5765 +#define CEDAR_CNFG23 CEDAR_PBA3C
5766 +#define CEDAR_PBA3M 0
5767 +#define CEDAR_CNFG24 CEDAR_PBA3M
5768 +
5769 +#define PCITC_DTIMER_VAL 8
5770 +#define PCITC_RTIMER_VAL 0x10
5771 +
5772 +#endif //__IDT_RC32365_PCI_V_H__
5773 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_dma.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h
5774 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 1970-01-01 01:00:00.000000000 +0100
5775 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 2006-01-10 00:32:33.000000000 +0100
5776 @@ -0,0 +1,205 @@
5777 +/**************************************************************************
5778 + *
5779 + * BRIEF MODULE DESCRIPTION
5780 + * DMA register definition
5781 + *
5782 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5783 + *
5784 + * This program is free software; you can redistribute it and/or modify it
5785 + * under the terms of the GNU General Public License as published by the
5786 + * Free Software Foundation; either version 2 of the License, or (at your
5787 + * option) any later version.
5788 + *
5789 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5790 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5791 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5792 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5793 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5794 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5795 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5796 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5797 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5798 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5799 + *
5800 + * You should have received a copy of the GNU General Public License along
5801 + * with this program; if not, write to the Free Software Foundation, Inc.,
5802 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5803 + *
5804 + *
5805 + **************************************************************************
5806 + * May 2004 rkt, neb
5807 + *
5808 + * Initial Release
5809 + *
5810 + *
5811 + *
5812 + **************************************************************************
5813 + */
5814 +
5815 +#ifndef __IDT_DMA_H__
5816 +#define __IDT_DMA_H__
5817 +
5818 +enum
5819 +{
5820 + DMA0_PhysicalAddress = 0x18040000,
5821 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
5822 +
5823 + DMA0_VirtualAddress = 0xb8040000,
5824 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
5825 +} ;
5826 +
5827 +/*
5828 + * DMA descriptor (in physical memory).
5829 + */
5830 +
5831 +typedef struct DMAD_s
5832 +{
5833 + u32 control ; // Control. use DMAD_*
5834 + u32 ca ; // Current Address.
5835 + u32 devcs ; // Device control and status.
5836 + u32 link ; // Next descriptor in chain.
5837 +} volatile *DMAD_t ;
5838 +
5839 +enum
5840 +{
5841 + DMAD_size = sizeof (struct DMAD_s),
5842 + DMAD_count_b = 0, // in DMAD_t -> control
5843 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
5844 + DMAD_ds_b = 20, // in DMAD_t -> control
5845 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
5846 + DMAD_ds_ethRcv0_v = 0,
5847 + DMAD_ds_ethXmt0_v = 0,
5848 + DMAD_ds_memToFifo_v = 0,
5849 + DMAD_ds_fifoToMem_v = 0,
5850 + DMAD_ds_pciToMem_v = 0,
5851 + DMAD_ds_memToPci_v = 0,
5852 +
5853 + DMAD_devcmd_b = 22, // in DMAD_t -> control
5854 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
5855 + DMAD_devcmd_byte_v = 0, //memory-to-memory
5856 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
5857 + DMAD_devcmd_word_v = 2, //memory-to-memory
5858 + DMAD_devcmd_2words_v = 3, //memory-to-memory
5859 + DMAD_devcmd_4words_v = 4, //memory-to-memory
5860 + DMAD_devcmd_6words_v = 5, //memory-to-memory
5861 + DMAD_devcmd_8words_v = 6, //memory-to-memory
5862 + DMAD_devcmd_16words_v = 7, //memory-to-memory
5863 + DMAD_cof_b = 25, // chain on finished
5864 + DMAD_cof_m = 0x02000000, //
5865 + DMAD_cod_b = 26, // chain on done
5866 + DMAD_cod_m = 0x04000000, //
5867 + DMAD_iof_b = 27, // interrupt on finished
5868 + DMAD_iof_m = 0x08000000, //
5869 + DMAD_iod_b = 28, // interrupt on done
5870 + DMAD_iod_m = 0x10000000, //
5871 + DMAD_t_b = 29, // terminated
5872 + DMAD_t_m = 0x20000000, //
5873 + DMAD_d_b = 30, // done
5874 + DMAD_d_m = 0x40000000, //
5875 + DMAD_f_b = 31, // finished
5876 + DMAD_f_m = 0x80000000, //
5877 +} ;
5878 +
5879 +/*
5880 + * DMA register (within Internal Register Map).
5881 + */
5882 +
5883 +struct DMA_Chan_s
5884 +{
5885 + u32 dmac ; // Control.
5886 + u32 dmas ; // Status.
5887 + u32 dmasm ; // Mask.
5888 + u32 dmadptr ; // Descriptor pointer.
5889 + u32 dmandptr ; // Next descriptor pointer.
5890 +};
5891 +
5892 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
5893 +
5894 +//DMA_Channels use DMACH_count instead
5895 +
5896 +enum
5897 +{
5898 + DMAC_run_b = 0, //
5899 + DMAC_run_m = 0x00000001, //
5900 + DMAC_dm_b = 1, // done mask
5901 + DMAC_dm_m = 0x00000002, //
5902 + DMAC_mode_b = 2, //
5903 + DMAC_mode_m = 0x0000000c, //
5904 + DMAC_mode_auto_v = 0,
5905 + DMAC_mode_burst_v = 1,
5906 + DMAC_mode_transfer_v = 2, //usually used
5907 + DMAC_mode_reserved_v = 3,
5908 + DMAC_a_b = 4, //
5909 + DMAC_a_m = 0x00000010, //
5910 +
5911 + DMAS_f_b = 0, // finished (sticky)
5912 + DMAS_f_m = 0x00000001, //
5913 + DMAS_d_b = 1, // done (sticky)
5914 + DMAS_d_m = 0x00000002, //
5915 + DMAS_c_b = 2, // chain (sticky)
5916 + DMAS_c_m = 0x00000004, //
5917 + DMAS_e_b = 3, // error (sticky)
5918 + DMAS_e_m = 0x00000008, //
5919 + DMAS_h_b = 4, // halt (sticky)
5920 + DMAS_h_m = 0x00000010, //
5921 +
5922 + DMASM_f_b = 0, // finished (1=mask)
5923 + DMASM_f_m = 0x00000001, //
5924 + DMASM_d_b = 1, // done (1=mask)
5925 + DMASM_d_m = 0x00000002, //
5926 + DMASM_c_b = 2, // chain (1=mask)
5927 + DMASM_c_m = 0x00000004, //
5928 + DMASM_e_b = 3, // error (1=mask)
5929 + DMASM_e_m = 0x00000008, //
5930 + DMASM_h_b = 4, // halt (1=mask)
5931 + DMASM_h_m = 0x00000010, //
5932 +} ;
5933 +
5934 +/*
5935 + * DMA channel definitions
5936 + */
5937 +
5938 +enum
5939 +{
5940 + DMACH_ethRcv0 = 0,
5941 + DMACH_ethXmt0 = 1,
5942 + DMACH_memToFifo = 2,
5943 + DMACH_fifoToMem = 3,
5944 + DMACH_pciToMem = 4,
5945 + DMACH_memToPci = 5,
5946 +
5947 + DMACH_count //must be last
5948 +};
5949 +
5950 +
5951 +typedef struct DMAC_s
5952 +{
5953 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
5954 +} volatile *DMA_t ;
5955 +
5956 +
5957 +/*
5958 + * External DMA parameters
5959 +*/
5960 +
5961 +enum
5962 +{
5963 + DMADEVCMD_ts_b = 0, // ts field in devcmd
5964 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
5965 + DMADEVCMD_ts_byte_v = 0,
5966 + DMADEVCMD_ts_halfword_v = 1,
5967 + DMADEVCMD_ts_word_v = 2,
5968 + DMADEVCMD_ts_2word_v = 3,
5969 + DMADEVCMD_ts_4word_v = 4,
5970 + DMADEVCMD_ts_6word_v = 5,
5971 + DMADEVCMD_ts_8word_v = 6,
5972 + DMADEVCMD_ts_16word_v = 7
5973 +};
5974 +
5975 +
5976 +#endif // __IDT_DMA_H__
5977 +
5978 +
5979 +
5980 +
5981 +
5982 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h
5983 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h 1970-01-01 01:00:00.000000000 +0100
5984 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h 2006-01-10 00:32:33.000000000 +0100
5985 @@ -0,0 +1,89 @@
5986 +/**************************************************************************
5987 + *
5988 + * BRIEF MODULE DESCRIPTION
5989 + * Definitions for DMA controller.
5990 + *
5991 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5992 + *
5993 + * This program is free software; you can redistribute it and/or modify it
5994 + * under the terms of the GNU General Public License as published by the
5995 + * Free Software Foundation; either version 2 of the License, or (at your
5996 + * option) any later version.
5997 + *
5998 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5999 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6000 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6001 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6002 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6003 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6004 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6005 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6006 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6007 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6008 + *
6009 + * You should have received a copy of the GNU General Public License along
6010 + * with this program; if not, write to the Free Software Foundation, Inc.,
6011 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6012 + *
6013 + *
6014 + **************************************************************************
6015 + * May 2004 rkt, neb.
6016 + *
6017 + * Initial Release
6018 + *
6019 + *
6020 + *
6021 + **************************************************************************
6022 + */
6023 +
6024 +#ifndef __IDT_DMA_V_H__
6025 +#define __IDT_DMA_V_H__
6026 +
6027 +#include <asm/idt-boards/rc32434/rc32434_dma.h>
6028 +#include <asm/idt-boards/rc32434/rc32434.h>
6029 +
6030 +#define DMA_CHAN_OFFSET 0x14
6031 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
6032 +#define DMA_COUNT(count) \
6033 + ((count) & DMAD_count_m)
6034 +
6035 +#define DMA_HALT_TIMEOUT 500
6036 +
6037 +
6038 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
6039 +{
6040 + int timeout=1;
6041 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
6042 + rc32434_writel(0, &ch->dmac);
6043 +
6044 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
6045 + if (rc32434_readl(&ch->dmas) & DMAS_h_m) {
6046 + rc32434_writel(0, &ch->dmas);
6047 + break;
6048 + }
6049 + }
6050 +
6051 + }
6052 +
6053 + return timeout ? 0 : 1;
6054 +}
6055 +
6056 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
6057 +{
6058 + rc32434_writel(0, &ch->dmandptr);
6059 + rc32434_writel(dma_addr, &ch->dmadptr);
6060 +}
6061 +
6062 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
6063 +{
6064 + rc32434_writel(dma_addr, &ch->dmandptr);
6065 +}
6066 +
6067 +#endif // __IDT_DMA_V_H__
6068 +
6069 +
6070 +
6071 +
6072 +
6073 +
6074 +
6075 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_eth.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h
6076 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
6077 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 2006-01-10 00:32:33.000000000 +0100
6078 @@ -0,0 +1,333 @@
6079 +/**************************************************************************
6080 + *
6081 + * BRIEF MODULE DESCRIPTION
6082 + * Ethernet register definition
6083 + *
6084 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6085 + *
6086 + * This program is free software; you can redistribute it and/or modify it
6087 + * under the terms of the GNU General Public License as published by the
6088 + * Free Software Foundation; either version 2 of the License, or (at your
6089 + * option) any later version.
6090 + *
6091 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6092 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6093 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6094 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6095 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6096 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6097 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6098 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6099 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6100 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6101 + *
6102 + * You should have received a copy of the GNU General Public License along
6103 + * with this program; if not, write to the Free Software Foundation, Inc.,
6104 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6105 + *
6106 + *
6107 + **************************************************************************
6108 + * May 2004 rkt, neb.
6109 + *
6110 + * Initial Release
6111 + *
6112 + *
6113 + *
6114 + **************************************************************************
6115 + */
6116 +
6117 +#ifndef __IDT_ETH_H__
6118 +#define __IDT_ETH_H__
6119 +
6120 +
6121 +enum
6122 +{
6123 + ETH0_PhysicalAddress = 0x18060000,
6124 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
6125 +
6126 + ETH0_VirtualAddress = 0xb8060000,
6127 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
6128 +} ;
6129 +
6130 +typedef struct
6131 +{
6132 + u32 ethintfc ;
6133 + u32 ethfifott ;
6134 + u32 etharc ;
6135 + u32 ethhash0 ;
6136 + u32 ethhash1 ;
6137 + u32 ethu0 [4] ; // Reserved.
6138 + u32 ethpfs ;
6139 + u32 ethmcp ;
6140 + u32 eth_u1 [10] ; // Reserved.
6141 + u32 ethspare ;
6142 + u32 eth_u2 [42] ; // Reserved.
6143 + u32 ethsal0 ;
6144 + u32 ethsah0 ;
6145 + u32 ethsal1 ;
6146 + u32 ethsah1 ;
6147 + u32 ethsal2 ;
6148 + u32 ethsah2 ;
6149 + u32 ethsal3 ;
6150 + u32 ethsah3 ;
6151 + u32 ethrbc ;
6152 + u32 ethrpc ;
6153 + u32 ethrupc ;
6154 + u32 ethrfc ;
6155 + u32 ethtbc ;
6156 + u32 ethgpf ;
6157 + u32 eth_u9 [50] ; // Reserved.
6158 + u32 ethmac1 ;
6159 + u32 ethmac2 ;
6160 + u32 ethipgt ;
6161 + u32 ethipgr ;
6162 + u32 ethclrt ;
6163 + u32 ethmaxf ;
6164 + u32 eth_u10 ; // Reserved.
6165 + u32 ethmtest ;
6166 + u32 miimcfg ;
6167 + u32 miimcmd ;
6168 + u32 miimaddr ;
6169 + u32 miimwtd ;
6170 + u32 miimrdd ;
6171 + u32 miimind ;
6172 + u32 eth_u11 ; // Reserved.
6173 + u32 eth_u12 ; // Reserved.
6174 + u32 ethcfsa0 ;
6175 + u32 ethcfsa1 ;
6176 + u32 ethcfsa2 ;
6177 +} volatile *ETH_t;
6178 +
6179 +enum
6180 +{
6181 + ETHINTFC_en_b = 0,
6182 + ETHINTFC_en_m = 0x00000001,
6183 + ETHINTFC_its_b = 1,
6184 + ETHINTFC_its_m = 0x00000002,
6185 + ETHINTFC_rip_b = 2,
6186 + ETHINTFC_rip_m = 0x00000004,
6187 + ETHINTFC_jam_b = 3,
6188 + ETHINTFC_jam_m = 0x00000008,
6189 + ETHINTFC_ovr_b = 4,
6190 + ETHINTFC_ovr_m = 0x00000010,
6191 + ETHINTFC_und_b = 5,
6192 + ETHINTFC_und_m = 0x00000020,
6193 +
6194 + ETHFIFOTT_tth_b = 0,
6195 + ETHFIFOTT_tth_m = 0x0000007f,
6196 +
6197 + ETHARC_pro_b = 0,
6198 + ETHARC_pro_m = 0x00000001,
6199 + ETHARC_am_b = 1,
6200 + ETHARC_am_m = 0x00000002,
6201 + ETHARC_afm_b = 2,
6202 + ETHARC_afm_m = 0x00000004,
6203 + ETHARC_ab_b = 3,
6204 + ETHARC_ab_m = 0x00000008,
6205 +
6206 + ETHSAL_byte5_b = 0,
6207 + ETHSAL_byte5_m = 0x000000ff,
6208 + ETHSAL_byte4_b = 8,
6209 + ETHSAL_byte4_m = 0x0000ff00,
6210 + ETHSAL_byte3_b = 16,
6211 + ETHSAL_byte3_m = 0x00ff0000,
6212 + ETHSAL_byte2_b = 24,
6213 + ETHSAL_byte2_m = 0xff000000,
6214 +
6215 + ETHSAH_byte1_b = 0,
6216 + ETHSAH_byte1_m = 0x000000ff,
6217 + ETHSAH_byte0_b = 8,
6218 + ETHSAH_byte0_m = 0x0000ff00,
6219 +
6220 + ETHGPF_ptv_b = 0,
6221 + ETHGPF_ptv_m = 0x0000ffff,
6222 +
6223 + ETHPFS_pfd_b = 0,
6224 + ETHPFS_pfd_m = 0x00000001,
6225 +
6226 + ETHCFSA0_cfsa4_b = 0,
6227 + ETHCFSA0_cfsa4_m = 0x000000ff,
6228 + ETHCFSA0_cfsa5_b = 8,
6229 + ETHCFSA0_cfsa5_m = 0x0000ff00,
6230 +
6231 + ETHCFSA1_cfsa2_b = 0,
6232 + ETHCFSA1_cfsa2_m = 0x000000ff,
6233 + ETHCFSA1_cfsa3_b = 8,
6234 + ETHCFSA1_cfsa3_m = 0x0000ff00,
6235 +
6236 + ETHCFSA2_cfsa0_b = 0,
6237 + ETHCFSA2_cfsa0_m = 0x000000ff,
6238 + ETHCFSA2_cfsa1_b = 8,
6239 + ETHCFSA2_cfsa1_m = 0x0000ff00,
6240 +
6241 + ETHMAC1_re_b = 0,
6242 + ETHMAC1_re_m = 0x00000001,
6243 + ETHMAC1_paf_b = 1,
6244 + ETHMAC1_paf_m = 0x00000002,
6245 + ETHMAC1_rfc_b = 2,
6246 + ETHMAC1_rfc_m = 0x00000004,
6247 + ETHMAC1_tfc_b = 3,
6248 + ETHMAC1_tfc_m = 0x00000008,
6249 + ETHMAC1_lb_b = 4,
6250 + ETHMAC1_lb_m = 0x00000010,
6251 + ETHMAC1_mr_b = 31,
6252 + ETHMAC1_mr_m = 0x80000000,
6253 +
6254 + ETHMAC2_fd_b = 0,
6255 + ETHMAC2_fd_m = 0x00000001,
6256 + ETHMAC2_flc_b = 1,
6257 + ETHMAC2_flc_m = 0x00000002,
6258 + ETHMAC2_hfe_b = 2,
6259 + ETHMAC2_hfe_m = 0x00000004,
6260 + ETHMAC2_dc_b = 3,
6261 + ETHMAC2_dc_m = 0x00000008,
6262 + ETHMAC2_cen_b = 4,
6263 + ETHMAC2_cen_m = 0x00000010,
6264 + ETHMAC2_pe_b = 5,
6265 + ETHMAC2_pe_m = 0x00000020,
6266 + ETHMAC2_vpe_b = 6,
6267 + ETHMAC2_vpe_m = 0x00000040,
6268 + ETHMAC2_ape_b = 7,
6269 + ETHMAC2_ape_m = 0x00000080,
6270 + ETHMAC2_ppe_b = 8,
6271 + ETHMAC2_ppe_m = 0x00000100,
6272 + ETHMAC2_lpe_b = 9,
6273 + ETHMAC2_lpe_m = 0x00000200,
6274 + ETHMAC2_nb_b = 12,
6275 + ETHMAC2_nb_m = 0x00001000,
6276 + ETHMAC2_bp_b = 13,
6277 + ETHMAC2_bp_m = 0x00002000,
6278 + ETHMAC2_ed_b = 14,
6279 + ETHMAC2_ed_m = 0x00004000,
6280 +
6281 + ETHIPGT_ipgt_b = 0,
6282 + ETHIPGT_ipgt_m = 0x0000007f,
6283 +
6284 + ETHIPGR_ipgr2_b = 0,
6285 + ETHIPGR_ipgr2_m = 0x0000007f,
6286 + ETHIPGR_ipgr1_b = 8,
6287 + ETHIPGR_ipgr1_m = 0x00007f00,
6288 +
6289 + ETHCLRT_maxret_b = 0,
6290 + ETHCLRT_maxret_m = 0x0000000f,
6291 + ETHCLRT_colwin_b = 8,
6292 + ETHCLRT_colwin_m = 0x00003f00,
6293 +
6294 + ETHMAXF_maxf_b = 0,
6295 + ETHMAXF_maxf_m = 0x0000ffff,
6296 +
6297 + ETHMTEST_tb_b = 2,
6298 + ETHMTEST_tb_m = 0x00000004,
6299 +
6300 + ETHMCP_div_b = 0,
6301 + ETHMCP_div_m = 0x000000ff,
6302 +
6303 + MIIMCFG_rsv_b = 0,
6304 + MIIMCFG_rsv_m = 0x0000000c,
6305 +
6306 + MIIMCMD_rd_b = 0,
6307 + MIIMCMD_rd_m = 0x00000001,
6308 + MIIMCMD_scn_b = 1,
6309 + MIIMCMD_scn_m = 0x00000002,
6310 +
6311 + MIIMADDR_regaddr_b = 0,
6312 + MIIMADDR_regaddr_m = 0x0000001f,
6313 + MIIMADDR_phyaddr_b = 8,
6314 + MIIMADDR_phyaddr_m = 0x00001f00,
6315 +
6316 + MIIMWTD_wdata_b = 0,
6317 + MIIMWTD_wdata_m = 0x0000ffff,
6318 +
6319 + MIIMRDD_rdata_b = 0,
6320 + MIIMRDD_rdata_m = 0x0000ffff,
6321 +
6322 + MIIMIND_bsy_b = 0,
6323 + MIIMIND_bsy_m = 0x00000001,
6324 + MIIMIND_scn_b = 1,
6325 + MIIMIND_scn_m = 0x00000002,
6326 + MIIMIND_nv_b = 2,
6327 + MIIMIND_nv_m = 0x00000004,
6328 +
6329 +} ;
6330 +
6331 +/*
6332 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
6333 + */
6334 +enum
6335 +{
6336 + ETHRX_fd_b = 0,
6337 + ETHRX_fd_m = 0x00000001,
6338 + ETHRX_ld_b = 1,
6339 + ETHRX_ld_m = 0x00000002,
6340 + ETHRX_rok_b = 2,
6341 + ETHRX_rok_m = 0x00000004,
6342 + ETHRX_fm_b = 3,
6343 + ETHRX_fm_m = 0x00000008,
6344 + ETHRX_mp_b = 4,
6345 + ETHRX_mp_m = 0x00000010,
6346 + ETHRX_bp_b = 5,
6347 + ETHRX_bp_m = 0x00000020,
6348 + ETHRX_vlt_b = 6,
6349 + ETHRX_vlt_m = 0x00000040,
6350 + ETHRX_cf_b = 7,
6351 + ETHRX_cf_m = 0x00000080,
6352 + ETHRX_ovr_b = 8,
6353 + ETHRX_ovr_m = 0x00000100,
6354 + ETHRX_crc_b = 9,
6355 + ETHRX_crc_m = 0x00000200,
6356 + ETHRX_cv_b = 10,
6357 + ETHRX_cv_m = 0x00000400,
6358 + ETHRX_db_b = 11,
6359 + ETHRX_db_m = 0x00000800,
6360 + ETHRX_le_b = 12,
6361 + ETHRX_le_m = 0x00001000,
6362 + ETHRX_lor_b = 13,
6363 + ETHRX_lor_m = 0x00002000,
6364 + ETHRX_ces_b = 14,
6365 + ETHRX_ces_m = 0x00004000,
6366 + ETHRX_length_b = 16,
6367 + ETHRX_length_m = 0xffff0000,
6368 +
6369 + ETHTX_fd_b = 0,
6370 + ETHTX_fd_m = 0x00000001,
6371 + ETHTX_ld_b = 1,
6372 + ETHTX_ld_m = 0x00000002,
6373 + ETHTX_oen_b = 2,
6374 + ETHTX_oen_m = 0x00000004,
6375 + ETHTX_pen_b = 3,
6376 + ETHTX_pen_m = 0x00000008,
6377 + ETHTX_cen_b = 4,
6378 + ETHTX_cen_m = 0x00000010,
6379 + ETHTX_hen_b = 5,
6380 + ETHTX_hen_m = 0x00000020,
6381 + ETHTX_tok_b = 6,
6382 + ETHTX_tok_m = 0x00000040,
6383 + ETHTX_mp_b = 7,
6384 + ETHTX_mp_m = 0x00000080,
6385 + ETHTX_bp_b = 8,
6386 + ETHTX_bp_m = 0x00000100,
6387 + ETHTX_und_b = 9,
6388 + ETHTX_und_m = 0x00000200,
6389 + ETHTX_of_b = 10,
6390 + ETHTX_of_m = 0x00000400,
6391 + ETHTX_ed_b = 11,
6392 + ETHTX_ed_m = 0x00000800,
6393 + ETHTX_ec_b = 12,
6394 + ETHTX_ec_m = 0x00001000,
6395 + ETHTX_lc_b = 13,
6396 + ETHTX_lc_m = 0x00002000,
6397 + ETHTX_td_b = 14,
6398 + ETHTX_td_m = 0x00004000,
6399 + ETHTX_crc_b = 15,
6400 + ETHTX_crc_m = 0x00008000,
6401 + ETHTX_le_b = 16,
6402 + ETHTX_le_m = 0x00010000,
6403 + ETHTX_cc_b = 17,
6404 + ETHTX_cc_m = 0x001E0000,
6405 +} ;
6406 +
6407 +#endif // __IDT_ETH_H__
6408 +
6409 +
6410 +
6411 +
6412 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h
6413 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h 1970-01-01 01:00:00.000000000 +0100
6414 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h 2006-01-10 00:32:33.000000000 +0100
6415 @@ -0,0 +1,77 @@
6416 +/**************************************************************************
6417 + *
6418 + * BRIEF MODULE DESCRIPTION
6419 + * Ethernet register definition
6420 + *
6421 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6422 + *
6423 + * This program is free software; you can redistribute it and/or modify it
6424 + * under the terms of the GNU General Public License as published by the
6425 + * Free Software Foundation; either version 2 of the License, or (at your
6426 + * option) any later version.
6427 + *
6428 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6429 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6430 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6431 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6432 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6433 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6434 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6435 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6436 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6437 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6438 + *
6439 + * You should have received a copy of the GNU General Public License along
6440 + * with this program; if not, write to the Free Software Foundation, Inc.,
6441 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6442 + *
6443 + *
6444 + **************************************************************************
6445 + * May 2004 rkt, neb.
6446 + *
6447 + * Initial Release
6448 + *
6449 + *
6450 + *
6451 + **************************************************************************
6452 + */
6453 +
6454 +#ifndef __IDT_ETH_V_H__
6455 +#define __IDT_ETH_V_H__
6456 +
6457 +#include <asm/idt-boards/rc32434/rc32434_eth.h>
6458 +
6459 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
6460 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
6461 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
6462 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
6463 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
6464 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
6465 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
6466 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
6467 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
6468 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
6469 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
6470 +
6471 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
6472 +
6473 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
6474 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
6475 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
6476 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
6477 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
6478 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
6479 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
6480 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
6481 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
6482 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
6483 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
6484 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
6485 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
6486 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
6487 +#endif // __IDT_ETH_V_H__
6488 +
6489 +
6490 +
6491 +
6492 +
6493 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h
6494 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h 1970-01-01 01:00:00.000000000 +0100
6495 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h 2006-01-10 00:32:33.000000000 +0100
6496 @@ -0,0 +1,167 @@
6497 +/**************************************************************************
6498 + *
6499 + * BRIEF MODULE DESCRIPTION
6500 + * GPIO register definition
6501 + *
6502 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6503 + *
6504 + * This program is free software; you can redistribute it and/or modify it
6505 + * under the terms of the GNU General Public License as published by the
6506 + * Free Software Foundation; either version 2 of the License, or (at your
6507 + * option) any later version.
6508 + *
6509 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6510 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6511 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6512 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6513 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6514 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6515 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6516 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6517 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6518 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6519 + *
6520 + * You should have received a copy of the GNU General Public License along
6521 + * with this program; if not, write to the Free Software Foundation, Inc.,
6522 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6523 + *
6524 + *
6525 + **************************************************************************
6526 + * May 2004 rkt, neb.
6527 + *
6528 + * Initial Release
6529 + *
6530 + *
6531 + *
6532 + **************************************************************************
6533 + */
6534 +
6535 +#ifndef __IDT_GPIO_H__
6536 +#define __IDT_GPIO_H__
6537 +
6538 +enum
6539 +{
6540 + GPIO0_PhysicalAddress = 0x18050000,
6541 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
6542 +
6543 + GPIO0_VirtualAddress = 0xb8050000,
6544 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
6545 +} ;
6546 +
6547 +typedef struct
6548 +{
6549 + u32 gpiofunc; /* GPIO Function Register
6550 + * gpiofunc[x]==0 bit = gpio
6551 + * func[x]==1 bit = altfunc
6552 + */
6553 + u32 gpiocfg; /* GPIO Configuration Register
6554 + * gpiocfg[x]==0 bit = input
6555 + * gpiocfg[x]==1 bit = output
6556 + */
6557 + u32 gpiod; /* GPIO Data Register
6558 + * gpiod[x] read/write gpio pinX status
6559 + */
6560 + u32 gpioilevel; /* GPIO Interrupt Status Register
6561 + * interrupt level (see gpioistat)
6562 + */
6563 + u32 gpioistat; /* Gpio Interrupt Status Register
6564 + * istat[x] = (gpiod[x] == level[x])
6565 + * cleared in ISR (STICKY bits)
6566 + */
6567 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
6568 +} volatile * GPIO_t ;
6569 +
6570 +typedef enum
6571 +{
6572 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
6573 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
6574 + GPIO_input_v = 0, // gpiocfg use pin as input.
6575 + GPIO_output_v = 1, // gpiocfg use pin as output.
6576 + GPIO_pin0_b = 0,
6577 + GPIO_pin0_m = 0x00000001,
6578 + GPIO_pin1_b = 1,
6579 + GPIO_pin1_m = 0x00000002,
6580 + GPIO_pin2_b = 2,
6581 + GPIO_pin2_m = 0x00000004,
6582 + GPIO_pin3_b = 3,
6583 + GPIO_pin3_m = 0x00000008,
6584 + GPIO_pin4_b = 4,
6585 + GPIO_pin4_m = 0x00000010,
6586 + GPIO_pin5_b = 5,
6587 + GPIO_pin5_m = 0x00000020,
6588 + GPIO_pin6_b = 6,
6589 + GPIO_pin6_m = 0x00000040,
6590 + GPIO_pin7_b = 7,
6591 + GPIO_pin7_m = 0x00000080,
6592 + GPIO_pin8_b = 8,
6593 + GPIO_pin8_m = 0x00000100,
6594 + GPIO_pin9_b = 9,
6595 + GPIO_pin9_m = 0x00000200,
6596 + GPIO_pin10_b = 10,
6597 + GPIO_pin10_m = 0x00000400,
6598 + GPIO_pin11_b = 11,
6599 + GPIO_pin11_m = 0x00000800,
6600 + GPIO_pin12_b = 12,
6601 + GPIO_pin12_m = 0x00001000,
6602 + GPIO_pin13_b = 13,
6603 + GPIO_pin13_m = 0x00002000,
6604 +
6605 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
6606 +
6607 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
6608 + GPIO_u0sout_m = GPIO_pin0_m,
6609 + GPIO_u0sout_cfg_v = GPIO_output_v,
6610 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
6611 + GPIO_u0sinp_m = GPIO_pin1_m,
6612 + GPIO_u0sinp_cfg_v = GPIO_input_v,
6613 + GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
6614 + GPIO_u0rtsn_m = GPIO_pin2_m,
6615 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
6616 + GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
6617 + GPIO_u0ctsn_m = GPIO_pin3_m,
6618 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
6619 +
6620 + GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
6621 + GPIO_maddr22_m = GPIO_pin4_m,
6622 + GPIO_maddr22_cfg_v = GPIO_output_v,
6623 +
6624 + GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
6625 + GPIO_maddr23_m = GPIO_pin5_m,
6626 + GPIO_maddr23_cfg_v = GPIO_output_v,
6627 +
6628 + GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
6629 + GPIO_maddr24_m = GPIO_pin6_m,
6630 + GPIO_maddr24_cfg_v = GPIO_output_v,
6631 +
6632 + GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
6633 + GPIO_maddr25_m = GPIO_pin7_m,
6634 + GPIO_maddr25_cfg_v = GPIO_output_v,
6635 +
6636 + GPIO_cpudmadebug_b = GPIO_pin8_b, // CPU or DMA debug pin
6637 + GPIO_cpudmadebug_m = GPIO_pin8_m,
6638 + GPIO_cpudmadebug_cfg_v = GPIO_output_v,
6639 +
6640 + GPIO_pcireq4_b = GPIO_pin9_b, // PCI Request 4
6641 + GPIO_pcireq4_m = GPIO_pin9_m,
6642 + GPIO_pcireq4_cfg_v = GPIO_input_v,
6643 +
6644 + GPIO_pcigrant4_b = GPIO_pin10_b, // PCI Grant 4
6645 + GPIO_pcigrant4_m = GPIO_pin10_m,
6646 + GPIO_pcigrant4_cfg_v = GPIO_output_v,
6647 +
6648 + GPIO_pcireq5_b = GPIO_pin11_b, // PCI Request 5
6649 + GPIO_pcireq5_m = GPIO_pin11_m,
6650 + GPIO_pcireq5_cfg_v = GPIO_input_v,
6651 +
6652 + GPIO_pcigrant5_b = GPIO_pin12_b, // PCI Grant 5
6653 + GPIO_pcigrant5_m = GPIO_pin12_m,
6654 + GPIO_pcigrant5_cfg_v = GPIO_output_v,
6655 +
6656 + GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
6657 + GPIO_pcimuintn_m = GPIO_pin13_m,
6658 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
6659 +
6660 +} GPIO_DEFS_t;
6661 +
6662 +#endif // __IDT_GPIO_H__
6663 +
6664 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434.h
6665 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434.h 1970-01-01 01:00:00.000000000 +0100
6666 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434.h 2006-01-10 00:32:33.000000000 +0100
6667 @@ -0,0 +1,199 @@
6668 + /**************************************************************************
6669 + *
6670 + * BRIEF MODULE DESCRIPTION
6671 + * Definitions for IDT RC32434 CPU
6672 + *
6673 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6674 + *
6675 + * This program is free software; you can redistribute it and/or modify it
6676 + * under the terms of the GNU General Public License as published by the
6677 + * Free Software Foundation; either version 2 of the License, or (at your
6678 + * option) any later version.
6679 + *
6680 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6681 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6682 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6683 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6684 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6685 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6686 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6687 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6688 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6689 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6690 + *
6691 + * You should have received a copy of the GNU General Public License along
6692 + * with this program; if not, write to the Free Software Foundation, Inc.,
6693 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6694 + *
6695 + *
6696 + **************************************************************************
6697 + * May 2004 rkt, neb.
6698 + *
6699 + * Initial Release
6700 + *
6701 + *
6702 + *
6703 + **************************************************************************
6704 + */
6705 +
6706 +#ifndef _RC32434_H_
6707 +#define _RC32434_H_
6708 +
6709 +#include <linux/config.h>
6710 +#include <linux/delay.h>
6711 +#include <asm/io.h>
6712 +#include <asm/idt-boards/rc32434/rc32434_timer.h>
6713 +
6714 +#define RC32434_REG_BASE 0x18000000
6715 +
6716 +
6717 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
6718 +#define idt_timer ((volatile TIM_t) TIM0_VirtualAddress)
6719 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
6720 +
6721 +#define IDT_CLOCK_MULT 2
6722 +#define MIPS_CPU_TIMER_IRQ 7
6723 +/* Interrupt Controller */
6724 +#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
6725 +#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
6726 +#define IC_GROUP_OFFSET 0x0C
6727 +#define RTC_BASE 0xBA001FF0
6728 +
6729 +#define NUM_INTR_GROUPS 5
6730 +/* 16550 UARTs */
6731 +
6732 +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
6733 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
6734 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
6735 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
6736 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
6737 +
6738 +#ifdef __MIPSEB__
6739 +
6740 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
6741 +#define EB434_UART1_BASE (0x19800003)
6742 +
6743 +#else
6744 +
6745 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
6746 +#define EB434_UART1_BASE (0x19800000)
6747 +
6748 +#endif
6749 +
6750 +#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
6751 +#define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
6752 +
6753 +#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
6754 +
6755 +/* cpu pipeline flush */
6756 +static inline void rc32434_sync(void)
6757 +{
6758 + __asm__ volatile ("sync");
6759 +}
6760 +
6761 +static inline void rc32434_sync_udelay(int us)
6762 +{
6763 + __asm__ volatile ("sync");
6764 + udelay(us);
6765 +}
6766 +
6767 +static inline void rc32434_sync_delay(int ms)
6768 +{
6769 + __asm__ volatile ("sync");
6770 + mdelay(ms);
6771 +}
6772 +
6773 +
6774 +
6775 +/*
6776 + * Macros to access internal RC32434 registers. No byte
6777 + * swapping should be done when accessing the internal
6778 + * registers.
6779 + */
6780 +
6781 +#define rc32434_readb __raw_readb
6782 +#define rc32434_readw __raw_readw
6783 +#define rc32434_readl __raw_readl
6784 +
6785 +#define rc32434_writeb __raw_writeb
6786 +#define rc32434_writew __raw_writew
6787 +#define rc32434_writel __raw_writel
6788 +
6789 +#if 0
6790 +static inline u8 rc32434_readb(unsigned long pa)
6791 +{
6792 + return *((volatile u8 *)KSEG1ADDR(pa));
6793 +}
6794 +static inline u16 rc32434_readw(unsigned long pa)
6795 +{
6796 + return *((volatile u16 *)KSEG1ADDR(pa));
6797 +}
6798 +static inline u32 rc32434_readl(unsigned long pa)
6799 +{
6800 + return *((volatile u32 *)KSEG1ADDR(pa));
6801 +}
6802 +static inline void rc32434_writeb(u8 val, unsigned long pa)
6803 +{
6804 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
6805 +}
6806 +static inline void rc32434_writew(u16 val, unsigned long pa)
6807 +{
6808 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
6809 +}
6810 +static inline void rc32434_writel(u32 val, unsigned long pa)
6811 +{
6812 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
6813 +}
6814 +
6815 +#endif
6816 +
6817 +
6818 +/*
6819 + * C access to CLZ and CLO instructions
6820 + * (count leading zeroes/ones).
6821 + */
6822 +static inline int rc32434_clz(unsigned long val)
6823 +{
6824 + int ret;
6825 + __asm__ volatile (
6826 + ".set\tnoreorder\n\t"
6827 + ".set\tnoat\n\t"
6828 + ".set\tmips32\n\t"
6829 + "clz\t%0,%1\n\t"
6830 + ".set\tmips0\n\t"
6831 + ".set\tat\n\t"
6832 + ".set\treorder"
6833 + : "=r" (ret)
6834 + : "r" (val));
6835 +
6836 + return ret;
6837 +}
6838 +static inline int rc32434_clo(unsigned long val)
6839 +{
6840 + int ret;
6841 + __asm__ volatile (
6842 + ".set\tnoreorder\n\t"
6843 + ".set\tnoat\n\t"
6844 + ".set\tmips32\n\t"
6845 + "clo\t%0,%1\n\t"
6846 + ".set\tmips0\n\t"
6847 + ".set\tat\n\t"
6848 + ".set\treorder"
6849 + : "=r" (ret)
6850 + : "r" (val));
6851 +
6852 + return ret;
6853 +}
6854 +#endif /* _RC32434_H_ */
6855 +
6856 +
6857 +
6858 +
6859 +
6860 +
6861 +
6862 +
6863 +
6864 +
6865 +
6866 +
6867 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_integ.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h
6868 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_integ.h 1970-01-01 01:00:00.000000000 +0100
6869 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h 2006-01-10 00:32:33.000000000 +0100
6870 @@ -0,0 +1,90 @@
6871 +/**************************************************************************
6872 + *
6873 + * BRIEF MODULE DESCRIPTION
6874 + * System Integrity register definition
6875 + *
6876 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6877 + *
6878 + * This program is free software; you can redistribute it and/or modify it
6879 + * under the terms of the GNU General Public License as published by the
6880 + * Free Software Foundation; either version 2 of the License, or (at your
6881 + * option) any later version.
6882 + *
6883 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6884 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6885 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6886 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6887 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6888 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6889 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6890 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6891 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6892 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6893 + *
6894 + * You should have received a copy of the GNU General Public License along
6895 + * with this program; if not, write to the Free Software Foundation, Inc.,
6896 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6897 + *
6898 + *
6899 + **************************************************************************
6900 + * May 2004 rkt, neb
6901 + *
6902 + * Initial Release
6903 + *
6904 + *
6905 + *
6906 + **************************************************************************
6907 + */
6908 +
6909 +#ifndef __IDT_INTEG_H__
6910 +#define __IDT_INTEG_H__
6911 +
6912 +enum
6913 +{
6914 + INTEG0_PhysicalAddress = 0x18030000,
6915 + INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default
6916 +
6917 + INTEG0_VirtualAddress = 0xB8030000,
6918 + INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default
6919 +} ;
6920 +
6921 +// if you are looking for CEA, try rst.h
6922 +typedef struct
6923 +{
6924 + u32 filler [0xc] ; // 0x30 bytes unused.
6925 + u32 errcs ; // sticky use ERRCS_
6926 + u32 wtcount ; // Watchdog timer count reg.
6927 + u32 wtcompare ; // Watchdog timer timeout value.
6928 + u32 wtc ; // Watchdog timer control. use WTC_
6929 +} volatile *INTEG_t ;
6930 +
6931 +enum
6932 +{
6933 + ERRCS_wto_b = 0, // In INTEG_t -> errcs
6934 + ERRCS_wto_m = 0x00000001,
6935 + ERRCS_wne_b = 1, // In INTEG_t -> errcs
6936 + ERRCS_wne_m = 0x00000002,
6937 + ERRCS_ucw_b = 2, // In INTEG_t -> errcs
6938 + ERRCS_ucw_m = 0x00000004,
6939 + ERRCS_ucr_b = 3, // In INTEG_t -> errcs
6940 + ERRCS_ucr_m = 0x00000008,
6941 + ERRCS_upw_b = 4, // In INTEG_t -> errcs
6942 + ERRCS_upw_m = 0x00000010,
6943 + ERRCS_upr_b = 5, // In INTEG_t -> errcs
6944 + ERRCS_upr_m = 0x00000020,
6945 + ERRCS_udw_b = 6, // In INTEG_t -> errcs
6946 + ERRCS_udw_m = 0x00000040,
6947 + ERRCS_udr_b = 7, // In INTEG_t -> errcs
6948 + ERRCS_udr_m = 0x00000080,
6949 + ERRCS_sae_b = 8, // In INTEG_t -> errcs
6950 + ERRCS_sae_m = 0x00000100,
6951 + ERRCS_wre_b = 9, // In INTEG_t -> errcs
6952 + ERRCS_wre_m = 0x00000200,
6953 +
6954 + WTC_en_b = 0, // In INTEG_t -> wtc
6955 + WTC_en_m = 0x00000001,
6956 + WTC_to_b = 1, // In INTEG_t -> wtc
6957 + WTC_to_m = 0x00000002,
6958 +} ;
6959 +
6960 +#endif // __IDT_INTEG_H__
6961 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_int.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h
6962 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_int.h 1970-01-01 01:00:00.000000000 +0100
6963 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h 2006-01-10 00:32:33.000000000 +0100
6964 @@ -0,0 +1,174 @@
6965 +/**************************************************************************
6966 + *
6967 + * BRIEF MODULE DESCRIPTION
6968 + * Interrupt Controller register definition.
6969 + *
6970 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6971 + *
6972 + * This program is free software; you can redistribute it and/or modify it
6973 + * under the terms of the GNU General Public License as published by the
6974 + * Free Software Foundation; either version 2 of the License, or (at your
6975 + * option) any later version.
6976 + *
6977 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6978 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6979 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6980 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6981 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6982 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6983 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6984 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6985 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6986 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6987 + *
6988 + * You should have received a copy of the GNU General Public License along
6989 + * with this program; if not, write to the Free Software Foundation, Inc.,
6990 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6991 + *
6992 + *
6993 + **************************************************************************
6994 + * May 2004 rkt, neb.
6995 + *
6996 + * Initial Release
6997 + *
6998 + *
6999 + *
7000 + **************************************************************************
7001 + */
7002 +
7003 +#ifndef __IDT_INT_H__
7004 +#define __IDT_INT_H__
7005 +
7006 +enum
7007 +{
7008 + INT0_PhysicalAddress = 0x18038000,
7009 + INT_PhysicalAddress = INT0_PhysicalAddress, // Default
7010 +
7011 + INT0_VirtualAddress = 0xB8038000,
7012 + INT_VirtualAddress = INT0_VirtualAddress, // Default
7013 +} ;
7014 +
7015 +struct INT_s
7016 +{
7017 + u32 ipend ; //Pending interrupts. use INT?_
7018 + u32 itest ; //Test bits. use INT?_
7019 + u32 imask ; //Interrupt disabled when set. use INT?_
7020 +} ;
7021 +
7022 +enum
7023 +{
7024 + IPEND2 = 0, // HW 2 interrupt to core. use INT2_
7025 + IPEND3 = 1, // HW 3 interrupt to core. use INT3_
7026 + IPEND4 = 2, // HW 4 interrupt to core. use INT4_
7027 + IPEND5 = 3, // HW 5 interrupt to core. use INT5_
7028 + IPEND6 = 4, // HW 6 interrupt to core. use INT6_
7029 +
7030 + IPEND_count, // must be last (used in loops)
7031 + IPEND_min = IPEND2 // min IPEND (used in loops)
7032 +};
7033 +
7034 +typedef struct INTC_s
7035 +{
7036 + struct INT_s i [IPEND_count] ;// use i[IPEND?] = INT?_
7037 + u32 nmips ; // use NMIPS_
7038 +} volatile *INT_t ;
7039 +
7040 +enum
7041 +{
7042 + INT2_timer0_b = 0,
7043 + INT2_timer0_m = 0x00000001,
7044 + INT2_timer1_b = 1,
7045 + INT2_timer1_m = 0x00000002,
7046 + INT2_timer2_b = 2,
7047 + INT2_timer2_m = 0x00000004,
7048 + INT2_refresh_b = 3,
7049 + INT2_refresh_m = 0x00000008,
7050 + INT2_watchdogTimeout_b = 4,
7051 + INT2_watchdogTimeout_m = 0x00000010,
7052 + INT2_undecodedCpuWrite_b = 5,
7053 + INT2_undecodedCpuWrite_m = 0x00000020,
7054 + INT2_undecodedCpuRead_b = 6,
7055 + INT2_undecodedCpuRead_m = 0x00000040,
7056 + INT2_undecodedPciWrite_b = 7,
7057 + INT2_undecodedPciWrite_m = 0x00000080,
7058 + INT2_undecodedPciRead_b = 8,
7059 + INT2_undecodedPciRead_m = 0x00000100,
7060 + INT2_undecodedDmaWrite_b = 9,
7061 + INT2_undecodedDmaWrite_m = 0x00000200,
7062 + INT2_undecodedDmaRead_b = 10,
7063 + INT2_undecodedDmaRead_m = 0x00000400,
7064 + INT2_ipBusSlaveAckError_b = 11,
7065 + INT2_ipBusSlaveAckError_m = 0x00000800,
7066 +
7067 + INT3_dmaChannel0_b = 0,
7068 + INT3_dmaChannel0_m = 0x00000001,
7069 + INT3_dmaChannel1_b = 1,
7070 + INT3_dmaChannel1_m = 0x00000002,
7071 + INT3_dmaChannel2_b = 2,
7072 + INT3_dmaChannel2_m = 0x00000004,
7073 + INT3_dmaChannel3_b = 3,
7074 + INT3_dmaChannel3_m = 0x00000008,
7075 + INT3_dmaChannel4_b = 4,
7076 + INT3_dmaChannel4_m = 0x00000010,
7077 + INT3_dmaChannel5_b = 5,
7078 + INT3_dmaChannel5_m = 0x00000020,
7079 +
7080 + INT5_uartGeneral0_b = 0,
7081 + INT5_uartGeneral0_m = 0x00000001,
7082 + INT5_uartTxrdy0_b = 1,
7083 + INT5_uartTxrdy0_m = 0x00000002,
7084 + INT5_uartRxrdy0_b = 2,
7085 + INT5_uartRxrdy0_m = 0x00000004,
7086 + INT5_pci_b = 3,
7087 + INT5_pci_m = 0x00000008,
7088 + INT5_pciDecoupled_b = 4,
7089 + INT5_pciDecoupled_m = 0x00000010,
7090 + INT5_spi_b = 5,
7091 + INT5_spi_m = 0x00000020,
7092 + INT5_deviceDecoupled_b = 6,
7093 + INT5_deviceDecoupled_m = 0x00000040,
7094 + INT5_eth0Ovr_b = 9,
7095 + INT5_eth0Ovr_m = 0x00000200,
7096 + INT5_eth0Und_b = 10,
7097 + INT5_eth0Und_m = 0x00000400,
7098 + INT5_eth0Pfd_b = 11,
7099 + INT5_eth0Pfd_m = 0x00000800,
7100 + INT5_nvram_b = 12,
7101 + INT5_nvram_m = 0x00001000,
7102 +
7103 + INT6_gpio0_b = 0,
7104 + INT6_gpio0_m = 0x00000001,
7105 + INT6_gpio1_b = 1,
7106 + INT6_gpio1_m = 0x00000002,
7107 + INT6_gpio2_b = 2,
7108 + INT6_gpio2_m = 0x00000004,
7109 + INT6_gpio3_b = 3,
7110 + INT6_gpio3_m = 0x00000008,
7111 + INT6_gpio4_b = 4,
7112 + INT6_gpio4_m = 0x00000010,
7113 + INT6_gpio5_b = 5,
7114 + INT6_gpio5_m = 0x00000020,
7115 + INT6_gpio6_b = 6,
7116 + INT6_gpio6_m = 0x00000040,
7117 + INT6_gpio7_b = 7,
7118 + INT6_gpio7_m = 0x00000080,
7119 + INT6_gpio8_b = 8,
7120 + INT6_gpio8_m = 0x00000100,
7121 + INT6_gpio9_b = 9,
7122 + INT6_gpio9_m = 0x00000200,
7123 + INT6_gpio10_b = 10,
7124 + INT6_gpio10_m = 0x00000400,
7125 + INT6_gpio11_b = 11,
7126 + INT6_gpio11_m = 0x00000800,
7127 + INT6_gpio12_b = 12,
7128 + INT6_gpio12_m = 0x00001000,
7129 + INT6_gpio13_b = 13,
7130 + INT6_gpio13_m = 0x00002000,
7131 +
7132 + NMIPS_gpio_b = 0,
7133 + NMIPS_gpio_m = 0x00000001,
7134 +} ;
7135 +
7136 +#endif // __IDT_INT_H__
7137 +
7138 +
7139 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h
7140 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h 1970-01-01 01:00:00.000000000 +0100
7141 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h 2006-01-10 00:32:33.000000000 +0100
7142 @@ -0,0 +1,111 @@
7143 +/**************************************************************************
7144 + *
7145 + * BRIEF MODULE DESCRIPTION
7146 + * IP Arbiter register definitions
7147 + *
7148 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7149 + *
7150 + * This program is free software; you can redistribute it and/or modify it
7151 + * under the terms of the GNU General Public License as published by the
7152 + * Free Software Foundation; either version 2 of the License, or (at your
7153 + * option) any later version.
7154 + *
7155 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7156 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7157 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7158 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7159 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7160 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7161 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7162 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7163 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7164 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7165 + *
7166 + * You should have received a copy of the GNU General Public License along
7167 + * with this program; if not, write to the Free Software Foundation, Inc.,
7168 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7169 + *
7170 + *
7171 + **************************************************************************
7172 + * May 2004 rkt,neb
7173 + *
7174 + * Initial Release
7175 + *
7176 + *
7177 + *
7178 + **************************************************************************
7179 + */
7180 +
7181 +#ifndef __IDT_IPARB_H__
7182 +#define __IDT_IPARB_H__
7183 +
7184 +enum
7185 +{
7186 + IPARB0_PhysicalAddress = 0x18048000,
7187 + IPARB_PhysicalAddress = IPARB0_PhysicalAddress, // Default
7188 +
7189 + IPARB0_VirtualAddress = 0xB8048000,
7190 + IPARB_VirtualAddress = IPARB0_VirtualAddress, // Default
7191 +} ;
7192 +
7193 +enum
7194 +{
7195 + IPABMXC_ethernet0Receive = 0,
7196 + IPABMXC_ethernet0Transmit = 1,
7197 + IPABMXC_memoryToHoldFifo = 2,
7198 + IPABMXC_holdFifoToMemory = 3,
7199 + IPABMXC_pciToMemory = 4,
7200 + IPABMXC_memoryToPci = 5,
7201 + IPABMXC_pciTarget = 6,
7202 + IPABMXC_pciTargetStart = 7,
7203 + IPABMXC_cpuToIpBus = 8,
7204 +
7205 + IPABMXC_Count, // Must be last in list !
7206 + IPABMXC_Min = IPABMXC_ethernet0Receive,
7207 +
7208 + IPAPXC_PriorityCount = 4, // 3-highest, 0-lowest.
7209 +} ;
7210 +
7211 +typedef struct
7212 +{
7213 + u32 ipapc [IPAPXC_PriorityCount] ; // ipapc[IPAPXC_] = IPAPC_
7214 + u32 ipabmc [IPABMXC_Count] ; // ipabmc[IPABMXC_] = IPABMC_
7215 + u32 ipac ; // use IPAC_
7216 + u32 ipaitcc; // use IPAITCC_
7217 + u32 ipaspare ;
7218 +} volatile * IPARB_t ;
7219 +
7220 +enum
7221 +{
7222 + IPAC_dp_b = 0,
7223 + IPAC_dp_m = 0x00000001,
7224 + IPAC_dep_b = 1,
7225 + IPAC_dep_m = 0x00000002,
7226 + IPAC_drm_b = 2,
7227 + IPAC_drm_m = 0x00000004,
7228 + IPAC_dwm_b = 3,
7229 + IPAC_dwm_m = 0x00000008,
7230 + IPAC_msk_b = 4,
7231 + IPAC_msk_m = 0x00000010,
7232 +
7233 + IPAPC_ptc_b = 0,
7234 + IPAPC_ptc_m = 0x00003fff,
7235 + IPAPC_mf_b = 14,
7236 + IPAPC_mf_m = 0x00004000,
7237 + IPAPC_cptc_b = 16,
7238 + IPAPC_cptc_m = 0x3fff0000,
7239 +
7240 + IPAITCC_itcc = 0,
7241 + IPAITCC_itcc, = 0x000001ff,
7242 +
7243 + IPABMC_mtc_b = 0,
7244 + IPABMC_mtc_m = 0x00000fff,
7245 + IPABMC_p_b = 12,
7246 + IPABMC_p_m = 0x00003000,
7247 + IPABMC_msk_b = 14,
7248 + IPABMC_msk_m = 0x00004000,
7249 + IPABMC_cmtc_b = 16,
7250 + IPABMC_cmtc_m = 0x0fff0000,
7251 +};
7252 +
7253 +#endif // __IDT_IPARB_H__
7254 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_pci.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h
7255 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 1970-01-01 01:00:00.000000000 +0100
7256 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 2006-01-10 00:32:33.000000000 +0100
7257 @@ -0,0 +1,695 @@
7258 +/**************************************************************************
7259 + *
7260 + * BRIEF MODULE DESCRIPTION
7261 + * PCI register definitio
7262 + *
7263 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7264 + *
7265 + * This program is free software; you can redistribute it and/or modify it
7266 + * under the terms of the GNU General Public License as published by the
7267 + * Free Software Foundation; either version 2 of the License, or (at your
7268 + * option) any later version.
7269 + *
7270 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7271 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7272 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7273 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7274 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7275 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7276 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7277 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7278 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7279 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7280 + *
7281 + * You should have received a copy of the GNU General Public License along
7282 + * with this program; if not, write to the Free Software Foundation, Inc.,
7283 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7284 + *
7285 + *
7286 + **************************************************************************
7287 + * May 2004 rkt, neb.
7288 + *
7289 + * Initial Release
7290 + *
7291 + *
7292 + *
7293 + **************************************************************************
7294 + */
7295 +
7296 +#ifndef __IDT_PCI_H__
7297 +#define __IDT_PCI_H__
7298 +
7299 +enum
7300 +{
7301 + PCI0_PhysicalAddress = 0x18080000,
7302 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
7303 +
7304 + PCI0_VirtualAddress = 0xB8080000,
7305 + PCI_VirtualAddress = PCI0_VirtualAddress,
7306 +} ;
7307 +
7308 +enum
7309 +{
7310 + PCI_LbaCount = 4, // Local base addresses.
7311 +} ;
7312 +
7313 +typedef struct
7314 +{
7315 + u32 a ; // Address.
7316 + u32 c ; // Control.
7317 + u32 m ; // mapping.
7318 +} PCI_Map_s ;
7319 +
7320 +typedef struct
7321 +{
7322 + u32 pcic ;
7323 + u32 pcis ;
7324 + u32 pcism ;
7325 + u32 pcicfga ;
7326 + u32 pcicfgd ;
7327 + PCI_Map_s pcilba [PCI_LbaCount] ;
7328 + u32 pcidac ;
7329 + u32 pcidas ;
7330 + u32 pcidasm ;
7331 + u32 pcidad ;
7332 + u32 pcidma8c ;
7333 + u32 pcidma9c ;
7334 + u32 pcitc ;
7335 +} volatile *PCI_t ;
7336 +
7337 +// PCI messaging unit.
7338 +enum
7339 +{
7340 + PCIM_Count = 2,
7341 +} ;
7342 +typedef struct
7343 +{
7344 + u32 pciim [PCIM_Count] ;
7345 + u32 pciom [PCIM_Count] ;
7346 + u32 pciid ;
7347 + u32 pciiic ;
7348 + u32 pciiim ;
7349 + u32 pciiod ;
7350 + u32 pciioic ;
7351 + u32 pciioim ;
7352 +} volatile *PCIM_t ;
7353 +
7354 +/*******************************************************************************
7355 + *
7356 + * PCI Control Register
7357 + *
7358 + ******************************************************************************/
7359 +enum
7360 +{
7361 + PCIC_en_b = 0,
7362 + PCIC_en_m = 0x00000001,
7363 + PCIC_tnr_b = 1,
7364 + PCIC_tnr_m = 0x00000002,
7365 + PCIC_sce_b = 2,
7366 + PCIC_sce_m = 0x00000004,
7367 + PCIC_ien_b = 3,
7368 + PCIC_ien_m = 0x00000008,
7369 + PCIC_aaa_b = 4,
7370 + PCIC_aaa_m = 0x00000010,
7371 + PCIC_eap_b = 5,
7372 + PCIC_eap_m = 0x00000020,
7373 + PCIC_pcim_b = 6,
7374 + PCIC_pcim_m = 0x000001c0,
7375 + PCIC_pcim_disabled_v = 0,
7376 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
7377 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
7378 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
7379 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
7380 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
7381 + PCIC_pcim_reserved6_v = 6,
7382 + PCIC_pcim_reserved7_v = 7,
7383 + PCIC_igm_b = 9,
7384 + PCIC_igm_m = 0x00000200,
7385 +} ;
7386 +
7387 +/*******************************************************************************
7388 + *
7389 + * PCI Status Register
7390 + *
7391 + ******************************************************************************/
7392 +enum {
7393 + PCIS_eed_b = 0,
7394 + PCIS_eed_m = 0x00000001,
7395 + PCIS_wr_b = 1,
7396 + PCIS_wr_m = 0x00000002,
7397 + PCIS_nmi_b = 2,
7398 + PCIS_nmi_m = 0x00000004,
7399 + PCIS_ii_b = 3,
7400 + PCIS_ii_m = 0x00000008,
7401 + PCIS_cwe_b = 4,
7402 + PCIS_cwe_m = 0x00000010,
7403 + PCIS_cre_b = 5,
7404 + PCIS_cre_m = 0x00000020,
7405 + PCIS_mdpe_b = 6,
7406 + PCIS_mdpe_m = 0x00000040,
7407 + PCIS_sta_b = 7,
7408 + PCIS_sta_m = 0x00000080,
7409 + PCIS_rta_b = 8,
7410 + PCIS_rta_m = 0x00000100,
7411 + PCIS_rma_b = 9,
7412 + PCIS_rma_m = 0x00000200,
7413 + PCIS_sse_b = 10,
7414 + PCIS_sse_m = 0x00000400,
7415 + PCIS_ose_b = 11,
7416 + PCIS_ose_m = 0x00000800,
7417 + PCIS_pe_b = 12,
7418 + PCIS_pe_m = 0x00001000,
7419 + PCIS_tae_b = 13,
7420 + PCIS_tae_m = 0x00002000,
7421 + PCIS_rle_b = 14,
7422 + PCIS_rle_m = 0x00004000,
7423 + PCIS_bme_b = 15,
7424 + PCIS_bme_m = 0x00008000,
7425 + PCIS_prd_b = 16,
7426 + PCIS_prd_m = 0x00010000,
7427 + PCIS_rip_b = 17,
7428 + PCIS_rip_m = 0x00020000,
7429 +} ;
7430 +
7431 +/*******************************************************************************
7432 + *
7433 + * PCI Status Mask Register
7434 + *
7435 + ******************************************************************************/
7436 +enum {
7437 + PCISM_eed_b = 0,
7438 + PCISM_eed_m = 0x00000001,
7439 + PCISM_wr_b = 1,
7440 + PCISM_wr_m = 0x00000002,
7441 + PCISM_nmi_b = 2,
7442 + PCISM_nmi_m = 0x00000004,
7443 + PCISM_ii_b = 3,
7444 + PCISM_ii_m = 0x00000008,
7445 + PCISM_cwe_b = 4,
7446 + PCISM_cwe_m = 0x00000010,
7447 + PCISM_cre_b = 5,
7448 + PCISM_cre_m = 0x00000020,
7449 + PCISM_mdpe_b = 6,
7450 + PCISM_mdpe_m = 0x00000040,
7451 + PCISM_sta_b = 7,
7452 + PCISM_sta_m = 0x00000080,
7453 + PCISM_rta_b = 8,
7454 + PCISM_rta_m = 0x00000100,
7455 + PCISM_rma_b = 9,
7456 + PCISM_rma_m = 0x00000200,
7457 + PCISM_sse_b = 10,
7458 + PCISM_sse_m = 0x00000400,
7459 + PCISM_ose_b = 11,
7460 + PCISM_ose_m = 0x00000800,
7461 + PCISM_pe_b = 12,
7462 + PCISM_pe_m = 0x00001000,
7463 + PCISM_tae_b = 13,
7464 + PCISM_tae_m = 0x00002000,
7465 + PCISM_rle_b = 14,
7466 + PCISM_rle_m = 0x00004000,
7467 + PCISM_bme_b = 15,
7468 + PCISM_bme_m = 0x00008000,
7469 + PCISM_prd_b = 16,
7470 + PCISM_prd_m = 0x00010000,
7471 + PCISM_rip_b = 17,
7472 + PCISM_rip_m = 0x00020000,
7473 +} ;
7474 +
7475 +/*******************************************************************************
7476 + *
7477 + * PCI Configuration Address Register
7478 + *
7479 + ******************************************************************************/
7480 +enum {
7481 + PCICFGA_reg_b = 2,
7482 + PCICFGA_reg_m = 0x000000fc,
7483 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
7484 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
7485 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
7486 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
7487 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
7488 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
7489 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
7490 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
7491 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
7492 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
7493 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
7494 + PCICFGA_reg_pba0m_v = 0x48>>2,
7495 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
7496 + PCICFGA_reg_pba1m_v = 0x50>>2,
7497 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
7498 + PCICFGA_reg_pba2m_v = 0x58>>2,
7499 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
7500 + PCICFGA_reg_pba3m_v = 0x60>>2,
7501 + PCICFGA_reg_pmgt_v = 0x64>>2,
7502 + PCICFGA_func_b = 8,
7503 + PCICFGA_func_m = 0x00000700,
7504 + PCICFGA_dev_b = 11,
7505 + PCICFGA_dev_m = 0x0000f800,
7506 + PCICFGA_dev_internal_v = 0,
7507 + PCICFGA_bus_b = 16,
7508 + PCICFGA_bus_m = 0x00ff0000,
7509 + PCICFGA_bus_type0_v = 0, //local bus
7510 + PCICFGA_en_b = 31, // read only
7511 + PCICFGA_en_m = 0x80000000,
7512 +} ;
7513 +
7514 +enum {
7515 + PCFGID_vendor_b = 0,
7516 + PCFGID_vendor_m = 0x0000ffff,
7517 + PCFGID_vendor_IDT_v = 0x111d,
7518 + PCFGID_device_b = 16,
7519 + PCFGID_device_m = 0xffff0000,
7520 + PCFGID_device_Korinade_v = 0x0214,
7521 +
7522 + PCFG04_command_ioena_b = 1,
7523 + PCFG04_command_ioena_m = 0x00000001,
7524 + PCFG04_command_memena_b = 2,
7525 + PCFG04_command_memena_m = 0x00000002,
7526 + PCFG04_command_bmena_b = 3,
7527 + PCFG04_command_bmena_m = 0x00000004,
7528 + PCFG04_command_mwinv_b = 5,
7529 + PCFG04_command_mwinv_m = 0x00000010,
7530 + PCFG04_command_parena_b = 7,
7531 + PCFG04_command_parena_m = 0x00000040,
7532 + PCFG04_command_serrena_b = 9,
7533 + PCFG04_command_serrena_m = 0x00000100,
7534 + PCFG04_command_fastbbena_b = 10,
7535 + PCFG04_command_fastbbena_m = 0x00000200,
7536 + PCFG04_status_b = 16,
7537 + PCFG04_status_m = 0xffff0000,
7538 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
7539 + PCFG04_status_66MHz_m = 0x00200000,
7540 + PCFG04_status_fbb_b = 23,
7541 + PCFG04_status_fbb_m = 0x00800000,
7542 + PCFG04_status_mdpe_b = 24,
7543 + PCFG04_status_mdpe_m = 0x01000000,
7544 + PCFG04_status_dst_b = 25,
7545 + PCFG04_status_dst_m = 0x06000000,
7546 + PCFG04_status_sta_b = 27,
7547 + PCFG04_status_sta_m = 0x08000000,
7548 + PCFG04_status_rta_b = 28,
7549 + PCFG04_status_rta_m = 0x10000000,
7550 + PCFG04_status_rma_b = 29,
7551 + PCFG04_status_rma_m = 0x20000000,
7552 + PCFG04_status_sse_b = 30,
7553 + PCFG04_status_sse_m = 0x40000000,
7554 + PCFG04_status_pe_b = 31,
7555 + PCFG04_status_pe_m = 0x40000000,
7556 +
7557 + PCFG08_revId_b = 0,
7558 + PCFG08_revId_m = 0x000000ff,
7559 + PCFG08_classCode_b = 0,
7560 + PCFG08_classCode_m = 0xffffff00,
7561 + PCFG08_classCode_bridge_v = 06,
7562 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
7563 + PCFG0C_cacheline_b = 0,
7564 + PCFG0C_cacheline_m = 0x000000ff,
7565 + PCFG0C_masterLatency_b = 8,
7566 + PCFG0C_masterLatency_m = 0x0000ff00,
7567 + PCFG0C_headerType_b = 16,
7568 + PCFG0C_headerType_m = 0x00ff0000,
7569 + PCFG0C_bist_b = 24,
7570 + PCFG0C_bist_m = 0xff000000,
7571 +
7572 + PCIPBA_msi_b = 0,
7573 + PCIPBA_msi_m = 0x00000001,
7574 + PCIPBA_p_b = 3,
7575 + PCIPBA_p_m = 0x00000004,
7576 + PCIPBA_baddr_b = 8,
7577 + PCIPBA_baddr_m = 0xffffff00,
7578 +
7579 + PCFGSS_vendorId_b = 0,
7580 + PCFGSS_vendorId_m = 0x0000ffff,
7581 + PCFGSS_id_b = 16,
7582 + PCFGSS_id_m = 0xffff0000,
7583 +
7584 + PCFG3C_interruptLine_b = 0,
7585 + PCFG3C_interruptLine_m = 0x000000ff,
7586 + PCFG3C_interruptPin_b = 8,
7587 + PCFG3C_interruptPin_m = 0x0000ff00,
7588 + PCFG3C_minGrant_b = 16,
7589 + PCFG3C_minGrant_m = 0x00ff0000,
7590 + PCFG3C_maxLat_b = 24,
7591 + PCFG3C_maxLat_m = 0xff000000,
7592 +
7593 + PCIPBAC_msi_b = 0,
7594 + PCIPBAC_msi_m = 0x00000001,
7595 + PCIPBAC_p_b = 1,
7596 + PCIPBAC_p_m = 0x00000002,
7597 + PCIPBAC_size_b = 2,
7598 + PCIPBAC_size_m = 0x0000007c,
7599 + PCIPBAC_sb_b = 7,
7600 + PCIPBAC_sb_m = 0x00000080,
7601 + PCIPBAC_pp_b = 8,
7602 + PCIPBAC_pp_m = 0x00000100,
7603 + PCIPBAC_mr_b = 9,
7604 + PCIPBAC_mr_m = 0x00000600,
7605 + PCIPBAC_mr_read_v =0, //no prefetching
7606 + PCIPBAC_mr_readLine_v =1,
7607 + PCIPBAC_mr_readMult_v =2,
7608 + PCIPBAC_mrl_b = 11,
7609 + PCIPBAC_mrl_m = 0x00000800,
7610 + PCIPBAC_mrm_b = 12,
7611 + PCIPBAC_mrm_m = 0x00001000,
7612 + PCIPBAC_trp_b = 13,
7613 + PCIPBAC_trp_m = 0x00002000,
7614 +
7615 + PCFG40_trdyTimeout_b = 0,
7616 + PCFG40_trdyTimeout_m = 0x000000ff,
7617 + PCFG40_retryLim_b = 8,
7618 + PCFG40_retryLim_m = 0x0000ff00,
7619 +};
7620 +
7621 +/*******************************************************************************
7622 + *
7623 + * PCI Local Base Address [0|1|2|3] Register
7624 + *
7625 + ******************************************************************************/
7626 +enum {
7627 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
7628 + PCILBA_baddr_m = 0xffffff00,
7629 +} ;
7630 +/*******************************************************************************
7631 + *
7632 + * PCI Local Base Address Control Register
7633 + *
7634 + ******************************************************************************/
7635 +enum {
7636 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
7637 + PCILBAC_msi_m = 0x00000001,
7638 + PCILBAC_msi_mem_v = 0,
7639 + PCILBAC_msi_io_v = 1,
7640 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
7641 + PCILBAC_size_m = 0x0000007c,
7642 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
7643 + PCILBAC_sb_m = 0x00000080,
7644 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
7645 + PCILBAC_rt_m = 0x00000100,
7646 + PCILBAC_rt_noprefetch_v = 0, // mem read
7647 + PCILBAC_rt_prefetch_v = 1, // mem readline
7648 +} ;
7649 +
7650 +/*******************************************************************************
7651 + *
7652 + * PCI Local Base Address [0|1|2|3] Mapping Register
7653 + *
7654 + ******************************************************************************/
7655 +enum {
7656 + PCILBAM_maddr_b = 8,
7657 + PCILBAM_maddr_m = 0xffffff00,
7658 +} ;
7659 +
7660 +/*******************************************************************************
7661 + *
7662 + * PCI Decoupled Access Control Register
7663 + *
7664 + ******************************************************************************/
7665 +enum {
7666 + PCIDAC_den_b = 0,
7667 + PCIDAC_den_m = 0x00000001,
7668 +} ;
7669 +
7670 +/*******************************************************************************
7671 + *
7672 + * PCI Decoupled Access Status Register
7673 + *
7674 + ******************************************************************************/
7675 +enum {
7676 + PCIDAS_d_b = 0,
7677 + PCIDAS_d_m = 0x00000001,
7678 + PCIDAS_b_b = 1,
7679 + PCIDAS_b_m = 0x00000002,
7680 + PCIDAS_e_b = 2,
7681 + PCIDAS_e_m = 0x00000004,
7682 + PCIDAS_ofe_b = 3,
7683 + PCIDAS_ofe_m = 0x00000008,
7684 + PCIDAS_off_b = 4,
7685 + PCIDAS_off_m = 0x00000010,
7686 + PCIDAS_ife_b = 5,
7687 + PCIDAS_ife_m = 0x00000020,
7688 + PCIDAS_iff_b = 6,
7689 + PCIDAS_iff_m = 0x00000040,
7690 +} ;
7691 +
7692 +/*******************************************************************************
7693 + *
7694 + * PCI DMA Channel 8 Configuration Register
7695 + *
7696 + ******************************************************************************/
7697 +enum
7698 +{
7699 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
7700 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
7701 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
7702 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
7703 +} ;
7704 +
7705 +/*******************************************************************************
7706 + *
7707 + * PCI DMA Channel 9 Configuration Register
7708 + *
7709 + ******************************************************************************/
7710 +enum
7711 +{
7712 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
7713 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
7714 +} ;
7715 +
7716 +/*******************************************************************************
7717 + *
7718 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
7719 + *
7720 + ******************************************************************************/
7721 +enum {
7722 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
7723 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
7724 + // These are for reads (DMA channel 8)
7725 + PCIDMAD_devcmd_mr_v = 0, //memory read
7726 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
7727 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
7728 + PCIDMAD_devcmd_ior_v = 3, //I/O read
7729 + // These are for writes (DMA channel 9)
7730 + PCIDMAD_devcmd_mw_v = 0, //memory write
7731 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
7732 + PCIDMAD_devcmd_iow_v = 3, //I/O write
7733 +
7734 + // Swap byte field applies to both DMA channel 8 and 9
7735 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
7736 + PCIDMAD_sb_m = 0x01000000, // swap byte field
7737 +} ;
7738 +
7739 +
7740 +/*******************************************************************************
7741 + *
7742 + * PCI Target Control Register
7743 + *
7744 + ******************************************************************************/
7745 +enum
7746 +{
7747 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
7748 + PCITC_rtimer_m = 0x000000ff,
7749 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
7750 + PCITC_dtimer_m = 0x0000ff00,
7751 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
7752 + PCITC_rdr_m = 0x00040000,
7753 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
7754 + PCITC_ddt_m = 0x00080000,
7755 +} ;
7756 +/*******************************************************************************
7757 + *
7758 + * PCI messaging unit [applies to both inbound and outbound registers ]
7759 + *
7760 + ******************************************************************************/
7761 +enum
7762 +{
7763 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7764 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
7765 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7766 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
7767 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7768 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
7769 +};
7770 +
7771 +
7772 +
7773 +
7774 +
7775 +
7776 +#define PCI_MSG_VirtualAddress 0xB8088010
7777 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
7778 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
7779 +
7780 +#define PCIM_SHFT 0x6
7781 +#define PCIM_BIT_LEN 0x7
7782 +#define PCIM_H_EA 0x3
7783 +#define PCIM_H_IA_FIX 0x4
7784 +#define PCIM_H_IA_RR 0x5
7785 +#if 0
7786 +#define PCI_ADDR_START 0x13000000
7787 +#endif
7788 +
7789 +#define PCI_ADDR_START 0x50000000
7790 +
7791 +#define CPUTOPCI_MEM_WIN 0x02000000
7792 +#define CPUTOPCI_IO_WIN 0x00100000
7793 +#define PCILBA_SIZE_SHFT 2
7794 +#define PCILBA_SIZE_MASK 0x1F
7795 +#define SIZE_256MB 0x1C
7796 +#define SIZE_128MB 0x1B
7797 +#define SIZE_64MB 0x1A
7798 +#define SIZE_32MB 0x19
7799 +#define SIZE_16MB 0x18
7800 +#define SIZE_4MB 0x16
7801 +#define SIZE_2MB 0x15
7802 +#define SIZE_1MB 0x14
7803 +#define KORINA_CONFIG0_ADDR 0x80000000
7804 +#define KORINA_CONFIG1_ADDR 0x80000004
7805 +#define KORINA_CONFIG2_ADDR 0x80000008
7806 +#define KORINA_CONFIG3_ADDR 0x8000000C
7807 +#define KORINA_CONFIG4_ADDR 0x80000010
7808 +#define KORINA_CONFIG5_ADDR 0x80000014
7809 +#define KORINA_CONFIG6_ADDR 0x80000018
7810 +#define KORINA_CONFIG7_ADDR 0x8000001C
7811 +#define KORINA_CONFIG8_ADDR 0x80000020
7812 +#define KORINA_CONFIG9_ADDR 0x80000024
7813 +#define KORINA_CONFIG10_ADDR 0x80000028
7814 +#define KORINA_CONFIG11_ADDR 0x8000002C
7815 +#define KORINA_CONFIG12_ADDR 0x80000030
7816 +#define KORINA_CONFIG13_ADDR 0x80000034
7817 +#define KORINA_CONFIG14_ADDR 0x80000038
7818 +#define KORINA_CONFIG15_ADDR 0x8000003C
7819 +#define KORINA_CONFIG16_ADDR 0x80000040
7820 +#define KORINA_CONFIG17_ADDR 0x80000044
7821 +#define KORINA_CONFIG18_ADDR 0x80000048
7822 +#define KORINA_CONFIG19_ADDR 0x8000004C
7823 +#define KORINA_CONFIG20_ADDR 0x80000050
7824 +#define KORINA_CONFIG21_ADDR 0x80000054
7825 +#define KORINA_CONFIG22_ADDR 0x80000058
7826 +#define KORINA_CONFIG23_ADDR 0x8000005C
7827 +#define KORINA_CONFIG24_ADDR 0x80000060
7828 +#define KORINA_CONFIG25_ADDR 0x80000064
7829 +#define KORINA_CMD (PCFG04_command_ioena_m | \
7830 + PCFG04_command_memena_m | \
7831 + PCFG04_command_bmena_m | \
7832 + PCFG04_command_mwinv_m | \
7833 + PCFG04_command_parena_m | \
7834 + PCFG04_command_serrena_m )
7835 +
7836 +#define KORINA_STAT (PCFG04_status_mdpe_m | \
7837 + PCFG04_status_sta_m | \
7838 + PCFG04_status_rta_m | \
7839 + PCFG04_status_rma_m | \
7840 + PCFG04_status_sse_m | \
7841 + PCFG04_status_pe_m)
7842 +
7843 +#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
7844 +
7845 +#define KORINA_REVID 0
7846 +#define KORINA_CLASS_CODE 0
7847 +#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
7848 + KORINA_REVID)
7849 +
7850 +#define KORINA_CACHE_LINE_SIZE 4
7851 +#define KORINA_MASTER_LAT 0x3c
7852 +#define KORINA_HEADER_TYPE 0
7853 +#define KORINA_BIST 0
7854 +
7855 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
7856 + (KORINA_HEADER_TYPE<<16) | \
7857 + (KORINA_MASTER_LAT<<8) | \
7858 + KORINA_CACHE_LINE_SIZE )
7859 +
7860 +#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
7861 +#define KORINA_BAR1 0x18800001 /* 1 MB IO */
7862 +#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
7863 + internal Registers */
7864 +#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
7865 +
7866 +#define KORINA_CNFG4 KORINA_BAR0
7867 +#define KORINA_CNFG5 KORINA_BAR1
7868 +#define KORINA_CNFG6 KORINA_BAR2
7869 +#define KORINA_CNFG7 KORINA_BAR3
7870 +
7871 +#define KORINA_SUBSYS_VENDOR_ID 0x011d
7872 +#define KORINA_SUBSYSTEM_ID 0x0214
7873 +#define KORINA_CNFG8 0
7874 +#define KORINA_CNFG9 0
7875 +#define KORINA_CNFG10 0
7876 +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
7877 + KORINA_SUBSYSTEM_ID)
7878 +#define KORINA_INT_LINE 1
7879 +#define KORINA_INT_PIN 1
7880 +#define KORINA_MIN_GNT 8
7881 +#define KORINA_MAX_LAT 0x38
7882 +#define KORINA_CNFG12 0
7883 +#define KORINA_CNFG13 0
7884 +#define KORINA_CNFG14 0
7885 +#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
7886 + (KORINA_MIN_GNT<<16) | \
7887 + (KORINA_INT_PIN<<8) | \
7888 + KORINA_INT_LINE)
7889 +#define KORINA_RETRY_LIMIT 0x80
7890 +#define KORINA_TRDY_LIMIT 0x80
7891 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
7892 + KORINA_TRDY_LIMIT)
7893 +#define PCI_PBAxC_R 0x0
7894 +#define PCI_PBAxC_RL 0x1
7895 +#define PCI_PBAxC_RM 0x2
7896 +#define SIZE_SHFT 2
7897 +
7898 +#if defined(__MIPSEB__)
7899 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
7900 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
7901 + PCIPBAC_pp_m | \
7902 + (SIZE_128MB<<SIZE_SHFT) | \
7903 + PCIPBAC_p_m)
7904 +#else
7905 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
7906 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
7907 + PCIPBAC_pp_m | \
7908 + (SIZE_128MB<<SIZE_SHFT) | \
7909 + PCIPBAC_p_m)
7910 +#endif
7911 +#define KORINA_CNFG17 KORINA_PBA0C
7912 +#define KORINA_PBA0M 0x0
7913 +#define KORINA_CNFG18 KORINA_PBA0M
7914 +
7915 +#if defined(__MIPSEB__)
7916 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
7917 + PCIPBAC_msi_m)
7918 +#else
7919 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
7920 + PCIPBAC_msi_m)
7921 +#endif
7922 +#define KORINA_CNFG19 KORINA_PBA1C
7923 +#define KORINA_PBA1M 0x0
7924 +#define KORINA_CNFG20 KORINA_PBA1M
7925 +
7926 +#if defined(__MIPSEB__)
7927 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
7928 + PCIPBAC_msi_m)
7929 +#else
7930 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
7931 + PCIPBAC_msi_m)
7932 +#endif
7933 +#define KORINA_CNFG21 KORINA_PBA2C
7934 +#define KORINA_PBA2M 0x18000000
7935 +#define KORINA_CNFG22 KORINA_PBA2M
7936 +#define KORINA_PBA3C 0
7937 +#define KORINA_CNFG23 KORINA_PBA3C
7938 +#define KORINA_PBA3M 0
7939 +#define KORINA_CNFG24 KORINA_PBA3M
7940 +
7941 +
7942 +
7943 +#define PCITC_DTIMER_VAL 8
7944 +#define PCITC_RTIMER_VAL 0x10
7945 +
7946 +
7947 +
7948 +
7949 +#endif // __IDT_PCI_H__
7950 +
7951 +
7952 +
7953 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_rst.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h
7954 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 1970-01-01 01:00:00.000000000 +0100
7955 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 2006-01-10 00:32:33.000000000 +0100
7956 @@ -0,0 +1,119 @@
7957 +/**************************************************************************
7958 + *
7959 + * BRIEF MODULE DESCRIPTION
7960 + * Reset register definitions.
7961 + *
7962 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7963 + *
7964 + * This program is free software; you can redistribute it and/or modify it
7965 + * under the terms of the GNU General Public License as published by the
7966 + * Free Software Foundation; either version 2 of the License, or (at your
7967 + * option) any later version.
7968 + *
7969 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7970 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7971 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7972 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7973 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7974 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7975 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7976 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7977 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7978 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7979 + *
7980 + * You should have received a copy of the GNU General Public License along
7981 + * with this program; if not, write to the Free Software Foundation, Inc.,
7982 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7983 + *
7984 + *
7985 + **************************************************************************
7986 + * May 2004 rkt, neb.
7987 + *
7988 + * Initial Release
7989 + *
7990 + *
7991 + *
7992 + **************************************************************************
7993 + */
7994 +
7995 +#ifndef __IDT_RST_H__
7996 +#define __IDT_RST_H__
7997 +
7998 +enum
7999 +{
8000 + RST0_PhysicalAddress = 0x18000000,
8001 + RST_PhysicalAddress = RST0_PhysicalAddress, // Default
8002 +
8003 + RST0_VirtualAddress = 0xb8000000,
8004 + RST_VirtualAddress = RST0_VirtualAddress, // Default
8005 +} ;
8006 +
8007 +typedef struct RST_s
8008 +{
8009 + u32 filler [0x0006] ;
8010 + u32 sysid ;
8011 + u32 filler2 [0x2000-8] ; // Pad out to offset 0x8000
8012 + u32 reset ;
8013 + u32 bcv ;
8014 + u32 cea ;
8015 +} volatile * RST_t ;
8016 +
8017 +enum
8018 +{
8019 + SYSID_rev_b = 0,
8020 + SYSID_rev_m = 0x000000ff,
8021 + SYSID_imp_b = 8,
8022 + SYSID_imp_m = 0x000fff00,
8023 + SYSID_vendor_b = 8,
8024 + SYSID_vendor_m = 0xfff00000,
8025 +
8026 + BCV_pll_b = 0,
8027 + BCV_pll_m = 0x0000000f,
8028 + BCV_pll_PLLBypass_v = 0x0, // PCLK=1*CLK.
8029 + BCV_pll_Mul3_v = 0x1, // PCLK=3*CLK.
8030 + BCV_pll_Mul4_v = 0x2, // PCLK=4*CLK.
8031 + BCV_pll_SlowMul5_v = 0x3, // PCLK=5*CLK.
8032 + BCV_pll_Mul5_v = 0x4, // PCLK=5*CLK.
8033 + BCV_pll_SlowMul6_v = 0x5, // PCLK=6*CLK.
8034 + BCV_pll_Mul6_v = 0x6, // PCLK=6*CLK.
8035 + BCV_pll_Mul8_v = 0x7, // PCLK=8*CLK.
8036 + BCV_pll_Mul10_v = 0x8, // PCLK=10*CLK.
8037 + BCV_pll_Res9_v = 0x9,
8038 + BCV_pll_Res10_v = 0xa,
8039 + BCV_pll_Res11_v = 0xb,
8040 + BCV_pll_Res12_v = 0xc,
8041 + BCV_pll_Res13_v = 0xd,
8042 + BCV_pll_Res14_v = 0xe,
8043 + BCV_pll_Res15_v = 0xf,
8044 + BCV_clkDiv_b = 4,
8045 + BCV_clkDiv_m = 0x00000030,
8046 + BCV_clkDiv_Div1_v = 0x0,
8047 + BCV_clkDiv_Div2_v = 0x1,
8048 + BCV_clkDiv_Div4_v = 0x2,
8049 + BCV_clkDiv_Res3_v = 0x3,
8050 + BCV_bigEndian_b = 6,
8051 + BCV_bigEndian_m = 0x00000040,
8052 + BCV_resetFast_b = 7,
8053 + BCV_resetFast_m = 0x00000080,
8054 + BCV_pciMode_b = 8,
8055 + BCV_pciMode_m = 0x00000700,
8056 + BCV_pciMode_disabled_v = 0, // PCI is disabled.
8057 + BCV_pciMode_tnr_v = 1, // satellite Target Not Ready.
8058 + BCV_pciMode_suspended_v = 2, // satellite with suspended CPU.
8059 + BCV_pciMode_external_v = 3, // host, external arbiter.
8060 + BCV_pciMode_fixed_v = 4, // host, fixed priority arbiter.
8061 + BCV_pciMode_roundRobin_v= 5, // host, round robin arbiter.
8062 + BCV_pciMode_res6_v = 6,
8063 + BCV_pciMode_res7_v = 7,
8064 + BCV_watchDisable_b = 11,
8065 + BCV_watchDisable_m = 0x00000800,
8066 + BCV_res12_b = 12,
8067 + BCV_res12_m = 0x00001000,
8068 + BCV_res13_b = 13,
8069 + BCV_res13_m = 0x00002000,
8070 + BCV_res14_b = 14,
8071 + BCV_res14_m = 0x00004000,
8072 + BCV_res15_b = 15,
8073 + BCV_res15_m = 0x00008000,
8074 +} ;
8075 +#endif // __IDT_RST_H__
8076 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_spi.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h
8077 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 1970-01-01 01:00:00.000000000 +0100
8078 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 2006-01-10 00:32:33.000000000 +0100
8079 @@ -0,0 +1,120 @@
8080 +/**************************************************************************
8081 + *
8082 + * BRIEF MODULE DESCRIPTION
8083 + * Serial Peripheral Interface register definitions.
8084 + *
8085 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8086 + *
8087 + * This program is free software; you can redistribute it and/or modify it
8088 + * under the terms of the GNU General Public License as published by the
8089 + * Free Software Foundation; either version 2 of the License, or (at your
8090 + * option) any later version.
8091 + *
8092 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8093 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8094 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8095 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8096 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8097 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8098 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8099 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8100 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8101 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8102 + *
8103 + * You should have received a copy of the GNU General Public License along
8104 + * with this program; if not, write to the Free Software Foundation, Inc.,
8105 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8106 + *
8107 + *
8108 + **************************************************************************
8109 + * May 2004 rkt, neb.
8110 + *
8111 + * Initial Release
8112 + *
8113 + *
8114 + *
8115 + **************************************************************************
8116 + */
8117 +
8118 +#ifndef __IDT_SPI_H__
8119 +#define __IDT_SPI_H__
8120 +
8121 +enum
8122 +{
8123 + SPI0_PhysicalAddress = 0x18070000,
8124 + SPI_PhysicalAddress = SPI0_PhysicalAddress,
8125 +
8126 + SPI0_VirtualAddress = 0xB8070000,
8127 + SPI_VirtualAddress = SPI0_VirtualAddress,
8128 +} ;
8129 +
8130 +typedef struct
8131 +{
8132 + u32 spcp ; // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
8133 + u32 spc ; // spi control reg use SPC_
8134 + u32 sps ; // spi status reg use SPS_
8135 + u32 spd ; // spi data reg use SPD_
8136 + u32 siofunc ; // serial IO function use SIOFUNC_
8137 + u32 siocfg ; // serial IO config use SIOCFG_
8138 + u32 siod; // serial IO data use SIOD_
8139 +} volatile *SPI_t ;
8140 +
8141 +enum
8142 +{
8143 + SPCP_div_b = 0,
8144 + SPCP_div_m = 0x000000ff,
8145 + SPC_spr_b = 0,
8146 + SPC_spr_m = 0x00000003,
8147 + SPC_spr_div2_v = 0,
8148 + SPC_spr_div4_v = 1,
8149 + SPC_spr_div16_v = 2,
8150 + SPC_spr_div32_v = 3,
8151 + SPC_cpha_b = 2,
8152 + SPC_cpha_m = 0x00000004,
8153 + SPC_cpol_b = 3,
8154 + SPC_cpol_m = 0x00000008,
8155 + SPC_mstr_b = 4,
8156 + SPC_mstr_m = 0x00000010,
8157 + SPC_spe_b = 6,
8158 + SPC_spe_m = 0x00000040,
8159 + SPC_spie_b = 7,
8160 + SPC_spie_m = 0x00000080,
8161 +
8162 + SPS_modf_b = 4,
8163 + SPS_modf_m = 0x00000010,
8164 + SPS_wcol_b = 6,
8165 + SPS_wcol_m = 0x00000040,
8166 + SPS_spif_b = 7,
8167 + SPS_spif_m = 0x00000070,
8168 +
8169 + SPD_data_b = 0,
8170 + SPD_data_m = 0x000000ff,
8171 +
8172 + SIOFUNC_sdo_b = 0,
8173 + SIOFUNC_sdo_m = 0x00000001,
8174 + SIOFUNC_sdi_b = 1,
8175 + SIOFUNC_sdi_m = 0x00000002,
8176 + SIOFUNC_sck_b = 2,
8177 + SIOFUNC_sck_m = 0x00000004,
8178 + SIOFUNC_pci_b = 3,
8179 + SIOFUNC_pci_m = 0x00000008,
8180 +
8181 + SIOCFG_sdo_b = 0,
8182 + SIOCFG_sdo_m = 0x00000001,
8183 + SIOCFG_sdi_b = 1,
8184 + SIOCFG_sdi_m = 0x00000002,
8185 + SIOCFG_sck_b = 2,
8186 + SIOCFG_sck_m = 0x00000004,
8187 + SIOCFG_pci_b = 3,
8188 + SIOCFG_pci_m = 0x00000008,
8189 +
8190 + SIOD_sdo_b = 0,
8191 + SIOD_sdo_m = 0x00000001,
8192 + SIOD_sdi_b = 1,
8193 + SIOD_sdi_m = 0x00000002,
8194 + SIOD_sck_b = 2,
8195 + SIOD_sck_m = 0x00000004,
8196 + SIOD_pci_b = 3,
8197 + SIOD_pci_m = 0x00000008,
8198 +} ;
8199 +#endif // __IDT_SPI_H__
8200 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_timer.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h
8201 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_timer.h 1970-01-01 01:00:00.000000000 +0100
8202 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h 2006-01-10 00:32:33.000000000 +0100
8203 @@ -0,0 +1,91 @@
8204 +/**************************************************************************
8205 + *
8206 + * BRIEF MODULE DESCRIPTION
8207 + * Definitions for timer registers
8208 + *
8209 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8210 + *
8211 + * This program is free software; you can redistribute it and/or modify it
8212 + * under the terms of the GNU General Public License as published by the
8213 + * Free Software Foundation; either version 2 of the License, or (at your
8214 + * option) any later version.
8215 + *
8216 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8217 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8218 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8219 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8220 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8221 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8222 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8223 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8224 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8225 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8226 + *
8227 + * You should have received a copy of the GNU General Public License along
8228 + * with this program; if not, write to the Free Software Foundation, Inc.,
8229 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8230 + *
8231 + *
8232 + **************************************************************************
8233 + * May 2004 rkt,neb.
8234 + *
8235 + * Initial Release
8236 + *
8237 + *
8238 + *
8239 + **************************************************************************
8240 + */
8241 +
8242 +#ifndef __IDT_TIM_H__
8243 +#define __IDT_TIM_H__
8244 +
8245 +enum
8246 +{
8247 + TIM0_PhysicalAddress = 0x18028000,
8248 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
8249 +
8250 + TIM0_VirtualAddress = 0xb8028000,
8251 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
8252 +} ;
8253 +
8254 +enum
8255 +{
8256 + TIM_Count = 3,
8257 +} ;
8258 +
8259 +struct TIM_CNTR_s
8260 +{
8261 + u32 count ;
8262 + u32 compare ;
8263 + u32 ctc ; //use CTC_
8264 +} ;
8265 +
8266 +typedef struct TIM_s
8267 +{
8268 + struct TIM_CNTR_s tim [TIM_Count] ;
8269 + u32 rcount ; //use RCOUNT_
8270 + u32 rcompare ; //use RCOMPARE_
8271 + u32 rtc ; //use RTC_
8272 +} volatile * TIM_t ;
8273 +
8274 +enum
8275 +{
8276 + CTC_en_b = 0,
8277 + CTC_en_m = 0x00000001,
8278 + CTC_to_b = 1,
8279 + CTC_to_m = 0x00000002,
8280 +
8281 + RCOUNT_count_b = 0,
8282 + RCOUNT_count_m = 0x0000ffff,
8283 + RCOMPARE_compare_b = 0,
8284 + RCOMPARE_compare_m = 0x0000ffff,
8285 + RTC_ce_b = 0,
8286 + RTC_ce_m = 0x00000001,
8287 + RTC_to_b = 1,
8288 + RTC_to_m = 0x00000002,
8289 + RTC_rqe_b = 2,
8290 + RTC_rqe_m = 0x00000004,
8291 +
8292 +} ;
8293 +#endif // __IDT_TIM_H__
8294 +
8295 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_uart.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h
8296 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_uart.h 1970-01-01 01:00:00.000000000 +0100
8297 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h 2006-01-10 00:32:33.000000000 +0100
8298 @@ -0,0 +1,189 @@
8299 +/**************************************************************************
8300 + *
8301 + * BRIEF MODULE DESCRIPTION
8302 + * UART register definitions
8303 + *
8304 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8305 + *
8306 + * This program is free software; you can redistribute it and/or modify it
8307 + * under the terms of the GNU General Public License as published by the
8308 + * Free Software Foundation; either version 2 of the License, or (at your
8309 + * option) any later version.
8310 + *
8311 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8312 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8313 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8314 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8315 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8316 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8317 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8318 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8319 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8320 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8321 + *
8322 + * You should have received a copy of the GNU General Public License along
8323 + * with this program; if not, write to the Free Software Foundation, Inc.,
8324 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8325 + *
8326 + *
8327 + **************************************************************************
8328 + * May 2004 rkt, neb.
8329 + *
8330 + * Initial Release
8331 + *
8332 + *
8333 + *
8334 + **************************************************************************
8335 + */
8336 +
8337 +#ifndef __IDT_UART_H__
8338 +#define __IDT_UART_H__
8339 +
8340 +enum
8341 +{
8342 + UART0_PhysicalAddress = 0x1c000000,
8343 + UART_PhysicalAddress = UART0_PhysicalAddress, // Default
8344 +
8345 + UART0_VirtualAddress = 0xbc000000,
8346 + UART_VirtualAddress = UART0_VirtualAddress, // Default
8347 +} ;
8348 +
8349 +/*
8350 + * Register definitions are in bytes so we can handle endian problems.
8351 + */
8352 +
8353 +typedef struct UART_s
8354 +{
8355 + union
8356 + {
8357 + u32 const uartrb ; // 0x00 - DLAB=0, read.
8358 + u32 uartth ; // 0x00 - DLAB=0, write.
8359 + u32 uartdll ; // 0x00 - DLAB=1, read/write.
8360 + } ;
8361 +
8362 + union
8363 + {
8364 + u32 uartie ; // 0x04 - DLAB=0, read/write.
8365 + u32 uartdlh ; // 0x04 - DLAB=1, read/write.
8366 + } ;
8367 + union
8368 + {
8369 + u32 const uartii ; // 0x08 - DLAB=0, read.
8370 + u32 uartfc ; // 0x08 - DLAB=0, write.
8371 + } ;
8372 +
8373 + u32 uartlc ; // 0x0c
8374 + u32 uartmc ; // 0x10
8375 + u32 uartls ; // 0x14
8376 + u32 uartms ; // 0x18
8377 + u32 uarts ; // 0x1c
8378 +} volatile *UART_t ;
8379 +
8380 +// Reset registers.
8381 +typedef u32 volatile *UARTRR_t ;
8382 +
8383 +enum
8384 +{
8385 + UARTIE_rda_b = 0,
8386 + UARTIE_rda_m = 0x00000001,
8387 + UARTIE_the_b = 1,
8388 + UARTIE_the_m = 0x00000002,
8389 + UARTIE_rls_b = 2,
8390 + UARTIE_rls_m = 0x00000004,
8391 + UARTIE_ems_b = 3,
8392 + UARTIE_ems_m = 0x00000008,
8393 +
8394 + UARTII_pi_b = 0,
8395 + UARTII_pi_m = 0x00000001,
8396 + UARTII_iid_b = 1,
8397 + UARTII_iid_m = 0x0000000e,
8398 + UARTII_iid_ms_v = 0, // Modem stat-CTS,DSR,RI or DCD.
8399 + UARTII_iid_thre_v = 1, // Trans. Holding Reg. empty.
8400 + UARTII_iid_rda_v = 2, // Receive data available
8401 + UARTII_iid_rls_v = 3, // Overrun, parity, etc, error.
8402 + UARTII_iid_res4_v = 4, // reserved.
8403 + UARTII_iid_res5_v = 5, // reserved.
8404 + UARTII_iid_cto_v = 6, // Character timeout.
8405 + UARTII_iid_res7_v = 7, // reserved.
8406 +
8407 + UARTFC_en_b = 0,
8408 + UARTFC_en_m = 0x00000001,
8409 + UARTFC_rr_b = 1,
8410 + UARTFC_rr_m = 0x00000002,
8411 + UARTFC_tr_b = 2,
8412 + UARTFC_tr_m = 0x00000004,
8413 + UARTFC_dms_b = 3,
8414 + UARTFC_dms_m = 0x00000008,
8415 + UARTFC_rt_b = 6,
8416 + UARTFC_rt_m = 0x000000c0,
8417 + UARTFC_rt_1Byte_v = 0,
8418 + UARTFC_rt_4Byte_v = 1,
8419 + UARTFC_rt_8Byte_v = 2,
8420 + UARTFC_rt_14Byte_v = 3,
8421 +
8422 + UARTLC_wls_b = 0,
8423 + UARTLC_wls_m = 0x00000003,
8424 + UARTLC_wls_5Bits_v = 0,
8425 + UARTLC_wls_6Bits_v = 1,
8426 + UARTLC_wls_7Bits_v = 2,
8427 + UARTLC_wls_8Bits_v = 3,
8428 + UARTLC_stb_b = 2,
8429 + UARTLC_stb_m = 0x00000004,
8430 + UARTLC_pen_b = 3,
8431 + UARTLC_pen_m = 0x00000008,
8432 + UARTLC_eps_b = 4,
8433 + UARTLC_eps_m = 0x00000010,
8434 + UARTLC_sp_b = 5,
8435 + UARTLC_sp_m = 0x00000020,
8436 + UARTLC_sb_b = 6,
8437 + UARTLC_sb_m = 0x00000040,
8438 + UARTLC_dlab_b = 7,
8439 + UARTLC_dlab_m = 0x00000080,
8440 +
8441 + UARTMC_dtr_b = 0,
8442 + UARTMC_dtr_m = 0x00000001,
8443 + UARTMC_rts_b = 1,
8444 + UARTMC_rts_m = 0x00000002,
8445 + UARTMC_o1_b = 2,
8446 + UARTMC_o1_m = 0x00000004,
8447 + UARTMC_o2_b = 3,
8448 + UARTMC_o2_m = 0x00000008,
8449 + UARTMC_lp_b = 4,
8450 + UARTMC_lp_m = 0x00000010,
8451 +
8452 + UARTLS_dr_b = 0,
8453 + UARTLS_dr_m = 0x00000001,
8454 + UARTLS_oe_b = 1,
8455 + UARTLS_oe_m = 0x00000002,
8456 + UARTLS_pe_b = 2,
8457 + UARTLS_pe_m = 0x00000004,
8458 + UARTLS_fe_b = 3,
8459 + UARTLS_fe_m = 0x00000008,
8460 + UARTLS_bi_b = 4,
8461 + UARTLS_bi_m = 0x00000010,
8462 + UARTLS_thr_b = 5,
8463 + UARTLS_thr_m = 0x00000020,
8464 + UARTLS_te_b = 6,
8465 + UARTLS_te_m = 0x00000040,
8466 + UARTLS_rfe_b = 7,
8467 + UARTLS_rfe_m = 0x00000080,
8468 +
8469 + UARTMS_dcts_b = 0,
8470 + UARTMS_dcts_m = 0x00000001,
8471 + UARTMS_ddsr_b = 1,
8472 + UARTMS_ddsr_m = 0x00000002,
8473 + UARTMS_teri_b = 2,
8474 + UARTMS_teri_m = 0x00000004,
8475 + UARTMS_ddcd_b = 3,
8476 + UARTMS_ddcd_m = 0x00000008,
8477 + UARTMS_cts_b = 4,
8478 + UARTMS_cts_m = 0x00000010,
8479 + UARTMS_dsr_b = 5,
8480 + UARTMS_dsr_m = 0x00000020,
8481 + UARTMS_ri_b = 6,
8482 + UARTMS_ri_m = 0x00000040,
8483 + UARTMS_dcd_b = 7,
8484 + UARTMS_dcd_m = 0x00000080,
8485 +} ;
8486 +
8487 +#endif // __IDT_UART_H__
8488 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_dma.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h
8489 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 1970-01-01 01:00:00.000000000 +0100
8490 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 2006-01-10 00:32:33.000000000 +0100
8491 @@ -0,0 +1,231 @@
8492 +/**************************************************************************
8493 + *
8494 + * BRIEF MODULE DESCRIPTION
8495 + * Register definitions for IDT RC32438 DMA.
8496 + *
8497 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8498 + *
8499 + * This program is free software; you can redistribute it and/or modify it
8500 + * under the terms of the GNU General Public License as published by the
8501 + * Free Software Foundation; either version 2 of the License, or (at your
8502 + * option) any later version.
8503 + *
8504 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8505 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8506 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8507 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8508 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8509 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8510 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8511 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8512 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8513 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8514 + *
8515 + * You should have received a copy of the GNU General Public License along
8516 + * with this program; if not, write to the Free Software Foundation, Inc.,
8517 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8518 + *
8519 + *
8520 + **************************************************************************
8521 + * May 2004 P. Sadik.
8522 + *
8523 + * Initial Release
8524 + *
8525 + *
8526 + *
8527 + **************************************************************************
8528 + */
8529 +#ifndef __IDT_RC32438_DMA_H__
8530 +#define __IDT_RC32438_DMA_H__
8531 +enum
8532 +{
8533 + DMA0_PhysicalAddress = 0x18040000,
8534 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
8535 +
8536 + DMA0_VirtualAddress = 0xb8040000,
8537 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
8538 +} ;
8539 +
8540 +/*
8541 + * DMA descriptor (in physical memory).
8542 + */
8543 +
8544 +typedef struct DMAD_s
8545 +{
8546 + u32 control ; // Control. use DMAD_*
8547 + u32 ca ; // Current Address.
8548 + u32 devcs ; // Device control and status.
8549 + u32 link ; // Next descriptor in chain.
8550 +} volatile *DMAD_t ;
8551 +
8552 +enum
8553 +{
8554 + DMAD_size = sizeof (struct DMAD_s),
8555 + DMAD_count_b = 0, // in DMAD_t -> control
8556 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
8557 + DMAD_ds_b = 20, // in DMAD_t -> control
8558 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
8559 + DMAD_ds_extToMem0_v = 0,
8560 + DMAD_ds_memToExt0_v = 1,
8561 + DMAD_ds_extToMem1_v = 0,
8562 + DMAD_ds_memToExt1_v = 1,
8563 + DMAD_ds_ethRcv0_v = 0,
8564 + DMAD_ds_ethXmt0_v = 0,
8565 + DMAD_ds_ethRcv1_v = 0,
8566 + DMAD_ds_ethXmt2_v = 0,
8567 + DMAD_ds_memToFifo_v = 0,
8568 + DMAD_ds_fifoToMem_v = 0,
8569 + DMAD_ds_rng_de_v = 1,//randomNumberGenerator on LC/DE
8570 + DMAD_ds_pciToMem_v = 0,
8571 + DMAD_ds_memToPci_v = 0,
8572 + DMAD_ds_securityInput_v = 0,
8573 + DMAD_ds_securityOutput_v = 0,
8574 + DMAD_ds_rng_se_v = 0,//randomNumberGenerator on SE
8575 +
8576 + DMAD_devcmd_b = 22, // in DMAD_t -> control
8577 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
8578 + DMAD_devcmd_byte_v = 0, //memory-to-memory
8579 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
8580 + DMAD_devcmd_word_v = 2, //memory-to-memory
8581 + DMAD_devcmd_2words_v = 3, //memory-to-memory
8582 + DMAD_devcmd_4words_v = 4, //memory-to-memory
8583 + DMAD_devcmd_6words_v = 5, //memory-to-memory
8584 + DMAD_devcmd_8words_v = 6, //memory-to-memory
8585 + DMAD_devcmd_16words_v = 7, //memory-to-memory
8586 + DMAD_cof_b = 25, // chain on finished
8587 + DMAD_cof_m = 0x02000000, //
8588 + DMAD_cod_b = 26, // chain on done
8589 + DMAD_cod_m = 0x04000000, //
8590 + DMAD_iof_b = 27, // interrupt on finished
8591 + DMAD_iof_m = 0x08000000, //
8592 + DMAD_iod_b = 28, // interrupt on done
8593 + DMAD_iod_m = 0x10000000, //
8594 + DMAD_t_b = 29, // terminated
8595 + DMAD_t_m = 0x20000000, //
8596 + DMAD_d_b = 30, // done
8597 + DMAD_d_m = 0x40000000, //
8598 + DMAD_f_b = 31, // finished
8599 + DMAD_f_m = 0x80000000, //
8600 +} ;
8601 +
8602 +/*
8603 + * DMA register (within Internal Register Map).
8604 + */
8605 +
8606 +struct DMA_Chan_s
8607 +{
8608 + u32 dmac ; // Control.
8609 + u32 dmas ; // Status.
8610 + u32 dmasm ; // Mask.
8611 + u32 dmadptr ; // Descriptor pointer.
8612 + u32 dmandptr ; // Next descriptor pointer.
8613 +};
8614 +
8615 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
8616 +
8617 +//DMA_Channels use DMACH_count instead
8618 +
8619 +enum
8620 +{
8621 + DMAC_run_b = 0, //
8622 + DMAC_run_m = 0x00000001, //
8623 + DMAC_dm_b = 1, // done mask
8624 + DMAC_dm_m = 0x00000002, //
8625 + DMAC_mode_b = 2, //
8626 + DMAC_mode_m = 0x0000000c, //
8627 + DMAC_mode_auto_v = 0,
8628 + DMAC_mode_burst_v = 1,
8629 + DMAC_mode_transfer_v = 2, //usually used
8630 + DMAC_mode_reserved_v = 3,
8631 + DMAC_a_b = 4, //
8632 + DMAC_a_m = 0x00000010, //
8633 +
8634 + DMAS_f_b = 0, // finished (sticky)
8635 + DMAS_f_m = 0x00000001, //
8636 + DMAS_d_b = 1, // done (sticky)
8637 + DMAS_d_m = 0x00000002, //
8638 + DMAS_c_b = 2, // chain (sticky)
8639 + DMAS_c_m = 0x00000004, //
8640 + DMAS_e_b = 3, // error (sticky)
8641 + DMAS_e_m = 0x00000008, //
8642 + DMAS_h_b = 4, // halt (sticky)
8643 + DMAS_h_m = 0x00000010, //
8644 +
8645 + DMASM_f_b = 0, // finished (1=mask)
8646 + DMASM_f_m = 0x00000001, //
8647 + DMASM_d_b = 1, // done (1=mask)
8648 + DMASM_d_m = 0x00000002, //
8649 + DMASM_c_b = 2, // chain (1=mask)
8650 + DMASM_c_m = 0x00000004, //
8651 + DMASM_e_b = 3, // error (1=mask)
8652 + DMASM_e_m = 0x00000008, //
8653 + DMASM_h_b = 4, // halt (1=mask)
8654 + DMASM_h_m = 0x00000010, //
8655 +} ;
8656 +
8657 +/*
8658 + * DMA channel definitions
8659 + */
8660 +
8661 +enum
8662 +{
8663 + DMACH_extToMem0 = 0,
8664 + DMACH_memToExt0 = 0,
8665 + DMACH_extToMem1 = 1,
8666 + DMACH_memToExt1 = 1,
8667 + DMACH_ethRcv0 = 2,
8668 + DMACH_ethXmt0 = 3,
8669 + DMACH_ethRcv1 = 4,
8670 + DMACH_ethXmt2 = 5,
8671 + DMACH_memToFifo = 6,
8672 + DMACH_fifoToMem = 7,
8673 + DMACH_rng_de = 7,//randomNumberGenerator on LC/DE
8674 + DMACH_pciToMem = 8,
8675 + DMACH_memToPci = 9,
8676 + DMACH_securityInput = 10,
8677 + DMACH_securityOutput = 11,
8678 + DMACH_rng_se = 12, //randomNumberGenerator on SE
8679 +
8680 + DMACH_count //must be last
8681 +};
8682 +
8683 +
8684 +typedef struct DMAC_s
8685 +{
8686 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
8687 +} volatile *DMA_t ;
8688 +
8689 +
8690 +/*
8691 + * External DMA parameters
8692 +*/
8693 +
8694 +enum
8695 +{
8696 + DMADEVCMD_ts_b = 0, // ts field in devcmd
8697 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
8698 + DMADEVCMD_ts_byte_v = 0,
8699 + DMADEVCMD_ts_halfword_v = 1,
8700 + DMADEVCMD_ts_word_v = 2,
8701 + DMADEVCMD_ts_2word_v = 3,
8702 + DMADEVCMD_ts_4word_v = 4,
8703 + DMADEVCMD_ts_6word_v = 5,
8704 + DMADEVCMD_ts_8word_v = 6,
8705 + DMADEVCMD_ts_16word_v = 7
8706 +};
8707 +
8708 +
8709 +#if 1 // aws - Compatibility.
8710 +# define EXTDMA_ts_b DMADEVCMD_ts_b
8711 +# define EXTDMA_ts_m DMADEVCMD_ts_m
8712 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
8713 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
8714 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
8715 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
8716 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
8717 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
8718 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
8719 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
8720 +#endif // aws - Compatibility.
8721 +
8722 +#endif //__IDT_RC32438_DMA_H__
8723 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h
8724 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h 1970-01-01 01:00:00.000000000 +0100
8725 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h 2006-01-10 00:32:33.000000000 +0100
8726 @@ -0,0 +1,82 @@
8727 +/**************************************************************************
8728 + *
8729 + * BRIEF MODULE DESCRIPTION
8730 + * DMA operations for IDT RC32438.
8731 + *
8732 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8733 + *
8734 + * This program is free software; you can redistribute it and/or modify it
8735 + * under the terms of the GNU General Public License as published by the
8736 + * Free Software Foundation; either version 2 of the License, or (at your
8737 + * option) any later version.
8738 + *
8739 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8740 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8741 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8742 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8743 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8744 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8745 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8746 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8747 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8748 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8749 + *
8750 + * You should have received a copy of the GNU General Public License along
8751 + * with this program; if not, write to the Free Software Foundation, Inc.,
8752 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8753 + *
8754 + *
8755 + **************************************************************************
8756 + * May 2004 P. Sadik.
8757 + *
8758 + * Initial Release
8759 + *
8760 + *
8761 + *
8762 + **************************************************************************
8763 + */
8764 +
8765 +#ifndef __IDT_RC32438_DMA_V_H__
8766 +#define __IDT_RC32438_DMA_V_H__
8767 +#include <asm/idt-boards/rc32438/rc32438_dma.h>
8768 +
8769 +#define DMA_CHAN_OFFSET 0x14
8770 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
8771 +#define DMA_COUNT(count) \
8772 + ((count) & DMAD_count_m)
8773 +
8774 +#define DMA_HALT_TIMEOUT 500
8775 +
8776 +
8777 +static inline int rc32438_halt_dma(DMA_Chan_t ch)
8778 +{
8779 + int timeout=1;
8780 + if (rc32438_readl(&ch->dmac) & DMAC_run_m) {
8781 + rc32438_writel(0, &ch->dmac);
8782 +
8783 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
8784 + if (rc32438_readl(&ch->dmas) & DMAS_h_m) {
8785 + rc32438_writel(0, &ch->dmas);
8786 + break;
8787 + }
8788 + }
8789 +
8790 + }
8791 +
8792 + return timeout ? 0 : 1;
8793 +}
8794 +
8795 +
8796 +
8797 +
8798 +static inline void rc32438_start_dma(DMA_Chan_t ch, u32 dma_addr)
8799 +{
8800 + rc32438_writel(0, &ch->dmandptr);
8801 + rc32438_writel(dma_addr, &ch->dmadptr);
8802 +}
8803 +
8804 +static inline void rc32438_chain_dma(DMA_Chan_t ch, u32 dma_addr)
8805 +{
8806 + rc32438_writel(dma_addr, &ch->dmandptr);
8807 +}
8808 +#endif //__IDT_RC32438_DMA_V_H__
8809 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_eth.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h
8810 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 1970-01-01 01:00:00.000000000 +0100
8811 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 2006-01-10 00:32:33.000000000 +0100
8812 @@ -0,0 +1,328 @@
8813 +/**************************************************************************
8814 + *
8815 + * BRIEF MODULE DESCRIPTION
8816 + * Definitions for IDT EB438 ethernet
8817 + *
8818 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8819 + *
8820 + * This program is free software; you can redistribute it and/or modify it
8821 + * under the terms of the GNU General Public License as published by the
8822 + * Free Software Foundation; either version 2 of the License, or (at your
8823 + * option) any later version.
8824 + *
8825 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8826 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8827 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8828 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8829 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8830 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8831 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8832 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8833 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8834 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8835 + *
8836 + * You should have received a copy of the GNU General Public License along
8837 + * with this program; if not, write to the Free Software Foundation, Inc.,
8838 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8839 + *
8840 + *
8841 + **************************************************************************
8842 + * May 2004 P. Sadik.
8843 + *
8844 + * Initial Release
8845 + *
8846 + *
8847 + *
8848 + **************************************************************************
8849 + */
8850 +
8851 +#ifndef __IDT_RC32438_ETH_H__
8852 +#define __IDT_RC32438_ETH_H__
8853 +enum
8854 +{
8855 + ETH0_PhysicalAddress = 0x18058000,
8856 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
8857 +
8858 + ETH0_VirtualAddress = 0xb8058000,
8859 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
8860 + ETH1_PhysicalAddress = 0x18060000,
8861 + ETH1_VirtualAddress = 0xb8060000, // Default
8862 +} ;
8863 +
8864 +typedef struct
8865 +{
8866 + u32 ethintfc ;
8867 + u32 ethfifott ;
8868 + u32 etharc ;
8869 + u32 ethhash0 ;
8870 + u32 ethhash1 ;
8871 + u32 ethu0 [4] ; // Reserved.
8872 + u32 ethpfs ;
8873 + u32 ethmcp ;
8874 + u32 eth_u1 [10] ; // Reserved.
8875 + u32 ethspare ;
8876 + u32 eth_u2 [42] ; // Reserved.
8877 + u32 ethsal0 ;
8878 + u32 ethsah0 ;
8879 + u32 ethsal1 ;
8880 + u32 ethsah1 ;
8881 + u32 ethsal2 ;
8882 + u32 ethsah2 ;
8883 + u32 ethsal3 ;
8884 + u32 ethsah3 ;
8885 + u32 ethrbc ;
8886 + u32 ethrpc ;
8887 + u32 ethrupc ;
8888 + u32 ethrfc ;
8889 + u32 ethtbc ;
8890 + u32 ethgpf ;
8891 + u32 eth_u9 [50] ; // Reserved.
8892 + u32 ethmac1 ;
8893 + u32 ethmac2 ;
8894 + u32 ethipgt ;
8895 + u32 ethipgr ;
8896 + u32 ethclrt ;
8897 + u32 ethmaxf ;
8898 + u32 eth_u10 ; // Reserved.
8899 + u32 ethmtest ;
8900 + u32 miimcfg ;
8901 + u32 miimcmd ;
8902 + u32 miimaddr ;
8903 + u32 miimwtd ;
8904 + u32 miimrdd ;
8905 + u32 miimind ;
8906 + u32 eth_u11 ; // Reserved.
8907 + u32 eth_u12 ; // Reserved.
8908 + u32 ethcfsa0 ;
8909 + u32 ethcfsa1 ;
8910 + u32 ethcfsa2 ;
8911 +} volatile *ETH_t;
8912 +
8913 +enum
8914 +{
8915 + ETHINTFC_en_b = 0,
8916 + ETHINTFC_en_m = 0x00000001,
8917 + ETHINTFC_its_b = 1,
8918 + ETHINTFC_its_m = 0x00000002,
8919 + ETHINTFC_rip_b = 2,
8920 + ETHINTFC_rip_m = 0x00000004,
8921 + ETHINTFC_jam_b = 3,
8922 + ETHINTFC_jam_m = 0x00000008,
8923 + ETHINTFC_ovr_b = 4,
8924 + ETHINTFC_ovr_m = 0x00000010,
8925 + ETHINTFC_und_b = 5,
8926 + ETHINTFC_und_m = 0x00000020,
8927 +
8928 + ETHFIFOTT_tth_b = 0,
8929 + ETHFIFOTT_tth_m = 0x0000007f,
8930 +
8931 + ETHARC_pro_b = 0,
8932 + ETHARC_pro_m = 0x00000001,
8933 + ETHARC_am_b = 1,
8934 + ETHARC_am_m = 0x00000002,
8935 + ETHARC_afm_b = 2,
8936 + ETHARC_afm_m = 0x00000004,
8937 + ETHARC_ab_b = 3,
8938 + ETHARC_ab_m = 0x00000008,
8939 +
8940 + ETHSAL_byte5_b = 0,
8941 + ETHSAL_byte5_m = 0x000000ff,
8942 + ETHSAL_byte4_b = 8,
8943 + ETHSAL_byte4_m = 0x0000ff00,
8944 + ETHSAL_byte3_b = 16,
8945 + ETHSAL_byte3_m = 0x00ff0000,
8946 + ETHSAL_byte2_b = 24,
8947 + ETHSAL_byte2_m = 0xff000000,
8948 +
8949 + ETHSAH_byte1_b = 0,
8950 + ETHSAH_byte1_m = 0x000000ff,
8951 + ETHSAH_byte0_b = 8,
8952 + ETHSAH_byte0_m = 0x0000ff00,
8953 +
8954 + ETHGPF_ptv_b = 0,
8955 + ETHGPF_ptv_m = 0x0000ffff,
8956 +
8957 + ETHPFS_pfd_b = 0,
8958 + ETHPFS_pfd_m = 0x00000001,
8959 +
8960 + ETHCFSA0_cfsa4_b = 0,
8961 + ETHCFSA0_cfsa4_m = 0x000000ff,
8962 + ETHCFSA0_cfsa5_b = 8,
8963 + ETHCFSA0_cfsa5_m = 0x0000ff00,
8964 +
8965 + ETHCFSA1_cfsa2_b = 0,
8966 + ETHCFSA1_cfsa2_m = 0x000000ff,
8967 + ETHCFSA1_cfsa3_b = 8,
8968 + ETHCFSA1_cfsa3_m = 0x0000ff00,
8969 +
8970 + ETHCFSA2_cfsa0_b = 0,
8971 + ETHCFSA2_cfsa0_m = 0x000000ff,
8972 + ETHCFSA2_cfsa1_b = 8,
8973 + ETHCFSA2_cfsa1_m = 0x0000ff00,
8974 +
8975 + ETHMAC1_re_b = 0,
8976 + ETHMAC1_re_m = 0x00000001,
8977 + ETHMAC1_paf_b = 1,
8978 + ETHMAC1_paf_m = 0x00000002,
8979 + ETHMAC1_rfc_b = 2,
8980 + ETHMAC1_rfc_m = 0x00000004,
8981 + ETHMAC1_tfc_b = 3,
8982 + ETHMAC1_tfc_m = 0x00000008,
8983 + ETHMAC1_lb_b = 4,
8984 + ETHMAC1_lb_m = 0x00000010,
8985 + ETHMAC1_mr_b = 31,
8986 + ETHMAC1_mr_m = 0x80000000,
8987 +
8988 + ETHMAC2_fd_b = 0,
8989 + ETHMAC2_fd_m = 0x00000001,
8990 + ETHMAC2_flc_b = 1,
8991 + ETHMAC2_flc_m = 0x00000002,
8992 + ETHMAC2_hfe_b = 2,
8993 + ETHMAC2_hfe_m = 0x00000004,
8994 + ETHMAC2_dc_b = 3,
8995 + ETHMAC2_dc_m = 0x00000008,
8996 + ETHMAC2_cen_b = 4,
8997 + ETHMAC2_cen_m = 0x00000010,
8998 + ETHMAC2_pe_b = 5,
8999 + ETHMAC2_pe_m = 0x00000020,
9000 + ETHMAC2_vpe_b = 6,
9001 + ETHMAC2_vpe_m = 0x00000040,
9002 + ETHMAC2_ape_b = 7,
9003 + ETHMAC2_ape_m = 0x00000080,
9004 + ETHMAC2_ppe_b = 8,
9005 + ETHMAC2_ppe_m = 0x00000100,
9006 + ETHMAC2_lpe_b = 9,
9007 + ETHMAC2_lpe_m = 0x00000200,
9008 + ETHMAC2_nb_b = 12,
9009 + ETHMAC2_nb_m = 0x00001000,
9010 + ETHMAC2_bp_b = 13,
9011 + ETHMAC2_bp_m = 0x00002000,
9012 + ETHMAC2_ed_b = 14,
9013 + ETHMAC2_ed_m = 0x00004000,
9014 +
9015 + ETHIPGT_ipgt_b = 0,
9016 + ETHIPGT_ipgt_m = 0x0000007f,
9017 +
9018 + ETHIPGR_ipgr2_b = 0,
9019 + ETHIPGR_ipgr2_m = 0x0000007f,
9020 + ETHIPGR_ipgr1_b = 8,
9021 + ETHIPGR_ipgr1_m = 0x00007f00,
9022 +
9023 + ETHCLRT_maxret_b = 0,
9024 + ETHCLRT_maxret_m = 0x0000000f,
9025 + ETHCLRT_colwin_b = 8,
9026 + ETHCLRT_colwin_m = 0x00003f00,
9027 +
9028 + ETHMAXF_maxf_b = 0,
9029 + ETHMAXF_maxf_m = 0x0000ffff,
9030 +
9031 + ETHMTEST_tb_b = 2,
9032 + ETHMTEST_tb_m = 0x00000004,
9033 +
9034 + ETHMCP_div_b = 0,
9035 + ETHMCP_div_m = 0x000000ff,
9036 +
9037 + MIIMCFG_rsv_b = 0,
9038 + MIIMCFG_rsv_m = 0x0000000c,
9039 +
9040 + MIIMCMD_rd_b = 0,
9041 + MIIMCMD_rd_m = 0x00000001,
9042 + MIIMCMD_scn_b = 1,
9043 + MIIMCMD_scn_m = 0x00000002,
9044 +
9045 + MIIMADDR_regaddr_b = 0,
9046 + MIIMADDR_regaddr_m = 0x0000001f,
9047 + MIIMADDR_phyaddr_b = 8,
9048 + MIIMADDR_phyaddr_m = 0x00001f00,
9049 +
9050 + MIIMWTD_wdata_b = 0,
9051 + MIIMWTD_wdata_m = 0x0000ffff,
9052 +
9053 + MIIMRDD_rdata_b = 0,
9054 + MIIMRDD_rdata_m = 0x0000ffff,
9055 +
9056 + MIIMIND_bsy_b = 0,
9057 + MIIMIND_bsy_m = 0x00000001,
9058 + MIIMIND_scn_b = 1,
9059 + MIIMIND_scn_m = 0x00000002,
9060 + MIIMIND_nv_b = 2,
9061 + MIIMIND_nv_m = 0x00000004,
9062 +
9063 +} ;
9064 +
9065 +/*
9066 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
9067 + */
9068 +enum
9069 +{
9070 + ETHRX_fd_b = 0,
9071 + ETHRX_fd_m = 0x00000001,
9072 + ETHRX_ld_b = 1,
9073 + ETHRX_ld_m = 0x00000002,
9074 + ETHRX_rok_b = 2,
9075 + ETHRX_rok_m = 0x00000004,
9076 + ETHRX_fm_b = 3,
9077 + ETHRX_fm_m = 0x00000008,
9078 + ETHRX_mp_b = 4,
9079 + ETHRX_mp_m = 0x00000010,
9080 + ETHRX_bp_b = 5,
9081 + ETHRX_bp_m = 0x00000020,
9082 + ETHRX_vlt_b = 6,
9083 + ETHRX_vlt_m = 0x00000040,
9084 + ETHRX_cf_b = 7,
9085 + ETHRX_cf_m = 0x00000080,
9086 + ETHRX_ovr_b = 8,
9087 + ETHRX_ovr_m = 0x00000100,
9088 + ETHRX_crc_b = 9,
9089 + ETHRX_crc_m = 0x00000200,
9090 + ETHRX_cv_b = 10,
9091 + ETHRX_cv_m = 0x00000400,
9092 + ETHRX_db_b = 11,
9093 + ETHRX_db_m = 0x00000800,
9094 + ETHRX_le_b = 12,
9095 + ETHRX_le_m = 0x00001000,
9096 + ETHRX_lor_b = 13,
9097 + ETHRX_lor_m = 0x00002000,
9098 + ETHRX_ces_b = 14,
9099 + ETHRX_ces_m = 0x00004000,
9100 + ETHRX_length_b = 16,
9101 + ETHRX_length_m = 0xffff0000,
9102 +
9103 + ETHTX_fd_b = 0,
9104 + ETHTX_fd_m = 0x00000001,
9105 + ETHTX_ld_b = 1,
9106 + ETHTX_ld_m = 0x00000002,
9107 + ETHTX_oen_b = 2,
9108 + ETHTX_oen_m = 0x00000004,
9109 + ETHTX_pen_b = 3,
9110 + ETHTX_pen_m = 0x00000008,
9111 + ETHTX_cen_b = 4,
9112 + ETHTX_cen_m = 0x00000010,
9113 + ETHTX_hen_b = 5,
9114 + ETHTX_hen_m = 0x00000020,
9115 + ETHTX_tok_b = 6,
9116 + ETHTX_tok_m = 0x00000040,
9117 + ETHTX_mp_b = 7,
9118 + ETHTX_mp_m = 0x00000080,
9119 + ETHTX_bp_b = 8,
9120 + ETHTX_bp_m = 0x00000100,
9121 + ETHTX_und_b = 9,
9122 + ETHTX_und_m = 0x00000200,
9123 + ETHTX_of_b = 10,
9124 + ETHTX_of_m = 0x00000400,
9125 + ETHTX_ed_b = 11,
9126 + ETHTX_ed_m = 0x00000800,
9127 + ETHTX_ec_b = 12,
9128 + ETHTX_ec_m = 0x00001000,
9129 + ETHTX_lc_b = 13,
9130 + ETHTX_lc_m = 0x00002000,
9131 + ETHTX_td_b = 14,
9132 + ETHTX_td_m = 0x00004000,
9133 + ETHTX_crc_b = 15,
9134 + ETHTX_crc_m = 0x00008000,
9135 + ETHTX_le_b = 16,
9136 + ETHTX_le_m = 0x00010000,
9137 + ETHTX_cc_b = 17,
9138 + ETHTX_cc_m = 0x001E0000,
9139 +} ;
9140 +#endif //__IDT_RC32438_ETH_H__
9141 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h
9142 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h 1970-01-01 01:00:00.000000000 +0100
9143 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h 2006-01-10 00:32:33.000000000 +0100
9144 @@ -0,0 +1,72 @@
9145 +/**************************************************************************
9146 + *
9147 + * BRIEF MODULE DESCRIPTION
9148 + * macros for IDT EB438 ethernet
9149 + *
9150 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9151 + *
9152 + * This program is free software; you can redistribute it and/or modify it
9153 + * under the terms of the GNU General Public License as published by the
9154 + * Free Software Foundation; either version 2 of the License, or (at your
9155 + * option) any later version.
9156 + *
9157 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9158 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9159 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9160 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9161 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9162 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9163 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9164 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9165 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9166 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9167 + *
9168 + * You should have received a copy of the GNU General Public License along
9169 + * with this program; if not, write to the Free Software Foundation, Inc.,
9170 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9171 + *
9172 + *
9173 + **************************************************************************
9174 + * May 2004 P. Sadik.
9175 + *
9176 + * Initial Release
9177 + *
9178 + *
9179 + *
9180 + **************************************************************************
9181 + */
9182 +
9183 +#ifndef __IDT_RC32438_ETH_V_H__
9184 +#define __IDT_RC32438_ETH_V_H__
9185 +#include <asm/idt-boards/rc32438/rc32438_eth.h>
9186 +
9187 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
9188 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
9189 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
9190 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
9191 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
9192 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
9193 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
9194 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
9195 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
9196 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
9197 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
9198 +
9199 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
9200 +
9201 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
9202 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
9203 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
9204 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
9205 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
9206 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
9207 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
9208 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
9209 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
9210 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
9211 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
9212 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
9213 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
9214 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
9215 +
9216 +#endif //__IDT_RC32438_ETH_V_H__
9217 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h
9218 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h 1970-01-01 01:00:00.000000000 +0100
9219 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h 2006-01-10 00:32:33.000000000 +0100
9220 @@ -0,0 +1,257 @@
9221 +/**************************************************************************
9222 + *
9223 + * BRIEF MODULE DESCRIPTION
9224 + * Definitions for IDT RC32438 GPIO.
9225 + *
9226 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9227 + *
9228 + * This program is free software; you can redistribute it and/or modify it
9229 + * under the terms of the GNU General Public License as published by the
9230 + * Free Software Foundation; either version 2 of the License, or (at your
9231 + * option) any later version.
9232 + *
9233 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9234 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9235 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9236 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9237 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9238 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9239 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9240 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9241 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9242 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9243 + *
9244 + * You should have received a copy of the GNU General Public License along
9245 + * with this program; if not, write to the Free Software Foundation, Inc.,
9246 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9247 + *
9248 + *
9249 + **************************************************************************
9250 + * May 2004 P. Sadik.
9251 + *
9252 + * Initial Release
9253 + *
9254 + *
9255 + *
9256 + **************************************************************************
9257 + */
9258 +#ifndef __IDT_RC32438_GPIO_H__
9259 +#define __IDT_RC32438_GPIO_H__
9260 +enum
9261 +{
9262 + GPIO0_PhysicalAddress = 0x18048000,
9263 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
9264 +
9265 + GPIO0_VirtualAddress = 0xb8048000,
9266 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
9267 +} ;
9268 +
9269 +typedef struct
9270 +{
9271 + u32 gpiofunc; /* GPIO Function Register
9272 + * gpiofunc[x]==0 bit = gpio
9273 + * func[x]==1 bit = altfunc
9274 + */
9275 + u32 gpiocfg; /* GPIO Configuration Register
9276 + * gpiocfg[x]==0 bit = input
9277 + * gpiocfg[x]==1 bit = output
9278 + */
9279 + u32 gpiod; /* GPIO Data Register
9280 + * gpiod[x] read/write gpio pinX status
9281 + */
9282 + u32 gpioilevel; /* GPIO Interrupt Status Register
9283 + * interrupt level (see gpioistat)
9284 + */
9285 + u32 gpioistat; /* Gpio Interrupt Status Register
9286 + * istat[x] = (gpiod[x] == level[x])
9287 + * cleared in ISR (STICKY bits)
9288 + */
9289 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
9290 +} volatile * GPIO_t ;
9291 +
9292 +typedef enum
9293 +{
9294 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
9295 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
9296 + GPIO_input_v = 0, // gpiocfg use pin as input.
9297 + GPIO_output_v = 1, // gpiocfg use pin as output.
9298 + GPIO_pin0_b = 0,
9299 + GPIO_pin0_m = 0x00000001,
9300 + GPIO_pin1_b = 1,
9301 + GPIO_pin1_m = 0x00000002,
9302 + GPIO_pin2_b = 2,
9303 + GPIO_pin2_m = 0x00000004,
9304 + GPIO_pin3_b = 3,
9305 + GPIO_pin3_m = 0x00000008,
9306 + GPIO_pin4_b = 4,
9307 + GPIO_pin4_m = 0x00000010,
9308 + GPIO_pin5_b = 5,
9309 + GPIO_pin5_m = 0x00000020,
9310 + GPIO_pin6_b = 6,
9311 + GPIO_pin6_m = 0x00000040,
9312 + GPIO_pin7_b = 7,
9313 + GPIO_pin7_m = 0x00000080,
9314 + GPIO_pin8_b = 8,
9315 + GPIO_pin8_m = 0x00000100,
9316 + GPIO_pin9_b = 9,
9317 + GPIO_pin9_m = 0x00000200,
9318 + GPIO_pin10_b = 10,
9319 + GPIO_pin10_m = 0x00000400,
9320 + GPIO_pin11_b = 11,
9321 + GPIO_pin11_m = 0x00000800,
9322 + GPIO_pin12_b = 12,
9323 + GPIO_pin12_m = 0x00001000,
9324 + GPIO_pin13_b = 13,
9325 + GPIO_pin13_m = 0x00002000,
9326 + GPIO_pin14_b = 14,
9327 + GPIO_pin14_m = 0x00004000,
9328 + GPIO_pin15_b = 15,
9329 + GPIO_pin15_m = 0x00008000,
9330 + GPIO_pin16_b = 16,
9331 + GPIO_pin16_m = 0x00010000,
9332 + GPIO_pin17_b = 17,
9333 + GPIO_pin17_m = 0x00020000,
9334 + GPIO_pin18_b = 18,
9335 + GPIO_pin18_m = 0x00040000,
9336 + GPIO_pin19_b = 19,
9337 + GPIO_pin19_m = 0x00080000,
9338 + GPIO_pin20_b = 20,
9339 + GPIO_pin20_m = 0x00100000,
9340 + GPIO_pin21_b = 21,
9341 + GPIO_pin21_m = 0x00200000,
9342 + GPIO_pin22_b = 22,
9343 + GPIO_pin22_m = 0x00400000,
9344 + GPIO_pin23_b = 23,
9345 + GPIO_pin23_m = 0x00800000,
9346 + GPIO_pin24_b = 24,
9347 + GPIO_pin24_m = 0x01000000,
9348 + GPIO_pin25_b = 25,
9349 + GPIO_pin25_m = 0x02000000,
9350 + GPIO_pin26_b = 26,
9351 + GPIO_pin26_m = 0x04000000,
9352 + GPIO_pin27_b = 27,
9353 + GPIO_pin27_m = 0x08000000,
9354 + GPIO_pin28_b = 28,
9355 + GPIO_pin28_m = 0x10000000,
9356 + GPIO_pin29_b = 29,
9357 + GPIO_pin29_m = 0x20000000,
9358 + GPIO_pin30_b = 30,
9359 + GPIO_pin30_m = 0x40000000,
9360 + GPIO_pin31_b = 31,
9361 + GPIO_pin31_m = 0x80000000,
9362 +
9363 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
9364 +
9365 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
9366 + GPIO_u0sout_m = GPIO_pin0_m,
9367 + GPIO_u0sout_cfg_v = GPIO_output_v,
9368 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
9369 + GPIO_u0sinp_m = GPIO_pin1_m,
9370 + GPIO_u0sinp_cfg_v = GPIO_input_v,
9371 + GPIO_u0rin_b = GPIO_pin2_b, // UART 0 ring indic.
9372 + GPIO_u0rin_m = GPIO_pin2_m,
9373 + GPIO_u0rin_cfg_v = GPIO_input_v,
9374 + GPIO_u0dcdn_b = GPIO_pin3_b, // UART 0 data carr.det.
9375 + GPIO_u0dcdn_m = GPIO_pin3_m,
9376 + GPIO_u0dcdn_cfg_v = GPIO_input_v,
9377 + GPIO_u0dtrn_b = GPIO_pin4_b, // UART 0 data term rdy.
9378 + GPIO_u0dtrn_m = GPIO_pin4_m,
9379 + GPIO_u0dtrn_cfg_v = GPIO_output_v,
9380 + GPIO_u0dsrn_b = GPIO_pin5_b, // UART 0 data set rdy.
9381 + GPIO_u0dsrn_m = GPIO_pin5_m,
9382 + GPIO_u0dsrn_cfg_v = GPIO_input_v,
9383 + GPIO_u0rtsn_b = GPIO_pin6_b, // UART 0 req. to send.
9384 + GPIO_u0rtsn_m = GPIO_pin6_m,
9385 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
9386 + GPIO_u0ctsn_b = GPIO_pin7_b, // UART 0 clear to send.
9387 + GPIO_u0ctsn_m = GPIO_pin7_m,
9388 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
9389 +
9390 + GPIO_u1sout_b = GPIO_pin8_b, // UART 1 serial out.
9391 + GPIO_u1sout_m = GPIO_pin8_m,
9392 + GPIO_u1sout_cfg_v = GPIO_output_v,
9393 + GPIO_u1sinp_b = GPIO_pin9_b, // UART 1 serial in.
9394 + GPIO_u1sinp_m = GPIO_pin9_m,
9395 + GPIO_u1sinp_cfg_v = GPIO_input_v,
9396 + GPIO_u1dtrn_b = GPIO_pin10_b, // UART 1 data term rdy.
9397 + GPIO_u1dtrn_m = GPIO_pin10_m,
9398 + GPIO_u1dtrn_cfg_v = GPIO_output_v,
9399 + GPIO_u1dsrn_b = GPIO_pin11_b, // UART 1 data set rdy.
9400 + GPIO_u1dsrn_m = GPIO_pin11_m,
9401 + GPIO_u1dsrn_cfg_v = GPIO_input_v,
9402 + GPIO_u1rtsn_b = GPIO_pin12_b, // UART 1 req. to send.
9403 + GPIO_u1rtsn_m = GPIO_pin12_m,
9404 + GPIO_u1rtsn_cfg_v = GPIO_output_v,
9405 + GPIO_u1ctsn_b = GPIO_pin13_b, // UART 1 clear to send.
9406 + GPIO_u1ctsn_m = GPIO_pin13_m,
9407 + GPIO_u1ctsn_cfg_v = GPIO_input_v,
9408 +
9409 + GPIO_dmareqn0_b = GPIO_pin14_b, // Ext. DMA 0 request
9410 + GPIO_dmareqn0_m = GPIO_pin14_m,
9411 + GPIO_dmareqn0_cfg_v = GPIO_input_v,
9412 +
9413 + GPIO_dmareqn1_b = GPIO_pin15_b, // Ext. DMA 1 request
9414 + GPIO_dmareqn1_m = GPIO_pin15_m,
9415 + GPIO_dmareqn1_cfg_v = GPIO_input_v,
9416 +
9417 + GPIO_dmadonen0_b = GPIO_pin16_b, // Ext. DMA 0 done
9418 + GPIO_dmadonen0_m = GPIO_pin16_m,
9419 + GPIO_dmadonen0_cfg_v = GPIO_input_v,
9420 +
9421 + GPIO_dmadonen1_b = GPIO_pin17_b, // Ext. DMA 1 done
9422 + GPIO_dmadonen1_m = GPIO_pin17_m,
9423 + GPIO_dmadonen1_cfg_v = GPIO_input_v,
9424 +
9425 + GPIO_dmafinn0_b = GPIO_pin18_b, // Ext. DMA 0 finished
9426 + GPIO_dmafinn0_m = GPIO_pin18_m,
9427 + GPIO_dmafinn0_cfg_v = GPIO_output_v,
9428 +
9429 + GPIO_dmafinn1_b = GPIO_pin19_b, // Ext. DMA 1 finished
9430 + GPIO_dmafinn1_m = GPIO_pin19_m,
9431 + GPIO_dmafinn1_cfg_v = GPIO_output_v,
9432 +
9433 + GPIO_maddr22_b = GPIO_pin20_b, // M&P bus bit 22.
9434 + GPIO_maddr22_m = GPIO_pin20_m,
9435 + GPIO_maddr22_cfg_v = GPIO_output_v,
9436 +
9437 + GPIO_maddr23_b = GPIO_pin21_b, // M&P bus bit 23.
9438 + GPIO_maddr23_m = GPIO_pin21_m,
9439 + GPIO_maddr23_cfg_v = GPIO_output_v,
9440 +
9441 + GPIO_maddr24_b = GPIO_pin22_b, // M&P bus bit 24.
9442 + GPIO_maddr24_m = GPIO_pin22_m,
9443 + GPIO_maddr24_cfg_v = GPIO_output_v,
9444 +
9445 + GPIO_maddr25_b = GPIO_pin23_b, // M&P bus bit 25.
9446 + GPIO_maddr25_m = GPIO_pin23_m,
9447 + GPIO_maddr25_cfg_v = GPIO_output_v,
9448 +
9449 + GPIO_afspare6_b = GPIO_pin24_b, // reserved.
9450 + GPIO_afspare6_m = GPIO_pin24_m,
9451 + GPIO_afspare6_cfg_v = GPIO_input_v,
9452 + GPIO_afspare5_b = GPIO_pin25_b, // reserved.
9453 + GPIO_afspare5_m = GPIO_pin25_m,
9454 + GPIO_afspare5_cfg_v = GPIO_input_v,
9455 + GPIO_afspare4_b = GPIO_pin26_b, // reserved.
9456 + GPIO_afspare4_m = GPIO_pin26_m,
9457 + GPIO_afspare4_cfg_v = GPIO_input_v,
9458 + GPIO_afspare3_b = GPIO_pin27_b, // reserved.
9459 + GPIO_afspare3_m = GPIO_pin27_m,
9460 + GPIO_afspare3_cfg_v = GPIO_input_v,
9461 + GPIO_afspare2_b = GPIO_pin28_b, // reserved.
9462 + GPIO_afspare2_m = GPIO_pin28_m,
9463 + GPIO_afspare2_cfg_v = GPIO_input_v,
9464 + GPIO_afspare1_b = GPIO_pin29_b, // reserved.
9465 + GPIO_afspare1_m = GPIO_pin29_m,
9466 + GPIO_afspare1_cfg_v = GPIO_input_v,
9467 +
9468 + GPIO_pcimuintn_b = GPIO_pin30_b, // PCI messaging int.
9469 + GPIO_pcimuintn_m = GPIO_pin30_m,
9470 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
9471 +
9472 + GPIO_rngclk_b = GPIO_pin31_b, // RNG external clock
9473 + GPIO_rngclk_m = GPIO_pin31_m,
9474 + GPIO_rncclk_cfg_v = GPIO_input_v,
9475 +} GPIO_DEFS_t;
9476 +
9477 +#endif //__IDT_RC32438_GPIO_H__
9478 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438.h
9479 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438.h 1970-01-01 01:00:00.000000000 +0100
9480 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438.h 2006-01-10 00:32:33.000000000 +0100
9481 @@ -0,0 +1,152 @@
9482 +/**************************************************************************
9483 + *
9484 + * BRIEF MODULE DESCRIPTION
9485 + * Definitions for IDT RC32438 CPU.
9486 + *
9487 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9488 + *
9489 + * This program is free software; you can redistribute it and/or modify it
9490 + * under the terms of the GNU General Public License as published by the
9491 + * Free Software Foundation; either version 2 of the License, or (at your
9492 + * option) any later version.
9493 + *
9494 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9495 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9496 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9497 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9498 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9499 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9500 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9501 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9502 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9503 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9504 + *
9505 + * You should have received a copy of the GNU General Public License along
9506 + * with this program; if not, write to the Free Software Foundation, Inc.,
9507 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9508 + *
9509 + *
9510 + **************************************************************************
9511 + * May 2004 P. Sadik.
9512 + *
9513 + * Initial Release
9514 + *
9515 + *
9516 + *
9517 + **************************************************************************
9518 + */
9519 +
9520 +#ifndef __IDT_RC32438_H__
9521 +#define __IDT_RC32438_H__
9522 +#include <linux/config.h>
9523 +#include <linux/delay.h>
9524 +#include <asm/io.h>
9525 +#include <asm/idt-boards/rc32438/rc32438_timer.h>
9526 +
9527 +#define RC32438_REG_BASE 0x18000000
9528 +
9529 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
9530 +#define idttimer ((volatile TIM_t) TIM0_VirtualAddress)
9531 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
9532 +
9533 +#define IDT_CLOCK_MULT 2
9534 +#define MIPS_CPU_TIMER_IRQ 7
9535 +/* Interrupt Controller */
9536 +#define IC_GROUP0_PEND (RC32438_REG_BASE + 0x38000)
9537 +#define IC_GROUP0_MASK (RC32438_REG_BASE + 0x38008)
9538 +#define IC_GROUP_OFFSET 0x0C
9539 +#define RTC_BASE 0xAC0801FF0
9540 +
9541 +#define NUM_INTR_GROUPS 5
9542 +/* 16550 UARTs */
9543 +
9544 +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
9545 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
9546 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
9547 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
9548 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
9549 +
9550 +#ifdef __MIPSEB__
9551 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50003)
9552 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50023)
9553 +#else
9554 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50000)
9555 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50020)
9556 +#endif
9557 +
9558 +#define RC32438_UART0_IRQ GROUP3_IRQ_BASE + 0
9559 +#define RC32438_UART1_IRQ GROUP3_IRQ_BASE + 3
9560 +
9561 +#define RC32438_NR_IRQS (GROUP4_IRQ_BASE + 32)
9562 +
9563 +
9564 +
9565 +/* cpu pipeline flush */
9566 +static inline void rc32438_sync(void)
9567 +{
9568 + __asm__ volatile ("sync");
9569 +}
9570 +
9571 +static inline void rc32438_sync_udelay(int us)
9572 +{
9573 + __asm__ volatile ("sync");
9574 + udelay(us);
9575 +}
9576 +
9577 +static inline void rc32438_sync_delay(int ms)
9578 +{
9579 + __asm__ volatile ("sync");
9580 + mdelay(ms);
9581 +}
9582 +
9583 +/*
9584 + * Macros to access internal RC32438 registers. No byte
9585 + * swapping should be done when accessing the internal
9586 + * registers.
9587 + */
9588 +
9589 +#define rc32438_readb __raw_readb
9590 +#define rc32438_readw __raw_readw
9591 +#define rc32438_readl __raw_readl
9592 +
9593 +#define rc32438_writeb __raw_writeb
9594 +#define rc32438_writew __raw_writew
9595 +#define rc32438_writel __raw_writel
9596 +
9597 +/*
9598 + * C access to CLZ and CLO instructions
9599 + * (count leading zeroes/ones).
9600 + */
9601 +static inline int rc32438_clz(unsigned long val)
9602 +{
9603 + int ret;
9604 + __asm__ volatile (
9605 + ".set\tnoreorder\n\t"
9606 + ".set\tnoat\n\t"
9607 + ".set\tmips32\n\t"
9608 + "clz\t%0,%1\n\t"
9609 + ".set\tmips0\n\t"
9610 + ".set\tat\n\t"
9611 + ".set\treorder"
9612 + : "=r" (ret)
9613 + : "r" (val));
9614 +
9615 + return ret;
9616 +}
9617 +static inline int rc32438_clo(unsigned long val)
9618 +{
9619 + int ret;
9620 + __asm__ volatile (
9621 + ".set\tnoreorder\n\t"
9622 + ".set\tnoat\n\t"
9623 + ".set\tmips32\n\t"
9624 + "clo\t%0,%1\n\t"
9625 + ".set\tmips0\n\t"
9626 + ".set\tat\n\t"
9627 + ".set\treorder"
9628 + : "=r" (ret)
9629 + : "r" (val));
9630 +
9631 + return ret;
9632 +}
9633 +#endif //__IDT_RC32438_H__
9634 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_pci.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h
9635 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 1970-01-01 01:00:00.000000000 +0100
9636 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 2006-01-10 00:32:33.000000000 +0100
9637 @@ -0,0 +1,510 @@
9638 +/**************************************************************************
9639 + *
9640 + * BRIEF MODULE DESCRIPTION
9641 + * Definitions for IDT RC32438 PCI.
9642 + *
9643 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9644 + *
9645 + * This program is free software; you can redistribute it and/or modify it
9646 + * under the terms of the GNU General Public License as published by the
9647 + * Free Software Foundation; either version 2 of the License, or (at your
9648 + * option) any later version.
9649 + *
9650 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9651 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9652 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9653 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9654 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9655 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9656 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9657 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9658 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9659 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9660 + *
9661 + * You should have received a copy of the GNU General Public License along
9662 + * with this program; if not, write to the Free Software Foundation, Inc.,
9663 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9664 + *
9665 + *
9666 + **************************************************************************
9667 + * May 2004 P. Sadik
9668 + *
9669 + * Initial Release
9670 + *
9671 + *
9672 + *
9673 + **************************************************************************
9674 + */
9675 +
9676 +enum
9677 +{
9678 + PCI0_PhysicalAddress = 0x18080000,
9679 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
9680 +
9681 + PCI0_VirtualAddress = 0xb8080000,
9682 + PCI_VirtualAddress = PCI0_VirtualAddress,
9683 +} ;
9684 +
9685 +enum
9686 +{
9687 + PCI_LbaCount = 4, // Local base addresses.
9688 +} ;
9689 +
9690 +typedef struct
9691 +{
9692 + u32 a ; // Address.
9693 + u32 c ; // Control.
9694 + u32 m ; // mapping.
9695 +} PCI_Map_s ;
9696 +
9697 +typedef struct
9698 +{
9699 + u32 pcic ;
9700 + u32 pcis ;
9701 + u32 pcism ;
9702 + u32 pcicfga ;
9703 + u32 pcicfgd ;
9704 + PCI_Map_s pcilba [PCI_LbaCount] ;
9705 + u32 pcidac ;
9706 + u32 pcidas ;
9707 + u32 pcidasm ;
9708 + u32 pcidad ;
9709 + u32 pcidma8c ;
9710 + u32 pcidma9c ;
9711 + u32 pcitc ;
9712 +} volatile *PCI_t ;
9713 +
9714 +// PCI messaging unit.
9715 +enum
9716 +{
9717 + PCIM_Count = 2,
9718 +} ;
9719 +typedef struct
9720 +{
9721 + u32 pciim [PCIM_Count] ;
9722 + u32 pciom [PCIM_Count] ;
9723 + u32 pciid ;
9724 + u32 pciiic ;
9725 + u32 pciiim ;
9726 + u32 pciiod ;
9727 + u32 pciioic ;
9728 + u32 pciioim ;
9729 +} volatile *PCIM_t ;
9730 +
9731 +/*******************************************************************************
9732 + *
9733 + * PCI Control Register
9734 + *
9735 + ******************************************************************************/
9736 +enum
9737 +{
9738 + PCIC_en_b = 0,
9739 + PCIC_en_m = 0x00000001,
9740 + PCIC_tnr_b = 1,
9741 + PCIC_tnr_m = 0x00000002,
9742 + PCIC_sce_b = 2,
9743 + PCIC_sce_m = 0x00000004,
9744 + PCIC_ien_b = 3,
9745 + PCIC_ien_m = 0x00000008,
9746 + PCIC_aaa_b = 4,
9747 + PCIC_aaa_m = 0x00000010,
9748 + PCIC_eap_b = 5,
9749 + PCIC_eap_m = 0x00000020,
9750 + PCIC_pcim_b = 6,
9751 + PCIC_pcim_m = 0x000001c0,
9752 + PCIC_pcim_disabled_v = 0,
9753 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
9754 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
9755 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
9756 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
9757 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
9758 + PCIC_pcim_reserved6_v = 6,
9759 + PCIC_pcim_reserved7_v = 7,
9760 + PCIC_igm_b = 9,
9761 + PCIC_igm_m = 0x00000200,
9762 +} ;
9763 +
9764 +/*******************************************************************************
9765 + *
9766 + * PCI Status Register
9767 + *
9768 + ******************************************************************************/
9769 +enum {
9770 + PCIS_eed_b = 0,
9771 + PCIS_eed_m = 0x00000001,
9772 + PCIS_wr_b = 1,
9773 + PCIS_wr_m = 0x00000002,
9774 + PCIS_nmi_b = 2,
9775 + PCIS_nmi_m = 0x00000004,
9776 + PCIS_ii_b = 3,
9777 + PCIS_ii_m = 0x00000008,
9778 + PCIS_cwe_b = 4,
9779 + PCIS_cwe_m = 0x00000010,
9780 + PCIS_cre_b = 5,
9781 + PCIS_cre_m = 0x00000020,
9782 + PCIS_mdpe_b = 6,
9783 + PCIS_mdpe_m = 0x00000040,
9784 + PCIS_sta_b = 7,
9785 + PCIS_sta_m = 0x00000080,
9786 + PCIS_rta_b = 8,
9787 + PCIS_rta_m = 0x00000100,
9788 + PCIS_rma_b = 9,
9789 + PCIS_rma_m = 0x00000200,
9790 + PCIS_sse_b = 10,
9791 + PCIS_sse_m = 0x00000400,
9792 + PCIS_ose_b = 11,
9793 + PCIS_ose_m = 0x00000800,
9794 + PCIS_pe_b = 12,
9795 + PCIS_pe_m = 0x00001000,
9796 + PCIS_tae_b = 13,
9797 + PCIS_tae_m = 0x00002000,
9798 + PCIS_rle_b = 14,
9799 + PCIS_rle_m = 0x00004000,
9800 + PCIS_bme_b = 15,
9801 + PCIS_bme_m = 0x00008000,
9802 + PCIS_prd_b = 16,
9803 + PCIS_prd_m = 0x00010000,
9804 + PCIS_rip_b = 17,
9805 + PCIS_rip_m = 0x00020000,
9806 +} ;
9807 +
9808 +/*******************************************************************************
9809 + *
9810 + * PCI Status Mask Register
9811 + *
9812 + ******************************************************************************/
9813 +enum {
9814 + PCISM_eed_b = 0,
9815 + PCISM_eed_m = 0x00000001,
9816 + PCISM_wr_b = 1,
9817 + PCISM_wr_m = 0x00000002,
9818 + PCISM_nmi_b = 2,
9819 + PCISM_nmi_m = 0x00000004,
9820 + PCISM_ii_b = 3,
9821 + PCISM_ii_m = 0x00000008,
9822 + PCISM_cwe_b = 4,
9823 + PCISM_cwe_m = 0x00000010,
9824 + PCISM_cre_b = 5,
9825 + PCISM_cre_m = 0x00000020,
9826 + PCISM_mdpe_b = 6,
9827 + PCISM_mdpe_m = 0x00000040,
9828 + PCISM_sta_b = 7,
9829 + PCISM_sta_m = 0x00000080,
9830 + PCISM_rta_b = 8,
9831 + PCISM_rta_m = 0x00000100,
9832 + PCISM_rma_b = 9,
9833 + PCISM_rma_m = 0x00000200,
9834 + PCISM_sse_b = 10,
9835 + PCISM_sse_m = 0x00000400,
9836 + PCISM_ose_b = 11,
9837 + PCISM_ose_m = 0x00000800,
9838 + PCISM_pe_b = 12,
9839 + PCISM_pe_m = 0x00001000,
9840 + PCISM_tae_b = 13,
9841 + PCISM_tae_m = 0x00002000,
9842 + PCISM_rle_b = 14,
9843 + PCISM_rle_m = 0x00004000,
9844 + PCISM_bme_b = 15,
9845 + PCISM_bme_m = 0x00008000,
9846 + PCISM_prd_b = 16,
9847 + PCISM_prd_m = 0x00010000,
9848 + PCISM_rip_b = 17,
9849 + PCISM_rip_m = 0x00020000,
9850 +} ;
9851 +
9852 +/*******************************************************************************
9853 + *
9854 + * PCI Configuration Address Register
9855 + *
9856 + ******************************************************************************/
9857 +enum {
9858 + PCICFGA_reg_b = 2,
9859 + PCICFGA_reg_m = 0x000000fc,
9860 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
9861 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
9862 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
9863 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
9864 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
9865 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
9866 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
9867 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
9868 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
9869 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
9870 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
9871 + PCICFGA_reg_pba0m_v = 0x48>>2,
9872 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
9873 + PCICFGA_reg_pba1m_v = 0x50>>2,
9874 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
9875 + PCICFGA_reg_pba2m_v = 0x58>>2,
9876 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
9877 + PCICFGA_reg_pba3m_v = 0x60>>2,
9878 + PCICFGA_reg_pmgt_v = 0x64>>2,
9879 + PCICFGA_func_b = 8,
9880 + PCICFGA_func_m = 0x00000700,
9881 + PCICFGA_dev_b = 11,
9882 + PCICFGA_dev_m = 0x0000f800,
9883 + PCICFGA_dev_internal_v = 0,
9884 + PCICFGA_bus_b = 16,
9885 + PCICFGA_bus_m = 0x00ff0000,
9886 + PCICFGA_bus_type0_v = 0, //local bus
9887 + PCICFGA_en_b = 31, // read only
9888 + PCICFGA_en_m = 0x80000000,
9889 +} ;
9890 +
9891 +enum {
9892 + PCFGID_vendor_b = 0,
9893 + PCFGID_vendor_m = 0x0000ffff,
9894 + PCFGID_vendor_IDT_v = 0x111d,
9895 + PCFGID_device_b = 16,
9896 + PCFGID_device_m = 0xffff0000,
9897 + PCFGID_device_Acaciade_v = 0x0207,
9898 +
9899 + PCFG04_command_ioena_b = 1,
9900 + PCFG04_command_ioena_m = 0x00000001,
9901 + PCFG04_command_memena_b = 2,
9902 + PCFG04_command_memena_m = 0x00000002,
9903 + PCFG04_command_bmena_b = 3,
9904 + PCFG04_command_bmena_m = 0x00000004,
9905 + PCFG04_command_mwinv_b = 5,
9906 + PCFG04_command_mwinv_m = 0x00000010,
9907 + PCFG04_command_parena_b = 7,
9908 + PCFG04_command_parena_m = 0x00000040,
9909 + PCFG04_command_serrena_b = 9,
9910 + PCFG04_command_serrena_m = 0x00000100,
9911 + PCFG04_command_fastbbena_b = 10,
9912 + PCFG04_command_fastbbena_m = 0x00000200,
9913 + PCFG04_status_b = 16,
9914 + PCFG04_status_m = 0xffff0000,
9915 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
9916 + PCFG04_status_66MHz_m = 0x00200000,
9917 + PCFG04_status_fbb_b = 23,
9918 + PCFG04_status_fbb_m = 0x00800000,
9919 + PCFG04_status_mdpe_b = 24,
9920 + PCFG04_status_mdpe_m = 0x01000000,
9921 + PCFG04_status_dst_b = 25,
9922 + PCFG04_status_dst_m = 0x06000000,
9923 + PCFG04_status_sta_b = 27,
9924 + PCFG04_status_sta_m = 0x08000000,
9925 + PCFG04_status_rta_b = 28,
9926 + PCFG04_status_rta_m = 0x10000000,
9927 + PCFG04_status_rma_b = 29,
9928 + PCFG04_status_rma_m = 0x20000000,
9929 + PCFG04_status_sse_b = 30,
9930 + PCFG04_status_sse_m = 0x40000000,
9931 + PCFG04_status_pe_b = 31,
9932 + PCFG04_status_pe_m = 0x40000000,
9933 +
9934 + PCFG08_revId_b = 0,
9935 + PCFG08_revId_m = 0x000000ff,
9936 + PCFG08_classCode_b = 0,
9937 + PCFG08_classCode_m = 0xffffff00,
9938 + PCFG08_classCode_bridge_v = 06,
9939 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
9940 + PCFG0C_cacheline_b = 0,
9941 + PCFG0C_cacheline_m = 0x000000ff,
9942 + PCFG0C_masterLatency_b = 8,
9943 + PCFG0C_masterLatency_m = 0x0000ff00,
9944 + PCFG0C_headerType_b = 16,
9945 + PCFG0C_headerType_m = 0x00ff0000,
9946 + PCFG0C_bist_b = 24,
9947 + PCFG0C_bist_m = 0xff000000,
9948 +
9949 + PCIPBA_msi_b = 0,
9950 + PCIPBA_msi_m = 0x00000001,
9951 + PCIPBA_p_b = 3,
9952 + PCIPBA_p_m = 0x00000004,
9953 + PCIPBA_baddr_b = 8,
9954 + PCIPBA_baddr_m = 0xffffff00,
9955 +
9956 + PCFGSS_vendorId_b = 0,
9957 + PCFGSS_vendorId_m = 0x0000ffff,
9958 + PCFGSS_id_b = 16,
9959 + PCFGSS_id_m = 0xffff0000,
9960 +
9961 + PCFG3C_interruptLine_b = 0,
9962 + PCFG3C_interruptLine_m = 0x000000ff,
9963 + PCFG3C_interruptPin_b = 8,
9964 + PCFG3C_interruptPin_m = 0x0000ff00,
9965 + PCFG3C_minGrant_b = 16,
9966 + PCFG3C_minGrant_m = 0x00ff0000,
9967 + PCFG3C_maxLat_b = 24,
9968 + PCFG3C_maxLat_m = 0xff000000,
9969 +
9970 + PCIPBAC_msi_b = 0,
9971 + PCIPBAC_msi_m = 0x00000001,
9972 + PCIPBAC_p_b = 1,
9973 + PCIPBAC_p_m = 0x00000002,
9974 + PCIPBAC_size_b = 2,
9975 + PCIPBAC_size_m = 0x0000007c,
9976 + PCIPBAC_sb_b = 7,
9977 + PCIPBAC_sb_m = 0x00000080,
9978 + PCIPBAC_pp_b = 8,
9979 + PCIPBAC_pp_m = 0x00000100,
9980 + PCIPBAC_mr_b = 9,
9981 + PCIPBAC_mr_m = 0x00000600,
9982 + PCIPBAC_mr_read_v =0, //no prefetching
9983 + PCIPBAC_mr_readLine_v =1,
9984 + PCIPBAC_mr_readMult_v =2,
9985 + PCIPBAC_mrl_b = 11,
9986 + PCIPBAC_mrl_m = 0x00000800,
9987 + PCIPBAC_mrm_b = 12,
9988 + PCIPBAC_mrm_m = 0x00001000,
9989 + PCIPBAC_trp_b = 13,
9990 + PCIPBAC_trp_m = 0x00002000,
9991 +
9992 + PCFG40_trdyTimeout_b = 0,
9993 + PCFG40_trdyTimeout_m = 0x000000ff,
9994 + PCFG40_retryLim_b = 8,
9995 + PCFG40_retryLim_m = 0x0000ff00,
9996 +};
9997 +
9998 +/*******************************************************************************
9999 + *
10000 + * PCI Local Base Address [0|1|2|3] Register
10001 + *
10002 + ******************************************************************************/
10003 +enum {
10004 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
10005 + PCILBA_baddr_m = 0xffffff00,
10006 +} ;
10007 +/*******************************************************************************
10008 + *
10009 + * PCI Local Base Address Control Register
10010 + *
10011 + ******************************************************************************/
10012 +enum {
10013 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
10014 + PCILBAC_msi_m = 0x00000001,
10015 + PCILBAC_msi_mem_v = 0,
10016 + PCILBAC_msi_io_v = 1,
10017 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
10018 + PCILBAC_size_m = 0x0000007c,
10019 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
10020 + PCILBAC_sb_m = 0x00000080,
10021 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
10022 + PCILBAC_rt_m = 0x00000100,
10023 + PCILBAC_rt_noprefetch_v = 0, // mem read
10024 + PCILBAC_rt_prefetch_v = 1, // mem readline
10025 +} ;
10026 +
10027 +/*******************************************************************************
10028 + *
10029 + * PCI Local Base Address [0|1|2|3] Mapping Register
10030 + *
10031 + ******************************************************************************/
10032 +enum {
10033 + PCILBAM_maddr_b = 8,
10034 + PCILBAM_maddr_m = 0xffffff00,
10035 +} ;
10036 +
10037 +/*******************************************************************************
10038 + *
10039 + * PCI Decoupled Access Control Register
10040 + *
10041 + ******************************************************************************/
10042 +enum {
10043 + PCIDAC_den_b = 0,
10044 + PCIDAC_den_m = 0x00000001,
10045 +} ;
10046 +
10047 +/*******************************************************************************
10048 + *
10049 + * PCI Decoupled Access Status Register
10050 + *
10051 + ******************************************************************************/
10052 +enum {
10053 + PCIDAS_d_b = 0,
10054 + PCIDAS_d_m = 0x00000001,
10055 + PCIDAS_b_b = 1,
10056 + PCIDAS_b_m = 0x00000002,
10057 + PCIDAS_e_b = 2,
10058 + PCIDAS_e_m = 0x00000004,
10059 + PCIDAS_ofe_b = 3,
10060 + PCIDAS_ofe_m = 0x00000008,
10061 + PCIDAS_off_b = 4,
10062 + PCIDAS_off_m = 0x00000010,
10063 + PCIDAS_ife_b = 5,
10064 + PCIDAS_ife_m = 0x00000020,
10065 + PCIDAS_iff_b = 6,
10066 + PCIDAS_iff_m = 0x00000040,
10067 +} ;
10068 +
10069 +/*******************************************************************************
10070 + *
10071 + * PCI DMA Channel 8 Configuration Register
10072 + *
10073 + ******************************************************************************/
10074 +enum
10075 +{
10076 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
10077 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
10078 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
10079 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
10080 +} ;
10081 +
10082 +/*******************************************************************************
10083 + *
10084 + * PCI DMA Channel 9 Configuration Register
10085 + *
10086 + ******************************************************************************/
10087 +enum
10088 +{
10089 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
10090 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
10091 +} ;
10092 +
10093 +/*******************************************************************************
10094 + *
10095 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
10096 + *
10097 + ******************************************************************************/
10098 +enum {
10099 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
10100 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
10101 + // These are for reads (DMA channel 8)
10102 + PCIDMAD_devcmd_mr_v = 0, //memory read
10103 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
10104 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
10105 + PCIDMAD_devcmd_ior_v = 3, //I/O read
10106 + // These are for writes (DMA channel 9)
10107 + PCIDMAD_devcmd_mw_v = 0, //memory write
10108 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
10109 + PCIDMAD_devcmd_iow_v = 3, //I/O write
10110 +
10111 + // Swap byte field applies to both DMA channel 8 and 9
10112 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
10113 + PCIDMAD_sb_m = 0x01000000, // swap byte field
10114 +} ;
10115 +
10116 +
10117 +/*******************************************************************************
10118 + *
10119 + * PCI Target Control Register
10120 + *
10121 + ******************************************************************************/
10122 +enum
10123 +{
10124 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
10125 + PCITC_rtimer_m = 0x000000ff,
10126 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
10127 + PCITC_dtimer_m = 0x0000ff00,
10128 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
10129 + PCITC_rdr_m = 0x00040000,
10130 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
10131 + PCITC_ddt_m = 0x00080000,
10132 +} ;
10133 +/*******************************************************************************
10134 + *
10135 + * PCI messaging unit [applies to both inbound and outbound registers ]
10136 + *
10137 + ******************************************************************************/
10138 +enum
10139 +{
10140 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10141 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
10142 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10143 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
10144 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10145 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
10146 +};
10147 +
10148 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h
10149 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h 1970-01-01 01:00:00.000000000 +0100
10150 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h 2006-01-10 00:32:33.000000000 +0100
10151 @@ -0,0 +1,190 @@
10152 +/**************************************************************************
10153 + *
10154 + * BRIEF MODULE DESCRIPTION
10155 + * Definitions for IDT RC32438 PCI setup.
10156 + *
10157 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
10158 + *
10159 + * This program is free software; you can redistribute it and/or modify it
10160 + * under the terms of the GNU General Public License as published by the
10161 + * Free Software Foundation; either version 2 of the License, or (at your
10162 + * option) any later version.
10163 + *
10164 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10165 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
10166 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10167 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
10168 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10169 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
10170 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10171 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10172 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10173 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10174 + *
10175 + * You should have received a copy of the GNU General Public License along
10176 + * with this program; if not, write to the Free Software Foundation, Inc.,
10177 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10178 + *
10179 + *
10180 + **************************************************************************
10181 + * May 2004 P. Sadik
10182 + *
10183 + * Initial Release
10184 + *
10185 + *
10186 + *
10187 + **************************************************************************
10188 + */
10189 +
10190 +#define PCI_MSG_VirtualAddress 0xB8088010
10191 +#define rc32438_pci ((volatile PCI_t) PCI0_VirtualAddress)
10192 +#define rc32438_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
10193 +
10194 +#define PCIM_SHFT 0x6
10195 +#define PCIM_BIT_LEN 0x7
10196 +#define PCIM_H_EA 0x3
10197 +#define PCIM_H_IA_FIX 0x4
10198 +#define PCIM_H_IA_RR 0x5
10199 +
10200 +#define PCI_ADDR_START 0x50000000
10201 +
10202 +#define CPUTOPCI_MEM_WIN 0x02000000
10203 +#define CPUTOPCI_IO_WIN 0x00100000
10204 +#define PCILBA_SIZE_SHFT 2
10205 +#define PCILBA_SIZE_MASK 0x1F
10206 +#define SIZE_256MB 0x1C
10207 +#define SIZE_128MB 0x1B
10208 +#define SIZE_64MB 0x1A
10209 +#define SIZE_32MB 0x19
10210 +#define SIZE_16MB 0x18
10211 +#define SIZE_4MB 0x16
10212 +#define SIZE_2MB 0x15
10213 +#define SIZE_1MB 0x14
10214 +#define ACACIA_CONFIG0_ADDR 0x80000000
10215 +#define ACACIA_CONFIG1_ADDR 0x80000004
10216 +#define ACACIA_CONFIG2_ADDR 0x80000008
10217 +#define ACACIA_CONFIG3_ADDR 0x8000000C
10218 +#define ACACIA_CONFIG4_ADDR 0x80000010
10219 +#define ACACIA_CONFIG5_ADDR 0x80000014
10220 +#define ACACIA_CONFIG6_ADDR 0x80000018
10221 +#define ACACIA_CONFIG7_ADDR 0x8000001C
10222 +#define ACACIA_CONFIG8_ADDR 0x80000020
10223 +#define ACACIA_CONFIG9_ADDR 0x80000024
10224 +#define ACACIA_CONFIG10_ADDR 0x80000028
10225 +#define ACACIA_CONFIG11_ADDR 0x8000002C
10226 +#define ACACIA_CONFIG12_ADDR 0x80000030
10227 +#define ACACIA_CONFIG13_ADDR 0x80000034
10228 +#define ACACIA_CONFIG14_ADDR 0x80000038
10229 +#define ACACIA_CONFIG15_ADDR 0x8000003C
10230 +#define ACACIA_CONFIG16_ADDR 0x80000040
10231 +#define ACACIA_CONFIG17_ADDR 0x80000044
10232 +#define ACACIA_CONFIG18_ADDR 0x80000048
10233 +#define ACACIA_CONFIG19_ADDR 0x8000004C
10234 +#define ACACIA_CONFIG20_ADDR 0x80000050
10235 +#define ACACIA_CONFIG21_ADDR 0x80000054
10236 +#define ACACIA_CONFIG22_ADDR 0x80000058
10237 +#define ACACIA_CONFIG23_ADDR 0x8000005C
10238 +#define ACACIA_CONFIG24_ADDR 0x80000060
10239 +#define ACACIA_CONFIG25_ADDR 0x80000064
10240 +#define ACACIA_CMD (PCFG04_command_ioena_m | \
10241 + PCFG04_command_memena_m | \
10242 + PCFG04_command_bmena_m | \
10243 + PCFG04_command_mwinv_m | \
10244 + PCFG04_command_parena_m | \
10245 + PCFG04_command_serrena_m )
10246 +
10247 +#define ACACIA_STAT (PCFG04_status_mdpe_m | \
10248 + PCFG04_status_sta_m | \
10249 + PCFG04_status_rta_m | \
10250 + PCFG04_status_rma_m | \
10251 + PCFG04_status_sse_m | \
10252 + PCFG04_status_pe_m)
10253 +
10254 +#define ACACIA_CNFG1 ((ACACIA_STAT<<16)|ACACIA_CMD)
10255 +
10256 +#define ACACIA_REVID 0
10257 +#define ACACIA_CLASS_CODE 0
10258 +#define ACACIA_CNFG2 ((ACACIA_CLASS_CODE<<8) | \
10259 + ACACIA_REVID)
10260 +
10261 +#define ACACIA_CACHE_LINE_SIZE 4
10262 +#define ACACIA_MASTER_LAT 0x3c
10263 +#define ACACIA_HEADER_TYPE 0
10264 +#define ACACIA_BIST 0
10265 +
10266 +#define ACACIA_CNFG3 ((ACACIA_BIST << 24) | \
10267 + (ACACIA_HEADER_TYPE<<16) | \
10268 + (ACACIA_MASTER_LAT<<8) | \
10269 + ACACIA_CACHE_LINE_SIZE )
10270 +
10271 +#define ACACIA_BAR0 0x00000008 /* 128 MB Memory */
10272 +#define ACACIA_BAR1 0x18800001 /* 1 MB IO */
10273 +#define ACACIA_BAR2 0x18000001 /* 2 MB IO window for Acacia
10274 + internal Registers */
10275 +#define ACACIA_BAR3 0x48000008 /* Spare 128 MB Memory */
10276 +
10277 +#define ACACIA_CNFG4 ACACIA_BAR0
10278 +#define ACACIA_CNFG5 ACACIA_BAR1
10279 +#define ACACIA_CNFG6 ACACIA_BAR2
10280 +#define ACACIA_CNFG7 ACACIA_BAR3
10281 +
10282 +#define ACACIA_SUBSYS_VENDOR_ID 0
10283 +#define ACACIA_SUBSYSTEM_ID 0
10284 +#define ACACIA_CNFG8 0
10285 +#define ACACIA_CNFG9 0
10286 +#define ACACIA_CNFG10 0
10287 +#define ACACIA_CNFG11 ((ACACIA_SUBSYS_VENDOR_ID<<16) | \
10288 + ACACIA_SUBSYSTEM_ID)
10289 +#define ACACIA_INT_LINE 1
10290 +#define ACACIA_INT_PIN 1
10291 +#define ACACIA_MIN_GNT 8
10292 +#define ACACIA_MAX_LAT 0x38
10293 +#define ACACIA_CNFG12 0
10294 +#define ACACIA_CNFG13 0
10295 +#define ACACIA_CNFG14 0
10296 +#define ACACIA_CNFG15 ((ACACIA_MAX_LAT<<24) | \
10297 + (ACACIA_MIN_GNT<<16) | \
10298 + (ACACIA_INT_PIN<<8) | \
10299 + ACACIA_INT_LINE)
10300 +#define ACACIA_RETRY_LIMIT 0x80
10301 +#define ACACIA_TRDY_LIMIT 0x80
10302 +#define ACACIA_CNFG16 ((ACACIA_RETRY_LIMIT<<8) | \
10303 + ACACIA_TRDY_LIMIT)
10304 +#define PCI_PBAxC_R 0x0
10305 +#define PCI_PBAxC_RL 0x1
10306 +#define PCI_PBAxC_RM 0x2
10307 +#define SIZE_SHFT 2
10308 +
10309 +#define ACACIA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
10310 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
10311 + PCIPBAC_pp_m | \
10312 + (SIZE_128MB<<SIZE_SHFT) | \
10313 + PCIPBAC_p_m)
10314 +
10315 +#define ACACIA_CNFG17 ACACIA_PBA0C
10316 +#define ACACIA_PBA0M 0x0
10317 +#define ACACIA_CNFG18 ACACIA_PBA0M
10318 +
10319 +#define ACACIA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
10320 + PCIPBAC_msi_m)
10321 +
10322 +#define ACACIA_CNFG19 ACACIA_PBA1C
10323 +#define ACACIA_PBA1M 0x0
10324 +#define ACACIA_CNFG20 ACACIA_PBA1M
10325 +
10326 +#define ACACIA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
10327 + PCIPBAC_msi_m)
10328 +
10329 +#define ACACIA_CNFG21 ACACIA_PBA2C
10330 +#define ACACIA_PBA2M 0x18000000
10331 +#define ACACIA_CNFG22 ACACIA_PBA2M
10332 +#define ACACIA_PBA3C 0
10333 +#define ACACIA_CNFG23 ACACIA_PBA3C
10334 +#define ACACIA_PBA3M 0
10335 +#define ACACIA_CNFG24 ACACIA_PBA3M
10336 +
10337 +
10338 +
10339 +#define PCITC_DTIMER_VAL 8
10340 +#define PCITC_RTIMER_VAL 0x10
10341 +
10342 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_timer.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h
10343 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_timer.h 1970-01-01 01:00:00.000000000 +0100
10344 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h 2006-01-10 00:32:33.000000000 +0100
10345 @@ -0,0 +1,91 @@
10346 +/**************************************************************************
10347 + *
10348 + * BRIEF MODULE DESCRIPTION
10349 + * Timer register definition IDT RC32438 CPU.
10350 + *
10351 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
10352 + *
10353 + * This program is free software; you can redistribute it and/or modify it
10354 + * under the terms of the GNU General Public License as published by the
10355 + * Free Software Foundation; either version 2 of the License, or (at your
10356 + * option) any later version.
10357 + *
10358 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10359 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
10360 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10361 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
10362 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10363 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
10364 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10365 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10366 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10367 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10368 + *
10369 + * You should have received a copy of the GNU General Public License along
10370 + * with this program; if not, write to the Free Software Foundation, Inc.,
10371 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10372 + *
10373 + *
10374 + **************************************************************************
10375 + * May 2004 P. Sadik.
10376 + *
10377 + * Initial Release
10378 + *
10379 + *
10380 + *
10381 + **************************************************************************
10382 + */
10383 +
10384 +#ifndef __IDT_RC32438_TIM_H__
10385 +#define __IDT_RC32438_TIM_H__
10386 +
10387 +enum
10388 +{
10389 + TIM0_PhysicalAddress = 0x18028000,
10390 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
10391 +
10392 + TIM0_VirtualAddress = 0xb8028000,
10393 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
10394 +} ;
10395 +
10396 +enum
10397 +{
10398 + TIM_Count = 3,
10399 +} ;
10400 +
10401 +struct TIM_CNTR_s
10402 +{
10403 + u32 count ;
10404 + u32 compare ;
10405 + u32 ctc ; //use CTC_
10406 +} ;
10407 +
10408 +typedef struct TIM_s
10409 +{
10410 + struct TIM_CNTR_s tim [TIM_Count] ;
10411 + u32 rcount ; //use RCOUNT_
10412 + u32 rcompare ; //use RCOMPARE_
10413 + u32 rtc ; //use RTC_
10414 +} volatile * TIM_t ;
10415 +
10416 +enum
10417 +{
10418 + CTC_en_b = 0,
10419 + CTC_en_m = 0x00000001,
10420 + CTC_to_b = 1,
10421 + CTC_to_m = 0x00000002,
10422 +
10423 + RCOUNT_count_b = 0,
10424 + RCOUNT_count_m = 0x0000ffff,
10425 + RCOMPARE_compare_b = 0,
10426 + RCOMPARE_compare_m = 0x0000ffff,
10427 + RTC_ce_b = 0,
10428 + RTC_ce_m = 0x00000001,
10429 + RTC_to_b = 1,
10430 + RTC_to_m = 0x00000002,
10431 + RTC_rqe_b = 2,
10432 + RTC_rqe_m = 0x00000004,
10433 +
10434 +} ;
10435 +#endif //__IDT_RC32438_TIM_H__
10436 +
10437 diff -Nur linux-2.6.15/include/asm-mips/mach-generic/irq.h linux-2.6.15-openwrt/include/asm-mips/mach-generic/irq.h
10438 --- linux-2.6.15/include/asm-mips/mach-generic/irq.h 2006-01-03 04:21:10.000000000 +0100
10439 +++ linux-2.6.15-openwrt/include/asm-mips/mach-generic/irq.h 2006-01-10 00:32:33.000000000 +0100
10440 @@ -8,6 +8,6 @@
10441 #ifndef __ASM_MACH_GENERIC_IRQ_H
10442 #define __ASM_MACH_GENERIC_IRQ_H
10443
10444 -#define NR_IRQS 128
10445 +#define NR_IRQS 256
10446
10447 #endif /* __ASM_MACH_GENERIC_IRQ_H */
10448 diff -Nur linux-2.6.15/include/linux/init.h linux-2.6.15-openwrt/include/linux/init.h
10449 --- linux-2.6.15/include/linux/init.h 2006-01-03 04:21:10.000000000 +0100
10450 +++ linux-2.6.15-openwrt/include/linux/init.h 2006-01-10 00:32:33.000000000 +0100
10451 @@ -86,6 +86,8 @@
10452 static initcall_t __initcall_##fn __attribute_used__ \
10453 __attribute__((__section__(".initcall" level ".init"))) = fn
10454
10455 +#define early_initcall(fn) __define_initcall(".early1",fn)
10456 +
10457 #define core_initcall(fn) __define_initcall("1",fn)
10458 #define postcore_initcall(fn) __define_initcall("2",fn)
10459 #define arch_initcall(fn) __define_initcall("3",fn)
10460 diff -Nur linux-2.6.15/include/linux/kernel.h linux-2.6.15-openwrt/include/linux/kernel.h
10461 --- linux-2.6.15/include/linux/kernel.h 2006-01-03 04:21:10.000000000 +0100
10462 +++ linux-2.6.15-openwrt/include/linux/kernel.h 2006-01-10 00:32:33.000000000 +0100
10463 @@ -307,6 +307,7 @@
10464 };
10465
10466 /* Force a compilation error if condition is true */
10467 +extern void BUILD_BUG(void);
10468 #define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
10469
10470 #ifdef CONFIG_SYSCTL
10471 diff -Nur linux-2.6.15/Makefile linux-2.6.15-openwrt/Makefile
10472 --- linux-2.6.15/Makefile 2006-01-03 04:21:10.000000000 +0100
10473 +++ linux-2.6.15-openwrt/Makefile 2006-01-10 00:32:33.000000000 +0100
10474 @@ -166,10 +166,7 @@
10475 # then ARCH is assigned, getting whatever value it gets normally, and
10476 # SUBARCH is subsequently ignored.
10477
10478 -SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \
10479 - -e s/arm.*/arm/ -e s/sa110/arm/ \
10480 - -e s/s390x/s390/ -e s/parisc64/parisc/ \
10481 - -e s/ppc64/powerpc/ )
10482 +SUBARCH := mips
10483
10484 # Cross compiling and selecting different set of gcc/bin-utils
10485 # ---------------------------------------------------------------------------
10486 diff -Nur linux-2.6.15/drivers/net/natsemi.c linux-2.6.15-openwrt/drivers/net/natsemi.c
10487 --- linux-2.6.15/drivers/net/natsemi.c 2006-01-02 19:21:10.000000000 -0800
10488 +++ linux-2.6.15-openwrt/drivers/net/natsemi.c 2006-01-10 07:29:49.581994000 -0800
10489 @@ -771,6 +771,49 @@
10490 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
10491 static struct ethtool_ops ethtool_ops;
10492
10493 +#ifdef CONFIG_MACH_ARUBA
10494 +
10495 +#include <linux/ctype.h>
10496 +
10497 +#ifndef ERR
10498 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
10499 +#endif
10500 +
10501 +static int parse_mac_addr(struct net_device *dev, char* macstr)
10502 +{
10503 + int i, j;
10504 + unsigned char result, value;
10505 +
10506 + for (i=0; i<6; i++) {
10507 + result = 0;
10508 + if (i != 5 && *(macstr+2) != ':') {
10509 + ERR("invalid mac address format: %d %c\n",
10510 + i, *(macstr+2));
10511 + return -EINVAL;
10512 + }
10513 + for (j=0; j<2; j++) {
10514 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
10515 + toupper(*macstr)-'A'+10) < 16) {
10516 + result = result*16 + value;
10517 + macstr++;
10518 + }
10519 + else {
10520 + ERR("invalid mac address "
10521 + "character: %c\n", *macstr);
10522 + return -EINVAL;
10523 + }
10524 + }
10525 +
10526 + macstr++;
10527 + dev->dev_addr[i] = result;
10528 + }
10529 +
10530 + dev->dev_addr[5]++;
10531 + return 0;
10532 +}
10533 +
10534 +#endif
10535 +
10536 static inline void __iomem *ns_ioaddr(struct net_device *dev)
10537 {
10538 return (void __iomem *) dev->base_addr;
10539 @@ -859,6 +902,7 @@
10540 goto err_ioremap;
10541 }
10542
10543 +#ifndef CONFIG_MACH_ARUBA
10544 /* Work around the dropped serial bit. */
10545 prev_eedata = eeprom_read(ioaddr, 6);
10546 for (i = 0; i < 3; i++) {
10547 @@ -867,6 +911,19 @@
10548 dev->dev_addr[i*2+1] = eedata >> 7;
10549 prev_eedata = eedata;
10550 }
10551 +#else
10552 + {
10553 + char mac[32];
10554 + unsigned char def_mac[6] = {00, 0x0b, 0x86, 0xba, 0xdb, 0xad};
10555 + extern char *getenv(char *e);
10556 + memset(mac, 0, 32);
10557 + memcpy(mac, getenv("ethaddr"), 17);
10558 + if (parse_mac_addr(dev, mac)){
10559 + printk("%s: MAC address not found\n", __func__);
10560 + memcpy(dev->dev_addr, def_mac, 6);
10561 + }
10562 + }
10563 +#endif
10564
10565 dev->base_addr = (unsigned long __force) ioaddr;
10566 dev->irq = irq;
10567 diff -Nur linux-2.6.15/drivers/net/Makefile linux-2.6.15-openwrt/drivers/net/Makefile
10568 --- linux-2.6.15/drivers/net/Makefile 2006-01-13 09:19:55.000000000 -0800
10569 +++ linux-2.6.15-openwrt/drivers/net/Makefile 2006-01-09 20:44:10.378339000 -0800
10570 @@ -35,6 +35,7 @@
10571
10572 obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
10573
10574 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
10575 obj-$(CONFIG_DGRS) += dgrs.o
10576 obj-$(CONFIG_VORTEX) += 3c59x.o
10577 obj-$(CONFIG_TYPHOON) += typhoon.o
10578 @@ -190,7 +189,6 @@
10579 obj-$(CONFIG_SMC91X) += smc91x.o
10580 obj-$(CONFIG_DM9000) += dm9000.o
10581 obj-$(CONFIG_FEC_8XX) += fec_8xx/
10582 -obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
10583
10584 obj-$(CONFIG_ARM) += arm/
10585 obj-$(CONFIG_DEV_APPLETALK) += appletalk/
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