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[ar71xx] move device registration function prototypes into a separate header file
[openwrt.git] / target / linux / storm / patches / 007-mtd.patch
1 --- a/drivers/mtd/chips/Kconfig
2 +++ b/drivers/mtd/chips/Kconfig
3 @@ -220,6 +220,13 @@ config MTD_ROM
4 This option enables basic support for ROM chips accessed through
5 a bus mapping driver.
6
7 +config MTD_SERIAL
8 + tristate "Support for Serial chips in bus mapping"
9 + depends on MTD
10 + help
11 + This option enables basic support for Serial chips accessed through
12 + a bus mapping driver.
13 +
14 config MTD_ABSENT
15 tristate "Support for absent chips in bus mapping"
16 help
17 --- a/drivers/mtd/chips/cfi_cmdset_0002.c
18 +++ b/drivers/mtd/chips/cfi_cmdset_0002.c
19 @@ -39,10 +39,15 @@
20 #include <linux/mtd/cfi.h>
21 #include <linux/mtd/xip.h>
22
23 +//****** Storlink SoC ******
24 #define AMD_BOOTLOC_BUG
25 -#define FORCE_WORD_WRITE 0
26 -
27 -#define MAX_WORD_RETRIES 3
28 +//#define FORCE_WORD_WRITE 0
29 +#define FORCE_WORD_WRITE 1
30 +#define FORCE_FAST_PROG 0
31 +
32 +//#define MAX_WORD_RETRIES 3
33 +#define MAX_WORD_RETRIES 3 // CONFIG_MTD_CFI_AMDSTD_RETRY
34 +//**************************
35
36 #define MANUFACTURER_AMD 0x0001
37 #define MANUFACTURER_ATMEL 0x001F
38 @@ -322,6 +327,13 @@ struct mtd_info *cfi_cmdset_0002(struct
39 #endif
40
41 bootloc = extp->TopBottom;
42 +//****** Storlink SoC ******
43 + if(bootloc == 5)
44 + {
45 + bootloc = 3;
46 + extp->TopBottom = 3;
47 + }
48 +//**************************
49 if ((bootloc != 2) && (bootloc != 3)) {
50 printk(KERN_WARNING "%s: CFI does not contain boot "
51 "bank location. Assuming top.\n", map->name);
52 @@ -340,6 +352,9 @@ struct mtd_info *cfi_cmdset_0002(struct
53 cfi->cfiq->EraseRegionInfo[j] = swap;
54 }
55 }
56 +#ifdef CONFIG_MTD_MAP_BANK_WIDTH_1
57 + cfi->device_type = CFI_DEVICETYPE_X8;
58 +#endif
59 /* Set the default CFI lock/unlock addresses */
60 cfi->addr_unlock1 = 0x555;
61 cfi->addr_unlock2 = 0x2aa;
62 @@ -461,6 +476,7 @@ static int __xipram chip_ready(struct ma
63 map_word d, t;
64
65 d = map_read(map, addr);
66 + udelay(20); //Storlink SoC
67 t = map_read(map, addr);
68
69 return map_word_equal(map, d, t);
70 @@ -626,7 +642,9 @@ static void put_chip(struct map_info *ma
71 default:
72 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
73 }
74 +//****** Storlink SoC ******
75 wake_up(&chip->wq);
76 +//**************************
77 }
78
79 #ifdef CONFIG_MTD_XIP
80 @@ -940,7 +958,9 @@ static inline int do_read_secsi_onechip(
81 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
82 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
83
84 +//****** Storlink SoC ******
85 wake_up(&chip->wq);
86 +//**************************
87 spin_unlock(chip->mutex);
88
89 return 0;
90 @@ -1005,7 +1025,10 @@ static int __xipram do_write_oneword(str
91 */
92 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
93 int ret = 0;
94 - map_word oldd;
95 +//****** Storlink SoC ******
96 +// map_word oldd;
97 + map_word oldd, tmp;
98 +//**************************
99 int retry_cnt = 0;
100
101 adr += chip->start;
102 @@ -1037,9 +1060,15 @@ static int __xipram do_write_oneword(str
103 ENABLE_VPP(map);
104 xip_disable(map, chip, adr);
105 retry:
106 +//****** Storlink SoC ******
107 +#if FORCE_FAST_PROG /* Unlock bypass */
108 + cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
109 +#else
110 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
111 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
112 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
113 +#endif
114 +//**************************
115 map_write(map, datum, adr);
116 chip->state = FL_WRITING;
117
118 @@ -1072,7 +1101,13 @@ static int __xipram do_write_oneword(str
119 }
120
121 if (chip_ready(map, adr))
122 - break;
123 + {
124 + tmp = map_read(map, adr);
125 + if(map_word_equal(map, tmp, datum))
126 +// goto op_done;
127 + break;
128 +
129 + }
130
131 /* Latency issues. Drop the lock, wait a while and retry */
132 UDELAY(map, chip, adr, 1);
133 @@ -1084,8 +1119,17 @@ static int __xipram do_write_oneword(str
134 /* FIXME - should have reset delay before continuing */
135
136 if (++retry_cnt <= MAX_WORD_RETRIES)
137 + {
138 +//****** Storlink SoC ******
139 +#if FORCE_FAST_PROG
140 + cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
141 + cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
142 + cfi_send_gen_cmd(0x20, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
143 + //udelay(1);
144 +#endif
145 + udelay(1);
146 goto retry;
147 -
148 + }
149 ret = -EIO;
150 }
151 xip_enable(map, chip, adr);
152 @@ -1171,7 +1215,14 @@ static int cfi_amdstd_write_words(struct
153 return 0;
154 }
155 }
156 -
157 +//****** Storlink SoC ******
158 + map_write( map, CMD(0xF0), chipstart );
159 +#if FORCE_FAST_PROG
160 + cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
161 + cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chipstart, map, cfi, cfi->device_type, NULL);
162 + cfi_send_gen_cmd(0x20, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
163 +#endif
164 +//**************************
165 /* We are now aligned, write as much as possible */
166 while(len >= map_bankwidth(map)) {
167 map_word datum;
168 @@ -1181,7 +1232,15 @@ static int cfi_amdstd_write_words(struct
169 ret = do_write_oneword(map, &cfi->chips[chipnum],
170 ofs, datum);
171 if (ret)
172 + {
173 +//****** Storlink SoC ******
174 +#if FORCE_FAST_PROG
175 + /* Get out of unlock bypass mode */
176 + cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
177 + cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
178 +#endif
179 return ret;
180 + }
181
182 ofs += map_bankwidth(map);
183 buf += map_bankwidth(map);
184 @@ -1189,19 +1248,38 @@ static int cfi_amdstd_write_words(struct
185 len -= map_bankwidth(map);
186
187 if (ofs >> cfi->chipshift) {
188 +//****** Storlink SoC ******
189 +#if FORCE_FAST_PROG
190 + /* Get out of unlock bypass mode */
191 + cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
192 + cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
193 +#endif
194 chipnum ++;
195 ofs = 0;
196 if (chipnum == cfi->numchips)
197 return 0;
198 chipstart = cfi->chips[chipnum].start;
199 +#if FORCE_FAST_PROG
200 + /* Go into unlock bypass mode for next set of chips */
201 + cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
202 + cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chipstart, map, cfi, cfi->device_type, NULL);
203 + cfi_send_gen_cmd(0x20, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
204 +#endif
205 }
206 }
207
208 +#if FORCE_FAST_PROG
209 + /* Get out of unlock bypass mode */
210 + cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
211 + cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
212 +#endif
213 +
214 /* Write the trailing bytes if any */
215 if (len & (map_bankwidth(map)-1)) {
216 map_word tmp_buf;
217
218 retry1:
219 +
220 spin_lock(cfi->chips[chipnum].mutex);
221
222 if (cfi->chips[chipnum].state != FL_READY) {
223 @@ -1221,7 +1299,11 @@ static int cfi_amdstd_write_words(struct
224 #endif
225 goto retry1;
226 }
227 -
228 +#if FORCE_FAST_PROG
229 + cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
230 + cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chipstart, map, cfi, cfi->device_type, NULL);
231 + cfi_send_gen_cmd(0x20, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
232 +#endif
233 tmp_buf = map_read(map, ofs + chipstart);
234
235 spin_unlock(cfi->chips[chipnum].mutex);
236 @@ -1231,11 +1313,23 @@ static int cfi_amdstd_write_words(struct
237 ret = do_write_oneword(map, &cfi->chips[chipnum],
238 ofs, tmp_buf);
239 if (ret)
240 + {
241 +#if FORCE_FAST_PROG
242 + /* Get out of unlock bypass mode */
243 + cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
244 + cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
245 +#endif
246 return ret;
247 -
248 + }
249 +#if FORCE_FAST_PROG
250 + /* Get out of unlock bypass mode */
251 + cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
252 + cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
253 +#endif
254 (*retlen) += len;
255 }
256
257 + map_write( map, CMD(0xF0), chipstart );
258 return 0;
259 }
260
261 @@ -1275,6 +1369,7 @@ static int __xipram do_write_buffer(stru
262 ENABLE_VPP(map);
263 xip_disable(map, chip, cmd_adr);
264
265 + map_write( map, CMD(0xF0), chip->start ); //Storlink
266 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
267 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
268 //cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
269 @@ -1535,6 +1630,9 @@ static int __xipram do_erase_oneblock(st
270 DECLARE_WAITQUEUE(wait, current);
271 int ret = 0;
272
273 +#ifdef CONFIG_SL2312_SHARE_PIN
274 + mtd_lock(); // sl2312 share pin lock
275 +#endif
276 adr += chip->start;
277
278 spin_lock(chip->mutex);
279 @@ -1613,6 +1711,9 @@ static int __xipram do_erase_oneblock(st
280 chip->state = FL_READY;
281 put_chip(map, chip, adr);
282 spin_unlock(chip->mutex);
283 +#ifdef CONFIG_SL2312_SHARE_PIN
284 + mtd_unlock(); // sl2312 share pin lock
285 +#endif
286 return ret;
287 }
288
289 --- /dev/null
290 +++ b/drivers/mtd/chips/map_serial.c
291 @@ -0,0 +1,188 @@
292 +/*
293 + * Common code to handle map devices which are simple ROM
294 + * (C) 2000 Red Hat. GPL'd.
295 + * $Id: map_serial.c,v 1.3 2006/06/05 02:34:54 middle Exp $
296 + */
297 +
298 +#include <linux/version.h>
299 +#include <linux/module.h>
300 +#include <linux/types.h>
301 +#include <linux/kernel.h>
302 +#include <asm/io.h>
303 +
304 +#include <asm/byteorder.h>
305 +#include <linux/errno.h>
306 +#include <linux/slab.h>
307 +
308 +#include <asm/hardware.h>
309 +#include <linux/mtd/map.h>
310 +#include <linux/mtd/mtd.h>
311 +#include <linux/init.h> //add
312 +#include <asm/arch/sl2312.h>
313 +#include <asm/arch/flash.h>
314 +
315 +static int mapserial_erase(struct mtd_info *mtd, struct erase_info *instr);
316 +static int mapserial_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
317 +static int mapserial_write (struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
318 +static void mapserial_nop (struct mtd_info *);
319 +struct mtd_info *map_serial_probe(struct map_info *map);
320 +
321 +extern int m25p80_sector_erase(__u32 address, __u32 schip_en);
322 +
323 +static struct mtd_chip_driver mapserial_chipdrv = {
324 + probe: map_serial_probe,
325 + name: "map_serial",
326 + module: THIS_MODULE
327 +};
328 +
329 +struct mtd_info *map_serial_probe(struct map_info *map)
330 +{
331 + struct mtd_info *mtd;
332 +
333 + mtd = kmalloc(sizeof(*mtd), GFP_KERNEL);
334 + if (!mtd)
335 + return NULL;
336 +
337 + memset(mtd, 0, sizeof(*mtd));
338 +
339 + map->fldrv = &mapserial_chipdrv;
340 + mtd->priv = map;
341 + mtd->name = map->name;
342 + mtd->type = MTD_OTHER;
343 + mtd->erase = mapserial_erase;
344 + mtd->size = map->size;
345 + mtd->read = mapserial_read;
346 + mtd->write = mapserial_write;
347 + mtd->sync = mapserial_nop;
348 + mtd->flags = (MTD_WRITEABLE|MTD_ERASEABLE);
349 +// mtd->erasesize = 512; // page size;
350 +#ifdef CONFIG_MTD_SL2312_SERIAL_ST
351 + mtd->erasesize = M25P80_SECTOR_SIZE; // block size;
352 +#else
353 + mtd->erasesize = 0x1000; // block size;
354 +#endif
355 +
356 + __module_get(THIS_MODULE);
357 + //MOD_INC_USE_COUNT;
358 + return mtd;
359 +}
360 +
361 +#define FLASH_ACCESS_OFFSET 0x00000010
362 +#define FLASH_ADDRESS_OFFSET 0x00000014
363 +#define FLASH_WRITE_DATA_OFFSET 0x00000018
364 +#define FLASH_READ_DATA_OFFSET 0x00000018
365 +
366 +static __u32 readflash_ctrl_reg(__u32 ofs)
367 +{
368 + __u32 *base;
369 +
370 + base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
371 + return __raw_readl(base);
372 +}
373 +
374 +static void writeflash_ctrl_reg(__u32 data, __u32 ofs)
375 +{
376 + __u32 *base;
377 +
378 + base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
379 + __raw_writel(data, base);
380 +}
381 +
382 +static int mapserial_erase_block(struct map_info *map,unsigned int block)
383 +{
384 +
385 + __u32 address;
386 +#ifdef CONFIG_MTD_SL2312_SERIAL_ST
387 +
388 + if(!m25p80_sector_erase(block, 0))
389 + return (MTD_ERASE_DONE);
390 +#else
391 + __u32 opcode;
392 + __u32 count=0;
393 +// __u8 status;
394 +
395 + // printk("mapserial_erase_block : erase block %d \n",block);
396 +// opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | cmd;
397 + opcode = 0x80000000 | 0x0200 | 0x50;
398 + address = (block << 13);
399 + writeflash_ctrl_reg(address,FLASH_ADDRESS_OFFSET);
400 + writeflash_ctrl_reg(opcode,FLASH_ACCESS_OFFSET);
401 + opcode=readflash_ctrl_reg(FLASH_ACCESS_OFFSET);
402 + while(opcode&0x80000000)
403 + {
404 + opcode = readflash_ctrl_reg(FLASH_ACCESS_OFFSET);
405 + count++;
406 + if (count > 10000)
407 + {
408 + return (MTD_ERASE_FAILED);
409 + }
410 + }
411 + return (MTD_ERASE_DONE);
412 +#endif
413 +}
414 +
415 +static int mapserial_erase(struct mtd_info *mtd, struct erase_info *instr)
416 +{
417 + struct map_info *map = (struct map_info *)mtd->priv;
418 + unsigned int addr;
419 + int len;
420 + unsigned int block;
421 + unsigned int ret=0;
422 +
423 + addr = instr->addr;
424 + len = instr->len;
425 + while (len > 0)
426 + {
427 + block = addr / mtd->erasesize;
428 +#ifdef CONFIG_MTD_SL2312_SERIAL_ST
429 + ret = mapserial_erase_block(map,addr);
430 +#else
431 + ret = mapserial_erase_block(map,block);
432 +#endif
433 + addr = addr + mtd->erasesize;
434 + len = len - mtd->erasesize;
435 + }
436 + return (ret);
437 +}
438 +
439 +static int mapserial_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
440 +{
441 + struct map_info *map = (struct map_info *)mtd->priv;
442 +// printk("mapserial_read : \n");
443 + map->copy_from(map, buf, from, len);
444 + *retlen = len;
445 + return 0;
446 +}
447 +
448 +static void mapserial_nop(struct mtd_info *mtd)
449 +{
450 + /* Nothing to see here */
451 +}
452 +
453 +static int mapserial_write (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf)
454 +{
455 + struct map_info *map = (struct map_info *)mtd->priv;
456 +// printk("mapserial_write : buf %x to %x len %x \n",(int)buf, (int)to, (int)len);
457 + //map->copy_to(map, buf, to, len);
458 + map->copy_to(map, to, buf, len);
459 + *retlen = len;
460 + return 0;
461 +}
462 +
463 +int __init map_serial_init(void)
464 +{
465 + register_mtd_chip_driver(&mapserial_chipdrv);
466 + return 0;
467 +}
468 +
469 +static void __exit map_serial_exit(void)
470 +{
471 + unregister_mtd_chip_driver(&mapserial_chipdrv);
472 +}
473 +
474 +module_init(map_serial_init);
475 +module_exit(map_serial_exit);
476 +
477 +MODULE_LICENSE("GPL");
478 +MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
479 +MODULE_DESCRIPTION("MTD chip driver for ROM chips");
480 --- a/drivers/mtd/maps/Kconfig
481 +++ b/drivers/mtd/maps/Kconfig
482 @@ -614,5 +614,30 @@ config MTD_PLATRAM
483
484 This selection automatically selects the map_ram driver.
485
486 +#***************************************************************************************
487 +# Storlink parallel/Serial Flash configuration
488 +#***************************************************************************************
489 +config MTD_SL2312_CFI
490 + tristate "CFI Flash device mapped on SL2312"
491 + depends on MTD_CFI
492 + help
493 + Map driver for SL2312 demo board.
494 +
495 +config MTD_SL2312_SERIAL_ATMEL
496 + tristate "ATMEL Serial Flash device mapped on SL2312"
497 + depends on MTD_PARTITIONS && ARCH_SL2312
498 + help
499 + Map driver for SL2312 demo board.
500 +
501 +config MTD_SL2312_SERIAL_ST
502 + tristate "ST Serial Flash device mapped on SL2312"
503 + depends on MTD_PARTITIONS && ARCH_SL2312
504 + help
505 + Map driver for SL2312 demo board.
506 +
507 +config SL2312_SHARE_PIN
508 + tristate "Parallel Flash share pin on SL2312 ASIC"
509 + depends on SL3516_ASIC
510 +
511 endmenu
512
513 --- /dev/null
514 +++ b/drivers/mtd/maps/sl2312-flash-atmel.c
515 @@ -0,0 +1,554 @@
516 +/*
517 + * $Id: sl2312-flash-atmel.c,v 1.2 2006/06/05 02:35:57 middle Exp $
518 + *
519 + * Flash and EPROM on Hitachi Solution Engine and similar boards.
520 + *
521 + * (C) 2001 Red Hat, Inc.
522 + *
523 + * GPL'd
524 + */
525 +
526 +#include <linux/module.h>
527 +#include <linux/types.h>
528 +#include <linux/kernel.h>
529 +
530 +#include <asm/io.h>
531 +#include <linux/mtd/mtd.h>
532 +#include <linux/mtd/map.h>
533 +#include <linux/mtd/partitions.h>
534 +#include <asm/hardware.h>
535 +
536 +#include <asm/arch/sl2312.h>
537 +#include <asm/arch/flash.h>
538 +#include <linux/init.h> //add
539 +
540 +
541 +#define g_page_addr AT45DB321_PAGE_SHIFT //321 : shift 10 ; 642 : shift 11
542 +#define g_chipen SERIAL_FLASH_CHIP0_EN //atmel
543 +
544 +extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partition **pparts);
545 +
546 +void address_to_page(__u32 address, __u16 *page, __u16 *offset)
547 +{
548 + *page = address / SPAGE_SIZE;
549 + *offset = address % SPAGE_SIZE;
550 +}
551 +
552 +static __u32 read_flash_ctrl_reg(__u32 ofs)
553 +{
554 + __u32 *base;
555 +
556 + base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
557 + return __raw_readl(base);
558 +}
559 +
560 +static void write_flash_ctrl_reg(__u32 ofs,__u32 data)
561 +{
562 + __u32 *base;
563 +
564 + base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
565 + __raw_writel(data, base);
566 +}
567 +
568 +void atmel_read_status(__u8 cmd, __u8 *data)
569 +{
570 + __u32 opcode;
571 + __u32 value;
572 +
573 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | cmd | g_chipen;
574 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
575 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
576 + while(opcode&0x80000000)
577 + {
578 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
579 + flash_delay();
580 + schedule();
581 + }
582 +
583 + value=read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
584 + *data = value & 0xff;
585 +}
586 +
587 +void main_memory_page_read(__u8 cmd, __u16 page, __u16 offset, __u8 *data)
588 +{
589 + __u32 opcode;
590 + __u32 address;
591 + __u32 value;
592 +
593 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS_4X_DATA | cmd | g_chipen;
594 + address = (page << g_page_addr) + offset;
595 + write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
596 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
597 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
598 + while(opcode&0x80000000)
599 + {
600 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
601 + flash_delay();
602 + schedule();
603 + }
604 +
605 + value=read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
606 + *data = value & 0xff;
607 +}
608 +
609 +void buffer_to_main_memory(__u8 cmd, __u16 page)
610 +{
611 + __u32 opcode;
612 + __u32 address;
613 + __u8 status;
614 +
615 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | cmd | g_chipen;
616 + address = (page << g_page_addr);
617 + write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
618 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
619 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
620 + while(opcode&0x80000000)
621 + {
622 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
623 + flash_delay();
624 + schedule();
625 + }
626 + atmel_read_status(READ_STATUS_SPI, &status);
627 + while(!(status&0x80))
628 + {
629 + atmel_read_status(READ_STATUS_SPI, &status);
630 + flash_delay();
631 + schedule();
632 + }
633 +
634 +}
635 +
636 +
637 +void atmel_flash_read_page(__u32 address, __u8 *buffer, __u32 len)
638 +{
639 + __u8 byte;
640 + __u16 page, offset;
641 + __u16 i;
642 +
643 + address_to_page(address, &page, &offset);
644 +
645 + for(i=0; i<len; i++,offset++)
646 + {
647 + main_memory_page_read(MAIN_MEMORY_PAGE_READ_SPI , page, offset, &byte);
648 + buffer [i]= byte;
649 + }
650 +}
651 +
652 +void atmel_flash_program_page(__u32 address, __u8 *buffer, __u32 len)
653 +{
654 + __u8 pattern;
655 + __u16 page, offset;
656 + __u32 i;
657 +
658 + address_to_page(address, &page, &offset);
659 + // printk("atmel_flash_program_page: offset %x len %x page %x \n", offset, len, page);
660 +
661 + if(offset)
662 + main_memory_to_buffer(MAIN_MEMORY_TO_BUFFER1,page);
663 +
664 + for(i=0; i<len; i++,offset++)
665 + {
666 + pattern = buffer[i];
667 + atmel_buffer_write(BUFFER1_WRITE,offset,pattern);
668 + }
669 +
670 + // printk("atmel_flash_program_page: offset %x \n", offset);
671 + buffer_to_main_memory(BUFFER1_TO_MAIN_MEMORY, page);
672 + // printk("atmel_flash_program_page: buffer_to_main_memory %x page\n", page);
673 +
674 +}
675 +
676 +
677 +void main_memory_to_buffer(__u8 cmd, __u16 page)
678 +{
679 + __u32 opcode;
680 + __u32 address;
681 + __u8 status;
682 +
683 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | cmd | g_chipen;
684 + address = (page << g_page_addr);
685 + write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
686 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
687 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
688 + while(opcode&0x80000000)
689 + {
690 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
691 + flash_delay();
692 + schedule();
693 + }
694 + atmel_read_status(READ_STATUS_SPI, &status);
695 + while(!(status&0x80))
696 + {
697 + atmel_read_status(READ_STATUS_SPI, &status);
698 + flash_delay();
699 + schedule();
700 + }
701 +
702 +}
703 +
704 +void main_memory_page_program(__u8 cmd, __u16 page, __u16 offset, __u8 data)
705 +{
706 + __u32 opcode;
707 + __u32 address;
708 + __u8 status;
709 +
710 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS_DATA | cmd | g_chipen;
711 + address = (page << g_page_addr) + offset;
712 + write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
713 + write_flash_ctrl_reg(FLASH_WRITE_DATA_OFFSET, data);
714 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
715 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
716 + while(opcode&0x80000000)
717 + {
718 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
719 + flash_delay();
720 + schedule();
721 + }
722 + atmel_read_status(READ_STATUS_SPI, &status);
723 + while(!(status&0x80))
724 + {
725 + atmel_read_status(READ_STATUS_SPI, &status);
726 + flash_delay();
727 + schedule();
728 + }
729 +}
730 +
731 +void atmel_buffer_write(__u8 cmd, __u16 offset, __u8 data)
732 +{
733 + __u32 opcode;
734 + __u32 address;
735 +
736 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS_DATA | cmd | g_chipen;
737 + address = offset;
738 + write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
739 + write_flash_ctrl_reg(FLASH_WRITE_DATA_OFFSET, data);
740 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
741 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
742 + while(opcode&0x80000000)
743 + {
744 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
745 + flash_delay();
746 + schedule();
747 + }
748 +
749 +}
750 +
751 +void atmel_erase_page(__u8 cmd, __u16 page)
752 +{
753 + __u32 opcode;
754 + __u32 address;
755 + __u8 status;
756 +
757 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | cmd | g_chipen;
758 + address = (page << g_page_addr);
759 + write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
760 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
761 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
762 + while(opcode&0x80000000)
763 + {
764 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
765 + flash_delay();
766 + schedule();
767 + }
768 + atmel_read_status(READ_STATUS_SPI, &status);
769 + while(!(status&0x80))
770 + {
771 + atmel_read_status(READ_STATUS_SPI, &status);
772 + flash_delay();
773 + schedule();
774 + }
775 +
776 +}
777 +
778 +void atmel_erase_block(__u8 cmd, __u16 block)
779 +{
780 + __u32 opcode;
781 + __u32 address;
782 + __u8 status;
783 +
784 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | cmd | g_chipen;
785 + address = (block << 13);
786 + write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
787 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
788 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
789 + while(opcode&0x80000000)
790 + {
791 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
792 + flash_delay();
793 + schedule();
794 + }
795 + atmel_read_status(READ_STATUS_SPI, &status);
796 + while(!(status&0x80))
797 + {
798 + atmel_read_status(READ_STATUS_SPI, &status);
799 + flash_delay();
800 + schedule();
801 + }
802 +
803 +}
804 +
805 +void flash_delay(void)
806 +{
807 + int i;
808 +
809 + for(i=0; i<50; i++)
810 + i=i;
811 +}
812 +
813 +
814 +
815 +
816 +__u32 sl2312_read32(struct map_info *map, unsigned long ofs)
817 +{
818 +
819 +#if 0
820 + __u16 page, offset;
821 + __u32 pattern;
822 + __u8 byte, i;
823 +
824 + pattern = 0;
825 + address_to_page(ofs, &page, &offset);
826 + for(i=0; i<4; i++, offset++)
827 + {
828 + pattern = pattern << 8;
829 + main_memory_page_read(MAIN_MEMORY_PAGE_READ_SPI , page, offset, &byte);
830 +//printk("sl2312_read32:: address = %08x data = %c \n",ofs,byte);
831 + pattern += byte;
832 + }
833 + return pattern;
834 +#else
835 + return read_flash_ctrl_reg(ofs);
836 +#endif
837 +
838 +}
839 +
840 +__u8 sl2312_read8(struct map_info *map, unsigned long ofs)
841 +{
842 + __u16 page, offset;
843 + __u8 byte;
844 +
845 + address_to_page(ofs, &page, &offset);
846 + main_memory_page_read(MAIN_MEMORY_PAGE_READ_SPI , page, offset, &byte);
847 + //printk("sl2312_read8:: address = %08x data = %c \n",ofs,byte);
848 + return byte;
849 +
850 +}
851 +
852 +void sl2312_write32(struct map_info *map, __u32 d, unsigned long ofs)
853 +{
854 +#if 0
855 + __u16 page, offset;
856 + __u8 byte, i;
857 +
858 + address_to_page(ofs, &page, &offset);
859 + for(i=0; i<4; i++, offset++)
860 + {
861 + byte = d & 0xff;
862 + main_memory_page_program(MAIN_MEMORY_PROGRAM_BUFFER1, page, offset, byte);
863 + d = d >> 8;
864 +//printk("sl2312_write32:: address = %08x data = %c \n",ofs,byte);
865 + }
866 +#else
867 + write_flash_ctrl_reg(ofs, d);
868 +#endif
869 +}
870 +
871 +void sl2312_write8(struct map_info *map, __u8 d, unsigned long ofs)
872 +{
873 + __u16 page, offset;
874 +
875 + address_to_page(ofs, &page, &offset);
876 + main_memory_page_program(MAIN_MEMORY_PROGRAM_BUFFER1, page, offset, d);
877 +//printk("sl2312_write8:: address = %08x data = %c \n",ofs,d);
878 +
879 +}
880 +
881 +void sl2312_copy_from(struct map_info *map, void *buf, unsigned long ofs, ssize_t len)
882 +{
883 + __u32 size;
884 + __u8 *buffer;
885 + __u32 length;//i, j,
886 +
887 + //printk("sl2312_copy_from:: address = %08x datalen = %d \n",ofs,len);
888 +
889 + length = len;
890 + buffer = (__u8 *)buf;
891 + while(len)
892 + {
893 + size = SPAGE_SIZE - (ofs%SPAGE_SIZE);
894 + if(size > len)
895 + size = len;
896 + atmel_flash_read_page(ofs, buffer, size);
897 + buffer+=size;
898 + ofs+=size;
899 + len -= size;
900 + }
901 +
902 +#if 0
903 + buffer = (__u8 *)buf;
904 + for(i=0; i<length; i+=16)
905 + {
906 + for(j=0; j<16; j++,buffer++)
907 + {
908 + if((i*16+j)<length)
909 + printk("%x ",(int)*buffer);
910 + }
911 + printk("\n");
912 + }
913 +
914 + printk("\n");
915 +#endif
916 +
917 +}
918 +
919 +
920 +void sl2312_copy_to(struct map_info *map, unsigned long ofs, void *buf, ssize_t len)
921 +{
922 + __u32 size;
923 + __u8 *buffer;
924 +
925 + buffer = (__u8 *)buf;
926 + //printk("sl2312_copy_to:offset %x len %x \n", ofs, len);
927 +// printk("sl2312_copy_to:buf is %x \n", (int)buf);
928 +
929 + while(len)
930 + {
931 + size = SPAGE_SIZE - (ofs%SPAGE_SIZE);
932 + if(size > len)
933 + size = len;
934 + atmel_flash_program_page(ofs, buffer, size);
935 + buffer+=size;
936 + ofs+=size;
937 + len-=size;
938 + }
939 +
940 +
941 +}
942 +
943 +
944 +static struct mtd_info *serial_mtd;
945 +
946 +static struct mtd_partition *parsed_parts;
947 +
948 +static struct map_info sl2312_serial_map = {
949 +// name: "SL2312 serial flash",
950 +// size: 4194304, //0x400000,
951 +// //buswidth: 4,
952 +// bankwidth: 4,
953 +// phys: SL2312_FLASH_BASE,
954 +//#ifdef CONFIG_MTD_COMPLEX_MAPPINGS
955 +// //read32: sl2312_read32,
956 +// //read8: sl2312_read8,
957 +// copy_from: sl2312_copy_from,
958 +// //write8: sl2312_write8,
959 +// //write32: sl2312_write32,
960 +// read: sl2312_read32,
961 +// write: sl2312_write32,
962 +// copy_to: sl2312_copy_to
963 +//#endif
964 + .name = "SL2312 serial flash",
965 + .size = 4194304, //0x400000,
966 + //buswidth: 4,
967 + .bankwidth = 4,
968 + .phys = SL2312_FLASH_BASE,
969 +#ifdef CONFIG_MTD_COMPLEX_MAPPINGS
970 + //read32: sl2312_read32,
971 + //read8: sl2312_read8,
972 + .copy_from = sl2312_copy_from,
973 + //write8: sl2312_write8,
974 + //write32: sl2312_write32,
975 + .read = sl2312_read32,
976 + .write = sl2312_write32,
977 + .copy_to = sl2312_copy_to
978 +#endif
979 +};
980 +
981 +
982 +
983 +static struct mtd_partition sl2312_partitions[] = {
984 +
985 +
986 + ///* boot code */
987 + //{ name: "bootloader", offset: 0x00000000, size: 0x20000, },
988 + ///* kernel image */
989 + //{ name: "kerel image", offset: 0x000020000, size: 0x2E0000 },
990 + ///* All else is writable (e.g. JFFS) */
991 + //{ name: "user data", offset: 0x00300000, size: 0x00100000, },
992 + /* boot code */
993 + { .name = "bootloader", .offset = 0x00000000, .size = 0x20000, },
994 + /* kernel image */
995 + { .name = "kerel image", .offset = 0x000020000, .size = 0xE0000 },
996 + /* All else is writable (e.g. JFFS) */
997 + { .name = "user data", .offset = 0x00100000, .size = 0x00300000, },
998 +
999 +
1000 +};
1001 +
1002 +
1003 +
1004 +static int __init init_sl2312_maps(void)
1005 +{
1006 + int nr_parts = 0;
1007 + struct mtd_partition *parts;
1008 +
1009 + serial_mtd = kmalloc(sizeof(struct mtd_info), GFP_KERNEL);
1010 + if (!serial_mtd)
1011 + return NULL;
1012 +
1013 + memset(serial_mtd, 0, sizeof(struct mtd_info));
1014 + //sl2312flash_map.virt = (unsigned long)ioremap(SL2312_FLASH_BASE, FLASH_SIZE);
1015 + //sl2312_serial_map.map_priv_1 = (unsigned long)ioremap(SL2312_FLASH_BASE, SFLASH_SIZE);//(unsigned long)FLASH_VBASE;
1016 + sl2312_serial_map.virt = (unsigned long)ioremap(SL2312_FLASH_BASE, SFLASH_SIZE);//(unsigned long)ioremap(FLASH_START, SFLASH_SIZE);
1017 + if (!sl2312_serial_map.virt) {
1018 + printk(" failed to ioremap \n");
1019 + return -EIO;
1020 + }
1021 + serial_mtd = do_map_probe("map_serial", &sl2312_serial_map);
1022 + if (serial_mtd) {
1023 + //serial_mtd->module = THIS_MODULE;
1024 + serial_mtd->owner = THIS_MODULE;
1025 +
1026 + }
1027 +
1028 +#ifdef CONFIG_MTD_REDBOOT_PARTS
1029 + nr_parts = parse_redboot_partitions(serial_mtd, &parsed_parts);
1030 + if (nr_parts > 0)
1031 + printk(KERN_NOTICE "Found RedBoot partition table.\n");
1032 + else if (nr_parts < 0)
1033 + printk(KERN_NOTICE "Error looking for RedBoot partitions.\n");
1034 +#else
1035 + parsed_parts = sl2312_partitions;
1036 + parts = sl2312_partitions;
1037 + nr_parts = sizeof(sl2312_partitions)/sizeof(*parts);
1038 + nr_parts = sizeof(sl2312_partitions)/sizeof(*parsed_parts);
1039 +#endif /* CONFIG_MTD_REDBOOT_PARTS */
1040 +
1041 + if (nr_parts > 0)
1042 + add_mtd_partitions(serial_mtd, parsed_parts, nr_parts);
1043 + else
1044 + add_mtd_device(serial_mtd);
1045 +
1046 + return 0;
1047 +}
1048 +
1049 +static void __exit cleanup_sl2312_maps(void)
1050 +{
1051 + if (parsed_parts)
1052 + del_mtd_partitions(serial_mtd);
1053 + else
1054 + del_mtd_device(serial_mtd);
1055 +
1056 + map_destroy(serial_mtd);
1057 +
1058 +
1059 +}
1060 +
1061 +module_init(init_sl2312_maps);
1062 +module_exit(cleanup_sl2312_maps);
1063 +
1064 +
1065 +
1066 +MODULE_LICENSE("GPL");
1067 +MODULE_AUTHOR("Plus Chen <plus@storlink.com.tw>");
1068 +MODULE_DESCRIPTION("MTD map driver for Storlink Sword boards");
1069 +
1070 --- /dev/null
1071 +++ b/drivers/mtd/maps/sl2312-flash-cfi.c
1072 @@ -0,0 +1,370 @@
1073 +/*======================================================================
1074 +
1075 + This program is free software; you can redistribute it and/or modify
1076 + it under the terms of the GNU General Public License as published by
1077 + the Free Software Foundation; either version 2 of the License, or
1078 + (at your option) any later version.
1079 +
1080 + This program is distributed in the hope that it will be useful,
1081 + but WITHOUT ANY WARRANTY; without even the implied warranty of
1082 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1083 + GNU General Public License for more details.
1084 +
1085 + You should have received a copy of the GNU General Public License
1086 + along with this program; if not, write to the Free Software
1087 + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1088 +======================================================================*/
1089 +
1090 +#include <linux/module.h>
1091 +#include <linux/types.h>
1092 +#include <linux/kernel.h>
1093 +#include <linux/slab.h>
1094 +#include <linux/ioport.h>
1095 +#include <linux/init.h>
1096 +#include <linux/string.h>
1097 +
1098 +#include <linux/mtd/mtd.h>
1099 +#include <linux/mtd/map.h>
1100 +#include <linux/mtd/partitions.h>
1101 +
1102 +#include <asm/hardware.h>
1103 +#include <asm/io.h>
1104 +#include <asm/system.h>
1105 +#include <asm/arch/sl2312.h>
1106 +#include <linux/mtd/kvctl.h>
1107 +#include "sl2312_flashmap.h"
1108 +
1109 +
1110 +//extern int parse_afs_partitions(struct mtd_info *, struct mtd_partition **);
1111 +
1112 +/* the base address of FLASH control register */
1113 +#define FLASH_CONTROL_BASE_ADDR (IO_ADDRESS(SL2312_FLASH_CTRL_BASE))
1114 +#define SL2312_GLOBAL_BASE_ADDR (IO_ADDRESS(SL2312_GLOBAL_BASE))
1115 +
1116 +/* define read/write register utility */
1117 +#define FLASH_READ_REG(offset) (__raw_readl(offset+FLASH_CONTROL_BASE_ADDR))
1118 +#define FLASH_WRITE_REG(offset,val) (__raw_writel(val,offset+FLASH_CONTROL_BASE_ADDR))
1119 +
1120 +/* the offset of FLASH control register */
1121 +enum EMAC_REGISTER {
1122 + FLASH_ID = 0x0000,
1123 + FLASH_STATUS = 0x0008,
1124 + FLASH_TYPE = 0x000c,
1125 + FLASH_ACCESS = 0x0020,
1126 + FLASH_ADDRESS = 0x0024,
1127 + FLASH_DATA = 0x0028,
1128 + FLASH_TIMING = 0x002c,
1129 +};
1130 +
1131 +//#define FLASH_BASE FLASH_CONTROL_BASE_ADDR
1132 +//#define FLASH_SIZE 0x00800000 //INTEGRATOR_FLASH_SIZE
1133 +
1134 +//#define FLASH_PART_SIZE 8388608
1135 +
1136 +static unsigned int flash_indirect_access = 0;
1137 +
1138 +#ifdef CONFIG_SL2312_SHARE_PIN
1139 +static unsigned int chip_en = 0x00000000;
1140 +
1141 +void sl2312flash_enable_parallel_flash(void)
1142 +{
1143 + unsigned int reg_val;
1144 +
1145 + reg_val = readl(SL2312_GLOBAL_BASE_ADDR + 0x30);
1146 + reg_val = reg_val & 0xfffffffd;
1147 + writel(reg_val,SL2312_GLOBAL_BASE_ADDR + 0x30);
1148 + return;
1149 +}
1150 +
1151 +void sl2312flash_disable_parallel_flash(void)
1152 +{
1153 + unsigned int reg_val;
1154 +
1155 + reg_val = readl(SL2312_GLOBAL_BASE_ADDR + 0x30);
1156 + reg_val = reg_val | 0x00000002;
1157 + writel(reg_val,SL2312_GLOBAL_BASE_ADDR + 0x30);
1158 + return;
1159 +}
1160 +#endif
1161 +
1162 +
1163 +static struct map_info sl2312flash_map =
1164 +{
1165 + name: "SL2312 CFI Flash",
1166 + size: FLASH_SIZE,
1167 + bankwidth: 2,
1168 + //bankwidth: 1, //for 8 bits width
1169 + phys: SL2312_FLASH_BASE,
1170 +};
1171 +
1172 +static struct mtd_info *mtd;
1173 +#if 0
1174 +static struct mtd_partition sl2312_partitions[] = {
1175 + /* boot code */
1176 + {
1177 + name: "bootloader",
1178 + offset: 0x00000000,
1179 + size: 0x20000,
1180 +// mask_flags: MTD_WRITEABLE,
1181 + },
1182 + /* kernel image */
1183 + {
1184 + name: "kerel image",
1185 + offset: 0x00020000,
1186 + size: 0x2E0000
1187 + },
1188 + /* All else is writable (e.g. JFFS) */
1189 + {
1190 + name: "user data",
1191 + offset: 0x00300000,
1192 + size: 0x00100000,
1193 + }
1194 +};
1195 +#endif
1196 +
1197 +
1198 +
1199 +static int __init sl2312flash_init(void)
1200 +{
1201 + struct mtd_partition *parts;
1202 + int nr_parts = 0;
1203 + int ret;
1204 +#ifndef CONFIG_SL2312_SHARE_PIN
1205 + unsigned int reg_val;
1206 +#endif
1207 +
1208 + printk("SL2312 MTD Driver Init.......\n");
1209 +
1210 +#ifndef CONFIG_SL2312_SHARE_PIN
1211 + /* enable flash */
1212 + reg_val = readl(SL2312_GLOBAL_BASE_ADDR + 0x30);
1213 + reg_val = reg_val & 0xfffffffd;
1214 + writel(reg_val,SL2312_GLOBAL_BASE_ADDR + 0x30);
1215 +#else
1216 + sl2312flash_enable_parallel_flash(); /* enable Parallel FLASH */
1217 +#endif
1218 + FLASH_WRITE_REG(FLASH_ACCESS,0x00004000); /* parallel flash direct access mode */
1219 + ret = FLASH_READ_REG(FLASH_ACCESS);
1220 + if (ret == 0x00004000)
1221 + {
1222 + flash_indirect_access = 0; /* parallel flash direct access */
1223 + }
1224 + else
1225 + {
1226 + flash_indirect_access = 1; /* parallel flash indirect access */
1227 + }
1228 +
1229 + /*
1230 + * Also, the CFI layer automatically works out what size
1231 + * of chips we have, and does the necessary identification
1232 + * for us automatically.
1233 + */
1234 +#ifdef CONFIG_GEMINI_IPI
1235 + sl2312flash_map.virt = FLASH_VBASE;//(unsigned int *)ioremap(SL2312_FLASH_BASE, FLASH_SIZE);
1236 +#else
1237 + sl2312flash_map.virt = (unsigned int *)ioremap(SL2312_FLASH_BASE, FLASH_SIZE);
1238 +#endif
1239 + //printk("sl2312flash_map.virt = %08x\n",(unsigned int)sl2312flash_map.virt);
1240 +
1241 +// simple_map_init(&sl2312flash_map);
1242 +
1243 + mtd = do_map_probe("cfi_probe", &sl2312flash_map);
1244 + if (!mtd)
1245 + {
1246 +#ifdef CONFIG_SL2312_SHARE_PIN
1247 + sl2312flash_disable_parallel_flash(); /* disable Parallel FLASH */
1248 +#endif
1249 + return -ENXIO;
1250 + }
1251 + mtd->owner = THIS_MODULE;
1252 +// mtd->erase = flash_erase;
1253 +// mtd->read = flash_read;
1254 +// mtd->write = flash_write;
1255 +
1256 + parts = sl2312_partitions;
1257 + nr_parts = sizeof(sl2312_partitions)/sizeof(*parts);
1258 + ret = add_mtd_partitions(mtd, parts, nr_parts);
1259 + /*If we got an error, free all resources.*/
1260 + if (ret < 0) {
1261 + del_mtd_partitions(mtd);
1262 + map_destroy(mtd);
1263 + }
1264 +#ifdef CONFIG_SL2312_SHARE_PIN
1265 + sl2312flash_disable_parallel_flash(); /* disable Parallel FLASH */
1266 +#endif
1267 + printk("SL2312 MTD Driver Init Success ......\n");
1268 + return ret;
1269 +}
1270 +
1271 +static void __exit sl2312flash_exit(void)
1272 +{
1273 + if (mtd) {
1274 + del_mtd_partitions(mtd);
1275 + map_destroy(mtd);
1276 + }
1277 +
1278 + if (sl2312flash_map.virt) {
1279 + iounmap((void *)sl2312flash_map.virt);
1280 + sl2312flash_map.virt = 0;
1281 + }
1282 +}
1283 +
1284 +char chrtohex(char c)
1285 +{
1286 + char val;
1287 + if ((c >= '0') && (c <= '9'))
1288 + {
1289 + val = c - '0';
1290 + return val;
1291 + }
1292 + else if ((c >= 'a') && (c <= 'f'))
1293 + {
1294 + val = 10 + (c - 'a');
1295 + return val;
1296 + }
1297 + else if ((c >= 'A') && (c <= 'F'))
1298 + {
1299 + val = 10 + (c - 'A');
1300 + return val;
1301 + }
1302 + printk("<1>Error number\n");
1303 + return 0;
1304 +}
1305 +
1306 +
1307 +int get_vlaninfo(vlaninfo* vlan)
1308 +{
1309 + vctl_mheader head;
1310 + vctl_entry entry;
1311 + struct mtd_info *mymtd=NULL;
1312 + int i, j, loc = 0;
1313 + char *payload=0, *tmp1, *tmp2, tmp3[9];
1314 + size_t retlen;
1315 +
1316 + #ifdef CONFIG_SL2312_SHARE_PIN
1317 + sl2312flash_enable_parallel_flash();
1318 + #endif
1319 + for(i=0;i<MAX_MTD_DEVICES;i++)
1320 + {
1321 + mymtd=get_mtd_device(NULL,i);
1322 + // printk("mymtd->name: %s\n", mymtd->name);
1323 + if(mymtd && !strcmp(mymtd->name,"VCTL"))
1324 + {
1325 + // printk("%s\n", mymtd->name);
1326 + break;
1327 + }
1328 + }
1329 + if( i >= MAX_MTD_DEVICES)
1330 + {
1331 + printk("Can't find version control\n");
1332 + #ifdef CONFIG_SL2312_SHARE_PIN
1333 + sl2312flash_disable_parallel_flash();
1334 + #endif
1335 + return 0;
1336 + }
1337 +
1338 + if (!mymtd | !mymtd->read)
1339 + {
1340 + printk("<1>Can't read Version Configuration\n");
1341 + #ifdef CONFIG_SL2312_SHARE_PIN
1342 + sl2312flash_disable_parallel_flash();
1343 + #endif
1344 + return 0;
1345 + }
1346 +
1347 + mymtd->read(mymtd, 0, VCTL_HEAD_SIZE, &retlen, (u_char*)&head);
1348 + // printk("entry header: %c%c%c%c\n", head.header[0], head.header[1], head.header[2], head.header[3]);
1349 + // printk("entry number: %x\n", head.entry_num);
1350 + if ( strncmp(head.header, "FLFM", 4) )
1351 + {
1352 + printk("VCTL is a erase block\n");
1353 + #ifdef CONFIG_SL2312_SHARE_PIN
1354 + sl2312flash_disable_parallel_flash();
1355 + #endif
1356 + return 0;
1357 + }
1358 + loc += retlen;
1359 + for (i = 0; i < head.entry_num; i++)
1360 + {
1361 + mymtd->read(mymtd, loc, VCTL_ENTRY_LEN, &retlen, (u_char*)&entry);
1362 + // printk("type: %x\n", entry.type);
1363 + // printk("size: %x\n", entry.size);
1364 + strncpy(tmp3, entry.header, 4);
1365 + if (entry.type == VCT_VLAN)
1366 + {
1367 + for (j = 0; j < 6 ; j++)
1368 + {
1369 + vlan[0].mac[j] = 0;
1370 + vlan[1].mac[j] = 0;
1371 + }
1372 + vlan[0].vlanid = 1;
1373 + vlan[1].vlanid = 2;
1374 + vlan[0].vlanmap = 0x7F;
1375 + vlan[1].vlanmap = 0x80;
1376 +
1377 + payload = (char *)kmalloc(entry.size - VCTL_ENTRY_LEN, GFP_KERNEL);
1378 + loc += VCTL_ENTRY_LEN;
1379 + mymtd->read(mymtd, loc, entry.size - VCTL_ENTRY_LEN, &retlen, payload);
1380 + // printk("%s\n", payload);
1381 + tmp1 = strstr(payload, "MAC1:");
1382 + tmp2 = strstr(payload, "MAC2:");
1383 + if(!tmp1||!tmp2){
1384 + kfree(payload);
1385 + #ifdef CONFIG_SL2312_SHARE_PIN
1386 + sl2312flash_disable_parallel_flash();
1387 + #endif
1388 + printk("Error VCTL format!!\n");
1389 + return 0;
1390 + }
1391 + tmp1 += 7;
1392 + tmp2 += 7;
1393 +
1394 +
1395 + for (j = 0; j < 6; j++)
1396 + {
1397 + vlan[0].mac[j] = chrtohex(tmp1[2*j])*16 + chrtohex(tmp1[(2*j)+1]);
1398 + vlan[1].mac[j] = chrtohex(tmp2[2*j])*16 + chrtohex(tmp2[(2*j)+1]);
1399 + }
1400 + tmp1 = strstr(payload, "ID1:");
1401 + tmp2 = strstr(payload, "ID2:");
1402 + tmp1 += 4;
1403 + tmp2 += 4;
1404 + vlan[0].vlanid = tmp1[0] - '0';
1405 + vlan[1].vlanid = tmp2[0] - '0';
1406 + tmp1 = strstr(payload, "MAP1:");
1407 + tmp2 = strstr(payload, "MAP2:");
1408 + tmp1 += 7;
1409 + tmp2 += 7;
1410 + vlan[0].vlanmap = chrtohex(tmp1[0]) * 16 + chrtohex(tmp1[1]);
1411 + vlan[1].vlanmap = chrtohex(tmp2[0]) * 16 + chrtohex(tmp2[1]);
1412 + // printk("Vlan1 id:%x map:%02x mac:%x%x%x%x%x%x\n", vlan[0].vlanid, vlan[0].vlanmap, vlan[0].mac[0], vlan[0].mac[1], vlan[0].mac[2], vlan[0].mac[3], vlan[0].mac[4], vlan[0].mac[5]);
1413 + // printk("Vlan2 id:%x map:%02x mac:%x%x%x%x%x%x\n", vlan[1].vlanid, vlan[1].vlanmap, vlan[1].mac[0], vlan[1].mac[1], vlan[1].mac[2], vlan[1].mac[3], vlan[1].mac[4], vlan[1].mac[5]);
1414 + break;
1415 + }
1416 + loc += entry.size;
1417 + }
1418 + if ( entry.type == VCT_VLAN )
1419 + {
1420 + #ifdef CONFIG_SL2312_SHARE_PIN
1421 + sl2312flash_disable_parallel_flash();
1422 + #endif
1423 + kfree(payload);
1424 + return 1;
1425 + }
1426 + if (i >= head.entry_num)
1427 + printk("Can't find vlan information\n");
1428 + #ifdef CONFIG_SL2312_SHARE_PIN
1429 + sl2312flash_disable_parallel_flash();
1430 + #endif
1431 + return 0;
1432 +}
1433 +
1434 +EXPORT_SYMBOL(get_vlaninfo);
1435 +
1436 +
1437 +module_init(sl2312flash_init);
1438 +module_exit(sl2312flash_exit);
1439 +
1440 +MODULE_AUTHOR("Storlink Ltd");
1441 +MODULE_DESCRIPTION("CFI map driver");
1442 +MODULE_LICENSE("GPL");
1443 --- /dev/null
1444 +++ b/drivers/mtd/maps/sl2312-flash-m25p80.c
1445 @@ -0,0 +1,498 @@
1446 +/*
1447 + * $Id: sl2312-flash-m25p80.c,v 1.2 2006/06/02 08:46:02 middle Exp $
1448 + *
1449 + * Flash and EPROM on Hitachi Solution Engine and similar boards.
1450 + *
1451 + * (C) 2001 Red Hat, Inc.
1452 + *
1453 + * GPL'd
1454 + */
1455 +
1456 +#include <linux/module.h>
1457 +#include <linux/types.h>
1458 +#include <linux/kernel.h>
1459 +
1460 +#include <asm/io.h>
1461 +#include <linux/mtd/mtd.h>
1462 +#include <linux/mtd/map.h>
1463 +#include <linux/mtd/partitions.h>
1464 +#include <asm/hardware.h>
1465 +
1466 +#include <asm/arch/sl2312.h>
1467 +#include <asm/arch/flash.h>
1468 +#include <linux/init.h> //add
1469 +#define g_chipen SERIAL_FLASH_CHIP0_EN //ST
1470 +
1471 +//static int m25p80_page_program(__u32 address, __u8 data, __u32 schip_en);
1472 +static void m25p80_write_cmd(__u8 cmd, __u32 schip_en);
1473 +extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partition **pparts);
1474 +
1475 +
1476 +static __u32 read_flash_ctrl_reg(__u32 ofs)
1477 +{
1478 + __u32 *base;
1479 +
1480 + base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
1481 + return __raw_readl(base);
1482 +}
1483 +
1484 +static void write_flash_ctrl_reg(__u32 ofs,__u32 data)
1485 +{
1486 + __u32 *base;
1487 +
1488 + base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
1489 + __raw_writel(data, base);
1490 +}
1491 +
1492 +static void m25p80_read(__u32 address, __u8 *data, __u32 schip_en)
1493 +{
1494 + __u32 opcode,status;
1495 + __u32 value;
1496 +
1497 + //opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | M25P80_READ;
1498 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS_DATA | M25P80_READ;
1499 + write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
1500 +
1501 + opcode|=g_chipen;
1502 +
1503 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1504 + status=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1505 + while(status&0x80000000)
1506 + {
1507 + status=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1508 + flash_delay();
1509 + schedule();
1510 + }
1511 +
1512 + value=read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1513 + *data = value & 0xff;
1514 +}
1515 +
1516 +static int m25p80_page_program(__u32 address, __u8 *data, __u32 schip_en)
1517 +{
1518 + __u32 opcode;
1519 + __u32 status;
1520 + __u32 tmp;
1521 + int res = FLASH_ERR_OK;
1522 + //volatile FLASH_DATA_T* data_ptr = (volatile FLASH_DATA_T*) data;
1523 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | M25P80_READ_STATUS;
1524 +
1525 + opcode|=g_chipen;
1526 +
1527 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1528 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1529 + while(tmp&0x80000000)
1530 + {
1531 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1532 + flash_delay();
1533 + schedule();
1534 + }
1535 + //middle delay_ms(130);
1536 + status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1537 + if((status&0x02)==0x02)
1538 + {
1539 + //middle delay_ms(100);
1540 + m25p80_write_cmd(M25P80_WRITE_DISABLE, schip_en);
1541 + }
1542 +
1543 +
1544 + m25p80_write_cmd(M25P80_WRITE_ENABLE, schip_en);
1545 + ////middle delay_ms(10);
1546 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS_DATA | M25P80_PAGE_PROGRAM;
1547 + write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
1548 + write_flash_ctrl_reg(FLASH_WRITE_DATA_OFFSET, *data);
1549 +
1550 + //status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1551 + //while(status!=data)
1552 + //{
1553 + // status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1554 + // //middle delay_ms(10);
1555 + //}
1556 +
1557 + opcode|=g_chipen;
1558 +
1559 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1560 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1561 + while(tmp&0x80000000)
1562 + {
1563 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1564 + flash_delay();
1565 + schedule();
1566 + }
1567 + //opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1568 +
1569 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | M25P80_READ_STATUS;
1570 +
1571 + opcode|=g_chipen;
1572 +
1573 +
1574 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1575 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1576 + while(tmp&0x80000000)
1577 + {
1578 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1579 + flash_delay();
1580 + schedule();
1581 + }
1582 + status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1583 + //while(status&0xfd)
1584 + while(status&0x01)
1585 + {
1586 + //if((status&0x9c)!=0)
1587 + // printf(" m25p80_page_program Protect Status = %x\n",status);
1588 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1589 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1590 + while(tmp&0x80000000)
1591 + {
1592 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1593 + flash_delay();
1594 + schedule();
1595 + }
1596 + status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1597 + flash_delay();
1598 + schedule();
1599 + //middle delay_ms(50);
1600 + }
1601 + //printf("status = %x, data = %x\n",status,data);
1602 + if((status&0x02)==0x02)
1603 + {
1604 + //middle delay_ms(100);
1605 + m25p80_write_cmd(M25P80_WRITE_DISABLE, schip_en);
1606 + }
1607 + //};//while (len > 0)
1608 + return res;
1609 +}
1610 +
1611 +void m25p80_copy_from(struct map_info *map, void *buf, unsigned long ofs, ssize_t len)
1612 +{
1613 +// __u32 size;
1614 + __u8 *buffer;
1615 + __u32 length;//i, j,
1616 +
1617 + length = len;
1618 + buffer = (__u8 *)buf;
1619 + while(len)
1620 + {
1621 + m25p80_read(ofs, buffer, g_chipen);
1622 + buffer++;
1623 + ofs++;
1624 + len --;
1625 + } ;
1626 +
1627 +}
1628 +
1629 +__u32 m25p80_read32(struct map_info *map, unsigned long ofs)
1630 +{
1631 +
1632 + return read_flash_ctrl_reg(ofs);
1633 +
1634 +
1635 +}
1636 +
1637 +void m25p80_write32(struct map_info *map, __u32 d, unsigned long ofs)
1638 +{
1639 +
1640 + write_flash_ctrl_reg(ofs, d);
1641 +
1642 +}
1643 +
1644 +void m25p80_copy_to(struct map_info *map, unsigned long ofs, void *buf, ssize_t len)
1645 +{
1646 + __u32 size, i, ret;
1647 +
1648 + while(len > 0)
1649 + {
1650 + if(len >= M25P80_PAGE_SIZE)
1651 + size = M25P80_PAGE_SIZE;
1652 + else
1653 + size = len;
1654 +
1655 + for(i=0;i<size;i++)
1656 + {
1657 + ret = m25p80_page_program( (ofs+i), (buf+i), g_chipen);
1658 + }
1659 + buf+=M25P80_PAGE_SIZE;
1660 + ofs+=M25P80_PAGE_SIZE;
1661 + len-=M25P80_PAGE_SIZE;
1662 +
1663 + };
1664 +
1665 +
1666 +}
1667 +
1668 +static struct mtd_info *serial_mtd;
1669 +
1670 +static struct mtd_partition *parsed_parts;
1671 +
1672 +static struct map_info m25p80_map = {
1673 +
1674 + .name = "SL2312 serial flash m25p80",
1675 + .size = 1048576, //0x100000,
1676 + //buswidth: 4,
1677 + .bankwidth = 4,
1678 + .phys = SL2312_FLASH_BASE,
1679 +#ifdef CONFIG_MTD_COMPLEX_MAPPINGS
1680 + .copy_from = m25p80_copy_from,
1681 + .read = m25p80_read32,
1682 + .write = m25p80_write32,
1683 + .copy_to = m25p80_copy_to
1684 +#endif
1685 +};
1686 +
1687 +
1688 +
1689 +static struct mtd_partition m25p80_partitions[] = {
1690 +
1691 + /* boot code */
1692 + { .name = "bootloader", .offset = 0x00000000, .size = 0x20000, },
1693 + /* kernel image */
1694 + { .name = "kerel image", .offset = 0x000020000, .size = 0xC0000 },
1695 + /* All else is writable (e.g. JFFS) */
1696 + { .name = "user data", .offset = 0x000E0000, .size = 0x00010000, },
1697 +
1698 +
1699 +};
1700 +
1701 +void flash_delay()
1702 +{
1703 + int i,j;
1704 + for(i=0;i<0x100;i++)
1705 + j=i*3+5;
1706 +}
1707 +
1708 +int m25p80_sector_erase(__u32 address, __u32 schip_en)
1709 +{
1710 + __u32 opcode;
1711 + __u32 status;
1712 + __u32 tmp;
1713 + int res = FLASH_ERR_OK;
1714 + //printf("\n-->m25p80_sector_erase");
1715 + if(address >= FLASH_START)
1716 + address-=FLASH_START;
1717 +
1718 + m25p80_write_cmd(M25P80_WRITE_ENABLE, schip_en);
1719 + //printf("\n m25p80_sector_erase : after we-en");
1720 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | M25P80_SECTOR_ERASE;
1721 + write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
1722 + #ifdef MIDWAY_DIAG
1723 + opcode|=schip_en;
1724 + #endif
1725 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1726 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1727 + while(tmp&0x80000000)
1728 + {
1729 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1730 + flash_delay();
1731 + schedule();
1732 + }
1733 +
1734 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | M25P80_READ_STATUS;
1735 + #ifdef MIDWAY_DIAG
1736 + opcode|=schip_en;
1737 + #endif
1738 +
1739 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1740 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1741 + while(tmp&0x80000000)
1742 + {
1743 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1744 + flash_delay();
1745 + schedule();
1746 + }
1747 + status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1748 + //while(status&0xfd)
1749 + while(status&0x01)
1750 + {
1751 + //if((status&0x9c)!=0)
1752 + // printf(" m25p80_sector_erase Protect Status = %x\n",status);
1753 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1754 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1755 + while(tmp&0x80000000)
1756 + {
1757 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1758 + flash_delay();
1759 + schedule();
1760 + }
1761 + status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1762 + flash_delay();
1763 + schedule();
1764 + //middle delay_ms(50);
1765 + }
1766 + if((status&0x02)==0x02)
1767 + {
1768 + //middle delay_ms(100);
1769 + m25p80_write_cmd(M25P80_WRITE_DISABLE, schip_en);
1770 + }
1771 + //printf("\n<--m25p80_sector_erase");
1772 + return res;
1773 +}
1774 +
1775 +static void m25p80_write_cmd(__u8 cmd, __u32 schip_en)
1776 +{
1777 + __u32 opcode,tmp;
1778 + __u32 status;
1779 +
1780 +
1781 +
1782 +
1783 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE | cmd;
1784 +
1785 + opcode|=g_chipen;
1786 +
1787 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1788 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1789 + while(tmp&0x80000000)
1790 + {
1791 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1792 + flash_delay();
1793 + schedule();
1794 + }
1795 + //////
1796 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | M25P80_READ_STATUS;
1797 +
1798 + opcode|=g_chipen;
1799 +
1800 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1801 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1802 + while(tmp&0x80000000)
1803 + {
1804 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1805 + flash_delay();
1806 + schedule();
1807 + }
1808 + //middle delay_ms(130);
1809 + status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1810 + //printf("\ncmd =%x status = %x",cmd,status);
1811 + if(cmd==M25P80_WRITE_ENABLE)
1812 + {
1813 + //printf("\n**-->enable** status = %x",status);
1814 + //middle delay_ms(100);
1815 + while((status&0x03) != 2)
1816 + {
1817 + //if((status&0x9c)!=0)
1818 + // printf(" M25P80_WRITE_ENABLE Protect Status = %x\n",status);
1819 +
1820 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1821 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1822 + while(tmp&0x80000000)
1823 + {
1824 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1825 + //flash_delay();
1826 + }
1827 + status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1828 + //printf("\n**enable** status = %x",status);
1829 + flash_delay();
1830 + schedule();
1831 + //middle delay_ms(100);
1832 + }
1833 + }
1834 + else if(cmd==M25P80_WRITE_DISABLE)
1835 + {
1836 + //while((status&0x03) == 2)
1837 + // printf("\n**disable** status = %x",status);
1838 + //middle delay_ms(100);
1839 + while((status&0x03) != 0)
1840 + {
1841 + //m25p80_write_status((status&0xfd),schip_en);
1842 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1843 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1844 + while(tmp&0x80000000)
1845 + {
1846 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1847 + flash_delay();
1848 + schedule();
1849 + }
1850 + status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1851 + //printf("\n**disable** status = %x",status);
1852 + flash_delay();
1853 + schedule();
1854 + //middle delay_ms(50);
1855 + }
1856 + }
1857 + else
1858 + {
1859 + //while((status&0x01) !=0)
1860 + while((status&0x01) !=0)
1861 + {
1862 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1863 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1864 + while(tmp&0x80000000)
1865 + {
1866 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1867 + flash_delay();
1868 + schedule();
1869 + }
1870 + status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1871 + flash_delay();
1872 + schedule();
1873 + //middle delay_ms(50);
1874 + }
1875 + }
1876 + //////
1877 +
1878 + //printf("\n<-- status = %x",status);
1879 +}
1880 +
1881 +static int __init init_sl2312_m25p80(void)
1882 +{
1883 + int nr_parts = 0;
1884 + struct mtd_partition *parts;
1885 +
1886 + serial_mtd = kmalloc(sizeof(struct mtd_info), GFP_KERNEL);
1887 + if (!serial_mtd)
1888 + return NULL;
1889 +
1890 + memset(serial_mtd, 0, sizeof(struct mtd_info));
1891 + m25p80_map.virt = (unsigned long)ioremap(SL2312_FLASH_BASE, SFLASH_SIZE);//(unsigned long)ioremap(FLASH_START, SFLASH_SIZE);
1892 + if (!m25p80_map.virt) {
1893 + printk(" failed to ioremap \n");
1894 + return -EIO;
1895 + }
1896 + serial_mtd = do_map_probe("map_serial", &m25p80_map);
1897 + if (serial_mtd) {
1898 + serial_mtd->owner = THIS_MODULE;
1899 +
1900 + }
1901 +
1902 +#ifdef CONFIG_MTD_REDBOOT_PARTS
1903 + nr_parts = parse_redboot_partitions(serial_mtd, &parsed_parts);
1904 + if (nr_parts > 0)
1905 + printk(KERN_NOTICE "Found RedBoot partition table.\n");
1906 + else if (nr_parts < 0)
1907 + printk(KERN_NOTICE "Error looking for RedBoot partitions.\n");
1908 +#else
1909 + parsed_parts = m25p80_partitions;
1910 + parts = m25p80_partitions;
1911 + nr_parts = sizeof(m25p80_partitions)/sizeof(*parts);
1912 + nr_parts = sizeof(m25p80_partitions)/sizeof(*parsed_parts);
1913 +#endif /* CONFIG_MTD_REDBOOT_PARTS */
1914 +
1915 + if (nr_parts > 0)
1916 + add_mtd_partitions(serial_mtd, parsed_parts, nr_parts);
1917 + else
1918 + add_mtd_device(serial_mtd);
1919 +
1920 + return 0;
1921 +}
1922 +
1923 +static void __exit cleanup_sl2312_m25p80(void)
1924 +{
1925 + if (parsed_parts)
1926 + del_mtd_partitions(serial_mtd);
1927 + else
1928 + del_mtd_device(serial_mtd);
1929 +
1930 + map_destroy(serial_mtd);
1931 +
1932 +
1933 +}
1934 +
1935 +module_init(init_sl2312_m25p80);
1936 +module_exit(cleanup_sl2312_m25p80);
1937 +
1938 +
1939 +
1940 +MODULE_LICENSE("GPL");
1941 +MODULE_AUTHOR("Plus Chen <plus@storlink.com.tw>");
1942 +MODULE_DESCRIPTION("MTD map driver for Storlink Sword boards");
1943 +
1944 --- /dev/null
1945 +++ b/drivers/mtd/maps/sl2312_flashmap.h
1946 @@ -0,0 +1,20 @@
1947 +/*
1948 + * Please note that the name are used in mkflash script. Therefore
1949 + * don't change them. If you want to add different partitions, you
1950 + * will need to modify mkflash script as well so that the end image
1951 + * is what you include here!
1952 + *
1953 + * Also, the 7th item is always the size, so please don't add extra
1954 + * spaces in the name or other items.
1955 + *
1956 + * - Alan
1957 + */
1958 +
1959 +static struct mtd_partition sl2312_partitions[] = {
1960 + { name: "RedBoot", offset: 0x00000000, size: 0x00020000, },
1961 + { name: "kernel", offset: 0x00020000, size: 0x00100000, },
1962 + { name: "rootfs", offset: 0x00120000, size: 0x006A0000, },
1963 + { name: "VCTL", offset: 0x007C0000, size: 0x00010000, },
1964 + { name: "cfg", offset: 0x007D0000, size: 0x00020000, },
1965 + { name: "FIS directory", offset: 0x007F0000, size: 0x00010000, }
1966 +};
1967 --- /dev/null
1968 +++ b/drivers/mtd/maps/sl2312_flashmap.h.16MB
1969 @@ -0,0 +1,21 @@
1970 +/*
1971 + * Please note that the name are used in mkflash script. Therefore
1972 + * don't change them. If you want to add different partitions, you
1973 + * will need to modify mkflash script as well so that the end image
1974 + * is what you include here!
1975 + *
1976 + * Also, the 7th item is always the size, so please don't add extra
1977 + * spaces in the name or other items.
1978 + *
1979 + * - Alan
1980 + */
1981 +
1982 +static struct mtd_partition sl2312_partitions[] = {
1983 + { name: "RedBoot", offset: 0x00000000, size: 0x00020000, },
1984 + { name: "Kernel", offset: 0x00020000, size: 0x00300000, },
1985 + { name: "Ramdisk", offset: 0x00320000, size: 0x00600000, },
1986 + { name: "Application", offset: 0x00920000, size: 0x00600000, },
1987 + { name: "VCTL", offset: 0x00F20000, size: 0x00020000, },
1988 + { name: "CurConf", offset: 0x00F40000, size: 0x000A0000, },
1989 + { name: "FIS directory", offset: 0x00FE0000, size: 0x00020000, }
1990 +};
1991 --- /dev/null
1992 +++ b/drivers/mtd/maps/sl2312_flashmap.h.8MB
1993 @@ -0,0 +1,21 @@
1994 +/*
1995 + * Please note that the name are used in mkflash script. Therefore
1996 + * don't change them. If you want to add different partitions, you
1997 + * will need to modify mkflash script as well so that the end image
1998 + * is what you include here!
1999 + *
2000 + * Also, the 7th item is always the size, so please don't add extra
2001 + * spaces in the name or other items.
2002 + *
2003 + * - Alan
2004 + */
2005 +
2006 +static struct mtd_partition sl2312_partitions[] = {
2007 + { name: "RedBoot", offset: 0x00000000, size: 0x00020000, },
2008 + { name: "Kernel", offset: 0x00020000, size: 0x00200000, },
2009 + { name: "Ramdisk", offset: 0x00220000, size: 0x00280000, },
2010 + { name: "Application", offset: 0x004A0000, size: 0x00300000, },
2011 + { name: "VCTL", offset: 0x007A0000, size: 0x00020000, },
2012 + { name: "CurConf", offset: 0x007C0000, size: 0x00020000, },
2013 + { name: "FIS directory", offset: 0x007E0000, size: 0x00020000, }
2014 +};
2015 --- a/drivers/mtd/mtdchar.c
2016 +++ b/drivers/mtd/mtdchar.c
2017 @@ -59,6 +59,77 @@ struct mtd_file_info {
2018 enum mtd_file_modes mode;
2019 };
2020
2021 +/***********************************************************************
2022 +/* Storlink SoC -- flash
2023 +/***********************************************************************/
2024 +#ifdef CONFIG_SL2312_SHARE_PIN
2025 +unsigned int share_pin_flag=0; // bit0:FLASH, bit1:UART, bit2:EMAC, bit3-4:IDE
2026 +unsigned int check_sleep_flag=0; // bit0:FLASH, bit1:IDE
2027 +static spinlock_t sl2312_flash_lock = SPIN_LOCK_UNLOCKED;
2028 +EXPORT_SYMBOL(share_pin_flag);
2029 +int dbg=0;
2030 +DECLARE_WAIT_QUEUE_HEAD(wq);
2031 +extern struct wait_queue_head_t *flash_wait;
2032 +unsigned int flash_req=0;
2033 +void mtd_lock()
2034 +{
2035 + struct task_struct *tsk = current;
2036 + unsigned int value ;
2037 + unsigned long flags;
2038 + flash_req = 1;
2039 + DECLARE_WAITQUEUE(wait, tsk);
2040 + add_wait_queue(&wq, &wait);
2041 + for(;;)
2042 + {
2043 + set_task_state(tsk, TASK_INTERRUPTIBLE);
2044 + spin_lock_irqsave(&sl2312_flash_lock,flags);
2045 + if((share_pin_flag&0x1E)){//||(check_sleep_flag&0x00000002)) {
2046 + spin_unlock_irqrestore(&sl2312_flash_lock, flags);
2047 + check_sleep_flag |= 0x00000001;
2048 + if(dbg)
2049 + printk("mtd yield %x %x\n",share_pin_flag,check_sleep_flag);
2050 + wake_up_interruptible(&flash_wait);
2051 + schedule();
2052 + }
2053 + else {
2054 + check_sleep_flag &= ~0x01;
2055 + share_pin_flag |= 0x00000001 ; // set share pin flag
2056 + spin_unlock_irqrestore(&sl2312_flash_lock, flags);
2057 + value = readl(IO_ADDRESS((SL2312_GLOBAL_BASE+GLOBAL_MISC_REG)));
2058 + value = value & (~PFLASH_SHARE_BIT) ;
2059 + writel(value,IO_ADDRESS((SL2312_GLOBAL_BASE+GLOBAL_MISC_REG)));
2060 + if(dbg)
2061 + printk("mtd Go %x %x\n",share_pin_flag,check_sleep_flag);
2062 + tsk->state = TASK_RUNNING;
2063 + remove_wait_queue(&wq, &wait);
2064 + return ;
2065 + }
2066 + }
2067 +}
2068 +
2069 +void mtd_unlock()
2070 +{
2071 + unsigned int value ;
2072 + unsigned long flags;
2073 +
2074 + spin_lock_irqsave(&sl2312_flash_lock,flags); // Disable IRQ
2075 + value = readl(IO_ADDRESS((SL2312_GLOBAL_BASE+GLOBAL_MISC_REG)));
2076 + value = value | PFLASH_SHARE_BIT ; // Disable Flash PADs
2077 + writel(value,IO_ADDRESS((SL2312_GLOBAL_BASE+GLOBAL_MISC_REG)));
2078 + share_pin_flag &= ~(0x00000001); // clear share pin flag
2079 + check_sleep_flag &= ~0x00000001;
2080 + spin_unlock_irqrestore(&sl2312_flash_lock, flags); // Restore IRQ
2081 + if (check_sleep_flag & 0x00000002)
2082 + {
2083 + check_sleep_flag &= ~(0x00000002);
2084 + wake_up_interruptible(&flash_wait);
2085 + }
2086 + DEBUG(MTD_DEBUG_LEVEL0, "Flash Unlock...\n");
2087 + flash_req = 0;
2088 +}
2089 +#endif
2090 +/***********************************************************************/
2091 +
2092 static loff_t mtd_lseek (struct file *file, loff_t offset, int orig)
2093 {
2094 struct mtd_file_info *mfi = file->private_data;
2095 @@ -162,13 +233,21 @@ static ssize_t mtd_read(struct file *fil
2096 int len;
2097 char *kbuf;
2098
2099 +#ifdef CONFIG_SL2312_SHARE_PIN
2100 + mtd_lock(); // sl2312 share pin lock
2101 +#endif
2102 +
2103 DEBUG(MTD_DEBUG_LEVEL0,"MTD_read\n");
2104
2105 if (*ppos + count > mtd->size)
2106 count = mtd->size - *ppos;
2107
2108 - if (!count)
2109 + if (!count){
2110 +#ifdef CONFIG_SL2312_SHARE_PIN
2111 + mtd_unlock(); // sl2312 share pin lock
2112 +#endif
2113 return 0;
2114 + }
2115
2116 /* FIXME: Use kiovec in 2.5 to lock down the user's buffers
2117 and pass them directly to the MTD functions */
2118 @@ -178,8 +257,12 @@ static ssize_t mtd_read(struct file *fil
2119 else
2120 kbuf=kmalloc(count, GFP_KERNEL);
2121
2122 - if (!kbuf)
2123 + if (!kbuf) {
2124 +#ifdef CONFIG_SL2312_SHARE_PIN
2125 + mtd_unlock(); // sl2312 share pin lock
2126 +#endif
2127 return -ENOMEM;
2128 + }
2129
2130 while (count) {
2131
2132 @@ -224,6 +307,9 @@ static ssize_t mtd_read(struct file *fil
2133 *ppos += retlen;
2134 if (copy_to_user(buf, kbuf, retlen)) {
2135 kfree(kbuf);
2136 +#ifdef CONFIG_SL2312_SHARE_PIN
2137 + mtd_unlock(); // sl2312 share pin lock
2138 +#endif
2139 return -EFAULT;
2140 }
2141 else
2142 @@ -235,13 +321,19 @@ static ssize_t mtd_read(struct file *fil
2143 count = 0;
2144 }
2145 else {
2146 - kfree(kbuf);
2147 + kfree(kbuf);
2148 +#ifdef CONFIG_SL2312_SHARE_PIN
2149 + mtd_unlock(); // sl2312 share pin lock
2150 +#endif
2151 return ret;
2152 }
2153
2154 }
2155
2156 kfree(kbuf);
2157 +#ifdef CONFIG_SL2312_SHARE_PIN
2158 + mtd_unlock(); // sl2312 share pin lock
2159 +#endif
2160 return total_retlen;
2161 } /* mtd_read */
2162
2163 @@ -255,24 +347,40 @@ static ssize_t mtd_write(struct file *fi
2164 int ret=0;
2165 int len;
2166
2167 +#ifdef CONFIG_SL2312_SHARE_PIN
2168 + mtd_lock(); // sl2312 share pin lock
2169 +#endif
2170 +
2171 DEBUG(MTD_DEBUG_LEVEL0,"MTD_write\n");
2172
2173 - if (*ppos == mtd->size)
2174 + if (*ppos == mtd->size){
2175 +#ifdef CONFIG_SL2312_SHARE_PIN
2176 + mtd_unlock(); // sl2312 share pin lock
2177 +#endif
2178 return -ENOSPC;
2179 + }
2180
2181 if (*ppos + count > mtd->size)
2182 count = mtd->size - *ppos;
2183
2184 - if (!count)
2185 + if (!count){
2186 +#ifdef CONFIG_SL2312_SHARE_PIN
2187 + mtd_unlock(); // sl2312 share pin lock
2188 +#endif
2189 return 0;
2190 + }
2191
2192 if (count > MAX_KMALLOC_SIZE)
2193 kbuf=kmalloc(MAX_KMALLOC_SIZE, GFP_KERNEL);
2194 else
2195 kbuf=kmalloc(count, GFP_KERNEL);
2196
2197 - if (!kbuf)
2198 + if (!kbuf) {
2199 +#ifdef CONFIG_SL2312_SHARE_PIN
2200 + mtd_unlock(); // sl2312 share pin lock
2201 +#endif
2202 return -ENOMEM;
2203 + }
2204
2205 while (count) {
2206
2207 @@ -283,6 +391,9 @@ static ssize_t mtd_write(struct file *fi
2208
2209 if (copy_from_user(kbuf, buf, len)) {
2210 kfree(kbuf);
2211 +#ifdef CONFIG_SL2312_SHARE_PIN
2212 + mtd_unlock(); // sl2312 share pin lock
2213 +#endif
2214 return -EFAULT;
2215 }
2216
2217 @@ -323,11 +434,17 @@ static ssize_t mtd_write(struct file *fi
2218 }
2219 else {
2220 kfree(kbuf);
2221 +#ifdef CONFIG_SL2312_SHARE_PIN
2222 + mtd_unlock(); // sl2312 share pin lock
2223 +#endif
2224 return ret;
2225 }
2226 }
2227
2228 kfree(kbuf);
2229 +#ifdef CONFIG_SL2312_SHARE_PIN
2230 + mtd_unlock(); // sl2312 share pin lock
2231 +#endif
2232 return total_retlen;
2233 } /* mtd_write */
2234
2235 @@ -381,36 +498,67 @@ static int mtd_ioctl(struct inode *inode
2236 u_long size;
2237 struct mtd_info_user info;
2238
2239 +#ifdef CONFIG_SL2312_SHARE_PIN
2240 + mtd_lock(); // sl2312 share pin lock
2241 +#endif
2242 +
2243 DEBUG(MTD_DEBUG_LEVEL0, "MTD_ioctl\n");
2244
2245 size = (cmd & IOCSIZE_MASK) >> IOCSIZE_SHIFT;
2246 if (cmd & IOC_IN) {
2247 if (!access_ok(VERIFY_READ, argp, size))
2248 + {
2249 +#ifdef CONFIG_SL2312_SHARE_PIN
2250 + mtd_unlock(); // sl2312 share pin lock
2251 +#endif
2252 return -EFAULT;
2253 + }
2254 }
2255 if (cmd & IOC_OUT) {
2256 if (!access_ok(VERIFY_WRITE, argp, size))
2257 + {
2258 +#ifdef CONFIG_SL2312_SHARE_PIN
2259 + mtd_unlock(); // sl2312 share pin lock
2260 +#endif
2261 return -EFAULT;
2262 + }
2263 }
2264
2265 switch (cmd) {
2266 case MEMGETREGIONCOUNT:
2267 if (copy_to_user(argp, &(mtd->numeraseregions), sizeof(int)))
2268 + {
2269 +#ifdef CONFIG_SL2312_SHARE_PIN
2270 + mtd_unlock(); // sl2312 share pin lock
2271 +#endif
2272 return -EFAULT;
2273 + }
2274 break;
2275
2276 case MEMGETREGIONINFO:
2277 {
2278 struct region_info_user ur;
2279
2280 - if (copy_from_user(&ur, argp, sizeof(struct region_info_user)))
2281 + if (copy_from_user(&ur, argp, sizeof(struct region_info_user))) {
2282 +#ifdef CONFIG_SL2312_SHARE_PIN
2283 + mtd_unlock(); // sl2312 share pin lock
2284 +#endif
2285 return -EFAULT;
2286 + }
2287
2288 - if (ur.regionindex >= mtd->numeraseregions)
2289 + if (ur.regionindex >= mtd->numeraseregions) {
2290 +#ifdef CONFIG_SL2312_SHARE_PIN
2291 + mtd_unlock(); // sl2312 share pin lock
2292 +#endif
2293 return -EINVAL;
2294 + }
2295 if (copy_to_user(argp, &(mtd->eraseregions[ur.regionindex]),
2296 - sizeof(struct mtd_erase_region_info)))
2297 + sizeof(struct mtd_erase_region_info))) {
2298 +#ifdef CONFIG_SL2312_SHARE_PIN
2299 + mtd_unlock(); // sl2312 share pin lock
2300 +#endif
2301 return -EFAULT;
2302 + }
2303 break;
2304 }
2305
2306 @@ -433,7 +581,12 @@ static int mtd_ioctl(struct inode *inode
2307 struct erase_info *erase;
2308
2309 if(!(file->f_mode & 2))
2310 + {
2311 +#ifdef CONFIG_SL2312_SHARE_PIN
2312 + mtd_unlock(); // sl2312 share pin lock
2313 +#endif
2314 return -EPERM;
2315 + }
2316
2317 erase=kzalloc(sizeof(struct erase_info),GFP_KERNEL);
2318 if (!erase)
2319 @@ -447,6 +600,9 @@ static int mtd_ioctl(struct inode *inode
2320 if (copy_from_user(&erase->addr, argp,
2321 sizeof(struct erase_info_user))) {
2322 kfree(erase);
2323 +#ifdef CONFIG_SL2312_SHARE_PIN
2324 + mtd_unlock(); // sl2312 share pin lock
2325 +#endif
2326 return -EFAULT;
2327 }
2328 erase->mtd = mtd;
2329 @@ -484,14 +640,26 @@ static int mtd_ioctl(struct inode *inode
2330 struct mtd_oob_buf buf;
2331 struct mtd_oob_ops ops;
2332
2333 - if(!(file->f_mode & 2))
2334 + if(!(file->f_mode & 2)) {
2335 +#ifdef CONFIG_SL2312_SHARE_PIN
2336 + mtd_unlock(); // sl2312 share pin lock
2337 +#endif
2338 return -EPERM;
2339 + }
2340
2341 - if (copy_from_user(&buf, argp, sizeof(struct mtd_oob_buf)))
2342 + if (copy_from_user(&buf, argp, sizeof(struct mtd_oob_buf))) {
2343 +#ifdef CONFIG_SL2312_SHARE_PIN
2344 + mtd_unlock(); // sl2312 share pin lock
2345 +#endif
2346 return -EFAULT;
2347 + }
2348
2349 - if (buf.length > 4096)
2350 + if (buf.length > 4096) {
2351 +#ifdef CONFIG_SL2312_SHARE_PIN
2352 + mtd_unlock(); // sl2312 share pin lock
2353 +#endif
2354 return -EINVAL;
2355 + }
2356
2357 if (!mtd->write_oob)
2358 ret = -EOPNOTSUPP;
2359 @@ -499,8 +667,12 @@ static int mtd_ioctl(struct inode *inode
2360 ret = access_ok(VERIFY_READ, buf.ptr,
2361 buf.length) ? 0 : EFAULT;
2362
2363 - if (ret)
2364 + if (ret) {
2365 +#ifdef CONFIG_SL2312_SHARE_PIN
2366 + mtd_unlock(); // sl2312 share pin lock
2367 +#endif
2368 return ret;
2369 + }
2370
2371 ops.ooblen = buf.length;
2372 ops.ooboffs = buf.start & (mtd->oobsize - 1);
2373 @@ -536,19 +708,35 @@ static int mtd_ioctl(struct inode *inode
2374 struct mtd_oob_buf buf;
2375 struct mtd_oob_ops ops;
2376
2377 - if (copy_from_user(&buf, argp, sizeof(struct mtd_oob_buf)))
2378 + if (copy_from_user(&buf, argp, sizeof(struct mtd_oob_buf))) {
2379 +#ifdef CONFIG_SL2312_SHARE_PIN
2380 + mtd_unlock(); // sl2312 share pin lock
2381 +#endif
2382 return -EFAULT;
2383 + }
2384
2385 - if (buf.length > 4096)
2386 + if (buf.length > 4096) {
2387 +#ifdef CONFIG_SL2312_SHARE_PIN
2388 + mtd_unlock(); // sl2312 share pin lock
2389 +#endif
2390 return -EINVAL;
2391 + }
2392
2393 - if (!mtd->read_oob)
2394 + if (!mtd->read_oob) {
2395 +#ifdef CONFIG_SL2312_SHARE_PIN
2396 + mtd_unlock(); // sl2312 share pin lock
2397 +#endif
2398 ret = -EOPNOTSUPP;
2399 + }
2400 else
2401 ret = access_ok(VERIFY_WRITE, buf.ptr,
2402 buf.length) ? 0 : -EFAULT;
2403 - if (ret)
2404 + if (ret) {
2405 +#ifdef CONFIG_SL2312_SHARE_PIN
2406 + mtd_unlock(); // sl2312 share pin lock
2407 +#endif
2408 return ret;
2409 + }
2410
2411 ops.ooblen = buf.length;
2412 ops.ooboffs = buf.start & (mtd->oobsize - 1);
2413 @@ -580,7 +768,12 @@ static int mtd_ioctl(struct inode *inode
2414 struct erase_info_user info;
2415
2416 if (copy_from_user(&info, argp, sizeof(info)))
2417 + {
2418 +#ifdef CONFIG_SL2312_SHARE_PIN
2419 + mtd_unlock(); // sl2312 share pin lock
2420 +#endif
2421 return -EFAULT;
2422 + }
2423
2424 if (!mtd->lock)
2425 ret = -EOPNOTSUPP;
2426 @@ -594,7 +787,12 @@ static int mtd_ioctl(struct inode *inode
2427 struct erase_info_user info;
2428
2429 if (copy_from_user(&info, argp, sizeof(info)))
2430 + {
2431 +#ifdef CONFIG_SL2312_SHARE_PIN
2432 + mtd_unlock(); // sl2312 share pin lock
2433 +#endif
2434 return -EFAULT;
2435 + }
2436
2437 if (!mtd->unlock)
2438 ret = -EOPNOTSUPP;
2439 @@ -629,11 +827,21 @@ static int mtd_ioctl(struct inode *inode
2440 loff_t offs;
2441
2442 if (copy_from_user(&offs, argp, sizeof(loff_t)))
2443 + {
2444 +#ifdef CONFIG_SL2312_SHARE_PIN
2445 + mtd_unlock(); // sl2312 share pin lock
2446 +#endif
2447 return -EFAULT;
2448 + }
2449 if (!mtd->block_isbad)
2450 ret = -EOPNOTSUPP;
2451 else
2452 + {
2453 +#ifdef CONFIG_SL2312_SHARE_PIN
2454 + mtd_unlock(); // sl2312 share pin lock
2455 +#endif
2456 return mtd->block_isbad(mtd, offs);
2457 + }
2458 break;
2459 }
2460
2461 @@ -642,11 +850,21 @@ static int mtd_ioctl(struct inode *inode
2462 loff_t offs;
2463
2464 if (copy_from_user(&offs, argp, sizeof(loff_t)))
2465 + {
2466 +#ifdef CONFIG_SL2312_SHARE_PIN
2467 + mtd_unlock(); // sl2312 share pin lock
2468 +#endif
2469 return -EFAULT;
2470 + }
2471 if (!mtd->block_markbad)
2472 ret = -EOPNOTSUPP;
2473 else
2474 + {
2475 +#ifdef CONFIG_SL2312_SHARE_PIN
2476 + mtd_unlock(); // sl2312 share pin lock
2477 +#endif
2478 return mtd->block_markbad(mtd, offs);
2479 + }
2480 break;
2481 }
2482
2483 @@ -654,8 +872,12 @@ static int mtd_ioctl(struct inode *inode
2484 case OTPSELECT:
2485 {
2486 int mode;
2487 - if (copy_from_user(&mode, argp, sizeof(int)))
2488 + if (copy_from_user(&mode, argp, sizeof(int))) {
2489 +#ifdef CONFIG_SL2312_SHARE_PIN
2490 + mtd_unlock(); // sl2312 share pin lock
2491 +#endif
2492 return -EFAULT;
2493 + }
2494
2495 mfi->mode = MTD_MODE_NORMAL;
2496
2497 @@ -670,7 +892,12 @@ static int mtd_ioctl(struct inode *inode
2498 {
2499 struct otp_info *buf = kmalloc(4096, GFP_KERNEL);
2500 if (!buf)
2501 + {
2502 +#ifdef CONFIG_SL2312_SHARE_PIN
2503 + mtd_unlock(); // sl2312 share pin lock
2504 +#endif
2505 return -ENOMEM;
2506 + }
2507 ret = -EOPNOTSUPP;
2508 switch (mfi->mode) {
2509 case MTD_MODE_OTP_FACTORY:
2510 @@ -701,12 +928,24 @@ static int mtd_ioctl(struct inode *inode
2511 {
2512 struct otp_info info;
2513
2514 - if (mfi->mode != MTD_MODE_OTP_USER)
2515 + if (mfi->mode != MTD_MODE_OTP_USER) {
2516 +#ifdef CONFIG_SL2312_SHARE_PIN
2517 + mtd_unlock(); // sl2312 share pin lock
2518 +#endif
2519 return -EINVAL;
2520 - if (copy_from_user(&info, argp, sizeof(info)))
2521 + }
2522 + if (copy_from_user(&info, argp, sizeof(info))) {
2523 +#ifdef CONFIG_SL2312_SHARE_PIN
2524 + mtd_unlock(); // sl2312 share pin lock
2525 +#endif
2526 return -EFAULT;
2527 - if (!mtd->lock_user_prot_reg)
2528 + }
2529 + if (!mtd->lock_user_prot_reg) {
2530 +#ifdef CONFIG_SL2312_SHARE_PIN
2531 + mtd_unlock(); // sl2312 share pin lock
2532 +#endif
2533 return -EOPNOTSUPP;
2534 + }
2535 ret = mtd->lock_user_prot_reg(mtd, info.start, info.length);
2536 break;
2537 }
2538 @@ -742,8 +981,12 @@ static int mtd_ioctl(struct inode *inode
2539 break;
2540
2541 case MTD_MODE_RAW:
2542 - if (!mtd->read_oob || !mtd->write_oob)
2543 + if (!mtd->read_oob || !mtd->write_oob) {
2544 +#ifdef CONFIG_SL2312_SHARE_PIN
2545 + mtd_unlock(); // sl2312 share pin lock
2546 +#endif
2547 return -EOPNOTSUPP;
2548 + }
2549 mfi->mode = arg;
2550
2551 case MTD_MODE_NORMAL:
2552 @@ -766,6 +1009,10 @@ static int mtd_ioctl(struct inode *inode
2553 ret = -ENOTTY;
2554 }
2555
2556 +#ifdef CONFIG_SL2312_SHARE_PIN
2557 + mtd_unlock(); // sl2312 share pin lock
2558 +#endif
2559 +
2560 return ret;
2561 } /* memory_ioctl */
2562
2563 --- a/drivers/mtd/nand/Kconfig
2564 +++ b/drivers/mtd/nand/Kconfig
2565 @@ -44,6 +44,13 @@ config MTD_NAND_AUTCPU12
2566 This enables the driver for the autronix autcpu12 board to
2567 access the SmartMediaCard.
2568
2569 +config MTD_NAND_SL2312
2570 + tristate "NAND Flash device on Storlink board"
2571 + depends on ARM && MTD_NAND && ARCH_SL2312
2572 + help
2573 + This enables the driver for the Storlink board to
2574 + access the nand device.
2575 +
2576 config MTD_NAND_EDB7312
2577 tristate "Support for Cirrus Logic EBD7312 evaluation board"
2578 depends on ARCH_EDB7312
2579 --- /dev/null
2580 +++ b/drivers/mtd/nand/sl2312-flash-nand.c
2581 @@ -0,0 +1,2287 @@
2582 +/*
2583 + * drivers/mtd/sl2312.c
2584 + *
2585 + * $Id: sl2312-flash-nand.c,v 1.5 2006/06/15 07:02:29 middle Exp $
2586 + *
2587 + * Copyright (C) 2001 Toshiba Corporation
2588 + *
2589 + * 2003 (c) MontaVista Software, Inc. This file is licensed under
2590 + * the terms of the GNU General Public License version 2. This program
2591 + * is licensed "as is" without any warranty of any kind, whether express
2592 + * or implied.
2593 + *
2594 + */
2595 +
2596 +#include <linux/slab.h>
2597 +#include <linux/init.h>
2598 +#include <linux/module.h>
2599 +#include <linux/mtd/mtd.h>
2600 +#include <linux/mtd/nand.h>
2601 +#include <linux/mtd/nand_ecc.h>
2602 +#include <linux/mtd/partitions.h>
2603 +#include <linux/delay.h>
2604 +#include <asm/io.h>
2605 +#include <asm/hardware.h>
2606 +#include <asm/arch/sl2312.h>
2607 +#include "sl2312-flash-nand.h"
2608 +
2609 +
2610 +#include <linux/errno.h>
2611 +#include <linux/sched.h>
2612 +#include <linux/types.h>
2613 +#include <linux/mtd/compatmac.h>
2614 +#include <linux/interrupt.h>
2615 +#include <linux/bitops.h>
2616 +
2617 +
2618 +/*
2619 + * NAND low-level MTD interface functions
2620 + */
2621 +static void sl2312_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
2622 +static void sl2312_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
2623 +static int sl2312_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len);
2624 +
2625 +static int sl2312_nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf);
2626 +static int sl2312_nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel);
2627 +static int sl2312_nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf);
2628 +static int sl2312_nand_write (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf);
2629 +static int sl2312_nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len,
2630 + size_t * retlen, const u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel);
2631 +static int sl2312_nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char *buf);
2632 +static int sl2312_nand_writev (struct mtd_info *mtd, const struct kvec *vecs,
2633 + unsigned long count, loff_t to, size_t * retlen);
2634 +static int sl2312_nand_writev_ecc (struct mtd_info *mtd, const struct kvec *vecs,
2635 + unsigned long count, loff_t to, size_t * retlen, u_char *eccbuf, struct nand_oobinfo *oobsel);
2636 +static int sl2312_nand_erase (struct mtd_info *mtd, struct erase_info *instr, int allowbbt);
2637 +static void sl2312_nand_sync (struct mtd_info *mtd);
2638 +static int sl2312_nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int page, u_char *oob_buf, struct nand_oobinfo *oobsel);
2639 +static int sl2312_nand_block_checkbad (struct mtd_info *mtd, loff_t ofs, int getchip, int allowbbt);
2640 +static int sl2312_nand_erase_block(struct mtd_info *mtd, int page);
2641 +
2642 +/*
2643 + * MTD structure for sl2312 NDFMC
2644 + */
2645 +static struct mtd_info *sl2312_mtd = NULL;
2646 +static int nand_page=0,nand_col=0;
2647 +
2648 +/* Define default oob placement schemes for large and small page devices */
2649 +static struct nand_oobinfo nand_oob_8 = {
2650 + .useecc = MTD_NANDECC_AUTOPLACE,
2651 + .eccbytes = 3,
2652 + .eccpos = {0, 1, 2},
2653 + .oobfree = { {3, 2}, {6, 2} }
2654 +};
2655 +
2656 +static struct nand_oobinfo nand_oob_16 = {
2657 + .useecc = MTD_NANDECC_AUTOPLACE,
2658 + .eccbytes = 6,
2659 + .eccpos = {0, 1, 2, 3, 6, 7},
2660 + .oobfree = { {8, 8} }
2661 +};
2662 +
2663 +static struct nand_oobinfo nand_oob_64 = {
2664 + .useecc = MTD_NANDECC_AUTOPLACE,
2665 + .eccbytes = 24,
2666 + .eccpos = {
2667 + 40, 41, 42, 43, 44, 45, 46, 47,
2668 + 48, 49, 50, 51, 52, 53, 54, 55,
2669 + 56, 57, 58, 59, 60, 61, 62, 63},
2670 + .oobfree = { {2, 38} }
2671 +};
2672 +
2673 +
2674 +/*
2675 + * Define partitions for flash device
2676 + */
2677 +/* the base address of FLASH control register */
2678 +#define FLASH_CONTROL_BASE_ADDR (IO_ADDRESS(SL2312_FLASH_CTRL_BASE))
2679 +#define SL2312_GLOBAL_BASE_ADDR (IO_ADDRESS(SL2312_GLOBAL_BASE))
2680 +//#define SL2312_FLASH_BASE_ADDR (IO_ADDRESS(SL2312_FLASH_BASE))
2681 +#define SL2312_FLASH_BASE_ADDR FLASH_VADDR(SL2312_FLASH_BASE)
2682 +static unsigned int CHIP_EN;
2683 +/* define read/write register utility */
2684 +//#define FLASH_READ_REG(offset) (__raw_readl(offset+FLASH_CONTROL_BASE_ADDR))
2685 +//#define FLASH_WRITE_REG(offset,val) (__raw_writel(val,offset+FLASH_CONTROL_BASE_ADDR))
2686 +//#define FLASH_READ_DATA(offset) (__raw_readb(offset+SL2312_FLASH_BASE_ADDR))
2687 +//#define FLASH_WRITE_DATA(offset,val) (__raw_writeb(val,offset+SL2312_FLASH_BASE_ADDR))
2688 +
2689 +unsigned int FLASH_READ_REG(unsigned int addr)
2690 +{
2691 + unsigned int *base;
2692 + unsigned int data;
2693 +
2694 + base = (unsigned int *)(FLASH_CONTROL_BASE_ADDR + addr);
2695 + data = *base;
2696 + return (data);
2697 +}
2698 +
2699 +void FLASH_WRITE_REG(unsigned int addr,unsigned int data)
2700 +{
2701 + unsigned int *base;
2702 +
2703 + base = (unsigned int *)(FLASH_CONTROL_BASE_ADDR + addr);
2704 + *base = data;
2705 + return;
2706 +}
2707 +
2708 +unsigned int FLASH_READ_DATA(unsigned int addr)
2709 +{
2710 + unsigned char *base;
2711 + unsigned int data;
2712 +
2713 + base = (unsigned char *)(SL2312_FLASH_BASE_ADDR + addr);
2714 + data = *base;
2715 + return (data);
2716 +}
2717 +
2718 +void FLASH_WRITE_DATA(unsigned int addr,unsigned int data)
2719 +{
2720 + unsigned char *base;
2721 +
2722 + base = (unsigned char *)(SL2312_FLASH_BASE_ADDR + addr);
2723 + *base = data;
2724 + return;
2725 +}
2726 +
2727 +/* the offset of FLASH control register */
2728 +enum NFLASH_REGISTER {
2729 + NFLASH_ID = 0x0000,
2730 + NFLASH_STATUS = 0x0008,
2731 + NFLASH_TYPE = 0x000c,
2732 + NFLASH_ACCESS = 0x0030,
2733 + NFLASH_COUNT = 0x0034,
2734 + NFLASH_CMD_ADDR = 0x0038,
2735 + NFLASH_ADDRESS = 0x003C,
2736 + NFLASH_DATA = 0x0040,
2737 + NFLASH_TIMING = 0x004C,
2738 + NFLASH_ECC_STATUS = 0x0050,
2739 + NFLASH_ECC_CONTROL = 0x0054,
2740 + NFLASH_ECC_OOB = 0x005c,
2741 + NFLASH_ECC_CODE_GEN0 = 0x0060,
2742 + NFLASH_ECC_CODE_GEN1 = 0x0064,
2743 + NFLASH_ECC_CODE_GEN2 = 0x0068,
2744 + NFLASH_ECC_CODE_GEN3 = 0x006C,
2745 + NFLASH_FIFO_CONTROL = 0x0070,
2746 + NFLASH_FIFO_STATUS = 0x0074,
2747 + NFLASH_FIFO_ADDRESS = 0x0078,
2748 + NFLASH_FIFO_DATA = 0x007c,
2749 +};
2750 +
2751 +
2752 +
2753 +//#define FLASH_BASE FLASH_CONTROL_BASE_ADDR
2754 +//#define FLASH_SIZE 0x00800000 //INTEGRATOR_FLASH_SIZE
2755 +
2756 +//#define FLASH_PART_SIZE 8388608
2757 +
2758 +//static unsigned int flash_indirect_access = 0;
2759 +
2760 +
2761 +#ifdef CONFIG_SL2312_SHARE_PIN
2762 +void sl2312flash_enable_nand_flash(void)
2763 +{
2764 + unsigned int reg_val;
2765 +
2766 + reg_val = readl(SL2312_GLOBAL_BASE_ADDR + 0x30);
2767 + reg_val = reg_val & 0xfffffffb;
2768 + writel(reg_val,SL2312_GLOBAL_BASE_ADDR + 0x30);
2769 + return;
2770 +}
2771 +
2772 +void sl2312flash_disable_nand_flash(void)
2773 +{
2774 + unsigned int reg_val;
2775 +
2776 + reg_val = readl(SL2312_GLOBAL_BASE_ADDR + 0x30);
2777 + reg_val = reg_val | 0x00000004;
2778 + writel(reg_val,SL2312_GLOBAL_BASE_ADDR + 0x30);
2779 + return;
2780 +}
2781 +#endif
2782 +
2783 +extern struct nand_oobinfo jffs2_oobinfo;
2784 +/*
2785 + * Define partitions for flash devices
2786 + */
2787 +
2788 +static struct mtd_partition sl2312_partitions[] = {
2789 + { name: "RedBoot", offset: 0x00000000, size: 0x0020000, },
2790 + { name: "Kernel", offset: 0x00020000, size: 0x00200000, },
2791 + { name: "Ramdisk", offset: 0x00220000, size: 0x00280000, },
2792 + { name: "Application", offset: 0x004A0000, size: 0x00320000, },
2793 + { name: "VCTL", offset: 0x007C0000, size: 0x20000, },
2794 + { name: "CurConf", offset: 0x007E0000, size: 0x20000, },
2795 + { name: "FIS directory", offset: 0x007e0000, size: 0x00020000, }
2796 +
2797 +};
2798 +
2799 +
2800 +/*
2801 + * hardware specific access to control-lines
2802 +*/
2803 +static void sl2312_hwcontrol(struct mtd_info *mtd, int cmd)
2804 +{
2805 +
2806 + return ;
2807 +}
2808 +
2809 +static int sl2312_nand_scan_bbt(struct mtd_info *mtd)
2810 +{
2811 + return 0;
2812 +}
2813 +
2814 +/**
2815 + * nand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad
2816 + * @mtd: MTD device structure
2817 + * @ofs: offset relative to mtd start
2818 + */
2819 +static int sl2312_nand_block_isbad (struct mtd_info *mtd, loff_t ofs)
2820 +{
2821 + /* Check for invalid offset */
2822 + if (ofs > mtd->size)
2823 + return -EINVAL;
2824 +
2825 + return sl2312_nand_block_checkbad (mtd, ofs, 1, 0);
2826 +}
2827 +
2828 +/**
2829 + * nand_block_checkbad - [GENERIC] Check if a block is marked bad
2830 + * @mtd: MTD device structure
2831 + * @ofs: offset from device start
2832 + * @getchip: 0, if the chip is already selected
2833 + * @allowbbt: 1, if its allowed to access the bbt area
2834 + *
2835 + * Check, if the block is bad. Either by reading the bad block table or
2836 + * calling of the scan function.
2837 + */
2838 +
2839 +static int sl2312_nand_erase_block(struct mtd_info *mtd, int page)
2840 +{
2841 + int opcode;
2842 + /* Send commands to erase a page */
2843 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
2844 +
2845 + if(mtd->oobblock > 528)
2846 + FLASH_WRITE_REG(NFLASH_COUNT, 0x7f0fff21); // 3 address & 2 command
2847 + else
2848 + FLASH_WRITE_REG(NFLASH_COUNT, 0x7f0fff11); // 2 address & 2 command
2849 +
2850 + FLASH_WRITE_REG(NFLASH_CMD_ADDR, 0x0000d060); // write read id command
2851 + FLASH_WRITE_REG(NFLASH_ADDRESS, page); //write address 0x00
2852 +
2853 +
2854 +
2855 + /* read maker code */
2856 + opcode = 0x80003000|DWIDTH|CHIP_EN; //set start bit & 8bits write command
2857 + FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
2858 +
2859 + while(opcode&0x80000000) //polling flash access 31b
2860 + {
2861 + opcode=FLASH_READ_REG(NFLASH_ACCESS);
2862 + //sl2312_flash_delay();
2863 + schedule();
2864 + //cond_resched();
2865 + }
2866 +}
2867 +
2868 +void sl2312_flash_delay(void)
2869 +{
2870 + int i;
2871 +
2872 + for(i=0; i<50; i++)
2873 + i=i;
2874 +}
2875 +
2876 +static int sl2312_nand_block_checkbad (struct mtd_info *mtd, loff_t ofs, int getchip, int allowbbt)
2877 +{
2878 + struct nand_chip *this = mtd->priv;
2879 +
2880 + if (!this->bbt)
2881 + return this->block_bad(mtd, ofs, getchip);
2882 +
2883 + /* Return info from the table */
2884 + return nand_isbad_bbt (mtd, ofs, allowbbt);
2885 +}
2886 +
2887 +/**
2888 + * nand_block_markbad - [MTD Interface] Mark the block at the given offset as bad
2889 + * @mtd: MTD device structure
2890 + * @ofs: offset relative to mtd start
2891 + */
2892 +static int sl2312_nand_block_markbad (struct mtd_info *mtd, loff_t ofs)
2893 +{
2894 + struct nand_chip *this = mtd->priv;
2895 + int ret;
2896 +
2897 + if ((ret = sl2312_nand_block_isbad(mtd, ofs))) {
2898 + /* If it was bad already, return success and do nothing. */
2899 + if (ret > 0)
2900 + return 0;
2901 + return ret;
2902 + }
2903 +
2904 + return this->block_markbad(mtd, ofs);
2905 +}
2906 +
2907 +/*
2908 + * Get chip for selected access
2909 + */
2910 +static inline void sl2312_nand_get_chip (struct nand_chip *this, struct mtd_info *mtd, int new_state, int *erase_state)
2911 +{
2912 +
2913 + DECLARE_WAITQUEUE (wait, current);
2914 +
2915 + /*
2916 + * Grab the lock and see if the device is available
2917 + * For erasing, we keep the spinlock until the
2918 + * erase command is written.
2919 + */
2920 +retry:
2921 + spin_lock_bh (&this->chip_lock);
2922 +
2923 + if (this->state == FL_READY) {
2924 + this->state = new_state;
2925 + if (new_state != FL_ERASING)
2926 + spin_unlock_bh (&this->chip_lock);
2927 + return;
2928 + }
2929 +
2930 + if (this->state == FL_ERASING) {
2931 + if (new_state != FL_ERASING) {
2932 + this->state = new_state;
2933 + spin_unlock_bh (&this->chip_lock);
2934 + this->select_chip(mtd, 0); /* select in any case */
2935 + this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2936 + return;
2937 + }
2938 + }
2939 +
2940 + set_current_state (TASK_UNINTERRUPTIBLE);
2941 + add_wait_queue (&this->wq, &wait);
2942 + spin_unlock_bh (&this->chip_lock);
2943 + schedule ();
2944 + remove_wait_queue (&this->wq, &wait);
2945 + goto retry;
2946 +}
2947 +
2948 +/*
2949 +* read device ready pin
2950 +*/
2951 +static int sl2312_device_ready(struct mtd_info *mtd)
2952 +{
2953 + int ready;
2954 +
2955 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
2956 + FLASH_WRITE_REG(NFLASH_COUNT, 0x7f000070); //set only command no address and two data
2957 +
2958 + FLASH_WRITE_REG(NFLASH_CMD_ADDR, 0x00000070); //write read status command
2959 +
2960 +
2961 + ready = 0x80002000|DWIDTH|CHIP_EN; //set start bit & 8bits read command
2962 + FLASH_WRITE_REG(NFLASH_ACCESS, ready);
2963 +
2964 + while(ready&0x80000000) //polling flash access 31b
2965 + {
2966 + ready=FLASH_READ_REG(NFLASH_ACCESS);
2967 + //sl2312_flash_delay();
2968 + schedule();
2969 + }
2970 + FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
2971 + ready=FLASH_READ_REG(NFLASH_DATA)&0xff;
2972 + return ready;
2973 +}
2974 +void sl2312_enable_hwecc(struct mtd_info *mtd, int mode)
2975 +{
2976 + /* reset first */
2977 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x80000001); //set 31b = 0
2978 +
2979 +}
2980 +
2981 +
2982 +void sl2312_device_setup(void)
2983 +{
2984 +
2985 +}
2986 +static u_char sl2312_nand_read_byte(struct mtd_info *mtd)
2987 +{
2988 +
2989 + unsigned int data=0, page=0, col=0, tmp, i;
2990 +
2991 + printk ("**************************sl2312_nand_read_byte !! \n");
2992 + //page = FLASH_READ_REG(NFLASH_ADDRESS)&0xffffff00;
2993 + //col = FLASH_READ_REG(NFLASH_ADDRESS)&0x000000ff;
2994 + page = nand_page;
2995 + col = nand_col;
2996 + for(i=0;i<(mtd->oobblock+mtd->oobsize);i++)
2997 + {
2998 + if(i==col)
2999 + data = FLASH_READ_DATA(page*mtd->oobblock +i);
3000 + else
3001 + tmp = FLASH_READ_DATA(page*mtd->oobblock +i);
3002 + }
3003 + return data&0xff;
3004 +}
3005 +
3006 +static void sl2312_nand_write_byte(struct mtd_info *mtd, u_char byte)
3007 +{
3008 + //struct nand_chip *this = mtd->priv;
3009 + unsigned int page=0, col=0, i;
3010 + u_char *databuf,oobbuf[mtd->oobsize];
3011 + size_t retlen;
3012 + retlen=0;
3013 + printk ("********************sl2312_nand_write_byte !! \n");
3014 + page = nand_page;
3015 + col = nand_col;
3016 + databuf = kmalloc (mtd->oobsize+mtd->oobblock,GFP_KERNEL);
3017 +
3018 + if (!databuf) {
3019 + printk ("sl2312_nand_write_byte : Unable to allocate SL2312 NAND MTD device structure.\n");
3020 +
3021 + }
3022 +
3023 + for(i=0;i<(mtd->oobblock+mtd->oobsize);i++)
3024 + databuf[i] = FLASH_READ_DATA(page*mtd->oobblock +i);
3025 +
3026 + databuf[col] = byte;
3027 + sl2312_nand_write_ecc (mtd, page, mtd->oobblock, &retlen, databuf, oobbuf, NULL);
3028 +
3029 +}
3030 +
3031 +static void sl2312_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
3032 +{
3033 + int i, page=0,col=0;
3034 + struct nand_chip *this = mtd->priv;
3035 + u_char *databuf, *oobbuf;
3036 + size_t retlen;
3037 + retlen=0;
3038 +
3039 +
3040 + printk ("***********************sl2312_nand_write_buf !! \n");
3041 + databuf = &(this->data_buf[0]);
3042 + oobbuf = &(this->data_buf[mtd->oobblock]);
3043 + for (i = 0; i < mtd->oobsize; i++)
3044 + oobbuf[i] = 0xff;
3045 +
3046 + if(len < mtd->oobblock)
3047 + {
3048 + //addr = FLASH_READ_REG(NFLASH_ADDRESS);
3049 + //page = FLASH_READ_REG(NFLASH_ADDRESS)&0xffffff00;
3050 + //col = FLASH_READ_REG(NFLASH_ADDRESS)&0x000000ff;
3051 + page = nand_page;
3052 + col = nand_col;
3053 +
3054 + sl2312_nand_read_ecc (mtd, page, mtd->oobblock , &retlen, databuf, oobbuf, NULL);
3055 +
3056 + for(i=col;i<len;i++)
3057 + databuf[col+i] = buf[i];
3058 +
3059 + sl2312_nand_write_ecc (mtd, page, mtd->oobblock, &retlen, databuf, oobbuf, NULL);
3060 +
3061 + }
3062 +
3063 +}
3064 +
3065 +static void sl2312_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
3066 +{
3067 + int i, page=0,col=0,addr=0,tmp=0;
3068 + //struct nand_chip *this = mtd->priv;
3069 + printk ("********************sl2312_nand_read_buf !! \n");
3070 + if(len < mtd->oobblock)
3071 + {
3072 + //addr = FLASH_READ_REG(NFLASH_ADDRESS);
3073 + //page = FLASH_READ_REG(NFLASH_ADDRESS)&0xffffff00;
3074 + //col = FLASH_READ_REG(NFLASH_ADDRESS)&0x000000ff;
3075 + page = nand_page;
3076 + col = nand_col;
3077 + for (i=col; i<((mtd->oobblock+mtd->oobsize)-col); i++)
3078 + {
3079 + if(i<len)
3080 + buf[i] = FLASH_READ_DATA(addr+i);
3081 + else
3082 + tmp = FLASH_READ_DATA(addr+i);
3083 + }
3084 + }
3085 +}
3086 +
3087 +static int sl2312_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
3088 +{
3089 + int i;
3090 + //struct nand_chip *this = mtd->priv;
3091 + u_char *datatmp, *oobtmp;
3092 + size_t retlen;
3093 + retlen=0;
3094 +
3095 + datatmp = kmalloc (mtd->oobblock,GFP_KERNEL);
3096 + oobtmp = kmalloc (mtd->oobsize,GFP_KERNEL);
3097 +
3098 + if ((!datatmp)||(!oobtmp)) {
3099 + printk ("sl2312_nand_verify_buf : Unable to allocate SL2312 NAND MTD device structure.\n");
3100 +
3101 + }
3102 + //page = nand_page;
3103 + for(i=0;i<mtd->oobblock;i++)
3104 + datatmp[i] = FLASH_READ_DATA(nand_page*mtd->oobblock +i);
3105 + /* read oobdata */
3106 + for (i = 0; i < mtd->oobsize; i++)
3107 + oobtmp[i] = FLASH_READ_DATA(nand_page*mtd->oobblock + mtd->oobblock + i);
3108 +
3109 + if(len==mtd->oobblock)
3110 + {
3111 + for (i=0; i<len; i++)
3112 + {
3113 + if (buf[i] != datatmp[i])
3114 + {
3115 + kfree(datatmp);
3116 + kfree(oobtmp);
3117 + printk("Data verify error -> page: %x, byte: %x \n",nand_page,i);
3118 + return i;
3119 + }
3120 + }
3121 + }
3122 + else if(len == mtd->oobsize)
3123 + {
3124 + for (i=0; i<len; i++)
3125 + {
3126 + if (buf[i] != oobtmp[i])
3127 + {
3128 + kfree(datatmp);
3129 + kfree(oobtmp);
3130 + printk("OOB verify error -> page: %x, byte: %x \n",nand_page,i);
3131 + return i;
3132 + }
3133 + }
3134 + }
3135 + else
3136 + {
3137 + printk (KERN_WARNING "sl2312_nand_verify_buf : verify length not match 0x%08x\n", len);
3138 + kfree(datatmp);
3139 + kfree(oobtmp);
3140 + return -1;
3141 + }
3142 +
3143 + kfree(datatmp);
3144 + kfree(oobtmp);
3145 + return 0;
3146 +}
3147 +
3148 +/*
3149 + * Send command to NAND device
3150 + */
3151 +static void sl2312_nand_command (struct mtd_info *mtd, unsigned command, int column, int page_addr)
3152 +{
3153 + register struct nand_chip *this = mtd->priv;
3154 + int opcode;
3155 +
3156 +
3157 + /*
3158 + * program and erase have their own busy handlers
3159 + * status and sequential in needs no delay
3160 + */
3161 + switch (command) {
3162 +
3163 + case NAND_CMD_PAGEPROG:
3164 + case NAND_CMD_ERASE1:
3165 + case NAND_CMD_ERASE2:
3166 + case NAND_CMD_SEQIN:
3167 + case NAND_CMD_STATUS:
3168 + case NAND_CMD_READ0:
3169 +
3170 + /*
3171 + * Write out the command to the device.
3172 + */
3173 + if (column != -1 || page_addr != -1) {
3174 +
3175 + /* Serially input address */
3176 + if (column != -1)
3177 + //FLASH_WRITE_REG(NFLASH_ADDRESS,column);
3178 + nand_col=column;
3179 +
3180 + opcode = FLASH_READ_REG(NFLASH_ADDRESS);
3181 +
3182 + if (page_addr != -1)
3183 + //FLASH_WRITE_REG(NFLASH_ADDRESS,opcode|(page_addr<<8));
3184 + nand_page = page_addr;
3185 +
3186 + }
3187 + return;
3188 +
3189 + case NAND_CMD_RESET:
3190 + if (this->dev_ready)
3191 + break;
3192 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
3193 + FLASH_WRITE_REG(NFLASH_COUNT, 0x7f0fff70); //set only command and no other data
3194 + FLASH_WRITE_REG(NFLASH_CMD_ADDR, NAND_CMD_RESET); //write reset command
3195 +
3196 + opcode = 0x80002000|DWIDTH|CHIP_EN; //set start bit & 8bits read command
3197 + FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
3198 +
3199 + while(opcode&0x80000000) //polling flash access 31b
3200 + {
3201 + opcode=FLASH_READ_REG(NFLASH_ACCESS);
3202 + //sl2312_flash_delay();
3203 + schedule();
3204 + }
3205 + while ( !(sl2312_device_ready(mtd) & 0x40));
3206 + {
3207 + FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3208 + //sl2312_flash_delay();
3209 + schedule();
3210 + return;
3211 + }
3212 + /* This applies to read commands */
3213 + default:
3214 + /*
3215 + * If we don't have access to the busy pin, we apply the given
3216 + * command delay
3217 + */
3218 + if (!this->dev_ready) {
3219 + udelay (this->chip_delay);
3220 + FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3221 + return;
3222 + }
3223 + }
3224 +
3225 + /* wait until command is processed */
3226 + while (!this->dev_ready(mtd));
3227 +
3228 +}
3229 +/*Add function*/
3230 +static void nand_read_id(int chip_no, unsigned char *id)
3231 +{
3232 + unsigned int opcode, i;
3233 +
3234 + if(chip_no==0)
3235 + CHIP_EN = NFLASH_CHIP0_EN;
3236 + else
3237 + CHIP_EN = NFLASH_CHIP1_EN;
3238 +
3239 + opcode = FLASH_READ_REG(NFLASH_TYPE);
3240 +
3241 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
3242 + if((opcode&0x00000300)<=0x00000100)
3243 + FLASH_WRITE_REG(NFLASH_COUNT, 0x7f000100); //set only command & address and two data
3244 + else
3245 + FLASH_WRITE_REG(NFLASH_COUNT, 0x7f000300); //set only command & address and 4 data
3246 +
3247 + FLASH_WRITE_REG(NFLASH_CMD_ADDR, 0x00000090); //write read id command
3248 + FLASH_WRITE_REG(NFLASH_ADDRESS, 0x00000000); //write address 0x00
3249 +
3250 + /* read maker code */
3251 + opcode = 0x80002000|DWIDTH|CHIP_EN;//|chip0_en; //set start bit & 8bits read command
3252 + FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
3253 + opcode=FLASH_READ_REG(NFLASH_ACCESS);
3254 + while(opcode&0x80000000) //polling flash access 31b
3255 + {
3256 + opcode=FLASH_READ_REG(NFLASH_ACCESS);
3257 + //sl2312_flash_delay();
3258 + schedule();
3259 + }
3260 +
3261 + opcode = FLASH_READ_REG(NFLASH_DATA);
3262 + if(DWIDTH==NFLASH_WiDTH16)
3263 + {
3264 + id[0] = opcode&0xff;
3265 + id[1] = (opcode&0xff00)>>8;
3266 + }
3267 + else
3268 + {
3269 + id[0] = opcode&0xff;
3270 + opcode = 0x80002000|DWIDTH|CHIP_EN;//|chip0_en; //set start bit & 8bits read command
3271 + FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
3272 + opcode=FLASH_READ_REG(NFLASH_ACCESS);
3273 + while(opcode&0x80000000) //polling flash access 31b
3274 + {
3275 + opcode=FLASH_READ_REG(NFLASH_ACCESS);
3276 + //sl2312_flash_delay();
3277 + schedule();
3278 + }
3279 + opcode = FLASH_READ_REG(NFLASH_DATA);
3280 + id[1] = (opcode&0xff00)>>8;
3281 +
3282 + opcode=FLASH_READ_REG(NFLASH_TYPE);
3283 + if((opcode&0x300)>0x100)
3284 + {
3285 + for(i=0;i<2;i++)
3286 + {
3287 + //data cycle 3 & 4 ->not use
3288 + opcode = 0x80002000|DWIDTH|CHIP_EN;//set start bit & 8bits read command
3289 + FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
3290 + opcode=FLASH_READ_REG(NFLASH_ACCESS);
3291 + while(opcode&0x80000000) //polling flash access 31b
3292 + {
3293 + opcode=FLASH_READ_REG(NFLASH_ACCESS);
3294 + //sl2312_flash_delay();
3295 + schedule();
3296 + }
3297 +
3298 + opcode=FLASH_READ_REG(NFLASH_DATA);
3299 + id[2+i] = (opcode&(0xff0000<<i*8))>>(8*(2+i));
3300 + }
3301 + }
3302 + }
3303 + FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3304 +}
3305 +
3306 +/*
3307 + * NAND erase a block
3308 + */
3309 +static int sl2312_nand_erase (struct mtd_info *mtd, struct erase_info *instr, int allowbbt)
3310 +{
3311 + int page, len, status, pages_per_block, ret, chipnr;
3312 + struct nand_chip *this = mtd->priv;
3313 +
3314 + DEBUG (MTD_DEBUG_LEVEL3,
3315 + "nand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len);
3316 +
3317 + /* Start address must align on block boundary */
3318 + if (instr->addr & ((1 << this->phys_erase_shift) - 1)) {
3319 + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
3320 + return -EINVAL;
3321 + }
3322 +
3323 + /* Length must align on block boundary */
3324 + if (instr->len & ((1 << this->phys_erase_shift) - 1)) {
3325 + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Length not block aligned\n");
3326 + return -EINVAL;
3327 + }
3328 +
3329 + /* Do not allow erase past end of device */
3330 + if ((instr->len + instr->addr) > mtd->size) {
3331 + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Erase past end of device\n");
3332 + return -EINVAL;
3333 + }
3334 +
3335 + instr->fail_addr = 0xffffffff;
3336 +
3337 + /* Grab the lock and see if the device is available */
3338 + sl2312_nand_get_chip (this, mtd, FL_ERASING, NULL);
3339 +
3340 + /* Shift to get first page */
3341 + page = (int) (instr->addr >> this->page_shift);
3342 + chipnr = (int) (instr->addr >> this->chip_shift);
3343 +
3344 + /* Calculate pages in each block */
3345 + pages_per_block = 1 << (this->phys_erase_shift - this->page_shift);
3346 +
3347 + /* Select the NAND device */
3348 + //this->select_chip(mtd, chipnr);
3349 + this->select_chip(mtd, 0);
3350 +
3351 + /* Check the WP bit */
3352 + /* Check, if it is write protected */
3353 + status = sl2312_device_ready(mtd);
3354 + if (!(status & 0x80)) {
3355 + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Device is write protected!!!\n");
3356 + instr->state = MTD_ERASE_FAILED;
3357 + goto erase_exit;
3358 + }
3359 +
3360 + /* Loop through the pages */
3361 + len = instr->len;
3362 +
3363 + instr->state = MTD_ERASING;
3364 +
3365 + while (len) {
3366 + /* Check if we have a bad block, we do not erase bad blocks ! */
3367 + if (this->block_bad(mtd, ((loff_t) page) << this->page_shift, 0)) {
3368 + printk (KERN_WARNING "nand_erase: attempt to erase a bad block at page 0x%08x\n", page);
3369 + //instr->state = MTD_ERASE_FAILED;
3370 + //goto erase_exit;
3371 + }
3372 +
3373 + /* Invalidate the page cache, if we erase the block which contains
3374 + the current cached page */
3375 + if (page <= this->pagebuf && this->pagebuf < (page + pages_per_block))
3376 + this->pagebuf = -1;
3377 + /////////
3378 +
3379 + ///* Send commands to erase a page */
3380 + //FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
3381 + //
3382 + //if(mtd->oobblock > 528)
3383 + // FLASH_WRITE_REG(NFLASH_COUNT, 0x7f0fff21); // 3 address & 2 command
3384 + //else
3385 + // FLASH_WRITE_REG(NFLASH_COUNT, 0x7f0fff11); // 2 address & 2 command
3386 + //
3387 + //FLASH_WRITE_REG(NFLASH_CMD_ADDR, 0x0000d060); // write read id command
3388 + //FLASH_WRITE_REG(NFLASH_ADDRESS, page); //write address 0x00
3389 + //
3390 + //
3391 + //
3392 + ///* read maker code */
3393 + //opcode = 0x80003000|DWIDTH|CHIP_EN; //set start bit & 8bits write command
3394 + //FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
3395 + //
3396 + //while(opcode&0x80000000) //polling flash access 31b
3397 + //{
3398 + // opcode=FLASH_READ_REG(NFLASH_ACCESS);
3399 + // //sl2312_flash_delay();
3400 + // schedule();
3401 + // //cond_resched();
3402 + //}
3403 + sl2312_nand_erase_block(mtd, page);
3404 + //////////////
3405 + status = this->waitfunc (mtd, this, FL_ERASING);
3406 + /* See if block erase succeeded */
3407 + if (status & 0x01) {
3408 + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: " "Failed erase, page 0x%08x\n", page);
3409 + instr->state = MTD_ERASE_FAILED;
3410 + instr->fail_addr = (page << this->page_shift);
3411 + goto erase_exit;
3412 + }
3413 +
3414 + /* Increment page address and decrement length */
3415 + len -= (1 << this->phys_erase_shift);
3416 + page += pages_per_block;
3417 +
3418 + /* Check, if we cross a chip boundary */
3419 + if (len && !(page & this->pagemask)) {
3420 + chipnr++;
3421 + this->select_chip(mtd, 0);
3422 + this->select_chip(mtd, 0);
3423 + }
3424 + //sl2312_flash_delay();
3425 + schedule();
3426 + //cond_resched();
3427 + }
3428 + instr->state = MTD_ERASE_DONE;
3429 +
3430 +erase_exit:
3431 + /* De-select the NAND device */
3432 + this->select_chip(mtd, 0);
3433 + spin_unlock_bh (&this->chip_lock);
3434 +
3435 + ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;;
3436 + /* Do call back function */
3437 + if (!ret && instr->callback)
3438 + instr->callback (instr);
3439 +
3440 + /* The device is ready */
3441 + spin_lock_bh (&this->chip_lock);
3442 + this->state = FL_READY;
3443 + spin_unlock_bh (&this->chip_lock);
3444 + FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3445 + /* Return more or less happy */
3446 + return ret;
3447 +}
3448 +
3449 +static void sl2312_nand_select_chip(struct mtd_info *mtd, int chip)
3450 +{
3451 + //struct nand_chip *this = mtd->priv;
3452 +
3453 + switch(chip) {
3454 + case -1:
3455 + CHIP_EN = NFLASH_CHIP0_EN;
3456 + break;
3457 + case 0:
3458 + CHIP_EN = NFLASH_CHIP0_EN;
3459 + break;
3460 + case 1:
3461 + CHIP_EN = NFLASH_CHIP1_EN;
3462 + break;
3463 + default:
3464 + CHIP_EN = NFLASH_CHIP0_EN;
3465 + break;
3466 + }
3467 +}
3468 +
3469 +/**
3470 + * nand_default_block_markbad - [DEFAULT] mark a block bad
3471 + * @mtd: MTD device structure
3472 + * @ofs: offset from device start
3473 + *
3474 + * This is the default implementation, which can be overridden by
3475 + * a hardware specific driver.
3476 +*/
3477 +static int sl2312_nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
3478 +{
3479 + struct nand_chip *this = mtd->priv;
3480 + u_char buf[2] = {0, 0};
3481 + size_t retlen;
3482 + int block;
3483 +
3484 + /* Get block number */
3485 + block = ((int) ofs) >> this->bbt_erase_shift;
3486 + this->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
3487 +
3488 + /* Do we have a flash based bad block table ? */
3489 + if (this->options & NAND_USE_FLASH_BBT)
3490 + return nand_update_bbt (mtd, ofs);
3491 +
3492 + /* We write two bytes, so we dont have to mess with 16 bit access */
3493 + ofs += mtd->oobsize + (this->badblockpos & ~0x01);
3494 + return sl2312_nand_write_oob (mtd, ofs , 2, &retlen, buf);
3495 +}
3496 +
3497 +/* Appropriate chip should already be selected */
3498 +static int sl2312_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)//(struct mtd_info *mtd, unsigned long page, )
3499 +{
3500 + u_char *buf, *oobbuf;
3501 + size_t retlen;
3502 + unsigned long page, chipnr;
3503 + struct nand_chip *this = mtd->priv;
3504 +
3505 + if (getchip) {
3506 + page = (int)(ofs >> this->page_shift);
3507 + chipnr = (int)(ofs >> this->chip_shift);
3508 +
3509 + /* Grab the lock and see if the device is available */
3510 + sl2312_nand_get_chip (this, mtd, FL_READING, NULL);
3511 + /* Select the NAND device */
3512 + this->select_chip(mtd, chipnr);
3513 + } else
3514 + page = (int) ofs;
3515 +
3516 + buf = kmalloc (mtd->oobblock,GFP_KERNEL);
3517 + oobbuf = kmalloc (mtd->oobsize,GFP_KERNEL);
3518 +
3519 + if ((!buf)||(!oobbuf)) {
3520 + printk ("sl2312_nand_block_bad : Unable to allocate SL2312 NAND MTD device structure.\n");
3521 +
3522 + }
3523 +
3524 + sl2312_nand_read_ecc (mtd, page, mtd->oobblock , &retlen, buf, oobbuf, NULL);
3525 +
3526 +
3527 + if(((mtd->oobblock < 528)&&(oobbuf[5] != 0xff))||((mtd->oobblock > 528)&&(oobbuf[0] != 0xff)))
3528 + {
3529 + kfree(buf);
3530 + kfree(oobbuf);
3531 + return 1;
3532 + }
3533 +
3534 + kfree(buf);
3535 + kfree(oobbuf);
3536 + return 0;
3537 +}
3538 +
3539 +/*
3540 +* Use NAND read ECC
3541 +*/
3542 +static int sl2312_nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf)
3543 +{
3544 + return sl2312_nand_read_ecc (mtd, from, len, retlen, buf, NULL, NULL);
3545 +}
3546 +
3547 +/*
3548 + * NAND read with ECC
3549 + */
3550 +static int sl2312_nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len,
3551 + size_t * retlen, u_char * buf, u_char * oob_buf, struct nand_oobinfo *oobsel)
3552 +{
3553 + int j, col, page, opcode, i;
3554 + int end=0;//, ecc=0;//, end_page=0;
3555 + int erase_state = 0;
3556 + int read = 0, oob = 0, ecc_failed = 0;//, ecc_status = 0
3557 + struct nand_chip *this = mtd->priv;
3558 + u_char *data_poi, *oob_data = oob_buf;
3559 + //u_char ecc_calc[6];
3560 + //u_char ecc_code[6];
3561 + int eccmode;
3562 + int *oob_config;
3563 +
3564 +
3565 +
3566 + // use chip default if zero
3567 + if (oobsel == NULL)
3568 + oobsel = &mtd->oobinfo;
3569 +
3570 + eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE;
3571 + oob_config = oobsel->eccpos;
3572 +
3573 + DEBUG (MTD_DEBUG_LEVEL3, "nand_read_ecc: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
3574 +
3575 + /* Do not allow reads past end of device */
3576 + if ((from + len) > mtd->size) {
3577 + DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: Attempt read beyond end of device\n");
3578 + *retlen = 0;
3579 + return -EINVAL;
3580 + }
3581 +
3582 + /* Grab the lock and see if the device is available */
3583 + sl2312_nand_get_chip (this, mtd ,FL_READING, &erase_state);
3584 +
3585 + /* Select the NAND device */
3586 + this->select_chip(mtd, 0);
3587 +
3588 + /* First we calculate the starting page */
3589 + page = from >> this->page_shift;
3590 +
3591 + //end_page = mtd->oobblock + mtd->oobsize;
3592 + end = mtd->oobblock;
3593 + //ecc = mtd->eccsize;
3594 + /* Get raw starting column */
3595 + col = (from & (mtd->oobblock - 1));
3596 +
3597 +
3598 + /* Send the read command */
3599 + //this->cmdfunc (mtd, NAND_CMD_READ0, 0x00, page);
3600 +
3601 + /* Loop until all data read */
3602 + FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3603 + while (read < len) {
3604 +
3605 + //udelay(1200);
3606 + /* If we have consequent page reads, apply delay or wait for ready/busy pin */
3607 + if (read) {
3608 + if (!this->dev_ready)
3609 + udelay (this->chip_delay);
3610 + else
3611 + while (!this->dev_ready(mtd));
3612 + }
3613 +
3614 + /*
3615 + * If the read is not page aligned, we have to read into data buffer
3616 + * due to ecc, else we read into return buffer direct
3617 + */
3618 + if (!col && (len - read) >= end)
3619 + data_poi = &buf[read];
3620 + else
3621 + data_poi = this->data_buf;
3622 +
3623 + /* get oob area, if we have no oob buffer from fs-driver */
3624 + if (!oob_buf) {
3625 + oob_data = &this->data_buf[end];
3626 + oob = 0;
3627 + }
3628 +
3629 + j = 0;
3630 + switch (eccmode) {
3631 + case NAND_ECC_NONE: { /* No ECC, Read in a page */
3632 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
3633 + break;
3634 + }
3635 +
3636 + case NAND_ECC_SOFT: /* Software ECC 3/256: Read in a page + oob data */
3637 + break;
3638 +
3639 + case NAND_ECC_HW3_256: /* Hardware ECC 3 byte /256 byte data: Read in first 256 byte, get ecc, */
3640 + break;
3641 +
3642 + case NAND_ECC_HW3_512:
3643 + case NAND_ECC_HW6_512: /* Hardware ECC 3/6 byte / 512 byte data : Read in a page */
3644 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x80000001); //set 31b = 0
3645 + break;
3646 +
3647 + default:
3648 + printk (KERN_WARNING "Invalid NAND_ECC_MODE %d\n", this->eccmode);
3649 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0);
3650 + //BUG();
3651 + }//end switch
3652 +
3653 + for(i=0;i<end;i++)
3654 + {
3655 + //udelay(7);
3656 + data_poi[i] = FLASH_READ_DATA(page*mtd->oobblock +i);
3657 + }
3658 + /* read oobdata */
3659 + for (i = 0; i < mtd->oobsize; i++)
3660 + {
3661 + //udelay(7);
3662 + oob_data[oob + i] = FLASH_READ_DATA(page*mtd->oobblock +end+i);
3663 + }
3664 +
3665 + /* Skip ECC, if not active */
3666 + if (eccmode == NAND_ECC_NONE)
3667 + goto readdata;
3668 +
3669 + // compare ecc and correct data
3670 +
3671 + opcode=FLASH_READ_REG(NFLASH_ECC_STATUS);
3672 + while(!(opcode&0x80000000)) //polling flash access 31b
3673 + {
3674 + opcode=FLASH_READ_REG(NFLASH_ECC_STATUS);
3675 + //sl2312_flash_delay();
3676 + schedule();
3677 + }
3678 + for(j=0;j<(end/512);j++)
3679 + {//for 2k page
3680 +
3681 + opcode = 0x00000000|oob_data[mtd->oobsize-3-4*j]<<16|oob_data[mtd->oobsize-2-4*j]<<8|oob_data[mtd->oobsize-1-4*j];
3682 +
3683 + //opcode=FLASH_READ_REG(NFLASH_ECC_CODE_GEN0+(j*4));
3684 +
3685 + FLASH_WRITE_REG(NFLASH_ECC_OOB, opcode);
3686 + opcode = 0x00000000|(j<<8); //select ECC code generation 0
3687 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, opcode); //???
3688 +
3689 + opcode=FLASH_READ_REG(NFLASH_ECC_STATUS);
3690 + if((opcode&0x00000003)==0x03)
3691 + {
3692 + printk (KERN_WARNING "\nPageRead Uncorrectable error !!\n");
3693 + ecc_failed++;
3694 + }
3695 + else if((opcode&0x00000003)==0x01)
3696 + {
3697 + printk (KERN_WARNING "\nPageRead One bit data error !!");
3698 + // correct data
3699 + if((data_poi[(opcode&0xff80)>>7]>>((opcode&0x38)>>3))%1)
3700 + data_poi[(opcode&0xff80)>>7] &= ~(1<<((opcode&0x38)>>3));
3701 + else
3702 + data_poi[(opcode&0xff80)>>7] |= (1<<((opcode&0x38)>>3));
3703 +
3704 + }
3705 + else if((opcode&0x00000003)==0x02)
3706 + {
3707 + printk (KERN_WARNING "\nPageRead One bit ECC error !!\n");
3708 + }
3709 + else if((opcode&0x00000003)==0x00)
3710 + {
3711 +
3712 + }
3713 +
3714 + }//for 2k page
3715 +readdata:
3716 + if (col || (len - read) < end) {
3717 + for (j = col; j < end && read < len; j++)
3718 + buf[read++] = data_poi[j];
3719 + } else
3720 + read += mtd->oobblock;
3721 + /* For subsequent reads align to page boundary. */
3722 + col = 0;
3723 + /* Increment page address */
3724 + page++;
3725 + schedule();
3726 + }
3727 + /* De-select the NAND device */
3728 + //this->select_chip(mtd, -1);
3729 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
3730 + FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_INDIRECT);
3731 + /* Wake up anyone waiting on the device */
3732 + spin_lock_bh (&this->chip_lock);
3733 + this->state = FL_READY;
3734 + wake_up (&this->wq);
3735 + spin_unlock_bh (&this->chip_lock);
3736 +
3737 + /*
3738 + * Return success, if no ECC failures, else -EIO
3739 + * fs driver will take care of that, because
3740 + * retlen == desired len and result == -EIO
3741 + */
3742 + *retlen = read;
3743 + return ecc_failed ? -EIO : 0;
3744 +}
3745 +
3746 +/*
3747 + * Wait for command done. This applies to erase and program only
3748 + * Erase can take up to 400ms and program up to 20ms according to
3749 + * general NAND and SmartMedia specs
3750 + *
3751 +*/
3752 +static int sl2312_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this, int state)
3753 +{
3754 + unsigned long timeo = jiffies;
3755 + int status, opcode;
3756 +
3757 + if (state == FL_ERASING)
3758 + timeo += (HZ * 400) / 1000;
3759 + else
3760 + timeo += (HZ * 20) / 1000;
3761 +
3762 + spin_lock_bh (&this->chip_lock);
3763 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
3764 + FLASH_WRITE_REG(NFLASH_COUNT, 0x007f000070); //set only command no address and two data
3765 +
3766 + FLASH_WRITE_REG(NFLASH_CMD_ADDR, 0x00000070); //write read status command
3767 +
3768 +
3769 + opcode = 0x80002000|DWIDTH|CHIP_EN; //set start bit & 8bits read command
3770 + FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
3771 +
3772 + while(opcode&0x80000000) //polling flash access 31b
3773 + {
3774 + opcode=FLASH_READ_REG(NFLASH_ACCESS);
3775 + //sl2312_flash_delay();
3776 + schedule();
3777 + }
3778 +
3779 + while (time_before(jiffies, timeo)) {
3780 + /* Check, if we were interrupted */
3781 + if (this->state != state) {
3782 + spin_unlock_bh (&this->chip_lock);
3783 + FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3784 + return 0;
3785 + }
3786 + if (this->dev_ready) {
3787 + if (this->dev_ready(mtd))
3788 + break;
3789 + }
3790 + if (FLASH_READ_REG(NFLASH_DATA) & 0x40)
3791 + break;
3792 +
3793 + spin_unlock_bh (&this->chip_lock);
3794 + yield ();
3795 + spin_lock_bh (&this->chip_lock);
3796 + }
3797 + status = FLASH_READ_REG(NFLASH_DATA)&0xff;
3798 + spin_unlock_bh (&this->chip_lock);
3799 + FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3800 + return status;
3801 +}
3802 +
3803 +static int sl2312_nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf)
3804 +{
3805 + int i, col, page, j=0;
3806 + //int erase_state = 0;
3807 + struct nand_chip *this = mtd->priv;
3808 + u_char *databuf, *oobbuf;
3809 +
3810 + databuf = &this->data_buf[0];
3811 + oobbuf = &this->data_buf[mtd->oobblock];
3812 + for (i = 0; i < mtd->oobsize; i++)
3813 + oobbuf[i] = 0xff;
3814 +
3815 + DEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
3816 +
3817 + /* Shift to get page */
3818 + page = ((int) from) >> this->page_shift;
3819 +
3820 + /* Mask to get column */
3821 + col = from & (mtd->oobsize-1); //0x0f;
3822 +
3823 + /* Initialize return length value */
3824 + *retlen = 0;
3825 + sl2312_nand_read_ecc (mtd, page, mtd->oobblock , retlen, databuf, oobbuf, NULL);
3826 + for(i=col,j=0;i<mtd->oobsize||i<(col+len);i++,j++)
3827 + buf[j] = oobbuf[i];
3828 +
3829 + *retlen = j ;
3830 + return 0;
3831 +}
3832 +
3833 +#define NOTALIGNED(x) (x & (mtd->oobblock-1)) != 0
3834 +/*
3835 +* Use NAND write ECC
3836 +*/
3837 +static int sl2312_nand_write (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf)
3838 +{
3839 + return (sl2312_nand_write_ecc (mtd, to, len, retlen, buf, NULL, NULL));
3840 +}
3841 +
3842 +/*
3843 + * NAND write with ECC
3844 + */
3845 +static int sl2312_nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len,
3846 + size_t * retlen, const u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel)
3847 +{
3848 + int page, ret = 0, oob = 0, written = 0;
3849 + struct nand_chip *this = mtd->priv;
3850 +
3851 + DEBUG (MTD_DEBUG_LEVEL3, "nand_write_ecc: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
3852 +
3853 +
3854 + /* Do not allow write past end of device */
3855 + if ((to + len) > mtd->size) {
3856 + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: Attempt to write past end of page\n");
3857 + return -EINVAL;
3858 + }
3859 +
3860 + /* reject writes, which are not page aligned */
3861 + if (NOTALIGNED (to) || NOTALIGNED(len)) {
3862 + printk (KERN_NOTICE "nand_write_ecc: Attempt to write not page aligned data\n");
3863 + return -EINVAL;
3864 + }
3865 +
3866 + // if oobsel is NULL, use chip defaults
3867 + if (oobsel == NULL)
3868 + oobsel = &mtd->oobinfo;
3869 +
3870 + /* Shift to get page */
3871 + page = ((int) to) >> this->page_shift;
3872 +
3873 + /* Grab the lock and see if the device is available */
3874 + sl2312_nand_get_chip (this, mtd, FL_WRITING, NULL);
3875 +
3876 + /* Select the NAND device */
3877 + this->select_chip(mtd, 0);
3878 +
3879 + /* Check the WP bit */
3880 + if (!(sl2312_device_ready(mtd) & 0x80)) {
3881 + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: Device is write protected!!!\n");
3882 + ret = -EIO;
3883 + goto out;
3884 + }
3885 +
3886 + /* Loop until all data is written */
3887 + while (written < len) {
3888 + //udelay(100);
3889 + int cnt = mtd->oobblock;
3890 + this->data_poi = (u_char*) &buf[written];
3891 + /* We use the same function for write and writev */
3892 + if (eccbuf) {
3893 + ret = sl2312_nand_write_page (mtd, this, page, &eccbuf[oob], oobsel);
3894 + oob += mtd->oobsize;
3895 + } else
3896 + ret = sl2312_nand_write_page (mtd, this, page, NULL, oobsel);
3897 +
3898 + if (ret)
3899 + goto out;
3900 +
3901 + /* Update written bytes count */
3902 + written += cnt;
3903 + /* Increment page address */
3904 + page++;
3905 + }
3906 +
3907 +out:
3908 + /* De-select the NAND device */
3909 + //this->select_chip(mtd, -1);
3910 +
3911 + /* Wake up anyone waiting on the device */
3912 + spin_lock_bh (&this->chip_lock);
3913 + this->state = FL_READY;
3914 + wake_up (&this->wq);
3915 + spin_unlock_bh (&this->chip_lock);
3916 +
3917 + *retlen = written;
3918 + return ret;
3919 +}
3920 +
3921 +/*
3922 + * Nand_page_program function is used for write and writev !
3923 + * This function will always program a full page of data
3924 + * If you call it with a non page aligned buffer, you're lost :)
3925 + */
3926 +static int sl2312_nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int page, u_char *oob_buf, struct nand_oobinfo *oobsel)
3927 +{
3928 + int i, j, status, opcode;
3929 + u_char ecc_code[16], *oob_data;
3930 + int eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE;
3931 + //int *oob_config = oobsel->eccpos;
3932 +
3933 + /* pad oob area, if we have no oob buffer from fs-driver */
3934 + if (!oob_buf) {
3935 + oob_data = &this->data_buf[mtd->oobblock];
3936 + for (i = 0; i < mtd->oobsize; i++)
3937 + oob_data[i] = 0xff;
3938 + } else
3939 + oob_data = oob_buf;
3940 +
3941 + /* Send command to begin auto page programming */
3942 +
3943 + memset(oob_data,0xff,mtd->oobsize);
3944 + /* Write out complete page of data, take care of eccmode */
3945 + switch (eccmode) {
3946 + /* No ecc and software ecc 3/256, write all */
3947 + case NAND_ECC_NONE:
3948 + printk (KERN_WARNING "Writing data without ECC to NAND-FLASH is not recommended\n");
3949 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
3950 + break;
3951 + case NAND_ECC_SOFT:
3952 + break;
3953 +
3954 + /* Hardware ecc 3 byte / 256 data, write first half, get ecc, then second, if 512 byte pagesize */
3955 + case NAND_ECC_HW3_256:
3956 + break;
3957 +
3958 + /* Hardware ecc 3 byte / 512 byte data, write full page */
3959 + case NAND_ECC_HW3_512:
3960 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x80000001); //set 31b = 0
3961 +
3962 + /* Hardware ecc 6 byte / 512 byte data, write full page */
3963 + case NAND_ECC_HW6_512:
3964 + break;
3965 +
3966 + default:
3967 + printk (KERN_WARNING "Invalid NAND_ECC_MODE %d\n", this->eccmode);
3968 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
3969 + //BUG();
3970 + }
3971 +
3972 + FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3973 +
3974 + for(i=0;i<mtd->oobblock;i++)
3975 + {
3976 + //udelay(5);
3977 + FLASH_WRITE_DATA((page*mtd->oobblock)+i,this->data_poi[i]);
3978 + }
3979 + ///////////////
3980 + if(eccmode!=NAND_ECC_NONE)
3981 + {
3982 + opcode=FLASH_READ_REG(NFLASH_ECC_STATUS);
3983 + while(!(opcode&0x80000000)) //polling flash access 31b
3984 + {
3985 + opcode=FLASH_READ_REG(NFLASH_ECC_STATUS);
3986 + //sl2312_flash_delay();
3987 + schedule();
3988 + }
3989 +
3990 +
3991 + for(i=0;i<(mtd->oobblock/512);i++)
3992 + {
3993 + opcode=FLASH_READ_REG(NFLASH_ECC_CODE_GEN0+(i*4));
3994 +
3995 + for(j=3;j>0;j--)
3996 + oob_data[(mtd->oobsize-j-(i*4))] = (opcode<<((4-j)*8)) >>24;
3997 +
3998 + for(j=0;j<4;j++)
3999 + {
4000 + ecc_code[15-i*4] = opcode;
4001 + ecc_code[15-i*4-1] = opcode>>8;
4002 + ecc_code[15-i*4-2] = opcode>>16;
4003 + }
4004 + }
4005 +
4006 + //disable ecc
4007 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000);
4008 +
4009 + /* Write out OOB data */
4010 + for(i=0;i<mtd->oobsize;i++)
4011 + {
4012 + //udelay(5);
4013 + FLASH_WRITE_DATA((page*mtd->oobblock)+mtd->oobblock+i,oob_data[i]);
4014 + }
4015 + }
4016 + else
4017 + {
4018 + for(i=0;i<mtd->oobsize;i++)
4019 + {
4020 + //udelay(5);
4021 + FLASH_WRITE_DATA((page*mtd->oobblock)+mtd->oobblock+i,0xff);
4022 + }
4023 + }
4024 +
4025 +
4026 + /* call wait ready function */
4027 + status = this->waitfunc (mtd, this, FL_WRITING);
4028 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
4029 + /* See if device thinks it succeeded */
4030 + if (status & 0x01) {
4031 + DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write, page 0x%08x, ", __FUNCTION__, page);
4032 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
4033 + return -EIO;
4034 + }
4035 +
4036 +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
4037 + /*
4038 + * The NAND device assumes that it is always writing to
4039 + * a cleanly erased page. Hence, it performs its internal
4040 + * write verification only on bits that transitioned from
4041 + * 1 to 0. The device does NOT verify the whole page on a
4042 + * byte by byte basis. It is possible that the page was
4043 + * not completely erased or the page is becoming unusable
4044 + * due to wear. The read with ECC would catch the error
4045 + * later when the ECC page check fails, but we would rather
4046 + * catch it early in the page write stage. Better to write
4047 + * no data than invalid data.
4048 + */
4049 +
4050 + /* Send command to read back the page */
4051 + this->cmdfunc (mtd, NAND_CMD_READ0, 0, page);
4052 + /* Loop through and verify the data */
4053 + if (this->verify_buf(mtd, this->data_poi, mtd->oobblock)) {
4054 + DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
4055 + return -EIO;
4056 + }
4057 +
4058 + /* check, if we have a fs-supplied oob-buffer */
4059 + if (oob_buf) {
4060 + if (this->verify_buf(mtd, oob_data, mtd->oobsize)) {
4061 + DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
4062 + return -EIO;
4063 + }
4064 + } else {
4065 + if (eccmode != NAND_ECC_NONE) {
4066 + int ecc_bytes = 0;
4067 +
4068 + switch (this->eccmode) {
4069 + case NAND_ECC_SOFT:
4070 + case NAND_ECC_HW3_256: ecc_bytes = (mtd->oobblock == 512) ? 6 : 3; break;
4071 + case NAND_ECC_HW3_512: ecc_bytes = 3; break;
4072 + case NAND_ECC_HW6_512: ecc_bytes = 6; break;
4073 + }
4074 +
4075 +
4076 +
4077 + for(i=0;i < (mtd->oobblock+mtd->oobsize);i++)
4078 + {
4079 + if(i>=mtd->oobblock)
4080 + oob_data[i-mtd->oobblock] = FLASH_READ_DATA((page*mtd->oobblock) +i);
4081 + else
4082 + oob_data[0] = FLASH_READ_DATA((page*mtd->oobblock) +i);
4083 + }
4084 +
4085 + if(this->eccmode == NAND_ECC_HW3_512)
4086 + {
4087 + for(i=0;i<(mtd->oobblock/512);i++)
4088 + {
4089 + for(j=0;j<3;j++)
4090 + {
4091 + if (oob_data[mtd->oobsize-1-j-4*i] != ecc_code[15-j-4*i]) {
4092 + DEBUG (MTD_DEBUG_LEVEL0,
4093 + "%s: Failed ECC write "
4094 + "verify, page 0x%08x, " "%6i bytes were succesful\n", __FUNCTION__, page, i);
4095 + return -EIO;
4096 + }
4097 + }
4098 + }
4099 + }
4100 + }//eccmode != NAND_ECC_NONE
4101 + }
4102 + /*
4103 + * Terminate the read command. This is faster than sending a reset command or
4104 + * applying a 20us delay before issuing the next programm sequence.
4105 + * This is not a problem for all chips, but I have found a bunch of them.
4106 + */
4107 + //this->select_chip(mtd, -1);
4108 + //this->select_chip(mtd, 0);
4109 +#endif
4110 +
4111 + return 0;
4112 +}
4113 +
4114 +/*
4115 + * NAND write with iovec
4116 + */
4117 +static int sl2312_nand_writev (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count,
4118 + loff_t to, size_t * retlen)
4119 +{
4120 + return (sl2312_nand_writev_ecc (mtd, vecs, count, to, retlen, NULL, 0));
4121 +}
4122 +
4123 +static int sl2312_nand_writev_ecc (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count,
4124 + loff_t to, size_t * retlen, u_char *eccbuf, struct nand_oobinfo *oobsel)
4125 +{
4126 + int i, page, len, total_len, ret = 0, written = 0;
4127 + struct nand_chip *this = mtd->priv;
4128 +
4129 + /* Calculate total length of data */
4130 + total_len = 0;
4131 + for (i = 0; i < count; i++)
4132 + total_len += (int) vecs[i].iov_len;
4133 +
4134 + DEBUG (MTD_DEBUG_LEVEL3,
4135 + "nand_writev: to = 0x%08x, len = %i, count = %ld\n", (unsigned int) to, (unsigned int) total_len, count);
4136 +
4137 + /* Do not allow write past end of page */
4138 + if ((to + total_len) > mtd->size) {
4139 + DEBUG (MTD_DEBUG_LEVEL0, "nand_writev: Attempted write past end of device\n");
4140 + return -EINVAL;
4141 + }
4142 +
4143 + /* reject writes, which are not page aligned */
4144 + if (NOTALIGNED (to) || NOTALIGNED(total_len)) {
4145 + printk (KERN_NOTICE "nand_write_ecc: Attempt to write not page aligned data\n");
4146 + return -EINVAL;
4147 + }
4148 +
4149 + // if oobsel is NULL, use chip defaults
4150 + if (oobsel == NULL)
4151 + oobsel = &mtd->oobinfo;
4152 +
4153 + /* Shift to get page */
4154 + page = ((int) to) >> this->page_shift;
4155 +
4156 + /* Grab the lock and see if the device is available */
4157 + sl2312_nand_get_chip (this, mtd, FL_WRITING, NULL);
4158 +
4159 + /* Select the NAND device */
4160 + this->select_chip(mtd, 0);
4161 +
4162 + /* Check the WP bit */
4163 + if (!(sl2312_device_ready(mtd) & 0x80)) {
4164 + DEBUG (MTD_DEBUG_LEVEL0, "sl2312_nand_writev_ecc: Device is write protected!!!\n");
4165 + ret = -EIO;
4166 + goto out;
4167 + }
4168 +
4169 + /* Loop until all iovecs' data has been written */
4170 + len = 0;
4171 + while (count) {
4172 + /*
4173 + * Check, if the tuple gives us not enough data for a
4174 + * full page write. Then we can use the iov direct,
4175 + * else we have to copy into data_buf.
4176 + */
4177 + if ((vecs->iov_len - len) >= mtd->oobblock) {
4178 + this->data_poi = (u_char *) vecs->iov_base;
4179 + this->data_poi += len;
4180 + len += mtd->oobblock;
4181 + /* Check, if we have to switch to the next tuple */
4182 + if (len >= (int) vecs->iov_len) {
4183 + vecs++;
4184 + len = 0;
4185 + count--;
4186 + }
4187 + } else {
4188 + /*
4189 + * Read data out of each tuple until we have a full page
4190 + * to write or we've read all the tuples.
4191 + */
4192 + int cnt = 0;
4193 + while ((cnt < mtd->oobblock) && count) {
4194 + if (vecs->iov_base != NULL && vecs->iov_len) {
4195 + this->data_buf[cnt++] = ((u_char *) vecs->iov_base)[len++];
4196 + }
4197 + /* Check, if we have to switch to the next tuple */
4198 + if (len >= (int) vecs->iov_len) {
4199 + vecs++;
4200 + len = 0;
4201 + count--;
4202 + }
4203 + }
4204 + this->data_poi = this->data_buf;
4205 + }
4206 +
4207 + /* We use the same function for write and writev !) */
4208 + ret = sl2312_nand_write_page (mtd, this, page, NULL, oobsel);
4209 + if (ret)
4210 + goto out;
4211 +
4212 + /* Update written bytes count */
4213 + written += mtd->oobblock;;
4214 +
4215 + /* Increment page address */
4216 + page++;
4217 + }
4218 +
4219 +out:
4220 + /* De-select the NAND device */
4221 + //this->select_chip(mtd, -1);
4222 +
4223 + /* Wake up anyone waiting on the device */
4224 + spin_lock_bh (&this->chip_lock);
4225 + this->state = FL_READY;
4226 + wake_up (&this->wq);
4227 + spin_unlock_bh (&this->chip_lock);
4228 +
4229 + *retlen = written;
4230 + return ret;
4231 +}
4232 +
4233 +/*
4234 +static u_char ffchars[] = {
4235 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4236 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
4237 +};
4238 +*/
4239 +/*
4240 + * NAND write out-of-band
4241 + */
4242 +static int sl2312_nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf)
4243 +{
4244 + int column, page, status, ret = 0, j=0;
4245 + struct nand_chip *this = mtd->priv;
4246 + u_char *databuf, *oobbuf;
4247 +
4248 +
4249 + databuf = &this->data_buf[0];
4250 + oobbuf = &this->data_buf[mtd->oobblock];
4251 + for (j = 0; j < mtd->oobsize; j++)
4252 + oobbuf[j] = 0xff;
4253 +//#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
4254 +// int i;
4255 +//#endif
4256 +
4257 + DEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
4258 +
4259 + /* Shift to get page */
4260 + page = ((int) to) >> this->page_shift;
4261 +
4262 + /* Mask to get column */
4263 + column = to & 0x1f;
4264 +
4265 + /* Initialize return length value */
4266 + *retlen = 0;
4267 +
4268 + /* Do not allow write past end of page */
4269 + if ((column + len) > mtd->oobsize) {
4270 + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: Attempt to write past end of page\n");
4271 + return -EINVAL;
4272 + }
4273 +
4274 + /* Grab the lock and see if the device is available */
4275 + sl2312_nand_get_chip (this, mtd, FL_WRITING, NULL);
4276 +
4277 + /* Select the NAND device */
4278 + this->select_chip(mtd, 0);
4279 +
4280 + /* Reset the chip. Some chips (like the Toshiba TC5832DC found
4281 + in one of my DiskOnChip 2000 test units) will clear the whole
4282 + data page too if we don't do this. I have no clue why, but
4283 + I seem to have 'fixed' it in the doc2000 driver in
4284 + August 1999. dwmw2. */
4285 + this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
4286 +
4287 + /* Check the WP bit */
4288 + if (!(sl2312_device_ready(mtd) & 0x80)) {
4289 + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: Device is write protected!!!\n");
4290 + ret = -EIO;
4291 + goto out;
4292 + }
4293 + /* Write out desired data */
4294 + this->cmdfunc (mtd, NAND_CMD_SEQIN, mtd->oobblock, page);
4295 +
4296 + sl2312_nand_read_ecc (mtd, page, mtd->oobblock , retlen, databuf, oobbuf, NULL);
4297 +
4298 + for(j=column;j<(column+len);j++)
4299 + oobbuf[j] = buf[j-column];
4300 + sl2312_nand_write_ecc (mtd, page, mtd->oobblock, retlen, databuf, oobbuf, NULL);
4301 +
4302 + status = this->waitfunc (mtd, this, FL_WRITING);
4303 +
4304 + /* See if device thinks it succeeded */
4305 + if (status & 0x01) {
4306 + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write, page 0x%08x\n", page);
4307 + ret = -EIO;
4308 + goto out;
4309 + }
4310 + /* Return happy */
4311 + *retlen = len;
4312 +
4313 +
4314 +out:
4315 + /* De-select the NAND device */
4316 + //this->select_chip(mtd, -1);
4317 +
4318 + /* Wake up anyone waiting on the device */
4319 + spin_lock_bh (&this->chip_lock);
4320 + this->state = FL_READY;
4321 + wake_up (&this->wq);
4322 + spin_unlock_bh (&this->chip_lock);
4323 +
4324 + return ret;
4325 +}
4326 +
4327 +/*
4328 + * NAND sync
4329 + */
4330 +static void sl2312_nand_sync (struct mtd_info *mtd)
4331 +{
4332 + struct nand_chip *this = mtd->priv;
4333 + DECLARE_WAITQUEUE (wait, current);
4334 +
4335 + DEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
4336 +
4337 +retry:
4338 + /* Grab the spinlock */
4339 + spin_lock_bh (&this->chip_lock);
4340 +
4341 + /* See what's going on */
4342 + switch (this->state) {
4343 + case FL_READY:
4344 + case FL_SYNCING:
4345 + this->state = FL_SYNCING;
4346 + spin_unlock_bh (&this->chip_lock);
4347 + break;
4348 +
4349 + default:
4350 + /* Not an idle state */
4351 + add_wait_queue (&this->wq, &wait);
4352 + spin_unlock_bh (&this->chip_lock);
4353 + schedule ();
4354 +
4355 + remove_wait_queue (&this->wq, &wait);
4356 + goto retry;
4357 + }
4358 +
4359 + /* Lock the device */
4360 + spin_lock_bh (&this->chip_lock);
4361 +
4362 + /* Set the device to be ready again */
4363 + if (this->state == FL_SYNCING) {
4364 + this->state = FL_READY;
4365 + wake_up (&this->wq);
4366 + }
4367 +
4368 + /* Unlock the device */
4369 + spin_unlock_bh (&this->chip_lock);
4370 +}
4371 +
4372 +
4373 +/*
4374 + * Scan for the NAND device
4375 + */
4376 +int sl2312_nand_scan (struct mtd_info *mtd, int maxchips)
4377 +{
4378 + int i, j, nand_maf_id, nand_dev_id, busw;
4379 + struct nand_chip *this = mtd->priv;
4380 + unsigned char id[4];
4381 +
4382 + /* Get buswidth to select the correct functions*/
4383 + busw = this->options & NAND_BUSWIDTH_16;
4384 +
4385 + /* check for proper chip_delay setup, set 20us if not */
4386 + if (!this->chip_delay)
4387 + this->chip_delay = 20;
4388 +
4389 + /* check, if a user supplied command function given */
4390 + if (this->cmdfunc == NULL)
4391 + this->cmdfunc = sl2312_nand_command;
4392 +
4393 + /* check, if a user supplied wait function given */
4394 + if (this->waitfunc == NULL)
4395 + this->waitfunc = sl2312_nand_waitfunc;
4396 +
4397 + if (!this->select_chip)
4398 + this->select_chip = sl2312_nand_select_chip;
4399 + if (!this->write_byte)
4400 + this->write_byte = sl2312_nand_write_byte; //busw ? nand_write_byte16 : nand_write_byte;
4401 + if (!this->read_byte)
4402 + this->read_byte = sl2312_nand_read_byte; //busw ? nand_read_byte16 : nand_read_byte;
4403 +// if (!this->write_word)
4404 +// this->write_word = nand_write_word;
4405 +// if (!this->read_word)
4406 +// this->read_word = nand_read_word;
4407 +// if (!this->block_bad)
4408 + this->block_bad = sl2312_nand_block_bad; //nand_block_bad;
4409 + if (!this->block_markbad)
4410 + this->block_markbad = sl2312_nand_default_block_markbad;
4411 + if (!this->write_buf)
4412 + this->write_buf = sl2312_nand_write_buf; //busw ? nand_write_buf16 : nand_write_buf;
4413 + if (!this->read_buf)
4414 + this->read_buf = sl2312_nand_read_buf; //busw ? nand_read_buf16 : nand_read_buf;
4415 + if (!this->verify_buf)
4416 + this->verify_buf = sl2312_nand_verify_buf; //busw ? nand_verify_buf16 : nand_verify_buf;
4417 + if (!this->scan_bbt)
4418 + this->scan_bbt = sl2312_nand_scan_bbt;
4419 +
4420 + /* Select the device */
4421 + this->select_chip(mtd, 0);
4422 +
4423 + /* Read manufacturer and device IDs */
4424 + nand_read_id(0,id);
4425 +
4426 + nand_maf_id = id[0];
4427 + nand_dev_id = id[1];
4428 +
4429 + /* Print and store flash device information */
4430 + for (i = 0; nand_flash_ids[i].name != NULL; i++) {
4431 +
4432 + if (nand_dev_id != nand_flash_ids[i].id)
4433 + continue;
4434 +
4435 + if (!mtd->name) mtd->name = nand_flash_ids[i].name;
4436 + this->chipsize = nand_flash_ids[i].chipsize << 20;
4437 +
4438 + /* New devices have all the information in additional id bytes */
4439 + if (!nand_flash_ids[i].pagesize) {
4440 + int extid;
4441 +
4442 + /* The 4th id byte is the important one */
4443 + extid = id[3];
4444 + /* Calc pagesize */
4445 + mtd->oobblock = 1024 << (extid & 0x3);
4446 + extid >>= 2;
4447 + /* Calc oobsize */
4448 + mtd->oobsize = (8 << (extid & 0x03)) * (mtd->oobblock / 512);
4449 + extid >>= 2;
4450 + /* Calc blocksize. Blocksize is multiples of 64KiB */
4451 + mtd->erasesize = (64 * 1024) << (extid & 0x03);
4452 + extid >>= 2;
4453 + /* Get buswidth information */
4454 + busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
4455 +
4456 + } else {
4457 + /* Old devices have this data hardcoded in the
4458 + * device id table */
4459 + mtd->erasesize = nand_flash_ids[i].erasesize;
4460 + mtd->oobblock = nand_flash_ids[i].pagesize;
4461 + mtd->oobsize = mtd->oobblock / 32;
4462 + busw = nand_flash_ids[i].options & NAND_BUSWIDTH_16;
4463 + }
4464 +
4465 + /* Check, if buswidth is correct. Hardware drivers should set
4466 + * this correct ! */
4467 + if (busw != (this->options & NAND_BUSWIDTH_16)) {
4468 + printk (KERN_INFO "NAND device: Manufacturer ID:"
4469 + " 0x%02x, Chip ID: 0x%02x (%s %s)\n", nand_maf_id, nand_dev_id,
4470 + nand_manuf_ids[i].name , mtd->name);
4471 + printk (KERN_WARNING
4472 + "NAND bus width %d instead %d bit\n",
4473 + (this->options & NAND_BUSWIDTH_16) ? 16 : 8,
4474 + busw ? 16 : 8);
4475 + this->select_chip(mtd, -1);
4476 + return 1;
4477 + }
4478 +
4479 + /* Calculate the address shift from the page size */
4480 + this->page_shift = ffs(mtd->oobblock) - 1;
4481 + this->bbt_erase_shift = this->phys_erase_shift = ffs(mtd->erasesize) - 1;
4482 + this->chip_shift = ffs(this->chipsize) - 1;
4483 +
4484 + /* Set the bad block position */
4485 + this->badblockpos = mtd->oobblock > 512 ?
4486 + NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
4487 +
4488 + /* Get chip options, preserve non chip based options */
4489 + this->options &= ~NAND_CHIPOPTIONS_MSK;
4490 + this->options |= nand_flash_ids[i].options & NAND_CHIPOPTIONS_MSK;
4491 + /* Set this as a default. Board drivers can override it, if neccecary */
4492 + this->options |= NAND_NO_AUTOINCR;
4493 + /* Check if this is a not a samsung device. Do not clear the options
4494 + * for chips which are not having an extended id.
4495 + */
4496 + if (nand_maf_id != NAND_MFR_SAMSUNG && !nand_flash_ids[i].pagesize)
4497 + this->options &= ~NAND_SAMSUNG_LP_OPTIONS;
4498 +
4499 + /* Check for AND chips with 4 page planes */
4500 + // if (this->options & NAND_4PAGE_ARRAY)
4501 + // this->erase_cmd = multi_erase_cmd;
4502 + // else
4503 + // this->erase_cmd = single_erase_cmd;
4504 +
4505 + /* Do not replace user supplied command function ! */
4506 + // if (mtd->oobblock > 512 && this->cmdfunc == nand_command)
4507 + // this->cmdfunc = nand_command_lp;
4508 +
4509 + /* Try to identify manufacturer */
4510 + for (j = 0; nand_manuf_ids[j].id != 0x0; j++) {
4511 + if (nand_manuf_ids[j].id == nand_maf_id)
4512 + break;
4513 + }
4514 + printk (KERN_INFO "NAND device: Manufacturer ID:"
4515 + " 0x%02x, Chip ID: 0x%02x (%s %s)\n", nand_maf_id, nand_dev_id,
4516 + nand_manuf_ids[j].name , nand_flash_ids[i].name);
4517 + break;
4518 + }
4519 + /////////////////////////////
4520 +
4521 + for (i=1; i < maxchips; i++) {
4522 + this->select_chip(mtd, i);
4523 +
4524 + /* Send the command for reading device ID */
4525 + nand_read_id(1,id);
4526 +
4527 + /* Read manufacturer and device IDs */
4528 + if (nand_maf_id != id[0] ||
4529 + nand_dev_id != id[1])
4530 + break;
4531 + }
4532 + if (i > 1)
4533 + printk(KERN_INFO "%d NAND chips detected\n", i);
4534 +
4535 + /* Allocate buffers, if neccecary */
4536 + if (!this->oob_buf) {
4537 + size_t len;
4538 + len = mtd->oobsize << (this->phys_erase_shift - this->page_shift);
4539 + this->oob_buf = kmalloc (len, GFP_KERNEL);
4540 + if (!this->oob_buf) {
4541 + printk (KERN_ERR "nand_scan(): Cannot allocate oob_buf\n");
4542 + return -ENOMEM;
4543 + }
4544 + this->options |= NAND_OOBBUF_ALLOC;
4545 + }
4546 +
4547 + if (!this->data_buf) {
4548 + size_t len;
4549 + len = mtd->oobblock + mtd->oobsize;
4550 + this->data_buf = kmalloc (len, GFP_KERNEL);
4551 + if (!this->data_buf) {
4552 + if (this->options & NAND_OOBBUF_ALLOC)
4553 + kfree (this->oob_buf);
4554 + printk (KERN_ERR "nand_scan(): Cannot allocate data_buf\n");
4555 + return -ENOMEM;
4556 + }
4557 + this->options |= NAND_DATABUF_ALLOC;
4558 + }
4559 +
4560 + /* Store the number of chips and calc total size for mtd */
4561 + this->numchips = i;
4562 + mtd->size = i * this->chipsize;
4563 + /* Convert chipsize to number of pages per chip -1. */
4564 + this->pagemask = (this->chipsize >> this->page_shift) - 1;
4565 + /* Preset the internal oob buffer */
4566 + memset(this->oob_buf, 0xff, mtd->oobsize << (this->phys_erase_shift - this->page_shift));
4567 +
4568 + /* If no default placement scheme is given, select an
4569 + * appropriate one */
4570 + if (!this->autooob) {
4571 + /* Select the appropriate default oob placement scheme for
4572 + * placement agnostic filesystems */
4573 + switch (mtd->oobsize) {
4574 + case 8:
4575 + this->autooob = &nand_oob_8;
4576 + break;
4577 + case 16:
4578 + this->autooob = &nand_oob_16;
4579 + break;
4580 + case 64:
4581 + this->autooob = &nand_oob_64;
4582 + break;
4583 + default:
4584 + printk (KERN_WARNING "No oob scheme defined for oobsize %d\n",
4585 + mtd->oobsize);
4586 + BUG();
4587 + }
4588 + }
4589 +
4590 + /* The number of bytes available for the filesystem to place fs dependend
4591 + * oob data */
4592 + if (this->options & NAND_BUSWIDTH_16) {
4593 + mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 2);
4594 + if (this->autooob->eccbytes & 0x01)
4595 + mtd->oobavail--;
4596 + } else
4597 + mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 1);
4598 +
4599 +
4600 + /*
4601 + * check ECC mode, default to software
4602 + * if 3byte/512byte hardware ECC is selected and we have 256 byte pagesize
4603 + * fallback to software ECC
4604 + */
4605 + this->eccsize = 256; /* set default eccsize */
4606 + this->eccbytes = 3;
4607 +
4608 + switch (this->eccmode) {
4609 + case NAND_ECC_HW12_2048:
4610 + if (mtd->oobblock < 2048) {
4611 + printk(KERN_WARNING "2048 byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4612 + mtd->oobblock);
4613 + this->eccmode = NAND_ECC_SOFT;
4614 + this->calculate_ecc = nand_calculate_ecc;
4615 + this->correct_data = nand_correct_data;
4616 + } else
4617 + this->eccsize = 2048;
4618 + break;
4619 +
4620 + case NAND_ECC_HW3_512:
4621 + case NAND_ECC_HW6_512:
4622 + case NAND_ECC_HW8_512:
4623 + if (mtd->oobblock == 256) {
4624 + printk (KERN_WARNING "512 byte HW ECC not possible on 256 Byte pagesize, fallback to SW ECC \n");
4625 + this->eccmode = NAND_ECC_SOFT;
4626 + this->calculate_ecc = nand_calculate_ecc;
4627 + this->correct_data = nand_correct_data;
4628 + } else
4629 + this->eccsize = 512; /* set eccsize to 512 */
4630 + break;
4631 +
4632 + case NAND_ECC_HW3_256:
4633 + break;
4634 +
4635 + case NAND_ECC_NONE:
4636 + printk (KERN_WARNING "NAND_ECC_NONE selected by board driver. This is not recommended !!\n");
4637 + this->eccmode = NAND_ECC_NONE;
4638 + break;
4639 +
4640 + case NAND_ECC_SOFT:
4641 + this->calculate_ecc = nand_calculate_ecc;
4642 + this->correct_data = nand_correct_data;
4643 + break;
4644 +
4645 + default:
4646 + printk (KERN_WARNING "Invalid NAND_ECC_MODE %d\n", this->eccmode);
4647 + BUG();
4648 + }
4649 +
4650 + /* Check hardware ecc function availability and adjust number of ecc bytes per
4651 + * calculation step
4652 + */
4653 + switch (this->eccmode) {
4654 + case NAND_ECC_HW12_2048:
4655 + this->eccbytes += 4;
4656 + case NAND_ECC_HW8_512:
4657 + this->eccbytes += 2;
4658 + case NAND_ECC_HW6_512:
4659 + this->eccbytes += 3;
4660 +// case NAND_ECC_HW3_512:
4661 + case NAND_ECC_HW3_256:
4662 + if (this->calculate_ecc && this->correct_data && this->enable_hwecc)
4663 + break;
4664 + printk (KERN_WARNING "No ECC functions supplied, Hardware ECC not possible\n");
4665 + BUG();
4666 + }
4667 +
4668 + mtd->eccsize = this->eccsize;
4669 +
4670 + /* Set the number of read / write steps for one page to ensure ECC generation */
4671 + switch (this->eccmode) {
4672 + case NAND_ECC_HW12_2048:
4673 + this->eccsteps = mtd->oobblock / 2048;
4674 + break;
4675 + case NAND_ECC_HW3_512:
4676 + case NAND_ECC_HW6_512:
4677 + case NAND_ECC_HW8_512:
4678 + this->eccsteps = mtd->oobblock / 512;
4679 + break;
4680 + case NAND_ECC_HW3_256:
4681 + case NAND_ECC_SOFT:
4682 + this->eccsteps = mtd->oobblock / 256;
4683 + break;
4684 +
4685 + case NAND_ECC_NONE:
4686 + this->eccsteps = 1;
4687 + break;
4688 + }
4689 +
4690 + /* Initialize state, waitqueue and spinlock */
4691 + this->state = FL_READY;
4692 + init_waitqueue_head (&this->wq);
4693 + spin_lock_init (&this->chip_lock);
4694 +
4695 + /* De-select the device */
4696 + this->select_chip(mtd, 0);
4697 +
4698 + /* Print warning message for no device */
4699 + if (!mtd->size) {
4700 + printk (KERN_WARNING "No NAND device found!!!\n");
4701 + return 1;
4702 + }
4703 +
4704 + /* Fill in remaining MTD driver data */
4705 + mtd->type = MTD_NANDFLASH;
4706 + mtd->flags = MTD_CAP_NANDFLASH | MTD_ECC;
4707 + mtd->ecctype = MTD_ECC_SW;
4708 + mtd->erase = sl2312_nand_erase;
4709 + mtd->point = NULL;
4710 + mtd->unpoint = NULL;
4711 + mtd->read = sl2312_nand_read;
4712 + mtd->write = sl2312_nand_write;
4713 + mtd->read_ecc = sl2312_nand_read_ecc;
4714 + mtd->write_ecc = sl2312_nand_write_ecc;
4715 + mtd->read_oob = sl2312_nand_read_oob;
4716 + mtd->write_oob = sl2312_nand_write_oob;
4717 + mtd->readv = NULL;
4718 + mtd->writev = sl2312_nand_writev;
4719 + mtd->writev_ecc = sl2312_nand_writev_ecc;
4720 + mtd->sync = sl2312_nand_sync;
4721 + mtd->lock = NULL;
4722 + mtd->unlock = NULL;
4723 + mtd->suspend = NULL;
4724 + mtd->resume = NULL;
4725 + mtd->block_isbad = sl2312_nand_block_isbad;
4726 + mtd->block_markbad = sl2312_nand_block_markbad;
4727 +
4728 + /* and make the autooob the default one */
4729 + memcpy(&mtd->oobinfo, this->autooob, sizeof(mtd->oobinfo));
4730 +
4731 + mtd->owner = THIS_MODULE;
4732 +
4733 + /* Build bad block table */
4734 + return this->scan_bbt (mtd);
4735 +}
4736 +
4737 +/*End Add function*/
4738 +
4739 +/*
4740 + * Main initialization routine
4741 + */
4742 +extern int nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
4743 +
4744 +int __init sl2312_mtd_init (void)
4745 +{
4746 + struct nand_chip *this;
4747 + int err = 0;
4748 + struct mtd_partition *parts;
4749 + int nr_parts = 0;
4750 + int ret, data, *base;
4751 +
4752 + printk("NAND MTD Driver Start Init ......\n");
4753 +
4754 + base = (unsigned int *)(IO_ADDRESS(SL2312_GLOBAL_BASE) + 0x30);
4755 + data = *base;
4756 + data&=0xffffffeb;
4757 + data|=0x3; //disable p & s flash
4758 + *base = data;
4759 +
4760 + /* Allocate memory for MTD device structure and private data */
4761 + sl2312_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
4762 + if (!sl2312_mtd) {
4763 + printk ("Unable to allocate SL2312 NAND MTD device structure.\n");
4764 + err = -ENOMEM;
4765 + goto out;
4766 + }
4767 +
4768 + // sl2312_device_setup();
4769 +
4770 + /* io is indirect via a register so don't need to ioremap address */
4771 +
4772 + /* Get pointer to private data */
4773 + this = (struct nand_chip *) (&sl2312_mtd[1]);
4774 +
4775 + /* Initialize structures */
4776 + memset((char *) sl2312_mtd, 0, sizeof(struct mtd_info));
4777 + memset((char *) this, 0, sizeof(struct nand_chip));
4778 +
4779 + /* Link the private data with the MTD structure */
4780 + sl2312_mtd->priv = this;
4781 + sl2312_mtd->name = "sl2312-nand";
4782 +
4783 + /* Set address of NAND IO lines */
4784 + this->IO_ADDR_R = (void __iomem *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE+NFLASH_DATA)); //(unsigned long)&(sl2312_ndfmcptr->dtr);
4785 + this->IO_ADDR_W = (void __iomem *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE+NFLASH_DATA)); //(unsigned long)&(sl2312_ndfmcptr->dtr);
4786 + this->read_byte = sl2312_nand_read_byte;
4787 + this->write_byte = sl2312_nand_write_byte;
4788 + this->write_buf = sl2312_nand_write_buf;
4789 + this->read_buf = sl2312_nand_read_buf;
4790 + this->verify_buf = sl2312_nand_verify_buf;
4791 + this->select_chip = sl2312_nand_select_chip;
4792 + this->block_bad = sl2312_nand_block_bad;
4793 + this->hwcontrol = sl2312_hwcontrol;
4794 + this->dev_ready = sl2312_device_ready;
4795 + this->cmdfunc = sl2312_nand_command;
4796 + this->waitfunc = sl2312_nand_waitfunc;
4797 + //this->calculate_ecc = sl2312_readecc;
4798 + this->enable_hwecc = sl2312_enable_hwecc;
4799 + this->eccmode = NAND_ECC_HW3_512;
4800 + /*this->eccsize = 512; */
4801 + /* 20 us command delay time */
4802 + this->chip_delay = 20;
4803 +
4804 + this->correct_data = nand_correct_data;
4805 +// this->scan_bbt = sl2312_nand_scan_bbt;
4806 +
4807 + /* Allocate memory for internal data buffer */
4808 + this->data_buf = kmalloc (sizeof(u_char) * (sl2312_mtd->oobblock + sl2312_mtd->oobsize), GFP_KERNEL);
4809 + if (!this->data_buf) {
4810 + printk ("Unable to allocate NAND data buffer.\n");
4811 + err = -ENOMEM;
4812 + goto out_ior;
4813 + }
4814 +
4815 + /* Scan to find existance of the device */
4816 + if (sl2312_nand_scan(sl2312_mtd, 1)) {
4817 + err = -ENXIO;
4818 + goto out_ior;
4819 + }
4820 +
4821 + /* Register the partitions */
4822 + parts = sl2312_partitions;
4823 + nr_parts = sizeof(sl2312_partitions)/sizeof(*parts);
4824 +
4825 + ret = add_mtd_partitions(sl2312_mtd, sl2312_partitions, nr_parts);
4826 + /*If we got an error, free all resources.*/
4827 + if (ret < 0) {
4828 + del_mtd_partitions(sl2312_mtd);
4829 + map_destroy(sl2312_mtd);
4830 + }
4831 + goto out;
4832 +
4833 +//out_buf:
4834 +// kfree (this->data_buf);
4835 +out_ior:
4836 +out:
4837 + printk("NAND MTD Driver Init Success ......\n");
4838 + return err;
4839 +}
4840 +
4841 +module_init(sl2312_mtd_init);
4842 +
4843 +/*
4844 + * Clean up routine
4845 + */
4846 +#ifdef MODULE
4847 +static void __exit sl2312_cleanup (void)
4848 +{
4849 + struct nand_chip *this = (struct nand_chip *) &sl2312_mtd[1];
4850 +
4851 + /* Unregister partitions */
4852 + del_mtd_partitions(sl2312_mtd);
4853 +
4854 + /* Unregister the device */
4855 + del_mtd_device (sl2312_mtd);
4856 +
4857 + /* Free internal data buffers */
4858 + kfree (this->data_buf);
4859 +
4860 + /* Free the MTD device structure */
4861 + kfree (sl2312_mtd);
4862 +}
4863 +module_exit(sl2312_cleanup);
4864 +#endif
4865 +
4866 +MODULE_LICENSE("GPL");
4867 +MODULE_AUTHOR("Alice Hennessy <ahennessy@mvista.com>");
4868 +MODULE_DESCRIPTION("Glue layer for SmartMediaCard on Toshiba RBsl2312");
4869 --- /dev/null
4870 +++ b/drivers/mtd/nand/sl2312-flash-nand.h
4871 @@ -0,0 +1,24 @@
4872 +#ifndef SL2312_FLASH_NAND_H
4873 +#define SL2312_FLASH_NAND_H
4874 +
4875 +#include <linux/wait.h>
4876 +#include <linux/spinlock.h>
4877 +
4878 +/*Add function*/
4879 +static void nand_read_id(int chip_no,unsigned char *id);
4880 +
4881 +
4882 +
4883 +#define NFLASH_WiDTH8 0x00000000
4884 +#define NFLASH_WiDTH16 0x00000400
4885 +#define NFLASH_WiDTH32 0x00000800
4886 +#define NFLASH_CHIP0_EN 0x00000000 // 16th bit = 0
4887 +#define NFLASH_CHIP1_EN 0x00010000 // 16th bit = 1
4888 +#define NFLASH_DIRECT 0x00004000
4889 +#define NFLASH_INDIRECT 0x00000000
4890 +
4891 +
4892 +#define DWIDTH NFLASH_WiDTH8
4893 +
4894 +
4895 +#endif /* SL2312_FLASH_NAND_H */
4896 --- /dev/null
4897 +++ b/include/linux/mtd/kvctl.h
4898 @@ -0,0 +1,40 @@
4899 +#ifndef KVCTL_H
4900 +#define KVCTL_H
4901 +
4902 +#define VCTL_HEAD_SIZE 8
4903 +#define VCTL_ENTRY_LEN 20
4904 +
4905 +typedef struct
4906 +{
4907 + char header[4];
4908 + unsigned int entry_num;
4909 +} vctl_mheader;
4910 +
4911 +typedef struct
4912 +{
4913 + char header[4];
4914 + unsigned int size;
4915 + unsigned int type;
4916 + char majorver[4];
4917 + char minorver[4];
4918 + unsigned char *payload;
4919 +} vctl_entry;
4920 +
4921 +typedef struct
4922 +{
4923 + unsigned char mac[6];
4924 + unsigned char vlanid;
4925 + unsigned char vlanmap;
4926 +} vlaninfo;
4927 +
4928 +#define VCT_VENDORSPEC 0
4929 +#define VCT_BOOTLOADER 1
4930 +#define VCT_KERNEL 2
4931 +#define VCT_VERCTL 3
4932 +#define VCT_CURRCONF 4
4933 +#define VCT_DEFAULTCONF 5
4934 +#define VCT_ROOTFS 6
4935 +#define VCT_APP 7
4936 +#define VCT_VLAN 8
4937 +
4938 +#endif
4939 --- a/drivers/mtd/maps/Makefile
4940 +++ b/drivers/mtd/maps/Makefile
4941 @@ -71,3 +71,7 @@ obj-$(CONFIG_MTD_PLATRAM) += plat-ram.o
4942 obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o
4943 obj-$(CONFIG_MTD_MTX1) += mtx-1_flash.o
4944 obj-$(CONFIG_MTD_TQM834x) += tqm834x.o
4945 +###### for Storlink Soc #######
4946 +obj-$(CONFIG_MTD_SL2312_CFI) += sl2312-flash-cfi.o
4947 +obj-$(CONFIG_MTD_SL2312_SERIAL_ATMEL) += sl2312-flash-atmel.o
4948 +obj-$(CONFIG_MTD_SL2312_SERIAL_ST) += sl2312-flash-m25p80.o
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