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[lantiq]
[openwrt.git] / target / linux / generic / patches-2.6.31 / 941-ssb_update.patch
1 --- a/drivers/ssb/driver_chipcommon_pmu.c
2 +++ b/drivers/ssb/driver_chipcommon_pmu.c
3 @@ -28,6 +28,21 @@ static void ssb_chipco_pll_write(struct
4 chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, value);
5 }
6
7 +static void ssb_chipco_regctl_maskset(struct ssb_chipcommon *cc,
8 + u32 offset, u32 mask, u32 set)
9 +{
10 + u32 value;
11 +
12 + chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR);
13 + chipco_write32(cc, SSB_CHIPCO_REGCTL_ADDR, offset);
14 + chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR);
15 + value = chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA);
16 + value &= mask;
17 + value |= set;
18 + chipco_write32(cc, SSB_CHIPCO_REGCTL_DATA, value);
19 + chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA);
20 +}
21 +
22 struct pmu0_plltab_entry {
23 u16 freq; /* Crystal frequency in kHz.*/
24 u8 xf; /* Crystal frequency value for PMU control */
25 @@ -506,3 +521,82 @@ void ssb_pmu_init(struct ssb_chipcommon
26 ssb_pmu_pll_init(cc);
27 ssb_pmu_resources_init(cc);
28 }
29 +
30 +void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
31 + enum ssb_pmu_ldo_volt_id id, u32 voltage)
32 +{
33 + struct ssb_bus *bus = cc->dev->bus;
34 + u32 addr, shift, mask;
35 +
36 + switch (bus->chip_id) {
37 + case 0x4328:
38 + case 0x5354:
39 + switch (id) {
40 + case LDO_VOLT1:
41 + addr = 2;
42 + shift = 25;
43 + mask = 0xF;
44 + break;
45 + case LDO_VOLT2:
46 + addr = 3;
47 + shift = 1;
48 + mask = 0xF;
49 + break;
50 + case LDO_VOLT3:
51 + addr = 3;
52 + shift = 9;
53 + mask = 0xF;
54 + break;
55 + case LDO_PAREF:
56 + addr = 3;
57 + shift = 17;
58 + mask = 0x3F;
59 + break;
60 + default:
61 + SSB_WARN_ON(1);
62 + return;
63 + }
64 + break;
65 + case 0x4312:
66 + if (SSB_WARN_ON(id != LDO_PAREF))
67 + return;
68 + addr = 0;
69 + shift = 21;
70 + mask = 0x3F;
71 + break;
72 + default:
73 + return;
74 + }
75 +
76 + ssb_chipco_regctl_maskset(cc, addr, ~(mask << shift),
77 + (voltage & mask) << shift);
78 +}
79 +
80 +void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on)
81 +{
82 + struct ssb_bus *bus = cc->dev->bus;
83 + int ldo;
84 +
85 + switch (bus->chip_id) {
86 + case 0x4312:
87 + ldo = SSB_PMURES_4312_PA_REF_LDO;
88 + break;
89 + case 0x4328:
90 + ldo = SSB_PMURES_4328_PA_REF_LDO;
91 + break;
92 + case 0x5354:
93 + ldo = SSB_PMURES_5354_PA_REF_LDO;
94 + break;
95 + default:
96 + return;
97 + }
98 +
99 + if (on)
100 + chipco_set32(cc, SSB_CHIPCO_PMU_MINRES_MSK, 1 << ldo);
101 + else
102 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK, ~(1 << ldo));
103 + chipco_read32(cc, SSB_CHIPCO_PMU_MINRES_MSK); //SPEC FIXME found via mmiotrace - dummy read?
104 +}
105 +
106 +EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
107 +EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
108 --- a/drivers/ssb/main.c
109 +++ b/drivers/ssb/main.c
110 @@ -469,6 +469,8 @@ static int ssb_devices_register(struct s
111 dev->parent = &bus->host_pcmcia->dev;
112 #endif
113 break;
114 + case SSB_BUSTYPE_SDIO:
115 + break;
116 case SSB_BUSTYPE_SSB:
117 dev->dma_mask = &dev->coherent_dma_mask;
118 break;
119 @@ -1358,8 +1360,10 @@ static int __init ssb_modinit(void)
120 ssb_buses_lock();
121 err = ssb_attach_queued_buses();
122 ssb_buses_unlock();
123 - if (err)
124 + if (err) {
125 bus_unregister(&ssb_bustype);
126 + goto out;
127 + }
128
129 err = b43_pci_ssb_bridge_init();
130 if (err) {
131 @@ -1375,7 +1379,7 @@ static int __init ssb_modinit(void)
132 /* don't fail SSB init because of this */
133 err = 0;
134 }
135 -
136 +out:
137 return err;
138 }
139 /* ssb must be initialized after PCI but before the ssb drivers.
140 --- a/drivers/ssb/pci.c
141 +++ b/drivers/ssb/pci.c
142 @@ -169,8 +169,14 @@ err_pci:
143 /* Get the word-offset for a SSB_SPROM_XXX define. */
144 #define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
145 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
146 -#define SPEX(_outvar, _offset, _mask, _shift) \
147 +#define SPEX16(_outvar, _offset, _mask, _shift) \
148 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
149 +#define SPEX32(_outvar, _offset, _mask, _shift) \
150 + out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
151 + in[SPOFF(_offset)]) & (_mask)) >> (_shift))
152 +#define SPEX(_outvar, _offset, _mask, _shift) \
153 + SPEX16(_outvar, _offset, _mask, _shift)
154 +
155
156 static inline u8 ssb_crc8(u8 crc, u8 data)
157 {
158 @@ -474,12 +480,14 @@ static void sprom_extract_r8(struct ssb_
159
160 /* extract the MAC address */
161 for (i = 0; i < 3; i++) {
162 - v = in[SPOFF(SSB_SPROM1_IL0MAC) + i];
163 + v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
164 *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
165 }
166 SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
167 SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
168 SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
169 + SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
170 + SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);
171 SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
172 SSB_SPROM8_ANTAVAIL_A_SHIFT);
173 SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
174 @@ -490,12 +498,55 @@ static void sprom_extract_r8(struct ssb_
175 SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
176 SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
177 SSB_SPROM8_ITSSI_A_SHIFT);
178 + SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
179 + SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
180 + SSB_SPROM8_MAXP_AL_SHIFT);
181 SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
182 SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
183 SSB_SPROM8_GPIOA_P1_SHIFT);
184 SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
185 SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
186 SSB_SPROM8_GPIOB_P3_SHIFT);
187 + SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
188 + SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
189 + SSB_SPROM8_TRI5G_SHIFT);
190 + SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
191 + SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
192 + SSB_SPROM8_TRI5GH_SHIFT);
193 + SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);
194 + SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
195 + SSB_SPROM8_RXPO5G_SHIFT);
196 + SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
197 + SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
198 + SSB_SPROM8_RSSISMC2G_SHIFT);
199 + SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
200 + SSB_SPROM8_RSSISAV2G_SHIFT);
201 + SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
202 + SSB_SPROM8_BXA2G_SHIFT);
203 + SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
204 + SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
205 + SSB_SPROM8_RSSISMC5G_SHIFT);
206 + SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
207 + SSB_SPROM8_RSSISAV5G_SHIFT);
208 + SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
209 + SSB_SPROM8_BXA5G_SHIFT);
210 + SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);
211 + SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);
212 + SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);
213 + SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);
214 + SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);
215 + SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);
216 + SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);
217 + SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);
218 + SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);
219 + SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);
220 + SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);
221 + SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);
222 + SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);
223 + SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);
224 + SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);
225 + SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);
226 + SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
227
228 /* Extract the antenna gain values. */
229 SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
230 @@ -549,6 +600,7 @@ static int sprom_extract(struct ssb_bus
231 ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
232 " revision %d detected. Will extract"
233 " v1\n", out->revision);
234 + out->revision = 1;
235 sprom_extract_r123(out, in);
236 }
237 }
238 --- a/drivers/ssb/scan.c
239 +++ b/drivers/ssb/scan.c
240 @@ -175,6 +175,8 @@ static u32 scan_read32(struct ssb_bus *b
241 } else
242 ssb_pcmcia_switch_segment(bus, 0);
243 break;
244 + case SSB_BUSTYPE_SDIO:
245 + break;
246 }
247 return readl(bus->mmio + offset);
248 }
249 @@ -188,6 +190,8 @@ static int scan_switchcore(struct ssb_bu
250 return ssb_pci_switch_coreidx(bus, coreidx);
251 case SSB_BUSTYPE_PCMCIA:
252 return ssb_pcmcia_switch_coreidx(bus, coreidx);
253 + case SSB_BUSTYPE_SDIO:
254 + break;
255 }
256 return 0;
257 }
258 @@ -206,6 +210,8 @@ void ssb_iounmap(struct ssb_bus *bus)
259 SSB_BUG_ON(1); /* Can't reach this code. */
260 #endif
261 break;
262 + case SSB_BUSTYPE_SDIO:
263 + break;
264 }
265 bus->mmio = NULL;
266 bus->mapped_device = NULL;
267 @@ -230,6 +236,8 @@ static void __iomem *ssb_ioremap(struct
268 SSB_BUG_ON(1); /* Can't reach this code. */
269 #endif
270 break;
271 + case SSB_BUSTYPE_SDIO:
272 + break;
273 }
274
275 return mmio;
276 --- a/include/linux/ssb/ssb.h
277 +++ b/include/linux/ssb/ssb.h
278 @@ -27,24 +27,54 @@ struct ssb_sprom {
279 u8 et1mdcport; /* MDIO for enet1 */
280 u8 board_rev; /* Board revision number from SPROM. */
281 u8 country_code; /* Country Code */
282 - u8 ant_available_a; /* A-PHY antenna available bits (up to 4) */
283 - u8 ant_available_bg; /* B/G-PHY antenna available bits (up to 4) */
284 + u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
285 + u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
286 u16 pa0b0;
287 u16 pa0b1;
288 u16 pa0b2;
289 u16 pa1b0;
290 u16 pa1b1;
291 u16 pa1b2;
292 + u16 pa1lob0;
293 + u16 pa1lob1;
294 + u16 pa1lob2;
295 + u16 pa1hib0;
296 + u16 pa1hib1;
297 + u16 pa1hib2;
298 u8 gpio0; /* GPIO pin 0 */
299 u8 gpio1; /* GPIO pin 1 */
300 u8 gpio2; /* GPIO pin 2 */
301 u8 gpio3; /* GPIO pin 3 */
302 - u16 maxpwr_a; /* A-PHY Amplifier Max Power (in dBm Q5.2) */
303 - u16 maxpwr_bg; /* B/G-PHY Amplifier Max Power (in dBm Q5.2) */
304 + u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
305 + u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
306 + u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
307 + u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
308 u8 itssi_a; /* Idle TSSI Target for A-PHY */
309 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
310 - u16 boardflags_lo; /* Boardflags (low 16 bits) */
311 - u16 boardflags_hi; /* Boardflags (high 16 bits) */
312 + u8 tri2g; /* 2.4GHz TX isolation */
313 + u8 tri5gl; /* 5.2GHz TX isolation */
314 + u8 tri5g; /* 5.3GHz TX isolation */
315 + u8 tri5gh; /* 5.8GHz TX isolation */
316 + u8 rxpo2g; /* 2GHz RX power offset */
317 + u8 rxpo5g; /* 5GHz RX power offset */
318 + u8 rssisav2g; /* 2GHz RSSI params */
319 + u8 rssismc2g;
320 + u8 rssismf2g;
321 + u8 bxa2g; /* 2GHz BX arch */
322 + u8 rssisav5g; /* 5GHz RSSI params */
323 + u8 rssismc5g;
324 + u8 rssismf5g;
325 + u8 bxa5g; /* 5GHz BX arch */
326 + u16 cck2gpo; /* CCK power offset */
327 + u32 ofdm2gpo; /* 2.4GHz OFDM power offset */
328 + u32 ofdm5glpo; /* 5.2GHz OFDM power offset */
329 + u32 ofdm5gpo; /* 5.3GHz OFDM power offset */
330 + u32 ofdm5ghpo; /* 5.8GHz OFDM power offset */
331 + u16 boardflags_lo; /* Board flags (bits 0-15) */
332 + u16 boardflags_hi; /* Board flags (bits 16-31) */
333 + u16 boardflags2_lo; /* Board flags (bits 32-47) */
334 + u16 boardflags2_hi; /* Board flags (bits 48-63) */
335 + /* TODO store board flags in a single u64 */
336
337 /* Antenna gain values for up to 4 antennas
338 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
339 @@ -58,7 +88,7 @@ struct ssb_sprom {
340 } ghz5; /* 5GHz band */
341 } antenna_gain;
342
343 - /* TODO - add any parameters needed from rev 2, 3, or 4 SPROMs */
344 + /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
345 };
346
347 /* Information about the PCB the circuitry is soldered on. */
348 @@ -208,6 +238,7 @@ enum ssb_bustype {
349 SSB_BUSTYPE_SSB, /* This SSB bus is the system bus */
350 SSB_BUSTYPE_PCI, /* SSB is connected to PCI bus */
351 SSB_BUSTYPE_PCMCIA, /* SSB is connected to PCMCIA bus */
352 + SSB_BUSTYPE_SDIO, /* SSB is connected to SDIO bus */
353 };
354
355 /* board_vendor */
356 @@ -240,8 +271,12 @@ struct ssb_bus {
357
358 /* The core in the basic address register window. (PCI bus only) */
359 struct ssb_device *mapped_device;
360 - /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
361 - u8 mapped_pcmcia_seg;
362 + union {
363 + /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
364 + u8 mapped_pcmcia_seg;
365 + /* Current SSB base address window for SDIO. */
366 + u32 sdio_sbaddr;
367 + };
368 /* Lock for core and segment switching.
369 * On PCMCIA-host busses this is used to protect the whole MMIO access. */
370 spinlock_t bar_lock;
371 @@ -252,6 +287,11 @@ struct ssb_bus {
372 struct pci_dev *host_pci;
373 /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
374 struct pcmcia_device *host_pcmcia;
375 + /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
376 + struct sdio_func *host_sdio;
377 +
378 + /* See enum ssb_quirks */
379 + unsigned int quirks;
380
381 #ifdef CONFIG_SSB_SPROM
382 /* Mutex to protect the SPROM writing. */
383 @@ -306,6 +346,11 @@ struct ssb_bus {
384 #endif /* DEBUG */
385 };
386
387 +enum ssb_quirks {
388 + /* SDIO connected card requires performing a read after writing a 32-bit value */
389 + SSB_QUIRK_SDIO_READ_AFTER_WRITE32 = (1 << 0),
390 +};
391 +
392 /* The initialization-invariants. */
393 struct ssb_init_invariants {
394 /* Versioning information about the PCB. */
395 --- a/include/linux/ssb/ssb_driver_chipcommon.h
396 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
397 @@ -629,5 +629,15 @@ extern int ssb_chipco_serial_init(struct
398 /* PMU support */
399 extern void ssb_pmu_init(struct ssb_chipcommon *cc);
400
401 +enum ssb_pmu_ldo_volt_id {
402 + LDO_PAREF = 0,
403 + LDO_VOLT1,
404 + LDO_VOLT2,
405 + LDO_VOLT3,
406 +};
407 +
408 +void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
409 + enum ssb_pmu_ldo_volt_id id, u32 voltage);
410 +void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
411
412 #endif /* LINUX_SSB_CHIPCO_H_ */
413 --- a/include/linux/ssb/ssb_regs.h
414 +++ b/include/linux/ssb/ssb_regs.h
415 @@ -162,7 +162,7 @@
416
417 /* SPROM shadow area. If not otherwise noted, fields are
418 * two bytes wide. Note that the SPROM can _only_ be read
419 - * in two-byte quantinies.
420 + * in two-byte quantities.
421 */
422 #define SSB_SPROMSIZE_WORDS 64
423 #define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16))
424 @@ -327,8 +327,11 @@
425 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
426
427 /* SPROM Revision 8 */
428 -#define SSB_SPROM8_BFLLO 0x1084 /* Boardflags (low 16 bits) */
429 -#define SSB_SPROM8_BFLHI 0x1086 /* Boardflags Hi */
430 +#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
431 +#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
432 +#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
433 +#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
434 +#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
435 #define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
436 #define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
437 #define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
438 @@ -354,14 +357,63 @@
439 #define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
440 #define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
441 #define SSB_SPROM8_GPIOB_P3_SHIFT 8
442 -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power BG in path 1 */
443 -#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
444 +#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
445 +#define SSB_SPROM8_RSSISMF2G 0x000F
446 +#define SSB_SPROM8_RSSISMC2G 0x00F0
447 +#define SSB_SPROM8_RSSISMC2G_SHIFT 4
448 +#define SSB_SPROM8_RSSISAV2G 0x0700
449 +#define SSB_SPROM8_RSSISAV2G_SHIFT 8
450 +#define SSB_SPROM8_BXA2G 0x1800
451 +#define SSB_SPROM8_BXA2G_SHIFT 11
452 +#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
453 +#define SSB_SPROM8_RSSISMF5G 0x000F
454 +#define SSB_SPROM8_RSSISMC5G 0x00F0
455 +#define SSB_SPROM8_RSSISMC5G_SHIFT 4
456 +#define SSB_SPROM8_RSSISAV5G 0x0700
457 +#define SSB_SPROM8_RSSISAV5G_SHIFT 8
458 +#define SSB_SPROM8_BXA5G 0x1800
459 +#define SSB_SPROM8_BXA5G_SHIFT 11
460 +#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
461 +#define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
462 +#define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
463 +#define SSB_SPROM8_TRI5G_SHIFT 8
464 +#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
465 +#define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
466 +#define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
467 +#define SSB_SPROM8_TRI5GH_SHIFT 8
468 +#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
469 +#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
470 +#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
471 +#define SSB_SPROM8_RXPO5G_SHIFT 8
472 +#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
473 +#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
474 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
475 #define SSB_SPROM8_ITSSI_BG_SHIFT 8
476 -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power A in path 1 */
477 -#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
478 +#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
479 +#define SSB_SPROM8_PA0B1 0x10C4
480 +#define SSB_SPROM8_PA0B2 0x10C6
481 +#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
482 +#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
483 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
484 #define SSB_SPROM8_ITSSI_A_SHIFT 8
485 +#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
486 +#define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
487 +#define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
488 +#define SSB_SPROM8_MAXP_AL_SHIFT 8
489 +#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
490 +#define SSB_SPROM8_PA1B1 0x10CE
491 +#define SSB_SPROM8_PA1B2 0x10D0
492 +#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
493 +#define SSB_SPROM8_PA1LOB1 0x10D4
494 +#define SSB_SPROM8_PA1LOB2 0x10D6
495 +#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
496 +#define SSB_SPROM8_PA1HIB1 0x10DA
497 +#define SSB_SPROM8_PA1HIB2 0x10DC
498 +#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
499 +#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
500 +#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
501 +#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
502 +#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
503
504 /* Values for SSB_SPROM1_BINF_CCODE */
505 enum {
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