target/linux/atheros/files/include/asm-mips/mach-atheros/ar531x.h

   1 #ifndef __AR531X_H
   2 #define __AR531X_H
   3
   4 #include <linux/version.h>
   5 #include <asm/cpu-info.h>
   6 #include <ar531x_platform.h>
   7 #include <ar5312/ar5312.h>
   8 #include <ar5315/ar5315.h>
   9
  10 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24))
  11 extern void (*board_time_init)(void);
  12 #endif
  13
  14 /*
  15  * Atheros CPUs before the AR2315 are using MIPS 4Kc core, later designs are
  16  * using MIPS 4KEc R2 core. This makes it easy to determine the board at runtime.
  17  */
  18 #ifdef CONFIG_ATHEROS_AR5312
  19 #define DO_AR5312(...) \
  20         if (current_cpu_data.cputype != CPU_4KEC) { \
  21                 __VA_ARGS__ \
  22         }
  23 #else
  24 #define DO_AR5312(...)
  25 #endif
  26 #ifdef CONFIG_ATHEROS_AR5315
  27 #define DO_AR5315(...) \
  28         if (current_cpu_data.cputype == CPU_4KEC) { \
  29                 __VA_ARGS__ \
  30         }
  31 #else
  32 #define DO_AR5315(...)
  33 #endif
  34
  35 #define AR531X_MISC_IRQ_BASE            0x20
  36 #define AR531X_GPIO_IRQ_BASE            0x30
  37
  38 /* Software's idea of interrupts handled by "CPU Interrupt Controller" */
  39 #define AR531X_IRQ_NONE         MIPS_CPU_IRQ_BASE+0
  40 #define AR531X_IRQ_CPU_CLOCK    MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */
  41
  42 /* Miscellaneous interrupts, which share IP6 */
  43 #define AR531X_MISC_IRQ_NONE            AR531X_MISC_IRQ_BASE+0
  44 #define AR531X_MISC_IRQ_TIMER           AR531X_MISC_IRQ_BASE+1
  45 #define AR531X_MISC_IRQ_AHB_PROC        AR531X_MISC_IRQ_BASE+2
  46 #define AR531X_MISC_IRQ_AHB_DMA         AR531X_MISC_IRQ_BASE+3
  47 #define AR531X_MISC_IRQ_GPIO            AR531X_MISC_IRQ_BASE+4
  48 #define AR531X_MISC_IRQ_UART0           AR531X_MISC_IRQ_BASE+5
  49 #define AR531X_MISC_IRQ_UART0_DMA       AR531X_MISC_IRQ_BASE+6
  50 #define AR531X_MISC_IRQ_WATCHDOG        AR531X_MISC_IRQ_BASE+7
  51 #define AR531X_MISC_IRQ_LOCAL           AR531X_MISC_IRQ_BASE+8
  52 #define AR531X_MISC_IRQ_SPI             AR531X_MISC_IRQ_BASE+9
  53 #define AR531X_MISC_IRQ_COUNT           10
  54
  55 /* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
  56 #define AR531X_GPIO_IRQ_NONE            AR531X_GPIO_IRQ_BASE+0
  57 #define AR531X_GPIO_IRQ(n)              AR531X_GPIO_IRQ_BASE+(n)+1
  58 #define AR531X_GPIO_IRQ_COUNT           22
  59
  60 #define sysRegRead(phys)        \
  61         (*(volatile u32 *)KSEG1ADDR(phys))
  62
  63 #define sysRegWrite(phys, val)  \
  64         ((*(volatile u32 *)KSEG1ADDR(phys)) = (val))
  65
  66 /*
  67  * This is board-specific data that is stored in a "fixed" location in flash.
  68  * It is shared across operating systems, so it should not be changed lightly.
  69  * The main reason we need it is in order to extract the ethernet MAC
  70  * address(es).
  71  */
  72 struct ar531x_boarddata {
  73     u32 magic;                       /* board data is valid */
  74 #define AR531X_BD_MAGIC 0x35333131   /* "5311", for all 531x platforms */
  75     u16 cksum;                       /* checksum (starting with BD_REV 2) */
  76     u16 rev;                         /* revision of this struct */
  77 #define BD_REV  4
  78     char   boardName[64];            /* Name of board */
  79     u16 major;                       /* Board major number */
  80     u16 minor;                       /* Board minor number */
  81     u32 config;                      /* Board configuration */
  82 #define BD_ENET0        0x00000001   /* ENET0 is stuffed */
  83 #define BD_ENET1        0x00000002   /* ENET1 is stuffed */
  84 #define BD_UART1        0x00000004   /* UART1 is stuffed */
  85 #define BD_UART0        0x00000008   /* UART0 is stuffed (dma) */
  86 #define BD_RSTFACTORY   0x00000010   /* Reset factory defaults stuffed */
  87 #define BD_SYSLED       0x00000020   /* System LED stuffed */
  88 #define BD_EXTUARTCLK   0x00000040   /* External UART clock */
  89 #define BD_CPUFREQ      0x00000080   /* cpu freq is valid in nvram */
  90 #define BD_SYSFREQ      0x00000100   /* sys freq is set in nvram */
  91 #define BD_WLAN0        0x00000200   /* Enable WLAN0 */
  92 #define BD_MEMCAP       0x00000400   /* CAP SDRAM @ memCap for testing */
  93 #define BD_DISWATCHDOG  0x00000800   /* disable system watchdog */
  94 #define BD_WLAN1        0x00001000   /* Enable WLAN1 (ar5212) */
  95 #define BD_ISCASPER     0x00002000   /* FLAG for AR2312 */
  96 #define BD_WLAN0_2G_EN  0x00004000   /* FLAG for radio0_2G */
  97 #define BD_WLAN0_5G_EN  0x00008000   /* FLAG for radio0_2G */
  98 #define BD_WLAN1_2G_EN  0x00020000   /* FLAG for radio0_2G */
  99 #define BD_WLAN1_5G_EN  0x00040000   /* FLAG for radio0_2G */
 100     u16 resetConfigGpio;             /* Reset factory GPIO pin */
 101     u16 sysLedGpio;                  /* System LED GPIO pin */
 102
 103     u32 cpuFreq;                     /* CPU core frequency in Hz */
 104     u32 sysFreq;                     /* System frequency in Hz */
 105     u32 cntFreq;                     /* Calculated C0_COUNT frequency */
 106
 107     u8  wlan0Mac[6];
 108     u8  enet0Mac[6];
 109     u8  enet1Mac[6];
 110
 111     u16 pciId;                       /* Pseudo PCIID for common code */
 112     u16 memCap;                      /* cap bank1 in MB */
 113
 114     /* version 3 */
 115     u8  wlan1Mac[6];                 /* (ar5212) */
 116 };
 117
 118 #define BOARD_CONFIG_BUFSZ              0x1000
 119
 120 extern char *board_config, *radio_config;
 121 extern void serial_setup(unsigned long mapbase, unsigned int uartclk);
 122 extern int ar531x_find_config(char *flash_limit);
 123
 124 extern void ar5312_prom_init(void);
 125 extern void ar5312_misc_intr_init(int irq_base);
 126 extern void ar5312_plat_setup(void);
 127 extern asmlinkage void ar5312_irq_dispatch(void);
 128
 129 extern void ar5315_prom_init(void);
 130 extern void ar5315_misc_intr_init(int irq_base);
 131 extern void ar5315_plat_setup(void);
 132 extern asmlinkage void ar5315_irq_dispatch(void);
 133 extern void ar5315_pci_irq(int irq);
 134 static inline u32 sysRegMask(u32 phys, u32 mask, u32 value)
 135 {
 136         u32 reg;
 137
 138         reg = sysRegRead(phys);
 139         reg &= ~mask;
 140         reg |= value & mask;
 141         sysRegWrite(phys, reg);
 142         reg = sysRegRead(phys); /* flush write to the hardware */
 143
 144         return reg;
 145 }
 146
 147 #define AR531X_NUM_GPIO         8
 148
 149 #endif