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[adm5120] fix switch driver, force all packets from all the ports are low priority
[openwrt.git] / target / linux / etrax-2.6 / patches / cris / 010-multi-target-build.patch
1 diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/Makefile linux-2.6.19.2/arch/cris/arch-v10/boot/Makefile
2 --- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/Makefile 2007-05-28 16:28:34.000000000 +0200
3 +++ linux-2.6.19.2/arch/cris/arch-v10/boot/Makefile 2007-05-28 17:24:26.000000000 +0200
4 @@ -5,7 +5,7 @@
5 OBJCOPY = /usr/local/cris/objcopy-cris
6 OBJCOPYFLAGS = -O binary --remove-section=.bss
7
8 -subdir- := compressed rescue
9 +subdir- := compressed
10 targets := Image
11
12 $(obj)/Image: vmlinux FORCE
13 @@ -14,8 +14,12 @@
14
15 $(obj)/compressed/vmlinux: $(obj)/Image FORCE
16 $(Q)$(MAKE) $(build)=$(obj)/compressed $@
17 - $(Q)$(MAKE) $(build)=$(obj)/rescue $(obj)/rescue/rescue.bin
18
19 $(obj)/zImage: $(obj)/compressed/vmlinux
20 @cp $< $@
21 + @cp $(obj)/compressed/vmlinux $(obj)/zImage_custom
22 + @cp $(obj)/compressed/vmlinux_MCM $(obj)/zImage_MCM
23 + @cp $(obj)/compressed/vmlinux_416 $(obj)/zImage_416
24 + @cp $(obj)/compressed/vmlinux_816 $(obj)/zImage_816
25 + @cp $(obj)/compressed/vmlinux_832 $(obj)/zImage_832
26 @echo ' Kernel: $@ is ready'
27 diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/Makefile linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/Makefile
28 --- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/Makefile 2007-05-28 16:28:34.000000000 +0200
29 +++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/Makefile 2007-05-28 17:03:02.000000000 +0200
30 @@ -17,18 +17,34 @@
31
32 $(obj)/decompress.o: $(OBJECTS) FORCE
33 $(call if_changed,ld)
34 + $(LD) $(LDFLAGS) arch/cris/boot/compressed/head_MCM.o arch/cris/boot/compressed/misc.o -o arch/cris/boot/compressed/decompress_MCM.o
35 + $(LD) $(LDFLAGS) arch/cris/boot/compressed/head_416.o arch/cris/boot/compressed/misc.o -o arch/cris/boot/compressed/decompress_416.o
36 + $(LD) $(LDFLAGS) arch/cris/boot/compressed/head_816.o arch/cris/boot/compressed/misc.o -o arch/cris/boot/compressed/decompress_816.o
37 + $(LD) $(LDFLAGS) arch/cris/boot/compressed/head_832.o arch/cris/boot/compressed/misc.o -o arch/cris/boot/compressed/decompress_832.o
38
39 $(obj)/decompress.bin: $(obj)/decompress.o FORCE
40 $(call if_changed,objcopy)
41 + $(OBJCOPY) $(OBJCOPYFLAGS) $(obj)/decompress_MCM.o $(obj)/decompress_MCM.bin
42 + $(OBJCOPY) $(OBJCOPYFLAGS) $(obj)/decompress_416.o $(obj)/decompress_416.bin
43 + $(OBJCOPY) $(OBJCOPYFLAGS) $(obj)/decompress_816.o $(obj)/decompress_816.bin
44 + $(OBJCOPY) $(OBJCOPYFLAGS) $(obj)/decompress_832.o $(obj)/decompress_832.bin
45 +
46 +$(obj)/head.o: $(obj)/head.S .config FORCE
47 + /usr/local/cris/gcc-cris -melf -Iinclude -include include/linux/autoconf.h -D__ASSEMBLY__ -traditional -c $< -o $@
48 + /usr/local/cris/gcc-cris -melf -Iinclude -include include/linux/autoconf.h -D__ASSEMBLY__ -traditional -c arch/cris/boot/compressed/head_MCM.S -o arch/cris/boot/compressed/head_MCM.o
49 + /usr/local/cris/gcc-cris -melf -Iinclude -include include/linux/autoconf.h -D__ASSEMBLY__ -traditional -c arch/cris/boot/compressed/head_416.S -o arch/cris/boot/compressed/head_416.o
50 + /usr/local/cris/gcc-cris -melf -Iinclude -include include/linux/autoconf.h -D__ASSEMBLY__ -traditional -c arch/cris/boot/compressed/head_816.S -o arch/cris/boot/compressed/head_816.o
51 + /usr/local/cris/gcc-cris -melf -Iinclude -include include/linux/autoconf.h -D__ASSEMBLY__ -traditional -c arch/cris/boot/compressed/head_832.S -o arch/cris/boot/compressed/head_832.o
52
53 -$(obj)/head.o: $(obj)/head.S .config
54 - /usr/local/cris/gcc-cris -melf $(LINUXINCLUDE) -D__ASSEMBLY__ -traditional -c $< -o $@
55 -
56 -$(obj)/misc.o: $(obj)/misc.c .config
57 +$(obj)/misc.o: $(obj)/misc.c .config FORCE
58 /usr/local/cris/gcc-cris -melf $(LINUXINCLUDE) -D__KERNEL__ -c $< -o $@
59
60 $(obj)/vmlinux: $(obj)/piggy.gz $(obj)/decompress.bin FORCE
61 $(call if_changed,image)
62 + cat $(obj)/decompress_MCM.bin $(obj)/piggy.gz > $(obj)/vmlinux_MCM
63 + cat $(obj)/decompress_416.bin $(obj)/piggy.gz > $(obj)/vmlinux_416
64 + cat $(obj)/decompress_816.bin $(obj)/piggy.gz > $(obj)/vmlinux_816
65 + cat $(obj)/decompress_832.bin $(obj)/piggy.gz > $(obj)/vmlinux_832
66
67 $(obj)/piggy.gz: $(obj)/../Image FORCE
68 $(call if_changed,gzip)
69 diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/dram_init.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/dram_init.S
70 --- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/dram_init.S 1970-01-01 01:00:00.000000000 +0100
71 +++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/dram_init.S 2007-05-28 16:42:15.000000000 +0200
72 @@ -0,0 +1,207 @@
73 +/* $Id: dram_init.S,v 1.5 2006/10/13 12:43:11 starvik Exp $
74 + *
75 + * DRAM/SDRAM initialization - alter with care
76 + * This file is intended to be included from other assembler files
77 + *
78 + * Note: This file may not modify r9 because r9 is used to carry
79 + * information from the decompresser to the kernel
80 + *
81 + * Copyright (C) 2000, 2001 Axis Communications AB
82 + *
83 + * Authors: Mikael Starvik (starvik@axis.com)
84 + *
85 + * $Log: dram_init.S,v $
86 + * Revision 1.5 2006/10/13 12:43:11 starvik
87 + * Merge of 2.6.18
88 + *
89 + * Revision 1.4 2003/09/22 09:21:59 starvik
90 + * Decompresser is linked to 0x407xxxxx and sdram commands are at 0x000xxxxx
91 + * so we need to mask off 12 bits.
92 + *
93 + * Revision 1.3 2003/03/31 09:38:37 starvik
94 + * Corrected calculation of end of sdram init commands
95 + *
96 + * Revision 1.2 2002/11/19 13:33:29 starvik
97 + * Changes from Linux 2.4
98 + *
99 + * Revision 1.13 2002/10/30 07:42:28 starvik
100 + * Always read SDRAM command sequence from flash
101 + *
102 + * Revision 1.12 2002/08/09 11:37:37 orjanf
103 + * Added double initialization work-around for Samsung SDRAMs.
104 + *
105 + * Revision 1.11 2002/06/04 11:43:21 starvik
106 + * Check if mrs_data is specified in kernelconfig (necessary for MCM)
107 + *
108 + * Revision 1.10 2001/10/04 12:00:21 martinnn
109 + * Added missing underscores.
110 + *
111 + * Revision 1.9 2001/10/01 14:47:35 bjornw
112 + * Added register prefixes and removed underscores
113 + *
114 + * Revision 1.8 2001/05/15 07:12:45 hp
115 + * Copy warning from head.S about r8 and r9
116 + *
117 + * Revision 1.7 2001/04/18 12:05:39 bjornw
118 + * Fixed comments, and explicitely include config.h to be sure its there
119 + *
120 + * Revision 1.6 2001/04/10 06:20:16 starvik
121 + * Delay should be 200us, not 200ns
122 + *
123 + * Revision 1.5 2001/04/09 06:01:13 starvik
124 + * Added support for 100 MHz SDRAMs
125 + *
126 + * Revision 1.4 2001/03/26 14:24:01 bjornw
127 + * Namechange of some config options
128 + *
129 + * Revision 1.3 2001/03/23 08:29:41 starvik
130 + * Corrected calculation of mrs_data
131 + *
132 + * Revision 1.2 2001/02/08 15:20:00 starvik
133 + * Corrected SDRAM initialization
134 + * Should now be included as inline
135 + *
136 + * Revision 1.1 2001/01/29 13:08:02 starvik
137 + * Initial version
138 + * This file should be included from all assembler files that needs to
139 + * initialize DRAM/SDRAM.
140 + *
141 + */
142 +
143 +/* Just to be certain the config file is included, we include it here
144 + * explicitely instead of depending on it being included in the file that
145 + * uses this code.
146 + */
147 +
148 +
149 + ;; WARNING! The registers r8 and r9 are used as parameters carrying
150 + ;; information from the decompressor (if the kernel was compressed).
151 + ;; They should not be used in the code below.
152 +
153 +#ifndef CONFIG_SVINTO_SIM
154 + move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
155 + move.d $r0, [R_WAITSTATES]
156 +
157 + move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
158 + move.d $r0, [R_BUS_CONFIG]
159 +
160 +#ifndef CONFIG_ETRAX_SDRAM
161 + move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
162 + move.d $r0, [R_DRAM_CONFIG]
163 +
164 + move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
165 + move.d $r0, [R_DRAM_TIMING]
166 +#else
167 + ;; Samsung SDRAMs seem to require to be initialized twice to work properly.
168 + moveq 2, $r6
169 +_sdram_init:
170 +
171 + ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
172 +
173 + ; Bank configuration
174 + move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r0
175 + move.d $r0, [R_SDRAM_CONFIG]
176 +
177 + ; Calculate value of mrs_data
178 + ; CAS latency = 2 && bus_width = 32 => 0x40
179 + ; CAS latency = 3 && bus_width = 32 => 0x60
180 + ; CAS latency = 2 && bus_width = 16 => 0x20
181 + ; CAS latency = 3 && bus_width = 16 => 0x30
182 +
183 + ; Check if value is already supplied in kernel config
184 + move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r2
185 + and.d 0x00ff0000, $r2
186 + bne _set_timing
187 + lsrq 16, $r2
188 +
189 + move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
190 + move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
191 + move.d $r1, $r3
192 + and.d 0x03, $r1 ; Get CAS latency
193 + and.d 0x1000, $r3 ; 50 or 100 MHz?
194 + beq _speed_50
195 + nop
196 +_speed_100:
197 + cmp.d 0x00, $r1 ; CAS latency = 2?
198 + beq _bw_check
199 + nop
200 + or.d 0x20, $r2 ; CAS latency = 3
201 + ba _bw_check
202 + nop
203 +_speed_50:
204 + cmp.d 0x01, $r1 ; CAS latency = 2?
205 + beq _bw_check
206 + nop
207 + or.d 0x20, $r2 ; CAS latency = 3
208 +_bw_check:
209 + move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r1
210 + and.d 0x800000, $r1 ; DRAM width is bit 23
211 + bne _set_timing
212 + nop
213 + lsrq 1, $r2 ; 16 bits. Shift down value.
214 +
215 + ; Set timing parameters. Starts master clock
216 +_set_timing:
217 + move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
218 + and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
219 + or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
220 + move.d $r1, $r5
221 + or.d 0x0000c000, $r1 ; ref = disable
222 + lslq 16, $r2 ; mrs data starts at bit 16
223 + or.d $r2, $r1
224 + move.d $r1, [R_SDRAM_TIMING]
225 +
226 + ; Wait 200us
227 + move.d 10000, $r2
228 +1: bne 1b
229 + subq 1, $r2
230 +
231 + ; Issue initialization command sequence
232 + move.d _sdram_commands_start, $r2
233 + and.d 0x000fffff, $r2 ; Make sure commands are read from flash
234 + move.d _sdram_commands_end, $r3
235 + and.d 0x000fffff, $r3
236 +1: clear.d $r4
237 + move.b [$r2+], $r4
238 + lslq 9, $r4 ; Command starts at bit 9
239 + or.d $r1, $r4
240 + move.d $r4, [R_SDRAM_TIMING]
241 + nop ; Wait five nop cycles between each command
242 + nop
243 + nop
244 + nop
245 + nop
246 + cmp.d $r2, $r3
247 + bne 1b
248 + nop
249 + move.d $r5, [R_SDRAM_TIMING]
250 + subq 1, $r6
251 + bne _sdram_init
252 + nop
253 + ba _sdram_commands_end
254 + nop
255 +
256 +_sdram_commands_start:
257 + .byte 3 ; Precharge
258 + .byte 0 ; nop
259 + .byte 2 ; refresh
260 + .byte 0 ; nop
261 + .byte 2 ; refresh
262 + .byte 0 ; nop
263 + .byte 2 ; refresh
264 + .byte 0 ; nop
265 + .byte 2 ; refresh
266 + .byte 0 ; nop
267 + .byte 2 ; refresh
268 + .byte 0 ; nop
269 + .byte 2 ; refresh
270 + .byte 0 ; nop
271 + .byte 2 ; refresh
272 + .byte 0 ; nop
273 + .byte 2 ; refresh
274 + .byte 0 ; nop
275 + .byte 1 ; mrs
276 + .byte 0 ; nop
277 +_sdram_commands_end:
278 +#endif
279 +#endif
280 diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/dram_init_416.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/dram_init_416.S
281 --- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/dram_init_416.S 1970-01-01 01:00:00.000000000 +0100
282 +++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/dram_init_416.S 2007-05-28 20:02:25.000000000 +0200
283 @@ -0,0 +1,207 @@
284 +/* $Id: dram_init.S,v 1.5 2006/10/13 12:43:11 starvik Exp $
285 + *
286 + * DRAM/SDRAM initialization - alter with care
287 + * This file is intended to be included from other assembler files
288 + *
289 + * Note: This file may not modify r9 because r9 is used to carry
290 + * information from the decompresser to the kernel
291 + *
292 + * Copyright (C) 2000, 2001 Axis Communications AB
293 + *
294 + * Authors: Mikael Starvik (starvik@axis.com)
295 + *
296 + * $Log: dram_init.S,v $
297 + * Revision 1.5 2006/10/13 12:43:11 starvik
298 + * Merge of 2.6.18
299 + *
300 + * Revision 1.4 2003/09/22 09:21:59 starvik
301 + * Decompresser is linked to 0x407xxxxx and sdram commands are at 0x000xxxxx
302 + * so we need to mask off 12 bits.
303 + *
304 + * Revision 1.3 2003/03/31 09:38:37 starvik
305 + * Corrected calculation of end of sdram init commands
306 + *
307 + * Revision 1.2 2002/11/19 13:33:29 starvik
308 + * Changes from Linux 2.4
309 + *
310 + * Revision 1.13 2002/10/30 07:42:28 starvik
311 + * Always read SDRAM command sequence from flash
312 + *
313 + * Revision 1.12 2002/08/09 11:37:37 orjanf
314 + * Added double initialization work-around for Samsung SDRAMs.
315 + *
316 + * Revision 1.11 2002/06/04 11:43:21 starvik
317 + * Check if mrs_data is specified in kernelconfig (necessary for MCM)
318 + *
319 + * Revision 1.10 2001/10/04 12:00:21 martinnn
320 + * Added missing underscores.
321 + *
322 + * Revision 1.9 2001/10/01 14:47:35 bjornw
323 + * Added register prefixes and removed underscores
324 + *
325 + * Revision 1.8 2001/05/15 07:12:45 hp
326 + * Copy warning from head.S about r8 and r9
327 + *
328 + * Revision 1.7 2001/04/18 12:05:39 bjornw
329 + * Fixed comments, and explicitely include config.h to be sure its there
330 + *
331 + * Revision 1.6 2001/04/10 06:20:16 starvik
332 + * Delay should be 200us, not 200ns
333 + *
334 + * Revision 1.5 2001/04/09 06:01:13 starvik
335 + * Added support for 100 MHz SDRAMs
336 + *
337 + * Revision 1.4 2001/03/26 14:24:01 bjornw
338 + * Namechange of some config options
339 + *
340 + * Revision 1.3 2001/03/23 08:29:41 starvik
341 + * Corrected calculation of mrs_data
342 + *
343 + * Revision 1.2 2001/02/08 15:20:00 starvik
344 + * Corrected SDRAM initialization
345 + * Should now be included as inline
346 + *
347 + * Revision 1.1 2001/01/29 13:08:02 starvik
348 + * Initial version
349 + * This file should be included from all assembler files that needs to
350 + * initialize DRAM/SDRAM.
351 + *
352 + */
353 +
354 +/* Just to be certain the config file is included, we include it here
355 + * explicitely instead of depending on it being included in the file that
356 + * uses this code.
357 + */
358 +
359 +
360 + ;; WARNING! The registers r8 and r9 are used as parameters carrying
361 + ;; information from the decompressor (if the kernel was compressed).
362 + ;; They should not be used in the code below.
363 +
364 +#ifndef CONFIG_SVINTO_SIM
365 + move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
366 + move.d $r0, [R_WAITSTATES]
367 +
368 + move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
369 + move.d $r0, [R_BUS_CONFIG]
370 +
371 +#ifndef CONFIG_ETRAX_SDRAM
372 + move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
373 + move.d $r0, [R_DRAM_CONFIG]
374 +
375 + move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
376 + move.d $r0, [R_DRAM_TIMING]
377 +#else
378 + ;; Samsung SDRAMs seem to require to be initialized twice to work properly.
379 + moveq 2, $r6
380 +_sdram_init:
381 +
382 + ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
383 +
384 + ; Bank configuration
385 + move.d 0x09603636, $r0
386 + move.d $r0, [R_SDRAM_CONFIG]
387 +
388 + ; Calculate value of mrs_data
389 + ; CAS latency = 2 && bus_width = 32 => 0x40
390 + ; CAS latency = 3 && bus_width = 32 => 0x60
391 + ; CAS latency = 2 && bus_width = 16 => 0x20
392 + ; CAS latency = 3 && bus_width = 16 => 0x30
393 +
394 + ; Check if value is already supplied in kernel config
395 + move.d 0x80008002, $r2
396 + and.d 0x00ff0000, $r2
397 + bne _set_timing
398 + lsrq 16, $r2
399 +
400 + move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
401 + move.d 0x80008002, $r1
402 + move.d $r1, $r3
403 + and.d 0x03, $r1 ; Get CAS latency
404 + and.d 0x1000, $r3 ; 50 or 100 MHz?
405 + beq _speed_50
406 + nop
407 +_speed_100:
408 + cmp.d 0x00, $r1 ; CAS latency = 2?
409 + beq _bw_check
410 + nop
411 + or.d 0x20, $r2 ; CAS latency = 3
412 + ba _bw_check
413 + nop
414 +_speed_50:
415 + cmp.d 0x01, $r1 ; CAS latency = 2?
416 + beq _bw_check
417 + nop
418 + or.d 0x20, $r2 ; CAS latency = 3
419 +_bw_check:
420 + move.d 0x09603636, $r1
421 + and.d 0x800000, $r1 ; DRAM width is bit 23
422 + bne _set_timing
423 + nop
424 + lsrq 1, $r2 ; 16 bits. Shift down value.
425 +
426 + ; Set timing parameters. Starts master clock
427 +_set_timing:
428 + move.d 0x80008002, $r1
429 + and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
430 + or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
431 + move.d $r1, $r5
432 + or.d 0x0000c000, $r1 ; ref = disable
433 + lslq 16, $r2 ; mrs data starts at bit 16
434 + or.d $r2, $r1
435 + move.d $r1, [R_SDRAM_TIMING]
436 +
437 + ; Wait 200us
438 + move.d 10000, $r2
439 +1: bne 1b
440 + subq 1, $r2
441 +
442 + ; Issue initialization command sequence
443 + move.d _sdram_commands_start, $r2
444 + and.d 0x000fffff, $r2 ; Make sure commands are read from flash
445 + move.d _sdram_commands_end, $r3
446 + and.d 0x000fffff, $r3
447 +1: clear.d $r4
448 + move.b [$r2+], $r4
449 + lslq 9, $r4 ; Command starts at bit 9
450 + or.d $r1, $r4
451 + move.d $r4, [R_SDRAM_TIMING]
452 + nop ; Wait five nop cycles between each command
453 + nop
454 + nop
455 + nop
456 + nop
457 + cmp.d $r2, $r3
458 + bne 1b
459 + nop
460 + move.d $r5, [R_SDRAM_TIMING]
461 + subq 1, $r6
462 + bne _sdram_init
463 + nop
464 + ba _sdram_commands_end
465 + nop
466 +
467 +_sdram_commands_start:
468 + .byte 3 ; Precharge
469 + .byte 0 ; nop
470 + .byte 2 ; refresh
471 + .byte 0 ; nop
472 + .byte 2 ; refresh
473 + .byte 0 ; nop
474 + .byte 2 ; refresh
475 + .byte 0 ; nop
476 + .byte 2 ; refresh
477 + .byte 0 ; nop
478 + .byte 2 ; refresh
479 + .byte 0 ; nop
480 + .byte 2 ; refresh
481 + .byte 0 ; nop
482 + .byte 2 ; refresh
483 + .byte 0 ; nop
484 + .byte 2 ; refresh
485 + .byte 0 ; nop
486 + .byte 1 ; mrs
487 + .byte 0 ; nop
488 +_sdram_commands_end:
489 +#endif
490 +#endif
491 diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/dram_init_816.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/dram_init_816.S
492 --- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/dram_init_816.S 1970-01-01 01:00:00.000000000 +0100
493 +++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/dram_init_816.S 2007-05-28 20:04:05.000000000 +0200
494 @@ -0,0 +1,207 @@
495 +/* $Id: dram_init.S,v 1.5 2006/10/13 12:43:11 starvik Exp $
496 + *
497 + * DRAM/SDRAM initialization - alter with care
498 + * This file is intended to be included from other assembler files
499 + *
500 + * Note: This file may not modify r9 because r9 is used to carry
501 + * information from the decompresser to the kernel
502 + *
503 + * Copyright (C) 2000, 2001 Axis Communications AB
504 + *
505 + * Authors: Mikael Starvik (starvik@axis.com)
506 + *
507 + * $Log: dram_init.S,v $
508 + * Revision 1.5 2006/10/13 12:43:11 starvik
509 + * Merge of 2.6.18
510 + *
511 + * Revision 1.4 2003/09/22 09:21:59 starvik
512 + * Decompresser is linked to 0x407xxxxx and sdram commands are at 0x000xxxxx
513 + * so we need to mask off 12 bits.
514 + *
515 + * Revision 1.3 2003/03/31 09:38:37 starvik
516 + * Corrected calculation of end of sdram init commands
517 + *
518 + * Revision 1.2 2002/11/19 13:33:29 starvik
519 + * Changes from Linux 2.4
520 + *
521 + * Revision 1.13 2002/10/30 07:42:28 starvik
522 + * Always read SDRAM command sequence from flash
523 + *
524 + * Revision 1.12 2002/08/09 11:37:37 orjanf
525 + * Added double initialization work-around for Samsung SDRAMs.
526 + *
527 + * Revision 1.11 2002/06/04 11:43:21 starvik
528 + * Check if mrs_data is specified in kernelconfig (necessary for MCM)
529 + *
530 + * Revision 1.10 2001/10/04 12:00:21 martinnn
531 + * Added missing underscores.
532 + *
533 + * Revision 1.9 2001/10/01 14:47:35 bjornw
534 + * Added register prefixes and removed underscores
535 + *
536 + * Revision 1.8 2001/05/15 07:12:45 hp
537 + * Copy warning from head.S about r8 and r9
538 + *
539 + * Revision 1.7 2001/04/18 12:05:39 bjornw
540 + * Fixed comments, and explicitely include config.h to be sure its there
541 + *
542 + * Revision 1.6 2001/04/10 06:20:16 starvik
543 + * Delay should be 200us, not 200ns
544 + *
545 + * Revision 1.5 2001/04/09 06:01:13 starvik
546 + * Added support for 100 MHz SDRAMs
547 + *
548 + * Revision 1.4 2001/03/26 14:24:01 bjornw
549 + * Namechange of some config options
550 + *
551 + * Revision 1.3 2001/03/23 08:29:41 starvik
552 + * Corrected calculation of mrs_data
553 + *
554 + * Revision 1.2 2001/02/08 15:20:00 starvik
555 + * Corrected SDRAM initialization
556 + * Should now be included as inline
557 + *
558 + * Revision 1.1 2001/01/29 13:08:02 starvik
559 + * Initial version
560 + * This file should be included from all assembler files that needs to
561 + * initialize DRAM/SDRAM.
562 + *
563 + */
564 +
565 +/* Just to be certain the config file is included, we include it here
566 + * explicitely instead of depending on it being included in the file that
567 + * uses this code.
568 + */
569 +
570 +
571 + ;; WARNING! The registers r8 and r9 are used as parameters carrying
572 + ;; information from the decompressor (if the kernel was compressed).
573 + ;; They should not be used in the code below.
574 +
575 +#ifndef CONFIG_SVINTO_SIM
576 + move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
577 + move.d $r0, [R_WAITSTATES]
578 +
579 + move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
580 + move.d $r0, [R_BUS_CONFIG]
581 +
582 +#ifndef CONFIG_ETRAX_SDRAM
583 + move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
584 + move.d $r0, [R_DRAM_CONFIG]
585 +
586 + move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
587 + move.d $r0, [R_DRAM_TIMING]
588 +#else
589 + ;; Samsung SDRAMs seem to require to be initialized twice to work properly.
590 + moveq 2, $r6
591 +_sdram_init:
592 +
593 + ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
594 +
595 + ; Bank configuration
596 + move.d 0x09603636, $r0
597 + move.d $r0, [R_SDRAM_CONFIG]
598 +
599 + ; Calculate value of mrs_data
600 + ; CAS latency = 2 && bus_width = 32 => 0x40
601 + ; CAS latency = 3 && bus_width = 32 => 0x60
602 + ; CAS latency = 2 && bus_width = 16 => 0x20
603 + ; CAS latency = 3 && bus_width = 16 => 0x30
604 +
605 + ; Check if value is already supplied in kernel config
606 + move.d 0x80008002, $r2
607 + and.d 0x00ff0000, $r2
608 + bne _set_timing
609 + lsrq 16, $r2
610 +
611 + move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
612 + move.d 0x80008002, $r1
613 + move.d $r1, $r3
614 + and.d 0x03, $r1 ; Get CAS latency
615 + and.d 0x1000, $r3 ; 50 or 100 MHz?
616 + beq _speed_50
617 + nop
618 +_speed_100:
619 + cmp.d 0x00, $r1 ; CAS latency = 2?
620 + beq _bw_check
621 + nop
622 + or.d 0x20, $r2 ; CAS latency = 3
623 + ba _bw_check
624 + nop
625 +_speed_50:
626 + cmp.d 0x01, $r1 ; CAS latency = 2?
627 + beq _bw_check
628 + nop
629 + or.d 0x20, $r2 ; CAS latency = 3
630 +_bw_check:
631 + move.d 0x09603636, $r1
632 + and.d 0x800000, $r1 ; DRAM width is bit 23
633 + bne _set_timing
634 + nop
635 + lsrq 1, $r2 ; 16 bits. Shift down value.
636 +
637 + ; Set timing parameters. Starts master clock
638 +_set_timing:
639 + move.d 0x80008002, $r1
640 + and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
641 + or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
642 + move.d $r1, $r5
643 + or.d 0x0000c000, $r1 ; ref = disable
644 + lslq 16, $r2 ; mrs data starts at bit 16
645 + or.d $r2, $r1
646 + move.d $r1, [R_SDRAM_TIMING]
647 +
648 + ; Wait 200us
649 + move.d 10000, $r2
650 +1: bne 1b
651 + subq 1, $r2
652 +
653 + ; Issue initialization command sequence
654 + move.d _sdram_commands_start, $r2
655 + and.d 0x000fffff, $r2 ; Make sure commands are read from flash
656 + move.d _sdram_commands_end, $r3
657 + and.d 0x000fffff, $r3
658 +1: clear.d $r4
659 + move.b [$r2+], $r4
660 + lslq 9, $r4 ; Command starts at bit 9
661 + or.d $r1, $r4
662 + move.d $r4, [R_SDRAM_TIMING]
663 + nop ; Wait five nop cycles between each command
664 + nop
665 + nop
666 + nop
667 + nop
668 + cmp.d $r2, $r3
669 + bne 1b
670 + nop
671 + move.d $r5, [R_SDRAM_TIMING]
672 + subq 1, $r6
673 + bne _sdram_init
674 + nop
675 + ba _sdram_commands_end
676 + nop
677 +
678 +_sdram_commands_start:
679 + .byte 3 ; Precharge
680 + .byte 0 ; nop
681 + .byte 2 ; refresh
682 + .byte 0 ; nop
683 + .byte 2 ; refresh
684 + .byte 0 ; nop
685 + .byte 2 ; refresh
686 + .byte 0 ; nop
687 + .byte 2 ; refresh
688 + .byte 0 ; nop
689 + .byte 2 ; refresh
690 + .byte 0 ; nop
691 + .byte 2 ; refresh
692 + .byte 0 ; nop
693 + .byte 2 ; refresh
694 + .byte 0 ; nop
695 + .byte 2 ; refresh
696 + .byte 0 ; nop
697 + .byte 1 ; mrs
698 + .byte 0 ; nop
699 +_sdram_commands_end:
700 +#endif
701 +#endif
702 diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/dram_init_832.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/dram_init_832.S
703 --- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/dram_init_832.S 1970-01-01 01:00:00.000000000 +0100
704 +++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/dram_init_832.S 2007-05-28 20:04:57.000000000 +0200
705 @@ -0,0 +1,207 @@
706 +/* $Id: dram_init.S,v 1.5 2006/10/13 12:43:11 starvik Exp $
707 + *
708 + * DRAM/SDRAM initialization - alter with care
709 + * This file is intended to be included from other assembler files
710 + *
711 + * Note: This file may not modify r9 because r9 is used to carry
712 + * information from the decompresser to the kernel
713 + *
714 + * Copyright (C) 2000, 2001 Axis Communications AB
715 + *
716 + * Authors: Mikael Starvik (starvik@axis.com)
717 + *
718 + * $Log: dram_init.S,v $
719 + * Revision 1.5 2006/10/13 12:43:11 starvik
720 + * Merge of 2.6.18
721 + *
722 + * Revision 1.4 2003/09/22 09:21:59 starvik
723 + * Decompresser is linked to 0x407xxxxx and sdram commands are at 0x000xxxxx
724 + * so we need to mask off 12 bits.
725 + *
726 + * Revision 1.3 2003/03/31 09:38:37 starvik
727 + * Corrected calculation of end of sdram init commands
728 + *
729 + * Revision 1.2 2002/11/19 13:33:29 starvik
730 + * Changes from Linux 2.4
731 + *
732 + * Revision 1.13 2002/10/30 07:42:28 starvik
733 + * Always read SDRAM command sequence from flash
734 + *
735 + * Revision 1.12 2002/08/09 11:37:37 orjanf
736 + * Added double initialization work-around for Samsung SDRAMs.
737 + *
738 + * Revision 1.11 2002/06/04 11:43:21 starvik
739 + * Check if mrs_data is specified in kernelconfig (necessary for MCM)
740 + *
741 + * Revision 1.10 2001/10/04 12:00:21 martinnn
742 + * Added missing underscores.
743 + *
744 + * Revision 1.9 2001/10/01 14:47:35 bjornw
745 + * Added register prefixes and removed underscores
746 + *
747 + * Revision 1.8 2001/05/15 07:12:45 hp
748 + * Copy warning from head.S about r8 and r9
749 + *
750 + * Revision 1.7 2001/04/18 12:05:39 bjornw
751 + * Fixed comments, and explicitely include config.h to be sure its there
752 + *
753 + * Revision 1.6 2001/04/10 06:20:16 starvik
754 + * Delay should be 200us, not 200ns
755 + *
756 + * Revision 1.5 2001/04/09 06:01:13 starvik
757 + * Added support for 100 MHz SDRAMs
758 + *
759 + * Revision 1.4 2001/03/26 14:24:01 bjornw
760 + * Namechange of some config options
761 + *
762 + * Revision 1.3 2001/03/23 08:29:41 starvik
763 + * Corrected calculation of mrs_data
764 + *
765 + * Revision 1.2 2001/02/08 15:20:00 starvik
766 + * Corrected SDRAM initialization
767 + * Should now be included as inline
768 + *
769 + * Revision 1.1 2001/01/29 13:08:02 starvik
770 + * Initial version
771 + * This file should be included from all assembler files that needs to
772 + * initialize DRAM/SDRAM.
773 + *
774 + */
775 +
776 +/* Just to be certain the config file is included, we include it here
777 + * explicitely instead of depending on it being included in the file that
778 + * uses this code.
779 + */
780 +
781 +
782 + ;; WARNING! The registers r8 and r9 are used as parameters carrying
783 + ;; information from the decompressor (if the kernel was compressed).
784 + ;; They should not be used in the code below.
785 +
786 +#ifndef CONFIG_SVINTO_SIM
787 + move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
788 + move.d $r0, [R_WAITSTATES]
789 +
790 + move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
791 + move.d $r0, [R_BUS_CONFIG]
792 +
793 +#ifndef CONFIG_ETRAX_SDRAM
794 + move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
795 + move.d $r0, [R_DRAM_CONFIG]
796 +
797 + move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
798 + move.d $r0, [R_DRAM_TIMING]
799 +#else
800 + ;; Samsung SDRAMs seem to require to be initialized twice to work properly.
801 + moveq 2, $r6
802 +_sdram_init:
803 +
804 + ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
805 +
806 + ; Bank configuration
807 + move.d 0x09603737, $r0
808 + move.d $r0, [R_SDRAM_CONFIG]
809 +
810 + ; Calculate value of mrs_data
811 + ; CAS latency = 2 && bus_width = 32 => 0x40
812 + ; CAS latency = 3 && bus_width = 32 => 0x60
813 + ; CAS latency = 2 && bus_width = 16 => 0x20
814 + ; CAS latency = 3 && bus_width = 16 => 0x30
815 +
816 + ; Check if value is already supplied in kernel config
817 + move.d 0x80008002, $r2
818 + and.d 0x00ff0000, $r2
819 + bne _set_timing
820 + lsrq 16, $r2
821 +
822 + move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
823 + move.d 0x80008002, $r1
824 + move.d $r1, $r3
825 + and.d 0x03, $r1 ; Get CAS latency
826 + and.d 0x1000, $r3 ; 50 or 100 MHz?
827 + beq _speed_50
828 + nop
829 +_speed_100:
830 + cmp.d 0x00, $r1 ; CAS latency = 2?
831 + beq _bw_check
832 + nop
833 + or.d 0x20, $r2 ; CAS latency = 3
834 + ba _bw_check
835 + nop
836 +_speed_50:
837 + cmp.d 0x01, $r1 ; CAS latency = 2?
838 + beq _bw_check
839 + nop
840 + or.d 0x20, $r2 ; CAS latency = 3
841 +_bw_check:
842 + move.d 0x09603737, $r1
843 + and.d 0x800000, $r1 ; DRAM width is bit 23
844 + bne _set_timing
845 + nop
846 + lsrq 1, $r2 ; 16 bits. Shift down value.
847 +
848 + ; Set timing parameters. Starts master clock
849 +_set_timing:
850 + move.d 0x80008002, $r1
851 + and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
852 + or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
853 + move.d $r1, $r5
854 + or.d 0x0000c000, $r1 ; ref = disable
855 + lslq 16, $r2 ; mrs data starts at bit 16
856 + or.d $r2, $r1
857 + move.d $r1, [R_SDRAM_TIMING]
858 +
859 + ; Wait 200us
860 + move.d 10000, $r2
861 +1: bne 1b
862 + subq 1, $r2
863 +
864 + ; Issue initialization command sequence
865 + move.d _sdram_commands_start, $r2
866 + and.d 0x000fffff, $r2 ; Make sure commands are read from flash
867 + move.d _sdram_commands_end, $r3
868 + and.d 0x000fffff, $r3
869 +1: clear.d $r4
870 + move.b [$r2+], $r4
871 + lslq 9, $r4 ; Command starts at bit 9
872 + or.d $r1, $r4
873 + move.d $r4, [R_SDRAM_TIMING]
874 + nop ; Wait five nop cycles between each command
875 + nop
876 + nop
877 + nop
878 + nop
879 + cmp.d $r2, $r3
880 + bne 1b
881 + nop
882 + move.d $r5, [R_SDRAM_TIMING]
883 + subq 1, $r6
884 + bne _sdram_init
885 + nop
886 + ba _sdram_commands_end
887 + nop
888 +
889 +_sdram_commands_start:
890 + .byte 3 ; Precharge
891 + .byte 0 ; nop
892 + .byte 2 ; refresh
893 + .byte 0 ; nop
894 + .byte 2 ; refresh
895 + .byte 0 ; nop
896 + .byte 2 ; refresh
897 + .byte 0 ; nop
898 + .byte 2 ; refresh
899 + .byte 0 ; nop
900 + .byte 2 ; refresh
901 + .byte 0 ; nop
902 + .byte 2 ; refresh
903 + .byte 0 ; nop
904 + .byte 2 ; refresh
905 + .byte 0 ; nop
906 + .byte 2 ; refresh
907 + .byte 0 ; nop
908 + .byte 1 ; mrs
909 + .byte 0 ; nop
910 +_sdram_commands_end:
911 +#endif
912 +#endif
913 diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/dram_init_MCM.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/dram_init_MCM.S
914 --- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/dram_init_MCM.S 1970-01-01 01:00:00.000000000 +0100
915 +++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/dram_init_MCM.S 2007-05-28 20:03:13.000000000 +0200
916 @@ -0,0 +1,207 @@
917 +/* $Id: dram_init.S,v 1.5 2006/10/13 12:43:11 starvik Exp $
918 + *
919 + * DRAM/SDRAM initialization - alter with care
920 + * This file is intended to be included from other assembler files
921 + *
922 + * Note: This file may not modify r9 because r9 is used to carry
923 + * information from the decompresser to the kernel
924 + *
925 + * Copyright (C) 2000, 2001 Axis Communications AB
926 + *
927 + * Authors: Mikael Starvik (starvik@axis.com)
928 + *
929 + * $Log: dram_init.S,v $
930 + * Revision 1.5 2006/10/13 12:43:11 starvik
931 + * Merge of 2.6.18
932 + *
933 + * Revision 1.4 2003/09/22 09:21:59 starvik
934 + * Decompresser is linked to 0x407xxxxx and sdram commands are at 0x000xxxxx
935 + * so we need to mask off 12 bits.
936 + *
937 + * Revision 1.3 2003/03/31 09:38:37 starvik
938 + * Corrected calculation of end of sdram init commands
939 + *
940 + * Revision 1.2 2002/11/19 13:33:29 starvik
941 + * Changes from Linux 2.4
942 + *
943 + * Revision 1.13 2002/10/30 07:42:28 starvik
944 + * Always read SDRAM command sequence from flash
945 + *
946 + * Revision 1.12 2002/08/09 11:37:37 orjanf
947 + * Added double initialization work-around for Samsung SDRAMs.
948 + *
949 + * Revision 1.11 2002/06/04 11:43:21 starvik
950 + * Check if mrs_data is specified in kernelconfig (necessary for MCM)
951 + *
952 + * Revision 1.10 2001/10/04 12:00:21 martinnn
953 + * Added missing underscores.
954 + *
955 + * Revision 1.9 2001/10/01 14:47:35 bjornw
956 + * Added register prefixes and removed underscores
957 + *
958 + * Revision 1.8 2001/05/15 07:12:45 hp
959 + * Copy warning from head.S about r8 and r9
960 + *
961 + * Revision 1.7 2001/04/18 12:05:39 bjornw
962 + * Fixed comments, and explicitely include config.h to be sure its there
963 + *
964 + * Revision 1.6 2001/04/10 06:20:16 starvik
965 + * Delay should be 200us, not 200ns
966 + *
967 + * Revision 1.5 2001/04/09 06:01:13 starvik
968 + * Added support for 100 MHz SDRAMs
969 + *
970 + * Revision 1.4 2001/03/26 14:24:01 bjornw
971 + * Namechange of some config options
972 + *
973 + * Revision 1.3 2001/03/23 08:29:41 starvik
974 + * Corrected calculation of mrs_data
975 + *
976 + * Revision 1.2 2001/02/08 15:20:00 starvik
977 + * Corrected SDRAM initialization
978 + * Should now be included as inline
979 + *
980 + * Revision 1.1 2001/01/29 13:08:02 starvik
981 + * Initial version
982 + * This file should be included from all assembler files that needs to
983 + * initialize DRAM/SDRAM.
984 + *
985 + */
986 +
987 +/* Just to be certain the config file is included, we include it here
988 + * explicitely instead of depending on it being included in the file that
989 + * uses this code.
990 + */
991 +
992 +
993 + ;; WARNING! The registers r8 and r9 are used as parameters carrying
994 + ;; information from the decompressor (if the kernel was compressed).
995 + ;; They should not be used in the code below.
996 +
997 +#ifndef CONFIG_SVINTO_SIM
998 + move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
999 + move.d $r0, [R_WAITSTATES]
1000 +
1001 + move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
1002 + move.d $r0, [R_BUS_CONFIG]
1003 +
1004 +#ifndef CONFIG_ETRAX_SDRAM
1005 + move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
1006 + move.d $r0, [R_DRAM_CONFIG]
1007 +
1008 + move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
1009 + move.d $r0, [R_DRAM_TIMING]
1010 +#else
1011 + ;; Samsung SDRAMs seem to require to be initialized twice to work properly.
1012 + moveq 2, $r6
1013 +_sdram_init:
1014 +
1015 + ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
1016 +
1017 + ; Bank configuration
1018 + move.d 0x09603636, $r0
1019 + move.d $r0, [R_SDRAM_CONFIG]
1020 +
1021 + ; Calculate value of mrs_data
1022 + ; CAS latency = 2 && bus_width = 32 => 0x40
1023 + ; CAS latency = 3 && bus_width = 32 => 0x60
1024 + ; CAS latency = 2 && bus_width = 16 => 0x20
1025 + ; CAS latency = 3 && bus_width = 16 => 0x30
1026 +
1027 + ; Check if value is already supplied in kernel config
1028 + move.d 0x80608002, $r2
1029 + and.d 0x00ff0000, $r2
1030 + bne _set_timing
1031 + lsrq 16, $r2
1032 +
1033 + move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
1034 + move.d 0x80608002, $r1
1035 + move.d $r1, $r3
1036 + and.d 0x03, $r1 ; Get CAS latency
1037 + and.d 0x1000, $r3 ; 50 or 100 MHz?
1038 + beq _speed_50
1039 + nop
1040 +_speed_100:
1041 + cmp.d 0x00, $r1 ; CAS latency = 2?
1042 + beq _bw_check
1043 + nop
1044 + or.d 0x20, $r2 ; CAS latency = 3
1045 + ba _bw_check
1046 + nop
1047 +_speed_50:
1048 + cmp.d 0x01, $r1 ; CAS latency = 2?
1049 + beq _bw_check
1050 + nop
1051 + or.d 0x20, $r2 ; CAS latency = 3
1052 +_bw_check:
1053 + move.d 0x09603636, $r1
1054 + and.d 0x800000, $r1 ; DRAM width is bit 23
1055 + bne _set_timing
1056 + nop
1057 + lsrq 1, $r2 ; 16 bits. Shift down value.
1058 +
1059 + ; Set timing parameters. Starts master clock
1060 +_set_timing:
1061 + move.d 0x80608002, $r1
1062 + and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
1063 + or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
1064 + move.d $r1, $r5
1065 + or.d 0x0000c000, $r1 ; ref = disable
1066 + lslq 16, $r2 ; mrs data starts at bit 16
1067 + or.d $r2, $r1
1068 + move.d $r1, [R_SDRAM_TIMING]
1069 +
1070 + ; Wait 200us
1071 + move.d 10000, $r2
1072 +1: bne 1b
1073 + subq 1, $r2
1074 +
1075 + ; Issue initialization command sequence
1076 + move.d _sdram_commands_start, $r2
1077 + and.d 0x000fffff, $r2 ; Make sure commands are read from flash
1078 + move.d _sdram_commands_end, $r3
1079 + and.d 0x000fffff, $r3
1080 +1: clear.d $r4
1081 + move.b [$r2+], $r4
1082 + lslq 9, $r4 ; Command starts at bit 9
1083 + or.d $r1, $r4
1084 + move.d $r4, [R_SDRAM_TIMING]
1085 + nop ; Wait five nop cycles between each command
1086 + nop
1087 + nop
1088 + nop
1089 + nop
1090 + cmp.d $r2, $r3
1091 + bne 1b
1092 + nop
1093 + move.d $r5, [R_SDRAM_TIMING]
1094 + subq 1, $r6
1095 + bne _sdram_init
1096 + nop
1097 + ba _sdram_commands_end
1098 + nop
1099 +
1100 +_sdram_commands_start:
1101 + .byte 3 ; Precharge
1102 + .byte 0 ; nop
1103 + .byte 2 ; refresh
1104 + .byte 0 ; nop
1105 + .byte 2 ; refresh
1106 + .byte 0 ; nop
1107 + .byte 2 ; refresh
1108 + .byte 0 ; nop
1109 + .byte 2 ; refresh
1110 + .byte 0 ; nop
1111 + .byte 2 ; refresh
1112 + .byte 0 ; nop
1113 + .byte 2 ; refresh
1114 + .byte 0 ; nop
1115 + .byte 2 ; refresh
1116 + .byte 0 ; nop
1117 + .byte 2 ; refresh
1118 + .byte 0 ; nop
1119 + .byte 1 ; mrs
1120 + .byte 0 ; nop
1121 +_sdram_commands_end:
1122 +#endif
1123 +#endif
1124 diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/head_416.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/head_416.S
1125 --- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/head_416.S 1970-01-01 01:00:00.000000000 +0100
1126 +++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/head_416.S 2007-05-28 17:16:28.000000000 +0200
1127 @@ -0,0 +1,126 @@
1128 +/*
1129 + * arch/cris/boot/compressed/head.S
1130 + *
1131 + * Copyright (C) 1999, 2001 Axis Communications AB
1132 + *
1133 + * Code that sets up the DRAM registers, calls the
1134 + * decompressor to unpack the piggybacked kernel, and jumps.
1135 + *
1136 + */
1137 +
1138 +#define ASSEMBLER_MACROS_ONLY
1139 +#include <asm/arch/sv_addr_ag.h>
1140 +
1141 +#define RAM_INIT_MAGIC 0x56902387
1142 +#define COMMAND_LINE_MAGIC 0x87109563
1143 +
1144 + ;; Exported symbols
1145 +
1146 + .globl _input_data
1147 +
1148 +
1149 + .text
1150 +
1151 + nop
1152 + di
1153 +
1154 +;; We need to initialze DRAM registers before we start using the DRAM
1155 +
1156 + cmp.d RAM_INIT_MAGIC, r8 ; Already initialized?
1157 + beq dram_init_finished
1158 + nop
1159 +
1160 +#include "dram_init_416.S"
1161 +
1162 +dram_init_finished:
1163 +
1164 + ;; Initiate the PA and PB ports
1165 +
1166 + move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, r0
1167 + move.b r0, [R_PORT_PA_DATA]
1168 +
1169 + move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, r0
1170 + move.b r0, [R_PORT_PA_DIR]
1171 +
1172 + move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, r0
1173 + move.b r0, [R_PORT_PB_DATA]
1174 +
1175 + move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, r0
1176 + move.b r0, [R_PORT_PB_DIR]
1177 +
1178 + ;; Setup the stack to a suitably high address.
1179 + ;; We assume 8 MB is the minimum DRAM in an eLinux
1180 + ;; product and put the sp at the top for now.
1181 +
1182 + move.d 0x40800000, sp
1183 +
1184 + ;; Figure out where the compressed piggyback image is
1185 + ;; in the flash (since we wont try to copy it to DRAM
1186 + ;; before unpacking). It is at _edata, but in flash.
1187 + ;; Use (_edata - basse) as offset to the current PC.
1188 +
1189 +basse: move.d pc, r5
1190 + and.d 0x7fffffff, r5 ; strip any non-cache bit
1191 + subq 2, r5 ; compensate for the move.d pc instr
1192 + move.d r5, r0 ; save for later - flash address of 'basse'
1193 + add.d _edata, r5
1194 + sub.d basse, r5 ; r5 = flash address of '_edata'
1195 +
1196 + ;; Copy text+data to DRAM
1197 +
1198 + move.d basse, r1 ; destination
1199 + move.d _edata, r2 ; end destination
1200 +1: move.w [r0+], r3
1201 + move.w r3, [r1+]
1202 + cmp.d r2, r1
1203 + bcs 1b
1204 + nop
1205 +
1206 + move.d r5, [_input_data] ; for the decompressor
1207 +
1208 +
1209 + ;; Clear the decompressors BSS (between _edata and _end)
1210 +
1211 + moveq 0, r0
1212 + move.d _edata, r1
1213 + move.d _end, r2
1214 +1: move.w r0, [r1+]
1215 + cmp.d r2, r1
1216 + bcs 1b
1217 + nop
1218 +
1219 + ;; Save command line magic and address.
1220 + move.d _cmd_line_magic, $r12
1221 + move.d $r10, [$r12]
1222 + move.d _cmd_line_addr, $r12
1223 + move.d $r11, [$r12]
1224 +
1225 + ;; Do the decompression and save compressed size in _inptr
1226 +
1227 + jsr _decompress_kernel
1228 +
1229 + ;; Put start address of root partition in r9 so the kernel can use it
1230 + ;; when mounting from flash
1231 +
1232 + move.d [_input_data], r9 ; flash address of compressed kernel
1233 + add.d [_inptr], r9 ; size of compressed kernel
1234 +
1235 + ;; Restore command line magic and address.
1236 + move.d _cmd_line_magic, $r10
1237 + move.d [$r10], $r10
1238 + move.d _cmd_line_addr, $r11
1239 + move.d [$r11], $r11
1240 +
1241 + ;; Enter the decompressed kernel
1242 + move.d RAM_INIT_MAGIC, r8 ; Tell kernel that DRAM is initialized
1243 + jump 0x40004000 ; kernel is linked to this address
1244 +
1245 + .data
1246 +
1247 +_input_data:
1248 + .dword 0 ; used by the decompressor
1249 +_cmd_line_magic:
1250 + .dword 0
1251 +_cmd_line_addr:
1252 + .dword 0
1253 +#include "hw_settings_416.S"
1254 diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/head_816.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/head_816.S
1255 --- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/head_816.S 1970-01-01 01:00:00.000000000 +0100
1256 +++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/head_816.S 2007-05-28 17:16:58.000000000 +0200
1257 @@ -0,0 +1,126 @@
1258 +/*
1259 + * arch/cris/boot/compressed/head.S
1260 + *
1261 + * Copyright (C) 1999, 2001 Axis Communications AB
1262 + *
1263 + * Code that sets up the DRAM registers, calls the
1264 + * decompressor to unpack the piggybacked kernel, and jumps.
1265 + *
1266 + */
1267 +
1268 +#define ASSEMBLER_MACROS_ONLY
1269 +#include <asm/arch/sv_addr_ag.h>
1270 +
1271 +#define RAM_INIT_MAGIC 0x56902387
1272 +#define COMMAND_LINE_MAGIC 0x87109563
1273 +
1274 + ;; Exported symbols
1275 +
1276 + .globl _input_data
1277 +
1278 +
1279 + .text
1280 +
1281 + nop
1282 + di
1283 +
1284 +;; We need to initialze DRAM registers before we start using the DRAM
1285 +
1286 + cmp.d RAM_INIT_MAGIC, r8 ; Already initialized?
1287 + beq dram_init_finished
1288 + nop
1289 +
1290 +#include "dram_init_816.S"
1291 +
1292 +dram_init_finished:
1293 +
1294 + ;; Initiate the PA and PB ports
1295 +
1296 + move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, r0
1297 + move.b r0, [R_PORT_PA_DATA]
1298 +
1299 + move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, r0
1300 + move.b r0, [R_PORT_PA_DIR]
1301 +
1302 + move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, r0
1303 + move.b r0, [R_PORT_PB_DATA]
1304 +
1305 + move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, r0
1306 + move.b r0, [R_PORT_PB_DIR]
1307 +
1308 + ;; Setup the stack to a suitably high address.
1309 + ;; We assume 8 MB is the minimum DRAM in an eLinux
1310 + ;; product and put the sp at the top for now.
1311 +
1312 + move.d 0x40800000, sp
1313 +
1314 + ;; Figure out where the compressed piggyback image is
1315 + ;; in the flash (since we wont try to copy it to DRAM
1316 + ;; before unpacking). It is at _edata, but in flash.
1317 + ;; Use (_edata - basse) as offset to the current PC.
1318 +
1319 +basse: move.d pc, r5
1320 + and.d 0x7fffffff, r5 ; strip any non-cache bit
1321 + subq 2, r5 ; compensate for the move.d pc instr
1322 + move.d r5, r0 ; save for later - flash address of 'basse'
1323 + add.d _edata, r5
1324 + sub.d basse, r5 ; r5 = flash address of '_edata'
1325 +
1326 + ;; Copy text+data to DRAM
1327 +
1328 + move.d basse, r1 ; destination
1329 + move.d _edata, r2 ; end destination
1330 +1: move.w [r0+], r3
1331 + move.w r3, [r1+]
1332 + cmp.d r2, r1
1333 + bcs 1b
1334 + nop
1335 +
1336 + move.d r5, [_input_data] ; for the decompressor
1337 +
1338 +
1339 + ;; Clear the decompressors BSS (between _edata and _end)
1340 +
1341 + moveq 0, r0
1342 + move.d _edata, r1
1343 + move.d _end, r2
1344 +1: move.w r0, [r1+]
1345 + cmp.d r2, r1
1346 + bcs 1b
1347 + nop
1348 +
1349 + ;; Save command line magic and address.
1350 + move.d _cmd_line_magic, $r12
1351 + move.d $r10, [$r12]
1352 + move.d _cmd_line_addr, $r12
1353 + move.d $r11, [$r12]
1354 +
1355 + ;; Do the decompression and save compressed size in _inptr
1356 +
1357 + jsr _decompress_kernel
1358 +
1359 + ;; Put start address of root partition in r9 so the kernel can use it
1360 + ;; when mounting from flash
1361 +
1362 + move.d [_input_data], r9 ; flash address of compressed kernel
1363 + add.d [_inptr], r9 ; size of compressed kernel
1364 +
1365 + ;; Restore command line magic and address.
1366 + move.d _cmd_line_magic, $r10
1367 + move.d [$r10], $r10
1368 + move.d _cmd_line_addr, $r11
1369 + move.d [$r11], $r11
1370 +
1371 + ;; Enter the decompressed kernel
1372 + move.d RAM_INIT_MAGIC, r8 ; Tell kernel that DRAM is initialized
1373 + jump 0x40004000 ; kernel is linked to this address
1374 +
1375 + .data
1376 +
1377 +_input_data:
1378 + .dword 0 ; used by the decompressor
1379 +_cmd_line_magic:
1380 + .dword 0
1381 +_cmd_line_addr:
1382 + .dword 0
1383 +#include "hw_settings_816.S"
1384 diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/head_832.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/head_832.S
1385 --- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/head_832.S 1970-01-01 01:00:00.000000000 +0100
1386 +++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/head_832.S 2007-05-28 17:17:12.000000000 +0200
1387 @@ -0,0 +1,126 @@
1388 +/*
1389 + * arch/cris/boot/compressed/head.S
1390 + *
1391 + * Copyright (C) 1999, 2001 Axis Communications AB
1392 + *
1393 + * Code that sets up the DRAM registers, calls the
1394 + * decompressor to unpack the piggybacked kernel, and jumps.
1395 + *
1396 + */
1397 +
1398 +#define ASSEMBLER_MACROS_ONLY
1399 +#include <asm/arch/sv_addr_ag.h>
1400 +
1401 +#define RAM_INIT_MAGIC 0x56902387
1402 +#define COMMAND_LINE_MAGIC 0x87109563
1403 +
1404 + ;; Exported symbols
1405 +
1406 + .globl _input_data
1407 +
1408 +
1409 + .text
1410 +
1411 + nop
1412 + di
1413 +
1414 +;; We need to initialze DRAM registers before we start using the DRAM
1415 +
1416 + cmp.d RAM_INIT_MAGIC, r8 ; Already initialized?
1417 + beq dram_init_finished
1418 + nop
1419 +
1420 +#include "dram_init_832.S"
1421 +
1422 +dram_init_finished:
1423 +
1424 + ;; Initiate the PA and PB ports
1425 +
1426 + move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, r0
1427 + move.b r0, [R_PORT_PA_DATA]
1428 +
1429 + move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, r0
1430 + move.b r0, [R_PORT_PA_DIR]
1431 +
1432 + move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, r0
1433 + move.b r0, [R_PORT_PB_DATA]
1434 +
1435 + move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, r0
1436 + move.b r0, [R_PORT_PB_DIR]
1437 +
1438 + ;; Setup the stack to a suitably high address.
1439 + ;; We assume 8 MB is the minimum DRAM in an eLinux
1440 + ;; product and put the sp at the top for now.
1441 +
1442 + move.d 0x40800000, sp
1443 +
1444 + ;; Figure out where the compressed piggyback image is
1445 + ;; in the flash (since we wont try to copy it to DRAM
1446 + ;; before unpacking). It is at _edata, but in flash.
1447 + ;; Use (_edata - basse) as offset to the current PC.
1448 +
1449 +basse: move.d pc, r5
1450 + and.d 0x7fffffff, r5 ; strip any non-cache bit
1451 + subq 2, r5 ; compensate for the move.d pc instr
1452 + move.d r5, r0 ; save for later - flash address of 'basse'
1453 + add.d _edata, r5
1454 + sub.d basse, r5 ; r5 = flash address of '_edata'
1455 +
1456 + ;; Copy text+data to DRAM
1457 +
1458 + move.d basse, r1 ; destination
1459 + move.d _edata, r2 ; end destination
1460 +1: move.w [r0+], r3
1461 + move.w r3, [r1+]
1462 + cmp.d r2, r1
1463 + bcs 1b
1464 + nop
1465 +
1466 + move.d r5, [_input_data] ; for the decompressor
1467 +
1468 +
1469 + ;; Clear the decompressors BSS (between _edata and _end)
1470 +
1471 + moveq 0, r0
1472 + move.d _edata, r1
1473 + move.d _end, r2
1474 +1: move.w r0, [r1+]
1475 + cmp.d r2, r1
1476 + bcs 1b
1477 + nop
1478 +
1479 + ;; Save command line magic and address.
1480 + move.d _cmd_line_magic, $r12
1481 + move.d $r10, [$r12]
1482 + move.d _cmd_line_addr, $r12
1483 + move.d $r11, [$r12]
1484 +
1485 + ;; Do the decompression and save compressed size in _inptr
1486 +
1487 + jsr _decompress_kernel
1488 +
1489 + ;; Put start address of root partition in r9 so the kernel can use it
1490 + ;; when mounting from flash
1491 +
1492 + move.d [_input_data], r9 ; flash address of compressed kernel
1493 + add.d [_inptr], r9 ; size of compressed kernel
1494 +
1495 + ;; Restore command line magic and address.
1496 + move.d _cmd_line_magic, $r10
1497 + move.d [$r10], $r10
1498 + move.d _cmd_line_addr, $r11
1499 + move.d [$r11], $r11
1500 +
1501 + ;; Enter the decompressed kernel
1502 + move.d RAM_INIT_MAGIC, r8 ; Tell kernel that DRAM is initialized
1503 + jump 0x40004000 ; kernel is linked to this address
1504 +
1505 + .data
1506 +
1507 +_input_data:
1508 + .dword 0 ; used by the decompressor
1509 +_cmd_line_magic:
1510 + .dword 0
1511 +_cmd_line_addr:
1512 + .dword 0
1513 +#include "hw_settings_832.S"
1514 diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/head_MCM.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/head_MCM.S
1515 --- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/head_MCM.S 1970-01-01 01:00:00.000000000 +0100
1516 +++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/head_MCM.S 2007-05-28 17:17:51.000000000 +0200
1517 @@ -0,0 +1,126 @@
1518 +/*
1519 + * arch/cris/boot/compressed/head.S
1520 + *
1521 + * Copyright (C) 1999, 2001 Axis Communications AB
1522 + *
1523 + * Code that sets up the DRAM registers, calls the
1524 + * decompressor to unpack the piggybacked kernel, and jumps.
1525 + *
1526 + */
1527 +
1528 +#define ASSEMBLER_MACROS_ONLY
1529 +#include <asm/arch/sv_addr_ag.h>
1530 +
1531 +#define RAM_INIT_MAGIC 0x56902387
1532 +#define COMMAND_LINE_MAGIC 0x87109563
1533 +
1534 + ;; Exported symbols
1535 +
1536 + .globl _input_data
1537 +
1538 +
1539 + .text
1540 +
1541 + nop
1542 + di
1543 +
1544 +;; We need to initialze DRAM registers before we start using the DRAM
1545 +
1546 + cmp.d RAM_INIT_MAGIC, r8 ; Already initialized?
1547 + beq dram_init_finished
1548 + nop
1549 +
1550 +#include "dram_init_MCM.S"
1551 +
1552 +dram_init_finished:
1553 +
1554 + ;; Initiate the PA and PB ports
1555 +
1556 + move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, r0
1557 + move.b r0, [R_PORT_PA_DATA]
1558 +
1559 + move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, r0
1560 + move.b r0, [R_PORT_PA_DIR]
1561 +
1562 + move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, r0
1563 + move.b r0, [R_PORT_PB_DATA]
1564 +
1565 + move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, r0
1566 + move.b r0, [R_PORT_PB_DIR]
1567 +
1568 + ;; Setup the stack to a suitably high address.
1569 + ;; We assume 8 MB is the minimum DRAM in an eLinux
1570 + ;; product and put the sp at the top for now.
1571 +
1572 + move.d 0x40800000, sp
1573 +
1574 + ;; Figure out where the compressed piggyback image is
1575 + ;; in the flash (since we wont try to copy it to DRAM
1576 + ;; before unpacking). It is at _edata, but in flash.
1577 + ;; Use (_edata - basse) as offset to the current PC.
1578 +
1579 +basse: move.d pc, r5
1580 + and.d 0x7fffffff, r5 ; strip any non-cache bit
1581 + subq 2, r5 ; compensate for the move.d pc instr
1582 + move.d r5, r0 ; save for later - flash address of 'basse'
1583 + add.d _edata, r5
1584 + sub.d basse, r5 ; r5 = flash address of '_edata'
1585 +
1586 + ;; Copy text+data to DRAM
1587 +
1588 + move.d basse, r1 ; destination
1589 + move.d _edata, r2 ; end destination
1590 +1: move.w [r0+], r3
1591 + move.w r3, [r1+]
1592 + cmp.d r2, r1
1593 + bcs 1b
1594 + nop
1595 +
1596 + move.d r5, [_input_data] ; for the decompressor
1597 +
1598 +
1599 + ;; Clear the decompressors BSS (between _edata and _end)
1600 +
1601 + moveq 0, r0
1602 + move.d _edata, r1
1603 + move.d _end, r2
1604 +1: move.w r0, [r1+]
1605 + cmp.d r2, r1
1606 + bcs 1b
1607 + nop
1608 +
1609 + ;; Save command line magic and address.
1610 + move.d _cmd_line_magic, $r12
1611 + move.d $r10, [$r12]
1612 + move.d _cmd_line_addr, $r12
1613 + move.d $r11, [$r12]
1614 +
1615 + ;; Do the decompression and save compressed size in _inptr
1616 +
1617 + jsr _decompress_kernel
1618 +
1619 + ;; Put start address of root partition in r9 so the kernel can use it
1620 + ;; when mounting from flash
1621 +
1622 + move.d [_input_data], r9 ; flash address of compressed kernel
1623 + add.d [_inptr], r9 ; size of compressed kernel
1624 +
1625 + ;; Restore command line magic and address.
1626 + move.d _cmd_line_magic, $r10
1627 + move.d [$r10], $r10
1628 + move.d _cmd_line_addr, $r11
1629 + move.d [$r11], $r11
1630 +
1631 + ;; Enter the decompressed kernel
1632 + move.d RAM_INIT_MAGIC, r8 ; Tell kernel that DRAM is initialized
1633 + jump 0x40004000 ; kernel is linked to this address
1634 +
1635 + .data
1636 +
1637 +_input_data:
1638 + .dword 0 ; used by the decompressor
1639 +_cmd_line_magic:
1640 + .dword 0
1641 +_cmd_line_addr:
1642 + .dword 0
1643 +#include "hw_settings_MCM.S"
1644 diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/hw_settings.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/hw_settings.S
1645 --- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/hw_settings.S 1970-01-01 01:00:00.000000000 +0100
1646 +++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/hw_settings.S 2007-05-28 17:14:14.000000000 +0200
1647 @@ -0,0 +1,62 @@
1648 +/*
1649 + * $Id: hw_settings.S,v 1.1 2001/12/17 13:59:27 bjornw Exp $
1650 + *
1651 + * This table is used by some tools to extract hardware parameters.
1652 + * The table should be included in the kernel and the decompressor.
1653 + * Don't forget to update the tools if you change this table.
1654 + *
1655 + * Copyright (C) 2001 Axis Communications AB
1656 + *
1657 + * Authors: Mikael Starvik (starvik@axis.com)
1658 + */
1659 +
1660 +#define PA_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PA_DIR << 8) | \
1661 + (CONFIG_ETRAX_DEF_R_PORT_PA_DATA))
1662 +#define PB_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG << 16) | \
1663 + (CONFIG_ETRAX_DEF_R_PORT_PB_DIR << 8) | \
1664 + (CONFIG_ETRAX_DEF_R_PORT_PB_DATA))
1665 +
1666 + .ascii "HW_PARAM_MAGIC" ; Magic number
1667 + .dword 0xc0004000 ; Kernel start address
1668 +
1669 + ; Debug port
1670 +#ifdef CONFIG_ETRAX_DEBUG_PORT0
1671 + .dword 0
1672 +#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
1673 + .dword 1
1674 +#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
1675 + .dword 2
1676 +#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
1677 + .dword 3
1678 +#else
1679 + .dword 4 ; No debug
1680 +#endif
1681 +
1682 + ; SDRAM or EDO DRAM?
1683 +#ifdef CONFIG_ETRAX_SDRAM
1684 + .dword 1
1685 +#else
1686 + .dword 0
1687 +#endif
1688 +
1689 + ; Register values
1690 + .dword R_WAITSTATES
1691 + .dword CONFIG_ETRAX_DEF_R_WAITSTATES
1692 + .dword R_BUS_CONFIG
1693 + .dword CONFIG_ETRAX_DEF_R_BUS_CONFIG
1694 +#ifdef CONFIG_ETRAX_SDRAM
1695 + .dword R_SDRAM_CONFIG
1696 + .dword CONFIG_ETRAX_DEF_R_SDRAM_CONFIG
1697 + .dword R_SDRAM_TIMING
1698 + .dword CONFIG_ETRAX_DEF_R_SDRAM_TIMING
1699 +#else
1700 + .dword R_DRAM_CONFIG
1701 + .dword CONFIG_ETRAX_DEF_R_DRAM_CONFIG
1702 + .dword R_DRAM_TIMING
1703 + .dword CONFIG_ETRAX_DEF_R_DRAM_TIMING
1704 +#endif
1705 + .dword R_PORT_PA_SET
1706 + .dword PA_SET_VALUE
1707 + .dword R_PORT_PB_SET
1708 + .dword PB_SET_VALUE
1709 + .dword 0 ; No more register values
1710 diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/hw_settings_416.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/hw_settings_416.S
1711 --- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/hw_settings_416.S 1970-01-01 01:00:00.000000000 +0100
1712 +++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/hw_settings_416.S 2007-05-28 20:12:02.000000000 +0200
1713 @@ -0,0 +1,62 @@
1714 +/*
1715 + * $Id: hw_settings.S,v 1.1 2001/12/17 13:59:27 bjornw Exp $
1716 + *
1717 + * This table is used by some tools to extract hardware parameters.
1718 + * The table should be included in the kernel and the decompressor.
1719 + * Don't forget to update the tools if you change this table.
1720 + *
1721 + * Copyright (C) 2001 Axis Communications AB
1722 + *
1723 + * Authors: Mikael Starvik (starvik@axis.com)
1724 + */
1725 +
1726 +#define PA_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PA_DIR << 8) | \
1727 + (CONFIG_ETRAX_DEF_R_PORT_PA_DATA))
1728 +#define PB_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG << 16) | \
1729 + (CONFIG_ETRAX_DEF_R_PORT_PB_DIR << 8) | \
1730 + (CONFIG_ETRAX_DEF_R_PORT_PB_DATA))
1731 +
1732 + .ascii "HW_PARAM_MAGIC" ; Magic number
1733 + .dword 0xc0004000 ; Kernel start address
1734 +
1735 + ; Debug port
1736 +#ifdef CONFIG_ETRAX_DEBUG_PORT0
1737 + .dword 0
1738 +#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
1739 + .dword 1
1740 +#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
1741 + .dword 2
1742 +#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
1743 + .dword 3
1744 +#else
1745 + .dword 4 ; No debug
1746 +#endif
1747 +
1748 + ; SDRAM or EDO DRAM?
1749 +#ifdef CONFIG_ETRAX_SDRAM
1750 + .dword 1
1751 +#else
1752 + .dword 0
1753 +#endif
1754 +
1755 + ; Register values
1756 + .dword R_WAITSTATES
1757 + .dword CONFIG_ETRAX_DEF_R_WAITSTATES
1758 + .dword R_BUS_CONFIG
1759 + .dword CONFIG_ETRAX_DEF_R_BUS_CONFIG
1760 +#ifdef CONFIG_ETRAX_SDRAM
1761 + .dword R_SDRAM_CONFIG
1762 + .dword 0x09603636
1763 + .dword R_SDRAM_TIMING
1764 + .dword 0x80008002
1765 +#else
1766 + .dword R_DRAM_CONFIG
1767 + .dword CONFIG_ETRAX_DEF_R_DRAM_CONFIG
1768 + .dword R_DRAM_TIMING
1769 + .dword CONFIG_ETRAX_DEF_R_DRAM_TIMING
1770 +#endif
1771 + .dword R_PORT_PA_SET
1772 + .dword PA_SET_VALUE
1773 + .dword R_PORT_PB_SET
1774 + .dword PB_SET_VALUE
1775 + .dword 0 ; No more register values
1776 diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/hw_settings_816.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/hw_settings_816.S
1777 --- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/hw_settings_816.S 1970-01-01 01:00:00.000000000 +0100
1778 +++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/hw_settings_816.S 2007-05-28 20:12:29.000000000 +0200
1779 @@ -0,0 +1,62 @@
1780 +/*
1781 + * $Id: hw_settings.S,v 1.1 2001/12/17 13:59:27 bjornw Exp $
1782 + *
1783 + * This table is used by some tools to extract hardware parameters.
1784 + * The table should be included in the kernel and the decompressor.
1785 + * Don't forget to update the tools if you change this table.
1786 + *
1787 + * Copyright (C) 2001 Axis Communications AB
1788 + *
1789 + * Authors: Mikael Starvik (starvik@axis.com)
1790 + */
1791 +
1792 +#define PA_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PA_DIR << 8) | \
1793 + (CONFIG_ETRAX_DEF_R_PORT_PA_DATA))
1794 +#define PB_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG << 16) | \
1795 + (CONFIG_ETRAX_DEF_R_PORT_PB_DIR << 8) | \
1796 + (CONFIG_ETRAX_DEF_R_PORT_PB_DATA))
1797 +
1798 + .ascii "HW_PARAM_MAGIC" ; Magic number
1799 + .dword 0xc0004000 ; Kernel start address
1800 +
1801 + ; Debug port
1802 +#ifdef CONFIG_ETRAX_DEBUG_PORT0
1803 + .dword 0
1804 +#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
1805 + .dword 1
1806 +#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
1807 + .dword 2
1808 +#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
1809 + .dword 3
1810 +#else
1811 + .dword 4 ; No debug
1812 +#endif
1813 +
1814 + ; SDRAM or EDO DRAM?
1815 +#ifdef CONFIG_ETRAX_SDRAM
1816 + .dword 1
1817 +#else
1818 + .dword 0
1819 +#endif
1820 +
1821 + ; Register values
1822 + .dword R_WAITSTATES
1823 + .dword CONFIG_ETRAX_DEF_R_WAITSTATES
1824 + .dword R_BUS_CONFIG
1825 + .dword CONFIG_ETRAX_DEF_R_BUS_CONFIG
1826 +#ifdef CONFIG_ETRAX_SDRAM
1827 + .dword R_SDRAM_CONFIG
1828 + .dword 0x09603636
1829 + .dword R_SDRAM_TIMING
1830 + .dword 0x80008002
1831 +#else
1832 + .dword R_DRAM_CONFIG
1833 + .dword CONFIG_ETRAX_DEF_R_DRAM_CONFIG
1834 + .dword R_DRAM_TIMING
1835 + .dword CONFIG_ETRAX_DEF_R_DRAM_TIMING
1836 +#endif
1837 + .dword R_PORT_PA_SET
1838 + .dword PA_SET_VALUE
1839 + .dword R_PORT_PB_SET
1840 + .dword PB_SET_VALUE
1841 + .dword 0 ; No more register values
1842 diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/hw_settings_832.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/hw_settings_832.S
1843 --- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/hw_settings_832.S 1970-01-01 01:00:00.000000000 +0100
1844 +++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/hw_settings_832.S 2007-05-28 20:12:55.000000000 +0200
1845 @@ -0,0 +1,62 @@
1846 +/*
1847 + * $Id: hw_settings.S,v 1.1 2001/12/17 13:59:27 bjornw Exp $
1848 + *
1849 + * This table is used by some tools to extract hardware parameters.
1850 + * The table should be included in the kernel and the decompressor.
1851 + * Don't forget to update the tools if you change this table.
1852 + *
1853 + * Copyright (C) 2001 Axis Communications AB
1854 + *
1855 + * Authors: Mikael Starvik (starvik@axis.com)
1856 + */
1857 +
1858 +#define PA_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PA_DIR << 8) | \
1859 + (CONFIG_ETRAX_DEF_R_PORT_PA_DATA))
1860 +#define PB_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG << 16) | \
1861 + (CONFIG_ETRAX_DEF_R_PORT_PB_DIR << 8) | \
1862 + (CONFIG_ETRAX_DEF_R_PORT_PB_DATA))
1863 +
1864 + .ascii "HW_PARAM_MAGIC" ; Magic number
1865 + .dword 0xc0004000 ; Kernel start address
1866 +
1867 + ; Debug port
1868 +#ifdef CONFIG_ETRAX_DEBUG_PORT0
1869 + .dword 0
1870 +#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
1871 + .dword 1
1872 +#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
1873 + .dword 2
1874 +#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
1875 + .dword 3
1876 +#else
1877 + .dword 4 ; No debug
1878 +#endif
1879 +
1880 + ; SDRAM or EDO DRAM?
1881 +#ifdef CONFIG_ETRAX_SDRAM
1882 + .dword 1
1883 +#else
1884 + .dword 0
1885 +#endif
1886 +
1887 + ; Register values
1888 + .dword R_WAITSTATES
1889 + .dword CONFIG_ETRAX_DEF_R_WAITSTATES
1890 + .dword R_BUS_CONFIG
1891 + .dword CONFIG_ETRAX_DEF_R_BUS_CONFIG
1892 +#ifdef CONFIG_ETRAX_SDRAM
1893 + .dword R_SDRAM_CONFIG
1894 + .dword CONFIG_ETRAX_DEF_R_SDRAM_CONFIG
1895 + .dword R_SDRAM_TIMING
1896 + .dword CONFIG_ETRAX_DEF_R_SDRAM_TIMING
1897 +#else
1898 + .dword R_DRAM_CONFIG
1899 + .dword 0x09603737
1900 + .dword R_DRAM_TIMING
1901 + .dword 0x80008002
1902 +#endif
1903 + .dword R_PORT_PA_SET
1904 + .dword PA_SET_VALUE
1905 + .dword R_PORT_PB_SET
1906 + .dword PB_SET_VALUE
1907 + .dword 0 ; No more register values
1908 diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/hw_settings_MCM.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/hw_settings_MCM.S
1909 --- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/hw_settings_MCM.S 1970-01-01 01:00:00.000000000 +0100
1910 +++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/hw_settings_MCM.S 2007-05-28 20:11:31.000000000 +0200
1911 @@ -0,0 +1,62 @@
1912 +/*
1913 + * $Id: hw_settings.S,v 1.1 2001/12/17 13:59:27 bjornw Exp $
1914 + *
1915 + * This table is used by some tools to extract hardware parameters.
1916 + * The table should be included in the kernel and the decompressor.
1917 + * Don't forget to update the tools if you change this table.
1918 + *
1919 + * Copyright (C) 2001 Axis Communications AB
1920 + *
1921 + * Authors: Mikael Starvik (starvik@axis.com)
1922 + */
1923 +
1924 +#define PA_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PA_DIR << 8) | \
1925 + (CONFIG_ETRAX_DEF_R_PORT_PA_DATA))
1926 +#define PB_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG << 16) | \
1927 + (CONFIG_ETRAX_DEF_R_PORT_PB_DIR << 8) | \
1928 + (CONFIG_ETRAX_DEF_R_PORT_PB_DATA))
1929 +
1930 + .ascii "HW_PARAM_MAGIC" ; Magic number
1931 + .dword 0xc0004000 ; Kernel start address
1932 +
1933 + ; Debug port
1934 +#ifdef CONFIG_ETRAX_DEBUG_PORT0
1935 + .dword 0
1936 +#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
1937 + .dword 1
1938 +#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
1939 + .dword 2
1940 +#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
1941 + .dword 3
1942 +#else
1943 + .dword 4 ; No debug
1944 +#endif
1945 +
1946 + ; SDRAM or EDO DRAM?
1947 +#ifdef CONFIG_ETRAX_SDRAM
1948 + .dword 1
1949 +#else
1950 + .dword 0
1951 +#endif
1952 +
1953 + ; Register values
1954 + .dword R_WAITSTATES
1955 + .dword CONFIG_ETRAX_DEF_R_WAITSTATES
1956 + .dword R_BUS_CONFIG
1957 + .dword CONFIG_ETRAX_DEF_R_BUS_CONFIG
1958 +#ifdef CONFIG_ETRAX_SDRAM
1959 + .dword R_SDRAM_CONFIG
1960 + .dword 0x09603636
1961 + .dword R_SDRAM_TIMING
1962 + .dword 0x80608002
1963 +#else
1964 + .dword R_DRAM_CONFIG
1965 + .dword CONFIG_ETRAX_DEF_R_DRAM_CONFIG
1966 + .dword R_DRAM_TIMING
1967 + .dword CONFIG_ETRAX_DEF_R_DRAM_TIMING
1968 +#endif
1969 + .dword R_PORT_PA_SET
1970 + .dword PA_SET_VALUE
1971 + .dword R_PORT_PB_SET
1972 + .dword PB_SET_VALUE
1973 + .dword 0 ; No more register values
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